Index: trunk/firmware/App/CubeMX/Secure_nsclib/secure_nsc.h
===================================================================
--- trunk/firmware/App/CubeMX/Secure_nsclib/secure_nsc.h	(revision 22)
+++ trunk/firmware/App/CubeMX/Secure_nsclib/secure_nsc.h	(revision 22)
@@ -0,0 +1,45 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    Secure_nsclib/secure_nsc.h
+  * @author  MCD Application Team
+  * @brief   Header for secure non-secure callable APIs list
+  ******************************************************************************
+    * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* USER CODE BEGIN Non_Secure_CallLib_h */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef SECURE_NSC_H
+#define SECURE_NSC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/* Exported types ------------------------------------------------------------*/
+/**
+  * @brief  non-secure callback ID enumeration definition
+  */
+typedef enum
+{
+SECURE_FAULT_CB_ID     = 0x00U, /*!< System secure fault callback ID */
+  IAC_ERROR_CB_ID       = 0x01U  /*!< Illegal access secure error callback ID */
+} SECURE_CallbackIDTypeDef;
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func);
+
+#endif /* SECURE_NSC_H */
+/* USER CODE END Non_Secure_CallLib_h */
+
Index: trunk/firmware/App/SES/Output/Production/Exe/blto_App.htm
===================================================================
--- trunk/firmware/App/SES/Output/Production/Exe/blto_App.htm	(revision 22)
+++ trunk/firmware/App/SES/Output/Production/Exe/blto_App.htm	(revision 22)
@@ -0,0 +1,18847 @@
+<!DOCTYPE html>
+<html>
+<style>
+body { font-family: "Tahoma", "Open Sans", "Helvetica Neue", Helvetica, Arial, sans-serif; font-size: 0.9rem; line-height: 1.5; min-width: 400px;             padding-left: 20px; padding-left: 80px; padding-right: 5px; }
+html { margin: 0; padding: 0; }
+pre { border: 1px solid #d0d4d9; background: #f6f9fc; padding: 10px 10px; border-radius: 3px; font-size: 0.9rem; font-family: Consolas, Courier, monospace; }
+th { background-color: #f6f9fc; }
+table, th, td { border: 1px solid #d0d4d9; border-collapse: collapse; padding: 4px 4px; }
+h1 { color: #0B5B9A; margin-top: 50px; margin-left: -50pt; margin-bottom: 20px; text-align: left; font-size: 1.5em; border-bottom: 1px solid #0B5B9A; }
+h2 { color: #0B5B9A; margin-top: 30px; margin-left: -50pt;                      text-align: left; font-size: 1.2em; }
+a { color: #0B5B9A; text-decoration: none; }
+a:hover { color: #d3d800; }
+ul { margin: 0; padding: 0; }
+ul li ul { margin: 10px; }
+</style>
+<body>
+<h1>CONTENTS</h1>
+<ul>
+  <li><a href="#LINK INFORMATION">LINK INFORMATION</a>
+<ul>
+  <li><a href="#LINK INFORMATION_Linker version">Linker version</a></li>
+  <li><a href="#LINK INFORMATION_Command line">Command line</a></li>
+</ul>
+  </li>
+  <li><a href="#LINKER SCRIPT">LINKER SCRIPT</a>
+<ul>
+  <li><a href="#LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;</a></li>
+</ul>
+  </li>
+  <li><a href="#PLACEMENT SUMMARY">PLACEMENT SUMMARY</a>
+<ul>
+  <li><a href="#PLACEMENT SUMMARY_place at 0x34064000">place at 0x34064000</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing">&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</a></li>
+</ul>
+  </li>
+  <li><a href="#MODULE SUMMARY">MODULE SUMMARY</a>
+<ul>
+  <li><a href="#MODULE SUMMARY_Memory use by input file">Memory use by input file</a></li>
+  <li><a href="#MODULE SUMMARY_Memory use by archive member">Memory use by archive member</a></li>
+  <li><a href="#MODULE SUMMARY_Memory use by linker">Memory use by linker</a></li>
+</ul>
+  </li>
+  <li><a href="#MODULE DETAIL">MODULE DETAIL</a>
+<ul>
+  <li><a href="#MODULE DETAIL_Module blto_App_lto.o">Module blto_App_lto.o</a></li>
+  <li><a href="#MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</a></li>
+  <li><a href="#MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</a></li>
+  <li><a href="#MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</a></li>
+  <li><a href="#MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</a></li>
+  <li><a href="#MODULE DETAIL_All modules">All modules</a></li>
+</ul>
+  </li>
+  <li><a href="#SECTION DETAIL">SECTION DETAIL</a>
+<ul>
+  <li><a href="#SECTION DETAIL_Sections by address">Sections by address</a></li>
+</ul>
+  </li>
+  <li><a href="#UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</a>
+<ul>
+  <li><a href="#UNUSED MEMORY SUMMARY_Detail">Detail</a></li>
+</ul>
+  </li>
+  <li><a href="#INITIALIZATION TABLE">INITIALIZATION TABLE</a>
+<ul>
+  <li><a href="#INITIALIZATION TABLE_Constructor list">Constructor list</a></li>
+  <li><a href="#INITIALIZATION TABLE_Initialize by zero">Initialize by zero</a></li>
+  <li><a href="#INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</a></li>
+  <li><a href="#INITIALIZATION TABLE_Summary">Summary</a></li>
+</ul>
+  </li>
+  <li><a href="#LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</a>
+<ul>
+  <li><a href="#LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Summary">Summary</a></li>
+</ul>
+  </li>
+  <li><a href="#SYMBOL LIST">SYMBOL LIST</a>
+<ul>
+  <li><a href="#SYMBOL LIST_Function symbols by name">Function symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Function symbols by address">Function symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</a></li>
+  <li><a href="#SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</a></li>
+</ul>
+  </li>
+  <li><a href="#REGION LIST">REGION LIST</a>
+<ul>
+  <li><a href="#REGION LIST_Regions by name">Regions by name</a></li>
+  <li><a href="#REGION LIST_Analysis">Analysis</a></li>
+</ul>
+  </li>
+  <li><a href="#BLOCK LIST">BLOCK LIST</a>
+<ul>
+  <li><a href="#BLOCK LIST_Blocks by name">Blocks by name</a></li>
+  <li><a href="#BLOCK LIST_Blocks by address">Blocks by address</a></li>
+</ul>
+  </li>
+  <li><a href="#STACK SIZES">STACK SIZES</a>
+<ul>
+  <li><a href="#STACK SIZES_Functions by stack size">Functions by stack size</a></li>
+  <li><a href="#STACK SIZES_Functions without stack size information">Functions without stack size information</a></li>
+</ul>
+  </li>
+  <li><a href="#UNUSED INPUTS">UNUSED INPUTS</a>
+<ul>
+  <li><a href="#UNUSED INPUTS_Unused object files">Unused object files</a></li>
+</ul>
+  </li>
+  <li><a href="#ABSOLUTE LISTING">ABSOLUTE LISTING</a>
+<ul>
+  <li><a href="#ABSOLUTE LISTING_Section .bss.uwTick from blto_App_lto.o, size=4, align=4">Section .bss.uwTick from blto_App_lto.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .data.uwTickPrio from blto_App_lto.o, size=4, align=4">Section .data.uwTickPrio from blto_App_lto.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .data.uwTickFreq from blto_App_lto.o, size=1, align=1">Section .data.uwTickFreq from blto_App_lto.o, size=1, align=1</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SysTick_Handler from blto_App_lto.o, size=8, align=4">Section .text.SysTick_Handler from blto_App_lto.o, size=8, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SystemInit from blto_App_lto.o, size=104, align=4">Section .text.SystemInit from blto_App_lto.o, size=104, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.TZ_SAU_Setup from blto_App_lto.o, size=108, align=4">Section .text.TZ_SAU_Setup from blto_App_lto.o, size=108, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=828, align=4">Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=828, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_Init from blto_App_lto.o, size=48, align=4">Section .text.HAL_Init from blto_App_lto.o, size=48, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.__NVIC_SetPriorityGrouping from blto_App_lto.o, size=60, align=4">Section .text.__NVIC_SetPriorityGrouping from blto_App_lto.o, size=60, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_NVIC_SetPriority from blto_App_lto.o, size=168, align=4">Section .text.HAL_NVIC_SetPriority from blto_App_lto.o, size=168, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.__NVIC_GetPriorityGrouping from blto_App_lto.o, size=16, align=4">Section .text.__NVIC_GetPriorityGrouping from blto_App_lto.o, size=16, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.NVIC_EncodePriority from blto_App_lto.o, size=100, align=4">Section .text.NVIC_EncodePriority from blto_App_lto.o, size=100, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_SYSTICK_Config from blto_App_lto.o, size=16, align=4">Section .text.HAL_SYSTICK_Config from blto_App_lto.o, size=16, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto_App_lto.o, size=1928, align=4">Section .text.HAL_GPIO_Init from blto_App_lto.o, size=1928, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.MX_GPIO_Init from blto_App_lto.o, size=426, align=4">Section .text.MX_GPIO_Init from blto_App_lto.o, size=426, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.LL_AHB4_GRP1_EnableClock from blto_App_lto.o, size=34, align=4">Section .text.LL_AHB4_GRP1_EnableClock from blto_App_lto.o, size=34, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.main from blto_App_lto.o, size=18, align=4">Section .text.main from blto_App_lto.o, size=18, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.assert_failed from blto_App_lto.o, size=10, align=4">Section .text.assert_failed from blto_App_lto.o, size=10, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_MspInit from blto_App_lto.o, size=2, align=4">Section .text.HAL_MspInit from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4">Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HardFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.HardFault_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.MemManage_Handler from blto_App_lto.o, size=2, align=4">Section .text.MemManage_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.BusFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.BusFault_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.UsageFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.UsageFault_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SVC_Handler from blto_App_lto.o, size=2, align=4">Section .text.SVC_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.DebugMon_Handler from blto_App_lto.o, size=2, align=4">Section .text.DebugMon_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.PendSV_Handler from blto_App_lto.o, size=2, align=4">Section .text.PendSV_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_InitTick from blto_App_lto.o, size=126, align=4">Section .text.HAL_InitTick from blto_App_lto.o, size=126, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_IncTick from blto_App_lto.o, size=26, align=4">Section .text.HAL_IncTick from blto_App_lto.o, size=26, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_NVIC_SetPriorityGrouping from blto_App_lto.o, size=62, align=4">Section .text.HAL_NVIC_SetPriorityGrouping from blto_App_lto.o, size=62, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.__NVIC_SetPriority from blto_App_lto.o, size=62, align=4">Section .text.__NVIC_SetPriority from blto_App_lto.o, size=62, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SysTick_Config from blto_App_lto.o, size=78, align=4">Section .text.SysTick_Config from blto_App_lto.o, size=78, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .rodata..L.str.7 from blto_App_lto.o, size=107, align=1">Section .rodata..L.str.7 from blto_App_lto.o, size=107, align=1</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .rodata..L.str.17 from blto_App_lto.o, size=105, align=1">Section .rodata..L.str.17 from blto_App_lto.o, size=105, align=1</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=12, align=4">Section .segger.init.data from [ Linker created ], size=12, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2</a></li>
+</ul>
+  </li>
+  <li><a href="#LINK SUMMARY">LINK SUMMARY</a>
+<ul>
+  <li><a href="#LINK SUMMARY_Memory breakdown">Memory breakdown</a></li>
+  <li><a href="#LINK SUMMARY_Region summary">Region summary</a></li>
+  <li><a href="#LINK SUMMARY_Diagnostic summary">Diagnostic summary</a></li>
+</ul>
+  </li>
+</ul>
+<h1 id="LINK INFORMATION">LINK INFORMATION</h1>
+<h2 id="LINK INFORMATION_Linker version">Linker version</h2>
+
+<pre>
+SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
+Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
+</pre>
+<h2 id="LINK INFORMATION_Command line">Command line</h2>
+
+<pre>
+--add-region:ITCM_RAM=0x00010000@0x10000000
+--add-region:DTCM_RAM=0x00020000@0x30000000
+--add-region:FLEX_RAM=0x00064000@0x34000000
+--add-region:AXI_RAM1=0x0009c000@0x34064000
+--add-region:AXI_RAM2=0x00070000@0x34100000
+--add-region:AXI_RAM3=0x00070000@0x34200000
+--add-region:AXI_RAM4=0x00070000@0x34270000
+--add-region:AXI_RAM5=0x00070000@0x342e0000
+--add-region:AXI_RAM6=0x00070000@0x34350000
+--add-region:AXI_RAM7=0x00040000@0x343c0000
+--add-region:AXI_RAM8=0x00020000@0x34400000
+--add-region:AHB_RAM1=0x00004000@0x38000000
+--add-region:AHB_RAM2=0x00004000@0x38004000
+--add-region:BKP_RAM=0x00002000@0x3c000000
+--add-region:FLASH_RAM=0x03f7fc00@0x70080400
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Production/Exe/blto_App.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=8.1-M.main
+--silent
+-TD:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf
+--defsym=__STACKSIZE__=8192
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=64
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/Output/Production/Exe/blto_App.elf
+D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/Output/Production/Obj/blto_App_lto.o
+Output/Production/Obj/SEGGER_THUMB_Startup.o
+Output/Production/Obj/stm32n657xx_Vectors.o
+Output/Production/Obj/STM32N6xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_basic_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi.a
+</pre>
+<h1 id="LINKER SCRIPT">LINKER SCRIPT</h1>
+<h2 id="LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;</h2>
+
+<pre>
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = FLEX_RAM;
+define region FLASH = FLASH_RAM;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH_RAM                          { section .FLASH_RAM, section .FLASH_RAM.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { section vectors };                                    // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in AXI_RAM5                           { section .AXI_RAM5, section .AXI_RAM5.* };  // This region may be deactivated and not accessible
+place in AXI_RAM6                           { section .AXI_RAM6, section .AXI_RAM6.* };  // This region may be deactivated and not accessible
+place in AXI_RAM7                           { section .AXI_RAM7, section .AXI_RAM7.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.* };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+</pre>
+<h1 id="PLACEMENT SUMMARY">PLACEMENT SUMMARY</h1>
+<h2 id="PLACEMENT SUMMARY_place at 0x34064000">place at 0x34064000</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing">&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080754</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700807BC</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080828</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080B64</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080B94</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080BD0</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080C78</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080C88</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080CEC</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080CFC</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081484</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081498</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700814C4</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008166E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081670</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081692</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081694</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816A6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816A8</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816B2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816B4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816B6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816B8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816BA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816BC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816BE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816C0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816C2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816C4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816C6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816C8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816CA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816CC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816CE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816D0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816D2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816D4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816D6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700816D8</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081756</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081758</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081772</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081774</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700817B2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700817B4</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700817F2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700817F4</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081842</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081844</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081846</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081848</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008184A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008184C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008184E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081850</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081852</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081854</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081856</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081858</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008185A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008185C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008185E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081860</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081862</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081864</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081866</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081868</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008186A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008186C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008186E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081870</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081872</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081874</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081876</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081878</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008187A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008187C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008187E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081880</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081882</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081884</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081886</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081888</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008188A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008188C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008188E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081890</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081892</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081894</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081896</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081898</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008189A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008189C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008189E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818A0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818A2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818A4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818A6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818A8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818AA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818AC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818AE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818B0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818B2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818B4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818B6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818B8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818BA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818BC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818BE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818C0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818C2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818C4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818C6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818C8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818CA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818CC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818CE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818D0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818D2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818D4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818D6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818D8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818DA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818DC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818DE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818E0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818E2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818E4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818E6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818E8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818EA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818EC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818EE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818F0</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818F2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818F4</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818F6</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818F8</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818FA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818FC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700818FE</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081900</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081902</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081904</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081906</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081908</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008190A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008190C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008190E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081910</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081912</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081914</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081916</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081918</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008191A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008191C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008191E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081920</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081922</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081924</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081926</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081928</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008192A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008192C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008192E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081930</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081932</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081934</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081936</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081938</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008193A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008193C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008193E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081940</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081942</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081944</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081946</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081948</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008194A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008194C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008194E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081950</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081952</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081954</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081956</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081958</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008195A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008195C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008195E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081960</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081962</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081964</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081966</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081968</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008196A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008196C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008196E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081970</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081972</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081974</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081976</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081978</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008197A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008197C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008197E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081980</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081982</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081984</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081986</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081988</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008198A</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008198C</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008198E</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081990</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081992</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..L.str.7]</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70081994</code></td>
+    <td align="right"><code>107</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..L.str.17]</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x700819FF</code></td>
+    <td align="right"><code>105</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata.block.tdata.copy]</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70081A68</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.init_array]</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="right"><code>0x70081A68</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081A6C</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70081A90</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70081AB4</code></td>
+    <td align="right"><code>12</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081AC0</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70081AD2</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="right"><code>0x34000008</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="right"><code>0x3400000C</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.heap]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34000010</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.heap]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34000010</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h1 id="MODULE SUMMARY">MODULE SUMMARY</h1>
+<h2 id="MODULE SUMMARY_Memory use by input file">Memory use by input file</h2>
+
+<table>
+  <tr>
+    <th align="left">Object File</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>blto_App_lto.o</code></td>
+    <td align="right"><code>4 244</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+    <td align="right"><code>1 216</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (4 objects)</code></td>
+    <td align="right"><code>5 524</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (1archives)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>5 598</code></td>
+    <td align="right"><code>260</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h2 id="MODULE SUMMARY_Memory use by archive member">Memory use by archive member</h2>
+
+<table>
+  <tr>
+    <th align="left">Archive member</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (1 members from 1 archives)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Objects (4 files)</code></td>
+    <td align="right"><code>5 524</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>5 598</code></td>
+    <td align="right"><code>260</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h2 id="MODULE SUMMARY_Memory use by linker">Memory use by linker</h2>
+
+<table>
+  <tr>
+    <th align="left">Description</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>Initialization table</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Memory for block &apos;stack&apos;</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (linker created):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Objects (4 files)</code></td>
+    <td align="right"><code>5 524</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Archives (1 files)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>5 598</code></td>
+    <td align="right"><code>260</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h1 id="MODULE DETAIL">MODULE DETAIL</h1>
+<h2 id="MODULE DETAIL_Module blto_App_lto.o">Module blto_App_lto.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..L.str.7]</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>107</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..L.str.17]</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>105</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>4 244</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>1 216</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_All modules">All modules</h2>
+
+<table>
+  <tr>
+    <th align="left"></th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>Grand total:</code></td>
+    <td align="right"><code>5 598</code></td>
+    <td align="right"><code>212</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+</table>
+<h1 id="SECTION DETAIL">SECTION DETAIL</h1>
+<h2 id="SECTION DETAIL_Sections by address">Sections by address</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="left">Symbol or [section] Name</th>
+    <th align="right">Size</th>
+    <th align="right">Al</th>
+    <th align="left">Init</th>
+    <th align="left">Ac</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>ZI</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-34000007</code></td>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>RW</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000008-3400000B</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>RW</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>3400000C-3400000C</code></td>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>RW</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>3400000D-34061FFF</code></td>
+    <td align="left" style="color: red;"><code>( UNUSED .=.+401395 )</code></td>
+    <td align="right"><code>401 395</code></td>
+    <td align="right"><code>-</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>-</code></td>
+    <td align="left"><code>-</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="left"><code>ZI</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080400-7008074B</code></td>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008074C-70080753</code></td>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080754-700807BB</code></td>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700807BC-70080827</code></td>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080828-70080B63</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080B64-70080B93</code></td>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080B94-70080BCF</code></td>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080BD0-70080C77</code></td>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080C78-70080C87</code></td>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080C88-70080CEB</code></td>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080CEC-70080CFB</code></td>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080CFC-70081483</code></td>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081484-70081497</code></td>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081498-700814C3</code></td>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700814C4-7008166D</code></td>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008166E-7008166F</code></td>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081670-70081691</code></td>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081692-70081693</code></td>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081694-700816A5</code></td>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816A6-700816A7</code></td>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816A8-700816B1</code></td>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816B2-700816B3</code></td>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816B4-700816B5</code></td>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816B6-700816B7</code></td>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816B8-700816B9</code></td>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816BA-700816BB</code></td>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816BC-700816BD</code></td>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816BE-700816BF</code></td>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816C0-700816C1</code></td>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816C2-700816C3</code></td>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816C4-700816C5</code></td>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816C6-700816C7</code></td>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816C8-700816C9</code></td>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816CA-700816CB</code></td>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816CC-700816CD</code></td>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816CE-700816CF</code></td>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816D0-700816D1</code></td>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816D2-700816D3</code></td>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816D4-700816D5</code></td>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816D6-700816D7</code></td>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700816D8-70081755</code></td>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081756-70081757</code></td>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081758-70081771</code></td>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081772-70081773</code></td>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081774-700817B1</code></td>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700817B2-700817B3</code></td>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700817B4-700817F1</code></td>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700817F2-700817F3</code></td>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700817F4-70081841</code></td>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081842-70081843</code></td>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081844-70081845</code></td>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081846-70081847</code></td>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081848-70081849</code></td>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008184A-7008184B</code></td>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008184C-7008184D</code></td>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008184E-7008184F</code></td>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081850-70081851</code></td>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081852-70081853</code></td>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081854-70081855</code></td>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081856-70081857</code></td>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081858-70081859</code></td>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008185A-7008185B</code></td>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008185C-7008185D</code></td>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008185E-7008185F</code></td>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081860-70081861</code></td>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081862-70081863</code></td>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081864-70081865</code></td>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081866-70081867</code></td>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081868-70081869</code></td>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008186A-7008186B</code></td>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008186C-7008186D</code></td>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008186E-7008186F</code></td>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081870-70081871</code></td>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081872-70081873</code></td>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081874-70081875</code></td>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081876-70081877</code></td>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081878-70081879</code></td>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008187A-7008187B</code></td>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008187C-7008187D</code></td>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008187E-7008187F</code></td>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081880-70081881</code></td>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081882-70081883</code></td>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081884-70081885</code></td>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081886-70081887</code></td>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081888-70081889</code></td>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008188A-7008188B</code></td>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008188C-7008188D</code></td>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008188E-7008188F</code></td>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081890-70081891</code></td>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081892-70081893</code></td>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081894-70081895</code></td>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081896-70081897</code></td>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081898-70081899</code></td>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008189A-7008189B</code></td>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008189C-7008189D</code></td>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008189E-7008189F</code></td>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818A0-700818A1</code></td>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818A2-700818A3</code></td>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818A4-700818A5</code></td>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818A6-700818A7</code></td>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818A8-700818A9</code></td>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818AA-700818AB</code></td>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818AC-700818AD</code></td>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818AE-700818AF</code></td>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818B0-700818B1</code></td>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818B2-700818B3</code></td>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818B4-700818B5</code></td>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818B6-700818B7</code></td>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818B8-700818B9</code></td>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818BA-700818BB</code></td>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818BC-700818BD</code></td>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818BE-700818BF</code></td>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818C0-700818C1</code></td>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818C2-700818C3</code></td>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818C4-700818C5</code></td>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818C6-700818C7</code></td>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818C8-700818C9</code></td>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818CA-700818CB</code></td>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818CC-700818CD</code></td>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818CE-700818CF</code></td>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818D0-700818D1</code></td>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818D2-700818D3</code></td>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818D4-700818D5</code></td>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818D6-700818D7</code></td>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818D8-700818D9</code></td>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818DA-700818DB</code></td>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818DC-700818DD</code></td>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818DE-700818DF</code></td>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818E0-700818E1</code></td>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818E2-700818E3</code></td>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818E4-700818E5</code></td>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818E6-700818E7</code></td>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818E8-700818E9</code></td>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818EA-700818EB</code></td>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818EC-700818ED</code></td>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818EE-700818EF</code></td>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818F0-700818F1</code></td>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818F2-700818F3</code></td>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818F4-700818F5</code></td>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818F6-700818F7</code></td>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818F8-700818F9</code></td>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818FA-700818FB</code></td>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818FC-700818FD</code></td>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700818FE-700818FF</code></td>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081900-70081901</code></td>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081902-70081903</code></td>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081904-70081905</code></td>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081906-70081907</code></td>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081908-70081909</code></td>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008190A-7008190B</code></td>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008190C-7008190D</code></td>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008190E-7008190F</code></td>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081910-70081911</code></td>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081912-70081913</code></td>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081914-70081915</code></td>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081916-70081917</code></td>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081918-70081919</code></td>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008191A-7008191B</code></td>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008191C-7008191D</code></td>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008191E-7008191F</code></td>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081920-70081921</code></td>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081922-70081923</code></td>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081924-70081925</code></td>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081926-70081927</code></td>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081928-70081929</code></td>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008192A-7008192B</code></td>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008192C-7008192D</code></td>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008192E-7008192F</code></td>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081930-70081931</code></td>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081932-70081933</code></td>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081934-70081935</code></td>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081936-70081937</code></td>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081938-70081939</code></td>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008193A-7008193B</code></td>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008193C-7008193D</code></td>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008193E-7008193F</code></td>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081940-70081941</code></td>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081942-70081943</code></td>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081944-70081945</code></td>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081946-70081947</code></td>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081948-70081949</code></td>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008194A-7008194B</code></td>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008194C-7008194D</code></td>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008194E-7008194F</code></td>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081950-70081951</code></td>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081952-70081953</code></td>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081954-70081955</code></td>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081956-70081957</code></td>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081958-70081959</code></td>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008195A-7008195B</code></td>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008195C-7008195D</code></td>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008195E-7008195F</code></td>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081960-70081961</code></td>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081962-70081963</code></td>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081964-70081965</code></td>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081966-70081967</code></td>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081968-70081969</code></td>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008196A-7008196B</code></td>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008196C-7008196D</code></td>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008196E-7008196F</code></td>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081970-70081971</code></td>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081972-70081973</code></td>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081974-70081975</code></td>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081976-70081977</code></td>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081978-70081979</code></td>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008197A-7008197B</code></td>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008197C-7008197D</code></td>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008197E-7008197F</code></td>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081980-70081981</code></td>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081982-70081983</code></td>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081984-70081985</code></td>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081986-70081987</code></td>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081988-70081989</code></td>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008198A-7008198B</code></td>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008198C-7008198D</code></td>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008198E-7008198F</code></td>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081990-70081991</code></td>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081992-70081993</code></td>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081994-700819FE</code></td>
+    <td align="left"><code>[.rodata..L.str.7]</code></td>
+    <td align="right"><code>107</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700819FF-70081A67</code></td>
+    <td align="left"><code>[.rodata..L.str.17]</code></td>
+    <td align="right"><code>105</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081A68-70081A6B</code></td>
+    <td align="left"><code>[.init_array]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>--</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081A6C-70081A8F</code></td>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081A90-70081AB3</code></td>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081AB4-70081ABF</code></td>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>12</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081AC0-70081AD1</code></td>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081AD2-70081AE5</code></td>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h1 id="UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</h1>
+<h2 id="UNUSED MEMORY SUMMARY_Detail">Detail</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Reason</th>
+  </tr>
+  <tr>
+    <td align="left"><code>3400000D-34061FFF</code></td>
+    <td align="right"><code>401 395</code></td>
+    <td align="left"><code>Unused memory between sections &apos;.data.uwTickFreq&apos; and &apos;.bss.block.stack&apos;</code></td>
+  </tr>
+</table>
+<h1 id="INITIALIZATION TABLE">INITIALIZATION TABLE</h1>
+<h2 id="INITIALIZATION TABLE_Constructor list">Constructor list</h2>
+
+<table>
+  <tr>
+    <th align="left">Table<br/>Address</th>
+    <th align="left">Called<br/>Address</th>
+    <th align="left">Called<br/>Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>0x70081A68</code></td>
+    <td align="left"><code>0x70080829</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+  </tr>
+</table>
+<h2 id="INITIALIZATION TABLE_Initialize by zero">Initialize by zero</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>uwTick</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Total (1 sections)</code></td>
+  </tr>
+<h2 id="INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-34000007</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>uwTickPrio</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000008-3400000B</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>3400000C-3400000C</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>uwTickFreq</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-3400000C</code></td>
+    <td align="right"><code>9</code></td>
+    <td align="left"><code>Total (3 sections)</code></td>
+  </tr>
+</pre>
+<h2 id="INITIALIZATION TABLE_Summary">Summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Description</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left">Initialization table</td>
+    <td align="right"><code>36 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Source image</td>
+    <td align="right"><code>9 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Destination image</td>
+    <td align="right"><code>13 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Saving</td>
+    <td align="right"><code>-32 bytes</code></td>
+  </tr>
+</table>
+<h1 id="LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</h1>
+<h2 id="LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Summary">Summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Veneer Type</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left">Thumb-Arm mode switch</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Arm-Thumb mode switch</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Thumb-Thumb range extension</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Arm-Arm range extension</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Total:</td>
+    <td align="right">0</td>
+  </tr>
+</table>
+<h1 id="SYMBOL LIST">SYMBOL LIST</h1>
+<h2 id="SYMBOL LIST_Function symbols by name">Function symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code>0x70081873</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>0x7008192B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x700816BF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>0x700816C5</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code>0x70081883</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x700816B7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code>0x70081863</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code>0x70081875</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code>0x7008198D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code>0x7008198F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code>0x70081877</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code>0x70081989</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code>0x70081889</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code>0x70081693</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>0x700816D1</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code>0x70081977</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code>0x700817F3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code>0x70081855</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code>0x70081857</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code>0x70081859</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code>0x7008185B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code>0x7008185D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code>0x7008185F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code>0x70081843</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code>0x70081845</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code>0x70081847</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code>0x70081849</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code>0x7008184B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code>0x7008184D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code>0x7008184F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code>0x70081851</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code>0x70081853</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x70081979</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x7008197B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x7008197D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x7008197F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x70081981</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x70081983</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code>0x70081985</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code>0x7008196B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code>0x700816C3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code>0x7008188F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code>0x70081891</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>0x700818B9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>0x700818CD</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>0x700818CF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>0x700818D1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>0x700818D3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>0x700818D5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>0x700818D7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>0x700818BB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>0x700818BD</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>0x700818BF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>0x700818C1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>0x700818C3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>0x700818C5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>0x700818C7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>0x700818C9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>0x700818CB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70081895</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code>0x70081893</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>0x70080CFD</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="right"><code>0x70081759</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="right"><code>0x70080B65</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="right"><code>0x700816D9</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="right"><code>0x700816B5</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="right"><code>0x70080BD1</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>0x70081775</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code>0x70081867</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>0x70081899</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>0x700818AD</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>0x700818AF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>0x700818B1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>0x700818B3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>0x700818B5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>0x700818B7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>0x7008189B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>0x7008189D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>0x7008189F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>0x700818A1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>0x700818A3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>0x700818A5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>0x700818A7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>0x700818A9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>0x700818AB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>0x700816BD</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818DB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818D9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818DF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818DD</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818E3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818E1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818E7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818E5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818EB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818E9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code>0x700818EF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code>0x700818ED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code>0x700816D3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code>0x70081897</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code>0x70081773</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code>0x7008188B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="right"><code>0x70081671</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code>0x700816B3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code>0x70081921</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code>0x70081923</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code>0x70081925</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code>0x70081927</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code>0x70081929</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code>0x70081963</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70081887</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code>0x70081885</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70081993</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code>0x70081991</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code>0x7008186B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code>0x7008186D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code>0x7008186F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code>0x70081871</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>0x7008192D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code>0x7008192F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code>0x70081931</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code>0x70081933</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code>0x70081935</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code>0x70081937</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code>0x70081987</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="right"><code>0x700814C5</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>0x700816C1</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>0x700816B9</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code>0x7008187B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code>0x7008187D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code>0x7008187F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code>0x70081881</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="right"><code>0x70080C89</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70081879</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code>0x70081865</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code>0x7008166F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>0x700816D5</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code>0x700816A7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code>0x700816D7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code>0x700816CF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code>0x70081869</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code>0x70081757</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code>0x700816C7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code>0x70081499</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code>0x70081861</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code>0x70081939</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code>0x7008193B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code>0x7008193D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code>0x7008193F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code>0x7008196D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code>0x7008196F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code>0x70081941</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code>0x70081943</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code>0x70081945</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code>0x70081947</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code>0x70081949</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code>0x7008194B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code>0x7008194D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>0x700816CD</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="right"><code>0x700817F5</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>0x7008074D</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>0x70080829</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>0x70080755</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code>0x700816CB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x700816BB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code>0x7008190F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code>0x70081911</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code>0x70081913</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code>0x70081915</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code>0x70081917</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code>0x70081919</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code>0x7008191B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code>0x7008191D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code>0x7008191F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code>0x700818F1</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code>0x700818F7</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>0x700818F5</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code>0x700818F3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code>0x700818F9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code>0x700818FB</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code>0x700818FD</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code>0x700818FF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code>0x70081901</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code>0x70081903</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code>0x70081905</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code>0x7008190B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>0x70081909</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code>0x70081907</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code>0x7008190D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="right"><code>0x700807BD</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code>0x70081955</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code>0x70081957</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code>0x7008195B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code>0x7008195D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code>0x7008195F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code>0x70081971</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code>0x70081961</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code>0x7008194F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code>0x70081951</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code>0x70081953</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code>0x70081959</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>0x70081973</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>0x70081975</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>0x700816C9</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code>0x7008188D</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code>0x7008198B</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code>0x700817B3</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code>0x70081965</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code>0x70081967</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code>0x70081969</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="right"><code>0x70080C79</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="right"><code>0x700817B5</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>0x70080B95</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>0x70081AD3</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>0x70081A6D</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code>0x7008148F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>0x70081AC1</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code>0x7008148F</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>0x70081485</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="right"><code>0x700816A9</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>0x70081493</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>0x70081695</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>0x70081499</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Function symbols by address">Function symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008074D</code></td>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080755</code></td>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700807BD</code></td>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080829</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080B65</code></td>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080B95</code></td>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080BD1</code></td>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080C79</code></td>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080C89</code></td>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CFD</code></td>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081485</code></td>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008148F</code></td>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008148F</code></td>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081493</code></td>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081499</code></td>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081499</code></td>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700814C5</code></td>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008166F</code></td>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081671</code></td>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081693</code></td>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081695</code></td>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816A7</code></td>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816A9</code></td>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816B3</code></td>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816B5</code></td>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816B7</code></td>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816B9</code></td>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816BB</code></td>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816BD</code></td>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816BF</code></td>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816C1</code></td>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816C3</code></td>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816C5</code></td>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816C7</code></td>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816C9</code></td>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816CB</code></td>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816CD</code></td>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816CF</code></td>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816D1</code></td>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816D3</code></td>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816D5</code></td>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816D7</code></td>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700816D9</code></td>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081757</code></td>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081759</code></td>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081773</code></td>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081775</code></td>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700817B3</code></td>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700817B5</code></td>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700817F3</code></td>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700817F5</code></td>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081843</code></td>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081845</code></td>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081847</code></td>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081849</code></td>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008184B</code></td>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008184D</code></td>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008184F</code></td>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081851</code></td>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081853</code></td>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081855</code></td>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081857</code></td>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081859</code></td>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008185B</code></td>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008185D</code></td>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008185F</code></td>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081861</code></td>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081863</code></td>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081865</code></td>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081867</code></td>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081869</code></td>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008186B</code></td>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008186D</code></td>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008186F</code></td>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081871</code></td>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081873</code></td>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081875</code></td>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081877</code></td>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081879</code></td>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008187B</code></td>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008187D</code></td>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008187F</code></td>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081881</code></td>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081883</code></td>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081885</code></td>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081887</code></td>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081889</code></td>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008188B</code></td>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008188D</code></td>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008188F</code></td>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081891</code></td>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081893</code></td>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081895</code></td>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081897</code></td>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081899</code></td>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008189B</code></td>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008189D</code></td>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008189F</code></td>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818A1</code></td>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818A3</code></td>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818A5</code></td>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818A7</code></td>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818A9</code></td>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818AB</code></td>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818AD</code></td>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818AF</code></td>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818B1</code></td>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818B3</code></td>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818B5</code></td>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818B7</code></td>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818B9</code></td>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818BB</code></td>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818BD</code></td>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818BF</code></td>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818C1</code></td>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818C3</code></td>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818C5</code></td>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818C7</code></td>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818C9</code></td>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818CB</code></td>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818CD</code></td>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818CF</code></td>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818D1</code></td>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818D3</code></td>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818D5</code></td>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818D7</code></td>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818D9</code></td>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818DB</code></td>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818DD</code></td>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818DF</code></td>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818E1</code></td>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818E3</code></td>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818E5</code></td>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818E7</code></td>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818E9</code></td>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818EB</code></td>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818ED</code></td>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818EF</code></td>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818F1</code></td>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818F3</code></td>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818F5</code></td>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818F7</code></td>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818F9</code></td>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818FB</code></td>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818FD</code></td>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700818FF</code></td>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081901</code></td>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081903</code></td>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081905</code></td>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081907</code></td>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081909</code></td>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008190B</code></td>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008190D</code></td>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008190F</code></td>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081911</code></td>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081913</code></td>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081915</code></td>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081917</code></td>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081919</code></td>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008191B</code></td>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008191D</code></td>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008191F</code></td>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081921</code></td>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081923</code></td>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081925</code></td>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081927</code></td>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081929</code></td>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008192B</code></td>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008192D</code></td>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008192F</code></td>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081931</code></td>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081933</code></td>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081935</code></td>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081937</code></td>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081939</code></td>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008193B</code></td>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008193D</code></td>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008193F</code></td>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081941</code></td>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081943</code></td>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081945</code></td>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081947</code></td>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081949</code></td>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008194B</code></td>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008194D</code></td>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008194F</code></td>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081951</code></td>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081953</code></td>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081955</code></td>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081957</code></td>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081959</code></td>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008195B</code></td>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008195D</code></td>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008195F</code></td>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081961</code></td>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081963</code></td>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081965</code></td>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081967</code></td>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081969</code></td>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008196B</code></td>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008196D</code></td>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008196F</code></td>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081971</code></td>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081973</code></td>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081975</code></td>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081977</code></td>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081979</code></td>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008197B</code></td>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008197D</code></td>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008197F</code></td>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081981</code></td>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081983</code></td>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081985</code></td>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081987</code></td>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081989</code></td>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008198B</code></td>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008198D</code></td>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008198F</code></td>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081991</code></td>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081993</code></td>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081A6D</code></td>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081AC1</code></td>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081AD3</code></td>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>1 928</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>828</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MX_GPIO_Init</code></td>
+    <td align="right"><code>426</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriority</code></td>
+    <td align="right"><code>168</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_InitTick</code></td>
+    <td align="right"><code>126</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TZ_SAU_Setup</code></td>
+    <td align="right"><code>108</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NVIC_EncodePriority</code></td>
+    <td align="right"><code>100</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Config</code></td>
+    <td align="right"><code>78</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriority</code></td>
+    <td align="right"><code>62</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_SetPriorityGrouping</code></td>
+    <td align="right"><code>60</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_Init</code></td>
+    <td align="right"><code>48</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LL_AHB4_GRP1_EnableClock</code></td>
+    <td align="right"><code>34</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_IncTick</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_SYSTICK_Config</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__NVIC_GetPriorityGrouping</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>assert_failed</code></td>
+    <td align="right"><code>10</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_MspInit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>0x34000008</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="right"><code>0x3400000C</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000008</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3400000C</code></td>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickPrio</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTickFreq</code></td>
+    <td align="right"><code>1</code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>0x70081AB4</code></td>
+    <td align="right"><code>[12]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>0x70081A90</code></td>
+    <td align="right"><code>[36]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081A90</code></td>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>[36]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081AB4</code></td>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>[12]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Value</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_size__</code></td>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_end__</code></td>
+    <td align="right"><code>0x38008000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_size__</code></td>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_start__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_end__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_start__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_end__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_size__</code></td>
+    <td align="right"><code>0x0009C000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_start__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_start__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_end__</code></td>
+    <td align="right"><code>0x34170000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_start__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_end__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_start__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_end__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_start__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_end__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_start__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_end__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_start__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_end__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_start__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_end__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_start__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_end__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_start__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_end__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_start__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_end__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_start__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_end__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_size__</code></td>
+    <td align="right"><code>0x00040000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_start__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_end__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_start__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_end__</code></td>
+    <td align="right"><code>0x34420000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_size__</code></td>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_start__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_end__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
+    <td align="right"><code>0x3C002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_end__</code></td>
+    <td align="right"><code>0x30020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_start__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_end__</code></td>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_size__</code></td>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x70081AE6</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x000016E6</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_end__</code></td>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_size__</code></td>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_end__</code></td>
+    <td align="right"><code>0x70081AE6</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_size__</code></td>
+    <td align="right"><code>0x000016E6</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__HEAPSIZE__</code></td>
+    <td align="right"><code>0x00000040</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_end__</code></td>
+    <td align="right"><code>0x10010000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00010000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_start__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__STACKSIZE__</code></td>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ctors_end__</code></td>
+    <td align="right"><code>0x70081A6C</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ctors_start__</code></td>
+    <td align="right"><code>0x70081A68</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__stack_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__stack_start__</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__thread_pointer$</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors_end</code></td>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>g_pfnVectors</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Value</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__thread_pointer$</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000040</code></td>
+    <td align="left"><code>__HEAPSIZE__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x000016E6</code></td>
+    <td align="left"><code>__FLASH_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x000016E6</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="left"><code>__STACKSIZE__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00010000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00040000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x0009C000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="left"><code>__FLASH_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10010000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30020000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="left"><code>__stack_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__stack_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34170000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34420000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38008000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C002000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>g_pfnVectors</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="left"><code>_vectors_end</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081A68</code></td>
+    <td align="left"><code>__ctors_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081A6C</code></td>
+    <td align="left"><code>__ctors_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081AE6</code></td>
+    <td align="left"><code>__FLASH_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70081AE6</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="left"><code>__FLASH_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h1 id="REGION LIST">REGION LIST</h1>
+<h2 id="REGION LIST_Regions by name">Regions by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left"><code>AHB_RAM1</code></td>
+    <td align="left"><code>38000000-38003FFF</code></td>
+    <td align="right"><code>16 384</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AHB_RAM2</code></td>
+    <td align="left"><code>38004000-38007FFF</code></td>
+    <td align="right"><code>16 384</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM1</code></td>
+    <td align="left"><code>34064000-340FFFFF</code></td>
+    <td align="right"><code>638 976</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM2</code></td>
+    <td align="left"><code>34100000-3416FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM3</code></td>
+    <td align="left"><code>34200000-3426FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM4</code></td>
+    <td align="left"><code>34270000-342DFFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM5</code></td>
+    <td align="left"><code>342E0000-3434FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM6</code></td>
+    <td align="left"><code>34350000-343BFFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM7</code></td>
+    <td align="left"><code>343C0000-343FFFFF</code></td>
+    <td align="right"><code>262 144</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM8</code></td>
+    <td align="left"><code>34400000-3441FFFF</code></td>
+    <td align="right"><code>131 072</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BKP_RAM</code></td>
+    <td align="left"><code>3C000000-3C001FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTCM_RAM</code></td>
+    <td align="left"><code>30000000-3001FFFF</code></td>
+    <td align="right"><code>131 072</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH_RAM</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLEX_RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ITCM_RAM</code></td>
+    <td align="left"><code>10000000-1000FFFF</code></td>
+    <td align="right"><code>65 536</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+  </tr>
+</table>
+<h2 id="REGION LIST_Analysis">Analysis</h2>
+
+FLASH:
+  Identical to region FLASH_RAM
+
+FLASH_RAM:
+  Identical to region FLASH
+
+FLEX_RAM:
+  Identical to region RAM
+
+RAM:
+  Identical to region FLEX_RAM
+<h1 id="BLOCK LIST">BLOCK LIST</h1>
+<h2 id="BLOCK LIST_Blocks by name">Blocks by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Ordering</th>
+  </tr>
+  <tr>
+    <td align="left"><code>ctors</code></td>
+    <td align="left"><code>70081A68-70081A6B</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>stack</code></td>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+</table>
+<h2 id="BLOCK LIST_Blocks by address">Blocks by address</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Name</th>
+    <th align="left">Ordering</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="left"><code>stack</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70081A68-70081A6B</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>ctors</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+</table>
+<h1 id="STACK SIZES">STACK SIZES</h1>
+<h2 id="STACK SIZES_Functions by stack size">Functions by stack size</h2>
+
+<table>
+  <tr>
+    <th align="left">Function name</th>
+    <th align="right">Stack</th>
+    <th align="left">Object File</th>
+  </tr>
+</table>
+<h2 id="STACK SIZES_Functions without stack size information">Functions without stack size information</h2>
+
+  MX_GPIO_Init
+  LL_AHB4_GRP1_EnableClock
+  HAL_GPIO_Init
+  HAL_Init
+  assert_failed
+  HAL_MspInit
+  HAL_IncTick
+  TZ_SAU_Setup
+  HAL_NVIC_SetPriorityGrouping
+  HAL_InitTick
+  HAL_SYSTICK_Config
+  HAL_NVIC_SetPriority
+  __NVIC_SetPriorityGrouping
+  __NVIC_GetPriorityGrouping
+  NVIC_EncodePriority
+  __NVIC_SetPriority
+  SysTick_Config
+  main
+  NMI_Handler
+  HardFault_Handler
+  MemManage_Handler
+  BusFault_Handler
+  UsageFault_Handler
+  SVC_Handler
+  DebugMon_Handler
+  PendSV_Handler
+  SysTick_Handler
+  SystemInit
+  SystemCoreClockUpdate
+  _start
+  __SEGGER_init_done
+  __startup_complete
+  exit
+  PVD_PVM_IRQHandler
+  DTS_IRQHandler
+  RCC_IRQHandler
+  LOCKUP_IRQHandler
+  CACHE_ECC_IRQHandler
+  TCM_ECC_IRQHandler
+  BCK_ECC_IRQHandler
+  FPU_IRQHandler
+  RTC_S_IRQHandler
+  TAMP_IRQHandler
+  RIFSC_TAMPER_IRQHandler
+  IAC_IRQHandler
+  RCC_S_IRQHandler
+  RTC_IRQHandler
+  IWDG_IRQHandler
+  WWDG_IRQHandler
+  EXTI0_IRQHandler
+  EXTI1_IRQHandler
+  EXTI2_IRQHandler
+  EXTI3_IRQHandler
+  EXTI4_IRQHandler
+  EXTI5_IRQHandler
+  EXTI6_IRQHandler
+  EXTI7_IRQHandler
+  EXTI8_IRQHandler
+  EXTI9_IRQHandler
+  EXTI10_IRQHandler
+  EXTI11_IRQHandler
+  EXTI12_IRQHandler
+  EXTI13_IRQHandler
+  EXTI14_IRQHandler
+  EXTI15_IRQHandler
+  SAES_IRQHandler
+  CRYP_IRQHandler
+  PKA_IRQHandler
+  HASH_IRQHandler
+  RNG_IRQHandler
+  MCE1_IRQHandler
+  MCE2_IRQHandler
+  MCE3_IRQHandler
+  MCE4_IRQHandler
+  ADC1_2_IRQHandler
+  CSI_IRQHandler
+  DCMIPP_IRQHandler
+  PAHB_ERR_IRQHandler
+  NPU0_IRQHandler
+  NPU1_IRQHandler
+  NPU2_IRQHandler
+  NPU3_IRQHandler
+  CACHEAXI_IRQHandler
+  LTDC_LO_IRQHandler
+  LTDC_LO_ERR_IRQHandler
+  DMA2D_IRQHandler
+  JPEG_IRQHandler
+  VENC_IRQHandler
+  GFXMMU_IRQHandler
+  GFXTIM_IRQHandler
+  GPU2D_IRQHandler
+  GPU2D_ER_IRQHandler
+  ICACHE_IRQHandler
+  HPDMA1_Channel0_IRQHandler
+  HPDMA1_Channel1_IRQHandler
+  HPDMA1_Channel2_IRQHandler
+  HPDMA1_Channel3_IRQHandler
+  HPDMA1_Channel4_IRQHandler
+  HPDMA1_Channel5_IRQHandler
+  HPDMA1_Channel6_IRQHandler
+  HPDMA1_Channel7_IRQHandler
+  HPDMA1_Channel8_IRQHandler
+  HPDMA1_Channel9_IRQHandler
+  HPDMA1_Channel10_IRQHandler
+  HPDMA1_Channel11_IRQHandler
+  HPDMA1_Channel12_IRQHandler
+  HPDMA1_Channel13_IRQHandler
+  HPDMA1_Channel14_IRQHandler
+  HPDMA1_Channel15_IRQHandler
+  GPDMA1_Channel0_IRQHandler
+  GPDMA1_Channel1_IRQHandler
+  GPDMA1_Channel2_IRQHandler
+  GPDMA1_Channel3_IRQHandler
+  GPDMA1_Channel4_IRQHandler
+  GPDMA1_Channel5_IRQHandler
+  GPDMA1_Channel6_IRQHandler
+  GPDMA1_Channel7_IRQHandler
+  GPDMA1_Channel8_IRQHandler
+  GPDMA1_Channel9_IRQHandler
+  GPDMA1_Channel10_IRQHandler
+  GPDMA1_Channel11_IRQHandler
+  GPDMA1_Channel12_IRQHandler
+  GPDMA1_Channel13_IRQHandler
+  GPDMA1_Channel14_IRQHandler
+  GPDMA1_Channel15_IRQHandler
+  I2C1_EV_IRQHandler
+  I2C1_ER_IRQHandler
+  I2C2_EV_IRQHandler
+  I2C2_ER_IRQHandler
+  I2C3_EV_IRQHandler
+  I2C3_ER_IRQHandler
+  I2C4_EV_IRQHandler
+  I2C4_ER_IRQHandler
+  I3C1_EV_IRQHandler
+  I3C1_ER_IRQHandler
+  I3C2_EV_IRQHandler
+  I3C2_ER_IRQHandler
+  TIM1_BRK_IRQHandler
+  TIM1_UP_IRQHandler
+  TIM1_TRG_CCU_IRQHandler
+  TIM1_CC_IRQHandler
+  TIM2_IRQHandler
+  TIM3_IRQHandler
+  TIM4_IRQHandler
+  TIM5_IRQHandler
+  TIM6_IRQHandler
+  TIM7_IRQHandler
+  TIM8_BRK_IRQHandler
+  TIM8_UP_IRQHandler
+  TIM8_TRG_CCU_IRQHandler
+  TIM8_CC_IRQHandler
+  TIM9_IRQHandler
+  TIM10_IRQHandler
+  TIM11_IRQHandler
+  TIM12_IRQHandler
+  TIM13_IRQHandler
+  TIM14_IRQHandler
+  TIM15_IRQHandler
+  TIM16_IRQHandler
+  TIM17_IRQHandler
+  TIM18_IRQHandler
+  LPTIM1_IRQHandler
+  LPTIM2_IRQHandler
+  LPTIM3_IRQHandler
+  LPTIM4_IRQHandler
+  LPTIM5_IRQHandler
+  ADF1_FLT0_IRQHandler
+  MDF1_FLT0_IRQHandler
+  MDF1_FLT1_IRQHandler
+  MDF1_FLT2_IRQHandler
+  MDF1_FLT3_IRQHandler
+  MDF1_FLT4_IRQHandler
+  MDF1_FLT5_IRQHandler
+  SAI1_A_IRQHandler
+  SAI1_B_IRQHandler
+  SAI2_A_IRQHandler
+  SAI2_B_IRQHandler
+  SPDIFRX_IRQHandler
+  SPI1_IRQHandler
+  SPI2_IRQHandler
+  SPI3_IRQHandler
+  SPI4_IRQHandler
+  SPI5_IRQHandler
+  SPI6_IRQHandler
+  USART1_IRQHandler
+  USART2_IRQHandler
+  USART3_IRQHandler
+  UART4_IRQHandler
+  UART5_IRQHandler
+  USART6_IRQHandler
+  UART7_IRQHandler
+  UART8_IRQHandler
+  UART9_IRQHandler
+  USART10_IRQHandler
+  LPUART1_IRQHandler
+  XSPI1_IRQHandler
+  XSPI2_IRQHandler
+  XSPI3_IRQHandler
+  FMC_IRQHandler
+  SDMMC1_IRQHandler
+  SDMMC2_IRQHandler
+  UCPD1_IRQHandler
+  USB1_OTG_HS_IRQHandler
+  USB2_OTG_HS_IRQHandler
+  ETH1_IRQHandler
+  FDCAN1_IT0_IRQHandler
+  FDCAN1_IT1_IRQHandler
+  FDCAN2_IT0_IRQHandler
+  FDCAN2_IT1_IRQHandler
+  FDCAN3_IT0_IRQHandler
+  FDCAN3_IT1_IRQHandler
+  FDCAN_CU_IRQHandler
+  MDIOS_IRQHandler
+  DCMI_PSSI_IRQHandler
+  WAKEUP_PIN_IRQHandler
+  CTI_INT0_IRQHandler
+  CTI_INT1_IRQHandler
+  LTDC_UP_IRQHandler
+  LTDC_UP_ERR_IRQHandler
+  reset_handler
+  Reset_Handler
+  __SEGGER_init_zero
+  __SEGGER_init_copy
+  __SEGGER_init_ctors
+<h1 id="UNUSED INPUTS">UNUSED INPUTS</h1>
+<h2 id="UNUSED INPUTS_Unused object files">Unused object files</h2>
+
+No unused object files
+<h1 id="ABSOLUTE LISTING">ABSOLUTE LISTING</h1>
+<h2 id="ABSOLUTE LISTING_Section .bss.uwTick from blto_App_lto.o, size=4, align=4">Section .bss.uwTick from blto_App_lto.o, size=4, align=4</h2>
+
+<pre>
+<br/><span id="uwTick">uwTick:</span>
+<span id="A34000000">  0x34000000:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A34000001">  0x34000001:  </span>3A           DC.B       0x3A                     ; ':'
+<span id="A34000002">  0x34000002:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A34000003">  0x34000003:  </span>50           DC.B       0x50                     ; 'P'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .data.uwTickPrio from blto_App_lto.o, size=4, align=4">Section .data.uwTickPrio from blto_App_lto.o, size=4, align=4</h2>
+
+<pre>
+<br/><span id="uwTickPrio">uwTickPrio:</span>
+<span id="A34000004">  0x34000004:  </span>10           DC.B       0x10                     ; '\x10'
+<span id="A34000005">  0x34000005:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000006">  0x34000006:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000007">  0x34000007:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4</h2>
+
+<pre>
+<br/><span id="SystemCoreClock">SystemCoreClock:</span>
+<span id="A34000008">  0x34000008:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000009">  0x34000009:  </span>90           DC.B       0x90                     ; '\x90'
+<span id="A3400000A">  0x3400000A:  </span>D0           DC.B       0xD0                     ; '\xD0'
+<span id="A3400000B">  0x3400000B:  </span>03           DC.B       0x03                     ; '\x03'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .data.uwTickFreq from blto_App_lto.o, size=1, align=1">Section .data.uwTickFreq from blto_App_lto.o, size=1, align=1</h2>
+
+<pre>
+<br/><span id="uwTickFreq">uwTickFreq:</span>
+<span id="A3400000C">  0x3400000C:  </span>01           DC.B       0x01                     ; '\x01'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</h2>
+
+<pre>
+(34062000-34063FFF excluded)
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</h2>
+
+<pre>
+<br/><span id="_vectors">_vectors:</span>
+<span id="g_pfnVectors">g_pfnVectors:</span>
+<span id="A70080400">  0x70080400:  </span>34064000     DC.W       34064000               ; R_ARM_ABS32
+<span id="A70080404">  0x70080404:  </span>70081499     DC.W       <a href="#reset_handler">reset_handler</a>
+<span id="A70080408">  0x70080408:  </span>700816B9     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008040C">  0x7008040C:  </span>700816BD     DC.W       <a href="#HardFault_Handler">HardFault_Handler</a>
+<span id="A70080410">  0x70080410:  </span>700816C1     DC.W       <a href="#MemManage_Handler">MemManage_Handler</a>
+<span id="A70080414">  0x70080414:  </span>700816C5     DC.W       <a href="#BusFault_Handler">BusFault_Handler</a>
+<span id="A70080418">  0x70080418:  </span>700816C9     DC.W       <a href="#UsageFault_Handler">UsageFault_Handler</a>
+<span id="A7008041C">  0x7008041C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041D">  0x7008041D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041E">  0x7008041E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041F">  0x7008041F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080420">  0x70080420:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080421">  0x70080421:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080422">  0x70080422:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080423">  0x70080423:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080424">  0x70080424:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080425">  0x70080425:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080426">  0x70080426:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080427">  0x70080427:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080428">  0x70080428:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080429">  0x70080429:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042A">  0x7008042A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042B">  0x7008042B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042C">  0x7008042C:  </span>700816CD     DC.W       <a href="#SVC_Handler">SVC_Handler</a>
+<span id="A70080430">  0x70080430:  </span>700816D1     DC.W       <a href="#DebugMon_Handler">DebugMon_Handler</a>
+<span id="A70080434">  0x70080434:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080435">  0x70080435:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080436">  0x70080436:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080437">  0x70080437:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080438">  0x70080438:  </span>700816D5     DC.W       <a href="#PendSV_Handler">PendSV_Handler</a>
+<span id="A7008043C">  0x7008043C:  </span>7008074D     DC.W       <a href="#SysTick_Handler">SysTick_Handler</a>
+<span id="A70080440">  0x70080440:  </span>7008166F     DC.W       <a href="#PVD_PVM_IRQHandler">PVD_PVM_IRQHandler</a>
+<span id="A70080444">  0x70080444:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080445">  0x70080445:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080446">  0x70080446:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080447">  0x70080447:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080448">  0x70080448:  </span>70081693     DC.W       <a href="#DTS_IRQHandler">DTS_IRQHandler</a>
+<span id="A7008044C">  0x7008044C:  </span>700816A7     DC.W       <a href="#RCC_IRQHandler">RCC_IRQHandler</a>
+<span id="A70080450">  0x70080450:  </span>700816B3     DC.W       <a href="#LOCKUP_IRQHandler">LOCKUP_IRQHandler</a>
+<span id="A70080454">  0x70080454:  </span>700816B7     DC.W       <a href="#CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler</a>
+<span id="A70080458">  0x70080458:  </span>700816BB     DC.W       <a href="#TCM_ECC_IRQHandler">TCM_ECC_IRQHandler</a>
+<span id="A7008045C">  0x7008045C:  </span>700816BF     DC.W       <a href="#BCK_ECC_IRQHandler">BCK_ECC_IRQHandler</a>
+<span id="A70080460">  0x70080460:  </span>700816C3     DC.W       <a href="#FPU_IRQHandler">FPU_IRQHandler</a>
+<span id="A70080464">  0x70080464:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080465">  0x70080465:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080466">  0x70080466:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080467">  0x70080467:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080468">  0x70080468:  </span>700816C7     DC.W       <a href="#RTC_S_IRQHandler">RTC_S_IRQHandler</a>
+<span id="A7008046C">  0x7008046C:  </span>700816CB     DC.W       <a href="#TAMP_IRQHandler">TAMP_IRQHandler</a>
+<span id="A70080470">  0x70080470:  </span>700816CF     DC.W       <a href="#RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler</a>
+<span id="A70080474">  0x70080474:  </span>700816D3     DC.W       <a href="#IAC_IRQHandler">IAC_IRQHandler</a>
+<span id="A70080478">  0x70080478:  </span>700816D7     DC.W       <a href="#RCC_S_IRQHandler">RCC_S_IRQHandler</a>
+<span id="A7008047C">  0x7008047C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047D">  0x7008047D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047E">  0x7008047E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047F">  0x7008047F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080480">  0x70080480:  </span>70081757     DC.W       <a href="#RTC_IRQHandler">RTC_IRQHandler</a>
+<span id="A70080484">  0x70080484:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080485">  0x70080485:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080486">  0x70080486:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080487">  0x70080487:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080488">  0x70080488:  </span>70081773     DC.W       <a href="#IWDG_IRQHandler">IWDG_IRQHandler</a>
+<span id="A7008048C">  0x7008048C:  </span>700817B3     DC.W       <a href="#WWDG_IRQHandler">WWDG_IRQHandler</a>
+<span id="A70080490">  0x70080490:  </span>700817F3     DC.W       <a href="#EXTI0_IRQHandler">EXTI0_IRQHandler</a>
+<span id="A70080494">  0x70080494:  </span>70081843     DC.W       <a href="#EXTI1_IRQHandler">EXTI1_IRQHandler</a>
+<span id="A70080498">  0x70080498:  </span>70081845     DC.W       <a href="#EXTI2_IRQHandler">EXTI2_IRQHandler</a>
+<span id="A7008049C">  0x7008049C:  </span>70081847     DC.W       <a href="#EXTI3_IRQHandler">EXTI3_IRQHandler</a>
+<span id="A700804A0">  0x700804A0:  </span>70081849     DC.W       <a href="#EXTI4_IRQHandler">EXTI4_IRQHandler</a>
+<span id="A700804A4">  0x700804A4:  </span>7008184B     DC.W       <a href="#EXTI5_IRQHandler">EXTI5_IRQHandler</a>
+<span id="A700804A8">  0x700804A8:  </span>7008184D     DC.W       <a href="#EXTI6_IRQHandler">EXTI6_IRQHandler</a>
+<span id="A700804AC">  0x700804AC:  </span>7008184F     DC.W       <a href="#EXTI7_IRQHandler">EXTI7_IRQHandler</a>
+<span id="A700804B0">  0x700804B0:  </span>70081851     DC.W       <a href="#EXTI8_IRQHandler">EXTI8_IRQHandler</a>
+<span id="A700804B4">  0x700804B4:  </span>70081853     DC.W       <a href="#EXTI9_IRQHandler">EXTI9_IRQHandler</a>
+<span id="A700804B8">  0x700804B8:  </span>70081855     DC.W       <a href="#EXTI10_IRQHandler">EXTI10_IRQHandler</a>
+<span id="A700804BC">  0x700804BC:  </span>70081857     DC.W       <a href="#EXTI11_IRQHandler">EXTI11_IRQHandler</a>
+<span id="A700804C0">  0x700804C0:  </span>70081859     DC.W       <a href="#EXTI12_IRQHandler">EXTI12_IRQHandler</a>
+<span id="A700804C4">  0x700804C4:  </span>7008185B     DC.W       <a href="#EXTI13_IRQHandler">EXTI13_IRQHandler</a>
+<span id="A700804C8">  0x700804C8:  </span>7008185D     DC.W       <a href="#EXTI14_IRQHandler">EXTI14_IRQHandler</a>
+<span id="A700804CC">  0x700804CC:  </span>7008185F     DC.W       <a href="#EXTI15_IRQHandler">EXTI15_IRQHandler</a>
+<span id="A700804D0">  0x700804D0:  </span>70081861     DC.W       <a href="#SAES_IRQHandler">SAES_IRQHandler</a>
+<span id="A700804D4">  0x700804D4:  </span>70081863     DC.W       <a href="#CRYP_IRQHandler">CRYP_IRQHandler</a>
+<span id="A700804D8">  0x700804D8:  </span>70081865     DC.W       <a href="#PKA_IRQHandler">PKA_IRQHandler</a>
+<span id="A700804DC">  0x700804DC:  </span>70081867     DC.W       <a href="#HASH_IRQHandler">HASH_IRQHandler</a>
+<span id="A700804E0">  0x700804E0:  </span>70081869     DC.W       <a href="#RNG_IRQHandler">RNG_IRQHandler</a>
+<span id="A700804E4">  0x700804E4:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E5">  0x700804E5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E6">  0x700804E6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E7">  0x700804E7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E8">  0x700804E8:  </span>7008186B     DC.W       <a href="#MCE1_IRQHandler">MCE1_IRQHandler</a>
+<span id="A700804EC">  0x700804EC:  </span>7008186D     DC.W       <a href="#MCE2_IRQHandler">MCE2_IRQHandler</a>
+<span id="A700804F0">  0x700804F0:  </span>7008186F     DC.W       <a href="#MCE3_IRQHandler">MCE3_IRQHandler</a>
+<span id="A700804F4">  0x700804F4:  </span>70081871     DC.W       <a href="#MCE4_IRQHandler">MCE4_IRQHandler</a>
+<span id="A700804F8">  0x700804F8:  </span>70081873     DC.W       <a href="#ADC1_2_IRQHandler">ADC1_2_IRQHandler</a>
+<span id="A700804FC">  0x700804FC:  </span>70081875     DC.W       <a href="#CSI_IRQHandler">CSI_IRQHandler</a>
+<span id="A70080500">  0x70080500:  </span>70081877     DC.W       <a href="#DCMIPP_IRQHandler">DCMIPP_IRQHandler</a>
+<span id="A70080504">  0x70080504:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080505">  0x70080505:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080506">  0x70080506:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080507">  0x70080507:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080508">  0x70080508:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080509">  0x70080509:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050A">  0x7008050A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050B">  0x7008050B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050C">  0x7008050C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050D">  0x7008050D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050E">  0x7008050E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050F">  0x7008050F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080510">  0x70080510:  </span>70081879     DC.W       <a href="#PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler</a>
+<span id="A70080514">  0x70080514:  </span>7008187B     DC.W       <a href="#NPU0_IRQHandler">NPU0_IRQHandler</a>
+<span id="A70080518">  0x70080518:  </span>7008187D     DC.W       <a href="#NPU1_IRQHandler">NPU1_IRQHandler</a>
+<span id="A7008051C">  0x7008051C:  </span>7008187F     DC.W       <a href="#NPU2_IRQHandler">NPU2_IRQHandler</a>
+<span id="A70080520">  0x70080520:  </span>70081881     DC.W       <a href="#NPU3_IRQHandler">NPU3_IRQHandler</a>
+<span id="A70080524">  0x70080524:  </span>70081883     DC.W       <a href="#CACHEAXI_IRQHandler">CACHEAXI_IRQHandler</a>
+<span id="A70080528">  0x70080528:  </span>70081885     DC.W       <a href="#LTDC_LO_IRQHandler">LTDC_LO_IRQHandler</a>
+<span id="A7008052C">  0x7008052C:  </span>70081887     DC.W       <a href="#LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler</a>
+<span id="A70080530">  0x70080530:  </span>70081889     DC.W       <a href="#DMA2D_IRQHandler">DMA2D_IRQHandler</a>
+<span id="A70080534">  0x70080534:  </span>7008188B     DC.W       <a href="#JPEG_IRQHandler">JPEG_IRQHandler</a>
+<span id="A70080538">  0x70080538:  </span>7008188D     DC.W       <a href="#VENC_IRQHandler">VENC_IRQHandler</a>
+<span id="A7008053C">  0x7008053C:  </span>7008188F     DC.W       <a href="#GFXMMU_IRQHandler">GFXMMU_IRQHandler</a>
+<span id="A70080540">  0x70080540:  </span>70081891     DC.W       <a href="#GFXTIM_IRQHandler">GFXTIM_IRQHandler</a>
+<span id="A70080544">  0x70080544:  </span>70081893     DC.W       <a href="#GPU2D_IRQHandler">GPU2D_IRQHandler</a>
+<span id="A70080548">  0x70080548:  </span>70081895     DC.W       <a href="#GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler</a>
+<span id="A7008054C">  0x7008054C:  </span>70081897     DC.W       <a href="#ICACHE_IRQHandler">ICACHE_IRQHandler</a>
+<span id="A70080550">  0x70080550:  </span>70081899     DC.W       <a href="#HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler</a>
+<span id="A70080554">  0x70080554:  </span>7008189B     DC.W       <a href="#HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler</a>
+<span id="A70080558">  0x70080558:  </span>7008189D     DC.W       <a href="#HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler</a>
+<span id="A7008055C">  0x7008055C:  </span>7008189F     DC.W       <a href="#HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler</a>
+<span id="A70080560">  0x70080560:  </span>700818A1     DC.W       <a href="#HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler</a>
+<span id="A70080564">  0x70080564:  </span>700818A3     DC.W       <a href="#HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler</a>
+<span id="A70080568">  0x70080568:  </span>700818A5     DC.W       <a href="#HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler</a>
+<span id="A7008056C">  0x7008056C:  </span>700818A7     DC.W       <a href="#HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler</a>
+<span id="A70080570">  0x70080570:  </span>700818A9     DC.W       <a href="#HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler</a>
+<span id="A70080574">  0x70080574:  </span>700818AB     DC.W       <a href="#HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler</a>
+<span id="A70080578">  0x70080578:  </span>700818AD     DC.W       <a href="#HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler</a>
+<span id="A7008057C">  0x7008057C:  </span>700818AF     DC.W       <a href="#HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler</a>
+<span id="A70080580">  0x70080580:  </span>700818B1     DC.W       <a href="#HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler</a>
+<span id="A70080584">  0x70080584:  </span>700818B3     DC.W       <a href="#HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler</a>
+<span id="A70080588">  0x70080588:  </span>700818B5     DC.W       <a href="#HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler</a>
+<span id="A7008058C">  0x7008058C:  </span>700818B7     DC.W       <a href="#HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler</a>
+<span id="A70080590">  0x70080590:  </span>700818B9     DC.W       <a href="#GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler</a>
+<span id="A70080594">  0x70080594:  </span>700818BB     DC.W       <a href="#GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler</a>
+<span id="A70080598">  0x70080598:  </span>700818BD     DC.W       <a href="#GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler</a>
+<span id="A7008059C">  0x7008059C:  </span>700818BF     DC.W       <a href="#GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler</a>
+<span id="A700805A0">  0x700805A0:  </span>700818C1     DC.W       <a href="#GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler</a>
+<span id="A700805A4">  0x700805A4:  </span>700818C3     DC.W       <a href="#GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler</a>
+<span id="A700805A8">  0x700805A8:  </span>700818C5     DC.W       <a href="#GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler</a>
+<span id="A700805AC">  0x700805AC:  </span>700818C7     DC.W       <a href="#GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler</a>
+<span id="A700805B0">  0x700805B0:  </span>700818C9     DC.W       <a href="#GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler</a>
+<span id="A700805B4">  0x700805B4:  </span>700818CB     DC.W       <a href="#GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler</a>
+<span id="A700805B8">  0x700805B8:  </span>700818CD     DC.W       <a href="#GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler</a>
+<span id="A700805BC">  0x700805BC:  </span>700818CF     DC.W       <a href="#GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler</a>
+<span id="A700805C0">  0x700805C0:  </span>700818D1     DC.W       <a href="#GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler</a>
+<span id="A700805C4">  0x700805C4:  </span>700818D3     DC.W       <a href="#GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler</a>
+<span id="A700805C8">  0x700805C8:  </span>700818D5     DC.W       <a href="#GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler</a>
+<span id="A700805CC">  0x700805CC:  </span>700818D7     DC.W       <a href="#GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler</a>
+<span id="A700805D0">  0x700805D0:  </span>700818D9     DC.W       <a href="#I2C1_EV_IRQHandler">I2C1_EV_IRQHandler</a>
+<span id="A700805D4">  0x700805D4:  </span>700818DB     DC.W       <a href="#I2C1_ER_IRQHandler">I2C1_ER_IRQHandler</a>
+<span id="A700805D8">  0x700805D8:  </span>700818DD     DC.W       <a href="#I2C2_EV_IRQHandler">I2C2_EV_IRQHandler</a>
+<span id="A700805DC">  0x700805DC:  </span>700818DF     DC.W       <a href="#I2C2_ER_IRQHandler">I2C2_ER_IRQHandler</a>
+<span id="A700805E0">  0x700805E0:  </span>700818E1     DC.W       <a href="#I2C3_EV_IRQHandler">I2C3_EV_IRQHandler</a>
+<span id="A700805E4">  0x700805E4:  </span>700818E3     DC.W       <a href="#I2C3_ER_IRQHandler">I2C3_ER_IRQHandler</a>
+<span id="A700805E8">  0x700805E8:  </span>700818E5     DC.W       <a href="#I2C4_EV_IRQHandler">I2C4_EV_IRQHandler</a>
+<span id="A700805EC">  0x700805EC:  </span>700818E7     DC.W       <a href="#I2C4_ER_IRQHandler">I2C4_ER_IRQHandler</a>
+<span id="A700805F0">  0x700805F0:  </span>700818E9     DC.W       <a href="#I3C1_EV_IRQHandler">I3C1_EV_IRQHandler</a>
+<span id="A700805F4">  0x700805F4:  </span>700818EB     DC.W       <a href="#I3C1_ER_IRQHandler">I3C1_ER_IRQHandler</a>
+<span id="A700805F8">  0x700805F8:  </span>700818ED     DC.W       <a href="#I3C2_EV_IRQHandler">I3C2_EV_IRQHandler</a>
+<span id="A700805FC">  0x700805FC:  </span>700818EF     DC.W       <a href="#I3C2_ER_IRQHandler">I3C2_ER_IRQHandler</a>
+<span id="A70080600">  0x70080600:  </span>700818F1     DC.W       <a href="#TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler</a>
+<span id="A70080604">  0x70080604:  </span>700818F3     DC.W       <a href="#TIM1_UP_IRQHandler">TIM1_UP_IRQHandler</a>
+<span id="A70080608">  0x70080608:  </span>700818F5     DC.W       <a href="#TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler</a>
+<span id="A7008060C">  0x7008060C:  </span>700818F7     DC.W       <a href="#TIM1_CC_IRQHandler">TIM1_CC_IRQHandler</a>
+<span id="A70080610">  0x70080610:  </span>700818F9     DC.W       <a href="#TIM2_IRQHandler">TIM2_IRQHandler</a>
+<span id="A70080614">  0x70080614:  </span>700818FB     DC.W       <a href="#TIM3_IRQHandler">TIM3_IRQHandler</a>
+<span id="A70080618">  0x70080618:  </span>700818FD     DC.W       <a href="#TIM4_IRQHandler">TIM4_IRQHandler</a>
+<span id="A7008061C">  0x7008061C:  </span>700818FF     DC.W       <a href="#TIM5_IRQHandler">TIM5_IRQHandler</a>
+<span id="A70080620">  0x70080620:  </span>70081901     DC.W       <a href="#TIM6_IRQHandler">TIM6_IRQHandler</a>
+<span id="A70080624">  0x70080624:  </span>70081903     DC.W       <a href="#TIM7_IRQHandler">TIM7_IRQHandler</a>
+<span id="A70080628">  0x70080628:  </span>70081905     DC.W       <a href="#TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler</a>
+<span id="A7008062C">  0x7008062C:  </span>70081907     DC.W       <a href="#TIM8_UP_IRQHandler">TIM8_UP_IRQHandler</a>
+<span id="A70080630">  0x70080630:  </span>70081909     DC.W       <a href="#TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler</a>
+<span id="A70080634">  0x70080634:  </span>7008190B     DC.W       <a href="#TIM8_CC_IRQHandler">TIM8_CC_IRQHandler</a>
+<span id="A70080638">  0x70080638:  </span>7008190D     DC.W       <a href="#TIM9_IRQHandler">TIM9_IRQHandler</a>
+<span id="A7008063C">  0x7008063C:  </span>7008190F     DC.W       <a href="#TIM10_IRQHandler">TIM10_IRQHandler</a>
+<span id="A70080640">  0x70080640:  </span>70081911     DC.W       <a href="#TIM11_IRQHandler">TIM11_IRQHandler</a>
+<span id="A70080644">  0x70080644:  </span>70081913     DC.W       <a href="#TIM12_IRQHandler">TIM12_IRQHandler</a>
+<span id="A70080648">  0x70080648:  </span>70081915     DC.W       <a href="#TIM13_IRQHandler">TIM13_IRQHandler</a>
+<span id="A7008064C">  0x7008064C:  </span>70081917     DC.W       <a href="#TIM14_IRQHandler">TIM14_IRQHandler</a>
+<span id="A70080650">  0x70080650:  </span>70081919     DC.W       <a href="#TIM15_IRQHandler">TIM15_IRQHandler</a>
+<span id="A70080654">  0x70080654:  </span>7008191B     DC.W       <a href="#TIM16_IRQHandler">TIM16_IRQHandler</a>
+<span id="A70080658">  0x70080658:  </span>7008191D     DC.W       <a href="#TIM17_IRQHandler">TIM17_IRQHandler</a>
+<span id="A7008065C">  0x7008065C:  </span>7008191F     DC.W       <a href="#TIM18_IRQHandler">TIM18_IRQHandler</a>
+<span id="A70080660">  0x70080660:  </span>70081921     DC.W       <a href="#LPTIM1_IRQHandler">LPTIM1_IRQHandler</a>
+<span id="A70080664">  0x70080664:  </span>70081923     DC.W       <a href="#LPTIM2_IRQHandler">LPTIM2_IRQHandler</a>
+<span id="A70080668">  0x70080668:  </span>70081925     DC.W       <a href="#LPTIM3_IRQHandler">LPTIM3_IRQHandler</a>
+<span id="A7008066C">  0x7008066C:  </span>70081927     DC.W       <a href="#LPTIM4_IRQHandler">LPTIM4_IRQHandler</a>
+<span id="A70080670">  0x70080670:  </span>70081929     DC.W       <a href="#LPTIM5_IRQHandler">LPTIM5_IRQHandler</a>
+<span id="A70080674">  0x70080674:  </span>7008192B     DC.W       <a href="#ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler</a>
+<span id="A70080678">  0x70080678:  </span>7008192D     DC.W       <a href="#MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler</a>
+<span id="A7008067C">  0x7008067C:  </span>7008192F     DC.W       <a href="#MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler</a>
+<span id="A70080680">  0x70080680:  </span>70081931     DC.W       <a href="#MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler</a>
+<span id="A70080684">  0x70080684:  </span>70081933     DC.W       <a href="#MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler</a>
+<span id="A70080688">  0x70080688:  </span>70081935     DC.W       <a href="#MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler</a>
+<span id="A7008068C">  0x7008068C:  </span>70081937     DC.W       <a href="#MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler</a>
+<span id="A70080690">  0x70080690:  </span>70081939     DC.W       <a href="#SAI1_A_IRQHandler">SAI1_A_IRQHandler</a>
+<span id="A70080694">  0x70080694:  </span>7008193B     DC.W       <a href="#SAI1_B_IRQHandler">SAI1_B_IRQHandler</a>
+<span id="A70080698">  0x70080698:  </span>7008193D     DC.W       <a href="#SAI2_A_IRQHandler">SAI2_A_IRQHandler</a>
+<span id="A7008069C">  0x7008069C:  </span>7008193F     DC.W       <a href="#SAI2_B_IRQHandler">SAI2_B_IRQHandler</a>
+<span id="A700806A0">  0x700806A0:  </span>70081941     DC.W       <a href="#SPDIFRX_IRQHandler">SPDIFRX_IRQHandler</a>
+<span id="A700806A4">  0x700806A4:  </span>70081943     DC.W       <a href="#SPI1_IRQHandler">SPI1_IRQHandler</a>
+<span id="A700806A8">  0x700806A8:  </span>70081945     DC.W       <a href="#SPI2_IRQHandler">SPI2_IRQHandler</a>
+<span id="A700806AC">  0x700806AC:  </span>70081947     DC.W       <a href="#SPI3_IRQHandler">SPI3_IRQHandler</a>
+<span id="A700806B0">  0x700806B0:  </span>70081949     DC.W       <a href="#SPI4_IRQHandler">SPI4_IRQHandler</a>
+<span id="A700806B4">  0x700806B4:  </span>7008194B     DC.W       <a href="#SPI5_IRQHandler">SPI5_IRQHandler</a>
+<span id="A700806B8">  0x700806B8:  </span>7008194D     DC.W       <a href="#SPI6_IRQHandler">SPI6_IRQHandler</a>
+<span id="A700806BC">  0x700806BC:  </span>7008194F     DC.W       <a href="#USART1_IRQHandler">USART1_IRQHandler</a>
+<span id="A700806C0">  0x700806C0:  </span>70081951     DC.W       <a href="#USART2_IRQHandler">USART2_IRQHandler</a>
+<span id="A700806C4">  0x700806C4:  </span>70081953     DC.W       <a href="#USART3_IRQHandler">USART3_IRQHandler</a>
+<span id="A700806C8">  0x700806C8:  </span>70081955     DC.W       <a href="#UART4_IRQHandler">UART4_IRQHandler</a>
+<span id="A700806CC">  0x700806CC:  </span>70081957     DC.W       <a href="#UART5_IRQHandler">UART5_IRQHandler</a>
+<span id="A700806D0">  0x700806D0:  </span>70081959     DC.W       <a href="#USART6_IRQHandler">USART6_IRQHandler</a>
+<span id="A700806D4">  0x700806D4:  </span>7008195B     DC.W       <a href="#UART7_IRQHandler">UART7_IRQHandler</a>
+<span id="A700806D8">  0x700806D8:  </span>7008195D     DC.W       <a href="#UART8_IRQHandler">UART8_IRQHandler</a>
+<span id="A700806DC">  0x700806DC:  </span>7008195F     DC.W       <a href="#UART9_IRQHandler">UART9_IRQHandler</a>
+<span id="A700806E0">  0x700806E0:  </span>70081961     DC.W       <a href="#USART10_IRQHandler">USART10_IRQHandler</a>
+<span id="A700806E4">  0x700806E4:  </span>70081963     DC.W       <a href="#LPUART1_IRQHandler">LPUART1_IRQHandler</a>
+<span id="A700806E8">  0x700806E8:  </span>70081965     DC.W       <a href="#XSPI1_IRQHandler">XSPI1_IRQHandler</a>
+<span id="A700806EC">  0x700806EC:  </span>70081967     DC.W       <a href="#XSPI2_IRQHandler">XSPI2_IRQHandler</a>
+<span id="A700806F0">  0x700806F0:  </span>70081969     DC.W       <a href="#XSPI3_IRQHandler">XSPI3_IRQHandler</a>
+<span id="A700806F4">  0x700806F4:  </span>7008196B     DC.W       <a href="#FMC_IRQHandler">FMC_IRQHandler</a>
+<span id="A700806F8">  0x700806F8:  </span>7008196D     DC.W       <a href="#SDMMC1_IRQHandler">SDMMC1_IRQHandler</a>
+<span id="A700806FC">  0x700806FC:  </span>7008196F     DC.W       <a href="#SDMMC2_IRQHandler">SDMMC2_IRQHandler</a>
+<span id="A70080700">  0x70080700:  </span>70081971     DC.W       <a href="#UCPD1_IRQHandler">UCPD1_IRQHandler</a>
+<span id="A70080704">  0x70080704:  </span>70081973     DC.W       <a href="#USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler</a>
+<span id="A70080708">  0x70080708:  </span>70081975     DC.W       <a href="#USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler</a>
+<span id="A7008070C">  0x7008070C:  </span>70081977     DC.W       <a href="#ETH1_IRQHandler">ETH1_IRQHandler</a>
+<span id="A70080710">  0x70080710:  </span>70081979     DC.W       <a href="#FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler</a>
+<span id="A70080714">  0x70080714:  </span>7008197B     DC.W       <a href="#FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler</a>
+<span id="A70080718">  0x70080718:  </span>7008197D     DC.W       <a href="#FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler</a>
+<span id="A7008071C">  0x7008071C:  </span>7008197F     DC.W       <a href="#FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler</a>
+<span id="A70080720">  0x70080720:  </span>70081981     DC.W       <a href="#FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler</a>
+<span id="A70080724">  0x70080724:  </span>70081983     DC.W       <a href="#FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler</a>
+<span id="A70080728">  0x70080728:  </span>70081985     DC.W       <a href="#FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler</a>
+<span id="A7008072C">  0x7008072C:  </span>70081987     DC.W       <a href="#MDIOS_IRQHandler">MDIOS_IRQHandler</a>
+<span id="A70080730">  0x70080730:  </span>70081989     DC.W       <a href="#DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler</a>
+<span id="A70080734">  0x70080734:  </span>7008198B     DC.W       <a href="#WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler</a>
+<span id="A70080738">  0x70080738:  </span>7008198D     DC.W       <a href="#CTI_INT0_IRQHandler">CTI_INT0_IRQHandler</a>
+<span id="A7008073C">  0x7008073C:  </span>7008198F     DC.W       <a href="#CTI_INT1_IRQHandler">CTI_INT1_IRQHandler</a>
+<span id="A70080740">  0x70080740:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080741">  0x70080741:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080742">  0x70080742:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080743">  0x70080743:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080744">  0x70080744:  </span>70081991     DC.W       <a href="#LTDC_UP_IRQHandler">LTDC_UP_IRQHandler</a>
+<span id="A70080748">  0x70080748:  </span>70081993     DC.W       <a href="#LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SysTick_Handler from blto_App_lto.o, size=8, align=4">Section .text.SysTick_Handler from blto_App_lto.o, size=8, align=4</h2>
+
+<pre>
+<br/><span id="SysTick_Handler">SysTick_Handler:</span>
+<span id="_vectors_end">_vectors_end:</span>
+<span id="A7008074C">  0x7008074C:  </span>B580         PUSH       123R7, LR}
+<span id="A7008074E">  0x7008074E:  </span>F001 F803    BL         <a href="#HAL_IncTick">HAL_IncTick</a>              ; 0x70081758
+<span id="A70080752">  0x70080752:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SystemInit from blto_App_lto.o, size=104, align=4">Section .text.SystemInit from blto_App_lto.o, size=104, align=4</h2>
+
+<pre>
+<br/><span id="SystemInit">SystemInit:</span>
+<span id="A70080754">  0x70080754:  </span>B580         PUSH       123R7, LR}
+<span id="A70080756">  0x70080756:  </span>F000 F831    BL         <a href="#TZ_SAU_Setup">TZ_SAU_Setup</a>             ; 0x700807BC
+<span id="A7008075A">  0x7008075A:  </span>F240 4000    MOVW       R0, #0x0400              ; 0x70080400 = g_pfnVectors
+<span id="A7008075E">  0x7008075E:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x70080400 = g_pfnVectors
+<span id="A70080762">  0x70080762:  </span>F64E 5108    MOVW       R1, #0xED08
+<span id="A70080766">  0x70080766:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A7008076A">  0x7008076A:  </span>6008         STR        R0, [R1]
+<span id="A7008076C">  0x7008076C:  </span>F648 2278    MOVW       R2, #0x8A78
+<span id="A70080770">  0x70080770:  </span>F2C5 6202    MOVT       R2, #0x5602
+<span id="A70080774">  0x70080774:  </span>2001         MOVS       R0, #1
+<span id="A70080776">  0x70080776:  </span>6010         STR        R0, [R2]
+<span id="A70080778">  0x70080778:  </span>F248 2278    MOVW       R2, #0x8278
+<span id="A7008077C">  0x7008077C:  </span>F2C5 6202    MOVT       R2, #0x5602
+<span id="A70080780">  0x70080780:  </span>6812         LDR        R2, [R2]
+<span id="A70080782">  0x70080782:  </span>680A         LDR        R2, [R1]
+<span id="A70080784">  0x70080784:  </span>F248 0110    MOVW       R1, #0x8010
+<span id="A70080788">  0x70080788:  </span>F2C5 6100    MOVT       R1, #0x5600
+<span id="A7008078C">  0x7008078C:  </span>600A         STR        R2, [R1]
+<span id="A7008078E">  0x7008078E:  </span>6809         LDR        R1, [R1]
+<span id="A70080790">  0x70080790:  </span>F249 2178    MOVW       R1, #0x9278
+<span id="A70080794">  0x70080794:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080798">  0x70080798:  </span>6008         STR        R0, [R1]
+<span id="A7008079A">  0x7008079A:  </span>F64E 5188    MOVW       R1, #0xED88
+<span id="A7008079E">  0x7008079E:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807A2">  0x700807A2:  </span>6808         LDR        R0, [R1]
+<span id="A700807A4">  0x700807A4:  </span>F440 0070    ORR        R0, R0, #0xF00000
+<span id="A700807A8">  0x700807A8:  </span>6008         STR        R0, [R1]
+<span id="A700807AA">  0x700807AA:  </span>F64E 5188    MOVW       R1, #0xED88
+<span id="A700807AE">  0x700807AE:  </span>F2CE 0102    MOVT       R1, #0xE002
+<span id="A700807B2">  0x700807B2:  </span>6808         LDR        R0, [R1]
+<span id="A700807B4">  0x700807B4:  </span>F440 0070    ORR        R0, R0, #0xF00000
+<span id="A700807B8">  0x700807B8:  </span>6008         STR        R0, [R1]
+<span id="A700807BA">  0x700807BA:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.TZ_SAU_Setup from blto_App_lto.o, size=108, align=4">Section .text.TZ_SAU_Setup from blto_App_lto.o, size=108, align=4</h2>
+
+<pre>
+<br/><span id="TZ_SAU_Setup">TZ_SAU_Setup:</span>
+<span id="A700807BC">  0x700807BC:  </span>F64E 518C    MOVW       R1, #0xED8C
+<span id="A700807C0">  0x700807C0:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807C4">  0x700807C4:  </span>6808         LDR        R0, [R1]
+<span id="A700807C6">  0x700807C6:  </span>F440 6040    ORR        R0, R0, #0x0C00
+<span id="A700807CA">  0x700807CA:  </span>6008         STR        R0, [R1]
+<span id="A700807CC">  0x700807CC:  </span>F64E 7134    MOVW       R1, #0xEF34
+<span id="A700807D0">  0x700807D0:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807D4">  0x700807D4:  </span>6808         LDR        R0, [R1]
+<span id="A700807D6">  0x700807D6:  </span>2204         MOVS       R2, #4
+<span id="A700807D8">  0x700807D8:  </span>F362 609C    BFI        R0, R2, #26, #3
+<span id="A700807DC">  0x700807DC:  </span>6008         STR        R0, [R1]
+<span id="A700807DE">  0x700807DE:  </span>F24E 3180    MOVW       R1, #0xE380
+<span id="A700807E2">  0x700807E2:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807E6">  0x700807E6:  </span>2000         MOVS       R0, #0
+<span id="A700807E8">  0x700807E8:  </span>6008         STR        R0, [R1]
+<span id="A700807EA">  0x700807EA:  </span>F24E 3184    MOVW       R1, #0xE384
+<span id="A700807EE">  0x700807EE:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807F2">  0x700807F2:  </span>6008         STR        R0, [R1]
+<span id="A700807F4">  0x700807F4:  </span>F24E 3188    MOVW       R1, #0xE388
+<span id="A700807F8">  0x700807F8:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A700807FC">  0x700807FC:  </span>6008         STR        R0, [R1]
+<span id="A700807FE">  0x700807FE:  </span>F24E 318C    MOVW       R1, #0xE38C
+<span id="A70080802">  0x70080802:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A70080806">  0x70080806:  </span>6008         STR        R0, [R1]
+<span id="A70080808">  0x70080808:  </span>F24E 3190    MOVW       R1, #0xE390
+<span id="A7008080C">  0x7008080C:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A70080810">  0x70080810:  </span>6008         STR        R0, [R1]
+<span id="A70080812">  0x70080812:  </span>F24E 3194    MOVW       R1, #0xE394
+<span id="A70080816">  0x70080816:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A7008081A">  0x7008081A:  </span>6008         STR        R0, [R1]
+<span id="A7008081C">  0x7008081C:  </span>F24E 3198    MOVW       R1, #0xE398
+<span id="A70080820">  0x70080820:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A70080824">  0x70080824:  </span>6008         STR        R0, [R1]
+<span id="A70080826">  0x70080826:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=828, align=4">Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=828, align=4</h2>
+
+<pre>
+<br/><span id="SystemCoreClockUpdate">SystemCoreClockUpdate:</span>
+<span id="A70080828">  0x70080828:  </span>B08E         SUB        SP, SP, #56
+<span id="A7008082A">  0x7008082A:  </span>2000         MOVS       R0, #0
+<span id="A7008082C">  0x7008082C:  </span>900D         STR        R0, [SP, #52]
+<span id="A7008082E">  0x7008082E:  </span>900C         STR        R0, [SP, #48]
+<span id="A70080830">  0x70080830:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080832">  0x70080832:  </span>900A         STR        R0, [SP, #40]
+<span id="A70080834">  0x70080834:  </span>9009         STR        R0, [SP, #36]
+<span id="A70080836">  0x70080836:  </span>9008         STR        R0, [SP, #32]
+<span id="A70080838">  0x70080838:  </span>F248 0020    MOVW       R0, #0x8020
+<span id="A7008083C">  0x7008083C:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080840">  0x70080840:  </span>6800         LDR        R0, [R0]
+<span id="A70080842">  0x70080842:  </span>F400 1040    AND        R0, R0, #0x300000
+<span id="A70080846">  0x70080846:  </span>4601         MOV        R1, R0
+<span id="A70080848">  0x70080848:  </span>9102         STR        R1, [SP, #8]
+<span id="A7008084A">  0x7008084A:  </span>B160         CBZ        R0, .L1                  ; 0x70080866
+<span id="A7008084C">  0x7008084C:  </span>9802         LDR        R0, [SP, #8]
+<span id="A7008084E">  0x7008084E:  </span>F5B0 1F80    CMP.W      R0, #0x100000
+<span id="A70080852">  0x70080852:  </span>D016         BEQ        46L2                      ; 0x70080882
+<span id="A70080854">  0x70080854:  </span>9802         LDR        R0, [SP, #8]
+<span id="A70080856">  0x70080856:  </span>F5B0 1F00    CMP.W      R0, #0x200000
+<span id="A7008085A">  0x7008085A:  </span>D026         BEQ        46L5                      ; 0x700808AA
+<span id="A7008085C">  0x7008085C:  </span>9802         LDR        R0, [SP, #8]
+<span id="A7008085E">  0x7008085E:  </span>F5B0 1F40    CMP.W      R0, #0x300000
+<span id="A70080862">  0x70080862:  </span>D028         BEQ        46L6                      ; 0x700808B6
+<span id="A70080864">  0x70080864:  </span>E174         B          46L23                     ; 0x70080B50
+<br/>.L1:
+<span id="A70080866">  0x70080866:  </span>F248 0048    MOVW       R0, #0x8048
+<span id="A7008086A">  0x7008086A:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008086E">  0x7008086E:  </span>6800         LDR        R0, [R0]
+<span id="A70080870">  0x70080870:  </span>F3C0 11C1    UBFX       R1, R0, #7, #2
+<span id="A70080874">  0x70080874:  </span>F249 0000    MOVW       R0, #0x9000
+<span id="A70080878">  0x70080878:  </span>F2C0 30D0    MOVT       R0, #0x03D0
+<span id="A7008087C">  0x7008087C:  </span>40C8         LSRS       R0, R1
+<span id="A7008087E">  0x7008087E:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080880">  0x70080880:  </span>E166         B          46L23                     ; 0x70080B50
+<br/>.L2:
+<span id="A70080882">  0x70080882:  </span>F248 0044    MOVW       R0, #0x8044
+<span id="A70080886">  0x70080886:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008088A">  0x7008088A:  </span>6800         LDR        R0, [R0]
+<span id="A7008088C">  0x7008088C:  </span>0580         LSLS       R0, R0, #22
+<span id="A7008088E">  0x7008088E:  </span>2800         CMP        R0, #0
+<span id="A70080890">  0x70080890:  </span>D405         BMI        46L3                      ; 0x7008089E
+<span id="A70080892">  0x70080892:  </span>F640 1000    MOVW       R0, #0x0900
+<span id="A70080896">  0x70080896:  </span>F2C0 003D    MOVT       R0, #61
+<span id="A7008089A">  0x7008089A:  </span>900D         STR        R0, [SP, #52]
+<span id="A7008089C">  0x7008089C:  </span>E004         B          46L4                      ; 0x700808A8
+<br/>.L3:
+<span id="A7008089E">  0x7008089E:  </span>F242 4000    MOVW       R0, #0x2400
+<span id="A700808A2">  0x700808A2:  </span>F2C0 00F4    MOVT       R0, #244
+<span id="A700808A6">  0x700808A6:  </span>900D         STR        R0, [SP, #52]
+<br/>.L4:
+<span id="A700808A8">  0x700808A8:  </span>E152         B          46L23                     ; 0x70080B50
+<br/>.L5:
+<span id="A700808AA">  0x700808AA:  </span>F646 4000    MOVW       R0, #0x6C00
+<span id="A700808AE">  0x700808AE:  </span>F2C0 20DC    MOVT       R0, #0x02DC
+<span id="A700808B2">  0x700808B2:  </span>900D         STR        R0, [SP, #52]
+<span id="A700808B4">  0x700808B4:  </span>E14C         B          46L23                     ; 0x70080B50
+<br/>.L6:
+<span id="A700808B6">  0x700808B6:  </span>F248 00C4    MOVW       R0, #0x80C4
+<span id="A700808BA">  0x700808BA:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700808BE">  0x700808BE:  </span>6800         LDR        R0, [R0]
+<span id="A700808C0">  0x700808C0:  </span>F000 5040    AND        R0, R0, #0x30000000
+<span id="A700808C4">  0x700808C4:  </span>4601         MOV        R1, R0
+<span id="A700808C6">  0x700808C6:  </span>9101         STR        R1, [SP, #4]
+<span id="A700808C8">  0x700808C8:  </span>B140         CBZ        R0, .L7                  ; 0x700808DC
+<span id="A700808CA">  0x700808CA:  </span>9801         LDR        R0, [SP, #4]
+<span id="A700808CC">  0x700808CC:  </span>F1B0 5F80    CMP.W      R0, #0x10000000
+<span id="A700808D0">  0x700808D0:  </span>D033         BEQ        46L9                      ; 0x7008093A
+<span id="A700808D2">  0x700808D2:  </span>9801         LDR        R0, [SP, #4]
+<span id="A700808D4">  0x700808D4:  </span>F1B0 5F00    CMP.W      R0, #0x20000000
+<span id="A700808D8">  0x700808D8:  </span>D05E         BEQ        46L11                     ; 0x70080998
+<span id="A700808DA">  0x700808DA:  </span>E08C         B          46L13                     ; 0x700809F6
+<br/>.L7:
+<span id="A700808DC">  0x700808DC:  </span>F248 0080    MOVW       R0, #0x8080
+<span id="A700808E0">  0x700808E0:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700808E4">  0x700808E4:  </span>6800         LDR        R0, [R0]
+<span id="A700808E6">  0x700808E6:  </span>9007         STR        R0, [SP, #28]
+<span id="A700808E8">  0x700808E8:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700808EA">  0x700808EA:  </span>F000 40E0    AND        R0, R0, #0x70000000
+<span id="A700808EE">  0x700808EE:  </span>9006         STR        R0, [SP, #24]
+<span id="A700808F0">  0x700808F0:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700808F2">  0x700808F2:  </span>F000 6000    AND        R0, R0, #0x08000000
+<span id="A700808F6">  0x700808F6:  </span>9005         STR        R0, [SP, #20]
+<span id="A700808F8">  0x700808F8:  </span>9805         LDR        R0, [SP, #20]
+<span id="A700808FA">  0x700808FA:  </span>B9E8         CBNZ       R0, .L8                  ; 0x70080938
+<span id="A700808FC">  0x700808FC:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700808FE">  0x700808FE:  </span>F3C0 5005    UBFX       R0, R0, #20, #6
+<span id="A70080902">  0x70080902:  </span>900C         STR        R0, [SP, #48]
+<span id="A70080904">  0x70080904:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080906">  0x70080906:  </span>F3C0 200B    UBFX       R0, R0, #8, #12
+<span id="A7008090A">  0x7008090A:  </span>900B         STR        R0, [SP, #44]
+<span id="A7008090C">  0x7008090C:  </span>F248 0084    MOVW       R0, #0x8084
+<span id="A70080910">  0x70080910:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080914">  0x70080914:  </span>6800         LDR        R0, [R0]
+<span id="A70080916">  0x70080916:  </span>F020 407F    BIC        R0, R0, #0xFF000000
+<span id="A7008091A">  0x7008091A:  </span>900A         STR        R0, [SP, #40]
+<span id="A7008091C">  0x7008091C:  </span>F248 0088    MOVW       R0, #0x8088
+<span id="A70080920">  0x70080920:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080924">  0x70080924:  </span>6800         LDR        R0, [R0]
+<span id="A70080926">  0x70080926:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080928">  0x70080928:  </span>9807         LDR        R0, [SP, #28]
+<span id="A7008092A">  0x7008092A:  </span>F3C0 60C2    UBFX       R0, R0, #27, #3
+<span id="A7008092E">  0x7008092E:  </span>9009         STR        R0, [SP, #36]
+<span id="A70080930">  0x70080930:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080932">  0x70080932:  </span>F3C0 6002    UBFX       R0, R0, #24, #3
+<span id="A70080936">  0x70080936:  </span>9008         STR        R0, [SP, #32]
+<br/>.L8:
+<span id="A70080938">  0x70080938:  </span>E08B         B          46L14                     ; 0x70080A52
+<br/>.L9:
+<span id="A7008093A">  0x7008093A:  </span>F248 0090    MOVW       R0, #0x8090
+<span id="A7008093E">  0x7008093E:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080942">  0x70080942:  </span>6800         LDR        R0, [R0]
+<span id="A70080944">  0x70080944:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080946">  0x70080946:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080948">  0x70080948:  </span>F000 40E0    AND        R0, R0, #0x70000000
+<span id="A7008094C">  0x7008094C:  </span>9006         STR        R0, [SP, #24]
+<span id="A7008094E">  0x7008094E:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080950">  0x70080950:  </span>F000 6000    AND        R0, R0, #0x08000000
+<span id="A70080954">  0x70080954:  </span>9005         STR        R0, [SP, #20]
+<span id="A70080956">  0x70080956:  </span>9805         LDR        R0, [SP, #20]
+<span id="A70080958">  0x70080958:  </span>B9E8         CBNZ       R0, .L10                 ; 0x70080996
+<span id="A7008095A">  0x7008095A:  </span>9807         LDR        R0, [SP, #28]
+<span id="A7008095C">  0x7008095C:  </span>F3C0 5005    UBFX       R0, R0, #20, #6
+<span id="A70080960">  0x70080960:  </span>900C         STR        R0, [SP, #48]
+<span id="A70080962">  0x70080962:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080964">  0x70080964:  </span>F3C0 200B    UBFX       R0, R0, #8, #12
+<span id="A70080968">  0x70080968:  </span>900B         STR        R0, [SP, #44]
+<span id="A7008096A">  0x7008096A:  </span>F248 0094    MOVW       R0, #0x8094
+<span id="A7008096E">  0x7008096E:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080972">  0x70080972:  </span>6800         LDR        R0, [R0]
+<span id="A70080974">  0x70080974:  </span>F020 407F    BIC        R0, R0, #0xFF000000
+<span id="A70080978">  0x70080978:  </span>900A         STR        R0, [SP, #40]
+<span id="A7008097A">  0x7008097A:  </span>F248 0098    MOVW       R0, #0x8098
+<span id="A7008097E">  0x7008097E:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080982">  0x70080982:  </span>6800         LDR        R0, [R0]
+<span id="A70080984">  0x70080984:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080986">  0x70080986:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080988">  0x70080988:  </span>F3C0 60C2    UBFX       R0, R0, #27, #3
+<span id="A7008098C">  0x7008098C:  </span>9009         STR        R0, [SP, #36]
+<span id="A7008098E">  0x7008098E:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080990">  0x70080990:  </span>F3C0 6002    UBFX       R0, R0, #24, #3
+<span id="A70080994">  0x70080994:  </span>9008         STR        R0, [SP, #32]
+<br/>.L10:
+<span id="A70080996">  0x70080996:  </span>E05C         B          46L14                     ; 0x70080A52
+<br/>.L11:
+<span id="A70080998">  0x70080998:  </span>F248 00A0    MOVW       R0, #0x80A0
+<span id="A7008099C">  0x7008099C:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700809A0">  0x700809A0:  </span>6800         LDR        R0, [R0]
+<span id="A700809A2">  0x700809A2:  </span>9007         STR        R0, [SP, #28]
+<span id="A700809A4">  0x700809A4:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809A6">  0x700809A6:  </span>F000 40E0    AND        R0, R0, #0x70000000
+<span id="A700809AA">  0x700809AA:  </span>9006         STR        R0, [SP, #24]
+<span id="A700809AC">  0x700809AC:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809AE">  0x700809AE:  </span>F000 6000    AND        R0, R0, #0x08000000
+<span id="A700809B2">  0x700809B2:  </span>9005         STR        R0, [SP, #20]
+<span id="A700809B4">  0x700809B4:  </span>9805         LDR        R0, [SP, #20]
+<span id="A700809B6">  0x700809B6:  </span>B9E8         CBNZ       R0, .L12                 ; 0x700809F4
+<span id="A700809B8">  0x700809B8:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809BA">  0x700809BA:  </span>F3C0 5005    UBFX       R0, R0, #20, #6
+<span id="A700809BE">  0x700809BE:  </span>900C         STR        R0, [SP, #48]
+<span id="A700809C0">  0x700809C0:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809C2">  0x700809C2:  </span>F3C0 200B    UBFX       R0, R0, #8, #12
+<span id="A700809C6">  0x700809C6:  </span>900B         STR        R0, [SP, #44]
+<span id="A700809C8">  0x700809C8:  </span>F248 00A4    MOVW       R0, #0x80A4
+<span id="A700809CC">  0x700809CC:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700809D0">  0x700809D0:  </span>6800         LDR        R0, [R0]
+<span id="A700809D2">  0x700809D2:  </span>F020 407F    BIC        R0, R0, #0xFF000000
+<span id="A700809D6">  0x700809D6:  </span>900A         STR        R0, [SP, #40]
+<span id="A700809D8">  0x700809D8:  </span>F248 00A8    MOVW       R0, #0x80A8
+<span id="A700809DC">  0x700809DC:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700809E0">  0x700809E0:  </span>6800         LDR        R0, [R0]
+<span id="A700809E2">  0x700809E2:  </span>9007         STR        R0, [SP, #28]
+<span id="A700809E4">  0x700809E4:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809E6">  0x700809E6:  </span>F3C0 60C2    UBFX       R0, R0, #27, #3
+<span id="A700809EA">  0x700809EA:  </span>9009         STR        R0, [SP, #36]
+<span id="A700809EC">  0x700809EC:  </span>9807         LDR        R0, [SP, #28]
+<span id="A700809EE">  0x700809EE:  </span>F3C0 6002    UBFX       R0, R0, #24, #3
+<span id="A700809F2">  0x700809F2:  </span>9008         STR        R0, [SP, #32]
+<br/>.L12:
+<span id="A700809F4">  0x700809F4:  </span>E02D         B          46L14                     ; 0x70080A52
+<br/>.L13:
+<span id="A700809F6">  0x700809F6:  </span>F248 00B0    MOVW       R0, #0x80B0
+<span id="A700809FA">  0x700809FA:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700809FE">  0x700809FE:  </span>6800         LDR        R0, [R0]
+<span id="A70080A00">  0x70080A00:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080A02">  0x70080A02:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A04">  0x70080A04:  </span>F000 40E0    AND        R0, R0, #0x70000000
+<span id="A70080A08">  0x70080A08:  </span>9006         STR        R0, [SP, #24]
+<span id="A70080A0A">  0x70080A0A:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A0C">  0x70080A0C:  </span>F000 6000    AND        R0, R0, #0x08000000
+<span id="A70080A10">  0x70080A10:  </span>9005         STR        R0, [SP, #20]
+<span id="A70080A12">  0x70080A12:  </span>9805         LDR        R0, [SP, #20]
+<span id="A70080A14">  0x70080A14:  </span>B9E8         CBNZ       R0, .L14                 ; 0x70080A52
+<span id="A70080A16">  0x70080A16:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A18">  0x70080A18:  </span>F3C0 5005    UBFX       R0, R0, #20, #6
+<span id="A70080A1C">  0x70080A1C:  </span>900C         STR        R0, [SP, #48]
+<span id="A70080A1E">  0x70080A1E:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A20">  0x70080A20:  </span>F3C0 200B    UBFX       R0, R0, #8, #12
+<span id="A70080A24">  0x70080A24:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080A26">  0x70080A26:  </span>F248 00B4    MOVW       R0, #0x80B4
+<span id="A70080A2A">  0x70080A2A:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080A2E">  0x70080A2E:  </span>6800         LDR        R0, [R0]
+<span id="A70080A30">  0x70080A30:  </span>F020 407F    BIC        R0, R0, #0xFF000000
+<span id="A70080A34">  0x70080A34:  </span>900A         STR        R0, [SP, #40]
+<span id="A70080A36">  0x70080A36:  </span>F248 00B8    MOVW       R0, #0x80B8
+<span id="A70080A3A">  0x70080A3A:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080A3E">  0x70080A3E:  </span>6800         LDR        R0, [R0]
+<span id="A70080A40">  0x70080A40:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080A42">  0x70080A42:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A44">  0x70080A44:  </span>F3C0 60C2    UBFX       R0, R0, #27, #3
+<span id="A70080A48">  0x70080A48:  </span>9009         STR        R0, [SP, #36]
+<span id="A70080A4A">  0x70080A4A:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080A4C">  0x70080A4C:  </span>F3C0 6002    UBFX       R0, R0, #24, #3
+<span id="A70080A50">  0x70080A50:  </span>9008         STR        R0, [SP, #32]
+<br/>.L14:
+<span id="A70080A52">  0x70080A52:  </span>9806         LDR        R0, [SP, #24]
+<span id="A70080A54">  0x70080A54:  </span>9000         STR        R0, [SP, #0]
+<span id="A70080A56">  0x70080A56:  </span>B160         CBZ        R0, .L15                 ; 0x70080A72
+<span id="A70080A58">  0x70080A58:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70080A5A">  0x70080A5A:  </span>F1B0 5F80    CMP.W      R0, #0x10000000
+<span id="A70080A5E">  0x70080A5E:  </span>D016         BEQ        46L16                     ; 0x70080A8E
+<span id="A70080A60">  0x70080A60:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70080A62">  0x70080A62:  </span>F1B0 5F00    CMP.W      R0, #0x20000000
+<span id="A70080A66">  0x70080A66:  </span>D026         BEQ        46L19                     ; 0x70080AB6
+<span id="A70080A68">  0x70080A68:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70080A6A">  0x70080A6A:  </span>F1B0 5F40    CMP.W      R0, #0x30000000
+<span id="A70080A6E">  0x70080A6E:  </span>D028         BEQ        46L20                     ; 0x70080AC2
+<span id="A70080A70">  0x70080A70:  </span>E02D         B          46L21                     ; 0x70080ACE
+<br/>.L15:
+<span id="A70080A72">  0x70080A72:  </span>F248 0048    MOVW       R0, #0x8048
+<span id="A70080A76">  0x70080A76:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080A7A">  0x70080A7A:  </span>6800         LDR        R0, [R0]
+<span id="A70080A7C">  0x70080A7C:  </span>F3C0 11C1    UBFX       R1, R0, #7, #2
+<span id="A70080A80">  0x70080A80:  </span>F249 0000    MOVW       R0, #0x9000
+<span id="A70080A84">  0x70080A84:  </span>F2C0 30D0    MOVT       R0, #0x03D0
+<span id="A70080A88">  0x70080A88:  </span>40C8         LSRS       R0, R1
+<span id="A70080A8A">  0x70080A8A:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080A8C">  0x70080A8C:  </span>E01F         B          46L21                     ; 0x70080ACE
+<br/>.L16:
+<span id="A70080A8E">  0x70080A8E:  </span>F248 0044    MOVW       R0, #0x8044
+<span id="A70080A92">  0x70080A92:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080A96">  0x70080A96:  </span>6800         LDR        R0, [R0]
+<span id="A70080A98">  0x70080A98:  </span>0580         LSLS       R0, R0, #22
+<span id="A70080A9A">  0x70080A9A:  </span>2800         CMP        R0, #0
+<span id="A70080A9C">  0x70080A9C:  </span>D405         BMI        46L17                     ; 0x70080AAA
+<span id="A70080A9E">  0x70080A9E:  </span>F640 1000    MOVW       R0, #0x0900
+<span id="A70080AA2">  0x70080AA2:  </span>F2C0 003D    MOVT       R0, #61
+<span id="A70080AA6">  0x70080AA6:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080AA8">  0x70080AA8:  </span>E004         B          46L18                     ; 0x70080AB4
+<br/>.L17:
+<span id="A70080AAA">  0x70080AAA:  </span>F242 4000    MOVW       R0, #0x2400
+<span id="A70080AAE">  0x70080AAE:  </span>F2C0 00F4    MOVT       R0, #244
+<span id="A70080AB2">  0x70080AB2:  </span>900D         STR        R0, [SP, #52]
+<br/>.L18:
+<span id="A70080AB4">  0x70080AB4:  </span>E00B         B          46L21                     ; 0x70080ACE
+<br/>.L19:
+<span id="A70080AB6">  0x70080AB6:  </span>F646 4000    MOVW       R0, #0x6C00
+<span id="A70080ABA">  0x70080ABA:  </span>F2C0 20DC    MOVT       R0, #0x02DC
+<span id="A70080ABE">  0x70080ABE:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080AC0">  0x70080AC0:  </span>E005         B          46L21                     ; 0x70080ACE
+<br/>.L20:
+<span id="A70080AC2">  0x70080AC2:  </span>F248 0000    MOVW       R0, #0x8000
+<span id="A70080AC6">  0x70080AC6:  </span>F2C0 00BB    MOVT       R0, #187
+<span id="A70080ACA">  0x70080ACA:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080ACC">  0x70080ACC:  </span>E7FF         B          46L21                     ; 0x70080ACE
+<br/>.L21:
+<span id="A70080ACE">  0x70080ACE:  </span>9805         LDR        R0, [SP, #20]
+<span id="A70080AD0">  0x70080AD0:  </span>BB68         CBNZ       R0, .L22                 ; 0x70080B2E
+<span id="A70080AD2">  0x70080AD2:  </span>ED9D 0A0D    VLDR       S0, [SP, #52]
+<span id="A70080AD6">  0x70080AD6:  </span>EEB8 0A40    VCVT.F32.U32 S0, S0
+<span id="A70080ADA">  0x70080ADA:  </span>ED9D 1A0B    VLDR       S2, [SP, #44]
+<span id="A70080ADE">  0x70080ADE:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
+<span id="A70080AE2">  0x70080AE2:  </span>ED9D 2A0A    VLDR       S4, [SP, #40]
+<span id="A70080AE6">  0x70080AE6:  </span>EEB8 2A42    VCVT.F32.U32 S4, S4
+<span id="A70080AEA">  0x70080AEA:  </span>ED9F 3A1D    VLDR       S6, =0x33800000          ; [PC, #116] [0x70080B60]
+<span id="A70080AEE">  0x70080AEE:  </span>EE22 2A03    VMUL.F32   S4, S4, S6
+<span id="A70080AF2">  0x70080AF2:  </span>EE31 1A02    VADD.F32   S2, S2, S4
+<span id="A70080AF6">  0x70080AF6:  </span>EE20 0A01    VMUL.F32   S0, S0, S2
+<span id="A70080AFA">  0x70080AFA:  </span>ED9D 1A0C    VLDR       S2, [SP, #48]
+<span id="A70080AFE">  0x70080AFE:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
+<span id="A70080B02">  0x70080B02:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
+<span id="A70080B06">  0x70080B06:  </span>ED8D 0A03    VSTR       S0, [SP, #12]
+<span id="A70080B0A">  0x70080B0A:  </span>ED9D 0A03    VLDR       S0, [SP, #12]
+<span id="A70080B0E">  0x70080B0E:  </span>ED9D 1A09    VLDR       S2, [SP, #36]
+<span id="A70080B12">  0x70080B12:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
+<span id="A70080B16">  0x70080B16:  </span>ED9D 2A08    VLDR       S4, [SP, #32]
+<span id="A70080B1A">  0x70080B1A:  </span>EEB8 2A42    VCVT.F32.U32 S4, S4
+<span id="A70080B1E">  0x70080B1E:  </span>EE21 1A02    VMUL.F32   S2, S2, S4
+<span id="A70080B22">  0x70080B22:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
+<span id="A70080B26">  0x70080B26:  </span>EEBC 0AC0    VCVT.U32.F32 S0, S0
+<span id="A70080B2A">  0x70080B2A:  </span>ED8D 0A0D    VSTR       S0, [SP, #52]
+<br/>.L22:
+<span id="A70080B2E">  0x70080B2E:  </span>F248 00C4    MOVW       R0, #0x80C4
+<span id="A70080B32">  0x70080B32:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080B36">  0x70080B36:  </span>6800         LDR        R0, [R0]
+<span id="A70080B38">  0x70080B38:  </span>F400 017F    AND        R1, R0, #0xFF0000
+<span id="A70080B3C">  0x70080B3C:  </span>2001         MOVS       R0, #1
+<span id="A70080B3E">  0x70080B3E:  </span>EB00 4011    ADD.W      R0, R0, R1, LSR #16
+<span id="A70080B42">  0x70080B42:  </span>9004         STR        R0, [SP, #16]
+<span id="A70080B44">  0x70080B44:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70080B46">  0x70080B46:  </span>9904         LDR        R1, [SP, #16]
+<span id="A70080B48">  0x70080B48:  </span>FBB0 F0F1    UDIV       R0, R0, R1
+<span id="A70080B4C">  0x70080B4C:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080B4E">  0x70080B4E:  </span>E7FF         B          46L23                     ; 0x70080B50
+<br/>.L23:
+<span id="A70080B50">  0x70080B50:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70080B52">  0x70080B52:  </span>F240 0108    MOVW       R1, #8                   ; 0x34000008 = SystemCoreClock
+<span id="A70080B56">  0x70080B56:  </span>F2C3 4100    MOVT       R1, #0x3400              ; 0x34000008 = SystemCoreClock
+<span id="A70080B5A">  0x70080B5A:  </span>6008         STR        R0, [R1]
+<span id="A70080B5C">  0x70080B5C:  </span>B00E         ADD        SP, SP, #56
+<span id="A70080B5E">  0x70080B5E:  </span>4770         BX         LR
+<span id="A70080B60">  0x70080B60:  </span>33800000     DC.W       0x33800000
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_Init from blto_App_lto.o, size=48, align=4">Section .text.HAL_Init from blto_App_lto.o, size=48, align=4</h2>
+
+<pre>
+<br/><span id="HAL_Init">HAL_Init:</span>
+<span id="A70080B64">  0x70080B64:  </span>B580         PUSH       123R7, LR}
+<span id="A70080B66">  0x70080B66:  </span>B082         SUB        SP, SP, #8
+<span id="A70080B68">  0x70080B68:  </span>2003         MOVS       R0, #3
+<span id="A70080B6A">  0x70080B6A:  </span>F000 FE03    BL         <a href="#HAL_NVIC_SetPriorityGrouping">HAL_NVIC_SetPriorityGrouping</a> ; 0x70081774
+<span id="A70080B6E">  0x70080B6E:  </span>F7FF FE5B    BL         <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>    ; 0x70080828
+<span id="A70080B72">  0x70080B72:  </span>200F         MOVS       R0, #15
+<span id="A70080B74">  0x70080B74:  </span>F000 FDB0    BL         <a href="#HAL_InitTick">HAL_InitTick</a>             ; 0x700816D8
+<span id="A70080B78">  0x70080B78:  </span>B118         CBZ        R0, .L1                  ; 0x70080B82
+<span id="A70080B7A">  0x70080B7A:  </span>2001         MOVS       R0, #1
+<span id="A70080B7C">  0x70080B7C:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<span id="A70080B80">  0x70080B80:  </span>E004         B          46L2                      ; 0x70080B8C
+<br/>.L1:
+<span id="A70080B82">  0x70080B82:  </span>F000 FD97    BL         <a href="#HAL_MspInit">HAL_MspInit</a>              ; 0x700816B4
+<span id="A70080B86">  0x70080B86:  </span>2000         MOVS       R0, #0
+<span id="A70080B88">  0x70080B88:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<br/>.L2:
+<span id="A70080B8C">  0x70080B8C:  </span>F89D 0007    LDRB.W     R0, [SP, #7]
+<span id="A70080B90">  0x70080B90:  </span>B002         ADD        SP, SP, #8
+<span id="A70080B92">  0x70080B92:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.__NVIC_SetPriorityGrouping from blto_App_lto.o, size=60, align=4">Section .text.__NVIC_SetPriorityGrouping from blto_App_lto.o, size=60, align=4</h2>
+
+<pre>
+<br/><span id="__NVIC_SetPriorityGrouping">__NVIC_SetPriorityGrouping:</span>
+<span id="A70080B94">  0x70080B94:  </span>B083         SUB        SP, SP, #12
+<span id="A70080B96">  0x70080B96:  </span>9002         STR        R0, [SP, #8]
+<span id="A70080B98">  0x70080B98:  </span>9802         LDR        R0, [SP, #8]
+<span id="A70080B9A">  0x70080B9A:  </span>F000 0007    AND        R0, R0, #7
+<span id="A70080B9E">  0x70080B9E:  </span>9000         STR        R0, [SP, #0]
+<span id="A70080BA0">  0x70080BA0:  </span>F64E 510C    MOVW       R1, #0xED0C
+<span id="A70080BA4">  0x70080BA4:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A70080BA8">  0x70080BA8:  </span>6808         LDR        R0, [R1]
+<span id="A70080BAA">  0x70080BAA:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080BAC">  0x70080BAC:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080BAE">  0x70080BAE:  </span>F64F 02FF    MOVW       R2, #0xF8FF
+<span id="A70080BB2">  0x70080BB2:  </span>4010         ANDS       R0, R2
+<span id="A70080BB4">  0x70080BB4:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080BB6">  0x70080BB6:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080BB8">  0x70080BB8:  </span>9A00         LDR        R2, [SP, #0]
+<span id="A70080BBA">  0x70080BBA:  </span>EA40 2002    ORR.W      R0, R0, R2, LSL #8
+<span id="A70080BBE">  0x70080BBE:  </span>2200         MOVS       R2, #0
+<span id="A70080BC0">  0x70080BC0:  </span>F2C0 52FA    MOVT       R2, #0x05FA
+<span id="A70080BC4">  0x70080BC4:  </span>4310         ORRS       R0, R2
+<span id="A70080BC6">  0x70080BC6:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080BC8">  0x70080BC8:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080BCA">  0x70080BCA:  </span>6008         STR        R0, [R1]
+<span id="A70080BCC">  0x70080BCC:  </span>B003         ADD        SP, SP, #12
+<span id="A70080BCE">  0x70080BCE:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_NVIC_SetPriority from blto_App_lto.o, size=168, align=4">Section .text.HAL_NVIC_SetPriority from blto_App_lto.o, size=168, align=4</h2>
+
+<pre>
+<br/><span id="HAL_NVIC_SetPriority">HAL_NVIC_SetPriority:</span>
+<span id="A70080BD0">  0x70080BD0:  </span>B580         PUSH       123R7, LR}
+<span id="A70080BD2">  0x70080BD2:  </span>B086         SUB        SP, SP, #24
+<span id="A70080BD4">  0x70080BD4:  </span>F8AD 0016    STRH.W     R0, [SP, #22]
+<span id="A70080BD8">  0x70080BD8:  </span>9104         STR        R1, [SP, #16]
+<span id="A70080BDA">  0x70080BDA:  </span>9203         STR        R2, [SP, #12]
+<span id="A70080BDC">  0x70080BDC:  </span>F9BD 0016    LDRSH.W    R0, [SP, #22]
+<span id="A70080BE0">  0x70080BE0:  </span>F110 0F0C    CMN        R0, #12
+<span id="A70080BE4">  0x70080BE4:  </span>DB04         BLT        46L1                      ; 0x70080BF0
+<span id="A70080BE6">  0x70080BE6:  </span>F9BD 0016    LDRSH.W    R0, [SP, #22]
+<span id="A70080BEA">  0x70080BEA:  </span>3004         ADDS       R0, #4
+<span id="A70080BEC">  0x70080BEC:  </span>B100         CBZ        R0, .L1                  ; 0x70080BF0
+<span id="A70080BEE">  0x70080BEE:  </span>E006         B          46L2                      ; 0x70080BFE
+<br/>.L1:
+<span id="A70080BF0">  0x70080BF0:  </span>F641 1094    MOVW       R0, #0x1994              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080BF4">  0x70080BF4:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080BF8">  0x70080BF8:  </span>21FF         MOVS       R1, #255
+<span id="A70080BFA">  0x70080BFA:  </span>F000 FD55    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L2:
+<span id="A70080BFE">  0x70080BFE:  </span>F000 F83B    BL         <a href="#__NVIC_GetPriorityGrouping">__NVIC_GetPriorityGrouping</a> ; 0x70080C78
+<span id="A70080C02">  0x70080C02:  </span>F000 0007    AND        R0, R0, #7
+<span id="A70080C06">  0x70080C06:  </span>9002         STR        R0, [SP, #8]
+<span id="A70080C08">  0x70080C08:  </span>9802         LDR        R0, [SP, #8]
+<span id="A70080C0A">  0x70080C0A:  </span>2802         CMP        R0, #2
+<span id="A70080C0C">  0x70080C0C:  </span>D802         BHI        46L3                      ; 0x70080C14
+<span id="A70080C0E">  0x70080C0E:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70080C10">  0x70080C10:  </span>B138         CBZ        R0, .L4                  ; 0x70080C22
+<span id="A70080C12">  0x70080C12:  </span>E007         B          46L5                      ; 0x70080C24
+<br/>.L3:
+<span id="A70080C14">  0x70080C14:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70080C16">  0x70080C16:  </span>9902         LDR        R1, [SP, #8]
+<span id="A70080C18">  0x70080C18:  </span>1ECA         SUBS       R2, R1, #3
+<span id="A70080C1A">  0x70080C1A:  </span>2101         MOVS       R1, #1
+<span id="A70080C1C">  0x70080C1C:  </span>4091         LSLS       R1, R2
+<span id="A70080C1E">  0x70080C1E:  </span>4288         CMP        R0, R1
+<span id="A70080C20">  0x70080C20:  </span>D200         BCS        46L5                      ; 0x70080C24
+<br/>.L4:
+<span id="A70080C22">  0x70080C22:  </span>E007         B          46L6                      ; 0x70080C34
+<br/>.L5:
+<span id="A70080C24">  0x70080C24:  </span>F641 1094    MOVW       R0, #0x1994              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080C28">  0x70080C28:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080C2C">  0x70080C2C:  </span>F44F 7181    MOV.W      R1, #0x0102
+<span id="A70080C30">  0x70080C30:  </span>F000 FD3A    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L6:
+<span id="A70080C34">  0x70080C34:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080C36">  0x70080C36:  </span>280F         CMP        R0, #15
+<span id="A70080C38">  0x70080C38:  </span>D808         BHI        46L7                      ; 0x70080C4C
+<span id="A70080C3A">  0x70080C3A:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080C3C">  0x70080C3C:  </span>9902         LDR        R1, [SP, #8]
+<span id="A70080C3E">  0x70080C3E:  </span>F1C1 0207    RSB        R2, R1, #7
+<span id="A70080C42">  0x70080C42:  </span>2101         MOVS       R1, #1
+<span id="A70080C44">  0x70080C44:  </span>4091         LSLS       R1, R2
+<span id="A70080C46">  0x70080C46:  </span>4288         CMP        R0, R1
+<span id="A70080C48">  0x70080C48:  </span>D200         BCS        46L7                      ; 0x70080C4C
+<span id="A70080C4A">  0x70080C4A:  </span>E007         B          46L8                      ; 0x70080C5C
+<br/>.L7:
+<span id="A70080C4C">  0x70080C4C:  </span>F641 1094    MOVW       R0, #0x1994              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080C50">  0x70080C50:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x70081994 = .rodata..L.str.7
+<span id="A70080C54">  0x70080C54:  </span>F240 1103    MOVW       R1, #0x0103
+<span id="A70080C58">  0x70080C58:  </span>F000 FD26    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L8:
+<span id="A70080C5C">  0x70080C5C:  </span>F9BD 0016    LDRSH.W    R0, [SP, #22]
+<span id="A70080C60">  0x70080C60:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080C62">  0x70080C62:  </span>9802         LDR        R0, [SP, #8]
+<span id="A70080C64">  0x70080C64:  </span>9904         LDR        R1, [SP, #16]
+<span id="A70080C66">  0x70080C66:  </span>9A03         LDR        R2, [SP, #12]
+<span id="A70080C68">  0x70080C68:  </span>F000 F80E    BL         <a href="#NVIC_EncodePriority">NVIC_EncodePriority</a>      ; 0x70080C88
+<span id="A70080C6C">  0x70080C6C:  </span>4601         MOV        R1, R0
+<span id="A70080C6E">  0x70080C6E:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080C70">  0x70080C70:  </span>F000 FDA0    BL         <a href="#__NVIC_SetPriority">__NVIC_SetPriority</a>       ; 0x700817B4
+<span id="A70080C74">  0x70080C74:  </span>B006         ADD        SP, SP, #24
+<span id="A70080C76">  0x70080C76:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.__NVIC_GetPriorityGrouping from blto_App_lto.o, size=16, align=4">Section .text.__NVIC_GetPriorityGrouping from blto_App_lto.o, size=16, align=4</h2>
+
+<pre>
+<br/><span id="__NVIC_GetPriorityGrouping">__NVIC_GetPriorityGrouping:</span>
+<span id="A70080C78">  0x70080C78:  </span>F64E 500C    MOVW       R0, #0xED0C
+<span id="A70080C7C">  0x70080C7C:  </span>F2CE 0000    MOVT       R0, #0xE000
+<span id="A70080C80">  0x70080C80:  </span>6800         LDR        R0, [R0]
+<span id="A70080C82">  0x70080C82:  </span>F3C0 2002    UBFX       R0, R0, #8, #3
+<span id="A70080C86">  0x70080C86:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.NVIC_EncodePriority from blto_App_lto.o, size=100, align=4">Section .text.NVIC_EncodePriority from blto_App_lto.o, size=100, align=4</h2>
+
+<pre>
+<br/><span id="NVIC_EncodePriority">NVIC_EncodePriority:</span>
+<span id="A70080C88">  0x70080C88:  </span>B088         SUB        SP, SP, #32
+<span id="A70080C8A">  0x70080C8A:  </span>9007         STR        R0, [SP, #28]
+<span id="A70080C8C">  0x70080C8C:  </span>9106         STR        R1, [SP, #24]
+<span id="A70080C8E">  0x70080C8E:  </span>9205         STR        R2, [SP, #20]
+<span id="A70080C90">  0x70080C90:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70080C92">  0x70080C92:  </span>F000 0007    AND        R0, R0, #7
+<span id="A70080C96">  0x70080C96:  </span>9004         STR        R0, [SP, #16]
+<span id="A70080C98">  0x70080C98:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080C9A">  0x70080C9A:  </span>F1C0 0007    RSB        R0, R0, #7
+<span id="A70080C9E">  0x70080C9E:  </span>2805         CMP        R0, #5
+<span id="A70080CA0">  0x70080CA0:  </span>D302         BCC        46L1                      ; 0x70080CA8
+<span id="A70080CA2">  0x70080CA2:  </span>2004         MOVS       R0, #4
+<span id="A70080CA4">  0x70080CA4:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080CA6">  0x70080CA6:  </span>E003         B          46L2                      ; 0x70080CB0
+<br/>.L1:
+<span id="A70080CA8">  0x70080CA8:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080CAA">  0x70080CAA:  </span>F1C0 0007    RSB        R0, R0, #7
+<span id="A70080CAE">  0x70080CAE:  </span>9001         STR        R0, [SP, #4]
+<br/>.L2:
+<span id="A70080CB0">  0x70080CB0:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080CB2">  0x70080CB2:  </span>9003         STR        R0, [SP, #12]
+<span id="A70080CB4">  0x70080CB4:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080CB6">  0x70080CB6:  </span>3004         ADDS       R0, #4
+<span id="A70080CB8">  0x70080CB8:  </span>2806         CMP        R0, #6
+<span id="A70080CBA">  0x70080CBA:  </span>D802         BHI        46L3                      ; 0x70080CC2
+<span id="A70080CBC">  0x70080CBC:  </span>2000         MOVS       R0, #0
+<span id="A70080CBE">  0x70080CBE:  </span>9000         STR        R0, [SP, #0]
+<span id="A70080CC0">  0x70080CC0:  </span>E002         B          46L4                      ; 0x70080CC8
+<br/>.L3:
+<span id="A70080CC2">  0x70080CC2:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70080CC4">  0x70080CC4:  </span>3803         SUBS       R0, #3
+<span id="A70080CC6">  0x70080CC6:  </span>9000         STR        R0, [SP, #0]
+<br/>.L4:
+<span id="A70080CC8">  0x70080CC8:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70080CCA">  0x70080CCA:  </span>9002         STR        R0, [SP, #8]
+<span id="A70080CCC">  0x70080CCC:  </span>9806         LDR        R0, [SP, #24]
+<span id="A70080CCE">  0x70080CCE:  </span>9903         LDR        R1, [SP, #12]
+<span id="A70080CD0">  0x70080CD0:  </span>2201         MOVS       R2, #1
+<span id="A70080CD2">  0x70080CD2:  </span>FA02 F101    LSL.W      R1, R2, R1
+<span id="A70080CD6">  0x70080CD6:  </span>3901         SUBS       R1, #1
+<span id="A70080CD8">  0x70080CD8:  </span>4008         ANDS       R0, R1
+<span id="A70080CDA">  0x70080CDA:  </span>9B02         LDR        R3, [SP, #8]
+<span id="A70080CDC">  0x70080CDC:  </span>4098         LSLS       R0, R3
+<span id="A70080CDE">  0x70080CDE:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080CE0">  0x70080CE0:  </span>409A         LSLS       R2, R3
+<span id="A70080CE2">  0x70080CE2:  </span>3A01         SUBS       R2, #1
+<span id="A70080CE4">  0x70080CE4:  </span>4011         ANDS       R1, R2
+<span id="A70080CE6">  0x70080CE6:  </span>4308         ORRS       R0, R1
+<span id="A70080CE8">  0x70080CE8:  </span>B008         ADD        SP, SP, #32
+<span id="A70080CEA">  0x70080CEA:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_SYSTICK_Config from blto_App_lto.o, size=16, align=4">Section .text.HAL_SYSTICK_Config from blto_App_lto.o, size=16, align=4</h2>
+
+<pre>
+<br/><span id="HAL_SYSTICK_Config">HAL_SYSTICK_Config:</span>
+<span id="A70080CEC">  0x70080CEC:  </span>B580         PUSH       123R7, LR}
+<span id="A70080CEE">  0x70080CEE:  </span>B082         SUB        SP, SP, #8
+<span id="A70080CF0">  0x70080CF0:  </span>9001         STR        R0, [SP, #4]
+<span id="A70080CF2">  0x70080CF2:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70080CF4">  0x70080CF4:  </span>F000 FD7E    BL         <a href="#SysTick_Config">SysTick_Config</a>           ; 0x700817F4
+<span id="A70080CF8">  0x70080CF8:  </span>B002         ADD        SP, SP, #8
+<span id="A70080CFA">  0x70080CFA:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto_App_lto.o, size=1928, align=4">Section .text.HAL_GPIO_Init from blto_App_lto.o, size=1928, align=4</h2>
+
+<pre>
+<br/><span id="HAL_GPIO_Init">HAL_GPIO_Init:</span>
+<span id="A70080CFC">  0x70080CFC:  </span>B580         PUSH       123R7, LR}
+<span id="A70080CFE">  0x70080CFE:  </span>B090         SUB        SP, SP, #64
+<span id="A70080D00">  0x70080D00:  </span>900F         STR        R0, [SP, #60]
+<span id="A70080D02">  0x70080D02:  </span>910E         STR        R1, [SP, #56]
+<span id="A70080D04">  0x70080D04:  </span>2000         MOVS       R0, #0
+<span id="A70080D06">  0x70080D06:  </span>900D         STR        R0, [SP, #52]
+<span id="A70080D08">  0x70080D08:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D0A">  0x70080D0A:  </span>2100         MOVS       R1, #0
+<span id="A70080D0C">  0x70080D0C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D10">  0x70080D10:  </span>4288         CMP        R0, R1
+<span id="A70080D12">  0x70080D12:  </span>F000 80A4    BEQ.W      46L1                      ; 0x70080E5E
+<span id="A70080D16">  0x70080D16:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D18">  0x70080D18:  </span>2100         MOVS       R1, #0
+<span id="A70080D1A">  0x70080D1A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080D1E">  0x70080D1E:  </span>4288         CMP        R0, R1
+<span id="A70080D20">  0x70080D20:  </span>F000 809D    BEQ.W      46L1                      ; 0x70080E5E
+<span id="A70080D24">  0x70080D24:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D26">  0x70080D26:  </span>F240 4100    MOVW       R1, #0x0400
+<span id="A70080D2A">  0x70080D2A:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D2E">  0x70080D2E:  </span>4288         CMP        R0, R1
+<span id="A70080D30">  0x70080D30:  </span>F000 8095    BEQ.W      46L1                      ; 0x70080E5E
+<span id="A70080D34">  0x70080D34:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D36">  0x70080D36:  </span>F240 4100    MOVW       R1, #0x0400
+<span id="A70080D3A">  0x70080D3A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080D3E">  0x70080D3E:  </span>4288         CMP        R0, R1
+<span id="A70080D40">  0x70080D40:  </span>F000 808D    BEQ.W      46L1                      ; 0x70080E5E
+<span id="A70080D44">  0x70080D44:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D46">  0x70080D46:  </span>F640 0100    MOVW       R1, #0x0800
+<span id="A70080D4A">  0x70080D4A:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D4E">  0x70080D4E:  </span>4288         CMP        R0, R1
+<span id="A70080D50">  0x70080D50:  </span>F000 8085    BEQ.W      46L1                      ; 0x70080E5E
+<span id="A70080D54">  0x70080D54:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D56">  0x70080D56:  </span>F640 0100    MOVW       R1, #0x0800
+<span id="A70080D5A">  0x70080D5A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080D5E">  0x70080D5E:  </span>4288         CMP        R0, R1
+<span id="A70080D60">  0x70080D60:  </span>D07D         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080D62">  0x70080D62:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D64">  0x70080D64:  </span>F640 4100    MOVW       R1, #0x0C00
+<span id="A70080D68">  0x70080D68:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D6C">  0x70080D6C:  </span>4288         CMP        R0, R1
+<span id="A70080D6E">  0x70080D6E:  </span>D076         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080D70">  0x70080D70:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D72">  0x70080D72:  </span>F640 4100    MOVW       R1, #0x0C00
+<span id="A70080D76">  0x70080D76:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080D7A">  0x70080D7A:  </span>4288         CMP        R0, R1
+<span id="A70080D7C">  0x70080D7C:  </span>D06F         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080D7E">  0x70080D7E:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D80">  0x70080D80:  </span>F241 0100    MOVW       R1, #0x1000
+<span id="A70080D84">  0x70080D84:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D88">  0x70080D88:  </span>4288         CMP        R0, R1
+<span id="A70080D8A">  0x70080D8A:  </span>D068         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080D8C">  0x70080D8C:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D8E">  0x70080D8E:  </span>F241 0100    MOVW       R1, #0x1000
+<span id="A70080D92">  0x70080D92:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080D96">  0x70080D96:  </span>4288         CMP        R0, R1
+<span id="A70080D98">  0x70080D98:  </span>D061         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080D9A">  0x70080D9A:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080D9C">  0x70080D9C:  </span>F241 4100    MOVW       R1, #0x1400
+<span id="A70080DA0">  0x70080DA0:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080DA4">  0x70080DA4:  </span>4288         CMP        R0, R1
+<span id="A70080DA6">  0x70080DA6:  </span>D05A         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DA8">  0x70080DA8:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DAA">  0x70080DAA:  </span>F241 4100    MOVW       R1, #0x1400
+<span id="A70080DAE">  0x70080DAE:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080DB2">  0x70080DB2:  </span>4288         CMP        R0, R1
+<span id="A70080DB4">  0x70080DB4:  </span>D053         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DB6">  0x70080DB6:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DB8">  0x70080DB8:  </span>F641 0100    MOVW       R1, #0x1800
+<span id="A70080DBC">  0x70080DBC:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080DC0">  0x70080DC0:  </span>4288         CMP        R0, R1
+<span id="A70080DC2">  0x70080DC2:  </span>D04C         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DC4">  0x70080DC4:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DC6">  0x70080DC6:  </span>F641 0100    MOVW       R1, #0x1800
+<span id="A70080DCA">  0x70080DCA:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080DCE">  0x70080DCE:  </span>4288         CMP        R0, R1
+<span id="A70080DD0">  0x70080DD0:  </span>D045         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DD2">  0x70080DD2:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DD4">  0x70080DD4:  </span>F641 4100    MOVW       R1, #0x1C00
+<span id="A70080DD8">  0x70080DD8:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080DDC">  0x70080DDC:  </span>4288         CMP        R0, R1
+<span id="A70080DDE">  0x70080DDE:  </span>D03E         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DE0">  0x70080DE0:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DE2">  0x70080DE2:  </span>F641 4100    MOVW       R1, #0x1C00
+<span id="A70080DE6">  0x70080DE6:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080DEA">  0x70080DEA:  </span>4288         CMP        R0, R1
+<span id="A70080DEC">  0x70080DEC:  </span>D037         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DEE">  0x70080DEE:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DF0">  0x70080DF0:  </span>F243 4100    MOVW       R1, #0x3400
+<span id="A70080DF4">  0x70080DF4:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080DF8">  0x70080DF8:  </span>4288         CMP        R0, R1
+<span id="A70080DFA">  0x70080DFA:  </span>D030         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080DFC">  0x70080DFC:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080DFE">  0x70080DFE:  </span>F243 4100    MOVW       R1, #0x3400
+<span id="A70080E02">  0x70080E02:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080E06">  0x70080E06:  </span>4288         CMP        R0, R1
+<span id="A70080E08">  0x70080E08:  </span>D029         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E0A">  0x70080E0A:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E0C">  0x70080E0C:  </span>F643 0100    MOVW       R1, #0x3800
+<span id="A70080E10">  0x70080E10:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080E14">  0x70080E14:  </span>4288         CMP        R0, R1
+<span id="A70080E16">  0x70080E16:  </span>D022         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E18">  0x70080E18:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E1A">  0x70080E1A:  </span>F643 0100    MOVW       R1, #0x3800
+<span id="A70080E1E">  0x70080E1E:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080E22">  0x70080E22:  </span>4288         CMP        R0, R1
+<span id="A70080E24">  0x70080E24:  </span>D01B         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E26">  0x70080E26:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E28">  0x70080E28:  </span>F643 4100    MOVW       R1, #0x3C00
+<span id="A70080E2C">  0x70080E2C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080E30">  0x70080E30:  </span>4288         CMP        R0, R1
+<span id="A70080E32">  0x70080E32:  </span>D014         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E34">  0x70080E34:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E36">  0x70080E36:  </span>F643 4100    MOVW       R1, #0x3C00
+<span id="A70080E3A">  0x70080E3A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080E3E">  0x70080E3E:  </span>4288         CMP        R0, R1
+<span id="A70080E40">  0x70080E40:  </span>D00D         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E42">  0x70080E42:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E44">  0x70080E44:  </span>F244 0100    MOVW       R1, #0x4000
+<span id="A70080E48">  0x70080E48:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080E4C">  0x70080E4C:  </span>4288         CMP        R0, R1
+<span id="A70080E4E">  0x70080E4E:  </span>D006         BEQ        46L1                      ; 0x70080E5E
+<span id="A70080E50">  0x70080E50:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080E52">  0x70080E52:  </span>F244 0100    MOVW       R1, #0x4000
+<span id="A70080E56">  0x70080E56:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70080E5A">  0x70080E5A:  </span>4288         CMP        R0, R1
+<span id="A70080E5C">  0x70080E5C:  </span>D100         BNE        46L2                      ; 0x70080E60
+<br/>.L1:
+<span id="A70080E5E">  0x70080E5E:  </span>E006         B          46L3                      ; 0x70080E6E
+<br/>.L2:
+<span id="A70080E60">  0x70080E60:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080E64">  0x70080E64:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080E68">  0x70080E68:  </span>21AD         MOVS       R1, #173
+<span id="A70080E6A">  0x70080E6A:  </span>F000 FC1D    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L3:
+<span id="A70080E6E">  0x70080E6E:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080E70">  0x70080E70:  </span>8800         LDRH       R0, [R0]
+<span id="A70080E72">  0x70080E72:  </span>B118         CBZ        R0, .L4                  ; 0x70080E7C
+<span id="A70080E74">  0x70080E74:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080E76">  0x70080E76:  </span>8840         LDRH       R0, [R0, #2]
+<span id="A70080E78">  0x70080E78:  </span>B900         CBNZ       R0, .L4                  ; 0x70080E7C
+<span id="A70080E7A">  0x70080E7A:  </span>E006         B          46L5                      ; 0x70080E8A
+<br/>.L4:
+<span id="A70080E7C">  0x70080E7C:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080E80">  0x70080E80:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080E84">  0x70080E84:  </span>21AE         MOVS       R1, #174
+<span id="A70080E86">  0x70080E86:  </span>F000 FC0F    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L5:
+<span id="A70080E8A">  0x70080E8A:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080E8C">  0x70080E8C:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080E8E">  0x70080E8E:  </span>B388         CBZ        R0, .L6                  ; 0x70080EF4
+<span id="A70080E90">  0x70080E90:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080E92">  0x70080E92:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080E94">  0x70080E94:  </span>2801         CMP        R0, #1
+<span id="A70080E96">  0x70080E96:  </span>D02D         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080E98">  0x70080E98:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080E9A">  0x70080E9A:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080E9C">  0x70080E9C:  </span>2811         CMP        R0, #17
+<span id="A70080E9E">  0x70080E9E:  </span>D029         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EA0">  0x70080EA0:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EA2">  0x70080EA2:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EA4">  0x70080EA4:  </span>2802         CMP        R0, #2
+<span id="A70080EA6">  0x70080EA6:  </span>D025         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EA8">  0x70080EA8:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EAA">  0x70080EAA:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EAC">  0x70080EAC:  </span>2812         CMP        R0, #18
+<span id="A70080EAE">  0x70080EAE:  </span>D021         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EB0">  0x70080EB0:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EB2">  0x70080EB2:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EB4">  0x70080EB4:  </span>F5B0 1F88    CMP.W      R0, #0x110000
+<span id="A70080EB8">  0x70080EB8:  </span>D01C         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EBA">  0x70080EBA:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EBC">  0x70080EBC:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EBE">  0x70080EBE:  </span>F5B0 1F04    CMP.W      R0, #0x210000
+<span id="A70080EC2">  0x70080EC2:  </span>D017         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EC4">  0x70080EC4:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EC6">  0x70080EC6:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EC8">  0x70080EC8:  </span>F5B0 1F44    CMP.W      R0, #0x310000
+<span id="A70080ECC">  0x70080ECC:  </span>D012         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080ECE">  0x70080ECE:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080ED0">  0x70080ED0:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080ED2">  0x70080ED2:  </span>F5B0 1F90    CMP.W      R0, #0x120000
+<span id="A70080ED6">  0x70080ED6:  </span>D00D         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080ED8">  0x70080ED8:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EDA">  0x70080EDA:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EDC">  0x70080EDC:  </span>F5B0 1F08    CMP.W      R0, #0x220000
+<span id="A70080EE0">  0x70080EE0:  </span>D008         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EE2">  0x70080EE2:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EE4">  0x70080EE4:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EE6">  0x70080EE6:  </span>F5B0 1F48    CMP.W      R0, #0x320000
+<span id="A70080EEA">  0x70080EEA:  </span>D003         BEQ        46L6                      ; 0x70080EF4
+<span id="A70080EEC">  0x70080EEC:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080EEE">  0x70080EEE:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080EF0">  0x70080EF0:  </span>2803         CMP        R0, #3
+<span id="A70080EF2">  0x70080EF2:  </span>D100         BNE        46L7                      ; 0x70080EF6
+<br/>.L6:
+<span id="A70080EF4">  0x70080EF4:  </span>E006         B          46L8                      ; 0x70080F04
+<br/>.L7:
+<span id="A70080EF6">  0x70080EF6:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080EFA">  0x70080EFA:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080EFE">  0x70080EFE:  </span>21AF         MOVS       R1, #175
+<span id="A70080F00">  0x70080F00:  </span>F000 FBD2    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L8:
+<span id="A70080F04">  0x70080F04:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F06">  0x70080F06:  </span>6800         LDR        R0, [R0]
+<span id="A70080F08">  0x70080F08:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70080F0A">  0x70080F0A:  </span>40C8         LSRS       R0, R1
+<span id="A70080F0C">  0x70080F0C:  </span>2800         CMP        R0, #0
+<span id="A70080F0E">  0x70080F0E:  </span>F000 82B7    BEQ.W      46L52                     ; 0x70081480
+<span id="A70080F12">  0x70080F12:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F14">  0x70080F14:  </span>6800         LDR        R0, [R0]
+<span id="A70080F16">  0x70080F16:  </span>9A0D         LDR        R2, [SP, #52]
+<span id="A70080F18">  0x70080F18:  </span>2101         MOVS       R1, #1
+<span id="A70080F1A">  0x70080F1A:  </span>4091         LSLS       R1, R2
+<span id="A70080F1C">  0x70080F1C:  </span>4008         ANDS       R0, R1
+<span id="A70080F1E">  0x70080F1E:  </span>900C         STR        R0, [SP, #48]
+<span id="A70080F20">  0x70080F20:  </span>980C         LDR        R0, [SP, #48]
+<span id="A70080F22">  0x70080F22:  </span>2800         CMP        R0, #0
+<span id="A70080F24">  0x70080F24:  </span>F000 82A8    BEQ.W      46L51                     ; 0x70081478
+<span id="A70080F28">  0x70080F28:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F2A">  0x70080F2A:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080F2C">  0x70080F2C:  </span>F000 0003    AND        R0, R0, #3
+<span id="A70080F30">  0x70080F30:  </span>2801         CMP        R0, #1
+<span id="A70080F32">  0x70080F32:  </span>D005         BEQ        46L9                      ; 0x70080F40
+<span id="A70080F34">  0x70080F34:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F36">  0x70080F36:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080F38">  0x70080F38:  </span>F000 0003    AND        R0, R0, #3
+<span id="A70080F3C">  0x70080F3C:  </span>2802         CMP        R0, #2
+<span id="A70080F3E">  0x70080F3E:  </span>D144         BNE        46L13                     ; 0x70080FCA
+<br/>.L9:
+<span id="A70080F40">  0x70080F40:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F42">  0x70080F42:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70080F44">  0x70080F44:  </span>B158         CBZ        R0, .L10                 ; 0x70080F5E
+<span id="A70080F46">  0x70080F46:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F48">  0x70080F48:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70080F4A">  0x70080F4A:  </span>2801         CMP        R0, #1
+<span id="A70080F4C">  0x70080F4C:  </span>D007         BEQ        46L10                     ; 0x70080F5E
+<span id="A70080F4E">  0x70080F4E:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F50">  0x70080F50:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70080F52">  0x70080F52:  </span>2802         CMP        R0, #2
+<span id="A70080F54">  0x70080F54:  </span>D003         BEQ        46L10                     ; 0x70080F5E
+<span id="A70080F56">  0x70080F56:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F58">  0x70080F58:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70080F5A">  0x70080F5A:  </span>2803         CMP        R0, #3
+<span id="A70080F5C">  0x70080F5C:  </span>D100         BNE        46L11                     ; 0x70080F60
+<br/>.L10:
+<span id="A70080F5E">  0x70080F5E:  </span>E006         B          46L12                     ; 0x70080F6E
+<br/>.L11:
+<span id="A70080F60">  0x70080F60:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080F64">  0x70080F64:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A70080F68">  0x70080F68:  </span>21BE         MOVS       R1, #190
+<span id="A70080F6A">  0x70080F6A:  </span>F000 FB9D    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L12:
+<span id="A70080F6E">  0x70080F6E:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080F70">  0x70080F70:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70080F72">  0x70080F72:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080F74">  0x70080F74:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70080F76">  0x70080F76:  </span>0041         LSLS       R1, R0, #1
+<span id="A70080F78">  0x70080F78:  </span>2003         MOVS       R0, #3
+<span id="A70080F7A">  0x70080F7A:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70080F7E">  0x70080F7E:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080F80">  0x70080F80:  </span>4388         BICS       R0, R1
+<span id="A70080F82">  0x70080F82:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080F84">  0x70080F84:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080F86">  0x70080F86:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70080F88">  0x70080F88:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70080F8A">  0x70080F8A:  </span>0049         LSLS       R1, R1, #1
+<span id="A70080F8C">  0x70080F8C:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70080F90">  0x70080F90:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080F92">  0x70080F92:  </span>4308         ORRS       R0, R1
+<span id="A70080F94">  0x70080F94:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080F96">  0x70080F96:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080F98">  0x70080F98:  </span>990F         LDR        R1, [SP, #60]
+<span id="A70080F9A">  0x70080F9A:  </span>6088         STR        R0, [R1, #8]
+<span id="A70080F9C">  0x70080F9C:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70080F9E">  0x70080F9E:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080FA0">  0x70080FA0:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080FA2">  0x70080FA2:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70080FA4">  0x70080FA4:  </span>2001         MOVS       R0, #1
+<span id="A70080FA6">  0x70080FA6:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70080FAA">  0x70080FAA:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080FAC">  0x70080FAC:  </span>4388         BICS       R0, R1
+<span id="A70080FAE">  0x70080FAE:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080FB0">  0x70080FB0:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FB2">  0x70080FB2:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080FB4">  0x70080FB4:  </span>F3C0 1000    UBFX       R0, R0, #4, #1
+<span id="A70080FB8">  0x70080FB8:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70080FBA">  0x70080FBA:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70080FBE">  0x70080FBE:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080FC0">  0x70080FC0:  </span>4308         ORRS       R0, R1
+<span id="A70080FC2">  0x70080FC2:  </span>900B         STR        R0, [SP, #44]
+<span id="A70080FC4">  0x70080FC4:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70080FC6">  0x70080FC6:  </span>990F         LDR        R1, [SP, #60]
+<span id="A70080FC8">  0x70080FC8:  </span>6048         STR        R0, [R1, #4]
+<br/>.L13:
+<span id="A70080FCA">  0x70080FCA:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FCC">  0x70080FCC:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080FCE">  0x70080FCE:  </span>43C0         MVNS       R0, R0
+<span id="A70080FD0">  0x70080FD0:  </span>0780         LSLS       R0, R0, #30
+<span id="A70080FD2">  0x70080FD2:  </span>B940         CBNZ       R0, .L14                 ; 0x70080FE6
+<span id="A70080FD4">  0x70080FD4:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FD6">  0x70080FD6:  </span>6840         LDR        R0, [R0, #4]
+<span id="A70080FD8">  0x70080FD8:  </span>43C0         MVNS       R0, R0
+<span id="A70080FDA">  0x70080FDA:  </span>0780         LSLS       R0, R0, #30
+<span id="A70080FDC">  0x70080FDC:  </span>BB68         CBNZ       R0, .L18                 ; 0x7008103A
+<span id="A70080FDE">  0x70080FDE:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FE0">  0x70080FE0:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70080FE2">  0x70080FE2:  </span>2801         CMP        R0, #1
+<span id="A70080FE4">  0x70080FE4:  </span>D029         BEQ        46L18                     ; 0x7008103A
+<br/>.L14:
+<span id="A70080FE6">  0x70080FE6:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FE8">  0x70080FE8:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70080FEA">  0x70080FEA:  </span>B138         CBZ        R0, .L15                 ; 0x70080FFC
+<span id="A70080FEC">  0x70080FEC:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FEE">  0x70080FEE:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70080FF0">  0x70080FF0:  </span>2801         CMP        R0, #1
+<span id="A70080FF2">  0x70080FF2:  </span>D003         BEQ        46L15                     ; 0x70080FFC
+<span id="A70080FF4">  0x70080FF4:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70080FF6">  0x70080FF6:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70080FF8">  0x70080FF8:  </span>2802         CMP        R0, #2
+<span id="A70080FFA">  0x70080FFA:  </span>D100         BNE        46L16                     ; 0x70080FFE
+<br/>.L15:
+<span id="A70080FFC">  0x70080FFC:  </span>E006         B          46L17                     ; 0x7008100C
+<br/>.L16:
+<span id="A70080FFE">  0x70080FFE:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A70081002">  0x70081002:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A70081006">  0x70081006:  </span>21D1         MOVS       R1, #209
+<span id="A70081008">  0x70081008:  </span>F000 FB4E    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L17:
+<span id="A7008100C">  0x7008100C:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008100E">  0x7008100E:  </span>68C0         LDR        R0, [R0, #12]
+<span id="A70081010">  0x70081010:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081012">  0x70081012:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70081014">  0x70081014:  </span>0041         LSLS       R1, R0, #1
+<span id="A70081016">  0x70081016:  </span>2003         MOVS       R0, #3
+<span id="A70081018">  0x70081018:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A7008101C">  0x7008101C:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008101E">  0x7008101E:  </span>4388         BICS       R0, R1
+<span id="A70081020">  0x70081020:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081022">  0x70081022:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70081024">  0x70081024:  </span>6880         LDR        R0, [R0, #8]
+<span id="A70081026">  0x70081026:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70081028">  0x70081028:  </span>0049         LSLS       R1, R1, #1
+<span id="A7008102A">  0x7008102A:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A7008102E">  0x7008102E:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081030">  0x70081030:  </span>4308         ORRS       R0, R1
+<span id="A70081032">  0x70081032:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081034">  0x70081034:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081036">  0x70081036:  </span>990F         LDR        R1, [SP, #60]
+<span id="A70081038">  0x70081038:  </span>60C8         STR        R0, [R1, #12]
+<br/>.L18:
+<span id="A7008103A">  0x7008103A:  </span>980E         LDR        R0, [SP, #56]
+<span id="A7008103C">  0x7008103C:  </span>6840         LDR        R0, [R0, #4]
+<span id="A7008103E">  0x7008103E:  </span>F000 0003    AND        R0, R0, #3
+<span id="A70081042">  0x70081042:  </span>2802         CMP        R0, #2
+<span id="A70081044">  0x70081044:  </span>F040 80E4    BNE.W      46L24                     ; 0x70081210
+<span id="A70081048">  0x70081048:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008104A">  0x7008104A:  </span>2100         MOVS       R1, #0
+<span id="A7008104C">  0x7008104C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081050">  0x70081050:  </span>4288         CMP        R0, R1
+<span id="A70081052">  0x70081052:  </span>F000 80A4    BEQ.W      46L19                     ; 0x7008119E
+<span id="A70081056">  0x70081056:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081058">  0x70081058:  </span>2100         MOVS       R1, #0
+<span id="A7008105A">  0x7008105A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008105E">  0x7008105E:  </span>4288         CMP        R0, R1
+<span id="A70081060">  0x70081060:  </span>F000 809D    BEQ.W      46L19                     ; 0x7008119E
+<span id="A70081064">  0x70081064:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081066">  0x70081066:  </span>F240 4100    MOVW       R1, #0x0400
+<span id="A7008106A">  0x7008106A:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008106E">  0x7008106E:  </span>4288         CMP        R0, R1
+<span id="A70081070">  0x70081070:  </span>F000 8095    BEQ.W      46L19                     ; 0x7008119E
+<span id="A70081074">  0x70081074:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081076">  0x70081076:  </span>F240 4100    MOVW       R1, #0x0400
+<span id="A7008107A">  0x7008107A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008107E">  0x7008107E:  </span>4288         CMP        R0, R1
+<span id="A70081080">  0x70081080:  </span>F000 808D    BEQ.W      46L19                     ; 0x7008119E
+<span id="A70081084">  0x70081084:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081086">  0x70081086:  </span>F640 0100    MOVW       R1, #0x0800
+<span id="A7008108A">  0x7008108A:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008108E">  0x7008108E:  </span>4288         CMP        R0, R1
+<span id="A70081090">  0x70081090:  </span>F000 8085    BEQ.W      46L19                     ; 0x7008119E
+<span id="A70081094">  0x70081094:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081096">  0x70081096:  </span>F640 0100    MOVW       R1, #0x0800
+<span id="A7008109A">  0x7008109A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008109E">  0x7008109E:  </span>4288         CMP        R0, R1
+<span id="A700810A0">  0x700810A0:  </span>D07D         BEQ        46L19                     ; 0x7008119E
+<span id="A700810A2">  0x700810A2:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810A4">  0x700810A4:  </span>F640 4100    MOVW       R1, #0x0C00
+<span id="A700810A8">  0x700810A8:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700810AC">  0x700810AC:  </span>4288         CMP        R0, R1
+<span id="A700810AE">  0x700810AE:  </span>D076         BEQ        46L19                     ; 0x7008119E
+<span id="A700810B0">  0x700810B0:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810B2">  0x700810B2:  </span>F640 4100    MOVW       R1, #0x0C00
+<span id="A700810B6">  0x700810B6:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A700810BA">  0x700810BA:  </span>4288         CMP        R0, R1
+<span id="A700810BC">  0x700810BC:  </span>D06F         BEQ        46L19                     ; 0x7008119E
+<span id="A700810BE">  0x700810BE:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810C0">  0x700810C0:  </span>F241 0100    MOVW       R1, #0x1000
+<span id="A700810C4">  0x700810C4:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700810C8">  0x700810C8:  </span>4288         CMP        R0, R1
+<span id="A700810CA">  0x700810CA:  </span>D068         BEQ        46L19                     ; 0x7008119E
+<span id="A700810CC">  0x700810CC:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810CE">  0x700810CE:  </span>F241 0100    MOVW       R1, #0x1000
+<span id="A700810D2">  0x700810D2:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A700810D6">  0x700810D6:  </span>4288         CMP        R0, R1
+<span id="A700810D8">  0x700810D8:  </span>D061         BEQ        46L19                     ; 0x7008119E
+<span id="A700810DA">  0x700810DA:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810DC">  0x700810DC:  </span>F241 4100    MOVW       R1, #0x1400
+<span id="A700810E0">  0x700810E0:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700810E4">  0x700810E4:  </span>4288         CMP        R0, R1
+<span id="A700810E6">  0x700810E6:  </span>D05A         BEQ        46L19                     ; 0x7008119E
+<span id="A700810E8">  0x700810E8:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810EA">  0x700810EA:  </span>F241 4100    MOVW       R1, #0x1400
+<span id="A700810EE">  0x700810EE:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A700810F2">  0x700810F2:  </span>4288         CMP        R0, R1
+<span id="A700810F4">  0x700810F4:  </span>D053         BEQ        46L19                     ; 0x7008119E
+<span id="A700810F6">  0x700810F6:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700810F8">  0x700810F8:  </span>F641 0100    MOVW       R1, #0x1800
+<span id="A700810FC">  0x700810FC:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081100">  0x70081100:  </span>4288         CMP        R0, R1
+<span id="A70081102">  0x70081102:  </span>D04C         BEQ        46L19                     ; 0x7008119E
+<span id="A70081104">  0x70081104:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081106">  0x70081106:  </span>F641 0100    MOVW       R1, #0x1800
+<span id="A7008110A">  0x7008110A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008110E">  0x7008110E:  </span>4288         CMP        R0, R1
+<span id="A70081110">  0x70081110:  </span>D045         BEQ        46L19                     ; 0x7008119E
+<span id="A70081112">  0x70081112:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081114">  0x70081114:  </span>F641 4100    MOVW       R1, #0x1C00
+<span id="A70081118">  0x70081118:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008111C">  0x7008111C:  </span>4288         CMP        R0, R1
+<span id="A7008111E">  0x7008111E:  </span>D03E         BEQ        46L19                     ; 0x7008119E
+<span id="A70081120">  0x70081120:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081122">  0x70081122:  </span>F641 4100    MOVW       R1, #0x1C00
+<span id="A70081126">  0x70081126:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008112A">  0x7008112A:  </span>4288         CMP        R0, R1
+<span id="A7008112C">  0x7008112C:  </span>D037         BEQ        46L19                     ; 0x7008119E
+<span id="A7008112E">  0x7008112E:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081130">  0x70081130:  </span>F243 4100    MOVW       R1, #0x3400
+<span id="A70081134">  0x70081134:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081138">  0x70081138:  </span>4288         CMP        R0, R1
+<span id="A7008113A">  0x7008113A:  </span>D030         BEQ        46L19                     ; 0x7008119E
+<span id="A7008113C">  0x7008113C:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008113E">  0x7008113E:  </span>F243 4100    MOVW       R1, #0x3400
+<span id="A70081142">  0x70081142:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70081146">  0x70081146:  </span>4288         CMP        R0, R1
+<span id="A70081148">  0x70081148:  </span>D029         BEQ        46L19                     ; 0x7008119E
+<span id="A7008114A">  0x7008114A:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008114C">  0x7008114C:  </span>F643 0100    MOVW       R1, #0x3800
+<span id="A70081150">  0x70081150:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081154">  0x70081154:  </span>4288         CMP        R0, R1
+<span id="A70081156">  0x70081156:  </span>D022         BEQ        46L19                     ; 0x7008119E
+<span id="A70081158">  0x70081158:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008115A">  0x7008115A:  </span>F643 0100    MOVW       R1, #0x3800
+<span id="A7008115E">  0x7008115E:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A70081162">  0x70081162:  </span>4288         CMP        R0, R1
+<span id="A70081164">  0x70081164:  </span>D01B         BEQ        46L19                     ; 0x7008119E
+<span id="A70081166">  0x70081166:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081168">  0x70081168:  </span>F643 4100    MOVW       R1, #0x3C00
+<span id="A7008116C">  0x7008116C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081170">  0x70081170:  </span>4288         CMP        R0, R1
+<span id="A70081172">  0x70081172:  </span>D014         BEQ        46L19                     ; 0x7008119E
+<span id="A70081174">  0x70081174:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081176">  0x70081176:  </span>F643 4100    MOVW       R1, #0x3C00
+<span id="A7008117A">  0x7008117A:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008117E">  0x7008117E:  </span>4288         CMP        R0, R1
+<span id="A70081180">  0x70081180:  </span>D00D         BEQ        46L19                     ; 0x7008119E
+<span id="A70081182">  0x70081182:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081184">  0x70081184:  </span>F244 0100    MOVW       R1, #0x4000
+<span id="A70081188">  0x70081188:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008118C">  0x7008118C:  </span>4288         CMP        R0, R1
+<span id="A7008118E">  0x7008118E:  </span>D006         BEQ        46L19                     ; 0x7008119E
+<span id="A70081190">  0x70081190:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081192">  0x70081192:  </span>F244 0100    MOVW       R1, #0x4000
+<span id="A70081196">  0x70081196:  </span>F2C4 6102    MOVT       R1, #0x4602
+<span id="A7008119A">  0x7008119A:  </span>4288         CMP        R0, R1
+<span id="A7008119C">  0x7008119C:  </span>D100         BNE        46L20                     ; 0x700811A0
+<br/>.L19:
+<span id="A7008119E">  0x7008119E:  </span>E006         B          46L21                     ; 0x700811AE
+<br/>.L20:
+<span id="A700811A0">  0x700811A0:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A700811A4">  0x700811A4:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A700811A8">  0x700811A8:  </span>21DE         MOVS       R1, #222
+<span id="A700811AA">  0x700811AA:  </span>F000 FA7D    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L21:
+<span id="A700811AE">  0x700811AE:  </span>980E         LDR        R0, [SP, #56]
+<span id="A700811B0">  0x700811B0:  </span>6900         LDR        R0, [R0, #16]
+<span id="A700811B2">  0x700811B2:  </span>280F         CMP        R0, #15
+<span id="A700811B4">  0x700811B4:  </span>D800         BHI        46L22                     ; 0x700811B8
+<span id="A700811B6">  0x700811B6:  </span>E006         B          46L23                     ; 0x700811C6
+<br/>.L22:
+<span id="A700811B8">  0x700811B8:  </span>F641 10FF    MOVW       R0, #0x19FF              ; 0x700819FF = .rodata..L.str.17
+<span id="A700811BC">  0x700811BC:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x700819FF = .rodata..L.str.17
+<span id="A700811C0">  0x700811C0:  </span>21DF         MOVS       R1, #223
+<span id="A700811C2">  0x700811C2:  </span>F000 FA71    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L23:
+<span id="A700811C6">  0x700811C6:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700811C8">  0x700811C8:  </span>990D         LDR        R1, [SP, #52]
+<span id="A700811CA">  0x700811CA:  </span>F06F 0203    MVN        R2, #3
+<span id="A700811CE">  0x700811CE:  </span>EA02 0151    AND.W      R1, R2, R1, LSR #1
+<span id="A700811D2">  0x700811D2:  </span>4408         ADD        R0, R1
+<span id="A700811D4">  0x700811D4:  </span>6A00         LDR        R0, [R0, #32]
+<span id="A700811D6">  0x700811D6:  </span>900B         STR        R0, [SP, #44]
+<span id="A700811D8">  0x700811D8:  </span>980D         LDR        R0, [SP, #52]
+<span id="A700811DA">  0x700811DA:  </span>F000 0007    AND        R0, R0, #7
+<span id="A700811DE">  0x700811DE:  </span>0081         LSLS       R1, R0, #2
+<span id="A700811E0">  0x700811E0:  </span>200F         MOVS       R0, #15
+<span id="A700811E2">  0x700811E2:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A700811E6">  0x700811E6:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700811E8">  0x700811E8:  </span>4388         BICS       R0, R1
+<span id="A700811EA">  0x700811EA:  </span>900B         STR        R0, [SP, #44]
+<span id="A700811EC">  0x700811EC:  </span>980E         LDR        R0, [SP, #56]
+<span id="A700811EE">  0x700811EE:  </span>6900         LDR        R0, [R0, #16]
+<span id="A700811F0">  0x700811F0:  </span>990D         LDR        R1, [SP, #52]
+<span id="A700811F2">  0x700811F2:  </span>F001 0107    AND        R1, R1, #7
+<span id="A700811F6">  0x700811F6:  </span>0089         LSLS       R1, R1, #2
+<span id="A700811F8">  0x700811F8:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A700811FC">  0x700811FC:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700811FE">  0x700811FE:  </span>4308         ORRS       R0, R1
+<span id="A70081200">  0x70081200:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081202">  0x70081202:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081204">  0x70081204:  </span>990F         LDR        R1, [SP, #60]
+<span id="A70081206">  0x70081206:  </span>9B0D         LDR        R3, [SP, #52]
+<span id="A70081208">  0x70081208:  </span>EA02 0253    AND.W      R2, R2, R3, LSR #1
+<span id="A7008120C">  0x7008120C:  </span>4411         ADD        R1, R2
+<span id="A7008120E">  0x7008120E:  </span>6208         STR        R0, [R1, #32]
+<br/>.L24:
+<span id="A70081210">  0x70081210:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081212">  0x70081212:  </span>6800         LDR        R0, [R0]
+<span id="A70081214">  0x70081214:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081216">  0x70081216:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70081218">  0x70081218:  </span>0041         LSLS       R1, R0, #1
+<span id="A7008121A">  0x7008121A:  </span>2003         MOVS       R0, #3
+<span id="A7008121C">  0x7008121C:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70081220">  0x70081220:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081222">  0x70081222:  </span>4388         BICS       R0, R1
+<span id="A70081224">  0x70081224:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081226">  0x70081226:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70081228">  0x70081228:  </span>6840         LDR        R0, [R0, #4]
+<span id="A7008122A">  0x7008122A:  </span>F000 0003    AND        R0, R0, #3
+<span id="A7008122E">  0x7008122E:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70081230">  0x70081230:  </span>0049         LSLS       R1, R1, #1
+<span id="A70081232">  0x70081232:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A70081236">  0x70081236:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081238">  0x70081238:  </span>4308         ORRS       R0, R1
+<span id="A7008123A">  0x7008123A:  </span>900B         STR        R0, [SP, #44]
+<span id="A7008123C">  0x7008123C:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008123E">  0x7008123E:  </span>990F         LDR        R1, [SP, #60]
+<span id="A70081240">  0x70081240:  </span>6008         STR        R0, [R1]
+<span id="A70081242">  0x70081242:  </span>980E         LDR        R0, [SP, #56]
+<span id="A70081244">  0x70081244:  </span>7980         LDRB       R0, [R0, #6]
+<span id="A70081246">  0x70081246:  </span>0780         LSLS       R0, R0, #30
+<span id="A70081248">  0x70081248:  </span>2800         CMP        R0, #0
+<span id="A7008124A">  0x7008124A:  </span>F000 8115    BEQ.W      46L51                     ; 0x70081478
+<span id="A7008124E">  0x7008124E:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70081250">  0x70081250:  </span>F020 0003    BIC        R0, R0, #3
+<span id="A70081254">  0x70081254:  </span>F245 0160    MOVW       R1, #0x5060
+<span id="A70081258">  0x70081258:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008125C">  0x7008125C:  </span>5840         LDR        R0, [R0, R1]
+<span id="A7008125E">  0x7008125E:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081260">  0x70081260:  </span>980D         LDR        R0, [SP, #52]
+<span id="A70081262">  0x70081262:  </span>F000 0003    AND        R0, R0, #3
+<span id="A70081266">  0x70081266:  </span>00C1         LSLS       R1, R0, #3
+<span id="A70081268">  0x70081268:  </span>200F         MOVS       R0, #15
+<span id="A7008126A">  0x7008126A:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A7008126E">  0x7008126E:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081270">  0x70081270:  </span>4388         BICS       R0, R1
+<span id="A70081272">  0x70081272:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081274">  0x70081274:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081276">  0x70081276:  </span>2100         MOVS       R1, #0
+<span id="A70081278">  0x70081278:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008127C">  0x7008127C:  </span>4288         CMP        R0, R1
+<span id="A7008127E">  0x7008127E:  </span>D102         BNE        46L25                     ; 0x70081286
+<span id="A70081280">  0x70081280:  </span>2000         MOVS       R0, #0
+<span id="A70081282">  0x70081282:  </span>900A         STR        R0, [SP, #40]
+<span id="A70081284">  0x70081284:  </span>E082         B          46L46                     ; 0x7008138C
+<br/>.L25:
+<span id="A70081286">  0x70081286:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081288">  0x70081288:  </span>F240 4100    MOVW       R1, #0x0400
+<span id="A7008128C">  0x7008128C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081290">  0x70081290:  </span>4288         CMP        R0, R1
+<span id="A70081292">  0x70081292:  </span>D102         BNE        46L26                     ; 0x7008129A
+<span id="A70081294">  0x70081294:  </span>2001         MOVS       R0, #1
+<span id="A70081296">  0x70081296:  </span>9009         STR        R0, [SP, #36]
+<span id="A70081298">  0x70081298:  </span>E076         B          46L45                     ; 0x70081388
+<br/>.L26:
+<span id="A7008129A">  0x7008129A:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008129C">  0x7008129C:  </span>F640 0100    MOVW       R1, #0x0800
+<span id="A700812A0">  0x700812A0:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700812A4">  0x700812A4:  </span>4288         CMP        R0, R1
+<span id="A700812A6">  0x700812A6:  </span>D102         BNE        46L27                     ; 0x700812AE
+<span id="A700812A8">  0x700812A8:  </span>2002         MOVS       R0, #2
+<span id="A700812AA">  0x700812AA:  </span>9008         STR        R0, [SP, #32]
+<span id="A700812AC">  0x700812AC:  </span>E06A         B          46L44                     ; 0x70081384
+<br/>.L27:
+<span id="A700812AE">  0x700812AE:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700812B0">  0x700812B0:  </span>F640 4100    MOVW       R1, #0x0C00
+<span id="A700812B4">  0x700812B4:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700812B8">  0x700812B8:  </span>4288         CMP        R0, R1
+<span id="A700812BA">  0x700812BA:  </span>D102         BNE        46L28                     ; 0x700812C2
+<span id="A700812BC">  0x700812BC:  </span>2003         MOVS       R0, #3
+<span id="A700812BE">  0x700812BE:  </span>9007         STR        R0, [SP, #28]
+<span id="A700812C0">  0x700812C0:  </span>E05E         B          46L43                     ; 0x70081380
+<br/>.L28:
+<span id="A700812C2">  0x700812C2:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700812C4">  0x700812C4:  </span>F241 0100    MOVW       R1, #0x1000
+<span id="A700812C8">  0x700812C8:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700812CC">  0x700812CC:  </span>4288         CMP        R0, R1
+<span id="A700812CE">  0x700812CE:  </span>D102         BNE        46L29                     ; 0x700812D6
+<span id="A700812D0">  0x700812D0:  </span>2004         MOVS       R0, #4
+<span id="A700812D2">  0x700812D2:  </span>9006         STR        R0, [SP, #24]
+<span id="A700812D4">  0x700812D4:  </span>E052         B          46L42                     ; 0x7008137C
+<br/>.L29:
+<span id="A700812D6">  0x700812D6:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700812D8">  0x700812D8:  </span>F241 4100    MOVW       R1, #0x1400
+<span id="A700812DC">  0x700812DC:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700812E0">  0x700812E0:  </span>4288         CMP        R0, R1
+<span id="A700812E2">  0x700812E2:  </span>D102         BNE        46L30                     ; 0x700812EA
+<span id="A700812E4">  0x700812E4:  </span>2005         MOVS       R0, #5
+<span id="A700812E6">  0x700812E6:  </span>9005         STR        R0, [SP, #20]
+<span id="A700812E8">  0x700812E8:  </span>E046         B          46L41                     ; 0x70081378
+<br/>.L30:
+<span id="A700812EA">  0x700812EA:  </span>980F         LDR        R0, [SP, #60]
+<span id="A700812EC">  0x700812EC:  </span>F641 0100    MOVW       R1, #0x1800
+<span id="A700812F0">  0x700812F0:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700812F4">  0x700812F4:  </span>4288         CMP        R0, R1
+<span id="A700812F6">  0x700812F6:  </span>D102         BNE        46L31                     ; 0x700812FE
+<span id="A700812F8">  0x700812F8:  </span>2006         MOVS       R0, #6
+<span id="A700812FA">  0x700812FA:  </span>9004         STR        R0, [SP, #16]
+<span id="A700812FC">  0x700812FC:  </span>E03A         B          46L40                     ; 0x70081374
+<br/>.L31:
+<span id="A700812FE">  0x700812FE:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081300">  0x70081300:  </span>F641 4100    MOVW       R1, #0x1C00
+<span id="A70081304">  0x70081304:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081308">  0x70081308:  </span>4288         CMP        R0, R1
+<span id="A7008130A">  0x7008130A:  </span>D102         BNE        46L32                     ; 0x70081312
+<span id="A7008130C">  0x7008130C:  </span>2007         MOVS       R0, #7
+<span id="A7008130E">  0x7008130E:  </span>9003         STR        R0, [SP, #12]
+<span id="A70081310">  0x70081310:  </span>E02E         B          46L39                     ; 0x70081370
+<br/>.L32:
+<span id="A70081312">  0x70081312:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081314">  0x70081314:  </span>F243 4100    MOVW       R1, #0x3400
+<span id="A70081318">  0x70081318:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008131C">  0x7008131C:  </span>4288         CMP        R0, R1
+<span id="A7008131E">  0x7008131E:  </span>D102         BNE        46L33                     ; 0x70081326
+<span id="A70081320">  0x70081320:  </span>2008         MOVS       R0, #8
+<span id="A70081322">  0x70081322:  </span>9002         STR        R0, [SP, #8]
+<span id="A70081324">  0x70081324:  </span>E022         B          46L38                     ; 0x7008136C
+<br/>.L33:
+<span id="A70081326">  0x70081326:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081328">  0x70081328:  </span>F643 0100    MOVW       R1, #0x3800
+<span id="A7008132C">  0x7008132C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081330">  0x70081330:  </span>4288         CMP        R0, R1
+<span id="A70081332">  0x70081332:  </span>D102         BNE        46L34                     ; 0x7008133A
+<span id="A70081334">  0x70081334:  </span>2009         MOVS       R0, #9
+<span id="A70081336">  0x70081336:  </span>9001         STR        R0, [SP, #4]
+<span id="A70081338">  0x70081338:  </span>E016         B          46L37                     ; 0x70081368
+<br/>.L34:
+<span id="A7008133A">  0x7008133A:  </span>980F         LDR        R0, [SP, #60]
+<span id="A7008133C">  0x7008133C:  </span>F643 4100    MOVW       R1, #0x3C00
+<span id="A70081340">  0x70081340:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081344">  0x70081344:  </span>4288         CMP        R0, R1
+<span id="A70081346">  0x70081346:  </span>D102         BNE        46L35                     ; 0x7008134E
+<span id="A70081348">  0x70081348:  </span>200A         MOVS       R0, #10
+<span id="A7008134A">  0x7008134A:  </span>9000         STR        R0, [SP, #0]
+<span id="A7008134C">  0x7008134C:  </span>E00A         B          46L36                     ; 0x70081364
+<br/>.L35:
+<span id="A7008134E">  0x7008134E:  </span>980F         LDR        R0, [SP, #60]
+<span id="A70081350">  0x70081350:  </span>F244 0100    MOVW       R1, #0x4000
+<span id="A70081354">  0x70081354:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081358">  0x70081358:  </span>4288         CMP        R0, R1
+<span id="A7008135A">  0x7008135A:  </span>F04F 0010    MOV.W      R0, #16
+<span id="A7008135E">  0x7008135E:  </span>BF08         IT         EQ
+<span id="A70081360">  0x70081360:  </span>200B         MOVEQ      R0, #11
+<span id="A70081362">  0x70081362:  </span>9000         STR        R0, [SP, #0]
+<br/>.L36:
+<span id="A70081364">  0x70081364:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70081366">  0x70081366:  </span>9001         STR        R0, [SP, #4]
+<br/>.L37:
+<span id="A70081368">  0x70081368:  </span>9801         LDR        R0, [SP, #4]
+<span id="A7008136A">  0x7008136A:  </span>9002         STR        R0, [SP, #8]
+<br/>.L38:
+<span id="A7008136C">  0x7008136C:  </span>9802         LDR        R0, [SP, #8]
+<span id="A7008136E">  0x7008136E:  </span>9003         STR        R0, [SP, #12]
+<br/>.L39:
+<span id="A70081370">  0x70081370:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081372">  0x70081372:  </span>9004         STR        R0, [SP, #16]
+<br/>.L40:
+<span id="A70081374">  0x70081374:  </span>9804         LDR        R0, [SP, #16]
+<span id="A70081376">  0x70081376:  </span>9005         STR        R0, [SP, #20]
+<br/>.L41:
+<span id="A70081378">  0x70081378:  </span>9805         LDR        R0, [SP, #20]
+<span id="A7008137A">  0x7008137A:  </span>9006         STR        R0, [SP, #24]
+<br/>.L42:
+<span id="A7008137C">  0x7008137C:  </span>9806         LDR        R0, [SP, #24]
+<span id="A7008137E">  0x7008137E:  </span>9007         STR        R0, [SP, #28]
+<br/>.L43:
+<span id="A70081380">  0x70081380:  </span>9807         LDR        R0, [SP, #28]
+<span id="A70081382">  0x70081382:  </span>9008         STR        R0, [SP, #32]
+<br/>.L44:
+<span id="A70081384">  0x70081384:  </span>9808         LDR        R0, [SP, #32]
+<span id="A70081386">  0x70081386:  </span>9009         STR        R0, [SP, #36]
+<br/>.L45:
+<span id="A70081388">  0x70081388:  </span>9809         LDR        R0, [SP, #36]
+<span id="A7008138A">  0x7008138A:  </span>900A         STR        R0, [SP, #40]
+<br/>.L46:
+<span id="A7008138C">  0x7008138C:  </span>980A         LDR        R0, [SP, #40]
+<span id="A7008138E">  0x7008138E:  </span>990D         LDR        R1, [SP, #52]
+<span id="A70081390">  0x70081390:  </span>F001 0103    AND        R1, R1, #3
+<span id="A70081394">  0x70081394:  </span>00C9         LSLS       R1, R1, #3
+<span id="A70081396">  0x70081396:  </span>FA00 F101    LSL.W      R1, R0, R1
+<span id="A7008139A">  0x7008139A:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008139C">  0x7008139C:  </span>4308         ORRS       R0, R1
+<span id="A7008139E">  0x7008139E:  </span>900B         STR        R0, [SP, #44]
+<span id="A700813A0">  0x700813A0:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700813A2">  0x700813A2:  </span>990D         LDR        R1, [SP, #52]
+<span id="A700813A4">  0x700813A4:  </span>F021 0103    BIC        R1, R1, #3
+<span id="A700813A8">  0x700813A8:  </span>F245 0260    MOVW       R2, #0x5060
+<span id="A700813AC">  0x700813AC:  </span>F2C5 6202    MOVT       R2, #0x5602
+<span id="A700813B0">  0x700813B0:  </span>5088         STR        R0, [R1, R2]
+<span id="A700813B2">  0x700813B2:  </span>F245 0080    MOVW       R0, #0x5080
+<span id="A700813B6">  0x700813B6:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700813BA">  0x700813BA:  </span>6800         LDR        R0, [R0]
+<span id="A700813BC">  0x700813BC:  </span>900B         STR        R0, [SP, #44]
+<span id="A700813BE">  0x700813BE:  </span>990C         LDR        R1, [SP, #48]
+<span id="A700813C0">  0x700813C0:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700813C2">  0x700813C2:  </span>4388         BICS       R0, R1
+<span id="A700813C4">  0x700813C4:  </span>900B         STR        R0, [SP, #44]
+<span id="A700813C6">  0x700813C6:  </span>980E         LDR        R0, [SP, #56]
+<span id="A700813C8">  0x700813C8:  </span>7980         LDRB       R0, [R0, #6]
+<span id="A700813CA">  0x700813CA:  </span>07C0         LSLS       R0, R0, #31
+<span id="A700813CC">  0x700813CC:  </span>B118         CBZ        R0, .L47                 ; 0x700813D6
+<span id="A700813CE">  0x700813CE:  </span>990C         LDR        R1, [SP, #48]
+<span id="A700813D0">  0x700813D0:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700813D2">  0x700813D2:  </span>4308         ORRS       R0, R1
+<span id="A700813D4">  0x700813D4:  </span>900B         STR        R0, [SP, #44]
+<br/>.L47:
+<span id="A700813D6">  0x700813D6:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700813D8">  0x700813D8:  </span>F245 0180    MOVW       R1, #0x5080
+<span id="A700813DC">  0x700813DC:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A700813E0">  0x700813E0:  </span>6008         STR        R0, [R1]
+<span id="A700813E2">  0x700813E2:  </span>F245 0084    MOVW       R0, #0x5084
+<span id="A700813E6">  0x700813E6:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700813EA">  0x700813EA:  </span>6800         LDR        R0, [R0]
+<span id="A700813EC">  0x700813EC:  </span>900B         STR        R0, [SP, #44]
+<span id="A700813EE">  0x700813EE:  </span>990C         LDR        R1, [SP, #48]
+<span id="A700813F0">  0x700813F0:  </span>980B         LDR        R0, [SP, #44]
+<span id="A700813F2">  0x700813F2:  </span>4388         BICS       R0, R1
+<span id="A700813F4">  0x700813F4:  </span>900B         STR        R0, [SP, #44]
+<span id="A700813F6">  0x700813F6:  </span>980E         LDR        R0, [SP, #56]
+<span id="A700813F8">  0x700813F8:  </span>7980         LDRB       R0, [R0, #6]
+<span id="A700813FA">  0x700813FA:  </span>0780         LSLS       R0, R0, #30
+<span id="A700813FC">  0x700813FC:  </span>2800         CMP        R0, #0
+<span id="A700813FE">  0x700813FE:  </span>D503         BPL        46L48                     ; 0x70081408
+<span id="A70081400">  0x70081400:  </span>990C         LDR        R1, [SP, #48]
+<span id="A70081402">  0x70081402:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081404">  0x70081404:  </span>4308         ORRS       R0, R1
+<span id="A70081406">  0x70081406:  </span>900B         STR        R0, [SP, #44]
+<br/>.L48:
+<span id="A70081408">  0x70081408:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008140A">  0x7008140A:  </span>F245 0184    MOVW       R1, #0x5084
+<span id="A7008140E">  0x7008140E:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081412">  0x70081412:  </span>6008         STR        R0, [R1]
+<span id="A70081414">  0x70081414:  </span>F245 0000    MOVW       R0, #0x5000
+<span id="A70081418">  0x70081418:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008141C">  0x7008141C:  </span>6800         LDR        R0, [R0]
+<span id="A7008141E">  0x7008141E:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081420">  0x70081420:  </span>990C         LDR        R1, [SP, #48]
+<span id="A70081422">  0x70081422:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081424">  0x70081424:  </span>4388         BICS       R0, R1
+<span id="A70081426">  0x70081426:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081428">  0x70081428:  </span>980E         LDR        R0, [SP, #56]
+<span id="A7008142A">  0x7008142A:  </span>7980         LDRB       R0, [R0, #6]
+<span id="A7008142C">  0x7008142C:  </span>06C0         LSLS       R0, R0, #27
+<span id="A7008142E">  0x7008142E:  </span>2800         CMP        R0, #0
+<span id="A70081430">  0x70081430:  </span>D503         BPL        46L49                     ; 0x7008143A
+<span id="A70081432">  0x70081432:  </span>990C         LDR        R1, [SP, #48]
+<span id="A70081434">  0x70081434:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081436">  0x70081436:  </span>4308         ORRS       R0, R1
+<span id="A70081438">  0x70081438:  </span>900B         STR        R0, [SP, #44]
+<br/>.L49:
+<span id="A7008143A">  0x7008143A:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008143C">  0x7008143C:  </span>F245 0100    MOVW       R1, #0x5000
+<span id="A70081440">  0x70081440:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081444">  0x70081444:  </span>6008         STR        R0, [R1]
+<span id="A70081446">  0x70081446:  </span>F245 0004    MOVW       R0, #0x5004
+<span id="A7008144A">  0x7008144A:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008144E">  0x7008144E:  </span>6800         LDR        R0, [R0]
+<span id="A70081450">  0x70081450:  </span>900B         STR        R0, [SP, #44]
+<span id="A70081452">  0x70081452:  </span>990C         LDR        R1, [SP, #48]
+<span id="A70081454">  0x70081454:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081456">  0x70081456:  </span>4388         BICS       R0, R1
+<span id="A70081458">  0x70081458:  </span>900B         STR        R0, [SP, #44]
+<span id="A7008145A">  0x7008145A:  </span>980E         LDR        R0, [SP, #56]
+<span id="A7008145C">  0x7008145C:  </span>7980         LDRB       R0, [R0, #6]
+<span id="A7008145E">  0x7008145E:  </span>0680         LSLS       R0, R0, #26
+<span id="A70081460">  0x70081460:  </span>2800         CMP        R0, #0
+<span id="A70081462">  0x70081462:  </span>D503         BPL        46L50                     ; 0x7008146C
+<span id="A70081464">  0x70081464:  </span>990C         LDR        R1, [SP, #48]
+<span id="A70081466">  0x70081466:  </span>980B         LDR        R0, [SP, #44]
+<span id="A70081468">  0x70081468:  </span>4308         ORRS       R0, R1
+<span id="A7008146A">  0x7008146A:  </span>900B         STR        R0, [SP, #44]
+<br/>.L50:
+<span id="A7008146C">  0x7008146C:  </span>980B         LDR        R0, [SP, #44]
+<span id="A7008146E">  0x7008146E:  </span>F245 0104    MOVW       R1, #0x5004
+<span id="A70081472">  0x70081472:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70081476">  0x70081476:  </span>6008         STR        R0, [R1]
+<br/>.L51:
+<span id="A70081478">  0x70081478:  </span>980D         LDR        R0, [SP, #52]
+<span id="A7008147A">  0x7008147A:  </span>3001         ADDS       R0, #1
+<span id="A7008147C">  0x7008147C:  </span>900D         STR        R0, [SP, #52]
+<span id="A7008147E">  0x7008147E:  </span>E541         B          46L8                      ; 0x70080F04
+<br/>.L52:
+<span id="A70081480">  0x70081480:  </span>B010         ADD        SP, SP, #64
+<span id="A70081482">  0x70081482:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</h2>
+
+<pre>
+<br/><span id="_start">_start:</span>
+<span id="A70081484">  0x70081484:  </span>4C03         LDR        R4, =0x70081A90          ; [PC, #12] [0x70081494] 
+<br/>.L1:
+<span id="A70081486">  0x70081486:  </span>6820         LDR        R0, [R4]
+<span id="A70081488">  0x70081488:  </span>3404         ADDS       R4, #4
+<span id="A7008148A">  0x7008148A:  </span>4780         BLX        R0
+<span id="A7008148C">  0x7008148C:  </span>E7FB         B          46L1                      ; 0x70081486
+<br/><span id="__SEGGER_init_done">__SEGGER_init_done:</span>
+<span id="__startup_complete">__startup_complete:</span>
+<span id="A7008148E">  0x7008148E:  </span>F000 F901    BL         <a href="#main">main</a>                     ; 0x70081694
+<br/><span id="exit">exit:</span>
+<span id="A70081492">  0x70081492:  </span>E7FE         B          <a href="#exit">exit</a>                     ; 0x70081492
+<span id="A70081494">  0x70081494:  </span>70081A90     DC.W       70081A90               ; R_ARM_ABS32
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</h2>
+
+<pre>
+<br/><span id="reset_handler">reset_handler:</span>
+<span id="Reset_Handler">Reset_Handler:</span>
+<span id="A70081498">  0x70081498:  </span>4909         LDR        R1, =0x34062000          ; [PC, #36] [0x700814C0] 
+<span id="A7008149A">  0x7008149A:  </span>F381 880A    MSR        MSPLIM, R1
+<span id="A7008149E">  0x7008149E:  </span>F04F 0100    MOV.W      R1, #0
+<span id="A700814A2">  0x700814A2:  </span>F381 880B    MSR        PSPLIM, R1
+<span id="A700814A6">  0x700814A6:  </span>F7FF F955    BL         <a href="#SystemInit">SystemInit</a>               ; 0x70080754
+<span id="A700814AA">  0x700814AA:  </span>F64E 5088    MOVW       R0, #0xED88
+<span id="A700814AE">  0x700814AE:  </span>F2CE 0000    MOVT       R0, #0xE000
+<span id="A700814B2">  0x700814B2:  </span>6801         LDR        R1, [R0]
+<span id="A700814B4">  0x700814B4:  </span>F451 0170    ORRS       R1, R1, #0xF00000
+<span id="A700814B8">  0x700814B8:  </span>6001         STR        R1, [R0]
+<span id="A700814BA">  0x700814BA:  </span>F7FF FFE3    BL         <a href="#_start">_start</a>                   ; 0x70081484
+<span id="A700814BE">  0x700814BE:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700814BF">  0x700814BF:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700814C0">  0x700814C0:  </span>34062000     DC.W       34062000               ; R_ARM_ABS32
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.MX_GPIO_Init from blto_App_lto.o, size=426, align=4">Section .text.MX_GPIO_Init from blto_App_lto.o, size=426, align=4</h2>
+
+<pre>
+<br/><span id="MX_GPIO_Init">MX_GPIO_Init:</span>
+<span id="A700814C4">  0x700814C4:  </span>B580         PUSH       123R7, LR}
+<span id="A700814C6">  0x700814C6:  </span>B08A         SUB        SP, SP, #40
+<span id="A700814C8">  0x700814C8:  </span>2000         MOVS       R0, #0
+<span id="A700814CA">  0x700814CA:  </span>9003         STR        R0, [SP, #12]
+<span id="A700814CC">  0x700814CC:  </span>9009         STR        R0, [SP, #36]
+<span id="A700814CE">  0x700814CE:  </span>9008         STR        R0, [SP, #32]
+<span id="A700814D0">  0x700814D0:  </span>9007         STR        R0, [SP, #28]
+<span id="A700814D2">  0x700814D2:  </span>9006         STR        R0, [SP, #24]
+<span id="A700814D4">  0x700814D4:  </span>9005         STR        R0, [SP, #20]
+<span id="A700814D6">  0x700814D6:  </span>F44F 3080    MOV.W      R0, #0x010000
+<span id="A700814DA">  0x700814DA:  </span>F000 F8C9    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814DE">  0x700814DE:  </span>2004         MOVS       R0, #4
+<span id="A700814E0">  0x700814E0:  </span>F000 F8C6    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814E4">  0x700814E4:  </span>2010         MOVS       R0, #16
+<span id="A700814E6">  0x700814E6:  </span>F000 F8C3    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814EA">  0x700814EA:  </span>2008         MOVS       R0, #8
+<span id="A700814EC">  0x700814EC:  </span>F000 F8C0    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814F0">  0x700814F0:  </span>2080         MOVS       R0, #128
+<span id="A700814F2">  0x700814F2:  </span>F000 F8BD    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814F6">  0x700814F6:  </span>2002         MOVS       R0, #2
+<span id="A700814F8">  0x700814F8:  </span>F000 F8BA    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A700814FC">  0x700814FC:  </span>F44F 4000    MOV.W      R0, #0x8000
+<span id="A70081500">  0x70081500:  </span>F000 F8B6    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A70081504">  0x70081504:  </span>F44F 4080    MOV.W      R0, #0x4000
+<span id="A70081508">  0x70081508:  </span>F000 F8B2    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A7008150C">  0x7008150C:  </span>2040         MOVS       R0, #64
+<span id="A7008150E">  0x7008150E:  </span>F000 F8AF    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A70081512">  0x70081512:  </span>2020         MOVS       R0, #32
+<span id="A70081514">  0x70081514:  </span>F000 F8AC    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A70081518">  0x70081518:  </span>F44F 5000    MOV.W      R0, #0x2000
+<span id="A7008151C">  0x7008151C:  </span>F000 F8A8    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A70081520">  0x70081520:  </span>2001         MOVS       R0, #1
+<span id="A70081522">  0x70081522:  </span>F000 F8A5    BL         <a href="#LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock</a> ; 0x70081670
+<span id="A70081526">  0x70081526:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081528">  0x70081528:  </span>21FF         MOVS       R1, #255
+<span id="A7008152A">  0x7008152A:  </span>9105         STR        R1, [SP, #20]
+<span id="A7008152C">  0x7008152C:  </span>2103         MOVS       R1, #3
+<span id="A7008152E">  0x7008152E:  </span>9102         STR        R1, [SP, #8]
+<span id="A70081530">  0x70081530:  </span>9106         STR        R1, [SP, #24]
+<span id="A70081532">  0x70081532:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081534">  0x70081534:  </span>F244 0000    MOVW       R0, #0x4000
+<span id="A70081538">  0x70081538:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008153C">  0x7008153C:  </span>A905         ADD        R1, SP, #20
+<span id="A7008153E">  0x7008153E:  </span>9104         STR        R1, [SP, #16]
+<span id="A70081540">  0x70081540:  </span>F7FF FBDC    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081544">  0x70081544:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081546">  0x70081546:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081548">  0x70081548:  </span>9904         LDR        R1, [SP, #16]
+<span id="A7008154A">  0x7008154A:  </span>F643 73FF    MOVW       R3, #0x3FFF
+<span id="A7008154E">  0x7008154E:  </span>9305         STR        R3, [SP, #20]
+<span id="A70081550">  0x70081550:  </span>9206         STR        R2, [SP, #24]
+<span id="A70081552">  0x70081552:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081554">  0x70081554:  </span>F640 0000    MOVW       R0, #0x0800
+<span id="A70081558">  0x70081558:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008155C">  0x7008155C:  </span>F7FF FBCE    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081560">  0x70081560:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081562">  0x70081562:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081564">  0x70081564:  </span>9904         LDR        R1, [SP, #16]
+<span id="A70081566">  0x70081566:  </span>F64F 73FF    MOVW       R3, #0xFFFF
+<span id="A7008156A">  0x7008156A:  </span>9301         STR        R3, [SP, #4]
+<span id="A7008156C">  0x7008156C:  </span>9305         STR        R3, [SP, #20]
+<span id="A7008156E">  0x7008156E:  </span>9206         STR        R2, [SP, #24]
+<span id="A70081570">  0x70081570:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081572">  0x70081572:  </span>F241 0000    MOVW       R0, #0x1000
+<span id="A70081576">  0x70081576:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008157A">  0x7008157A:  </span>F7FF FBBF    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A7008157E">  0x7008157E:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A70081580">  0x70081580:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081582">  0x70081582:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081584">  0x70081584:  </span>9904         LDR        R1, [SP, #16]
+<span id="A70081586">  0x70081586:  </span>9305         STR        R3, [SP, #20]
+<span id="A70081588">  0x70081588:  </span>9206         STR        R2, [SP, #24]
+<span id="A7008158A">  0x7008158A:  </span>9007         STR        R0, [SP, #28]
+<span id="A7008158C">  0x7008158C:  </span>F640 4000    MOVW       R0, #0x0C00
+<span id="A70081590">  0x70081590:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70081594">  0x70081594:  </span>F7FF FBB2    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081598">  0x70081598:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A7008159A">  0x7008159A:  </span>9803         LDR        R0, [SP, #12]
+<span id="A7008159C">  0x7008159C:  </span>9904         LDR        R1, [SP, #16]
+<span id="A7008159E">  0x7008159E:  </span>F44F 737F    MOV.W      R3, #0x03FC
+<span id="A700815A2">  0x700815A2:  </span>9305         STR        R3, [SP, #20]
+<span id="A700815A4">  0x700815A4:  </span>9206         STR        R2, [SP, #24]
+<span id="A700815A6">  0x700815A6:  </span>9007         STR        R0, [SP, #28]
+<span id="A700815A8">  0x700815A8:  </span>F641 4000    MOVW       R0, #0x1C00
+<span id="A700815AC">  0x700815AC:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700815B0">  0x700815B0:  </span>F7FF FBA4    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A700815B4">  0x700815B4:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A700815B6">  0x700815B6:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A700815B8">  0x700815B8:  </span>9803         LDR        R0, [SP, #12]
+<span id="A700815BA">  0x700815BA:  </span>9904         LDR        R1, [SP, #16]
+<span id="A700815BC">  0x700815BC:  </span>9305         STR        R3, [SP, #20]
+<span id="A700815BE">  0x700815BE:  </span>9206         STR        R2, [SP, #24]
+<span id="A700815C0">  0x700815C0:  </span>9007         STR        R0, [SP, #28]
+<span id="A700815C2">  0x700815C2:  </span>F240 4000    MOVW       R0, #0x0400
+<span id="A700815C6">  0x700815C6:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700815CA">  0x700815CA:  </span>F7FF FB97    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A700815CE">  0x700815CE:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A700815D0">  0x700815D0:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A700815D2">  0x700815D2:  </span>9803         LDR        R0, [SP, #12]
+<span id="A700815D4">  0x700815D4:  </span>9904         LDR        R1, [SP, #16]
+<span id="A700815D6">  0x700815D6:  </span>9305         STR        R3, [SP, #20]
+<span id="A700815D8">  0x700815D8:  </span>9206         STR        R2, [SP, #24]
+<span id="A700815DA">  0x700815DA:  </span>9007         STR        R0, [SP, #28]
+<span id="A700815DC">  0x700815DC:  </span>F643 4000    MOVW       R0, #0x3C00
+<span id="A700815E0">  0x700815E0:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700815E4">  0x700815E4:  </span>F7FF FB8A    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A700815E8">  0x700815E8:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A700815EA">  0x700815EA:  </span>9803         LDR        R0, [SP, #12]
+<span id="A700815EC">  0x700815EC:  </span>9904         LDR        R1, [SP, #16]
+<span id="A700815EE">  0x700815EE:  </span>233F         MOVS       R3, #63
+<span id="A700815F0">  0x700815F0:  </span>9305         STR        R3, [SP, #20]
+<span id="A700815F2">  0x700815F2:  </span>9206         STR        R2, [SP, #24]
+<span id="A700815F4">  0x700815F4:  </span>9007         STR        R0, [SP, #28]
+<span id="A700815F6">  0x700815F6:  </span>F643 0000    MOVW       R0, #0x3800
+<span id="A700815FA">  0x700815FA:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A700815FE">  0x700815FE:  </span>F7FF FB7D    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081602">  0x70081602:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A70081604">  0x70081604:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081606">  0x70081606:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081608">  0x70081608:  </span>9904         LDR        R1, [SP, #16]
+<span id="A7008160A">  0x7008160A:  </span>9305         STR        R3, [SP, #20]
+<span id="A7008160C">  0x7008160C:  </span>9206         STR        R2, [SP, #24]
+<span id="A7008160E">  0x7008160E:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081610">  0x70081610:  </span>F641 0000    MOVW       R0, #0x1800
+<span id="A70081614">  0x70081614:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70081618">  0x70081618:  </span>F7FF FB70    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A7008161C">  0x7008161C:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A7008161E">  0x7008161E:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081620">  0x70081620:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081622">  0x70081622:  </span>9904         LDR        R1, [SP, #16]
+<span id="A70081624">  0x70081624:  </span>9305         STR        R3, [SP, #20]
+<span id="A70081626">  0x70081626:  </span>9206         STR        R2, [SP, #24]
+<span id="A70081628">  0x70081628:  </span>9007         STR        R0, [SP, #28]
+<span id="A7008162A">  0x7008162A:  </span>F241 4000    MOVW       R0, #0x1400
+<span id="A7008162E">  0x7008162E:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70081632">  0x70081632:  </span>F7FF FB63    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081636">  0x70081636:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081638">  0x70081638:  </span>9803         LDR        R0, [SP, #12]
+<span id="A7008163A">  0x7008163A:  </span>9904         LDR        R1, [SP, #16]
+<span id="A7008163C">  0x7008163C:  </span>F641 73FF    MOVW       R3, #0x1FFF
+<span id="A70081640">  0x70081640:  </span>9305         STR        R3, [SP, #20]
+<span id="A70081642">  0x70081642:  </span>9206         STR        R2, [SP, #24]
+<span id="A70081644">  0x70081644:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081646">  0x70081646:  </span>F243 4000    MOVW       R0, #0x3400
+<span id="A7008164A">  0x7008164A:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A7008164E">  0x7008164E:  </span>F7FF FB55    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A70081652">  0x70081652:  </span>9B01         LDR        R3, [SP, #4]
+<span id="A70081654">  0x70081654:  </span>9A02         LDR        R2, [SP, #8]
+<span id="A70081656">  0x70081656:  </span>9803         LDR        R0, [SP, #12]
+<span id="A70081658">  0x70081658:  </span>9904         LDR        R1, [SP, #16]
+<span id="A7008165A">  0x7008165A:  </span>9305         STR        R3, [SP, #20]
+<span id="A7008165C">  0x7008165C:  </span>9206         STR        R2, [SP, #24]
+<span id="A7008165E">  0x7008165E:  </span>9007         STR        R0, [SP, #28]
+<span id="A70081660">  0x70081660:  </span>2000         MOVS       R0, #0
+<span id="A70081662">  0x70081662:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70081666">  0x70081666:  </span>F7FF FB49    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x70080CFC
+<span id="A7008166A">  0x7008166A:  </span>B00A         ADD        SP, SP, #40
+<span id="A7008166C">  0x7008166C:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="PVD_PVM_IRQHandler">PVD_PVM_IRQHandler:</span>
+<span id="A7008166E">  0x7008166E:  </span>E7FE         B          <a href="#PVD_PVM_IRQHandler">PVD_PVM_IRQHandler</a>       ; 0x7008166E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.LL_AHB4_GRP1_EnableClock from blto_App_lto.o, size=34, align=4">Section .text.LL_AHB4_GRP1_EnableClock from blto_App_lto.o, size=34, align=4</h2>
+
+<pre>
+<br/><span id="LL_AHB4_GRP1_EnableClock">LL_AHB4_GRP1_EnableClock:</span>
+<span id="A70081670">  0x70081670:  </span>B082         SUB        SP, SP, #8
+<span id="A70081672">  0x70081672:  </span>9001         STR        R0, [SP, #4]
+<span id="A70081674">  0x70081674:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70081676">  0x70081676:  </span>F648 215C    MOVW       R1, #0x8A5C
+<span id="A7008167A">  0x7008167A:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A7008167E">  0x7008167E:  </span>6008         STR        R0, [R1]
+<span id="A70081680">  0x70081680:  </span>F248 205C    MOVW       R0, #0x825C
+<span id="A70081684">  0x70081684:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70081688">  0x70081688:  </span>6800         LDR        R0, [R0]
+<span id="A7008168A">  0x7008168A:  </span>9000         STR        R0, [SP, #0]
+<span id="A7008168C">  0x7008168C:  </span>9800         LDR        R0, [SP, #0]
+<span id="A7008168E">  0x7008168E:  </span>B002         ADD        SP, SP, #8
+<span id="A70081690">  0x70081690:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="DTS_IRQHandler">DTS_IRQHandler:</span>
+<span id="A70081692">  0x70081692:  </span>E7FE         B          <a href="#DTS_IRQHandler">DTS_IRQHandler</a>           ; 0x70081692
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.main from blto_App_lto.o, size=18, align=4">Section .text.main from blto_App_lto.o, size=18, align=4</h2>
+
+<pre>
+<br/><span id="main">main:</span>
+<span id="A70081694">  0x70081694:  </span>B580         PUSH       123R7, LR}
+<span id="A70081696">  0x70081696:  </span>B082         SUB        SP, SP, #8
+<span id="A70081698">  0x70081698:  </span>2000         MOVS       R0, #0
+<span id="A7008169A">  0x7008169A:  </span>9001         STR        R0, [SP, #4]
+<span id="A7008169C">  0x7008169C:  </span>F7FF FA62    BL         <a href="#HAL_Init">HAL_Init</a>                 ; 0x70080B64
+<span id="A700816A0">  0x700816A0:  </span>F7FF FF10    BL         <a href="#MX_GPIO_Init">MX_GPIO_Init</a>             ; 0x700814C4
+<br/>.L1:
+<span id="A700816A4">  0x700816A4:  </span>E7FE         B          46L1                      ; 0x700816A4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RCC_IRQHandler">RCC_IRQHandler:</span>
+<span id="A700816A6">  0x700816A6:  </span>E7FE         B          <a href="#RCC_IRQHandler">RCC_IRQHandler</a>           ; 0x700816A6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.assert_failed from blto_App_lto.o, size=10, align=4">Section .text.assert_failed from blto_App_lto.o, size=10, align=4</h2>
+
+<pre>
+<br/><span id="assert_failed">assert_failed:</span>
+<span id="A700816A8">  0x700816A8:  </span>B082         SUB        SP, SP, #8
+<span id="A700816AA">  0x700816AA:  </span>9001         STR        R0, [SP, #4]
+<span id="A700816AC">  0x700816AC:  </span>9100         STR        R1, [SP, #0]
+<span id="A700816AE">  0x700816AE:  </span>B002         ADD        SP, SP, #8
+<span id="A700816B0">  0x700816B0:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LOCKUP_IRQHandler">LOCKUP_IRQHandler:</span>
+<span id="A700816B2">  0x700816B2:  </span>E7FE         B          <a href="#LOCKUP_IRQHandler">LOCKUP_IRQHandler</a>        ; 0x700816B2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_MspInit from blto_App_lto.o, size=2, align=4">Section .text.HAL_MspInit from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="HAL_MspInit">HAL_MspInit:</span>
+<span id="A700816B4">  0x700816B4:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler:</span>
+<span id="A700816B6">  0x700816B6:  </span>E7FE         B          <a href="#CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler</a>     ; 0x700816B6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4">Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="NMI_Handler">NMI_Handler:</span>
+<span id="A700816B8">  0x700816B8:  </span>E7FE         B          <a href="#NMI_Handler">NMI_Handler</a>              ; 0x700816B8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TCM_ECC_IRQHandler">TCM_ECC_IRQHandler:</span>
+<span id="A700816BA">  0x700816BA:  </span>E7FE         B          <a href="#TCM_ECC_IRQHandler">TCM_ECC_IRQHandler</a>       ; 0x700816BA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HardFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.HardFault_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="HardFault_Handler">HardFault_Handler:</span>
+<span id="A700816BC">  0x700816BC:  </span>E7FE         B          <a href="#HardFault_Handler">HardFault_Handler</a>        ; 0x700816BC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="BCK_ECC_IRQHandler">BCK_ECC_IRQHandler:</span>
+<span id="A700816BE">  0x700816BE:  </span>E7FE         B          <a href="#BCK_ECC_IRQHandler">BCK_ECC_IRQHandler</a>       ; 0x700816BE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.MemManage_Handler from blto_App_lto.o, size=2, align=4">Section .text.MemManage_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="MemManage_Handler">MemManage_Handler:</span>
+<span id="A700816C0">  0x700816C0:  </span>E7FE         B          <a href="#MemManage_Handler">MemManage_Handler</a>        ; 0x700816C0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FPU_IRQHandler">FPU_IRQHandler:</span>
+<span id="A700816C2">  0x700816C2:  </span>E7FE         B          <a href="#FPU_IRQHandler">FPU_IRQHandler</a>           ; 0x700816C2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.BusFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.BusFault_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="BusFault_Handler">BusFault_Handler:</span>
+<span id="A700816C4">  0x700816C4:  </span>E7FE         B          <a href="#BusFault_Handler">BusFault_Handler</a>         ; 0x700816C4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RTC_S_IRQHandler">RTC_S_IRQHandler:</span>
+<span id="A700816C6">  0x700816C6:  </span>E7FE         B          <a href="#RTC_S_IRQHandler">RTC_S_IRQHandler</a>         ; 0x700816C6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.UsageFault_Handler from blto_App_lto.o, size=2, align=4">Section .text.UsageFault_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="UsageFault_Handler">UsageFault_Handler:</span>
+<span id="A700816C8">  0x700816C8:  </span>E7FE         B          <a href="#UsageFault_Handler">UsageFault_Handler</a>       ; 0x700816C8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TAMP_IRQHandler">TAMP_IRQHandler:</span>
+<span id="A700816CA">  0x700816CA:  </span>E7FE         B          <a href="#TAMP_IRQHandler">TAMP_IRQHandler</a>          ; 0x700816CA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SVC_Handler from blto_App_lto.o, size=2, align=4">Section .text.SVC_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="SVC_Handler">SVC_Handler:</span>
+<span id="A700816CC">  0x700816CC:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler:</span>
+<span id="A700816CE">  0x700816CE:  </span>E7FE         B          <a href="#RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler</a>  ; 0x700816CE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.DebugMon_Handler from blto_App_lto.o, size=2, align=4">Section .text.DebugMon_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="DebugMon_Handler">DebugMon_Handler:</span>
+<span id="A700816D0">  0x700816D0:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="IAC_IRQHandler">IAC_IRQHandler:</span>
+<span id="A700816D2">  0x700816D2:  </span>E7FE         B          <a href="#IAC_IRQHandler">IAC_IRQHandler</a>           ; 0x700816D2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.PendSV_Handler from blto_App_lto.o, size=2, align=4">Section .text.PendSV_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="PendSV_Handler">PendSV_Handler:</span>
+<span id="A700816D4">  0x700816D4:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RCC_S_IRQHandler">RCC_S_IRQHandler:</span>
+<span id="A700816D6">  0x700816D6:  </span>E7FE         B          <a href="#RCC_S_IRQHandler">RCC_S_IRQHandler</a>         ; 0x700816D6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_InitTick from blto_App_lto.o, size=126, align=4">Section .text.HAL_InitTick from blto_App_lto.o, size=126, align=4</h2>
+
+<pre>
+<br/><span id="HAL_InitTick">HAL_InitTick:</span>
+<span id="A700816D8">  0x700816D8:  </span>B580         PUSH       123R7, LR}
+<span id="A700816DA">  0x700816DA:  </span>B082         SUB        SP, SP, #8
+<span id="A700816DC">  0x700816DC:  </span>9000         STR        R0, [SP, #0]
+<span id="A700816DE">  0x700816DE:  </span>F240 000C    MOVW       R0, #12                  ; 0x3400000C = uwTickFreq
+<span id="A700816E2">  0x700816E2:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x3400000C = uwTickFreq
+<span id="A700816E6">  0x700816E6:  </span>7800         LDRB       R0, [R0]
+<span id="A700816E8">  0x700816E8:  </span>B918         CBNZ       R0, .L1                  ; 0x700816F2
+<span id="A700816EA">  0x700816EA:  </span>2001         MOVS       R0, #1
+<span id="A700816EC">  0x700816EC:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<span id="A700816F0">  0x700816F0:  </span>E02D         B          46L5                      ; 0x7008174E
+<br/>.L1:
+<span id="A700816F2">  0x700816F2:  </span>F240 0008    MOVW       R0, #8                   ; 0x34000008 = SystemCoreClock
+<span id="A700816F6">  0x700816F6:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x34000008 = SystemCoreClock
+<span id="A700816FA">  0x700816FA:  </span>6800         LDR        R0, [R0]
+<span id="A700816FC">  0x700816FC:  </span>F240 010C    MOVW       R1, #12                  ; 0x3400000C = uwTickFreq
+<span id="A70081700">  0x70081700:  </span>F2C3 4100    MOVT       R1, #0x3400              ; 0x3400000C = uwTickFreq
+<span id="A70081704">  0x70081704:  </span>780A         LDRB       R2, [R1]
+<span id="A70081706">  0x70081706:  </span>F44F 717A    MOV.W      R1, #0x03E8
+<span id="A7008170A">  0x7008170A:  </span>FBB1 F1F2    UDIV       R1, R1, R2
+<span id="A7008170E">  0x7008170E:  </span>FBB0 F0F1    UDIV       R0, R0, R1
+<span id="A70081712">  0x70081712:  </span>F7FF FAEB    BL         <a href="#HAL_SYSTICK_Config">HAL_SYSTICK_Config</a>       ; 0x70080CEC
+<span id="A70081716">  0x70081716:  </span>B118         CBZ        R0, .L2                  ; 0x70081720
+<span id="A70081718">  0x70081718:  </span>2001         MOVS       R0, #1
+<span id="A7008171A">  0x7008171A:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<span id="A7008171E">  0x7008171E:  </span>E016         B          46L5                      ; 0x7008174E
+<br/>.L2:
+<span id="A70081720">  0x70081720:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70081722">  0x70081722:  </span>280F         CMP        R0, #15
+<span id="A70081724">  0x70081724:  </span>D80C         BHI        46L3                      ; 0x70081740
+<span id="A70081726">  0x70081726:  </span>9900         LDR        R1, [SP, #0]
+<span id="A70081728">  0x70081728:  </span>F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+<span id="A7008172C">  0x7008172C:  </span>2200         MOVS       R2, #0
+<span id="A7008172E">  0x7008172E:  </span>F7FF FA4F    BL         <a href="#HAL_NVIC_SetPriority">HAL_NVIC_SetPriority</a>     ; 0x70080BD0
+<span id="A70081732">  0x70081732:  </span>9800         LDR        R0, [SP, #0]
+<span id="A70081734">  0x70081734:  </span>F240 0104    MOVW       R1, #4                   ; 0x34000004 = uwTickPrio
+<span id="A70081738">  0x70081738:  </span>F2C3 4100    MOVT       R1, #0x3400              ; 0x34000004 = uwTickPrio
+<span id="A7008173C">  0x7008173C:  </span>6008         STR        R0, [R1]
+<span id="A7008173E">  0x7008173E:  </span>E003         B          46L4                      ; 0x70081748
+<br/>.L3:
+<span id="A70081740">  0x70081740:  </span>2001         MOVS       R0, #1
+<span id="A70081742">  0x70081742:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<span id="A70081746">  0x70081746:  </span>E002         B          46L5                      ; 0x7008174E
+<br/>.L4:
+<span id="A70081748">  0x70081748:  </span>2000         MOVS       R0, #0
+<span id="A7008174A">  0x7008174A:  </span>F88D 0007    STRB.W     R0, [SP, #7]
+<br/>.L5:
+<span id="A7008174E">  0x7008174E:  </span>F89D 0007    LDRB.W     R0, [SP, #7]
+<span id="A70081752">  0x70081752:  </span>B002         ADD        SP, SP, #8
+<span id="A70081754">  0x70081754:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RTC_IRQHandler">RTC_IRQHandler:</span>
+<span id="A70081756">  0x70081756:  </span>E7FE         B          <a href="#RTC_IRQHandler">RTC_IRQHandler</a>           ; 0x70081756
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_IncTick from blto_App_lto.o, size=26, align=4">Section .text.HAL_IncTick from blto_App_lto.o, size=26, align=4</h2>
+
+<pre>
+<br/><span id="HAL_IncTick">HAL_IncTick:</span>
+<span id="A70081758">  0x70081758:  </span>F240 000C    MOVW       R0, #12                  ; 0x3400000C = uwTickFreq
+<span id="A7008175C">  0x7008175C:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x3400000C = uwTickFreq
+<span id="A70081760">  0x70081760:  </span>7802         LDRB       R2, [R0]
+<span id="A70081762">  0x70081762:  </span>F240 0100    MOVW       R1, #0                   ; 0x34000000 = uwTick
+<span id="A70081766">  0x70081766:  </span>F2C3 4100    MOVT       R1, #0x3400              ; 0x34000000 = uwTick
+<span id="A7008176A">  0x7008176A:  </span>6808         LDR        R0, [R1]
+<span id="A7008176C">  0x7008176C:  </span>4410         ADD        R0, R2
+<span id="A7008176E">  0x7008176E:  </span>6008         STR        R0, [R1]
+<span id="A70081770">  0x70081770:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="IWDG_IRQHandler">IWDG_IRQHandler:</span>
+<span id="A70081772">  0x70081772:  </span>E7FE         B          <a href="#IWDG_IRQHandler">IWDG_IRQHandler</a>          ; 0x70081772
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_NVIC_SetPriorityGrouping from blto_App_lto.o, size=62, align=4">Section .text.HAL_NVIC_SetPriorityGrouping from blto_App_lto.o, size=62, align=4</h2>
+
+<pre>
+<br/><span id="HAL_NVIC_SetPriorityGrouping">HAL_NVIC_SetPriorityGrouping:</span>
+<span id="A70081774">  0x70081774:  </span>B580         PUSH       123R7, LR}
+<span id="A70081776">  0x70081776:  </span>B082         SUB        SP, SP, #8
+<span id="A70081778">  0x70081778:  </span>9001         STR        R0, [SP, #4]
+<span id="A7008177A">  0x7008177A:  </span>9801         LDR        R0, [SP, #4]
+<span id="A7008177C">  0x7008177C:  </span>2807         CMP        R0, #7
+<span id="A7008177E">  0x7008177E:  </span>D00B         BEQ        46L1                      ; 0x70081798
+<span id="A70081780">  0x70081780:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70081782">  0x70081782:  </span>2806         CMP        R0, #6
+<span id="A70081784">  0x70081784:  </span>D008         BEQ        46L1                      ; 0x70081798
+<span id="A70081786">  0x70081786:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70081788">  0x70081788:  </span>2805         CMP        R0, #5
+<span id="A7008178A">  0x7008178A:  </span>D005         BEQ        46L1                      ; 0x70081798
+<span id="A7008178C">  0x7008178C:  </span>9801         LDR        R0, [SP, #4]
+<span id="A7008178E">  0x7008178E:  </span>2804         CMP        R0, #4
+<span id="A70081790">  0x70081790:  </span>D002         BEQ        46L1                      ; 0x70081798
+<span id="A70081792">  0x70081792:  </span>9801         LDR        R0, [SP, #4]
+<span id="A70081794">  0x70081794:  </span>2803         CMP        R0, #3
+<span id="A70081796">  0x70081796:  </span>D100         BNE        46L2                      ; 0x7008179A
+<br/>.L1:
+<span id="A70081798">  0x70081798:  </span>E006         B          46L3                      ; 0x700817A8
+<br/>.L2:
+<span id="A7008179A">  0x7008179A:  </span>F641 1094    MOVW       R0, #0x1994              ; 0x70081994 = .rodata..L.str.7
+<span id="A7008179E">  0x7008179E:  </span>F2C7 0008    MOVT       R0, #0x7008              ; 0x70081994 = .rodata..L.str.7
+<span id="A700817A2">  0x700817A2:  </span>21E6         MOVS       R1, #230
+<span id="A700817A4">  0x700817A4:  </span>F7FF FF80    BL         <a href="#assert_failed">assert_failed</a>            ; 0x700816A8
+<br/>.L3:
+<span id="A700817A8">  0x700817A8:  </span>9801         LDR        R0, [SP, #4]
+<span id="A700817AA">  0x700817AA:  </span>F7FF F9F3    BL         <a href="#__NVIC_SetPriorityGrouping">__NVIC_SetPriorityGrouping</a> ; 0x70080B94
+<span id="A700817AE">  0x700817AE:  </span>B002         ADD        SP, SP, #8
+<span id="A700817B0">  0x700817B0:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="WWDG_IRQHandler">WWDG_IRQHandler:</span>
+<span id="A700817B2">  0x700817B2:  </span>E7FE         B          <a href="#WWDG_IRQHandler">WWDG_IRQHandler</a>          ; 0x700817B2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.__NVIC_SetPriority from blto_App_lto.o, size=62, align=4">Section .text.__NVIC_SetPriority from blto_App_lto.o, size=62, align=4</h2>
+
+<pre>
+<br/><span id="__NVIC_SetPriority">__NVIC_SetPriority:</span>
+<span id="A700817B4">  0x700817B4:  </span>B082         SUB        SP, SP, #8
+<span id="A700817B6">  0x700817B6:  </span>F8AD 0006    STRH.W     R0, [SP, #6]
+<span id="A700817BA">  0x700817BA:  </span>9100         STR        R1, [SP, #0]
+<span id="A700817BC">  0x700817BC:  </span>F9BD 0006    LDRSH.W    R0, [SP, #6]
+<span id="A700817C0">  0x700817C0:  </span>2800         CMP        R0, #0
+<span id="A700817C2">  0x700817C2:  </span>D409         BMI        46L1                      ; 0x700817D8
+<span id="A700817C4">  0x700817C4:  </span>9800         LDR        R0, [SP, #0]
+<span id="A700817C6">  0x700817C6:  </span>0100         LSLS       R0, R0, #4
+<span id="A700817C8">  0x700817C8:  </span>F9BD 1006    LDRSH.W    R1, [SP, #6]
+<span id="A700817CC">  0x700817CC:  </span>F24E 4200    MOVW       R2, #0xE400
+<span id="A700817D0">  0x700817D0:  </span>F2CE 0200    MOVT       R2, #0xE000
+<span id="A700817D4">  0x700817D4:  </span>5488         STRB       R0, [R1, R2]
+<span id="A700817D6">  0x700817D6:  </span>E00A         B          46L2                      ; 0x700817EE
+<br/>.L1:
+<span id="A700817D8">  0x700817D8:  </span>9800         LDR        R0, [SP, #0]
+<span id="A700817DA">  0x700817DA:  </span>0100         LSLS       R0, R0, #4
+<span id="A700817DC">  0x700817DC:  </span>F8BD 1006    LDRH.W     R1, [SP, #6]
+<span id="A700817E0">  0x700817E0:  </span>F001 010F    AND        R1, R1, #15
+<span id="A700817E4">  0x700817E4:  </span>F64E 5214    MOVW       R2, #0xED14
+<span id="A700817E8">  0x700817E8:  </span>F2CE 0200    MOVT       R2, #0xE000
+<span id="A700817EC">  0x700817EC:  </span>5488         STRB       R0, [R1, R2]
+<br/>.L2:
+<span id="A700817EE">  0x700817EE:  </span>B002         ADD        SP, SP, #8
+<span id="A700817F0">  0x700817F0:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI0_IRQHandler">EXTI0_IRQHandler:</span>
+<span id="A700817F2">  0x700817F2:  </span>E7FE         B          <a href="#EXTI0_IRQHandler">EXTI0_IRQHandler</a>         ; 0x700817F2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SysTick_Config from blto_App_lto.o, size=78, align=4">Section .text.SysTick_Config from blto_App_lto.o, size=78, align=4</h2>
+
+<pre>
+<br/><span id="SysTick_Config">SysTick_Config:</span>
+<span id="A700817F4">  0x700817F4:  </span>B580         PUSH       123R7, LR}
+<span id="A700817F6">  0x700817F6:  </span>B082         SUB        SP, SP, #8
+<span id="A700817F8">  0x700817F8:  </span>9000         STR        R0, [SP, #0]
+<span id="A700817FA">  0x700817FA:  </span>9800         LDR        R0, [SP, #0]
+<span id="A700817FC">  0x700817FC:  </span>3801         SUBS       R0, #1
+<span id="A700817FE">  0x700817FE:  </span>F1B0 7F80    CMP.W      R0, #0x01000000
+<span id="A70081802">  0x70081802:  </span>D302         BCC        46L1                      ; 0x7008180A
+<span id="A70081804">  0x70081804:  </span>2001         MOVS       R0, #1
+<span id="A70081806">  0x70081806:  </span>9001         STR        R0, [SP, #4]
+<span id="A70081808">  0x70081808:  </span>E018         B          46L2                      ; 0x7008183C
+<br/>.L1:
+<span id="A7008180A">  0x7008180A:  </span>9800         LDR        R0, [SP, #0]
+<span id="A7008180C">  0x7008180C:  </span>3801         SUBS       R0, #1
+<span id="A7008180E">  0x7008180E:  </span>F24E 0114    MOVW       R1, #0xE014
+<span id="A70081812">  0x70081812:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A70081816">  0x70081816:  </span>6008         STR        R0, [R1]
+<span id="A70081818">  0x70081818:  </span>F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+<span id="A7008181C">  0x7008181C:  </span>210F         MOVS       R1, #15
+<span id="A7008181E">  0x7008181E:  </span>F7FF FFC9    BL         <a href="#__NVIC_SetPriority">__NVIC_SetPriority</a>       ; 0x700817B4
+<span id="A70081822">  0x70081822:  </span>F24E 0118    MOVW       R1, #0xE018
+<span id="A70081826">  0x70081826:  </span>F2CE 0100    MOVT       R1, #0xE000
+<span id="A7008182A">  0x7008182A:  </span>2000         MOVS       R0, #0
+<span id="A7008182C">  0x7008182C:  </span>6008         STR        R0, [R1]
+<span id="A7008182E">  0x7008182E:  </span>F24E 0210    MOVW       R2, #0xE010
+<span id="A70081832">  0x70081832:  </span>F2CE 0200    MOVT       R2, #0xE000
+<span id="A70081836">  0x70081836:  </span>2107         MOVS       R1, #7
+<span id="A70081838">  0x70081838:  </span>6011         STR        R1, [R2]
+<span id="A7008183A">  0x7008183A:  </span>9001         STR        R0, [SP, #4]
+<br/>.L2:
+<span id="A7008183C">  0x7008183C:  </span>9801         LDR        R0, [SP, #4]
+<span id="A7008183E">  0x7008183E:  </span>B002         ADD        SP, SP, #8
+<span id="A70081840">  0x70081840:  </span>BD80         POP        123R7, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI1_IRQHandler">EXTI1_IRQHandler:</span>
+<span id="A70081842">  0x70081842:  </span>E7FE         B          <a href="#EXTI1_IRQHandler">EXTI1_IRQHandler</a>         ; 0x70081842
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI2_IRQHandler">EXTI2_IRQHandler:</span>
+<span id="A70081844">  0x70081844:  </span>E7FE         B          <a href="#EXTI2_IRQHandler">EXTI2_IRQHandler</a>         ; 0x70081844
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI3_IRQHandler">EXTI3_IRQHandler:</span>
+<span id="A70081846">  0x70081846:  </span>E7FE         B          <a href="#EXTI3_IRQHandler">EXTI3_IRQHandler</a>         ; 0x70081846
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI4_IRQHandler">EXTI4_IRQHandler:</span>
+<span id="A70081848">  0x70081848:  </span>E7FE         B          <a href="#EXTI4_IRQHandler">EXTI4_IRQHandler</a>         ; 0x70081848
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI5_IRQHandler">EXTI5_IRQHandler:</span>
+<span id="A7008184A">  0x7008184A:  </span>E7FE         B          <a href="#EXTI5_IRQHandler">EXTI5_IRQHandler</a>         ; 0x7008184A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI6_IRQHandler">EXTI6_IRQHandler:</span>
+<span id="A7008184C">  0x7008184C:  </span>E7FE         B          <a href="#EXTI6_IRQHandler">EXTI6_IRQHandler</a>         ; 0x7008184C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI7_IRQHandler">EXTI7_IRQHandler:</span>
+<span id="A7008184E">  0x7008184E:  </span>E7FE         B          <a href="#EXTI7_IRQHandler">EXTI7_IRQHandler</a>         ; 0x7008184E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI8_IRQHandler">EXTI8_IRQHandler:</span>
+<span id="A70081850">  0x70081850:  </span>E7FE         B          <a href="#EXTI8_IRQHandler">EXTI8_IRQHandler</a>         ; 0x70081850
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI9_IRQHandler">EXTI9_IRQHandler:</span>
+<span id="A70081852">  0x70081852:  </span>E7FE         B          <a href="#EXTI9_IRQHandler">EXTI9_IRQHandler</a>         ; 0x70081852
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI10_IRQHandler">EXTI10_IRQHandler:</span>
+<span id="A70081854">  0x70081854:  </span>E7FE         B          <a href="#EXTI10_IRQHandler">EXTI10_IRQHandler</a>        ; 0x70081854
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI11_IRQHandler">EXTI11_IRQHandler:</span>
+<span id="A70081856">  0x70081856:  </span>E7FE         B          <a href="#EXTI11_IRQHandler">EXTI11_IRQHandler</a>        ; 0x70081856
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI12_IRQHandler">EXTI12_IRQHandler:</span>
+<span id="A70081858">  0x70081858:  </span>E7FE         B          <a href="#EXTI12_IRQHandler">EXTI12_IRQHandler</a>        ; 0x70081858
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI13_IRQHandler">EXTI13_IRQHandler:</span>
+<span id="A7008185A">  0x7008185A:  </span>E7FE         B          <a href="#EXTI13_IRQHandler">EXTI13_IRQHandler</a>        ; 0x7008185A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI14_IRQHandler">EXTI14_IRQHandler:</span>
+<span id="A7008185C">  0x7008185C:  </span>E7FE         B          <a href="#EXTI14_IRQHandler">EXTI14_IRQHandler</a>        ; 0x7008185C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="EXTI15_IRQHandler">EXTI15_IRQHandler:</span>
+<span id="A7008185E">  0x7008185E:  </span>E7FE         B          <a href="#EXTI15_IRQHandler">EXTI15_IRQHandler</a>        ; 0x7008185E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SAES_IRQHandler">SAES_IRQHandler:</span>
+<span id="A70081860">  0x70081860:  </span>E7FE         B          <a href="#SAES_IRQHandler">SAES_IRQHandler</a>          ; 0x70081860
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CRYP_IRQHandler">CRYP_IRQHandler:</span>
+<span id="A70081862">  0x70081862:  </span>E7FE         B          <a href="#CRYP_IRQHandler">CRYP_IRQHandler</a>          ; 0x70081862
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="PKA_IRQHandler">PKA_IRQHandler:</span>
+<span id="A70081864">  0x70081864:  </span>E7FE         B          <a href="#PKA_IRQHandler">PKA_IRQHandler</a>           ; 0x70081864
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HASH_IRQHandler">HASH_IRQHandler:</span>
+<span id="A70081866">  0x70081866:  </span>E7FE         B          <a href="#HASH_IRQHandler">HASH_IRQHandler</a>          ; 0x70081866
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="RNG_IRQHandler">RNG_IRQHandler:</span>
+<span id="A70081868">  0x70081868:  </span>E7FE         B          <a href="#RNG_IRQHandler">RNG_IRQHandler</a>           ; 0x70081868
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MCE1_IRQHandler">MCE1_IRQHandler:</span>
+<span id="A7008186A">  0x7008186A:  </span>E7FE         B          <a href="#MCE1_IRQHandler">MCE1_IRQHandler</a>          ; 0x7008186A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MCE2_IRQHandler">MCE2_IRQHandler:</span>
+<span id="A7008186C">  0x7008186C:  </span>E7FE         B          <a href="#MCE2_IRQHandler">MCE2_IRQHandler</a>          ; 0x7008186C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MCE3_IRQHandler">MCE3_IRQHandler:</span>
+<span id="A7008186E">  0x7008186E:  </span>E7FE         B          <a href="#MCE3_IRQHandler">MCE3_IRQHandler</a>          ; 0x7008186E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MCE4_IRQHandler">MCE4_IRQHandler:</span>
+<span id="A70081870">  0x70081870:  </span>E7FE         B          <a href="#MCE4_IRQHandler">MCE4_IRQHandler</a>          ; 0x70081870
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="ADC1_2_IRQHandler">ADC1_2_IRQHandler:</span>
+<span id="A70081872">  0x70081872:  </span>E7FE         B          <a href="#ADC1_2_IRQHandler">ADC1_2_IRQHandler</a>        ; 0x70081872
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CSI_IRQHandler">CSI_IRQHandler:</span>
+<span id="A70081874">  0x70081874:  </span>E7FE         B          <a href="#CSI_IRQHandler">CSI_IRQHandler</a>           ; 0x70081874
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="DCMIPP_IRQHandler">DCMIPP_IRQHandler:</span>
+<span id="A70081876">  0x70081876:  </span>E7FE         B          <a href="#DCMIPP_IRQHandler">DCMIPP_IRQHandler</a>        ; 0x70081876
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler:</span>
+<span id="A70081878">  0x70081878:  </span>E7FE         B          <a href="#PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler</a>      ; 0x70081878
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="NPU0_IRQHandler">NPU0_IRQHandler:</span>
+<span id="A7008187A">  0x7008187A:  </span>E7FE         B          <a href="#NPU0_IRQHandler">NPU0_IRQHandler</a>          ; 0x7008187A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="NPU1_IRQHandler">NPU1_IRQHandler:</span>
+<span id="A7008187C">  0x7008187C:  </span>E7FE         B          <a href="#NPU1_IRQHandler">NPU1_IRQHandler</a>          ; 0x7008187C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="NPU2_IRQHandler">NPU2_IRQHandler:</span>
+<span id="A7008187E">  0x7008187E:  </span>E7FE         B          <a href="#NPU2_IRQHandler">NPU2_IRQHandler</a>          ; 0x7008187E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="NPU3_IRQHandler">NPU3_IRQHandler:</span>
+<span id="A70081880">  0x70081880:  </span>E7FE         B          <a href="#NPU3_IRQHandler">NPU3_IRQHandler</a>          ; 0x70081880
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CACHEAXI_IRQHandler">CACHEAXI_IRQHandler:</span>
+<span id="A70081882">  0x70081882:  </span>E7FE         B          <a href="#CACHEAXI_IRQHandler">CACHEAXI_IRQHandler</a>      ; 0x70081882
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LTDC_LO_IRQHandler">LTDC_LO_IRQHandler:</span>
+<span id="A70081884">  0x70081884:  </span>E7FE         B          <a href="#LTDC_LO_IRQHandler">LTDC_LO_IRQHandler</a>       ; 0x70081884
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler:</span>
+<span id="A70081886">  0x70081886:  </span>E7FE         B          <a href="#LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler</a>   ; 0x70081886
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="DMA2D_IRQHandler">DMA2D_IRQHandler:</span>
+<span id="A70081888">  0x70081888:  </span>E7FE         B          <a href="#DMA2D_IRQHandler">DMA2D_IRQHandler</a>         ; 0x70081888
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="JPEG_IRQHandler">JPEG_IRQHandler:</span>
+<span id="A7008188A">  0x7008188A:  </span>E7FE         B          <a href="#JPEG_IRQHandler">JPEG_IRQHandler</a>          ; 0x7008188A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="VENC_IRQHandler">VENC_IRQHandler:</span>
+<span id="A7008188C">  0x7008188C:  </span>E7FE         B          <a href="#VENC_IRQHandler">VENC_IRQHandler</a>          ; 0x7008188C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GFXMMU_IRQHandler">GFXMMU_IRQHandler:</span>
+<span id="A7008188E">  0x7008188E:  </span>E7FE         B          <a href="#GFXMMU_IRQHandler">GFXMMU_IRQHandler</a>        ; 0x7008188E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GFXTIM_IRQHandler">GFXTIM_IRQHandler:</span>
+<span id="A70081890">  0x70081890:  </span>E7FE         B          <a href="#GFXTIM_IRQHandler">GFXTIM_IRQHandler</a>        ; 0x70081890
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPU2D_IRQHandler">GPU2D_IRQHandler:</span>
+<span id="A70081892">  0x70081892:  </span>E7FE         B          <a href="#GPU2D_IRQHandler">GPU2D_IRQHandler</a>         ; 0x70081892
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler:</span>
+<span id="A70081894">  0x70081894:  </span>E7FE         B          <a href="#GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler</a>      ; 0x70081894
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="ICACHE_IRQHandler">ICACHE_IRQHandler:</span>
+<span id="A70081896">  0x70081896:  </span>E7FE         B          <a href="#ICACHE_IRQHandler">ICACHE_IRQHandler</a>        ; 0x70081896
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler:</span>
+<span id="A70081898">  0x70081898:  </span>E7FE         B          <a href="#HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler</a> ; 0x70081898
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler:</span>
+<span id="A7008189A">  0x7008189A:  </span>E7FE         B          <a href="#HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler</a> ; 0x7008189A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler:</span>
+<span id="A7008189C">  0x7008189C:  </span>E7FE         B          <a href="#HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler</a> ; 0x7008189C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler:</span>
+<span id="A7008189E">  0x7008189E:  </span>E7FE         B          <a href="#HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler</a> ; 0x7008189E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler:</span>
+<span id="A700818A0">  0x700818A0:  </span>E7FE         B          <a href="#HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler</a> ; 0x700818A0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler:</span>
+<span id="A700818A2">  0x700818A2:  </span>E7FE         B          <a href="#HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler</a> ; 0x700818A2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler:</span>
+<span id="A700818A4">  0x700818A4:  </span>E7FE         B          <a href="#HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler</a> ; 0x700818A4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler:</span>
+<span id="A700818A6">  0x700818A6:  </span>E7FE         B          <a href="#HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler</a> ; 0x700818A6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler:</span>
+<span id="A700818A8">  0x700818A8:  </span>E7FE         B          <a href="#HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler</a> ; 0x700818A8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler:</span>
+<span id="A700818AA">  0x700818AA:  </span>E7FE         B          <a href="#HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler</a> ; 0x700818AA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler:</span>
+<span id="A700818AC">  0x700818AC:  </span>E7FE         B          <a href="#HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler</a> ; 0x700818AC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler:</span>
+<span id="A700818AE">  0x700818AE:  </span>E7FE         B          <a href="#HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler</a> ; 0x700818AE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler:</span>
+<span id="A700818B0">  0x700818B0:  </span>E7FE         B          <a href="#HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler</a> ; 0x700818B0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler:</span>
+<span id="A700818B2">  0x700818B2:  </span>E7FE         B          <a href="#HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler</a> ; 0x700818B2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler:</span>
+<span id="A700818B4">  0x700818B4:  </span>E7FE         B          <a href="#HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler</a> ; 0x700818B4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler:</span>
+<span id="A700818B6">  0x700818B6:  </span>E7FE         B          <a href="#HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler</a> ; 0x700818B6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler:</span>
+<span id="A700818B8">  0x700818B8:  </span>E7FE         B          <a href="#GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler</a> ; 0x700818B8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler:</span>
+<span id="A700818BA">  0x700818BA:  </span>E7FE         B          <a href="#GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler</a> ; 0x700818BA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler:</span>
+<span id="A700818BC">  0x700818BC:  </span>E7FE         B          <a href="#GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler</a> ; 0x700818BC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler:</span>
+<span id="A700818BE">  0x700818BE:  </span>E7FE         B          <a href="#GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler</a> ; 0x700818BE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler:</span>
+<span id="A700818C0">  0x700818C0:  </span>E7FE         B          <a href="#GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler</a> ; 0x700818C0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler:</span>
+<span id="A700818C2">  0x700818C2:  </span>E7FE         B          <a href="#GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler</a> ; 0x700818C2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler:</span>
+<span id="A700818C4">  0x700818C4:  </span>E7FE         B          <a href="#GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler</a> ; 0x700818C4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler:</span>
+<span id="A700818C6">  0x700818C6:  </span>E7FE         B          <a href="#GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler</a> ; 0x700818C6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler:</span>
+<span id="A700818C8">  0x700818C8:  </span>E7FE         B          <a href="#GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler</a> ; 0x700818C8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler:</span>
+<span id="A700818CA">  0x700818CA:  </span>E7FE         B          <a href="#GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler</a> ; 0x700818CA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler:</span>
+<span id="A700818CC">  0x700818CC:  </span>E7FE         B          <a href="#GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler</a> ; 0x700818CC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler:</span>
+<span id="A700818CE">  0x700818CE:  </span>E7FE         B          <a href="#GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler</a> ; 0x700818CE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler:</span>
+<span id="A700818D0">  0x700818D0:  </span>E7FE         B          <a href="#GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler</a> ; 0x700818D0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler:</span>
+<span id="A700818D2">  0x700818D2:  </span>E7FE         B          <a href="#GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler</a> ; 0x700818D2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler:</span>
+<span id="A700818D4">  0x700818D4:  </span>E7FE         B          <a href="#GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler</a> ; 0x700818D4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler:</span>
+<span id="A700818D6">  0x700818D6:  </span>E7FE         B          <a href="#GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler</a> ; 0x700818D6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C1_EV_IRQHandler">I2C1_EV_IRQHandler:</span>
+<span id="A700818D8">  0x700818D8:  </span>E7FE         B          <a href="#I2C1_EV_IRQHandler">I2C1_EV_IRQHandler</a>       ; 0x700818D8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C1_ER_IRQHandler">I2C1_ER_IRQHandler:</span>
+<span id="A700818DA">  0x700818DA:  </span>E7FE         B          <a href="#I2C1_ER_IRQHandler">I2C1_ER_IRQHandler</a>       ; 0x700818DA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C2_EV_IRQHandler">I2C2_EV_IRQHandler:</span>
+<span id="A700818DC">  0x700818DC:  </span>E7FE         B          <a href="#I2C2_EV_IRQHandler">I2C2_EV_IRQHandler</a>       ; 0x700818DC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C2_ER_IRQHandler">I2C2_ER_IRQHandler:</span>
+<span id="A700818DE">  0x700818DE:  </span>E7FE         B          <a href="#I2C2_ER_IRQHandler">I2C2_ER_IRQHandler</a>       ; 0x700818DE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C3_EV_IRQHandler">I2C3_EV_IRQHandler:</span>
+<span id="A700818E0">  0x700818E0:  </span>E7FE         B          <a href="#I2C3_EV_IRQHandler">I2C3_EV_IRQHandler</a>       ; 0x700818E0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C3_ER_IRQHandler">I2C3_ER_IRQHandler:</span>
+<span id="A700818E2">  0x700818E2:  </span>E7FE         B          <a href="#I2C3_ER_IRQHandler">I2C3_ER_IRQHandler</a>       ; 0x700818E2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C4_EV_IRQHandler">I2C4_EV_IRQHandler:</span>
+<span id="A700818E4">  0x700818E4:  </span>E7FE         B          <a href="#I2C4_EV_IRQHandler">I2C4_EV_IRQHandler</a>       ; 0x700818E4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I2C4_ER_IRQHandler">I2C4_ER_IRQHandler:</span>
+<span id="A700818E6">  0x700818E6:  </span>E7FE         B          <a href="#I2C4_ER_IRQHandler">I2C4_ER_IRQHandler</a>       ; 0x700818E6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I3C1_EV_IRQHandler">I3C1_EV_IRQHandler:</span>
+<span id="A700818E8">  0x700818E8:  </span>E7FE         B          <a href="#I3C1_EV_IRQHandler">I3C1_EV_IRQHandler</a>       ; 0x700818E8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I3C1_ER_IRQHandler">I3C1_ER_IRQHandler:</span>
+<span id="A700818EA">  0x700818EA:  </span>E7FE         B          <a href="#I3C1_ER_IRQHandler">I3C1_ER_IRQHandler</a>       ; 0x700818EA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I3C2_EV_IRQHandler">I3C2_EV_IRQHandler:</span>
+<span id="A700818EC">  0x700818EC:  </span>E7FE         B          <a href="#I3C2_EV_IRQHandler">I3C2_EV_IRQHandler</a>       ; 0x700818EC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="I3C2_ER_IRQHandler">I3C2_ER_IRQHandler:</span>
+<span id="A700818EE">  0x700818EE:  </span>E7FE         B          <a href="#I3C2_ER_IRQHandler">I3C2_ER_IRQHandler</a>       ; 0x700818EE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler:</span>
+<span id="A700818F0">  0x700818F0:  </span>E7FE         B          <a href="#TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler</a>      ; 0x700818F0
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM1_UP_IRQHandler">TIM1_UP_IRQHandler:</span>
+<span id="A700818F2">  0x700818F2:  </span>E7FE         B          <a href="#TIM1_UP_IRQHandler">TIM1_UP_IRQHandler</a>       ; 0x700818F2
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler:</span>
+<span id="A700818F4">  0x700818F4:  </span>E7FE         B          <a href="#TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler</a>  ; 0x700818F4
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM1_CC_IRQHandler">TIM1_CC_IRQHandler:</span>
+<span id="A700818F6">  0x700818F6:  </span>E7FE         B          <a href="#TIM1_CC_IRQHandler">TIM1_CC_IRQHandler</a>       ; 0x700818F6
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM2_IRQHandler">TIM2_IRQHandler:</span>
+<span id="A700818F8">  0x700818F8:  </span>E7FE         B          <a href="#TIM2_IRQHandler">TIM2_IRQHandler</a>          ; 0x700818F8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM3_IRQHandler">TIM3_IRQHandler:</span>
+<span id="A700818FA">  0x700818FA:  </span>E7FE         B          <a href="#TIM3_IRQHandler">TIM3_IRQHandler</a>          ; 0x700818FA
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM4_IRQHandler">TIM4_IRQHandler:</span>
+<span id="A700818FC">  0x700818FC:  </span>E7FE         B          <a href="#TIM4_IRQHandler">TIM4_IRQHandler</a>          ; 0x700818FC
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM5_IRQHandler">TIM5_IRQHandler:</span>
+<span id="A700818FE">  0x700818FE:  </span>E7FE         B          <a href="#TIM5_IRQHandler">TIM5_IRQHandler</a>          ; 0x700818FE
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM6_IRQHandler">TIM6_IRQHandler:</span>
+<span id="A70081900">  0x70081900:  </span>E7FE         B          <a href="#TIM6_IRQHandler">TIM6_IRQHandler</a>          ; 0x70081900
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM7_IRQHandler">TIM7_IRQHandler:</span>
+<span id="A70081902">  0x70081902:  </span>E7FE         B          <a href="#TIM7_IRQHandler">TIM7_IRQHandler</a>          ; 0x70081902
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler:</span>
+<span id="A70081904">  0x70081904:  </span>E7FE         B          <a href="#TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler</a>      ; 0x70081904
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM8_UP_IRQHandler">TIM8_UP_IRQHandler:</span>
+<span id="A70081906">  0x70081906:  </span>E7FE         B          <a href="#TIM8_UP_IRQHandler">TIM8_UP_IRQHandler</a>       ; 0x70081906
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler:</span>
+<span id="A70081908">  0x70081908:  </span>E7FE         B          <a href="#TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler</a>  ; 0x70081908
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM8_CC_IRQHandler">TIM8_CC_IRQHandler:</span>
+<span id="A7008190A">  0x7008190A:  </span>E7FE         B          <a href="#TIM8_CC_IRQHandler">TIM8_CC_IRQHandler</a>       ; 0x7008190A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM9_IRQHandler">TIM9_IRQHandler:</span>
+<span id="A7008190C">  0x7008190C:  </span>E7FE         B          <a href="#TIM9_IRQHandler">TIM9_IRQHandler</a>          ; 0x7008190C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM10_IRQHandler">TIM10_IRQHandler:</span>
+<span id="A7008190E">  0x7008190E:  </span>E7FE         B          <a href="#TIM10_IRQHandler">TIM10_IRQHandler</a>         ; 0x7008190E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM11_IRQHandler">TIM11_IRQHandler:</span>
+<span id="A70081910">  0x70081910:  </span>E7FE         B          <a href="#TIM11_IRQHandler">TIM11_IRQHandler</a>         ; 0x70081910
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM12_IRQHandler">TIM12_IRQHandler:</span>
+<span id="A70081912">  0x70081912:  </span>E7FE         B          <a href="#TIM12_IRQHandler">TIM12_IRQHandler</a>         ; 0x70081912
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM13_IRQHandler">TIM13_IRQHandler:</span>
+<span id="A70081914">  0x70081914:  </span>E7FE         B          <a href="#TIM13_IRQHandler">TIM13_IRQHandler</a>         ; 0x70081914
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM14_IRQHandler">TIM14_IRQHandler:</span>
+<span id="A70081916">  0x70081916:  </span>E7FE         B          <a href="#TIM14_IRQHandler">TIM14_IRQHandler</a>         ; 0x70081916
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM15_IRQHandler">TIM15_IRQHandler:</span>
+<span id="A70081918">  0x70081918:  </span>E7FE         B          <a href="#TIM15_IRQHandler">TIM15_IRQHandler</a>         ; 0x70081918
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM16_IRQHandler">TIM16_IRQHandler:</span>
+<span id="A7008191A">  0x7008191A:  </span>E7FE         B          <a href="#TIM16_IRQHandler">TIM16_IRQHandler</a>         ; 0x7008191A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM17_IRQHandler">TIM17_IRQHandler:</span>
+<span id="A7008191C">  0x7008191C:  </span>E7FE         B          <a href="#TIM17_IRQHandler">TIM17_IRQHandler</a>         ; 0x7008191C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="TIM18_IRQHandler">TIM18_IRQHandler:</span>
+<span id="A7008191E">  0x7008191E:  </span>E7FE         B          <a href="#TIM18_IRQHandler">TIM18_IRQHandler</a>         ; 0x7008191E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPTIM1_IRQHandler">LPTIM1_IRQHandler:</span>
+<span id="A70081920">  0x70081920:  </span>E7FE         B          <a href="#LPTIM1_IRQHandler">LPTIM1_IRQHandler</a>        ; 0x70081920
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPTIM2_IRQHandler">LPTIM2_IRQHandler:</span>
+<span id="A70081922">  0x70081922:  </span>E7FE         B          <a href="#LPTIM2_IRQHandler">LPTIM2_IRQHandler</a>        ; 0x70081922
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPTIM3_IRQHandler">LPTIM3_IRQHandler:</span>
+<span id="A70081924">  0x70081924:  </span>E7FE         B          <a href="#LPTIM3_IRQHandler">LPTIM3_IRQHandler</a>        ; 0x70081924
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPTIM4_IRQHandler">LPTIM4_IRQHandler:</span>
+<span id="A70081926">  0x70081926:  </span>E7FE         B          <a href="#LPTIM4_IRQHandler">LPTIM4_IRQHandler</a>        ; 0x70081926
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPTIM5_IRQHandler">LPTIM5_IRQHandler:</span>
+<span id="A70081928">  0x70081928:  </span>E7FE         B          <a href="#LPTIM5_IRQHandler">LPTIM5_IRQHandler</a>        ; 0x70081928
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler:</span>
+<span id="A7008192A">  0x7008192A:  </span>E7FE         B          <a href="#ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler</a>     ; 0x7008192A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler:</span>
+<span id="A7008192C">  0x7008192C:  </span>E7FE         B          <a href="#MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler</a>     ; 0x7008192C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler:</span>
+<span id="A7008192E">  0x7008192E:  </span>E7FE         B          <a href="#MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler</a>     ; 0x7008192E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler:</span>
+<span id="A70081930">  0x70081930:  </span>E7FE         B          <a href="#MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler</a>     ; 0x70081930
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler:</span>
+<span id="A70081932">  0x70081932:  </span>E7FE         B          <a href="#MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler</a>     ; 0x70081932
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler:</span>
+<span id="A70081934">  0x70081934:  </span>E7FE         B          <a href="#MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler</a>     ; 0x70081934
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler:</span>
+<span id="A70081936">  0x70081936:  </span>E7FE         B          <a href="#MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler</a>     ; 0x70081936
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SAI1_A_IRQHandler">SAI1_A_IRQHandler:</span>
+<span id="A70081938">  0x70081938:  </span>E7FE         B          <a href="#SAI1_A_IRQHandler">SAI1_A_IRQHandler</a>        ; 0x70081938
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SAI1_B_IRQHandler">SAI1_B_IRQHandler:</span>
+<span id="A7008193A">  0x7008193A:  </span>E7FE         B          <a href="#SAI1_B_IRQHandler">SAI1_B_IRQHandler</a>        ; 0x7008193A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SAI2_A_IRQHandler">SAI2_A_IRQHandler:</span>
+<span id="A7008193C">  0x7008193C:  </span>E7FE         B          <a href="#SAI2_A_IRQHandler">SAI2_A_IRQHandler</a>        ; 0x7008193C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SAI2_B_IRQHandler">SAI2_B_IRQHandler:</span>
+<span id="A7008193E">  0x7008193E:  </span>E7FE         B          <a href="#SAI2_B_IRQHandler">SAI2_B_IRQHandler</a>        ; 0x7008193E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPDIFRX_IRQHandler">SPDIFRX_IRQHandler:</span>
+<span id="A70081940">  0x70081940:  </span>E7FE         B          <a href="#SPDIFRX_IRQHandler">SPDIFRX_IRQHandler</a>       ; 0x70081940
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI1_IRQHandler">SPI1_IRQHandler:</span>
+<span id="A70081942">  0x70081942:  </span>E7FE         B          <a href="#SPI1_IRQHandler">SPI1_IRQHandler</a>          ; 0x70081942
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI2_IRQHandler">SPI2_IRQHandler:</span>
+<span id="A70081944">  0x70081944:  </span>E7FE         B          <a href="#SPI2_IRQHandler">SPI2_IRQHandler</a>          ; 0x70081944
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI3_IRQHandler">SPI3_IRQHandler:</span>
+<span id="A70081946">  0x70081946:  </span>E7FE         B          <a href="#SPI3_IRQHandler">SPI3_IRQHandler</a>          ; 0x70081946
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI4_IRQHandler">SPI4_IRQHandler:</span>
+<span id="A70081948">  0x70081948:  </span>E7FE         B          <a href="#SPI4_IRQHandler">SPI4_IRQHandler</a>          ; 0x70081948
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI5_IRQHandler">SPI5_IRQHandler:</span>
+<span id="A7008194A">  0x7008194A:  </span>E7FE         B          <a href="#SPI5_IRQHandler">SPI5_IRQHandler</a>          ; 0x7008194A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SPI6_IRQHandler">SPI6_IRQHandler:</span>
+<span id="A7008194C">  0x7008194C:  </span>E7FE         B          <a href="#SPI6_IRQHandler">SPI6_IRQHandler</a>          ; 0x7008194C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USART1_IRQHandler">USART1_IRQHandler:</span>
+<span id="A7008194E">  0x7008194E:  </span>E7FE         B          <a href="#USART1_IRQHandler">USART1_IRQHandler</a>        ; 0x7008194E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USART2_IRQHandler">USART2_IRQHandler:</span>
+<span id="A70081950">  0x70081950:  </span>E7FE         B          <a href="#USART2_IRQHandler">USART2_IRQHandler</a>        ; 0x70081950
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USART3_IRQHandler">USART3_IRQHandler:</span>
+<span id="A70081952">  0x70081952:  </span>E7FE         B          <a href="#USART3_IRQHandler">USART3_IRQHandler</a>        ; 0x70081952
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UART4_IRQHandler">UART4_IRQHandler:</span>
+<span id="A70081954">  0x70081954:  </span>E7FE         B          <a href="#UART4_IRQHandler">UART4_IRQHandler</a>         ; 0x70081954
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UART5_IRQHandler">UART5_IRQHandler:</span>
+<span id="A70081956">  0x70081956:  </span>E7FE         B          <a href="#UART5_IRQHandler">UART5_IRQHandler</a>         ; 0x70081956
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USART6_IRQHandler">USART6_IRQHandler:</span>
+<span id="A70081958">  0x70081958:  </span>E7FE         B          <a href="#USART6_IRQHandler">USART6_IRQHandler</a>        ; 0x70081958
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UART7_IRQHandler">UART7_IRQHandler:</span>
+<span id="A7008195A">  0x7008195A:  </span>E7FE         B          <a href="#UART7_IRQHandler">UART7_IRQHandler</a>         ; 0x7008195A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UART8_IRQHandler">UART8_IRQHandler:</span>
+<span id="A7008195C">  0x7008195C:  </span>E7FE         B          <a href="#UART8_IRQHandler">UART8_IRQHandler</a>         ; 0x7008195C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UART9_IRQHandler">UART9_IRQHandler:</span>
+<span id="A7008195E">  0x7008195E:  </span>E7FE         B          <a href="#UART9_IRQHandler">UART9_IRQHandler</a>         ; 0x7008195E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USART10_IRQHandler">USART10_IRQHandler:</span>
+<span id="A70081960">  0x70081960:  </span>E7FE         B          <a href="#USART10_IRQHandler">USART10_IRQHandler</a>       ; 0x70081960
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LPUART1_IRQHandler">LPUART1_IRQHandler:</span>
+<span id="A70081962">  0x70081962:  </span>E7FE         B          <a href="#LPUART1_IRQHandler">LPUART1_IRQHandler</a>       ; 0x70081962
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="XSPI1_IRQHandler">XSPI1_IRQHandler:</span>
+<span id="A70081964">  0x70081964:  </span>E7FE         B          <a href="#XSPI1_IRQHandler">XSPI1_IRQHandler</a>         ; 0x70081964
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="XSPI2_IRQHandler">XSPI2_IRQHandler:</span>
+<span id="A70081966">  0x70081966:  </span>E7FE         B          <a href="#XSPI2_IRQHandler">XSPI2_IRQHandler</a>         ; 0x70081966
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="XSPI3_IRQHandler">XSPI3_IRQHandler:</span>
+<span id="A70081968">  0x70081968:  </span>E7FE         B          <a href="#XSPI3_IRQHandler">XSPI3_IRQHandler</a>         ; 0x70081968
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FMC_IRQHandler">FMC_IRQHandler:</span>
+<span id="A7008196A">  0x7008196A:  </span>E7FE         B          <a href="#FMC_IRQHandler">FMC_IRQHandler</a>           ; 0x7008196A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SDMMC1_IRQHandler">SDMMC1_IRQHandler:</span>
+<span id="A7008196C">  0x7008196C:  </span>E7FE         B          <a href="#SDMMC1_IRQHandler">SDMMC1_IRQHandler</a>        ; 0x7008196C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SDMMC2_IRQHandler">SDMMC2_IRQHandler:</span>
+<span id="A7008196E">  0x7008196E:  </span>E7FE         B          <a href="#SDMMC2_IRQHandler">SDMMC2_IRQHandler</a>        ; 0x7008196E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="UCPD1_IRQHandler">UCPD1_IRQHandler:</span>
+<span id="A70081970">  0x70081970:  </span>E7FE         B          <a href="#UCPD1_IRQHandler">UCPD1_IRQHandler</a>         ; 0x70081970
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler:</span>
+<span id="A70081972">  0x70081972:  </span>E7FE         B          <a href="#USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler</a>   ; 0x70081972
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler:</span>
+<span id="A70081974">  0x70081974:  </span>E7FE         B          <a href="#USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler</a>   ; 0x70081974
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="ETH1_IRQHandler">ETH1_IRQHandler:</span>
+<span id="A70081976">  0x70081976:  </span>E7FE         B          <a href="#ETH1_IRQHandler">ETH1_IRQHandler</a>          ; 0x70081976
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler:</span>
+<span id="A70081978">  0x70081978:  </span>E7FE         B          <a href="#FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler</a>    ; 0x70081978
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler:</span>
+<span id="A7008197A">  0x7008197A:  </span>E7FE         B          <a href="#FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler</a>    ; 0x7008197A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler:</span>
+<span id="A7008197C">  0x7008197C:  </span>E7FE         B          <a href="#FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler</a>    ; 0x7008197C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler:</span>
+<span id="A7008197E">  0x7008197E:  </span>E7FE         B          <a href="#FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler</a>    ; 0x7008197E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler:</span>
+<span id="A70081980">  0x70081980:  </span>E7FE         B          <a href="#FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler</a>    ; 0x70081980
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler:</span>
+<span id="A70081982">  0x70081982:  </span>E7FE         B          <a href="#FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler</a>    ; 0x70081982
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler:</span>
+<span id="A70081984">  0x70081984:  </span>E7FE         B          <a href="#FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler</a>      ; 0x70081984
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="MDIOS_IRQHandler">MDIOS_IRQHandler:</span>
+<span id="A70081986">  0x70081986:  </span>E7FE         B          <a href="#MDIOS_IRQHandler">MDIOS_IRQHandler</a>         ; 0x70081986
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler:</span>
+<span id="A70081988">  0x70081988:  </span>E7FE         B          <a href="#DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler</a>     ; 0x70081988
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler:</span>
+<span id="A7008198A">  0x7008198A:  </span>E7FE         B          <a href="#WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler</a>    ; 0x7008198A
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CTI_INT0_IRQHandler">CTI_INT0_IRQHandler:</span>
+<span id="A7008198C">  0x7008198C:  </span>E7FE         B          <a href="#CTI_INT0_IRQHandler">CTI_INT0_IRQHandler</a>      ; 0x7008198C
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="CTI_INT1_IRQHandler">CTI_INT1_IRQHandler:</span>
+<span id="A7008198E">  0x7008198E:  </span>E7FE         B          <a href="#CTI_INT1_IRQHandler">CTI_INT1_IRQHandler</a>      ; 0x7008198E
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LTDC_UP_IRQHandler">LTDC_UP_IRQHandler:</span>
+<span id="A70081990">  0x70081990:  </span>E7FE         B          <a href="#LTDC_UP_IRQHandler">LTDC_UP_IRQHandler</a>       ; 0x70081990
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler:</span>
+<span id="A70081992">  0x70081992:  </span>E7FE         B          <a href="#LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler</a>   ; 0x70081992
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .rodata..L.str.7 from blto_App_lto.o, size=107, align=1">Section .rodata..L.str.7 from blto_App_lto.o, size=107, align=1</h2>
+
+<pre>
+<span id="A70081994">  0x70081994:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A70081995">  0x70081995:  </span>3A           DC.B       0x3A                     ; ':'
+<span id="A70081996">  0x70081996:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081997">  0x70081997:  </span>50           DC.B       0x50                     ; 'P'
+<span id="A70081998">  0x70081998:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081999">  0x70081999:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A7008199A">  0x7008199A:  </span>6A           DC.B       0x6A                     ; 'j'
+<span id="A7008199B">  0x7008199B:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A7008199C">  0x7008199C:  </span>6B           DC.B       0x6B                     ; 'k'
+<span id="A7008199D">  0x7008199D:  </span>74           DC.B       0x74                     ; 't'
+<span id="A7008199E">  0x7008199E:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A7008199F">  0x7008199F:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819A0">  0x700819A0:  </span>68           DC.B       0x68                     ; 'h'
+<span id="A700819A1">  0x700819A1:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A700819A2">  0x700819A2:  </span>64           DC.B       0x64                     ; 'd'
+<span id="A700819A3">  0x700819A3:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819A4">  0x700819A4:  </span>77           DC.B       0x77                     ; 'w'
+<span id="A700819A5">  0x700819A5:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819A6">  0x700819A6:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A700819A7">  0x700819A7:  </span>62           DC.B       0x62                     ; 'b'
+<span id="A700819A8">  0x700819A8:  </span>6C           DC.B       0x6C                     ; 'l'
+<span id="A700819A9">  0x700819A9:  </span>74           DC.B       0x74                     ; 't'
+<span id="A700819AA">  0x700819AA:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A700819AB">  0x700819AB:  </span>32           DC.B       0x32                     ; '2'
+<span id="A700819AC">  0x700819AC:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819AD">  0x700819AD:  </span>74           DC.B       0x74                     ; 't'
+<span id="A700819AE">  0x700819AE:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819AF">  0x700819AF:  </span>75           DC.B       0x75                     ; 'u'
+<span id="A700819B0">  0x700819B0:  </span>6E           DC.B       0x6E                     ; 'n'
+<span id="A700819B1">  0x700819B1:  </span>6B           DC.B       0x6B                     ; 'k'
+<span id="A700819B2">  0x700819B2:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819B3">  0x700819B3:  </span>66           DC.B       0x66                     ; 'f'
+<span id="A700819B4">  0x700819B4:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A700819B5">  0x700819B5:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819B6">  0x700819B6:  </span>6D           DC.B       0x6D                     ; 'm'
+<span id="A700819B7">  0x700819B7:  </span>77           DC.B       0x77                     ; 'w'
+<span id="A700819B8">  0x700819B8:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A700819B9">  0x700819B9:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819BA">  0x700819BA:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819BB">  0x700819BB:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819BC">  0x700819BC:  </span>41           DC.B       0x41                     ; 'A'
+<span id="A700819BD">  0x700819BD:  </span>70           DC.B       0x70                     ; 'p'
+<span id="A700819BE">  0x700819BE:  </span>70           DC.B       0x70                     ; 'p'
+<span id="A700819BF">  0x700819BF:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819C0">  0x700819C0:  </span>43           DC.B       0x43                     ; 'C'
+<span id="A700819C1">  0x700819C1:  </span>75           DC.B       0x75                     ; 'u'
+<span id="A700819C2">  0x700819C2:  </span>62           DC.B       0x62                     ; 'b'
+<span id="A700819C3">  0x700819C3:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819C4">  0x700819C4:  </span>4D           DC.B       0x4D                     ; 'M'
+<span id="A700819C5">  0x700819C5:  </span>58           DC.B       0x58                     ; 'X'
+<span id="A700819C6">  0x700819C6:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819C7">  0x700819C7:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A700819C8">  0x700819C8:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819C9">  0x700819C9:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A700819CA">  0x700819CA:  </span>76           DC.B       0x76                     ; 'v'
+<span id="A700819CB">  0x700819CB:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819CC">  0x700819CC:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819CD">  0x700819CD:  </span>73           DC.B       0x73                     ; 's'
+<span id="A700819CE">  0x700819CE:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819CF">  0x700819CF:  </span>53           DC.B       0x53                     ; 'S'
+<span id="A700819D0">  0x700819D0:  </span>54           DC.B       0x54                     ; 'T'
+<span id="A700819D1">  0x700819D1:  </span>4D           DC.B       0x4D                     ; 'M'
+<span id="A700819D2">  0x700819D2:  </span>33           DC.B       0x33                     ; '3'
+<span id="A700819D3">  0x700819D3:  </span>32           DC.B       0x32                     ; '2'
+<span id="A700819D4">  0x700819D4:  </span>4E           DC.B       0x4E                     ; 'N'
+<span id="A700819D5">  0x700819D5:  </span>36           DC.B       0x36                     ; '6'
+<span id="A700819D6">  0x700819D6:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A700819D7">  0x700819D7:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A700819D8">  0x700819D8:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A700819D9">  0x700819D9:  </span>48           DC.B       0x48                     ; 'H'
+<span id="A700819DA">  0x700819DA:  </span>41           DC.B       0x41                     ; 'A'
+<span id="A700819DB">  0x700819DB:  </span>4C           DC.B       0x4C                     ; 'L'
+<span id="A700819DC">  0x700819DC:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A700819DD">  0x700819DD:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A700819DE">  0x700819DE:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819DF">  0x700819DF:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A700819E0">  0x700819E0:  </span>76           DC.B       0x76                     ; 'v'
+<span id="A700819E1">  0x700819E1:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819E2">  0x700819E2:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819E3">  0x700819E3:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819E4">  0x700819E4:  </span>53           DC.B       0x53                     ; 'S'
+<span id="A700819E5">  0x700819E5:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819E6">  0x700819E6:  </span>63           DC.B       0x63                     ; 'c'
+<span id="A700819E7">  0x700819E7:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A700819E8">  0x700819E8:  </span>73           DC.B       0x73                     ; 's'
+<span id="A700819E9">  0x700819E9:  </span>74           DC.B       0x74                     ; 't'
+<span id="A700819EA">  0x700819EA:  </span>6D           DC.B       0x6D                     ; 'm'
+<span id="A700819EB">  0x700819EB:  </span>33           DC.B       0x33                     ; '3'
+<span id="A700819EC">  0x700819EC:  </span>32           DC.B       0x32                     ; '2'
+<span id="A700819ED">  0x700819ED:  </span>6E           DC.B       0x6E                     ; 'n'
+<span id="A700819EE">  0x700819EE:  </span>36           DC.B       0x36                     ; '6'
+<span id="A700819EF">  0x700819EF:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A700819F0">  0x700819F0:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A700819F1">  0x700819F1:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A700819F2">  0x700819F2:  </span>68           DC.B       0x68                     ; 'h'
+<span id="A700819F3">  0x700819F3:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A700819F4">  0x700819F4:  </span>6C           DC.B       0x6C                     ; 'l'
+<span id="A700819F5">  0x700819F5:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A700819F6">  0x700819F6:  </span>63           DC.B       0x63                     ; 'c'
+<span id="A700819F7">  0x700819F7:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A700819F8">  0x700819F8:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A700819F9">  0x700819F9:  </span>74           DC.B       0x74                     ; 't'
+<span id="A700819FA">  0x700819FA:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A700819FB">  0x700819FB:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A700819FC">  0x700819FC:  </span>2E           DC.B       0x2E                     ; '.'
+<span id="A700819FD">  0x700819FD:  </span>63           DC.B       0x63                     ; 'c'
+<span id="A700819FE">  0x700819FE:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .rodata..L.str.17 from blto_App_lto.o, size=105, align=1">Section .rodata..L.str.17 from blto_App_lto.o, size=105, align=1</h2>
+
+<pre>
+<span id="A700819FF">  0x700819FF:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A70081A00">  0x70081A00:  </span>3A           DC.B       0x3A                     ; ':'
+<span id="A70081A01">  0x70081A01:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A02">  0x70081A02:  </span>50           DC.B       0x50                     ; 'P'
+<span id="A70081A03">  0x70081A03:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A04">  0x70081A04:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A70081A05">  0x70081A05:  </span>6A           DC.B       0x6A                     ; 'j'
+<span id="A70081A06">  0x70081A06:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A07">  0x70081A07:  </span>6B           DC.B       0x6B                     ; 'k'
+<span id="A70081A08">  0x70081A08:  </span>74           DC.B       0x74                     ; 't'
+<span id="A70081A09">  0x70081A09:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A0A">  0x70081A0A:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A0B">  0x70081A0B:  </span>68           DC.B       0x68                     ; 'h'
+<span id="A70081A0C">  0x70081A0C:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A70081A0D">  0x70081A0D:  </span>64           DC.B       0x64                     ; 'd'
+<span id="A70081A0E">  0x70081A0E:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A0F">  0x70081A0F:  </span>77           DC.B       0x77                     ; 'w'
+<span id="A70081A10">  0x70081A10:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A11">  0x70081A11:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A70081A12">  0x70081A12:  </span>62           DC.B       0x62                     ; 'b'
+<span id="A70081A13">  0x70081A13:  </span>6C           DC.B       0x6C                     ; 'l'
+<span id="A70081A14">  0x70081A14:  </span>74           DC.B       0x74                     ; 't'
+<span id="A70081A15">  0x70081A15:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A70081A16">  0x70081A16:  </span>32           DC.B       0x32                     ; '2'
+<span id="A70081A17">  0x70081A17:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A18">  0x70081A18:  </span>74           DC.B       0x74                     ; 't'
+<span id="A70081A19">  0x70081A19:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A1A">  0x70081A1A:  </span>75           DC.B       0x75                     ; 'u'
+<span id="A70081A1B">  0x70081A1B:  </span>6E           DC.B       0x6E                     ; 'n'
+<span id="A70081A1C">  0x70081A1C:  </span>6B           DC.B       0x6B                     ; 'k'
+<span id="A70081A1D">  0x70081A1D:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A1E">  0x70081A1E:  </span>66           DC.B       0x66                     ; 'f'
+<span id="A70081A1F">  0x70081A1F:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A70081A20">  0x70081A20:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A21">  0x70081A21:  </span>6D           DC.B       0x6D                     ; 'm'
+<span id="A70081A22">  0x70081A22:  </span>77           DC.B       0x77                     ; 'w'
+<span id="A70081A23">  0x70081A23:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A70081A24">  0x70081A24:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A25">  0x70081A25:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A26">  0x70081A26:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A27">  0x70081A27:  </span>41           DC.B       0x41                     ; 'A'
+<span id="A70081A28">  0x70081A28:  </span>70           DC.B       0x70                     ; 'p'
+<span id="A70081A29">  0x70081A29:  </span>70           DC.B       0x70                     ; 'p'
+<span id="A70081A2A">  0x70081A2A:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A2B">  0x70081A2B:  </span>43           DC.B       0x43                     ; 'C'
+<span id="A70081A2C">  0x70081A2C:  </span>75           DC.B       0x75                     ; 'u'
+<span id="A70081A2D">  0x70081A2D:  </span>62           DC.B       0x62                     ; 'b'
+<span id="A70081A2E">  0x70081A2E:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A2F">  0x70081A2F:  </span>4D           DC.B       0x4D                     ; 'M'
+<span id="A70081A30">  0x70081A30:  </span>58           DC.B       0x58                     ; 'X'
+<span id="A70081A31">  0x70081A31:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A32">  0x70081A32:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A70081A33">  0x70081A33:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A34">  0x70081A34:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A70081A35">  0x70081A35:  </span>76           DC.B       0x76                     ; 'v'
+<span id="A70081A36">  0x70081A36:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A37">  0x70081A37:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A38">  0x70081A38:  </span>73           DC.B       0x73                     ; 's'
+<span id="A70081A39">  0x70081A39:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A3A">  0x70081A3A:  </span>53           DC.B       0x53                     ; 'S'
+<span id="A70081A3B">  0x70081A3B:  </span>54           DC.B       0x54                     ; 'T'
+<span id="A70081A3C">  0x70081A3C:  </span>4D           DC.B       0x4D                     ; 'M'
+<span id="A70081A3D">  0x70081A3D:  </span>33           DC.B       0x33                     ; '3'
+<span id="A70081A3E">  0x70081A3E:  </span>32           DC.B       0x32                     ; '2'
+<span id="A70081A3F">  0x70081A3F:  </span>4E           DC.B       0x4E                     ; 'N'
+<span id="A70081A40">  0x70081A40:  </span>36           DC.B       0x36                     ; '6'
+<span id="A70081A41">  0x70081A41:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A70081A42">  0x70081A42:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A70081A43">  0x70081A43:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A70081A44">  0x70081A44:  </span>48           DC.B       0x48                     ; 'H'
+<span id="A70081A45">  0x70081A45:  </span>41           DC.B       0x41                     ; 'A'
+<span id="A70081A46">  0x70081A46:  </span>4C           DC.B       0x4C                     ; 'L'
+<span id="A70081A47">  0x70081A47:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A70081A48">  0x70081A48:  </span>44           DC.B       0x44                     ; 'D'
+<span id="A70081A49">  0x70081A49:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A4A">  0x70081A4A:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A70081A4B">  0x70081A4B:  </span>76           DC.B       0x76                     ; 'v'
+<span id="A70081A4C">  0x70081A4C:  </span>65           DC.B       0x65                     ; 'e'
+<span id="A70081A4D">  0x70081A4D:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A4E">  0x70081A4E:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A4F">  0x70081A4F:  </span>53           DC.B       0x53                     ; 'S'
+<span id="A70081A50">  0x70081A50:  </span>72           DC.B       0x72                     ; 'r'
+<span id="A70081A51">  0x70081A51:  </span>63           DC.B       0x63                     ; 'c'
+<span id="A70081A52">  0x70081A52:  </span>5C           DC.B       0x5C                     ; '\\'
+<span id="A70081A53">  0x70081A53:  </span>73           DC.B       0x73                     ; 's'
+<span id="A70081A54">  0x70081A54:  </span>74           DC.B       0x74                     ; 't'
+<span id="A70081A55">  0x70081A55:  </span>6D           DC.B       0x6D                     ; 'm'
+<span id="A70081A56">  0x70081A56:  </span>33           DC.B       0x33                     ; '3'
+<span id="A70081A57">  0x70081A57:  </span>32           DC.B       0x32                     ; '2'
+<span id="A70081A58">  0x70081A58:  </span>6E           DC.B       0x6E                     ; 'n'
+<span id="A70081A59">  0x70081A59:  </span>36           DC.B       0x36                     ; '6'
+<span id="A70081A5A">  0x70081A5A:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A70081A5B">  0x70081A5B:  </span>78           DC.B       0x78                     ; 'x'
+<span id="A70081A5C">  0x70081A5C:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A70081A5D">  0x70081A5D:  </span>68           DC.B       0x68                     ; 'h'
+<span id="A70081A5E">  0x70081A5E:  </span>61           DC.B       0x61                     ; 'a'
+<span id="A70081A5F">  0x70081A5F:  </span>6C           DC.B       0x6C                     ; 'l'
+<span id="A70081A60">  0x70081A60:  </span>5F           DC.B       0x5F                     ; '_'
+<span id="A70081A61">  0x70081A61:  </span>67           DC.B       0x67                     ; 'g'
+<span id="A70081A62">  0x70081A62:  </span>70           DC.B       0x70                     ; 'p'
+<span id="A70081A63">  0x70081A63:  </span>69           DC.B       0x69                     ; 'i'
+<span id="A70081A64">  0x70081A64:  </span>6F           DC.B       0x6F                     ; 'o'
+<span id="A70081A65">  0x70081A65:  </span>2E           DC.B       0x2E                     ; '.'
+<span id="A70081A66">  0x70081A66:  </span>63           DC.B       0x63                     ; 'c'
+<span id="A70081A67">  0x70081A67:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</h2>
+
+<pre>
+<span id="A70081A68">  0x70081A68:  </span>70080829     DC.W       <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_ctors">__SEGGER_init_ctors:</span>
+<span id="A70081A6C">  0x70081A6C:  </span>B500         PUSH       123LR}
+<span id="A70081A6E">  0x70081A6E:  </span>4806         LDR        R0, =0x70081A68          ; [PC, #24] [0x70081A88] 
+<span id="A70081A70">  0x70081A70:  </span>4906         LDR        R1, =__SEGGER_init_ctors ; [PC, #24] [0x70081A8C] =0x70081A6C 
+<br/>.L1:
+<span id="A70081A72">  0x70081A72:  </span>4288         CMP        R0, R1
+<span id="A70081A74">  0x70081A74:  </span>D005         BEQ        46L2                      ; 0x70081A82
+<span id="A70081A76">  0x70081A76:  </span>6802         LDR        R2, [R0]
+<span id="A70081A78">  0x70081A78:  </span>3004         ADDS       R0, #4
+<span id="A70081A7A">  0x70081A7A:  </span>B403         PUSH       123R0-R1}
+<span id="A70081A7C">  0x70081A7C:  </span>4790         BLX        R2
+<span id="A70081A7E">  0x70081A7E:  </span>BC03         POP        123R0-R1}
+<span id="A70081A80">  0x70081A80:  </span>E7F7         B          46L1                      ; 0x70081A72
+<br/>.L2:
+<span id="A70081A82">  0x70081A82:  </span>BC08         POP        123R3}
+<span id="A70081A84">  0x70081A84:  </span>4718         BX         R3
+<span id="A70081A86">  0x70081A86:  </span>0000         NOP
+<span id="A70081A88">  0x70081A88:  </span>70081A68     DC.W       70081A68               ; R_ARM_ABS32
+<span id="A70081A8C">  0x70081A8C:  </span>70081A6C     DC.W       <a href="#__SEGGER_init_ctors">__SEGGER_init_ctors</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</h2>
+
+<pre>
+<span id="A70081A90">  0x70081A90:  </span>70081AC1     DC.W       <a href="#__SEGGER_init_zero">__SEGGER_init_zero</a>
+<span id="A70081A94">  0x70081A94:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A95">  0x70081A95:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A96">  0x70081A96:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A97">  0x70081A97:  </span>34           DC.B       0x34                     ; '4'
+<span id="A70081A98">  0x70081A98:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70081A99">  0x70081A99:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A9A">  0x70081A9A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A9B">  0x70081A9B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081A9C">  0x70081A9C:  </span>70081AD3     DC.W       <a href="#__SEGGER_init_copy">__SEGGER_init_copy</a>
+<span id="A70081AA0">  0x70081AA0:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70081AA1">  0x70081AA1:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AA2">  0x70081AA2:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AA3">  0x70081AA3:  </span>34           DC.B       0x34                     ; '4'
+<span id="A70081AA4">  0x70081AA4:  </span>70081AB4     DC.W       70081AB4               ; R_ARM_ABS32
+<span id="A70081AA8">  0x70081AA8:  </span>09           DC.B       0x09                     ; '\t'
+<span id="A70081AA9">  0x70081AA9:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AAA">  0x70081AAA:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AAB">  0x70081AAB:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AAC">  0x70081AAC:  </span>70081A6D     DC.W       <a href="#__SEGGER_init_ctors">__SEGGER_init_ctors</a>
+<span id="A70081AB0">  0x70081AB0:  </span>7008148F     DC.W       <a href="#__SEGGER_init_done">__SEGGER_init_done</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=12, align=4">Section .segger.init.data from [ Linker created ], size=12, align=4</h2>
+
+<pre>
+<span id="A70081AB4">  0x70081AB4:  </span>10           DC.B       0x10                     ; '\x10'
+<span id="A70081AB5">  0x70081AB5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AB6">  0x70081AB6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AB7">  0x70081AB7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AB8">  0x70081AB8:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081AB9">  0x70081AB9:  </span>90           DC.B       0x90                     ; '\x90'
+<span id="A70081ABA">  0x70081ABA:  </span>D0           DC.B       0xD0                     ; '\xD0'
+<span id="A70081ABB">  0x70081ABB:  </span>03           DC.B       0x03                     ; '\x03'
+<span id="A70081ABC">  0x70081ABC:  </span>01           DC.B       0x01                     ; '\x01'
+<span id="A70081ABD">  0x70081ABD:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081ABE">  0x70081ABE:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70081ABF">  0x70081ABF:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_zero">__SEGGER_init_zero:</span>
+<span id="A70081AC0">  0x70081AC0:  </span>6820         LDR        R0, [R4]
+<span id="A70081AC2">  0x70081AC2:  </span>6861         LDR        R1, [R4, #4]
+<span id="A70081AC4">  0x70081AC4:  </span>3408         ADDS       R4, #8
+<span id="A70081AC6">  0x70081AC6:  </span>2200         MOVS       R2, #0
+<span id="A70081AC8">  0x70081AC8:  </span>E000         B          46L2                      ; 0x70081ACC
+<br/>.L1:
+<span id="A70081ACA">  0x70081ACA:  </span>5442         STRB       R2, [R0, R1]
+<br/>.L2:
+<span id="A70081ACC">  0x70081ACC:  </span>1E49         SUBS       R1, R1, #1
+<span id="A70081ACE">  0x70081ACE:  </span>D5FC         BPL        46L1                      ; 0x70081ACA
+<span id="A70081AD0">  0x70081AD0:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_copy">__SEGGER_init_copy:</span>
+<span id="A70081AD2">  0x70081AD2:  </span>6820         LDR        R0, [R4]
+<span id="A70081AD4">  0x70081AD4:  </span>6861         LDR        R1, [R4, #4]
+<span id="A70081AD6">  0x70081AD6:  </span>68A2         LDR        R2, [R4, #8]
+<span id="A70081AD8">  0x70081AD8:  </span>340C         ADDS       R4, #12
+<span id="A70081ADA">  0x70081ADA:  </span>E001         B          46L2                      ; 0x70081AE0
+<br/>.L1:
+<span id="A70081ADC">  0x70081ADC:  </span>5C8B         LDRB       R3, [R1, R2]
+<span id="A70081ADE">  0x70081ADE:  </span>5483         STRB       R3, [R0, R2]
+<br/>.L2:
+<span id="A70081AE0">  0x70081AE0:  </span>1E52         SUBS       R2, R2, #1
+<span id="A70081AE2">  0x70081AE2:  </span>D5FB         BPL        46L1                      ; 0x70081ADC
+<span id="A70081AE4">  0x70081AE4:  </span>4770         BX         LR
+</pre>
+<h1 id="LINK SUMMARY">LINK SUMMARY</h1>
+<h2 id="LINK SUMMARY_Memory breakdown">Memory breakdown</h2>
+
+<pre>
+  5 598 bytes read-only  code    + 
+    260 bytes read-only  data    =   5 858 bytes read-only (total)
+  8 205 bytes read-write data
+</pre>
+<h2 id="LINK SUMMARY_Region summary">Region summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="right">Used</th>
+    <th align="right">Unused</th>
+    <th align="right">Alignment Loss</th>
+  </tr>
+  <tr>
+    <td align="left"><code>FLEX_RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+    <td align="right"><code>8 205   2.00</code></td>
+    <td align="right"><code>401 395  98.00</code></td>
+    <td align="right"><code>0   0.00</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+    <td align="right"><code>5 862   0.01</code></td>
+    <td align="right"><code>66 577 690  99.99</code></td>
+    <td align="right"><code>0   0.00</code></td>
+  </tr>
+</table>
+<h2 id="LINK SUMMARY_Diagnostic summary">Diagnostic summary</h2>
+
+<pre>
+Link complete: 0 errors.
+</pre>
+</body></html>
Index: trunk/firmware/App/SES/Output/Release/Exe/blto_App.htm
===================================================================
--- trunk/firmware/App/SES/Output/Release/Exe/blto_App.htm	(revision 22)
+++ trunk/firmware/App/SES/Output/Release/Exe/blto_App.htm	(revision 22)
@@ -0,0 +1,10697 @@
+<!DOCTYPE html>
+<html>
+<style>
+body { font-family: "Tahoma", "Open Sans", "Helvetica Neue", Helvetica, Arial, sans-serif; font-size: 0.9rem; line-height: 1.5; min-width: 400px;             padding-left: 20px; padding-left: 80px; padding-right: 5px; }
+html { margin: 0; padding: 0; }
+pre { border: 1px solid #d0d4d9; background: #f6f9fc; padding: 10px 10px; border-radius: 3px; font-size: 0.9rem; font-family: Consolas, Courier, monospace; }
+th { background-color: #f6f9fc; }
+table, th, td { border: 1px solid #d0d4d9; border-collapse: collapse; padding: 4px 4px; }
+h1 { color: #0B5B9A; margin-top: 50px; margin-left: -50pt; margin-bottom: 20px; text-align: left; font-size: 1.5em; border-bottom: 1px solid #0B5B9A; }
+h2 { color: #0B5B9A; margin-top: 30px; margin-left: -50pt;                      text-align: left; font-size: 1.2em; }
+a { color: #0B5B9A; text-decoration: none; }
+a:hover { color: #d3d800; }
+ul { margin: 0; padding: 0; }
+ul li ul { margin: 10px; }
+</style>
+<body>
+<h1>CONTENTS</h1>
+<ul>
+  <li><a href="#LINK INFORMATION">LINK INFORMATION</a>
+<ul>
+  <li><a href="#LINK INFORMATION_Linker version">Linker version</a></li>
+  <li><a href="#LINK INFORMATION_Command line">Command line</a></li>
+</ul>
+  </li>
+  <li><a href="#LINKER SCRIPT">LINKER SCRIPT</a>
+<ul>
+  <li><a href="#LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;</a></li>
+</ul>
+  </li>
+  <li><a href="#PLACEMENT SUMMARY">PLACEMENT SUMMARY</a>
+<ul>
+  <li><a href="#PLACEMENT SUMMARY_place at 0x34064000">place at 0x34064000</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing">&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</a></li>
+  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</a></li>
+</ul>
+  </li>
+  <li><a href="#MODULE SUMMARY">MODULE SUMMARY</a>
+<ul>
+  <li><a href="#MODULE SUMMARY_Memory use by input file">Memory use by input file</a></li>
+  <li><a href="#MODULE SUMMARY_Memory use by archive member">Memory use by archive member</a></li>
+  <li><a href="#MODULE SUMMARY_Memory use by linker">Memory use by linker</a></li>
+</ul>
+  </li>
+  <li><a href="#MODULE DETAIL">MODULE DETAIL</a>
+<ul>
+  <li><a href="#MODULE DETAIL_Module blto_App_lto.o">Module blto_App_lto.o</a></li>
+  <li><a href="#MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</a></li>
+  <li><a href="#MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</a></li>
+  <li><a href="#MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</a></li>
+  <li><a href="#MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</a></li>
+  <li><a href="#MODULE DETAIL_All modules">All modules</a></li>
+</ul>
+  </li>
+  <li><a href="#SECTION DETAIL">SECTION DETAIL</a>
+<ul>
+  <li><a href="#SECTION DETAIL_Sections by address">Sections by address</a></li>
+</ul>
+  </li>
+  <li><a href="#UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</a>
+<ul>
+  <li><a href="#UNUSED MEMORY SUMMARY_Detail">Detail</a></li>
+</ul>
+  </li>
+  <li><a href="#INITIALIZATION TABLE">INITIALIZATION TABLE</a>
+<ul>
+  <li><a href="#INITIALIZATION TABLE_Constructor list">Constructor list</a></li>
+  <li><a href="#INITIALIZATION TABLE_Initialize by zero">Initialize by zero</a></li>
+  <li><a href="#INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</a></li>
+  <li><a href="#INITIALIZATION TABLE_Summary">Summary</a></li>
+</ul>
+  </li>
+  <li><a href="#LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</a>
+<ul>
+  <li><a href="#LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</a></li>
+  <li><a href="#LINKER-CREATED VENEERS_Summary">Summary</a></li>
+</ul>
+  </li>
+  <li><a href="#SYMBOL LIST">SYMBOL LIST</a>
+<ul>
+  <li><a href="#SYMBOL LIST_Function symbols by name">Function symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Function symbols by address">Function symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</a></li>
+  <li><a href="#SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</a></li>
+  <li><a href="#SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</a></li>
+  <li><a href="#SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</a></li>
+</ul>
+  </li>
+  <li><a href="#REGION LIST">REGION LIST</a>
+<ul>
+  <li><a href="#REGION LIST_Regions by name">Regions by name</a></li>
+  <li><a href="#REGION LIST_Analysis">Analysis</a></li>
+</ul>
+  </li>
+  <li><a href="#BLOCK LIST">BLOCK LIST</a>
+<ul>
+  <li><a href="#BLOCK LIST_Blocks by name">Blocks by name</a></li>
+  <li><a href="#BLOCK LIST_Blocks by address">Blocks by address</a></li>
+</ul>
+  </li>
+  <li><a href="#STACK SIZES">STACK SIZES</a>
+<ul>
+  <li><a href="#STACK SIZES_Functions by stack size">Functions by stack size</a></li>
+  <li><a href="#STACK SIZES_Functions without stack size information">Functions without stack size information</a></li>
+</ul>
+  </li>
+  <li><a href="#UNUSED INPUTS">UNUSED INPUTS</a>
+<ul>
+  <li><a href="#UNUSED INPUTS_Unused object files">Unused object files</a></li>
+</ul>
+  </li>
+  <li><a href="#ABSOLUTE LISTING">ABSOLUTE LISTING</a>
+<ul>
+  <li><a href="#ABSOLUTE LISTING_Section .bss.uwTick from blto_App_lto.o, size=4, align=4">Section .bss.uwTick from blto_App_lto.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=392, align=4">Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=392, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto_App_lto.o, size=416, align=4">Section .text.HAL_GPIO_Init from blto_App_lto.o, size=416, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto_App_lto.o, size=64, align=4">Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto_App_lto.o, size=64, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.main from blto_App_lto.o, size=502, align=4">Section .text.main from blto_App_lto.o, size=502, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SVC_Handler from blto_App_lto.o, size=2, align=2">Section .text.SVC_Handler from blto_App_lto.o, size=2, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4">Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SystemInit from blto_App_lto.o, size=134, align=2">Section .text.SystemInit from blto_App_lto.o, size=134, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .text.SysTick_Handler from blto_App_lto.o, size=16, align=2">Section .text.SysTick_Handler from blto_App_lto.o, size=16, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=4, align=4">Section .segger.init.data from [ Linker created ], size=4, align=4</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2</a></li>
+  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2</a></li>
+</ul>
+  </li>
+  <li><a href="#OPTIMIZATION REPORT">OPTIMIZATION REPORT</a>
+<ul>
+  <li><a href="#OPTIMIZATION REPORT_Transformations performed">Transformations performed</a></li>
+</ul>
+  </li>
+  <li><a href="#LINK SUMMARY">LINK SUMMARY</a>
+<ul>
+  <li><a href="#LINK SUMMARY_Memory breakdown">Memory breakdown</a></li>
+  <li><a href="#LINK SUMMARY_Region summary">Region summary</a></li>
+  <li><a href="#LINK SUMMARY_Diagnostic summary">Diagnostic summary</a></li>
+</ul>
+  </li>
+</ul>
+<h1 id="LINK INFORMATION">LINK INFORMATION</h1>
+<h2 id="LINK INFORMATION_Linker version">Linker version</h2>
+
+<pre>
+SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
+Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
+</pre>
+<h2 id="LINK INFORMATION_Command line">Command line</h2>
+
+<pre>
+--add-region:ITCM_RAM=0x00010000@0x10000000
+--add-region:DTCM_RAM=0x00020000@0x30000000
+--add-region:FLEX_RAM=0x00064000@0x34000000
+--add-region:AXI_RAM1=0x0009c000@0x34064000
+--add-region:AXI_RAM2=0x00070000@0x34100000
+--add-region:AXI_RAM3=0x00070000@0x34200000
+--add-region:AXI_RAM4=0x00070000@0x34270000
+--add-region:AXI_RAM5=0x00070000@0x342e0000
+--add-region:AXI_RAM6=0x00070000@0x34350000
+--add-region:AXI_RAM7=0x00040000@0x343c0000
+--add-region:AXI_RAM8=0x00020000@0x34400000
+--add-region:AHB_RAM1=0x00004000@0x38000000
+--add-region:AHB_RAM2=0x00004000@0x38004000
+--add-region:BKP_RAM=0x00002000@0x3c000000
+--add-region:FLASH_RAM=0x03f7fc00@0x70080400
+--full-section-headers
+--dedupe-code
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Release/Exe/blto_App.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=8.1-M.main
+--silent
+-TD:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf
+--defsym=__STACKSIZE__=8192
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=64
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/Output/Release/Exe/blto_App.elf
+D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/Output/Release/Obj/blto_App_lto.o
+Output/Release/Obj/SEGGER_THUMB_Startup.o
+Output/Release/Obj/stm32n657xx_Vectors.o
+Output/Release/Obj/STM32N6xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_basic_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi.a
+</pre>
+<h1 id="LINKER SCRIPT">LINKER SCRIPT</h1>
+<h2 id="LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/App/SES/STM32N6xx_RAM.icf&apos;</h2>
+
+<pre>
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = FLEX_RAM;
+define region FLASH = FLASH_RAM;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH_RAM                          { section .FLASH_RAM, section .FLASH_RAM.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { section vectors };                                    // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in AXI_RAM5                           { section .AXI_RAM5, section .AXI_RAM5.* };  // This region may be deactivated and not accessible
+place in AXI_RAM6                           { section .AXI_RAM6, section .AXI_RAM6.* };  // This region may be deactivated and not accessible
+place in AXI_RAM7                           { section .AXI_RAM7, section .AXI_RAM7.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.* };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+</pre>
+<h1 id="PLACEMENT SUMMARY">PLACEMENT SUMMARY</h1>
+<h2 id="PLACEMENT SUMMARY_place at 0x34064000">place at 0x34064000</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing">&quot;&lt;#5&gt; at line 111, col 45&quot;: place in [0x70080400 to 0x73FFFFFF] with maximum packing</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x700808D4</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70080A74</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080AB4</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080AC8</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080AF4</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080CEA</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080CEC</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080CEE</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080D74</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.init_array]</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="right"><code>0x70080D84</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata.block.tdata.copy]</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70080D84</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080D88</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70080DAC</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="right"><code>0x70080DD0</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080DD4</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="right"><code>0x70080DE6</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#20&gt; at line 140, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.heap]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34000008</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="PLACEMENT SUMMARY_&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order">&quot;&lt;#21&gt; at line 144, col 45&quot;: place in [0x34000000 to 0x34063FFF] with auto order</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="left">Type</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>[.bss.block.heap]</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="right"><code>0x34000008</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h1 id="MODULE SUMMARY">MODULE SUMMARY</h1>
+<h2 id="MODULE SUMMARY_Memory use by input file">Memory use by input file</h2>
+
+<table>
+  <tr>
+    <th align="left">Object File</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>blto_App_lto.o</code></td>
+    <td align="right"><code>1 464</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (4 objects)</code></td>
+    <td align="right"><code>2 372</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (1archives)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>40</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>2 446</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h2 id="MODULE SUMMARY_Memory use by archive member">Memory use by archive member</h2>
+
+<table>
+  <tr>
+    <th align="left">Archive member</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (1 members from 1 archives)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Objects (4 files)</code></td>
+    <td align="right"><code>2 372</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>40</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>2 446</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h2 id="MODULE SUMMARY_Memory use by linker">Memory use by linker</h2>
+
+<table>
+  <tr>
+    <th align="left">Description</th>
+    <th align="right">RX Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>Initialization table</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>40</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Memory for block &apos;stack&apos;</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Subtotal (linker created):</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>40</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Objects (4 files)</code></td>
+    <td align="right"><code>2 372</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Archives (1 files)</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>2 446</code></td>
+    <td align="right"><code>104</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>8 196</code></td>
+  </tr>
+</table>
+<h1 id="MODULE DETAIL">MODULE DETAIL</h1>
+<h2 id="MODULE DETAIL_Module blto_App_lto.o">Module blto_App_lto.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>1 464</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol or [section] name</th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>74</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+  </tr>
+</table>
+<h2 id="MODULE DETAIL_All modules">All modules</h2>
+
+<table>
+  <tr>
+    <th align="left"></th>
+    <th align="right">Code</th>
+    <th align="right">RO Data</th>
+    <th align="right">RW Data</th>
+    <th align="right">ZI Data</th>
+  </tr>
+  <tr>
+    <td align="left"><code>Grand total:</code></td>
+    <td align="right"><code>2 446</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+  </tr>
+</table>
+<h1 id="SECTION DETAIL">SECTION DETAIL</h1>
+<h2 id="SECTION DETAIL_Sections by address">Sections by address</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="left">Symbol or [section] Name</th>
+    <th align="right">Size</th>
+    <th align="right">Al</th>
+    <th align="left">Init</th>
+    <th align="left">Ac</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>ZI</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-34000007</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>RW</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000008-34061FFF</code></td>
+    <td align="left" style="color: red;"><code>( UNUSED .=.+401400 )</code></td>
+    <td align="right"><code>401 400</code></td>
+    <td align="right"><code>-</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>-</code></td>
+    <td align="left"><code>-</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="left"><code>[.bss.block.stack]</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="right"><code>8</code></td>
+    <td align="left"><code>None</code></td>
+    <td align="left"><code>ZI</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080400-7008074B</code></td>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>844</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>7008074C-700808D3</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>700808D4-70080A73</code></td>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080A74-70080AB3</code></td>
+    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
+    <td align="right"><code>64</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080AB4-70080AC7</code></td>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080AC8-70080AF3</code></td>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>44</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080AF4-70080CE9</code></td>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080CEA-70080CEB</code></td>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080CEC-70080CED</code></td>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080CEE-70080D73</code></td>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080D74-70080D83</code></td>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080D84-70080D87</code></td>
+    <td align="left"><code>[.init_array]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>--</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080D88-70080DAB</code></td>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080DAC-70080DCF</code></td>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>36</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080DD0-70080DD3</code></td>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>RO</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080DD4-70080DE5</code></td>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080DE6-70080DF9</code></td>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>RX</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h1 id="UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</h1>
+<h2 id="UNUSED MEMORY SUMMARY_Detail">Detail</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Reason</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000008-34061FFF</code></td>
+    <td align="right"><code>401 400</code></td>
+    <td align="left"><code>Unused memory between sections &apos;.data.SystemCoreClock&apos; and &apos;.bss.block.stack&apos;</code></td>
+  </tr>
+</table>
+<h1 id="INITIALIZATION TABLE">INITIALIZATION TABLE</h1>
+<h2 id="INITIALIZATION TABLE_Constructor list">Constructor list</h2>
+
+<table>
+  <tr>
+    <th align="left">Table<br/>Address</th>
+    <th align="left">Called<br/>Address</th>
+    <th align="left">Called<br/>Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>0x70080D84</code></td>
+    <td align="left"><code>0x7008074D</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+  </tr>
+</table>
+<h2 id="INITIALIZATION TABLE_Initialize by zero">Initialize by zero</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>uwTick</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000000-34000003</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Total (1 sections)</code></td>
+  </tr>
+<h2 id="INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Symbol or [section] name</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-34000007</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>34000004-34000007</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Total (1 sections)</code></td>
+  </tr>
+</pre>
+<h2 id="INITIALIZATION TABLE_Summary">Summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Description</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left">Initialization table</td>
+    <td align="right"><code>36 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Source image</td>
+    <td align="right"><code>4 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Destination image</td>
+    <td align="right"><code>8 bytes</code></td>
+  </tr>
+  <tr>
+    <td align="left">Saving</td>
+    <td align="right"><code>-32 bytes</code></td>
+  </tr>
+</table>
+<h1 id="LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</h1>
+<h2 id="LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</h2>
+
+<table>
+  <tr>
+    <th align="right">Veneer Size</th>
+    <th align="left">Target</th>
+    <th align="left">Source</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0</code></td>
+    <td align="left"><code>Total</code></td>
+    <td align="left"><code></code></td>
+  </tr>
+</table>
+<h2 id="LINKER-CREATED VENEERS_Summary">Summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Veneer Type</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left">Thumb-Arm mode switch</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Arm-Thumb mode switch</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Thumb-Thumb range extension</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Arm-Arm range extension</td>
+    <td align="right">0</td>
+  </tr>
+  <tr>
+    <td align="left">Total:</td>
+    <td align="right">0</td>
+  </tr>
+</table>
+<h1 id="SYMBOL LIST">SYMBOL LIST</h1>
+<h2 id="SYMBOL LIST_Function symbols by name">Function symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>0x700808D5</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code>0x70080AC9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>0x70080D75</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>0x7008074D</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>0x70080CEF</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>0x70080DE7</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>0x70080D89</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code>0x70080ABF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>0x70080DD5</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code>0x70080ABF</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>0x70080AB5</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>0x70080AC3</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>0x70080AF5</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code>0x70080AC9</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Function symbols by address">Function symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008074D</code></td>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x700808D5</code></td>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080AB5</code></td>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080ABF</code></td>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080ABF</code></td>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080AC3</code></td>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080AC9</code></td>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080AC9</code></td>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080AF5</code></td>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CEB</code></td>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CED</code></td>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080CEF</code></td>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080D75</code></td>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080D89</code></td>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DD5</code></td>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DE7</code></td>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>main</code></td>
+    <td align="right"><code>502</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HAL_GPIO_Init</code></td>
+    <td align="right"><code>416</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClockUpdate</code></td>
+    <td align="right"><code>392</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemInit</code></td>
+    <td align="right"><code>134</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_ctors</code></td>
+    <td align="right"><code>26</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_copy</code></td>
+    <td align="right"><code>20</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_zero</code></td>
+    <td align="right"><code>18</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a)</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SysTick_Handler</code></td>
+    <td align="right"><code>16</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_start</code></td>
+    <td align="right"><code>14</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BusFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DebugMon_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HardFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MemManage_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NMI_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PendSV_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SVC_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UsageFault_Handler</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>exit</code></td>
+    <td align="right"><code>2</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADC1_2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CRYP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMIPP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DMA2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ETH1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>EXTI9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FMC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FPU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXMMU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GFXTIM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>GPU2D_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HASH_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IAC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ICACHE_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>IWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>JPEG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LOCKUP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPTIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LPUART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MCE4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>MDIOS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU0_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>NPU3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PKA_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RCC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RNG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RTC_S_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Reset_Handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAES_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI1_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_A_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SAI2_B_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SDMMC2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>SPI6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TAMP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM11_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM12_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM13_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM14_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM15_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM16_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM17_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM18_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>TIM9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART4_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART5_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART7_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART8_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UART9_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>UCPD1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART10_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USART6_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>VENC_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>WWDG_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI1_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI2_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>XSPI3_IRQHandler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Wk</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_done</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__startup_complete</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>reset_handler</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>STM32N6xx_Startup.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000004</code></td>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>SystemCoreClock</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Init</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>uwTick</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Zero</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>blto_App_lto.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Address</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>0x70080DD0</code></td>
+    <td align="right"><code>[4]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>0x70080DAC</code></td>
+    <td align="right"><code>[36]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Address</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DAC</code></td>
+    <td align="left"><code>__SEGGER_init_table__</code></td>
+    <td align="right"><code>[36]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DD0</code></td>
+    <td align="left"><code>__SEGGER_init_data__</code></td>
+    <td align="right"><code>[4]</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Cnst</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Symbol name</th>
+    <th align="right">Value</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_size__</code></td>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_end__</code></td>
+    <td align="right"><code>0x38008000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_size__</code></td>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_start__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_end__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AHB_RAM2_segment_used_start__</code></td>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_end__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_size__</code></td>
+    <td align="right"><code>0x0009C000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_start__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM1_segment_used_start__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_end__</code></td>
+    <td align="right"><code>0x34170000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_start__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_end__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM2_segment_used_start__</code></td>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_end__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_start__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_end__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM3_segment_used_start__</code></td>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_end__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_start__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_end__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM4_segment_used_start__</code></td>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_end__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_start__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_end__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM5_segment_used_start__</code></td>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_end__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_size__</code></td>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_start__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_end__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM6_segment_used_start__</code></td>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_end__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_size__</code></td>
+    <td align="right"><code>0x00040000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_start__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_end__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM7_segment_used_start__</code></td>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_end__</code></td>
+    <td align="right"><code>0x34420000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_size__</code></td>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_start__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_end__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
+    <td align="right"><code>0x3C002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_end__</code></td>
+    <td align="right"><code>0x30020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_start__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__DTCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_end__</code></td>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_size__</code></td>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x70080DFA</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x000009FA</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_end__</code></td>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_size__</code></td>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_end__</code></td>
+    <td align="right"><code>0x70080DFA</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_size__</code></td>
+    <td align="right"><code>0x000009FA</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLASH_segment_used_start__</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__FLEX_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__HEAPSIZE__</code></td>
+    <td align="right"><code>0x00000040</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_end__</code></td>
+    <td align="right"><code>0x10010000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_size__</code></td>
+    <td align="right"><code>0x00010000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_start__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ITCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_size__</code></td>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__RAM_segment_used_start__</code></td>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__STACKSIZE__</code></td>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ctors_end__</code></td>
+    <td align="right"><code>0x70080D88</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__ctors_start__</code></td>
+    <td align="right"><code>0x70080D84</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__stack_end__</code></td>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__stack_start__</code></td>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>__thread_pointer$</code></td>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>_vectors_end</code></td>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>g_pfnVectors</code></td>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+</table>
+<h2 id="SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</h2>
+
+<table>
+  <tr>
+    <th align="right">Value</th>
+    <th align="left">Symbol name</th>
+    <th align="right">Size</th>
+    <th align="right">Align</th>
+    <th align="left">Type</th>
+    <th align="left">Bd</th>
+    <th align="left">Object File</th>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__thread_pointer$</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00000040</code></td>
+    <td align="left"><code>__HEAPSIZE__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x000009FA</code></td>
+    <td align="left"><code>__FLASH_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x000009FA</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="left"><code>__STACKSIZE__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00002000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00004000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00010000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00020000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00040000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x00070000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x0009C000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="left"><code>__FLASH_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x03F7FC00</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_size__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10000000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x10010000</code></td>
+    <td align="left"><code>__ITCM_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30000000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x30020000</code></td>
+    <td align="left"><code>__DTCM_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34000000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34062000</code></td>
+    <td align="left"><code>__stack_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__stack_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__FLEX_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34064000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34100000</code></td>
+    <td align="left"><code>__AXI_RAM1_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34170000</code></td>
+    <td align="left"><code>__AXI_RAM2_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34200000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34270000</code></td>
+    <td align="left"><code>__AXI_RAM3_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x342E0000</code></td>
+    <td align="left"><code>__AXI_RAM4_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34350000</code></td>
+    <td align="left"><code>__AXI_RAM5_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x343C0000</code></td>
+    <td align="left"><code>__AXI_RAM6_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34400000</code></td>
+    <td align="left"><code>__AXI_RAM7_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x34420000</code></td>
+    <td align="left"><code>__AXI_RAM8_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38000000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38004000</code></td>
+    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x38008000</code></td>
+    <td align="left"><code>__AHB_RAM2_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C000000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x3C002000</code></td>
+    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>g_pfnVectors</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>_vectors</code></td>
+    <td align="right"><code>[844]</code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080400</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x7008074C</code></td>
+    <td align="left"><code>_vectors_end</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code>1024</code></td>
+    <td align="left"><code>Code</code></td>
+    <td align="left"><code>Lc</code></td>
+    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080D84</code></td>
+    <td align="left"><code>__ctors_start__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080D88</code></td>
+    <td align="left"><code>__ctors_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DFA</code></td>
+    <td align="left"><code>__FLASH_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x70080DFA</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_used_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="left"><code>__FLASH_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+  <tr>
+    <td align="right"><code>0x74000000</code></td>
+    <td align="left"><code>__FLASH_RAM_segment_end__</code></td>
+    <td align="right"><code></code></td>
+    <td align="right"><code></code></td>
+    <td align="left"><code>----</code></td>
+    <td align="left"><code>Gb</code></td>
+    <td align="left"><code>[ Linker created ]</code></td>
+  </tr>
+</table>
+<h1 id="REGION LIST">REGION LIST</h1>
+<h2 id="REGION LIST_Regions by name">Regions by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+  </tr>
+  <tr>
+    <td align="left"><code>AHB_RAM1</code></td>
+    <td align="left"><code>38000000-38003FFF</code></td>
+    <td align="right"><code>16 384</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AHB_RAM2</code></td>
+    <td align="left"><code>38004000-38007FFF</code></td>
+    <td align="right"><code>16 384</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM1</code></td>
+    <td align="left"><code>34064000-340FFFFF</code></td>
+    <td align="right"><code>638 976</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM2</code></td>
+    <td align="left"><code>34100000-3416FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM3</code></td>
+    <td align="left"><code>34200000-3426FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM4</code></td>
+    <td align="left"><code>34270000-342DFFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM5</code></td>
+    <td align="left"><code>342E0000-3434FFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM6</code></td>
+    <td align="left"><code>34350000-343BFFFF</code></td>
+    <td align="right"><code>458 752</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM7</code></td>
+    <td align="left"><code>343C0000-343FFFFF</code></td>
+    <td align="right"><code>262 144</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>AXI_RAM8</code></td>
+    <td align="left"><code>34400000-3441FFFF</code></td>
+    <td align="right"><code>131 072</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>BKP_RAM</code></td>
+    <td align="left"><code>3C000000-3C001FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>DTCM_RAM</code></td>
+    <td align="left"><code>30000000-3001FFFF</code></td>
+    <td align="right"><code>131 072</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH_RAM</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLEX_RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>ITCM_RAM</code></td>
+    <td align="left"><code>10000000-1000FFFF</code></td>
+    <td align="right"><code>65 536</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+  </tr>
+</table>
+<h2 id="REGION LIST_Analysis">Analysis</h2>
+
+FLASH:
+  Identical to region FLASH_RAM
+
+FLASH_RAM:
+  Identical to region FLASH
+
+FLEX_RAM:
+  Identical to region RAM
+
+RAM:
+  Identical to region FLEX_RAM
+<h1 id="BLOCK LIST">BLOCK LIST</h1>
+<h2 id="BLOCK LIST_Blocks by name">Blocks by name</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Ordering</th>
+  </tr>
+  <tr>
+    <td align="left"><code>ctors</code></td>
+    <td align="left"><code>70080D84-70080D87</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>stack</code></td>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+</table>
+<h2 id="BLOCK LIST_Blocks by address">Blocks by address</h2>
+
+<table>
+  <tr>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="left">Name</th>
+    <th align="left">Ordering</th>
+  </tr>
+  <tr>
+    <td align="left"><code>34062000-34063FFF</code></td>
+    <td align="right"><code>8 192</code></td>
+    <td align="left"><code>stack</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>70080D84-70080D87</code></td>
+    <td align="right"><code>4</code></td>
+    <td align="left"><code>ctors</code></td>
+    <td align="left"><code>Auto</code></td>
+  </tr>
+</table>
+<h1 id="STACK SIZES">STACK SIZES</h1>
+<h2 id="STACK SIZES_Functions by stack size">Functions by stack size</h2>
+
+<table>
+  <tr>
+    <th align="left">Function name</th>
+    <th align="right">Stack</th>
+    <th align="left">Object File</th>
+  </tr>
+</table>
+<h2 id="STACK SIZES_Functions without stack size information">Functions without stack size information</h2>
+
+  HAL_GPIO_Init
+  main
+  SystemCoreClockUpdate
+  NMI_Handler
+  HardFault_Handler
+  MemManage_Handler
+  BusFault_Handler
+  UsageFault_Handler
+  SVC_Handler
+  DebugMon_Handler
+  PendSV_Handler
+  SysTick_Handler
+  SystemInit
+  _start
+  __SEGGER_init_done
+  __startup_complete
+  exit
+  PVD_PVM_IRQHandler
+  DTS_IRQHandler
+  RCC_IRQHandler
+  LOCKUP_IRQHandler
+  CACHE_ECC_IRQHandler
+  TCM_ECC_IRQHandler
+  BCK_ECC_IRQHandler
+  FPU_IRQHandler
+  RTC_S_IRQHandler
+  TAMP_IRQHandler
+  RIFSC_TAMPER_IRQHandler
+  IAC_IRQHandler
+  RCC_S_IRQHandler
+  RTC_IRQHandler
+  IWDG_IRQHandler
+  WWDG_IRQHandler
+  EXTI0_IRQHandler
+  EXTI1_IRQHandler
+  EXTI2_IRQHandler
+  EXTI3_IRQHandler
+  EXTI4_IRQHandler
+  EXTI5_IRQHandler
+  EXTI6_IRQHandler
+  EXTI7_IRQHandler
+  EXTI8_IRQHandler
+  EXTI9_IRQHandler
+  EXTI10_IRQHandler
+  EXTI11_IRQHandler
+  EXTI12_IRQHandler
+  EXTI13_IRQHandler
+  EXTI14_IRQHandler
+  EXTI15_IRQHandler
+  SAES_IRQHandler
+  CRYP_IRQHandler
+  PKA_IRQHandler
+  HASH_IRQHandler
+  RNG_IRQHandler
+  MCE1_IRQHandler
+  MCE2_IRQHandler
+  MCE3_IRQHandler
+  MCE4_IRQHandler
+  ADC1_2_IRQHandler
+  CSI_IRQHandler
+  DCMIPP_IRQHandler
+  PAHB_ERR_IRQHandler
+  NPU0_IRQHandler
+  NPU1_IRQHandler
+  NPU2_IRQHandler
+  NPU3_IRQHandler
+  CACHEAXI_IRQHandler
+  LTDC_LO_IRQHandler
+  LTDC_LO_ERR_IRQHandler
+  DMA2D_IRQHandler
+  JPEG_IRQHandler
+  VENC_IRQHandler
+  GFXMMU_IRQHandler
+  GFXTIM_IRQHandler
+  GPU2D_IRQHandler
+  GPU2D_ER_IRQHandler
+  ICACHE_IRQHandler
+  HPDMA1_Channel0_IRQHandler
+  HPDMA1_Channel1_IRQHandler
+  HPDMA1_Channel2_IRQHandler
+  HPDMA1_Channel3_IRQHandler
+  HPDMA1_Channel4_IRQHandler
+  HPDMA1_Channel5_IRQHandler
+  HPDMA1_Channel6_IRQHandler
+  HPDMA1_Channel7_IRQHandler
+  HPDMA1_Channel8_IRQHandler
+  HPDMA1_Channel9_IRQHandler
+  HPDMA1_Channel10_IRQHandler
+  HPDMA1_Channel11_IRQHandler
+  HPDMA1_Channel12_IRQHandler
+  HPDMA1_Channel13_IRQHandler
+  HPDMA1_Channel14_IRQHandler
+  HPDMA1_Channel15_IRQHandler
+  GPDMA1_Channel0_IRQHandler
+  GPDMA1_Channel1_IRQHandler
+  GPDMA1_Channel2_IRQHandler
+  GPDMA1_Channel3_IRQHandler
+  GPDMA1_Channel4_IRQHandler
+  GPDMA1_Channel5_IRQHandler
+  GPDMA1_Channel6_IRQHandler
+  GPDMA1_Channel7_IRQHandler
+  GPDMA1_Channel8_IRQHandler
+  GPDMA1_Channel9_IRQHandler
+  GPDMA1_Channel10_IRQHandler
+  GPDMA1_Channel11_IRQHandler
+  GPDMA1_Channel12_IRQHandler
+  GPDMA1_Channel13_IRQHandler
+  GPDMA1_Channel14_IRQHandler
+  GPDMA1_Channel15_IRQHandler
+  I2C1_EV_IRQHandler
+  I2C1_ER_IRQHandler
+  I2C2_EV_IRQHandler
+  I2C2_ER_IRQHandler
+  I2C3_EV_IRQHandler
+  I2C3_ER_IRQHandler
+  I2C4_EV_IRQHandler
+  I2C4_ER_IRQHandler
+  I3C1_EV_IRQHandler
+  I3C1_ER_IRQHandler
+  I3C2_EV_IRQHandler
+  I3C2_ER_IRQHandler
+  TIM1_BRK_IRQHandler
+  TIM1_UP_IRQHandler
+  TIM1_TRG_CCU_IRQHandler
+  TIM1_CC_IRQHandler
+  TIM2_IRQHandler
+  TIM3_IRQHandler
+  TIM4_IRQHandler
+  TIM5_IRQHandler
+  TIM6_IRQHandler
+  TIM7_IRQHandler
+  TIM8_BRK_IRQHandler
+  TIM8_UP_IRQHandler
+  TIM8_TRG_CCU_IRQHandler
+  TIM8_CC_IRQHandler
+  TIM9_IRQHandler
+  TIM10_IRQHandler
+  TIM11_IRQHandler
+  TIM12_IRQHandler
+  TIM13_IRQHandler
+  TIM14_IRQHandler
+  TIM15_IRQHandler
+  TIM16_IRQHandler
+  TIM17_IRQHandler
+  TIM18_IRQHandler
+  LPTIM1_IRQHandler
+  LPTIM2_IRQHandler
+  LPTIM3_IRQHandler
+  LPTIM4_IRQHandler
+  LPTIM5_IRQHandler
+  ADF1_FLT0_IRQHandler
+  MDF1_FLT0_IRQHandler
+  MDF1_FLT1_IRQHandler
+  MDF1_FLT2_IRQHandler
+  MDF1_FLT3_IRQHandler
+  MDF1_FLT4_IRQHandler
+  MDF1_FLT5_IRQHandler
+  SAI1_A_IRQHandler
+  SAI1_B_IRQHandler
+  SAI2_A_IRQHandler
+  SAI2_B_IRQHandler
+  SPDIFRX_IRQHandler
+  SPI1_IRQHandler
+  SPI2_IRQHandler
+  SPI3_IRQHandler
+  SPI4_IRQHandler
+  SPI5_IRQHandler
+  SPI6_IRQHandler
+  USART1_IRQHandler
+  USART2_IRQHandler
+  USART3_IRQHandler
+  UART4_IRQHandler
+  UART5_IRQHandler
+  USART6_IRQHandler
+  UART7_IRQHandler
+  UART8_IRQHandler
+  UART9_IRQHandler
+  USART10_IRQHandler
+  LPUART1_IRQHandler
+  XSPI1_IRQHandler
+  XSPI2_IRQHandler
+  XSPI3_IRQHandler
+  FMC_IRQHandler
+  SDMMC1_IRQHandler
+  SDMMC2_IRQHandler
+  UCPD1_IRQHandler
+  USB1_OTG_HS_IRQHandler
+  USB2_OTG_HS_IRQHandler
+  ETH1_IRQHandler
+  FDCAN1_IT0_IRQHandler
+  FDCAN1_IT1_IRQHandler
+  FDCAN2_IT0_IRQHandler
+  FDCAN2_IT1_IRQHandler
+  FDCAN3_IT0_IRQHandler
+  FDCAN3_IT1_IRQHandler
+  FDCAN_CU_IRQHandler
+  MDIOS_IRQHandler
+  DCMI_PSSI_IRQHandler
+  WAKEUP_PIN_IRQHandler
+  CTI_INT0_IRQHandler
+  CTI_INT1_IRQHandler
+  LTDC_UP_IRQHandler
+  LTDC_UP_ERR_IRQHandler
+  reset_handler
+  Reset_Handler
+  __SEGGER_init_zero
+  __SEGGER_init_copy
+  __SEGGER_init_ctors
+<h1 id="UNUSED INPUTS">UNUSED INPUTS</h1>
+<h2 id="UNUSED INPUTS_Unused object files">Unused object files</h2>
+
+No unused object files
+<h1 id="ABSOLUTE LISTING">ABSOLUTE LISTING</h1>
+<h2 id="ABSOLUTE LISTING_Section .bss.uwTick from blto_App_lto.o, size=4, align=4">Section .bss.uwTick from blto_App_lto.o, size=4, align=4</h2>
+
+<pre>
+<br/><span id="uwTick">uwTick:</span>
+<span id="A34000000">  0x34000000:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000001">  0x34000001:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000002">  0x34000002:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000003">  0x34000003:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto_App_lto.o, size=4, align=4</h2>
+
+<pre>
+<br/><span id="SystemCoreClock">SystemCoreClock:</span>
+<span id="A34000004">  0x34000004:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A34000005">  0x34000005:  </span>90           DC.B       0x90                     ; '\x90'
+<span id="A34000006">  0x34000006:  </span>D0           DC.B       0xD0                     ; '\xD0'
+<span id="A34000007">  0x34000007:  </span>03           DC.B       0x03                     ; '\x03'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</h2>
+
+<pre>
+(34062000-34063FFF excluded)
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</h2>
+
+<pre>
+<br/><span id="_vectors">_vectors:</span>
+<span id="g_pfnVectors">g_pfnVectors:</span>
+<span id="A70080400">  0x70080400:  </span>34064000     DC.W       34064000               ; R_ARM_ABS32
+<span id="A70080404">  0x70080404:  </span>70080AC9     DC.W       <a href="#reset_handler">reset_handler</a>
+<span id="A70080408">  0x70080408:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008040C">  0x7008040C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080410">  0x70080410:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080414">  0x70080414:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080418">  0x70080418:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008041C">  0x7008041C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041D">  0x7008041D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041E">  0x7008041E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008041F">  0x7008041F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080420">  0x70080420:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080421">  0x70080421:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080422">  0x70080422:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080423">  0x70080423:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080424">  0x70080424:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080425">  0x70080425:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080426">  0x70080426:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080427">  0x70080427:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080428">  0x70080428:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080429">  0x70080429:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042A">  0x7008042A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042B">  0x7008042B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008042C">  0x7008042C:  </span>70080CEB     DC.W       <a href="#SVC_Handler">SVC_Handler</a>
+<span id="A70080430">  0x70080430:  </span>70080CEB     DC.W       <a href="#SVC_Handler">SVC_Handler</a>
+<span id="A70080434">  0x70080434:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080435">  0x70080435:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080436">  0x70080436:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080437">  0x70080437:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080438">  0x70080438:  </span>70080CEB     DC.W       <a href="#SVC_Handler">SVC_Handler</a>
+<span id="A7008043C">  0x7008043C:  </span>70080D75     DC.W       <a href="#SysTick_Handler">SysTick_Handler</a>
+<span id="A70080440">  0x70080440:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080444">  0x70080444:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080445">  0x70080445:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080446">  0x70080446:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080447">  0x70080447:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080448">  0x70080448:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008044C">  0x7008044C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080450">  0x70080450:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080454">  0x70080454:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080458">  0x70080458:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008045C">  0x7008045C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080460">  0x70080460:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080464">  0x70080464:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080465">  0x70080465:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080466">  0x70080466:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080467">  0x70080467:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080468">  0x70080468:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008046C">  0x7008046C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080470">  0x70080470:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080474">  0x70080474:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080478">  0x70080478:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008047C">  0x7008047C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047D">  0x7008047D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047E">  0x7008047E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008047F">  0x7008047F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080480">  0x70080480:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080484">  0x70080484:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080485">  0x70080485:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080486">  0x70080486:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080487">  0x70080487:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080488">  0x70080488:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008048C">  0x7008048C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080490">  0x70080490:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080494">  0x70080494:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080498">  0x70080498:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008049C">  0x7008049C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804A0">  0x700804A0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804A4">  0x700804A4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804A8">  0x700804A8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804AC">  0x700804AC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804B0">  0x700804B0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804B4">  0x700804B4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804B8">  0x700804B8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804BC">  0x700804BC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804C0">  0x700804C0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804C4">  0x700804C4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804C8">  0x700804C8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804CC">  0x700804CC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804D0">  0x700804D0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804D4">  0x700804D4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804D8">  0x700804D8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804DC">  0x700804DC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804E0">  0x700804E0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804E4">  0x700804E4:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E5">  0x700804E5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E6">  0x700804E6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E7">  0x700804E7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A700804E8">  0x700804E8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804EC">  0x700804EC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804F0">  0x700804F0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804F4">  0x700804F4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804F8">  0x700804F8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700804FC">  0x700804FC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080500">  0x70080500:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080504">  0x70080504:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080505">  0x70080505:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080506">  0x70080506:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080507">  0x70080507:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080508">  0x70080508:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080509">  0x70080509:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050A">  0x7008050A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050B">  0x7008050B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050C">  0x7008050C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050D">  0x7008050D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050E">  0x7008050E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A7008050F">  0x7008050F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080510">  0x70080510:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080514">  0x70080514:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080518">  0x70080518:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008051C">  0x7008051C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080520">  0x70080520:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080524">  0x70080524:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080528">  0x70080528:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008052C">  0x7008052C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080530">  0x70080530:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080534">  0x70080534:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080538">  0x70080538:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008053C">  0x7008053C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080540">  0x70080540:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080544">  0x70080544:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080548">  0x70080548:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008054C">  0x7008054C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080550">  0x70080550:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080554">  0x70080554:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080558">  0x70080558:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008055C">  0x7008055C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080560">  0x70080560:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080564">  0x70080564:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080568">  0x70080568:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008056C">  0x7008056C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080570">  0x70080570:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080574">  0x70080574:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080578">  0x70080578:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008057C">  0x7008057C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080580">  0x70080580:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080584">  0x70080584:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080588">  0x70080588:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008058C">  0x7008058C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080590">  0x70080590:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080594">  0x70080594:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080598">  0x70080598:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008059C">  0x7008059C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805A0">  0x700805A0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805A4">  0x700805A4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805A8">  0x700805A8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805AC">  0x700805AC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805B0">  0x700805B0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805B4">  0x700805B4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805B8">  0x700805B8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805BC">  0x700805BC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805C0">  0x700805C0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805C4">  0x700805C4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805C8">  0x700805C8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805CC">  0x700805CC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805D0">  0x700805D0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805D4">  0x700805D4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805D8">  0x700805D8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805DC">  0x700805DC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805E0">  0x700805E0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805E4">  0x700805E4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805E8">  0x700805E8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805EC">  0x700805EC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805F0">  0x700805F0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805F4">  0x700805F4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805F8">  0x700805F8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700805FC">  0x700805FC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080600">  0x70080600:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080604">  0x70080604:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080608">  0x70080608:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008060C">  0x7008060C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080610">  0x70080610:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080614">  0x70080614:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080618">  0x70080618:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008061C">  0x7008061C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080620">  0x70080620:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080624">  0x70080624:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080628">  0x70080628:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008062C">  0x7008062C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080630">  0x70080630:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080634">  0x70080634:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080638">  0x70080638:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008063C">  0x7008063C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080640">  0x70080640:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080644">  0x70080644:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080648">  0x70080648:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008064C">  0x7008064C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080650">  0x70080650:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080654">  0x70080654:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080658">  0x70080658:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008065C">  0x7008065C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080660">  0x70080660:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080664">  0x70080664:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080668">  0x70080668:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008066C">  0x7008066C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080670">  0x70080670:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080674">  0x70080674:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080678">  0x70080678:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008067C">  0x7008067C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080680">  0x70080680:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080684">  0x70080684:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080688">  0x70080688:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008068C">  0x7008068C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080690">  0x70080690:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080694">  0x70080694:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080698">  0x70080698:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008069C">  0x7008069C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806A0">  0x700806A0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806A4">  0x700806A4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806A8">  0x700806A8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806AC">  0x700806AC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806B0">  0x700806B0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806B4">  0x700806B4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806B8">  0x700806B8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806BC">  0x700806BC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806C0">  0x700806C0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806C4">  0x700806C4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806C8">  0x700806C8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806CC">  0x700806CC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806D0">  0x700806D0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806D4">  0x700806D4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806D8">  0x700806D8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806DC">  0x700806DC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806E0">  0x700806E0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806E4">  0x700806E4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806E8">  0x700806E8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806EC">  0x700806EC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806F0">  0x700806F0:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806F4">  0x700806F4:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806F8">  0x700806F8:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A700806FC">  0x700806FC:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080700">  0x70080700:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080704">  0x70080704:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080708">  0x70080708:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008070C">  0x7008070C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080710">  0x70080710:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080714">  0x70080714:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080718">  0x70080718:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008071C">  0x7008071C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080720">  0x70080720:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080724">  0x70080724:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080728">  0x70080728:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008072C">  0x7008072C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080730">  0x70080730:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080734">  0x70080734:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080738">  0x70080738:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A7008073C">  0x7008073C:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080740">  0x70080740:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080741">  0x70080741:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080742">  0x70080742:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080743">  0x70080743:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080744">  0x70080744:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+<span id="A70080748">  0x70080748:  </span>70080CED     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=392, align=4">Section .text.SystemCoreClockUpdate from blto_App_lto.o, size=392, align=4</h2>
+
+<pre>
+<br/><span id="SystemCoreClockUpdate">SystemCoreClockUpdate:</span>
+<span id="_vectors_end">_vectors_end:</span>
+<span id="A7008074C">  0x7008074C:  </span>F248 0020    MOVW       R0, #0x8020
+<span id="A70080750">  0x70080750:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080754">  0x70080754:  </span>6801         LDR        R1, [R0]
+<span id="A70080756">  0x70080756:  </span>F3C1 5201    UBFX       R2, R1, #20, #2
+<span id="A7008075A">  0x7008075A:  </span>F646 4100    MOVW       R1, #0x6C00
+<span id="A7008075E">  0x7008075E:  </span>F2C0 21DC    MOVT       R1, #0x02DC
+<span id="A70080762">  0x70080762:  </span>E8DF F002    TBB        91PC, R2]
+<span id="A70080766">  0x70080766:  </span>02           DC.B       0x02                     ; '\x02'
+<span id="A70080767">  0x70080767:  </span>0B           DC.B       0x0B                     ; '\v'
+<span id="A70080768">  0x70080768:  </span>AC           DC.B       0xAC                     ; '\xAC'
+<span id="A70080769">  0x70080769:  </span>18           DC.B       0x18                     ; '\x18'
+<span id="A7008076A">  0x7008076A:  </span>6A80         LDR        R0, [R0, #40]
+<span id="A7008076C">  0x7008076C:  </span>F249 0100    MOVW       R1, #0x9000
+<span id="A70080770">  0x70080770:  </span>F2C0 31D0    MOVT       R1, #0x03D0
+<span id="A70080774">  0x70080774:  </span>F3C0 10C1    UBFX       R0, R0, #7, #2
+<span id="A70080778">  0x70080778:  </span>40C1         LSRS       R1, R0
+<span id="A7008077A">  0x7008077A:  </span>E0A0         B          46L7                      ; 0x700808BE
+<span id="A7008077C">  0x7008077C:  </span>6A40         LDR        R0, [R0, #36]
+<span id="A7008077E">  0x7008077E:  </span>F242 4100    MOVW       R1, #0x2400
+<span id="A70080782">  0x70080782:  </span>F2C0 01F4    MOVT       R1, #244
+<span id="A70080786">  0x70080786:  </span>0580         LSLS       R0, R0, #22
+<span id="A70080788">  0x70080788:  </span>F100 8099    BMI.W      46L7                      ; 0x700808BE
+<span id="A7008078C">  0x7008078C:  </span>F640 1100    MOVW       R1, #0x0900
+<span id="A70080790">  0x70080790:  </span>F2C0 013D    MOVT       R1, #61
+<span id="A70080794">  0x70080794:  </span>E093         B          46L7                      ; 0x700808BE
+<span id="A70080796">  0x70080796:  </span>F8D0 20A4    LDR.W      R2, [R0, #164]
+<span id="A7008079A">  0x7008079A:  </span>F3C2 7201    UBFX       R2, R2, #28, #2
+<span id="A7008079E">  0x7008079E:  </span>B5F0         PUSH       123R4-R7, LR}
+<span id="A700807A0">  0x700807A0:  </span>E8DF F002    TBB        91PC, R2]
+<span id="A700807A4">  0x700807A4:  </span>02           DC.B       0x02                     ; '\x02'
+<span id="A700807A5">  0x700807A5:  </span>1C           DC.B       0x1C                     ; '\x1C'
+<span id="A700807A6">  0x700807A6:  </span>0A           DC.B       0x0A                     ; '\n'
+<span id="A700807A7">  0x700807A7:  </span>13           DC.B       0x13                     ; '\x13'
+<span id="A700807A8">  0x700807A8:  </span>6E02         LDR        R2, [R0, #96]
+<span id="A700807AA">  0x700807AA:  </span>0113         LSLS       R3, R2, #4
+<span id="A700807AC">  0x700807AC:  </span>D444         BMI        46L2                      ; 0x70080838
+<span id="A700807AE">  0x700807AE:  </span>F100 0C64    ADD.W      R12, R0, #100
+<span id="A700807B2">  0x700807B2:  </span>F100 0E68    ADD.W      LR, R0, #104
+<span id="A700807B6">  0x700807B6:  </span>E018         B          46L1                      ; 0x700807EA
+<span id="A700807B8">  0x700807B8:  </span>F8D0 2080    LDR.W      R2, [R0, #128]
+<span id="A700807BC">  0x700807BC:  </span>0113         LSLS       R3, R2, #4
+<span id="A700807BE">  0x700807BE:  </span>D43B         BMI        46L2                      ; 0x70080838
+<span id="A700807C0">  0x700807C0:  </span>F100 0C84    ADD.W      R12, R0, #132
+<span id="A700807C4">  0x700807C4:  </span>F100 0E88    ADD.W      LR, R0, #136
+<span id="A700807C8">  0x700807C8:  </span>E00F         B          46L1                      ; 0x700807EA
+<span id="A700807CA">  0x700807CA:  </span>F8D0 2090    LDR.W      R2, [R0, #144]
+<span id="A700807CE">  0x700807CE:  </span>0113         LSLS       R3, R2, #4
+<span id="A700807D0">  0x700807D0:  </span>D432         BMI        46L2                      ; 0x70080838
+<span id="A700807D2">  0x700807D2:  </span>F100 0C94    ADD.W      R12, R0, #148
+<span id="A700807D6">  0x700807D6:  </span>F100 0E98    ADD.W      LR, R0, #152
+<span id="A700807DA">  0x700807DA:  </span>E006         B          46L1                      ; 0x700807EA
+<span id="A700807DC">  0x700807DC:  </span>6F02         LDR        R2, [R0, #112]
+<span id="A700807DE">  0x700807DE:  </span>0113         LSLS       R3, R2, #4
+<span id="A700807E0">  0x700807E0:  </span>D42A         BMI        46L2                      ; 0x70080838
+<span id="A700807E2">  0x700807E2:  </span>F100 0C74    ADD.W      R12, R0, #116
+<span id="A700807E6">  0x700807E6:  </span>F100 0E78    ADD.W      LR, R0, #120
+<br/>.L1:
+<span id="A700807EA">  0x700807EA:  </span>F8DC 3000    LDR.W      R3, [R12]
+<span id="A700807EE">  0x700807EE:  </span>F3C2 240B    UBFX       R4, R2, #8, #12
+<span id="A700807F2">  0x700807F2:  </span>F023 437F    BIC        R3, R3, #0xFF000000
+<span id="A700807F6">  0x700807F6:  </span>EE01 3A10    VMOV       S2, R3
+<span id="A700807FA">  0x700807FA:  </span>F8DE 5000    LDR.W      R5, [LR]
+<span id="A700807FE">  0x700807FE:  </span>EE00 4A10    VMOV       S0, R4
+<span id="A70080802">  0x70080802:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
+<span id="A70080806">  0x70080806:  </span>ED9F 2A32    VLDR       S4, =0x33800000          ; [PC, #200] [0x700808D0]
+<span id="A7008080A">  0x7008080A:  </span>F3C2 5705    UBFX       R7, R2, #20, #6
+<span id="A7008080E">  0x7008080E:  </span>F3C5 66C2    UBFX       R6, R5, #27, #3
+<span id="A70080812">  0x70080812:  </span>EEB8 0A40    VCVT.F32.U32 S0, S0
+<span id="A70080816">  0x70080816:  </span>EE21 1A02    VMUL.F32   S2, S2, S4
+<span id="A7008081A">  0x7008081A:  </span>F3C5 6302    UBFX       R3, R5, #24, #3
+<span id="A7008081E">  0x7008081E:  </span>EE31 0A00    VADD.F32   S0, S2, S0
+<span id="A70080822">  0x70080822:  </span>EE01 7A10    VMOV       S2, R7
+<span id="A70080826">  0x70080826:  </span>4373         MULS       R3, R6, R3
+<span id="A70080828">  0x70080828:  </span>EEB8 2A41    VCVT.F32.U32 S4, S2
+<span id="A7008082C">  0x7008082C:  </span>EE01 3A10    VMOV       S2, R3
+<span id="A70080830">  0x70080830:  </span>2301         MOVS       R3, #1
+<span id="A70080832">  0x70080832:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
+<span id="A70080836">  0x70080836:  </span>E006         B          46L3                      ; 0x70080846
+<br/>.L2:
+<span id="A70080838">  0x70080838:  </span>ED9F 0A24    VLDR       S0, =0x00000000          ; [PC, #144] [0x700808CC]
+<span id="A7008083C">  0x7008083C:  </span>2300         MOVS       R3, #0
+<span id="A7008083E">  0x7008083E:  </span>EEB0 1A40    VMOV.F32   S2, S0
+<span id="A70080842">  0x70080842:  </span>EEB0 2A40    VMOV.F32   S4, S0
+<br/>.L3:
+<span id="A70080846">  0x70080846:  </span>F3C2 7202    UBFX       R2, R2, #28, #3
+<span id="A7008084A">  0x7008084A:  </span>2A03         CMP        R2, #3
+<span id="A7008084C">  0x7008084C:  </span>D81E         BHI        46L4                      ; 0x7008088C
+<span id="A7008084E">  0x7008084E:  </span>E8DF F002    TBB        91PC, R2]
+<span id="A70080852">  0x70080852:  </span>02           DC.B       0x02                     ; '\x02'
+<span id="A70080853">  0x70080853:  </span>0C           DC.B       0x0C                     ; '\x0C'
+<span id="A70080854">  0x70080854:  </span>1E           DC.B       0x1E                     ; '\x1E'
+<span id="A70080855">  0x70080855:  </span>18           DC.B       0x18                     ; '\x18'
+<span id="A70080856">  0x70080856:  </span>6A81         LDR        R1, [R0, #40]
+<span id="A70080858">  0x70080858:  </span>F249 0200    MOVW       R2, #0x9000
+<span id="A7008085C">  0x7008085C:  </span>F2C0 32D0    MOVT       R2, #0x03D0
+<span id="A70080860">  0x70080860:  </span>F3C1 11C1    UBFX       R1, R1, #7, #2
+<span id="A70080864">  0x70080864:  </span>FA22 F101    LSR.W      R1, R2, R1
+<span id="A70080868">  0x70080868:  </span>E011         B          46L5                      ; 0x7008088E
+<span id="A7008086A">  0x7008086A:  </span>6A41         LDR        R1, [R0, #36]
+<span id="A7008086C">  0x7008086C:  </span>0589         LSLS       R1, R1, #22
+<span id="A7008086E">  0x7008086E:  </span>F242 4100    MOVW       R1, #0x2400
+<span id="A70080872">  0x70080872:  </span>F2C0 01F4    MOVT       R1, #244
+<span id="A70080876">  0x70080876:  </span>D40A         BMI        46L5                      ; 0x7008088E
+<span id="A70080878">  0x70080878:  </span>F640 1100    MOVW       R1, #0x0900
+<span id="A7008087C">  0x7008087C:  </span>F2C0 013D    MOVT       R1, #61
+<span id="A70080880">  0x70080880:  </span>E005         B          46L5                      ; 0x7008088E
+<span id="A70080882">  0x70080882:  </span>F248 0100    MOVW       R1, #0x8000
+<span id="A70080886">  0x70080886:  </span>F2C0 01BB    MOVT       R1, #187
+<span id="A7008088A">  0x7008088A:  </span>E000         B          46L5                      ; 0x7008088E
+<br/>.L4:
+<span id="A7008088C">  0x7008088C:  </span>2100         MOVS       R1, #0
+<br/>.L5:
+<span id="A7008088E">  0x7008088E:  </span>B16B         CBZ        R3, .L6                  ; 0x700808AC
+<span id="A70080890">  0x70080890:  </span>EE03 1A10    VMOV       S6, R1
+<span id="A70080894">  0x70080894:  </span>EEB8 3A43    VCVT.F32.U32 S6, S6
+<span id="A70080898">  0x70080898:  </span>EE20 0A03    VMUL.F32   S0, S0, S6
+<span id="A7008089C">  0x7008089C:  </span>EE80 0A02    VDIV.F32   S0, S0, S4
+<span id="A700808A0">  0x700808A0:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
+<span id="A700808A4">  0x700808A4:  </span>EEBC 0AC0    VCVT.U32.F32 S0, S0
+<span id="A700808A8">  0x700808A8:  </span>EE10 1A10    VMOV       R1, S0
+<br/>.L6:
+<span id="A700808AC">  0x700808AC:  </span>F8D0 00A4    LDR.W      R0, [R0, #164]
+<span id="A700808B0">  0x700808B0:  </span>2201         MOVS       R2, #1
+<span id="A700808B2">  0x700808B2:  </span>FA52 F0A0    UXTAB      R0, R2, R0, ROR #16
+<span id="A700808B6">  0x700808B6:  </span>FBB1 F1F0    UDIV       R1, R1, R0
+<span id="A700808BA">  0x700808BA:  </span>E8BD 40F0    POP.W      123R4-R7, LR}
+<br/>.L7:
+<span id="A700808BE">  0x700808BE:  </span>F240 0004    MOVW       R0, #4                   ; 0x34000004 = SystemCoreClock
+<span id="A700808C2">  0x700808C2:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x34000004 = SystemCoreClock
+<span id="A700808C6">  0x700808C6:  </span>6001         STR        R1, [R0]
+<span id="A700808C8">  0x700808C8:  </span>4770         BX         LR
+<span id="A700808CA">  0x700808CA:  </span>BF00         NOP
+<span id="A700808CC">  0x700808CC:  </span>00000000     DC.W       0x00000000
+<span id="A700808D0">  0x700808D0:  </span>33800000     DC.W       0x33800000
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto_App_lto.o, size=416, align=4">Section .text.HAL_GPIO_Init from blto_App_lto.o, size=416, align=4</h2>
+
+<pre>
+<br/><span id="HAL_GPIO_Init">HAL_GPIO_Init:</span>
+<span id="A700808D4">  0x700808D4:  </span>E92D 4FF0    PUSH.W     123R4-R11, LR}
+<span id="A700808D8">  0x700808D8:  </span>B083         SUB        SP, SP, #12
+<span id="A700808DA">  0x700808DA:  </span>680C         LDR        R4, [R1]
+<span id="A700808DC">  0x700808DC:  </span>2C00         CMP        R4, #0
+<span id="A700808DE">  0x700808DE:  </span>F000 80C6    BEQ.W      46L6                      ; 0x70080A6E
+<span id="A700808E2">  0x700808E2:  </span>F100 4228    ADD.W      R2, R0, #0xA8000000
+<span id="A700808E6">  0x700808E6:  </span>F24E 06FF    MOVW       R6, #0xE0FF
+<span id="A700808EA">  0x700808EA:  </span>F102 72FF    ADD.W      R2, R2, #0x01FE0000
+<span id="A700808EE">  0x700808EE:  </span>2500         MOVS       R5, #0
+<span id="A700808F0">  0x700808F0:  </span>EA4F 27B2    ROR        R7, R2, #10
+<span id="A700808F4">  0x700808F4:  </span>F244 0200    MOVW       R2, #0x4000
+<span id="A700808F8">  0x700808F8:  </span>F2C5 6202    MOVT       R2, #0x5602
+<span id="A700808FC">  0x700808FC:  </span>4290         CMP        R0, R2
+<span id="A700808FE">  0x700808FE:  </span>BF14         ITE        NE
+<span id="A70080900">  0x70080900:  </span>2210         MOVNE      R2, #16
+<span id="A70080902">  0x70080902:  </span>220B         MOVEQ      R2, #11
+<span id="A70080904">  0x70080904:  </span>2F10         CMP        R7, #16
+<span id="A70080906">  0x70080906:  </span>9700         STR        R7, [SP, #0]
+<span id="A70080908">  0x70080908:  </span>B2BF         UXTH       R7, R7
+<span id="A7008090A">  0x7008090A:  </span>EA5F 932F    CSET       R3, CC
+<span id="A7008090E">  0x7008090E:  </span>FA26 F707    LSR.W      R7, R6, R7
+<span id="A70080912">  0x70080912:  </span>9202         STR        R2, [SP, #8]
+<span id="A70080914">  0x70080914:  </span>EA03 0207    AND.W      R2, R3, R7
+<span id="A70080918">  0x70080918:  </span>9201         STR        R2, [SP, #4]
+<span id="A7008091A">  0x7008091A:  </span>BF00         NOP
+<br/>.L1:
+<span id="A7008091C">  0x7008091C:  </span>2201         MOVS       R2, #1
+<span id="A7008091E">  0x7008091E:  </span>FA02 FA05    LSL.W      R10, R2, R5
+<span id="A70080922">  0x70080922:  </span>EA1A 0804    ANDS.W     R8, R10, R4
+<span id="A70080926">  0x70080926:  </span>F000 809C    BEQ.W      46L5                      ; 0x70080A62
+<span id="A7008092A">  0x7008092A:  </span>E9D1 9E01    LDRD       R9, LR, [R1, #4]
+<span id="A7008092E">  0x7008092E:  </span>F009 0B03    AND        R11, R9, #3
+<span id="A70080932">  0x70080932:  </span>F1AB 0301    SUB.W      R3, R11, #1
+<span id="A70080936">  0x70080936:  </span>2B01         CMP        R3, #1
+<span id="A70080938">  0x70080938:  </span>D816         BHI        46L2                      ; 0x70080968
+<span id="A7008093A">  0x7008093A:  </span>68CB         LDR        R3, [R1, #12]
+<span id="A7008093C">  0x7008093C:  </span>2203         MOVS       R2, #3
+<span id="A7008093E">  0x7008093E:  </span>6886         LDR        R6, [R0, #8]
+<span id="A70080940">  0x70080940:  </span>EA4F 0C45    LSL.W      R12, R5, #1
+<span id="A70080944">  0x70080944:  </span>FA02 F70C    LSL.W      R7, R2, R12
+<span id="A70080948">  0x70080948:  </span>43BE         BICS       R6, R7
+<span id="A7008094A">  0x7008094A:  </span>FA03 F30C    LSL.W      R3, R3, R12
+<span id="A7008094E">  0x7008094E:  </span>4333         ORRS       R3, R6
+<span id="A70080950">  0x70080950:  </span>6083         STR        R3, [R0, #8]
+<span id="A70080952">  0x70080952:  </span>43FC         MVNS       R4, R7
+<span id="A70080954">  0x70080954:  </span>6843         LDR        R3, [R0, #4]
+<span id="A70080956">  0x70080956:  </span>F3C9 1700    UBFX       R7, R9, #4, #1
+<span id="A7008095A">  0x7008095A:  </span>EA23 030A    BIC.W      R3, R3, R10
+<span id="A7008095E">  0x7008095E:  </span>40AF         LSLS       R7, R5
+<span id="A70080960">  0x70080960:  </span>433B         ORRS       R3, R7
+<span id="A70080962">  0x70080962:  </span>6043         STR        R3, [R0, #4]
+<span id="A70080964">  0x70080964:  </span>E00A         B          46L3                      ; 0x7008097C
+<span id="A70080966">  0x70080966:  </span>BF00         NOP
+<br/>.L2:
+<span id="A70080968">  0x70080968:  </span>F1BB 0F03    CMP.W      R11, #3
+<span id="A7008096C">  0x7008096C:  </span>BF08         IT         EQ
+<span id="A7008096E">  0x7008096E:  </span>4596         CMPEQ      LR, R2
+<span id="A70080970">  0x70080970:  </span>D025         BEQ        46L4                      ; 0x700809BE
+<span id="A70080972">  0x70080972:  </span>006B         LSLS       R3, R5, #1
+<span id="A70080974">  0x70080974:  </span>2203         MOVS       R2, #3
+<span id="A70080976">  0x70080976:  </span>FA02 F303    LSL.W      R3, R2, R3
+<span id="A7008097A">  0x7008097A:  </span>43DC         MVNS       R4, R3
+<br/>.L3:
+<span id="A7008097C">  0x7008097C:  </span>68C3         LDR        R3, [R0, #12]
+<span id="A7008097E">  0x7008097E:  </span>006F         LSLS       R7, R5, #1
+<span id="A70080980">  0x70080980:  </span>4023         ANDS       R3, R4
+<span id="A70080982">  0x70080982:  </span>FA0E F707    LSL.W      R7, LR, R7
+<span id="A70080986">  0x70080986:  </span>433B         ORRS       R3, R7
+<span id="A70080988">  0x70080988:  </span>F1BB 0F02    CMP.W      R11, #2
+<span id="A7008098C">  0x7008098C:  </span>60C3         STR        R3, [R0, #12]
+<span id="A7008098E">  0x7008098E:  </span>D116         BNE        46L4                      ; 0x700809BE
+<span id="A70080990">  0x70080990:  </span>43D2         MVNS       R2, R2
+<span id="A70080992">  0x70080992:  </span>F100 0C20    ADD.W      R12, R0, #32
+<span id="A70080996">  0x70080996:  </span>EA02 0755    AND.W      R7, R2, R5, LSR #1
+<span id="A7008099A">  0x7008099A:  </span>221C         MOVS       R2, #28
+<span id="A7008099C">  0x7008099C:  </span>690B         LDR        R3, [R1, #16]
+<span id="A7008099E">  0x7008099E:  </span>EA02 0685    AND.W      R6, R2, R5, LSL #2
+<span id="A700809A2">  0x700809A2:  </span>F85C 4007    LDR.W      R4, [R12, R7]
+<span id="A700809A6">  0x700809A6:  </span>220F         MOVS       R2, #15
+<span id="A700809A8">  0x700809A8:  </span>40B2         LSLS       R2, R6
+<span id="A700809AA">  0x700809AA:  </span>EA24 0202    BIC.W      R2, R4, R2
+<span id="A700809AE">  0x700809AE:  </span>40B3         LSLS       R3, R6
+<span id="A700809B0">  0x700809B0:  </span>431A         ORRS       R2, R3
+<span id="A700809B2">  0x700809B2:  </span>F84C 2007    STR.W      R2, [R12, R7]
+<span id="A700809B6">  0x700809B6:  </span>F8D1 9004    LDR.W      R9, [R1, #4]
+<span id="A700809BA">  0x700809BA:  </span>F009 0B03    AND        R11, R9, #3
+<br/>.L4:
+<span id="A700809BE">  0x700809BE:  </span>6802         LDR        R2, [R0]
+<span id="A700809C0">  0x700809C0:  </span>2703         MOVS       R7, #3
+<span id="A700809C2">  0x700809C2:  </span>006B         LSLS       R3, R5, #1
+<span id="A700809C4">  0x700809C4:  </span>409F         LSLS       R7, R3
+<span id="A700809C6">  0x700809C6:  </span>43BA         BICS       R2, R7
+<span id="A700809C8">  0x700809C8:  </span>FA0B F303    LSL.W      R3, R11, R3
+<span id="A700809CC">  0x700809CC:  </span>431A         ORRS       R2, R3
+<span id="A700809CE">  0x700809CE:  </span>F419 3F40    TST        R9, #0x030000
+<span id="A700809D2">  0x700809D2:  </span>6002         STR        R2, [R0]
+<span id="A700809D4">  0x700809D4:  </span>D045         BEQ        46L5                      ; 0x70080A62
+<span id="A700809D6">  0x700809D6:  </span>240F         MOVS       R4, #15
+<span id="A700809D8">  0x700809D8:  </span>F245 0C60    MOVW       R12, #0x5060
+<span id="A700809DC">  0x700809DC:  </span>F2C5 6C02    MOVT       R12, #0x5602
+<span id="A700809E0">  0x700809E0:  </span>F025 0203    BIC        R2, R5, #3
+<span id="A700809E4">  0x700809E4:  </span>F85C 6002    LDR.W      R6, [R12, R2]
+<span id="A700809E8">  0x700809E8:  </span>E9DD 2301    LDRD       R2, R3, [SP, #4]
+<span id="A700809EC">  0x700809EC:  </span>08AF         LSRS       R7, R5, #2
+<span id="A700809EE">  0x700809EE:  </span>2A00         CMP        R2, #0
+<span id="A700809F0">  0x700809F0:  </span>BF1F         ITTTT      NE
+<span id="A700809F2">  0x700809F2:  </span>9A00         LDRNE      R2, [SP, #0]
+<span id="A700809F4">  0x700809F4:  </span>F640 2374    MOVWNE     R3, #0x0A74              ; 0x70080A74 = .rodata..Lswitch.table.HAL_GPIO_DeInit
+<span id="A700809F8">  0x700809F8:  </span>F2C7 0308    MOVTNE     R3, #0x7008              ; 0x70080A74 = .rodata..Lswitch.table.HAL_GPIO_DeInit
+<span id="A700809FC">  0x700809FC:  </span>F853 3022    LDRNE.W    R3, [R3, R2, LSL #2]
+<span id="A70080A00">  0x70080A00:  </span>2218         MOVS       R2, #24
+<span id="A70080A02">  0x70080A02:  </span>EA02 02C5    AND.W      R2, R2, R5, LSL #3
+<span id="A70080A06">  0x70080A06:  </span>4094         LSLS       R4, R2
+<span id="A70080A08">  0x70080A08:  </span>43A6         BICS       R6, R4
+<span id="A70080A0A">  0x70080A0A:  </span>F1AC 0460    SUB.W      R4, R12, #96
+<span id="A70080A0E">  0x70080A0E:  </span>FA03 F202    LSL.W      R2, R3, R2
+<span id="A70080A12">  0x70080A12:  </span>4332         ORRS       R2, R6
+<span id="A70080A14">  0x70080A14:  </span>F84C 2027    STR.W      R2, [R12, R7, LSL #2]
+<span id="A70080A18">  0x70080A18:  </span>F8D4 2080    LDR.W      R2, [R4, #128]
+<span id="A70080A1C">  0x70080A1C:  </span>684B         LDR        R3, [R1, #4]
+<span id="A70080A1E">  0x70080A1E:  </span>EA42 0708    ORR.W      R7, R2, R8
+<span id="A70080A22">  0x70080A22:  </span>03DE         LSLS       R6, R3, #15
+<span id="A70080A24">  0x70080A24:  </span>BF58         IT         PL
+<span id="A70080A26">  0x70080A26:  </span>EA22 0708    BICPL.W    R7, R2, R8
+<span id="A70080A2A">  0x70080A2A:  </span>F8C4 7080    STR.W      R7, [R4, #128]
+<span id="A70080A2E">  0x70080A2E:  </span>F8D4 2084    LDR.W      R2, [R4, #132]
+<span id="A70080A32">  0x70080A32:  </span>EA42 0708    ORR.W      R7, R2, R8
+<span id="A70080A36">  0x70080A36:  </span>039E         LSLS       R6, R3, #14
+<span id="A70080A38">  0x70080A38:  </span>BF58         IT         PL
+<span id="A70080A3A">  0x70080A3A:  </span>EA22 0708    BICPL.W    R7, R2, R8
+<span id="A70080A3E">  0x70080A3E:  </span>F8C4 7084    STR.W      R7, [R4, #132]
+<span id="A70080A42">  0x70080A42:  </span>6822         LDR        R2, [R4]
+<span id="A70080A44">  0x70080A44:  </span>EA42 0708    ORR.W      R7, R2, R8
+<span id="A70080A48">  0x70080A48:  </span>02DE         LSLS       R6, R3, #11
+<span id="A70080A4A">  0x70080A4A:  </span>BF58         IT         PL
+<span id="A70080A4C">  0x70080A4C:  </span>EA22 0708    BICPL.W    R7, R2, R8
+<span id="A70080A50">  0x70080A50:  </span>6027         STR        R7, [R4]
+<span id="A70080A52">  0x70080A52:  </span>6862         LDR        R2, [R4, #4]
+<span id="A70080A54">  0x70080A54:  </span>EA42 0708    ORR.W      R7, R2, R8
+<span id="A70080A58">  0x70080A58:  </span>029B         LSLS       R3, R3, #10
+<span id="A70080A5A">  0x70080A5A:  </span>BF58         IT         PL
+<span id="A70080A5C">  0x70080A5C:  </span>EA22 0708    BICPL.W    R7, R2, R8
+<span id="A70080A60">  0x70080A60:  </span>6067         STR        R7, [R4, #4]
+<br/>.L5:
+<span id="A70080A62">  0x70080A62:  </span>680C         LDR        R4, [R1]
+<span id="A70080A64">  0x70080A64:  </span>3501         ADDS       R5, #1
+<span id="A70080A66">  0x70080A66:  </span>FA34 F205    LSRS.W     R2, R4, R5
+<span id="A70080A6A">  0x70080A6A:  </span>F47F AF57    BNE.W      46L1                      ; 0x7008091C
+<br/>.L6:
+<span id="A70080A6E">  0x70080A6E:  </span>B003         ADD        SP, SP, #12
+<span id="A70080A70">  0x70080A70:  </span>E8BD 8FF0    POP.W      123R4-R11, PC}
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto_App_lto.o, size=64, align=4">Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto_App_lto.o, size=64, align=4</h2>
+
+<pre>
+<span id="A70080A74">  0x70080A74:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A75">  0x70080A75:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A76">  0x70080A76:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A77">  0x70080A77:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A78">  0x70080A78:  </span>01           DC.B       0x01                     ; '\x01'
+<span id="A70080A79">  0x70080A79:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A7A">  0x70080A7A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A7B">  0x70080A7B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A7C">  0x70080A7C:  </span>02           DC.B       0x02                     ; '\x02'
+<span id="A70080A7D">  0x70080A7D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A7E">  0x70080A7E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A7F">  0x70080A7F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A80">  0x70080A80:  </span>03           DC.B       0x03                     ; '\x03'
+<span id="A70080A81">  0x70080A81:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A82">  0x70080A82:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A83">  0x70080A83:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A84">  0x70080A84:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70080A85">  0x70080A85:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A86">  0x70080A86:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A87">  0x70080A87:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A88">  0x70080A88:  </span>05           DC.B       0x05                     ; '\x05'
+<span id="A70080A89">  0x70080A89:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A8A">  0x70080A8A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A8B">  0x70080A8B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A8C">  0x70080A8C:  </span>06           DC.B       0x06                     ; '\x06'
+<span id="A70080A8D">  0x70080A8D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A8E">  0x70080A8E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A8F">  0x70080A8F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A90">  0x70080A90:  </span>07           DC.B       0x07                     ; '\x07'
+<span id="A70080A91">  0x70080A91:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A92">  0x70080A92:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A93">  0x70080A93:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A94">  0x70080A94:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A95">  0x70080A95:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A96">  0x70080A96:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A97">  0x70080A97:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A98">  0x70080A98:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A99">  0x70080A99:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9A">  0x70080A9A:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9B">  0x70080A9B:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9C">  0x70080A9C:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9D">  0x70080A9D:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9E">  0x70080A9E:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080A9F">  0x70080A9F:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA0">  0x70080AA0:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA1">  0x70080AA1:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA2">  0x70080AA2:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA3">  0x70080AA3:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA4">  0x70080AA4:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA5">  0x70080AA5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA6">  0x70080AA6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA7">  0x70080AA7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AA8">  0x70080AA8:  </span>08           DC.B       0x08                     ; '\b'
+<span id="A70080AA9">  0x70080AA9:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AAA">  0x70080AAA:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AAB">  0x70080AAB:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AAC">  0x70080AAC:  </span>09           DC.B       0x09                     ; '\t'
+<span id="A70080AAD">  0x70080AAD:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AAE">  0x70080AAE:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AAF">  0x70080AAF:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AB0">  0x70080AB0:  </span>0A           DC.B       0x0A                     ; '\n'
+<span id="A70080AB1">  0x70080AB1:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AB2">  0x70080AB2:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AB3">  0x70080AB3:  </span>00           DC.B       0x00                     ; '\0'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</h2>
+
+<pre>
+<br/><span id="_start">_start:</span>
+<span id="A70080AB4">  0x70080AB4:  </span>4C03         LDR        R4, =0x70080DAC          ; [PC, #12] [0x70080AC4] 
+<br/>.L1:
+<span id="A70080AB6">  0x70080AB6:  </span>6820         LDR        R0, [R4]
+<span id="A70080AB8">  0x70080AB8:  </span>3404         ADDS       R4, #4
+<span id="A70080ABA">  0x70080ABA:  </span>4780         BLX        R0
+<span id="A70080ABC">  0x70080ABC:  </span>E7FB         B          46L1                      ; 0x70080AB6
+<br/><span id="__SEGGER_init_done">__SEGGER_init_done:</span>
+<span id="__startup_complete">__startup_complete:</span>
+<span id="A70080ABE">  0x70080ABE:  </span>F000 F819    BL         <a href="#main">main</a>                     ; 0x70080AF4
+<br/><span id="exit">exit:</span>
+<span id="A70080AC2">  0x70080AC2:  </span>E7FE         B          <a href="#exit">exit</a>                     ; 0x70080AC2
+<span id="A70080AC4">  0x70080AC4:  </span>70080DAC     DC.W       70080DAC               ; R_ARM_ABS32
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</h2>
+
+<pre>
+<br/><span id="reset_handler">reset_handler:</span>
+<span id="Reset_Handler">Reset_Handler:</span>
+<span id="A70080AC8">  0x70080AC8:  </span>4909         LDR        R1, =0x34062000          ; [PC, #36] [0x70080AF0] 
+<span id="A70080ACA">  0x70080ACA:  </span>F381 880A    MSR        MSPLIM, R1
+<span id="A70080ACE">  0x70080ACE:  </span>F04F 0100    MOV.W      R1, #0
+<span id="A70080AD2">  0x70080AD2:  </span>F381 880B    MSR        PSPLIM, R1
+<span id="A70080AD6">  0x70080AD6:  </span>F000 F90A    BL         <a href="#SystemInit">SystemInit</a>               ; 0x70080CEE
+<span id="A70080ADA">  0x70080ADA:  </span>F64E 5088    MOVW       R0, #0xED88
+<span id="A70080ADE">  0x70080ADE:  </span>F2CE 0000    MOVT       R0, #0xE000
+<span id="A70080AE2">  0x70080AE2:  </span>6801         LDR        R1, [R0]
+<span id="A70080AE4">  0x70080AE4:  </span>F451 0170    ORRS       R1, R1, #0xF00000
+<span id="A70080AE8">  0x70080AE8:  </span>6001         STR        R1, [R0]
+<span id="A70080AEA">  0x70080AEA:  </span>F7FF FFE3    BL         <a href="#_start">_start</a>                   ; 0x70080AB4
+<span id="A70080AEE">  0x70080AEE:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AEF">  0x70080AEF:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080AF0">  0x70080AF0:  </span>34062000     DC.W       34062000               ; R_ARM_ABS32
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.main from blto_App_lto.o, size=502, align=4">Section .text.main from blto_App_lto.o, size=502, align=4</h2>
+
+<pre>
+<br/><span id="main">main:</span>
+<span id="A70080AF4">  0x70080AF4:  </span>B086         SUB        SP, SP, #24
+<span id="A70080AF6">  0x70080AF6:  </span>F64E 540C    MOVW       R4, #0xED0C
+<span id="A70080AFA">  0x70080AFA:  </span>F64F 01FF    MOVW       R1, #0xF8FF
+<span id="A70080AFE">  0x70080AFE:  </span>F2CE 0400    MOVT       R4, #0xE000
+<span id="A70080B02">  0x70080B02:  </span>6820         LDR        R0, [R4]
+<span id="A70080B04">  0x70080B04:  </span>4008         ANDS       R0, R1
+<span id="A70080B06">  0x70080B06:  </span>F240 3100    MOVW       R1, #0x0300
+<span id="A70080B0A">  0x70080B0A:  </span>F2C0 51FA    MOVT       R1, #0x05FA
+<span id="A70080B0E">  0x70080B0E:  </span>4308         ORRS       R0, R1
+<span id="A70080B10">  0x70080B10:  </span>6020         STR        R0, [R4]
+<span id="A70080B12">  0x70080B12:  </span>F7FF FE1B    BL         <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>    ; 0x7008074C
+<span id="A70080B16">  0x70080B16:  </span>F240 0004    MOVW       R0, #4                   ; 0x34000004 = SystemCoreClock
+<span id="A70080B1A">  0x70080B1A:  </span>F644 51D3    MOVW       R1, #0x4DD3
+<span id="A70080B1E">  0x70080B1E:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x34000004 = SystemCoreClock
+<span id="A70080B22">  0x70080B22:  </span>6800         LDR        R0, [R0]
+<span id="A70080B24">  0x70080B24:  </span>F2C1 0162    MOVT       R1, #0x1062
+<span id="A70080B28">  0x70080B28:  </span>FBA0 0101    UMULL      R0, R1, R0, R1
+<span id="A70080B2C">  0x70080B2C:  </span>F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+<span id="A70080B30">  0x70080B30:  </span>EB00 1191    ADD.W      R1, R0, R1, LSR #6
+<span id="A70080B34">  0x70080B34:  </span>0E0A         LSRS       R2, R1, #24
+<span id="A70080B36">  0x70080B36:  </span>D117         BNE        46L1                      ; 0x70080B68
+<span id="A70080B38">  0x70080B38:  </span>F6A4 42FC    SUBW       R2, R4, #0x0CFC
+<span id="A70080B3C">  0x70080B3C:  </span>6051         STR        R1, [R2, #4]
+<span id="A70080B3E">  0x70080B3E:  </span>21F0         MOVS       R1, #240
+<span id="A70080B40">  0x70080B40:  </span>75E1         STRB       R1, [R4, #23]
+<span id="A70080B42">  0x70080B42:  </span>2100         MOVS       R1, #0
+<span id="A70080B44">  0x70080B44:  </span>6091         STR        R1, [R2, #8]
+<span id="A70080B46">  0x70080B46:  </span>2107         MOVS       R1, #7
+<span id="A70080B48">  0x70080B48:  </span>6011         STR        R1, [R2]
+<span id="A70080B4A">  0x70080B4A:  </span>6821         LDR        R1, [R4]
+<span id="A70080B4C">  0x70080B4C:  </span>F3C1 2102    UBFX       R1, R1, #8, #3
+<span id="A70080B50">  0x70080B50:  </span>F081 0207    EOR        R2, R1, #7
+<span id="A70080B54">  0x70080B54:  </span>2A04         CMP        R2, #4
+<span id="A70080B56">  0x70080B56:  </span>BF28         IT         CS
+<span id="A70080B58">  0x70080B58:  </span>2204         MOVCS      R2, #4
+<span id="A70080B5A">  0x70080B5A:  </span>4090         LSLS       R0, R2
+<span id="A70080B5C">  0x70080B5C:  </span>43C0         MVNS       R0, R0
+<span id="A70080B5E">  0x70080B5E:  </span>3903         SUBS       R1, #3
+<span id="A70080B60">  0x70080B60:  </span>BF28         IT         CS
+<span id="A70080B62">  0x70080B62:  </span>4088         LSLCS      R0, R1
+<span id="A70080B64">  0x70080B64:  </span>0100         LSLS       R0, R0, #4
+<span id="A70080B66">  0x70080B66:  </span>75E0         STRB       R0, [R4, #23]
+<br/>.L1:
+<span id="A70080B68">  0x70080B68:  </span>F248 205C    MOVW       R0, #0x825C
+<span id="A70080B6C">  0x70080B6C:  </span>2600         MOVS       R6, #0
+<span id="A70080B6E">  0x70080B6E:  </span>F2C5 6002    MOVT       R0, #0x5602
+<span id="A70080B72">  0x70080B72:  </span>F44F 3180    MOV.W      R1, #0x010000
+<span id="A70080B76">  0x70080B76:  </span>E9CD 6603    STRD       R6, R6, [SP, #12]
+<span id="A70080B7A">  0x70080B7A:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080B7E">  0x70080B7E:  </span>6801         LDR        R1, [R0]
+<span id="A70080B80">  0x70080B80:  </span>2703         MOVS       R7, #3
+<span id="A70080B82">  0x70080B82:  </span>1EFC         SUBS       R4, R7, #3
+<span id="A70080B84">  0x70080B84:  </span>F2C5 6402    MOVT       R4, #0x5602
+<span id="A70080B88">  0x70080B88:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080B8A">  0x70080B8A:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080B8C">  0x70080B8C:  </span>2104         MOVS       R1, #4
+<span id="A70080B8E">  0x70080B8E:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080B92">  0x70080B92:  </span>6801         LDR        R1, [R0]
+<span id="A70080B94">  0x70080B94:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080B96">  0x70080B96:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080B98">  0x70080B98:  </span>2110         MOVS       R1, #16
+<span id="A70080B9A">  0x70080B9A:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080B9E">  0x70080B9E:  </span>6801         LDR        R1, [R0]
+<span id="A70080BA0">  0x70080BA0:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BA2">  0x70080BA2:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BA4">  0x70080BA4:  </span>2108         MOVS       R1, #8
+<span id="A70080BA6">  0x70080BA6:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BAA">  0x70080BAA:  </span>6801         LDR        R1, [R0]
+<span id="A70080BAC">  0x70080BAC:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BAE">  0x70080BAE:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BB0">  0x70080BB0:  </span>2180         MOVS       R1, #128
+<span id="A70080BB2">  0x70080BB2:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BB6">  0x70080BB6:  </span>6801         LDR        R1, [R0]
+<span id="A70080BB8">  0x70080BB8:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BBA">  0x70080BBA:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BBC">  0x70080BBC:  </span>2102         MOVS       R1, #2
+<span id="A70080BBE">  0x70080BBE:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BC2">  0x70080BC2:  </span>6801         LDR        R1, [R0]
+<span id="A70080BC4">  0x70080BC4:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BC6">  0x70080BC6:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BC8">  0x70080BC8:  </span>F44F 4100    MOV.W      R1, #0x8000
+<span id="A70080BCC">  0x70080BCC:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BD0">  0x70080BD0:  </span>6801         LDR        R1, [R0]
+<span id="A70080BD2">  0x70080BD2:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BD4">  0x70080BD4:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BD6">  0x70080BD6:  </span>F44F 4180    MOV.W      R1, #0x4000
+<span id="A70080BDA">  0x70080BDA:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BDE">  0x70080BDE:  </span>6801         LDR        R1, [R0]
+<span id="A70080BE0">  0x70080BE0:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BE2">  0x70080BE2:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BE4">  0x70080BE4:  </span>2140         MOVS       R1, #64
+<span id="A70080BE6">  0x70080BE6:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BEA">  0x70080BEA:  </span>6801         LDR        R1, [R0]
+<span id="A70080BEC">  0x70080BEC:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BEE">  0x70080BEE:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BF0">  0x70080BF0:  </span>2120         MOVS       R1, #32
+<span id="A70080BF2">  0x70080BF2:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080BF6">  0x70080BF6:  </span>6801         LDR        R1, [R0]
+<span id="A70080BF8">  0x70080BF8:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080BFA">  0x70080BFA:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080BFC">  0x70080BFC:  </span>F44F 5100    MOV.W      R1, #0x2000
+<span id="A70080C00">  0x70080C00:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080C04">  0x70080C04:  </span>6801         LDR        R1, [R0]
+<span id="A70080C06">  0x70080C06:  </span>9105         STR        R1, [SP, #20]
+<span id="A70080C08">  0x70080C08:  </span>9905         LDR        R1, [SP, #20]
+<span id="A70080C0A">  0x70080C0A:  </span>2101         MOVS       R1, #1
+<span id="A70080C0C">  0x70080C0C:  </span>F8C0 1800    STR.W      R1, [R0, #0x0800]
+<span id="A70080C10">  0x70080C10:  </span>4669         MOV        R1, SP
+<span id="A70080C12">  0x70080C12:  </span>6800         LDR        R0, [R0]
+<span id="A70080C14">  0x70080C14:  </span>9005         STR        R0, [SP, #20]
+<span id="A70080C16">  0x70080C16:  </span>9805         LDR        R0, [SP, #20]
+<span id="A70080C18">  0x70080C18:  </span>20FF         MOVS       R0, #255
+<span id="A70080C1A">  0x70080C1A:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C1C">  0x70080C1C:  </span>E9CD 0700    STRD       R0, R7, [SP]
+<span id="A70080C20">  0x70080C20:  </span>F504 4080    ADD.W      R0, R4, #0x4000
+<span id="A70080C24">  0x70080C24:  </span>F7FF FE56    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C28">  0x70080C28:  </span>F643 70FF    MOVW       R0, #0x3FFF
+<span id="A70080C2C">  0x70080C2C:  </span>4669         MOV        R1, SP
+<span id="A70080C2E">  0x70080C2E:  </span>E9CD 0700    STRD       R0, R7, [SP]
+<span id="A70080C32">  0x70080C32:  </span>F504 6000    ADD.W      R0, R4, #0x0800
+<span id="A70080C36">  0x70080C36:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C38">  0x70080C38:  </span>F7FF FE4C    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C3C">  0x70080C3C:  </span>F64F 75FF    MOVW       R5, #0xFFFF
+<span id="A70080C40">  0x70080C40:  </span>F504 5080    ADD.W      R0, R4, #0x1000
+<span id="A70080C44">  0x70080C44:  </span>4669         MOV        R1, SP
+<span id="A70080C46">  0x70080C46:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C48">  0x70080C48:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080C4C">  0x70080C4C:  </span>F7FF FE42    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C50">  0x70080C50:  </span>F504 6040    ADD.W      R0, R4, #0x0C00
+<span id="A70080C54">  0x70080C54:  </span>4669         MOV        R1, SP
+<span id="A70080C56">  0x70080C56:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080C5A">  0x70080C5A:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C5C">  0x70080C5C:  </span>F7FF FE3A    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C60">  0x70080C60:  </span>F44F 707F    MOV.W      R0, #0x03FC
+<span id="A70080C64">  0x70080C64:  </span>4669         MOV        R1, SP
+<span id="A70080C66">  0x70080C66:  </span>E9CD 0700    STRD       R0, R7, [SP]
+<span id="A70080C6A">  0x70080C6A:  </span>F504 50E0    ADD.W      R0, R4, #0x1C00
+<span id="A70080C6E">  0x70080C6E:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C70">  0x70080C70:  </span>F7FF FE30    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C74">  0x70080C74:  </span>F504 6080    ADD.W      R0, R4, #0x0400
+<span id="A70080C78">  0x70080C78:  </span>4669         MOV        R1, SP
+<span id="A70080C7A">  0x70080C7A:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080C7E">  0x70080C7E:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C80">  0x70080C80:  </span>F7FF FE28    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C84">  0x70080C84:  </span>F504 5070    ADD.W      R0, R4, #0x3C00
+<span id="A70080C88">  0x70080C88:  </span>4669         MOV        R1, SP
+<span id="A70080C8A">  0x70080C8A:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080C8E">  0x70080C8E:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080C90">  0x70080C90:  </span>F7FF FE20    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080C94">  0x70080C94:  </span>203F         MOVS       R0, #63
+<span id="A70080C96">  0x70080C96:  </span>4669         MOV        R1, SP
+<span id="A70080C98">  0x70080C98:  </span>E9CD 0700    STRD       R0, R7, [SP]
+<span id="A70080C9C">  0x70080C9C:  </span>F504 5060    ADD.W      R0, R4, #0x3800
+<span id="A70080CA0">  0x70080CA0:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080CA2">  0x70080CA2:  </span>F7FF FE17    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080CA6">  0x70080CA6:  </span>F504 50C0    ADD.W      R0, R4, #0x1800
+<span id="A70080CAA">  0x70080CAA:  </span>4669         MOV        R1, SP
+<span id="A70080CAC">  0x70080CAC:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080CB0">  0x70080CB0:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080CB2">  0x70080CB2:  </span>F7FF FE0F    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080CB6">  0x70080CB6:  </span>F504 50A0    ADD.W      R0, R4, #0x1400
+<span id="A70080CBA">  0x70080CBA:  </span>4669         MOV        R1, SP
+<span id="A70080CBC">  0x70080CBC:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080CC0">  0x70080CC0:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080CC2">  0x70080CC2:  </span>F7FF FE07    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080CC6">  0x70080CC6:  </span>F641 70FF    MOVW       R0, #0x1FFF
+<span id="A70080CCA">  0x70080CCA:  </span>4669         MOV        R1, SP
+<span id="A70080CCC">  0x70080CCC:  </span>E9CD 0700    STRD       R0, R7, [SP]
+<span id="A70080CD0">  0x70080CD0:  </span>F504 5050    ADD.W      R0, R4, #0x3400
+<span id="A70080CD4">  0x70080CD4:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080CD6">  0x70080CD6:  </span>F7FF FDFD    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<span id="A70080CDA">  0x70080CDA:  </span>4620         MOV        R0, R4
+<span id="A70080CDC">  0x70080CDC:  </span>4669         MOV        R1, SP
+<span id="A70080CDE">  0x70080CDE:  </span>E9CD 5700    STRD       R5, R7, [SP]
+<span id="A70080CE2">  0x70080CE2:  </span>9602         STR        R6, [SP, #8]
+<span id="A70080CE4">  0x70080CE4:  </span>F7FF FDF6    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x700808D4
+<br/>.L2:
+<span id="A70080CE8">  0x70080CE8:  </span>E7FE         B          46L2                      ; 0x70080CE8
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SVC_Handler from blto_App_lto.o, size=2, align=2">Section .text.SVC_Handler from blto_App_lto.o, size=2, align=2</h2>
+
+<pre>
+<br/><span id="SVC_Handler">SVC_Handler:</span>
+<span id="DebugMon_Handler">DebugMon_Handler:</span>
+<span id="PendSV_Handler">PendSV_Handler:</span>
+<span id="A70080CEA">  0x70080CEA:  </span>4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4">Section .text.NMI_Handler from blto_App_lto.o, size=2, align=4</h2>
+
+<pre>
+<br/><span id="NMI_Handler">NMI_Handler:</span>
+<span id="HardFault_Handler">HardFault_Handler:</span>
+<span id="MemManage_Handler">MemManage_Handler:</span>
+<span id="BusFault_Handler">BusFault_Handler:</span>
+<span id="UsageFault_Handler">UsageFault_Handler:</span>
+<span id="PVD_PVM_IRQHandler">PVD_PVM_IRQHandler:</span>
+<span id="DTS_IRQHandler">DTS_IRQHandler:</span>
+<span id="RCC_IRQHandler">RCC_IRQHandler:</span>
+<span id="LOCKUP_IRQHandler">LOCKUP_IRQHandler:</span>
+<span id="CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler:</span>
+<span id="TCM_ECC_IRQHandler">TCM_ECC_IRQHandler:</span>
+<span id="BCK_ECC_IRQHandler">BCK_ECC_IRQHandler:</span>
+<span id="FPU_IRQHandler">FPU_IRQHandler:</span>
+<span id="RTC_S_IRQHandler">RTC_S_IRQHandler:</span>
+<span id="TAMP_IRQHandler">TAMP_IRQHandler:</span>
+<span id="RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler:</span>
+<span id="IAC_IRQHandler">IAC_IRQHandler:</span>
+<span id="RCC_S_IRQHandler">RCC_S_IRQHandler:</span>
+<span id="RTC_IRQHandler">RTC_IRQHandler:</span>
+<span id="IWDG_IRQHandler">IWDG_IRQHandler:</span>
+<span id="WWDG_IRQHandler">WWDG_IRQHandler:</span>
+<span id="EXTI0_IRQHandler">EXTI0_IRQHandler:</span>
+<span id="EXTI1_IRQHandler">EXTI1_IRQHandler:</span>
+<span id="EXTI2_IRQHandler">EXTI2_IRQHandler:</span>
+<span id="EXTI3_IRQHandler">EXTI3_IRQHandler:</span>
+<span id="EXTI4_IRQHandler">EXTI4_IRQHandler:</span>
+<span id="EXTI5_IRQHandler">EXTI5_IRQHandler:</span>
+<span id="EXTI6_IRQHandler">EXTI6_IRQHandler:</span>
+<span id="EXTI7_IRQHandler">EXTI7_IRQHandler:</span>
+<span id="EXTI8_IRQHandler">EXTI8_IRQHandler:</span>
+<span id="EXTI9_IRQHandler">EXTI9_IRQHandler:</span>
+<span id="EXTI10_IRQHandler">EXTI10_IRQHandler:</span>
+<span id="EXTI11_IRQHandler">EXTI11_IRQHandler:</span>
+<span id="EXTI12_IRQHandler">EXTI12_IRQHandler:</span>
+<span id="EXTI13_IRQHandler">EXTI13_IRQHandler:</span>
+<span id="EXTI14_IRQHandler">EXTI14_IRQHandler:</span>
+<span id="EXTI15_IRQHandler">EXTI15_IRQHandler:</span>
+<span id="SAES_IRQHandler">SAES_IRQHandler:</span>
+<span id="CRYP_IRQHandler">CRYP_IRQHandler:</span>
+<span id="PKA_IRQHandler">PKA_IRQHandler:</span>
+<span id="HASH_IRQHandler">HASH_IRQHandler:</span>
+<span id="RNG_IRQHandler">RNG_IRQHandler:</span>
+<span id="MCE1_IRQHandler">MCE1_IRQHandler:</span>
+<span id="MCE2_IRQHandler">MCE2_IRQHandler:</span>
+<span id="MCE3_IRQHandler">MCE3_IRQHandler:</span>
+<span id="MCE4_IRQHandler">MCE4_IRQHandler:</span>
+<span id="ADC1_2_IRQHandler">ADC1_2_IRQHandler:</span>
+<span id="CSI_IRQHandler">CSI_IRQHandler:</span>
+<span id="DCMIPP_IRQHandler">DCMIPP_IRQHandler:</span>
+<span id="PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler:</span>
+<span id="NPU0_IRQHandler">NPU0_IRQHandler:</span>
+<span id="NPU1_IRQHandler">NPU1_IRQHandler:</span>
+<span id="NPU2_IRQHandler">NPU2_IRQHandler:</span>
+<span id="NPU3_IRQHandler">NPU3_IRQHandler:</span>
+<span id="CACHEAXI_IRQHandler">CACHEAXI_IRQHandler:</span>
+<span id="LTDC_LO_IRQHandler">LTDC_LO_IRQHandler:</span>
+<span id="LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler:</span>
+<span id="DMA2D_IRQHandler">DMA2D_IRQHandler:</span>
+<span id="JPEG_IRQHandler">JPEG_IRQHandler:</span>
+<span id="VENC_IRQHandler">VENC_IRQHandler:</span>
+<span id="GFXMMU_IRQHandler">GFXMMU_IRQHandler:</span>
+<span id="GFXTIM_IRQHandler">GFXTIM_IRQHandler:</span>
+<span id="GPU2D_IRQHandler">GPU2D_IRQHandler:</span>
+<span id="GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler:</span>
+<span id="ICACHE_IRQHandler">ICACHE_IRQHandler:</span>
+<span id="HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler:</span>
+<span id="HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler:</span>
+<span id="HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler:</span>
+<span id="HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler:</span>
+<span id="HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler:</span>
+<span id="HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler:</span>
+<span id="HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler:</span>
+<span id="HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler:</span>
+<span id="HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler:</span>
+<span id="HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler:</span>
+<span id="HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler:</span>
+<span id="HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler:</span>
+<span id="HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler:</span>
+<span id="HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler:</span>
+<span id="HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler:</span>
+<span id="HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler:</span>
+<span id="GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler:</span>
+<span id="GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler:</span>
+<span id="GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler:</span>
+<span id="GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler:</span>
+<span id="GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler:</span>
+<span id="GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler:</span>
+<span id="GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler:</span>
+<span id="GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler:</span>
+<span id="GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler:</span>
+<span id="GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler:</span>
+<span id="GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler:</span>
+<span id="GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler:</span>
+<span id="GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler:</span>
+<span id="GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler:</span>
+<span id="GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler:</span>
+<span id="GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler:</span>
+<span id="I2C1_EV_IRQHandler">I2C1_EV_IRQHandler:</span>
+<span id="I2C1_ER_IRQHandler">I2C1_ER_IRQHandler:</span>
+<span id="I2C2_EV_IRQHandler">I2C2_EV_IRQHandler:</span>
+<span id="I2C2_ER_IRQHandler">I2C2_ER_IRQHandler:</span>
+<span id="I2C3_EV_IRQHandler">I2C3_EV_IRQHandler:</span>
+<span id="I2C3_ER_IRQHandler">I2C3_ER_IRQHandler:</span>
+<span id="I2C4_EV_IRQHandler">I2C4_EV_IRQHandler:</span>
+<span id="I2C4_ER_IRQHandler">I2C4_ER_IRQHandler:</span>
+<span id="I3C1_EV_IRQHandler">I3C1_EV_IRQHandler:</span>
+<span id="I3C1_ER_IRQHandler">I3C1_ER_IRQHandler:</span>
+<span id="I3C2_EV_IRQHandler">I3C2_EV_IRQHandler:</span>
+<span id="I3C2_ER_IRQHandler">I3C2_ER_IRQHandler:</span>
+<span id="TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler:</span>
+<span id="TIM1_UP_IRQHandler">TIM1_UP_IRQHandler:</span>
+<span id="TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler:</span>
+<span id="TIM1_CC_IRQHandler">TIM1_CC_IRQHandler:</span>
+<span id="TIM2_IRQHandler">TIM2_IRQHandler:</span>
+<span id="TIM3_IRQHandler">TIM3_IRQHandler:</span>
+<span id="TIM4_IRQHandler">TIM4_IRQHandler:</span>
+<span id="TIM5_IRQHandler">TIM5_IRQHandler:</span>
+<span id="TIM6_IRQHandler">TIM6_IRQHandler:</span>
+<span id="TIM7_IRQHandler">TIM7_IRQHandler:</span>
+<span id="TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler:</span>
+<span id="TIM8_UP_IRQHandler">TIM8_UP_IRQHandler:</span>
+<span id="TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler:</span>
+<span id="TIM8_CC_IRQHandler">TIM8_CC_IRQHandler:</span>
+<span id="TIM9_IRQHandler">TIM9_IRQHandler:</span>
+<span id="TIM10_IRQHandler">TIM10_IRQHandler:</span>
+<span id="TIM11_IRQHandler">TIM11_IRQHandler:</span>
+<span id="TIM12_IRQHandler">TIM12_IRQHandler:</span>
+<span id="TIM13_IRQHandler">TIM13_IRQHandler:</span>
+<span id="TIM14_IRQHandler">TIM14_IRQHandler:</span>
+<span id="TIM15_IRQHandler">TIM15_IRQHandler:</span>
+<span id="TIM16_IRQHandler">TIM16_IRQHandler:</span>
+<span id="TIM17_IRQHandler">TIM17_IRQHandler:</span>
+<span id="TIM18_IRQHandler">TIM18_IRQHandler:</span>
+<span id="LPTIM1_IRQHandler">LPTIM1_IRQHandler:</span>
+<span id="LPTIM2_IRQHandler">LPTIM2_IRQHandler:</span>
+<span id="LPTIM3_IRQHandler">LPTIM3_IRQHandler:</span>
+<span id="LPTIM4_IRQHandler">LPTIM4_IRQHandler:</span>
+<span id="LPTIM5_IRQHandler">LPTIM5_IRQHandler:</span>
+<span id="ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler:</span>
+<span id="MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler:</span>
+<span id="MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler:</span>
+<span id="MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler:</span>
+<span id="MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler:</span>
+<span id="MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler:</span>
+<span id="MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler:</span>
+<span id="SAI1_A_IRQHandler">SAI1_A_IRQHandler:</span>
+<span id="SAI1_B_IRQHandler">SAI1_B_IRQHandler:</span>
+<span id="SAI2_A_IRQHandler">SAI2_A_IRQHandler:</span>
+<span id="SAI2_B_IRQHandler">SAI2_B_IRQHandler:</span>
+<span id="SPDIFRX_IRQHandler">SPDIFRX_IRQHandler:</span>
+<span id="SPI1_IRQHandler">SPI1_IRQHandler:</span>
+<span id="SPI2_IRQHandler">SPI2_IRQHandler:</span>
+<span id="SPI3_IRQHandler">SPI3_IRQHandler:</span>
+<span id="SPI4_IRQHandler">SPI4_IRQHandler:</span>
+<span id="SPI5_IRQHandler">SPI5_IRQHandler:</span>
+<span id="SPI6_IRQHandler">SPI6_IRQHandler:</span>
+<span id="USART1_IRQHandler">USART1_IRQHandler:</span>
+<span id="USART2_IRQHandler">USART2_IRQHandler:</span>
+<span id="USART3_IRQHandler">USART3_IRQHandler:</span>
+<span id="UART4_IRQHandler">UART4_IRQHandler:</span>
+<span id="UART5_IRQHandler">UART5_IRQHandler:</span>
+<span id="USART6_IRQHandler">USART6_IRQHandler:</span>
+<span id="UART7_IRQHandler">UART7_IRQHandler:</span>
+<span id="UART8_IRQHandler">UART8_IRQHandler:</span>
+<span id="UART9_IRQHandler">UART9_IRQHandler:</span>
+<span id="USART10_IRQHandler">USART10_IRQHandler:</span>
+<span id="LPUART1_IRQHandler">LPUART1_IRQHandler:</span>
+<span id="XSPI1_IRQHandler">XSPI1_IRQHandler:</span>
+<span id="XSPI2_IRQHandler">XSPI2_IRQHandler:</span>
+<span id="XSPI3_IRQHandler">XSPI3_IRQHandler:</span>
+<span id="FMC_IRQHandler">FMC_IRQHandler:</span>
+<span id="SDMMC1_IRQHandler">SDMMC1_IRQHandler:</span>
+<span id="SDMMC2_IRQHandler">SDMMC2_IRQHandler:</span>
+<span id="UCPD1_IRQHandler">UCPD1_IRQHandler:</span>
+<span id="USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler:</span>
+<span id="USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler:</span>
+<span id="ETH1_IRQHandler">ETH1_IRQHandler:</span>
+<span id="FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler:</span>
+<span id="FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler:</span>
+<span id="FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler:</span>
+<span id="FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler:</span>
+<span id="FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler:</span>
+<span id="FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler:</span>
+<span id="FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler:</span>
+<span id="MDIOS_IRQHandler">MDIOS_IRQHandler:</span>
+<span id="DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler:</span>
+<span id="WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler:</span>
+<span id="CTI_INT0_IRQHandler">CTI_INT0_IRQHandler:</span>
+<span id="CTI_INT1_IRQHandler">CTI_INT1_IRQHandler:</span>
+<span id="LTDC_UP_IRQHandler">LTDC_UP_IRQHandler:</span>
+<span id="LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler:</span>
+<span id="A70080CEC">  0x70080CEC:  </span>E7FE         B          <a href="#NMI_Handler">NMI_Handler</a>              ; Dedupe identical section .init.LTDC_UP_ERR_IRQHandler
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SystemInit from blto_App_lto.o, size=134, align=2">Section .text.SystemInit from blto_App_lto.o, size=134, align=2</h2>
+
+<pre>
+<br/><span id="SystemInit">SystemInit:</span>
+<span id="A70080CEE">  0x70080CEE:  </span>F64E 5008    MOVW       R0, #0xED08
+<span id="A70080CF2">  0x70080CF2:  </span>2204         MOVS       R2, #4
+<span id="A70080CF4">  0x70080CF4:  </span>F2CE 0000    MOVT       R0, #0xE000
+<span id="A70080CF8">  0x70080CF8:  </span>F248 0310    MOVW       R3, #0x8010
+<span id="A70080CFC">  0x70080CFC:  </span>F8D0 1084    LDR.W      R1, [R0, #132]
+<span id="A70080D00">  0x70080D00:  </span>F2C5 6300    MOVT       R3, #0x5600
+<span id="A70080D04">  0x70080D04:  </span>F441 6140    ORR        R1, R1, #0x0C00
+<span id="A70080D08">  0x70080D08:  </span>F8C0 1084    STR.W      R1, [R0, #132]
+<span id="A70080D0C">  0x70080D0C:  </span>F8D0 122C    LDR.W      R1, [R0, #0x022C]
+<span id="A70080D10">  0x70080D10:  </span>F362 619C    BFI        R1, R2, #26, #3
+<span id="A70080D14">  0x70080D14:  </span>F8C0 122C    STR.W      R1, [R0, #0x022C]
+<span id="A70080D18">  0x70080D18:  </span>2200         MOVS       R2, #0
+<span id="A70080D1A">  0x70080D1A:  </span>F6A0 1188    SUBW       R1, R0, #0x0988
+<span id="A70080D1E">  0x70080D1E:  </span>600A         STR        R2, [R1]
+<span id="A70080D20">  0x70080D20:  </span>604A         STR        R2, [R1, #4]
+<span id="A70080D22">  0x70080D22:  </span>608A         STR        R2, [R1, #8]
+<span id="A70080D24">  0x70080D24:  </span>60CA         STR        R2, [R1, #12]
+<span id="A70080D26">  0x70080D26:  </span>610A         STR        R2, [R1, #16]
+<span id="A70080D28">  0x70080D28:  </span>614A         STR        R2, [R1, #20]
+<span id="A70080D2A">  0x70080D2A:  </span>618A         STR        R2, [R1, #24]
+<span id="A70080D2C">  0x70080D2C:  </span>F240 4100    MOVW       R1, #0x0400              ; 0x70080400 = g_pfnVectors
+<span id="A70080D30">  0x70080D30:  </span>F2C7 0108    MOVT       R1, #0x7008              ; 0x70080400 = g_pfnVectors
+<span id="A70080D34">  0x70080D34:  </span>2201         MOVS       R2, #1
+<span id="A70080D36">  0x70080D36:  </span>6001         STR        R1, [R0]
+<span id="A70080D38">  0x70080D38:  </span>F248 2178    MOVW       R1, #0x8278
+<span id="A70080D3C">  0x70080D3C:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D40">  0x70080D40:  </span>F8C1 2800    STR.W      R2, [R1, #0x0800]
+<span id="A70080D44">  0x70080D44:  </span>6809         LDR        R1, [R1]
+<span id="A70080D46">  0x70080D46:  </span>6801         LDR        R1, [R0]
+<span id="A70080D48">  0x70080D48:  </span>6019         STR        R1, [R3]
+<span id="A70080D4A">  0x70080D4A:  </span>6819         LDR        R1, [R3]
+<span id="A70080D4C">  0x70080D4C:  </span>F249 2178    MOVW       R1, #0x9278
+<span id="A70080D50">  0x70080D50:  </span>F2C5 6102    MOVT       R1, #0x5602
+<span id="A70080D54">  0x70080D54:  </span>600A         STR        R2, [R1]
+<span id="A70080D56">  0x70080D56:  </span>F8D0 1080    LDR.W      R1, [R0, #128]
+<span id="A70080D5A">  0x70080D5A:  </span>F441 0170    ORR        R1, R1, #0xF00000
+<span id="A70080D5E">  0x70080D5E:  </span>F8C0 1080    STR.W      R1, [R0, #128]
+<span id="A70080D62">  0x70080D62:  </span>F64E 5088    MOVW       R0, #0xED88
+<span id="A70080D66">  0x70080D66:  </span>F2CE 0002    MOVT       R0, #0xE002
+<span id="A70080D6A">  0x70080D6A:  </span>6801         LDR        R1, [R0]
+<span id="A70080D6C">  0x70080D6C:  </span>F441 0170    ORR        R1, R1, #0xF00000
+<span id="A70080D70">  0x70080D70:  </span>6001         STR        R1, [R0]
+<span id="A70080D72">  0x70080D72:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .text.SysTick_Handler from blto_App_lto.o, size=16, align=2">Section .text.SysTick_Handler from blto_App_lto.o, size=16, align=2</h2>
+
+<pre>
+<br/><span id="SysTick_Handler">SysTick_Handler:</span>
+<span id="A70080D74">  0x70080D74:  </span>F240 0000    MOVW       R0, #0                   ; 0x34000000 = uwTick
+<span id="A70080D78">  0x70080D78:  </span>F2C3 4000    MOVT       R0, #0x3400              ; 0x34000000 = uwTick
+<span id="A70080D7C">  0x70080D7C:  </span>6801         LDR        R1, [R0]
+<span id="A70080D7E">  0x70080D7E:  </span>3101         ADDS       R1, #1
+<span id="A70080D80">  0x70080D80:  </span>6001         STR        R1, [R0]
+<span id="A70080D82">  0x70080D82:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</h2>
+
+<pre>
+<span id="A70080D84">  0x70080D84:  </span>7008074D     DC.W       <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=36, align=4</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_ctors">__SEGGER_init_ctors:</span>
+<span id="A70080D88">  0x70080D88:  </span>B500         PUSH       123LR}
+<span id="A70080D8A">  0x70080D8A:  </span>4806         LDR        R0, =0x70080D84          ; [PC, #24] [0x70080DA4] 
+<span id="A70080D8C">  0x70080D8C:  </span>4906         LDR        R1, =__SEGGER_init_ctors ; [PC, #24] [0x70080DA8] =0x70080D88 
+<br/>.L1:
+<span id="A70080D8E">  0x70080D8E:  </span>4288         CMP        R0, R1
+<span id="A70080D90">  0x70080D90:  </span>D005         BEQ        46L2                      ; 0x70080D9E
+<span id="A70080D92">  0x70080D92:  </span>6802         LDR        R2, [R0]
+<span id="A70080D94">  0x70080D94:  </span>3004         ADDS       R0, #4
+<span id="A70080D96">  0x70080D96:  </span>B403         PUSH       123R0-R1}
+<span id="A70080D98">  0x70080D98:  </span>4790         BLX        R2
+<span id="A70080D9A">  0x70080D9A:  </span>BC03         POP        123R0-R1}
+<span id="A70080D9C">  0x70080D9C:  </span>E7F7         B          46L1                      ; 0x70080D8E
+<br/>.L2:
+<span id="A70080D9E">  0x70080D9E:  </span>BC08         POP        123R3}
+<span id="A70080DA0">  0x70080DA0:  </span>4718         BX         R3
+<span id="A70080DA2">  0x70080DA2:  </span>0000         NOP
+<span id="A70080DA4">  0x70080DA4:  </span>70080D84     DC.W       70080D84               ; R_ARM_ABS32
+<span id="A70080DA8">  0x70080DA8:  </span>70080D88     DC.W       <a href="#__SEGGER_init_ctors">__SEGGER_init_ctors</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</h2>
+
+<pre>
+<span id="A70080DAC">  0x70080DAC:  </span>70080DD5     DC.W       <a href="#__SEGGER_init_zero">__SEGGER_init_zero</a>
+<span id="A70080DB0">  0x70080DB0:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB1">  0x70080DB1:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB2">  0x70080DB2:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB3">  0x70080DB3:  </span>34           DC.B       0x34                     ; '4'
+<span id="A70080DB4">  0x70080DB4:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70080DB5">  0x70080DB5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB6">  0x70080DB6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB7">  0x70080DB7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DB8">  0x70080DB8:  </span>70080DE7     DC.W       <a href="#__SEGGER_init_copy">__SEGGER_init_copy</a>
+<span id="A70080DBC">  0x70080DBC:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70080DBD">  0x70080DBD:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DBE">  0x70080DBE:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DBF">  0x70080DBF:  </span>34           DC.B       0x34                     ; '4'
+<span id="A70080DC0">  0x70080DC0:  </span>70080DD0     DC.W       70080DD0               ; R_ARM_ABS32
+<span id="A70080DC4">  0x70080DC4:  </span>04           DC.B       0x04                     ; '\x04'
+<span id="A70080DC5">  0x70080DC5:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DC6">  0x70080DC6:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DC7">  0x70080DC7:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DC8">  0x70080DC8:  </span>70080D89     DC.W       <a href="#__SEGGER_init_ctors">__SEGGER_init_ctors</a>
+<span id="A70080DCC">  0x70080DCC:  </span>70080ABF     DC.W       <a href="#__SEGGER_init_done">__SEGGER_init_done</a>
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=4, align=4">Section .segger.init.data from [ Linker created ], size=4, align=4</h2>
+
+<pre>
+<span id="A70080DD0">  0x70080DD0:  </span>00           DC.B       0x00                     ; '\0'
+<span id="A70080DD1">  0x70080DD1:  </span>90           DC.B       0x90                     ; '\x90'
+<span id="A70080DD2">  0x70080DD2:  </span>D0           DC.B       0xD0                     ; '\xD0'
+<span id="A70080DD3">  0x70080DD3:  </span>03           DC.B       0x03                     ; '\x03'
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=18, align=2</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_zero">__SEGGER_init_zero:</span>
+<span id="A70080DD4">  0x70080DD4:  </span>6820         LDR        R0, [R4]
+<span id="A70080DD6">  0x70080DD6:  </span>6861         LDR        R1, [R4, #4]
+<span id="A70080DD8">  0x70080DD8:  </span>3408         ADDS       R4, #8
+<span id="A70080DDA">  0x70080DDA:  </span>2200         MOVS       R2, #0
+<span id="A70080DDC">  0x70080DDC:  </span>E000         B          46L2                      ; 0x70080DE0
+<br/>.L1:
+<span id="A70080DDE">  0x70080DDE:  </span>5442         STRB       R2, [R0, R1]
+<br/>.L2:
+<span id="A70080DE0">  0x70080DE0:  </span>1E49         SUBS       R1, R1, #1
+<span id="A70080DE2">  0x70080DE2:  </span>D5FC         BPL        46L1                      ; 0x70080DDE
+<span id="A70080DE4">  0x70080DE4:  </span>4770         BX         LR
+</pre>
+<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi.a), size=20, align=2</h2>
+
+<pre>
+<br/><span id="__SEGGER_init_copy">__SEGGER_init_copy:</span>
+<span id="A70080DE6">  0x70080DE6:  </span>6820         LDR        R0, [R4]
+<span id="A70080DE8">  0x70080DE8:  </span>6861         LDR        R1, [R4, #4]
+<span id="A70080DEA">  0x70080DEA:  </span>68A2         LDR        R2, [R4, #8]
+<span id="A70080DEC">  0x70080DEC:  </span>340C         ADDS       R4, #12
+<span id="A70080DEE">  0x70080DEE:  </span>E001         B          46L2                      ; 0x70080DF4
+<br/>.L1:
+<span id="A70080DF0">  0x70080DF0:  </span>5C8B         LDRB       R3, [R1, R2]
+<span id="A70080DF2">  0x70080DF2:  </span>5483         STRB       R3, [R0, R2]
+<br/>.L2:
+<span id="A70080DF4">  0x70080DF4:  </span>1E52         SUBS       R2, R2, #1
+<span id="A70080DF6">  0x70080DF6:  </span>D5FB         BPL        46L1                      ; 0x70080DF0
+<span id="A70080DF8">  0x70080DF8:  </span>4770         BX         LR
+</pre>
+<h1 id="OPTIMIZATION REPORT">OPTIMIZATION REPORT</h1>
+<h2 id="OPTIMIZATION REPORT_Transformations performed">Transformations performed</h2>
+
+<table>
+  <tr>
+    <th align="left">Transformation</th>
+    <th align="right">Bytes saved</th>
+  </tr>
+  <tr>
+    <td align="left"><code>Dedupe code</code></td>
+    <td align="right"><code>384</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>Total:</code></td>
+    <td align="right"><code>384</code></td>
+  </tr>
+<h1 id="LINK SUMMARY">LINK SUMMARY</h1>
+<h2 id="LINK SUMMARY_Memory breakdown">Memory breakdown</h2>
+
+<pre>
+  2 446 bytes read-only  code    + 
+    104 bytes read-only  data    =   2 550 bytes read-only (total)
+  8 200 bytes read-write data
+</pre>
+<h2 id="LINK SUMMARY_Region summary">Region summary</h2>
+
+<table>
+  <tr>
+    <th align="left">Name</th>
+    <th align="left">Range</th>
+    <th align="right">Size</th>
+    <th align="right">Used</th>
+    <th align="right">Unused</th>
+    <th align="right">Alignment Loss</th>
+  </tr>
+  <tr>
+    <td align="left"><code>FLEX_RAM</code></td>
+    <td align="left"><code>34000000-34063FFF</code></td>
+    <td align="right"><code>409 600</code></td>
+    <td align="right"><code>8 200   2.00</code></td>
+    <td align="right"><code>401 400  98.00</code></td>
+    <td align="right"><code>0   0.00</code></td>
+  </tr>
+  <tr>
+    <td align="left"><code>FLASH</code></td>
+    <td align="left"><code>70080400-73FFFFFF</code></td>
+    <td align="right"><code>66 583 552</code></td>
+    <td align="right"><code>2 554   0.00</code></td>
+    <td align="right"><code>66 580 998 100.00</code></td>
+    <td align="right"><code>0   0.00</code></td>
+  </tr>
+</table>
+<h2 id="LINK SUMMARY_Diagnostic summary">Diagnostic summary</h2>
+
+<pre>
+Link complete: 0 errors.
+</pre>
+</body></html>
Index: trunk/firmware/App/SES/SEGGER_THUMB_Startup.s
===================================================================
--- trunk/firmware/App/SES/SEGGER_THUMB_Startup.s	(revision 22)
+++ trunk/firmware/App/SES/SEGGER_THUMB_Startup.s	(revision 22)
@@ -0,0 +1,288 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File      : SEGGER_THUMB_Startup.s
+Purpose   : Generic runtime init startup code for ARM CPUs running 
+            in THUMB mode.
+            Designed to work with the SEGGER linker to produce 
+            smallest possible executables.
+            
+            This file does not normally require any customization.
+
+Additional information:
+  Preprocessor Definitions
+    FULL_LIBRARY
+      If defined then 
+        - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs().
+        - the exit symbol is defined and executes on return from main.
+        - the exit symbol calls destructors, atexit functions and then
+          calls SEGGER_SEMIHOST_Exit().
+    
+      If not defined then
+        - argc and argv are not valid (main is assumed to not take parameters)
+        - the exit symbol is defined, executes on return from main and
+          halts in a loop.
+*/
+
+        .syntax unified  
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+#ifndef   APP_ENTRY_POINT
+  #define APP_ENTRY_POINT main
+#endif
+
+#ifndef   ARGSSPACE
+  #define ARGSSPACE 128
+#endif
+
+/*********************************************************************
+*
+*       Macros
+*
+**********************************************************************
+*/
+//
+// Declare a label as function symbol (without switching sections)
+//
+.macro MARK_FUNC Name
+        .global \Name
+        .thumb_func
+        .code 16
+\Name:
+.endm
+//
+// Declare a regular function.
+// Functions from the startup are placed in the init section.
+//
+.macro START_FUNC Name
+        .section .init.\Name, "ax"
+        .global \Name
+        .balign 2
+        .thumb_func
+        .code 16
+\Name:
+.endm
+
+//
+// Declare a weak function
+//
+.macro WEAK_FUNC Name
+        .section .init.\Name, "ax", %progbits
+        .weak \Name
+        .balign 2
+        .thumb_func
+        .code 16
+\Name:
+.endm
+
+//
+// Mark the end of a function and calculate its size
+//
+.macro END_FUNC name
+        .size \name,.-\name
+.endm
+
+/*********************************************************************
+*
+*       Externals
+*
+**********************************************************************
+*/
+        .extern APP_ENTRY_POINT     // typically main
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       _start
+*
+*  Function description
+*    Entry point for the startup code. 
+*    Usually called by the reset handler.
+*    Performs all initialisation, based on the entries in the 
+*    linker-generated init table, then calls main().
+*    It is device independent, so there should not be any need for an 
+*    end-user to modify it.
+*
+*  Additional information
+*    At this point, the stack pointer should already have been 
+*    initialized 
+*      - by hardware (such as on Cortex-M),
+*      - by the device-specific reset handler,
+*      - or by the debugger (such as for RAM Code).
+*/
+#undef L
+#define L(label) .L_start_##label
+
+START_FUNC _start
+        //
+        // Call linker init functions which in turn performs the following:
+        // * Perform segment init
+        // * Perform heap init (if used)
+        // * Call constructors of global Objects (if any exist)
+        //
+        ldr     R4, =__SEGGER_init_table__      // Set table pointer to start of initialization table
+L(RunInit): 
+        ldr     R0, [R4]                        // Get next initialization function from table
+        adds    R4, R4, #4                      // Increment table pointer to point to function arguments
+        blx     R0                              // Call initialization function
+        b       L(RunInit)
+        //
+MARK_FUNC __SEGGER_init_done
+MARK_FUNC __startup_complete
+        //
+        // Time to call main(), the application entry point.
+        //
+#ifndef FULL_LIBRARY
+        //
+        // In a real embedded application ("Free-standing environment"), 
+        // main() does not get any arguments,
+        // which means it is not necessary to init R0 and R1.
+        //
+        bl      APP_ENTRY_POINT                 // Call to application entry point (usually main())
+
+END_FUNC _start
+        //
+        // end of _start
+        // Fall-through to exit if main ever returns.
+        //
+MARK_FUNC exit
+        //
+        // In a free-standing environment, if returned from application:
+        // Loop forever.
+        //
+        b       .
+        .size exit,.-exit
+#else
+        //
+        // In a hosted environment, 
+        // we need to load R0 and R1 with argc and argv, in order to handle 
+        // the command line arguments.
+        // This is required for some programs running under control of a 
+        // debugger, such as automated tests.
+        //
+        movs    R0, #ARGSSPACE
+        ldr     R1, =__SEGGER_init_arg_data
+        bl      SEGGER_SEMIHOST_GetArgs
+        ldr     R1, =__SEGGER_init_arg_data
+        bl      APP_ENTRY_POINT                 // Call to application entry point (usually main())
+        bl      exit                            // Call exit function
+        b       .                               // If we unexpectedly return from exit, hang.
+END_FUNC _start
+#endif
+        // 
+#ifdef FULL_LIBRARY
+/*********************************************************************
+*
+*       exit
+*
+*  Function description
+*    Exit of the system.
+*    Called on return from application entry point or explicit call 
+*    to exit.
+*
+*  Additional information
+*    In a hosted environment exit gracefully, by
+*    saving the return value,
+*    calling destructurs of global objects, 
+*    calling registered atexit functions, 
+*    and notifying the host/debugger.
+*/
+#undef L
+#define L(label) .L_exit_##label
+
+WEAK_FUNC exit
+        mov     R5, R0                  // Save the exit parameter/return result
+        //
+        // Call destructors
+        //
+        ldr     R0, =__dtors_start__    // Pointer to destructor list
+        ldr     R1, =__dtors_end__
+L(Loop):
+        cmp     R0, R1
+        beq     L(End)                  // Reached end of destructor list? => Done
+        ldr     R2, [R0]                // Load current destructor address into R2
+        adds    R0, R0, #4              // Increment pointer
+        push    {R0-R1}                 // Save R0 and R1
+        blx     R2                      // Call destructor
+        pop     {R0-R1}                 // Restore R0 and R1
+        b       L(Loop)
+L(End):
+        //
+        // Call atexit functions
+        //
+        bl      __SEGGER_RTL_execute_at_exit_fns
+        //
+        // Call debug_exit with return result/exit parameter
+        //
+        mov     R0, R5
+        //
+        // Entry points for _exit and _Exit, which terminate immediately.
+        // Note: Destructors and registered atexit functions are not called. File descriptors are not closed.
+        //
+MARK_FUNC _exit
+MARK_FUNC _Exit
+        bl      SEGGER_SEMIHOST_Exit
+        //
+        // If execution is not terminated, loop forever
+        //
+L(ExitLoop):
+        b       L(ExitLoop) // Loop forever.
+END_FUNC exit
+#endif
+
+#ifdef FULL_LIBRARY
+        .bss
+        .balign 4
+__SEGGER_init_arg_data:
+        .space ARGSSPACE
+        .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data
+        .type __SEGGER_init_arg_data, %object
+#endif
+
+/*************************** End of file ****************************/
Index: trunk/firmware/App/SES/STM32N657X0HxQ_MemoryMap.xml
===================================================================
--- trunk/firmware/App/SES/STM32N657X0HxQ_MemoryMap.xml	(revision 22)
+++ trunk/firmware/App/SES/STM32N657X0HxQ_MemoryMap.xml	(revision 22)
@@ -0,0 +1,18 @@
+<!DOCTYPE Board_Memory_Definition_File>
+<root name="STM32N657X0HxQ">
+  <MemorySegment name="FLASH_RAM" start="0x70080400" size="0x03F7FC00" access="Read/Write" />
+  <MemorySegment name="ITCM_RAM"  start="0x10000000" size="0x00010000" access="Read/Write" />
+  <MemorySegment name="DTCM_RAM"  start="0x30000000" size="0x00020000" access="Read/Write" />
+  <MemorySegment name="FLEX_RAM"  start="0x34000000" size="0x00064000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM1"  start="0x34064000" size="0x0009C000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM2"  start="0x34100000" size="0x00070000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM3"  start="0x34200000" size="0x00070000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM4"  start="0x34270000" size="0x00070000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM5"  start="0x342E0000" size="0x00070000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM6"  start="0x34350000" size="0x00070000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM7"  start="0x343C0000" size="0x00040000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM8"  start="0x34400000" size="0x00020000" access="Read/Write" />
+  <MemorySegment name="AHB_RAM1"  start="0x38000000" size="0x00004000" access="Read/Write" />
+  <MemorySegment name="AHB_RAM2"  start="0x38004000" size="0x00004000" access="Read/Write" />
+  <MemorySegment name="BKP_RAM"   start="0x3C000000" size="0x00002000" access="Read/Write" />
+</root>
Index: trunk/firmware/App/SES/STM32N657_Registers.xml
===================================================================
--- trunk/firmware/App/SES/STM32N657_Registers.xml	(revision 22)
+++ trunk/firmware/App/SES/STM32N657_Registers.xml	(revision 22)
@@ -0,0 +1,247787 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="STM32N657" description="STM32N657">
+  <RegisterGroup name="ADC1" description="Analog-to-digital converters" start="0x40022000">
+    <Register name="ADC_ISR" description="ADC interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register" start="+0x008" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in Deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in Deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single-ended input calibration mode." start="0x0" />
+        <Enum name="B_0x1" description="Differential input calibration mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Calibration mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR1" description="ADC configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data management configuration" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One-shot mode selected" start="0x1" />
+        <Enum name="B_0x2" description="MDF mode detected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="12-bit" start="0x0" />
+        <Enum name="B_0x1" description="10-bit" start="0x1" />
+        <Enum name="B_0x2" description="8-bit" start="0x2" />
+        <Enum name="B_0x3" description="6-bit" start="0x3" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group" start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected." start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / Continuous conversion mode for regular conversions" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection" start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel 0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel 1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x13" description="ADC analog input channel 19 monitored by AWD1" start="0x13" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected queue disable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular oversampling enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected oversampling enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling shift" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit shift" start="0xA" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered regular oversampling" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular oversampling mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="BULB" description="Bulb sampling mode" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bulb sampling mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion." start="0x1" />
+      </BitField>
+      <BitField name="SWTRIG" description="Software trigger bit for sampling time control trigger mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Software trigger starts the conversion for sampling time control trigger mode" start="0x0" />
+        <Enum name="B_0x1" description="Software trigger starts the sampling for sampling time control trigger mode" start="0x1" />
+      </BitField>
+      <BitField name="SMPTRIG" description="Sampling time control trigger mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sampling time control trigger mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sampling time control trigger mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio" start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit left shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit left shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit left shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit left shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit left shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit left shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit left shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit left shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit left shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit left shift" start="0xA" />
+        <Enum name="B_0xB" description="11-bit left shift" start="0xB" />
+        <Enum name="B_0xC" description="12-bit left shift" start="0xC" />
+        <Enum name="B_0xD" description="13-bit left shift" start="0xD" />
+        <Enum name="B_0xE" description="14-bit left shift" start="0xE" />
+        <Enum name="B_0xF" description="15-bit left shift" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL" description="Channel i (Vless thansub&gt;INPless than/sub&gt;[i]) preselection" start="0" size="20" access="Read/Write">
+        <Enum name="B_0x0" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is not preselected for conversion, the result of the ADC conversion for this channel is wrong" start="0x0" />
+        <Enum name="B_0x1" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is preselected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular data converted" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group" start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_jext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_jext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_jext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_jext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_jext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_jext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_jext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_jext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_jext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence" start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence" start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence" start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR1" description="ADC offset 1 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR2" description="ADC offset 2 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR3" description="ADC offset 3 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR4" description="ADC offset 4 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC offset 1 register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR2" description="ADC offset 2 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR3" description="ADC offset 3 register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR4" description="ADC offset 4 register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_GCOMP" description="ADC gain compensation register" start="+0x070" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCOMPCOEFF" description="Gain compensation coefficient" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x800" description="gain factor of 0.5" start="0x800" />
+        <Enum name="B_0x1000" description="gain factor of 1" start="0x1000" />
+        <Enum name="B_0x2000" description="gain factor of 2" start="0x2000" />
+        <Enum name="B_0x3000" description="gain factor of 3" start="0x3000" />
+      </BitField>
+      <BitField name="GCOMP" description="Gain compensation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular ADC operation mode" start="0x0" />
+        <Enum name="B_0x1" description="Gain compensation enabled and applied on all channels." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration Register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration Register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1LTR" description="ADC analog watchdog 1 lower threshold register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 1 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1HTR" description="ADC analog watchdog 1 higher threshold register" start="+0x0AC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 1 higher threshold" start="0" size="23" access="Read/Write" />
+      <BitField name="AWDFILT" description="Analog watchdog filtering parameter" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No filtering, one detection generates an AWDx flag or an interrupt" start="0x0" />
+        <Enum name="B_0x1" description="two consecutive detections generate an AWDx flag or an interrupt" start="0x1" />
+        <Enum name="B_0x7" description="Eight consecutive detections generate an AWDx flag or an interrupt" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_AWD2LTR" description="ADC analog watchdog 2 lower threshold register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 2 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD2HTR" description="ADC analog watchdog 2 higher threshold register" start="+0x0B4" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 2 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3LTR" description="ADC analog watchdog 3 lower threshold register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 3 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3HTR" description="ADC analog watchdog 3 higher threshold register" start="+0x0BC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 3 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC Differential mode selection register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration factors In Single-ended mode" start="0" size="9" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration factors in Differential mode" start="16" size="9" access="Read/Write" />
+      <BitField name="CALADDOS" description="Calibration additional offset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration additional positive offset disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration additional positive offset enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OR" description="ADC option register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SELREF" description="Internal reference voltage selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal reference voltage buffer disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal reference voltage buffer enabled" start="0x1" />
+      </BitField>
+      <BitField name="SELBG" description="Bandgap selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal bandgap disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal bandgap enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDCOREEN" description="VDDCORE enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC1_S" description="Analog-to-digital converters" start="0x50022000">
+    <Register name="ADC_ISR" description="ADC interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register" start="+0x008" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in Deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in Deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single-ended input calibration mode." start="0x0" />
+        <Enum name="B_0x1" description="Differential input calibration mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Calibration mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR1" description="ADC configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data management configuration" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One-shot mode selected" start="0x1" />
+        <Enum name="B_0x2" description="MDF mode detected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="12-bit" start="0x0" />
+        <Enum name="B_0x1" description="10-bit" start="0x1" />
+        <Enum name="B_0x2" description="8-bit" start="0x2" />
+        <Enum name="B_0x3" description="6-bit" start="0x3" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group" start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected." start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / Continuous conversion mode for regular conversions" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection" start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel 0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel 1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x13" description="ADC analog input channel 19 monitored by AWD1" start="0x13" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected queue disable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular oversampling enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected oversampling enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling shift" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit shift" start="0xA" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered regular oversampling" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular oversampling mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="BULB" description="Bulb sampling mode" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bulb sampling mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion." start="0x1" />
+      </BitField>
+      <BitField name="SWTRIG" description="Software trigger bit for sampling time control trigger mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Software trigger starts the conversion for sampling time control trigger mode" start="0x0" />
+        <Enum name="B_0x1" description="Software trigger starts the sampling for sampling time control trigger mode" start="0x1" />
+      </BitField>
+      <BitField name="SMPTRIG" description="Sampling time control trigger mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sampling time control trigger mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sampling time control trigger mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio" start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit left shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit left shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit left shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit left shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit left shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit left shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit left shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit left shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit left shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit left shift" start="0xA" />
+        <Enum name="B_0xB" description="11-bit left shift" start="0xB" />
+        <Enum name="B_0xC" description="12-bit left shift" start="0xC" />
+        <Enum name="B_0xD" description="13-bit left shift" start="0xD" />
+        <Enum name="B_0xE" description="14-bit left shift" start="0xE" />
+        <Enum name="B_0xF" description="15-bit left shift" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL" description="Channel i (Vless thansub&gt;INPless than/sub&gt;[i]) preselection" start="0" size="20" access="Read/Write">
+        <Enum name="B_0x0" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is not preselected for conversion, the result of the ADC conversion for this channel is wrong" start="0x0" />
+        <Enum name="B_0x1" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is preselected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular data converted" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group" start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_jext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_jext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_jext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_jext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_jext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_jext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_jext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_jext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_jext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence" start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence" start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence" start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR1" description="ADC offset 1 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR2" description="ADC offset 2 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR3" description="ADC offset 3 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR4" description="ADC offset 4 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC offset 1 register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR2" description="ADC offset 2 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR3" description="ADC offset 3 register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR4" description="ADC offset 4 register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_GCOMP" description="ADC gain compensation register" start="+0x070" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCOMPCOEFF" description="Gain compensation coefficient" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x800" description="gain factor of 0.5" start="0x800" />
+        <Enum name="B_0x1000" description="gain factor of 1" start="0x1000" />
+        <Enum name="B_0x2000" description="gain factor of 2" start="0x2000" />
+        <Enum name="B_0x3000" description="gain factor of 3" start="0x3000" />
+      </BitField>
+      <BitField name="GCOMP" description="Gain compensation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular ADC operation mode" start="0x0" />
+        <Enum name="B_0x1" description="Gain compensation enabled and applied on all channels." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration Register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration Register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1LTR" description="ADC analog watchdog 1 lower threshold register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 1 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1HTR" description="ADC analog watchdog 1 higher threshold register" start="+0x0AC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 1 higher threshold" start="0" size="23" access="Read/Write" />
+      <BitField name="AWDFILT" description="Analog watchdog filtering parameter" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No filtering, one detection generates an AWDx flag or an interrupt" start="0x0" />
+        <Enum name="B_0x1" description="two consecutive detections generate an AWDx flag or an interrupt" start="0x1" />
+        <Enum name="B_0x7" description="Eight consecutive detections generate an AWDx flag or an interrupt" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_AWD2LTR" description="ADC analog watchdog 2 lower threshold register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 2 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD2HTR" description="ADC analog watchdog 2 higher threshold register" start="+0x0B4" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 2 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3LTR" description="ADC analog watchdog 3 lower threshold register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 3 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3HTR" description="ADC analog watchdog 3 higher threshold register" start="+0x0BC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 3 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC Differential mode selection register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration factors In Single-ended mode" start="0" size="9" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration factors in Differential mode" start="16" size="9" access="Read/Write" />
+      <BitField name="CALADDOS" description="Calibration additional offset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration additional positive offset disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration additional positive offset enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OR" description="ADC option register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SELREF" description="Internal reference voltage selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal reference voltage buffer disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal reference voltage buffer enabled" start="0x1" />
+      </BitField>
+      <BitField name="SELBG" description="Bandgap selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal bandgap disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal bandgap enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDCOREEN" description="VDDCORE enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC2" description="Analog-to-digital converters" start="0x40022100">
+    <Register name="ADC_ISR" description="ADC interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register" start="+0x008" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in Deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in Deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single-ended input calibration mode." start="0x0" />
+        <Enum name="B_0x1" description="Differential input calibration mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Calibration mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR1" description="ADC configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data management configuration" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One-shot mode selected" start="0x1" />
+        <Enum name="B_0x2" description="MDF mode detected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="12-bit" start="0x0" />
+        <Enum name="B_0x1" description="10-bit" start="0x1" />
+        <Enum name="B_0x2" description="8-bit" start="0x2" />
+        <Enum name="B_0x3" description="6-bit" start="0x3" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group" start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected." start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / Continuous conversion mode for regular conversions" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection" start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel 0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel 1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x13" description="ADC analog input channel 19 monitored by AWD1" start="0x13" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected queue disable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular oversampling enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected oversampling enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling shift" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit shift" start="0xA" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered regular oversampling" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular oversampling mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="BULB" description="Bulb sampling mode" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bulb sampling mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion." start="0x1" />
+      </BitField>
+      <BitField name="SWTRIG" description="Software trigger bit for sampling time control trigger mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Software trigger starts the conversion for sampling time control trigger mode" start="0x0" />
+        <Enum name="B_0x1" description="Software trigger starts the sampling for sampling time control trigger mode" start="0x1" />
+      </BitField>
+      <BitField name="SMPTRIG" description="Sampling time control trigger mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sampling time control trigger mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sampling time control trigger mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio" start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit left shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit left shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit left shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit left shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit left shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit left shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit left shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit left shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit left shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit left shift" start="0xA" />
+        <Enum name="B_0xB" description="11-bit left shift" start="0xB" />
+        <Enum name="B_0xC" description="12-bit left shift" start="0xC" />
+        <Enum name="B_0xD" description="13-bit left shift" start="0xD" />
+        <Enum name="B_0xE" description="14-bit left shift" start="0xE" />
+        <Enum name="B_0xF" description="15-bit left shift" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL" description="Channel i (Vless thansub&gt;INPless than/sub&gt;[i]) preselection" start="0" size="20" access="Read/Write">
+        <Enum name="B_0x0" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is not preselected for conversion, the result of the ADC conversion for this channel is wrong" start="0x0" />
+        <Enum name="B_0x1" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is preselected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular data converted" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group" start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_jext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_jext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_jext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_jext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_jext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_jext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_jext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_jext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_jext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence" start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence" start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence" start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR1" description="ADC offset 1 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR2" description="ADC offset 2 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR3" description="ADC offset 3 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR4" description="ADC offset 4 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC offset 1 register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR2" description="ADC offset 2 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR3" description="ADC offset 3 register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR4" description="ADC offset 4 register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_GCOMP" description="ADC gain compensation register" start="+0x070" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCOMPCOEFF" description="Gain compensation coefficient" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x800" description="gain factor of 0.5" start="0x800" />
+        <Enum name="B_0x1000" description="gain factor of 1" start="0x1000" />
+        <Enum name="B_0x2000" description="gain factor of 2" start="0x2000" />
+        <Enum name="B_0x3000" description="gain factor of 3" start="0x3000" />
+      </BitField>
+      <BitField name="GCOMP" description="Gain compensation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular ADC operation mode" start="0x0" />
+        <Enum name="B_0x1" description="Gain compensation enabled and applied on all channels." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration Register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration Register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1LTR" description="ADC analog watchdog 1 lower threshold register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 1 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1HTR" description="ADC analog watchdog 1 higher threshold register" start="+0x0AC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 1 higher threshold" start="0" size="23" access="Read/Write" />
+      <BitField name="AWDFILT" description="Analog watchdog filtering parameter" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No filtering, one detection generates an AWDx flag or an interrupt" start="0x0" />
+        <Enum name="B_0x1" description="two consecutive detections generate an AWDx flag or an interrupt" start="0x1" />
+        <Enum name="B_0x7" description="Eight consecutive detections generate an AWDx flag or an interrupt" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_AWD2LTR" description="ADC analog watchdog 2 lower threshold register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 2 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD2HTR" description="ADC analog watchdog 2 higher threshold register" start="+0x0B4" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 2 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3LTR" description="ADC analog watchdog 3 lower threshold register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 3 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3HTR" description="ADC analog watchdog 3 higher threshold register" start="+0x0BC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 3 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC Differential mode selection register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration factors In Single-ended mode" start="0" size="9" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration factors in Differential mode" start="16" size="9" access="Read/Write" />
+      <BitField name="CALADDOS" description="Calibration additional offset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration additional positive offset disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration additional positive offset enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OR" description="ADC option register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SELREF" description="Internal reference voltage selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal reference voltage buffer disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal reference voltage buffer enabled" start="0x1" />
+      </BitField>
+      <BitField name="SELBG" description="Bandgap selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal bandgap disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal bandgap enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDCOREEN" description="VDDCORE enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC2_S" description="Analog-to-digital converters" start="0x50022100">
+    <Register name="ADC_ISR" description="ADC interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register" start="+0x008" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in Deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in Deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single-ended input calibration mode." start="0x0" />
+        <Enum name="B_0x1" description="Differential input calibration mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Calibration mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR1" description="ADC configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data management configuration" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One-shot mode selected" start="0x1" />
+        <Enum name="B_0x2" description="MDF mode detected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="12-bit" start="0x0" />
+        <Enum name="B_0x1" description="10-bit" start="0x1" />
+        <Enum name="B_0x2" description="8-bit" start="0x2" />
+        <Enum name="B_0x3" description="6-bit" start="0x3" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group" start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected." start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / Continuous conversion mode for regular conversions" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection" start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel 0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel 1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x13" description="ADC analog input channel 19 monitored by AWD1" start="0x13" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected queue disable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular oversampling enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected oversampling enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling shift" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit shift" start="0xA" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered regular oversampling" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular oversampling mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="BULB" description="Bulb sampling mode" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bulb sampling mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion." start="0x1" />
+      </BitField>
+      <BitField name="SWTRIG" description="Software trigger bit for sampling time control trigger mode" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Software trigger starts the conversion for sampling time control trigger mode" start="0x0" />
+        <Enum name="B_0x1" description="Software trigger starts the sampling for sampling time control trigger mode" start="0x1" />
+      </BitField>
+      <BitField name="SMPTRIG" description="Sampling time control trigger mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sampling time control trigger mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sampling time control trigger mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio" start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="1-bit left shift" start="0x1" />
+        <Enum name="B_0x2" description="2-bit left shift" start="0x2" />
+        <Enum name="B_0x3" description="3-bit left shift" start="0x3" />
+        <Enum name="B_0x4" description="4-bit left shift" start="0x4" />
+        <Enum name="B_0x5" description="5-bit left shift" start="0x5" />
+        <Enum name="B_0x6" description="6-bit left shift" start="0x6" />
+        <Enum name="B_0x7" description="7-bit left shift" start="0x7" />
+        <Enum name="B_0x8" description="8-bit left shift" start="0x8" />
+        <Enum name="B_0x9" description="9-bit left shift" start="0x9" />
+        <Enum name="B_0xA" description="10-bit left shift" start="0xA" />
+        <Enum name="B_0xB" description="11-bit left shift" start="0xB" />
+        <Enum name="B_0xC" description="12-bit left shift" start="0xC" />
+        <Enum name="B_0xD" description="13-bit left shift" start="0xD" />
+        <Enum name="B_0xE" description="14-bit left shift" start="0xE" />
+        <Enum name="B_0xF" description="15-bit left shift" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection" start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection" start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection" start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="3.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="7.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="12.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="24.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="47.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="1501.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL" description="Channel i (Vless thansub&gt;INPless than/sub&gt;[i]) preselection" start="0" size="20" access="Read/Write">
+        <Enum name="B_0x0" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is not preselected for conversion, the result of the ADC conversion for this channel is wrong" start="0x0" />
+        <Enum name="B_0x1" description="Input channel i (Vless thansub&gt;INPless than/sub&gt;[i]) is preselected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence" start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence" start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence" start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence" start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence" start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular data converted" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group" start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_jext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_jext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_jext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_jext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_jext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_jext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_jext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_jext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_jext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence" start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence" start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence" start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR1" description="ADC offset 1 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR2" description="ADC offset 2 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR3" description="ADC offset 3 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFCFGR4" description="ADC offset 4 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POSOFF" description="Positive offset enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset" start="0x0" />
+        <Enum name="B_0x1" description="Positive offset" start="0x1" />
+      </BitField>
+      <BitField name="USAT" description="Unsigned saturation enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="SSAT" description="Signed saturation enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining the data integrity and extending converted data size (13-bit signed format)" start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain the converted data size" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y" start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC offset 1 register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR2" description="ADC offset 2 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR3" description="ADC offset 3 register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR4" description="ADC offset 4 register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into OFFSETy_CH[4:0] bits" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="ADC_GCOMP" description="ADC gain compensation register" start="+0x070" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCOMPCOEFF" description="Gain compensation coefficient" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x800" description="gain factor of 0.5" start="0x800" />
+        <Enum name="B_0x1000" description="gain factor of 1" start="0x1000" />
+        <Enum name="B_0x2000" description="gain factor of 2" start="0x2000" />
+        <Enum name="B_0x3000" description="gain factor of 3" start="0x3000" />
+      </BitField>
+      <BitField name="GCOMP" description="Gain compensation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular ADC operation mode" start="0x0" />
+        <Enum name="B_0x1" description="Gain compensation enabled and applied on all channels." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration Register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration Register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1LTR" description="ADC analog watchdog 1 lower threshold register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 1 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD1HTR" description="ADC analog watchdog 1 higher threshold register" start="+0x0AC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 1 higher threshold" start="0" size="23" access="Read/Write" />
+      <BitField name="AWDFILT" description="Analog watchdog filtering parameter" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No filtering, one detection generates an AWDx flag or an interrupt" start="0x0" />
+        <Enum name="B_0x1" description="two consecutive detections generate an AWDx flag or an interrupt" start="0x1" />
+        <Enum name="B_0x7" description="Eight consecutive detections generate an AWDx flag or an interrupt" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_AWD2LTR" description="ADC analog watchdog 2 lower threshold register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 2 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD2HTR" description="ADC analog watchdog 2 higher threshold register" start="+0x0B4" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 2 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3LTR" description="ADC analog watchdog 3 lower threshold register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR" description="Analog watchdog 3 lower threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3HTR" description="ADC analog watchdog 3 higher threshold register" start="+0x0BC" size="4" reset_value="0x003FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR" description="Analog watchdog 3 higher threshold" start="0" size="23" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC Differential mode selection register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration factors In Single-ended mode" start="0" size="9" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration factors in Differential mode" start="16" size="9" access="Read/Write" />
+      <BitField name="CALADDOS" description="Calibration additional offset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration additional positive offset disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration additional positive offset enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OR" description="ADC option register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SELREF" description="Internal reference voltage selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal reference voltage buffer disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal reference voltage buffer enabled" start="0x1" />
+      </BitField>
+      <BitField name="SELBG" description="Bandgap selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC internal bandgap disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC internal bandgap enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDCOREEN" description="VDDCORE enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC12" description="ADC common registers" start="0x40022300">
+    <Register name="ADC12_CSR" description="ADC12 common status register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY_MST" description="Master ADC ready" start="0" size="1" access="ReadOnly" />
+      <BitField name="EOSMP_MST" description="End of Sampling phase flag of the master ADC" start="1" size="1" access="ReadOnly" />
+      <BitField name="EOC_MST" description="End of regular conversion of the master ADC" start="2" size="1" access="ReadOnly" />
+      <BitField name="EOS_MST" description="End of regular sequence flag of the master ADC" start="3" size="1" access="ReadOnly" />
+      <BitField name="OVR_MST" description="Overrun flag of the master ADC" start="4" size="1" access="ReadOnly" />
+      <BitField name="JEOC_MST" description="End of injected conversion flag of the master ADC" start="5" size="1" access="ReadOnly" />
+      <BitField name="JEOS_MST" description="End of injected sequence flag of the master ADC" start="6" size="1" access="ReadOnly" />
+      <BitField name="AWD1_MST" description="Analog watchdog 1 flag of the master ADC" start="7" size="1" access="ReadOnly" />
+      <BitField name="AWD2_MST" description="Analog watchdog 2 flag of the master ADC" start="8" size="1" access="ReadOnly" />
+      <BitField name="AWD3_MST" description="Analog watchdog 3 flag of the master ADC" start="9" size="1" access="ReadOnly" />
+      <BitField name="ADRDY_SLV" description="Slave ADC ready" start="16" size="1" access="ReadOnly" />
+      <BitField name="EOSMP_SLV" description="End of Sampling phase flag of the slave ADC" start="17" size="1" access="ReadOnly" />
+      <BitField name="EOC_SLV" description="End of regular conversion of the slave ADC" start="18" size="1" access="ReadOnly" />
+      <BitField name="EOS_SLV" description="End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register." start="19" size="1" access="ReadOnly" />
+      <BitField name="OVR_SLV" description="Overrun flag of the slave ADC " start="20" size="1" access="ReadOnly" />
+      <BitField name="JEOC_SLV" description="End of injected conversion flag of the slave ADC " start="21" size="1" access="ReadOnly" />
+      <BitField name="JEOS_SLV" description="End of injected sequence flag of the slave ADC " start="22" size="1" access="ReadOnly" />
+      <BitField name="AWD1_SLV" description="Analog watchdog 1 flag of the slave ADC " start="23" size="1" access="ReadOnly" />
+      <BitField name="AWD2_SLV" description="Analog watchdog 2 flag of the slave ADC " start="24" size="1" access="ReadOnly" />
+      <BitField name="AWD3_SLV" description="Analog watchdog 3 flag of the slave ADC" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ADC12_CCR" description="ADC12 common control register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUAL" description="Dual ADC mode selection " start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Independent mode" start="0x0" />
+        <Enum name="B_0x1" description="Combined regular simultaneous + Injected simultaneous mode" start="0x1" />
+        <Enum name="B_0x2" description="Combined regular simultaneous + Alternate trigger mode" start="0x2" />
+        <Enum name="B_0x3" description="Combined Interleaved mode + Injected simultaneous mode" start="0x3" />
+        <Enum name="B_0x5" description="Injected simultaneous mode only" start="0x5" />
+        <Enum name="B_0x6" description="Regular simultaneous mode only" start="0x6" />
+        <Enum name="B_0x7" description="Interleaved mode only" start="0x7" />
+        <Enum name="B_0x9" description="Alternate trigger mode only" start="0x9" />
+      </BitField>
+      <BitField name="DELAY" description="Delay between two sampling phases " start="8" size="4" access="Read/Write" />
+      <BitField name="DAMDF" description="Dual ADC mode data format " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not used)." start="0x0" />
+        <Enum name="B_0x2" description="Data formatting mode for any data width (ADCx_CDR data register is used when the data width is less than 16 bits, otherwise ADCx_CDR2 register is used)" start="0x2" />
+        <Enum name="B_0x3" description="Data formatting mode for data width lower that 8 bits (ADCx_CDR data register is used)" start="0x3" />
+      </BitField>
+      <BitField name="VREFEN" description="Vless thansub&gt;REFINTless than/sub&gt; enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;REFINTless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;REFINTless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBATEN" description="VBAT enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC12_CDR" description="ADC12 common regular data register for Dual mode" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_MST" description="Regular data of the master ADC." start="0" size="16" access="ReadOnly" />
+      <BitField name="RDATA_SLV" description="Regular data of the slave ADC" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC12_CDR2" description="ADC12 common regular data register for Dual mode" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_ALT" description="Regular data of the master/slave alternated ADCs." start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC12_S" description="ADC common registers" start="0x50022300">
+    <Register name="ADC12_CSR" description="ADC12 common status register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY_MST" description="Master ADC ready" start="0" size="1" access="ReadOnly" />
+      <BitField name="EOSMP_MST" description="End of Sampling phase flag of the master ADC" start="1" size="1" access="ReadOnly" />
+      <BitField name="EOC_MST" description="End of regular conversion of the master ADC" start="2" size="1" access="ReadOnly" />
+      <BitField name="EOS_MST" description="End of regular sequence flag of the master ADC" start="3" size="1" access="ReadOnly" />
+      <BitField name="OVR_MST" description="Overrun flag of the master ADC" start="4" size="1" access="ReadOnly" />
+      <BitField name="JEOC_MST" description="End of injected conversion flag of the master ADC" start="5" size="1" access="ReadOnly" />
+      <BitField name="JEOS_MST" description="End of injected sequence flag of the master ADC" start="6" size="1" access="ReadOnly" />
+      <BitField name="AWD1_MST" description="Analog watchdog 1 flag of the master ADC" start="7" size="1" access="ReadOnly" />
+      <BitField name="AWD2_MST" description="Analog watchdog 2 flag of the master ADC" start="8" size="1" access="ReadOnly" />
+      <BitField name="AWD3_MST" description="Analog watchdog 3 flag of the master ADC" start="9" size="1" access="ReadOnly" />
+      <BitField name="ADRDY_SLV" description="Slave ADC ready" start="16" size="1" access="ReadOnly" />
+      <BitField name="EOSMP_SLV" description="End of Sampling phase flag of the slave ADC" start="17" size="1" access="ReadOnly" />
+      <BitField name="EOC_SLV" description="End of regular conversion of the slave ADC" start="18" size="1" access="ReadOnly" />
+      <BitField name="EOS_SLV" description="End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register." start="19" size="1" access="ReadOnly" />
+      <BitField name="OVR_SLV" description="Overrun flag of the slave ADC " start="20" size="1" access="ReadOnly" />
+      <BitField name="JEOC_SLV" description="End of injected conversion flag of the slave ADC " start="21" size="1" access="ReadOnly" />
+      <BitField name="JEOS_SLV" description="End of injected sequence flag of the slave ADC " start="22" size="1" access="ReadOnly" />
+      <BitField name="AWD1_SLV" description="Analog watchdog 1 flag of the slave ADC " start="23" size="1" access="ReadOnly" />
+      <BitField name="AWD2_SLV" description="Analog watchdog 2 flag of the slave ADC " start="24" size="1" access="ReadOnly" />
+      <BitField name="AWD3_SLV" description="Analog watchdog 3 flag of the slave ADC" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ADC12_CCR" description="ADC12 common control register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUAL" description="Dual ADC mode selection " start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Independent mode" start="0x0" />
+        <Enum name="B_0x1" description="Combined regular simultaneous + Injected simultaneous mode" start="0x1" />
+        <Enum name="B_0x2" description="Combined regular simultaneous + Alternate trigger mode" start="0x2" />
+        <Enum name="B_0x3" description="Combined Interleaved mode + Injected simultaneous mode" start="0x3" />
+        <Enum name="B_0x5" description="Injected simultaneous mode only" start="0x5" />
+        <Enum name="B_0x6" description="Regular simultaneous mode only" start="0x6" />
+        <Enum name="B_0x7" description="Interleaved mode only" start="0x7" />
+        <Enum name="B_0x9" description="Alternate trigger mode only" start="0x9" />
+      </BitField>
+      <BitField name="DELAY" description="Delay between two sampling phases " start="8" size="4" access="Read/Write" />
+      <BitField name="DAMDF" description="Dual ADC mode data format " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not used)." start="0x0" />
+        <Enum name="B_0x2" description="Data formatting mode for any data width (ADCx_CDR data register is used when the data width is less than 16 bits, otherwise ADCx_CDR2 register is used)" start="0x2" />
+        <Enum name="B_0x3" description="Data formatting mode for data width lower that 8 bits (ADCx_CDR data register is used)" start="0x3" />
+      </BitField>
+      <BitField name="VREFEN" description="Vless thansub&gt;REFINTless than/sub&gt; enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;REFINTless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;REFINTless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBATEN" description="VBAT enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC12_CDR" description="ADC12 common regular data register for Dual mode" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_MST" description="Regular data of the master ADC." start="0" size="16" access="ReadOnly" />
+      <BitField name="RDATA_SLV" description="Regular data of the slave ADC" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC12_CDR2" description="ADC12 common regular data register for Dual mode" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_ALT" description="Regular data of the master/slave alternated ADCs." start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADF" description="Audio digital filter" start="0x42026000">
+    <Register name="ADF_GCR" description="ADF global control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRGO" description="Trigger output control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write 0 has no effect. Read 0 means that the trigger can be set again to 1." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 generates a positive pulse on the adf_trgo signal and triggers the acquisition on enabled filter having their ACQMOD[2:0] = 01x and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_CKGCR" description="ADF clock generator control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKGDEN" description="CKGEN dividers enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKGEN dividers disabled" start="0x0" />
+        <Enum name="B_0x1" description="CKGEN dividers enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCK0EN" description="ADF_CCK0 clock enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the ADF_CCK0 pin" start="0x1" />
+      </BitField>
+      <BitField name="CCK1EN" description="ADF_CCK1 clock enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the ADF_CCK1 pin." start="0x1" />
+      </BitField>
+      <BitField name="CKGMOD" description="Clock generator mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The kernel clock is provided to the dividers as soon as CKGDEN is set to 1." start="0x0" />
+        <Enum name="B_0x1" description="The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met." start="0x1" />
+      </BitField>
+      <BitField name="CCK0DIR" description="ADF_CCK0 direction" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK0 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK0 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="CCK1DIR" description="ADF_CCK1 direction" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK1 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK1 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="TRGSENS" description="CKGEN trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the activation of CKGEN dividers." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the activation of CKGEN dividers." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x2" description="adf_trg1 selected" start="0x2" />
+      </BitField>
+      <BitField name="CCKDIV" description="Divider to control the ADF_CCK clock" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK clock is adf_proc_ck." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK clock is adf_proc_ck / 2." start="0x1" />
+        <Enum name="B_0x2" description="The ADF_CCK clock is adf_proc_ck / 3." start="0x2" />
+        <Enum name="B_0xF" description="The ADF_CCK clock is adf_proc_ck / 16." start="0xF" />
+      </BitField>
+      <BitField name="PROCDIV" description="Divider to control the serial interface clock" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="adf_ker_ck provided to the SITF" start="0x0" />
+        <Enum name="B_0x1" description="adf_ker_ck / 2 provided to the SITF" start="0x1" />
+      </BitField>
+      <BitField name="CKGACTIVE" description="Clock generator active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The clock generator is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The clock generator is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SITF0CR" description="ADF serial interface control register 0" start="+0x080" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is ADF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is ADF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active, and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_BSMX0CR" description="ADF bitstream matrix control register 0" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLT0" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLT0" start="0x1" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0CR" description="ADF digital filter control register 0" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="DFLT0 enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="DFLT0 trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+      </BitField>
+      <BitField name="TRGSENS" description="DFLT0 trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="DFLT0 trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x2" description="adf_trgi selected" start="0x2" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="DFLT0 run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DFLT0 not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="DFLT0running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="DFLT0 active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DFLT0 not active (can be re-enabled again, via DFLTEN bit, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="DFLT0 active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0CICR" description="ADF digital filer configuration register 0" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC order" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="MCIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+        <Enum name="B_0x5" description="MCIC configured in single Sincless thansup&gt;5less than/sup&gt; filter" start="0x5" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="-6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="-2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0RSFR" description="ADF reshape filter configuration register 0" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x FPCM" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x FPCM" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x FPCM" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x FPCM" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DLY0CR" description="ADF delay control register 0" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ADF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under precessing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0IER" description="ADF DFLT0 interrupt enable register" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDDETIE" description="Sound activity detection interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sound-trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sound-trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDLVLIE" description="SAD sound-level value ready enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sound-level-ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sound-level-ready interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0ISR" description="ADF DFLT0 interrupt status register 0" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SDDETF" description="Sound activity detection flag" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no sound activity is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that sound activity is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SDLVLF" description="Sound level value ready flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that new sound level value is not ready. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that new sound level value is ready. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SADCR" description="ADF SAD control register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADEN" description="Sound activity detector enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAD disabled and SAD state reset" start="0x0" />
+        <Enum name="B_0x1" description="SAD enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATCAP" description="Data capture mode" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Samples from DFLT0 not transfered into the memory" start="0x0" />
+        <Enum name="B_0x1" description="Samples from DFLT0 transfered into the memory when SAD is in DETECT state" start="0x1" />
+      </BitField>
+      <BitField name="DETCFG" description="Sound trigger event configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="sddet_evt generated when SAD enters the MONITOR state" start="0x0" />
+        <Enum name="B_0x1" description="sddet_evt generated when SAD enters or exits the DETECT state" start="0x1" />
+      </BitField>
+      <BitField name="SADST" description="SAD state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="SAD in LEARN state" start="0x0" />
+        <Enum name="B_0x1" description="SAD in MONITOR state" start="0x1" />
+        <Enum name="B_0x3" description="SAD in DETECT state" start="0x3" />
+      </BitField>
+      <BitField name="HYSTEN" description="Hysteresis enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hysteresis function disabled. THRless thansub&gt;Hless than/sub&gt; is always used." start="0x0" />
+        <Enum name="B_0x1" description="Hysteresis function enabled. THRless thansub&gt;Hless than/sub&gt; is used for MONITOR to DETECT transition and THRless thansub&gt;Lless than/sub&gt; is used for DETECT to MONITOR transition." start="0x1" />
+      </BitField>
+      <BitField name="FRSIZE" description="Frame size" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 PCM samples used to compute the short-term signal level" start="0x0" />
+        <Enum name="B_0x1" description="16 PCM samples used to compute the short-term signal level" start="0x1" />
+        <Enum name="B_0x2" description="32 PCM samples used to compute the short-term signal level" start="0x2" />
+        <Enum name="B_0x3" description="64 PCM samples used to compute the short-term signal level" start="0x3" />
+        <Enum name="B_0x4" description="128 PCM samples used to compute the short-term signal level" start="0x4" />
+        <Enum name="B_0x5" description="256 PCM samples used to compute the short-term signal level" start="0x5" />
+      </BitField>
+      <BitField name="SADMOD" description="SAD working mode" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Threshold value computed according to the estimated ambient noise" start="0x0" />
+        <Enum name="B_0x1" description="Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="SADACTIVE" description="SAD Active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SAD not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SAD active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SADCFGR" description="ADF SAD configuration register" start="+0x0BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SNTHR" description="Signal to noise threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="THRless thansub&gt;H less than/sub&gt;is 3.5 dB higher than ANLVL" start="0x0" />
+        <Enum name="B_0x1" description="THRless thansub&gt;H less than/sub&gt;is 6.0 dB higher than ANLVL" start="0x1" />
+        <Enum name="B_0x2" description="THRless thansub&gt;H less than/sub&gt;is 9.5 dB higher than ANLVL" start="0x2" />
+        <Enum name="B_0x3" description="THRless thansub&gt;H less than/sub&gt;is 12 dB higher than ANLVL" start="0x3" />
+        <Enum name="B_0x4" description="THRless thansub&gt;H less than/sub&gt;is 15.6 dB higher than ANLVL" start="0x4" />
+        <Enum name="B_0x5" description="THRless thansub&gt;H less than/sub&gt;is 18 dB higher than ANLVL" start="0x5" />
+        <Enum name="B_0x6" description="THRless thansub&gt;H less than/sub&gt;is 21.6 dB higher than ANLVL" start="0x6" />
+        <Enum name="B_0x7" description="THRless thansub&gt;H less than/sub&gt;is 24.1 dB higher than ANLVL" start="0x7" />
+        <Enum name="B_0x8" description="THRless thansub&gt;H less than/sub&gt;is 27.6 dB higher than ANLVL" start="0x8" />
+        <Enum name="B_0x9" description="THRless thansub&gt;H less than/sub&gt;is 30.1dB higher than ANLVL" start="0x9" />
+      </BitField>
+      <BitField name="ANSLP" description="Ambient noise slope control " start="4" size="3" access="Read/Write" />
+      <BitField name="LFRNB" description="Number of learning frames" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2 frames used to compute the initial noise level" start="0x0" />
+        <Enum name="B_0x1" description="4 frames used to compute the initial noise level" start="0x1" />
+        <Enum name="B_0x2" description="8 frames used to compute the initial noise level" start="0x2" />
+        <Enum name="B_0x3" description="16 frames used to compute the initial noise level" start="0x3" />
+      </BitField>
+      <BitField name="HGOVR" description="Hangover time window" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SAD back to MONITOR state if sound is below threshold for 4 frames" start="0x0" />
+        <Enum name="B_0x1" description="SAD back to MONITOR state if sound is below threshold for 8 frames" start="0x1" />
+        <Enum name="B_0x2" description="SAD back to MONITOR state if sound is below threshold for 16 frames" start="0x2" />
+        <Enum name="B_0x3" description="SAD back to MONITOR state if sound is below threshold for 32 frames" start="0x3" />
+        <Enum name="B_0x4" description="SAD back to MONITOR state if sound is below threshold for 64 frames" start="0x4" />
+        <Enum name="B_0x5" description="SAD back to MONITOR state if sound is below threshold for 128 frames" start="0x5" />
+        <Enum name="B_0x6" description="SAD back to MONITOR state if sound is below threshold for 256 frames" start="0x6" />
+        <Enum name="B_0x7" description="SAD back to MONITOR state if sound is below threshold for 512 frames" start="0x7" />
+      </BitField>
+      <BitField name="ANMIN" description="Minimum noise level" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="ADF_SADSDLVR" description="ADF SAD sound level register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDLVL" description="Short term sound level" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="ADF_SADANLVR" description="ADF SAD ambient noise level register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANLVL" description="Ambient noise level estimation" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="ADF_DFLT0DR" description="ADF digital filter data register 0" start="+0x0F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by DFT0" start="8" size="24" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADF_S" description="Audio digital filter" start="0x52026000">
+    <Register name="ADF_GCR" description="ADF global control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRGO" description="Trigger output control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write 0 has no effect. Read 0 means that the trigger can be set again to 1." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 generates a positive pulse on the adf_trgo signal and triggers the acquisition on enabled filter having their ACQMOD[2:0] = 01x and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_CKGCR" description="ADF clock generator control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKGDEN" description="CKGEN dividers enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKGEN dividers disabled" start="0x0" />
+        <Enum name="B_0x1" description="CKGEN dividers enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCK0EN" description="ADF_CCK0 clock enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the ADF_CCK0 pin" start="0x1" />
+      </BitField>
+      <BitField name="CCK1EN" description="ADF_CCK1 clock enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the ADF_CCK1 pin." start="0x1" />
+      </BitField>
+      <BitField name="CKGMOD" description="Clock generator mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The kernel clock is provided to the dividers as soon as CKGDEN is set to 1." start="0x0" />
+        <Enum name="B_0x1" description="The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met." start="0x1" />
+      </BitField>
+      <BitField name="CCK0DIR" description="ADF_CCK0 direction" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK0 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK0 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="CCK1DIR" description="ADF_CCK1 direction" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK1 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK1 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="TRGSENS" description="CKGEN trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the activation of CKGEN dividers." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the activation of CKGEN dividers." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x2" description="adf_trg1 selected" start="0x2" />
+      </BitField>
+      <BitField name="CCKDIV" description="Divider to control the ADF_CCK clock" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="The ADF_CCK clock is adf_proc_ck." start="0x0" />
+        <Enum name="B_0x1" description="The ADF_CCK clock is adf_proc_ck / 2." start="0x1" />
+        <Enum name="B_0x2" description="The ADF_CCK clock is adf_proc_ck / 3." start="0x2" />
+        <Enum name="B_0xF" description="The ADF_CCK clock is adf_proc_ck / 16." start="0xF" />
+      </BitField>
+      <BitField name="PROCDIV" description="Divider to control the serial interface clock" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="adf_ker_ck provided to the SITF" start="0x0" />
+        <Enum name="B_0x1" description="adf_ker_ck / 2 provided to the SITF" start="0x1" />
+      </BitField>
+      <BitField name="CKGACTIVE" description="Clock generator active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The clock generator is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The clock generator is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SITF0CR" description="ADF serial interface control register 0" start="+0x080" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is ADF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is ADF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active, and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_BSMX0CR" description="ADF bitstream matrix control register 0" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLT0" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLT0" start="0x1" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0CR" description="ADF digital filter control register 0" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="DFLT0 enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="DFLT0 trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+      </BitField>
+      <BitField name="TRGSENS" description="DFLT0 trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="DFLT0 trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x2" description="adf_trgi selected" start="0x2" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="DFLT0 run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DFLT0 not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="DFLT0running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="DFLT0 active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DFLT0 not active (can be re-enabled again, via DFLTEN bit, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="DFLT0 active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0CICR" description="ADF digital filer configuration register 0" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC order" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="MCIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+        <Enum name="B_0x5" description="MCIC configured in single Sincless thansup&gt;5less than/sup&gt; filter" start="0x5" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="-6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="-2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0RSFR" description="ADF reshape filter configuration register 0" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x FPCM" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x FPCM" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x FPCM" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x FPCM" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DLY0CR" description="ADF delay control register 0" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ADF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under precessing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0IER" description="ADF DFLT0 interrupt enable register" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDDETIE" description="Sound activity detection interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sound-trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sound-trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDLVLIE" description="SAD sound-level value ready enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sound-level-ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Sound-level-ready interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_DFLT0ISR" description="ADF DFLT0 interrupt status register 0" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SDDETF" description="Sound activity detection flag" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no sound activity is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that sound activity is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SDLVLF" description="Sound level value ready flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that new sound level value is not ready. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that new sound level value is ready. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SADCR" description="ADF SAD control register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADEN" description="Sound activity detector enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAD disabled and SAD state reset" start="0x0" />
+        <Enum name="B_0x1" description="SAD enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATCAP" description="Data capture mode" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Samples from DFLT0 not transfered into the memory" start="0x0" />
+        <Enum name="B_0x1" description="Samples from DFLT0 transfered into the memory when SAD is in DETECT state" start="0x1" />
+      </BitField>
+      <BitField name="DETCFG" description="Sound trigger event configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="sddet_evt generated when SAD enters the MONITOR state" start="0x0" />
+        <Enum name="B_0x1" description="sddet_evt generated when SAD enters or exits the DETECT state" start="0x1" />
+      </BitField>
+      <BitField name="SADST" description="SAD state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="SAD in LEARN state" start="0x0" />
+        <Enum name="B_0x1" description="SAD in MONITOR state" start="0x1" />
+        <Enum name="B_0x3" description="SAD in DETECT state" start="0x3" />
+      </BitField>
+      <BitField name="HYSTEN" description="Hysteresis enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hysteresis function disabled. THRless thansub&gt;Hless than/sub&gt; is always used." start="0x0" />
+        <Enum name="B_0x1" description="Hysteresis function enabled. THRless thansub&gt;Hless than/sub&gt; is used for MONITOR to DETECT transition and THRless thansub&gt;Lless than/sub&gt; is used for DETECT to MONITOR transition." start="0x1" />
+      </BitField>
+      <BitField name="FRSIZE" description="Frame size" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 PCM samples used to compute the short-term signal level" start="0x0" />
+        <Enum name="B_0x1" description="16 PCM samples used to compute the short-term signal level" start="0x1" />
+        <Enum name="B_0x2" description="32 PCM samples used to compute the short-term signal level" start="0x2" />
+        <Enum name="B_0x3" description="64 PCM samples used to compute the short-term signal level" start="0x3" />
+        <Enum name="B_0x4" description="128 PCM samples used to compute the short-term signal level" start="0x4" />
+        <Enum name="B_0x5" description="256 PCM samples used to compute the short-term signal level" start="0x5" />
+      </BitField>
+      <BitField name="SADMOD" description="SAD working mode" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Threshold value computed according to the estimated ambient noise" start="0x0" />
+        <Enum name="B_0x1" description="Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="SADACTIVE" description="SAD Active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SAD not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SAD active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADF_SADCFGR" description="ADF SAD configuration register" start="+0x0BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SNTHR" description="Signal to noise threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="THRless thansub&gt;H less than/sub&gt;is 3.5 dB higher than ANLVL" start="0x0" />
+        <Enum name="B_0x1" description="THRless thansub&gt;H less than/sub&gt;is 6.0 dB higher than ANLVL" start="0x1" />
+        <Enum name="B_0x2" description="THRless thansub&gt;H less than/sub&gt;is 9.5 dB higher than ANLVL" start="0x2" />
+        <Enum name="B_0x3" description="THRless thansub&gt;H less than/sub&gt;is 12 dB higher than ANLVL" start="0x3" />
+        <Enum name="B_0x4" description="THRless thansub&gt;H less than/sub&gt;is 15.6 dB higher than ANLVL" start="0x4" />
+        <Enum name="B_0x5" description="THRless thansub&gt;H less than/sub&gt;is 18 dB higher than ANLVL" start="0x5" />
+        <Enum name="B_0x6" description="THRless thansub&gt;H less than/sub&gt;is 21.6 dB higher than ANLVL" start="0x6" />
+        <Enum name="B_0x7" description="THRless thansub&gt;H less than/sub&gt;is 24.1 dB higher than ANLVL" start="0x7" />
+        <Enum name="B_0x8" description="THRless thansub&gt;H less than/sub&gt;is 27.6 dB higher than ANLVL" start="0x8" />
+        <Enum name="B_0x9" description="THRless thansub&gt;H less than/sub&gt;is 30.1dB higher than ANLVL" start="0x9" />
+      </BitField>
+      <BitField name="ANSLP" description="Ambient noise slope control " start="4" size="3" access="Read/Write" />
+      <BitField name="LFRNB" description="Number of learning frames" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2 frames used to compute the initial noise level" start="0x0" />
+        <Enum name="B_0x1" description="4 frames used to compute the initial noise level" start="0x1" />
+        <Enum name="B_0x2" description="8 frames used to compute the initial noise level" start="0x2" />
+        <Enum name="B_0x3" description="16 frames used to compute the initial noise level" start="0x3" />
+      </BitField>
+      <BitField name="HGOVR" description="Hangover time window" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SAD back to MONITOR state if sound is below threshold for 4 frames" start="0x0" />
+        <Enum name="B_0x1" description="SAD back to MONITOR state if sound is below threshold for 8 frames" start="0x1" />
+        <Enum name="B_0x2" description="SAD back to MONITOR state if sound is below threshold for 16 frames" start="0x2" />
+        <Enum name="B_0x3" description="SAD back to MONITOR state if sound is below threshold for 32 frames" start="0x3" />
+        <Enum name="B_0x4" description="SAD back to MONITOR state if sound is below threshold for 64 frames" start="0x4" />
+        <Enum name="B_0x5" description="SAD back to MONITOR state if sound is below threshold for 128 frames" start="0x5" />
+        <Enum name="B_0x6" description="SAD back to MONITOR state if sound is below threshold for 256 frames" start="0x6" />
+        <Enum name="B_0x7" description="SAD back to MONITOR state if sound is below threshold for 512 frames" start="0x7" />
+      </BitField>
+      <BitField name="ANMIN" description="Minimum noise level" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="ADF_SADSDLVR" description="ADF SAD sound level register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDLVL" description="Short term sound level" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="ADF_SADANLVR" description="ADF SAD ambient noise level register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANLVL" description="Ambient noise level estimation" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="ADF_DFLT0DR" description="ADF digital filter data register 0" start="+0x0F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by DFT0" start="8" size="24" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="BSEC" description="Boot and security control" start="0x46009000">
+    <Register name="BSEC_FVR0" description="BSEC fuse word 0 value register" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR1" description="BSEC fuse word 1 value register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR2" description="BSEC fuse word 2 value register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR3" description="BSEC fuse word 3 value register" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR4" description="BSEC fuse word 4 value register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR5" description="BSEC fuse word 5 value register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR6" description="BSEC fuse word 6 value register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR7" description="BSEC fuse word 7 value register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR8" description="BSEC fuse word 8 value register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR9" description="BSEC fuse word 9 value register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR10" description="BSEC fuse word 10 value register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR11" description="BSEC fuse word 11 value register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR12" description="BSEC fuse word 12 value register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR13" description="BSEC fuse word 13 value register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR14" description="BSEC fuse word 14 value register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR15" description="BSEC fuse word 15 value register" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR16" description="BSEC fuse word 16 value register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR17" description="BSEC fuse word 17 value register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR18" description="BSEC fuse word 18 value register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR19" description="BSEC fuse word 19 value register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR20" description="BSEC fuse word 20 value register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR21" description="BSEC fuse word 21 value register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR22" description="BSEC fuse word 22 value register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR23" description="BSEC fuse word 23 value register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR24" description="BSEC fuse word 24 value register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR25" description="BSEC fuse word 25 value register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR26" description="BSEC fuse word 26 value register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR27" description="BSEC fuse word 27 value register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR28" description="BSEC fuse word 28 value register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR29" description="BSEC fuse word 29 value register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR30" description="BSEC fuse word 30 value register" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR31" description="BSEC fuse word 31 value register" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR32" description="BSEC fuse word 32 value register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR33" description="BSEC fuse word 33 value register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR34" description="BSEC fuse word 34 value register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR35" description="BSEC fuse word 35 value register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR36" description="BSEC fuse word 36 value register" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR37" description="BSEC fuse word 37 value register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR38" description="BSEC fuse word 38 value register" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR39" description="BSEC fuse word 39 value register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR40" description="BSEC fuse word 40 value register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR41" description="BSEC fuse word 41 value register" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR42" description="BSEC fuse word 42 value register" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR43" description="BSEC fuse word 43 value register" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR44" description="BSEC fuse word 44 value register" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR45" description="BSEC fuse word 45 value register" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR46" description="BSEC fuse word 46 value register" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR47" description="BSEC fuse word 47 value register" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR48" description="BSEC fuse word 48 value register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR49" description="BSEC fuse word 49 value register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR50" description="BSEC fuse word 50 value register" start="+0xC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR51" description="BSEC fuse word 51 value register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR52" description="BSEC fuse word 52 value register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR53" description="BSEC fuse word 53 value register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR54" description="BSEC fuse word 54 value register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR55" description="BSEC fuse word 55 value register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR56" description="BSEC fuse word 56 value register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR57" description="BSEC fuse word 57 value register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR58" description="BSEC fuse word 58 value register" start="+0xE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR59" description="BSEC fuse word 59 value register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR60" description="BSEC fuse word 60 value register" start="+0xF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR61" description="BSEC fuse word 61 value register" start="+0xF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR62" description="BSEC fuse word 62 value register" start="+0xF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR63" description="BSEC fuse word 63 value register" start="+0xFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR64" description="BSEC fuse word 64 value register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR65" description="BSEC fuse word 65 value register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR66" description="BSEC fuse word 66 value register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR67" description="BSEC fuse word 67 value register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR68" description="BSEC fuse word 68 value register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR69" description="BSEC fuse word 69 value register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR70" description="BSEC fuse word 70 value register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR71" description="BSEC fuse word 71 value register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR72" description="BSEC fuse word 72 value register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR73" description="BSEC fuse word 73 value register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR74" description="BSEC fuse word 74 value register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR75" description="BSEC fuse word 75 value register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR76" description="BSEC fuse word 76 value register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR77" description="BSEC fuse word 77 value register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR78" description="BSEC fuse word 78 value register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR79" description="BSEC fuse word 79 value register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR80" description="BSEC fuse word 80 value register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR81" description="BSEC fuse word 81 value register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR82" description="BSEC fuse word 82 value register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR83" description="BSEC fuse word 83 value register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR84" description="BSEC fuse word 84 value register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR85" description="BSEC fuse word 85 value register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR86" description="BSEC fuse word 86 value register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR87" description="BSEC fuse word 87 value register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR88" description="BSEC fuse word 88 value register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR89" description="BSEC fuse word 89 value register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR90" description="BSEC fuse word 90 value register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR91" description="BSEC fuse word 91 value register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR92" description="BSEC fuse word 92 value register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR93" description="BSEC fuse word 93 value register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR94" description="BSEC fuse word 94 value register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR95" description="BSEC fuse word 95 value register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR96" description="BSEC fuse word 96 value register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR97" description="BSEC fuse word 97 value register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR98" description="BSEC fuse word 98 value register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR99" description="BSEC fuse word 99 value register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR100" description="BSEC fuse word 100 value register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR101" description="BSEC fuse word 101 value register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR102" description="BSEC fuse word 102 value register" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR103" description="BSEC fuse word 103 value register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR104" description="BSEC fuse word 104 value register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR105" description="BSEC fuse word 105 value register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR106" description="BSEC fuse word 106 value register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR107" description="BSEC fuse word 107 value register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR108" description="BSEC fuse word 108 value register" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR109" description="BSEC fuse word 109 value register" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR110" description="BSEC fuse word 110 value register" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR111" description="BSEC fuse word 111 value register" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR112" description="BSEC fuse word 112 value register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR113" description="BSEC fuse word 113 value register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR114" description="BSEC fuse word 114 value register" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR115" description="BSEC fuse word 115 value register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR116" description="BSEC fuse word 116 value register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR117" description="BSEC fuse word 117 value register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR118" description="BSEC fuse word 118 value register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR119" description="BSEC fuse word 119 value register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR120" description="BSEC fuse word 120 value register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR121" description="BSEC fuse word 121 value register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR122" description="BSEC fuse word 122 value register" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR123" description="BSEC fuse word 123 value register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR124" description="BSEC fuse word 124 value register" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR125" description="BSEC fuse word 125 value register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR126" description="BSEC fuse word 126 value register" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR127" description="BSEC fuse word 127 value register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR128" description="BSEC fuse word 128 value register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR129" description="BSEC fuse word 129 value register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR130" description="BSEC fuse word 130 value register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR131" description="BSEC fuse word 131 value register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR132" description="BSEC fuse word 132 value register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR133" description="BSEC fuse word 133 value register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR134" description="BSEC fuse word 134 value register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR135" description="BSEC fuse word 135 value register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR136" description="BSEC fuse word 136 value register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR137" description="BSEC fuse word 137 value register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR138" description="BSEC fuse word 138 value register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR139" description="BSEC fuse word 139 value register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR140" description="BSEC fuse word 140 value register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR141" description="BSEC fuse word 141 value register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR142" description="BSEC fuse word 142 value register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR143" description="BSEC fuse word 143 value register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR144" description="BSEC fuse word 144 value register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR145" description="BSEC fuse word 145 value register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR146" description="BSEC fuse word 146 value register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR147" description="BSEC fuse word 147 value register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR148" description="BSEC fuse word 148 value register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR149" description="BSEC fuse word 149 value register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR150" description="BSEC fuse word 150 value register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR151" description="BSEC fuse word 151 value register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR152" description="BSEC fuse word 152 value register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR153" description="BSEC fuse word 153 value register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR154" description="BSEC fuse word 154 value register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR155" description="BSEC fuse word 155 value register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR156" description="BSEC fuse word 156 value register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR157" description="BSEC fuse word 157 value register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR158" description="BSEC fuse word 158 value register" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR159" description="BSEC fuse word 159 value register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR160" description="BSEC fuse word 160 value register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR161" description="BSEC fuse word 161 value register" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR162" description="BSEC fuse word 162 value register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR163" description="BSEC fuse word 163 value register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR164" description="BSEC fuse word 164 value register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR165" description="BSEC fuse word 165 value register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR166" description="BSEC fuse word 166 value register" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR167" description="BSEC fuse word 167 value register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR168" description="BSEC fuse word 168 value register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR169" description="BSEC fuse word 169 value register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR170" description="BSEC fuse word 170 value register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR171" description="BSEC fuse word 171 value register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR172" description="BSEC fuse word 172 value register" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR173" description="BSEC fuse word 173 value register" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR174" description="BSEC fuse word 174 value register" start="+0x2B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR175" description="BSEC fuse word 175 value register" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR176" description="BSEC fuse word 176 value register" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR177" description="BSEC fuse word 177 value register" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR178" description="BSEC fuse word 178 value register" start="+0x2C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR179" description="BSEC fuse word 179 value register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR180" description="BSEC fuse word 180 value register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR181" description="BSEC fuse word 181 value register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR182" description="BSEC fuse word 182 value register" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR183" description="BSEC fuse word 183 value register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR184" description="BSEC fuse word 184 value register" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR185" description="BSEC fuse word 185 value register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR186" description="BSEC fuse word 186 value register" start="+0x2E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR187" description="BSEC fuse word 187 value register" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR188" description="BSEC fuse word 188 value register" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR189" description="BSEC fuse word 189 value register" start="+0x2F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR190" description="BSEC fuse word 190 value register" start="+0x2F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR191" description="BSEC fuse word 191 value register" start="+0x2FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR192" description="BSEC fuse word 192 value register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR193" description="BSEC fuse word 193 value register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR194" description="BSEC fuse word 194 value register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR195" description="BSEC fuse word 195 value register" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR196" description="BSEC fuse word 196 value register" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR197" description="BSEC fuse word 197 value register" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR198" description="BSEC fuse word 198 value register" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR199" description="BSEC fuse word 199 value register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR200" description="BSEC fuse word 200 value register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR201" description="BSEC fuse word 201 value register" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR202" description="BSEC fuse word 202 value register" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR203" description="BSEC fuse word 203 value register" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR204" description="BSEC fuse word 204 value register" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR205" description="BSEC fuse word 205 value register" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR206" description="BSEC fuse word 206 value register" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR207" description="BSEC fuse word 207 value register" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR208" description="BSEC fuse word 208 value register" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR209" description="BSEC fuse word 209 value register" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR210" description="BSEC fuse word 210 value register" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR211" description="BSEC fuse word 211 value register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR212" description="BSEC fuse word 212 value register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR213" description="BSEC fuse word 213 value register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR214" description="BSEC fuse word 214 value register" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR215" description="BSEC fuse word 215 value register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR216" description="BSEC fuse word 216 value register" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR217" description="BSEC fuse word 217 value register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR218" description="BSEC fuse word 218 value register" start="+0x368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR219" description="BSEC fuse word 219 value register" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR220" description="BSEC fuse word 220 value register" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR221" description="BSEC fuse word 221 value register" start="+0x374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR222" description="BSEC fuse word 222 value register" start="+0x378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR223" description="BSEC fuse word 223 value register" start="+0x37C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR224" description="BSEC fuse word 224 value register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR225" description="BSEC fuse word 225 value register" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR226" description="BSEC fuse word 226 value register" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR227" description="BSEC fuse word 227 value register" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR228" description="BSEC fuse word 228 value register" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR229" description="BSEC fuse word 229 value register" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR230" description="BSEC fuse word 230 value register" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR231" description="BSEC fuse word 231 value register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR232" description="BSEC fuse word 232 value register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR233" description="BSEC fuse word 233 value register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR234" description="BSEC fuse word 234 value register" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR235" description="BSEC fuse word 235 value register" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR236" description="BSEC fuse word 236 value register" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR237" description="BSEC fuse word 237 value register" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR238" description="BSEC fuse word 238 value register" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR239" description="BSEC fuse word 239 value register" start="+0x3BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR240" description="BSEC fuse word 240 value register" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR241" description="BSEC fuse word 241 value register" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR242" description="BSEC fuse word 242 value register" start="+0x3C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR243" description="BSEC fuse word 243 value register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR244" description="BSEC fuse word 244 value register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR245" description="BSEC fuse word 245 value register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR246" description="BSEC fuse word 246 value register" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR247" description="BSEC fuse word 247 value register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR248" description="BSEC fuse word 248 value register" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR249" description="BSEC fuse word 249 value register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR250" description="BSEC fuse word 250 value register" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR251" description="BSEC fuse word 251 value register" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR252" description="BSEC fuse word 252 value register" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR253" description="BSEC fuse word 253 value register" start="+0x3F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR254" description="BSEC fuse word 254 value register" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR255" description="BSEC fuse word 255 value register" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR256" description="BSEC fuse word 256 value register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR257" description="BSEC fuse word 257 value register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR258" description="BSEC fuse word 258 value register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR259" description="BSEC fuse word 259 value register" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR260" description="BSEC fuse word 260 value register" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR261" description="BSEC fuse word 261 value register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR262" description="BSEC fuse word 262 value register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR263" description="BSEC fuse word 263 value register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR264" description="BSEC fuse word 264 value register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR265" description="BSEC fuse word 265 value register" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR266" description="BSEC fuse word 266 value register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR267" description="BSEC fuse word 267 value register" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR268" description="BSEC fuse word 268 value register" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR269" description="BSEC fuse word 269 value register" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR270" description="BSEC fuse word 270 value register" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR271" description="BSEC fuse word 271 value register" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR272" description="BSEC fuse word 272 value register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR273" description="BSEC fuse word 273 value register" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR274" description="BSEC fuse word 274 value register" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR275" description="BSEC fuse word 275 value register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR276" description="BSEC fuse word 276 value register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR277" description="BSEC fuse word 277 value register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR278" description="BSEC fuse word 278 value register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR279" description="BSEC fuse word 279 value register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR280" description="BSEC fuse word 280 value register" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR281" description="BSEC fuse word 281 value register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR282" description="BSEC fuse word 282 value register" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR283" description="BSEC fuse word 283 value register" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR284" description="BSEC fuse word 284 value register" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR285" description="BSEC fuse word 285 value register" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR286" description="BSEC fuse word 286 value register" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR287" description="BSEC fuse word 287 value register" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR288" description="BSEC fuse word 288 value register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR289" description="BSEC fuse word 289 value register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR290" description="BSEC fuse word 290 value register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR291" description="BSEC fuse word 291 value register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR292" description="BSEC fuse word 292 value register" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR293" description="BSEC fuse word 293 value register" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR294" description="BSEC fuse word 294 value register" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR295" description="BSEC fuse word 295 value register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR296" description="BSEC fuse word 296 value register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR297" description="BSEC fuse word 297 value register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR298" description="BSEC fuse word 298 value register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR299" description="BSEC fuse word 299 value register" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR300" description="BSEC fuse word 300 value register" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR301" description="BSEC fuse word 301 value register" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR302" description="BSEC fuse word 302 value register" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR303" description="BSEC fuse word 303 value register" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR304" description="BSEC fuse word 304 value register" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR305" description="BSEC fuse word 305 value register" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR306" description="BSEC fuse word 306 value register" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR307" description="BSEC fuse word 307 value register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR308" description="BSEC fuse word 308 value register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR309" description="BSEC fuse word 309 value register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR310" description="BSEC fuse word 310 value register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR311" description="BSEC fuse word 311 value register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR312" description="BSEC fuse word 312 value register" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR313" description="BSEC fuse word 313 value register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR314" description="BSEC fuse word 314 value register" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR315" description="BSEC fuse word 315 value register" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR316" description="BSEC fuse word 316 value register" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR317" description="BSEC fuse word 317 value register" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR318" description="BSEC fuse word 318 value register" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR319" description="BSEC fuse word 319 value register" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR320" description="BSEC fuse word 320 value register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR321" description="BSEC fuse word 321 value register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR322" description="BSEC fuse word 322 value register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR323" description="BSEC fuse word 323 value register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR324" description="BSEC fuse word 324 value register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR325" description="BSEC fuse word 325 value register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR326" description="BSEC fuse word 326 value register" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR327" description="BSEC fuse word 327 value register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR328" description="BSEC fuse word 328 value register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR329" description="BSEC fuse word 329 value register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR330" description="BSEC fuse word 330 value register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR331" description="BSEC fuse word 331 value register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR332" description="BSEC fuse word 332 value register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR333" description="BSEC fuse word 333 value register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR334" description="BSEC fuse word 334 value register" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR335" description="BSEC fuse word 335 value register" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR336" description="BSEC fuse word 336 value register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR337" description="BSEC fuse word 337 value register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR338" description="BSEC fuse word 338 value register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR339" description="BSEC fuse word 339 value register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR340" description="BSEC fuse word 340 value register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR341" description="BSEC fuse word 341 value register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR342" description="BSEC fuse word 342 value register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR343" description="BSEC fuse word 343 value register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR344" description="BSEC fuse word 344 value register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR345" description="BSEC fuse word 345 value register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR346" description="BSEC fuse word 346 value register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR347" description="BSEC fuse word 347 value register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR348" description="BSEC fuse word 348 value register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR349" description="BSEC fuse word 349 value register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR350" description="BSEC fuse word 350 value register" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR351" description="BSEC fuse word 351 value register" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR352" description="BSEC fuse word 352 value register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR353" description="BSEC fuse word 353 value register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR354" description="BSEC fuse word 354 value register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR355" description="BSEC fuse word 355 value register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR356" description="BSEC fuse word 356 value register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR357" description="BSEC fuse word 357 value register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR358" description="BSEC fuse word 358 value register" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR359" description="BSEC fuse word 359 value register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR360" description="BSEC fuse word 360 value register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR361" description="BSEC fuse word 361 value register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR362" description="BSEC fuse word 362 value register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR363" description="BSEC fuse word 363 value register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR364" description="BSEC fuse word 364 value register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR365" description="BSEC fuse word 365 value register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR366" description="BSEC fuse word 366 value register" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR367" description="BSEC fuse word 367 value register" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR368" description="BSEC fuse word 368 value register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR369" description="BSEC fuse word 369 value register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR370" description="BSEC fuse word 370 value register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR371" description="BSEC fuse word 371 value register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR372" description="BSEC fuse word 372 value register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR373" description="BSEC fuse word 373 value register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR374" description="BSEC fuse word 374 value register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR375" description="BSEC fuse word 375 value register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SPLOCK0" description="BSEC sticky programming lock register 0" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK0" description="Sticky programming lock for word 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 0 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 0 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK1" description="Sticky programming lock for word 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 1 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 1 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK2" description="Sticky programming lock for word 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 2 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 2 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK3" description="Sticky programming lock for word 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 3 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 3 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK4" description="Sticky programming lock for word 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 4 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 4 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK5" description="Sticky programming lock for word 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 5 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 5 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK6" description="Sticky programming lock for word 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 6 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 6 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK7" description="Sticky programming lock for word 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 7 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 7 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK8" description="Sticky programming lock for word 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 8 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 8 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK9" description="Sticky programming lock for word 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 9 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 9 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK10" description="Sticky programming lock for word 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 10 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 10 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK11" description="Sticky programming lock for word 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 11 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 11 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK12" description="Sticky programming lock for word 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 12 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 12 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK13" description="Sticky programming lock for word 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 13 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 13 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK14" description="Sticky programming lock for word 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 14 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 14 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK15" description="Sticky programming lock for word 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 15 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 15 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK16" description="Sticky programming lock for word 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 16 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 16 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK17" description="Sticky programming lock for word 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 17 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 17 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK18" description="Sticky programming lock for word 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 18 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 18 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK19" description="Sticky programming lock for word 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 19 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 19 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK20" description="Sticky programming lock for word 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 20 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 20 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK21" description="Sticky programming lock for word 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 21 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 21 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK22" description="Sticky programming lock for word 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 22 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 22 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK23" description="Sticky programming lock for word 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 23 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 23 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK24" description="Sticky programming lock for word 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 24 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 24 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK25" description="Sticky programming lock for word 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 25 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 25 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK26" description="Sticky programming lock for word 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 26 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 26 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK27" description="Sticky programming lock for word 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 27 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 27 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK28" description="Sticky programming lock for word 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 28 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 28 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK29" description="Sticky programming lock for word 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 29 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 29 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK30" description="Sticky programming lock for word 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 30 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 30 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK31" description="Sticky programming lock for word 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 31 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 31 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK1" description="BSEC sticky programming lock register 1" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK32" description="Sticky programming lock for word 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 32 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 32 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK33" description="Sticky programming lock for word 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 33 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 33 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK34" description="Sticky programming lock for word 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 34 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 34 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK35" description="Sticky programming lock for word 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 35 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 35 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK36" description="Sticky programming lock for word 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 36 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 36 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK37" description="Sticky programming lock for word 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 37 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 37 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK38" description="Sticky programming lock for word 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 38 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 38 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK39" description="Sticky programming lock for word 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 39 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 39 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK40" description="Sticky programming lock for word 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 40 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 40 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK41" description="Sticky programming lock for word 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 41 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 41 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK42" description="Sticky programming lock for word 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 42 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 42 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK43" description="Sticky programming lock for word 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 43 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 43 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK44" description="Sticky programming lock for word 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 44 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 44 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK45" description="Sticky programming lock for word 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 45 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 45 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK46" description="Sticky programming lock for word 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 46 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 46 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK47" description="Sticky programming lock for word 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 47 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 47 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK48" description="Sticky programming lock for word 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 48 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 48 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK49" description="Sticky programming lock for word 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 49 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 49 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK50" description="Sticky programming lock for word 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 50 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 50 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK51" description="Sticky programming lock for word 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 51 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 51 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK52" description="Sticky programming lock for word 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 52 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 52 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK53" description="Sticky programming lock for word 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 53 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 53 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK54" description="Sticky programming lock for word 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 54 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 54 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK55" description="Sticky programming lock for word 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 55 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 55 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK56" description="Sticky programming lock for word 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 56 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 56 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK57" description="Sticky programming lock for word 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 57 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 57 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK58" description="Sticky programming lock for word 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 58 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 58 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK59" description="Sticky programming lock for word 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 59 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 59 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK60" description="Sticky programming lock for word 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 60 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 60 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK61" description="Sticky programming lock for word 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 61 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 61 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK62" description="Sticky programming lock for word 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 62 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 62 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK63" description="Sticky programming lock for word 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 63 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 63 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK2" description="BSEC sticky programming lock register 2" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK64" description="Sticky programming lock for word 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 64 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 64 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK65" description="Sticky programming lock for word 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 65 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 65 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK66" description="Sticky programming lock for word 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 66 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 66 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK67" description="Sticky programming lock for word 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 67 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 67 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK68" description="Sticky programming lock for word 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 68 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 68 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK69" description="Sticky programming lock for word 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 69 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 69 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK70" description="Sticky programming lock for word 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 70 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 70 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK71" description="Sticky programming lock for word 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 71 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 71 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK72" description="Sticky programming lock for word 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 72 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 72 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK73" description="Sticky programming lock for word 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 73 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 73 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK74" description="Sticky programming lock for word 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 74 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 74 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK75" description="Sticky programming lock for word 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 75 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 75 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK76" description="Sticky programming lock for word 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 76 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 76 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK77" description="Sticky programming lock for word 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 77 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 77 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK78" description="Sticky programming lock for word 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 78 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 78 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK79" description="Sticky programming lock for word 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 79 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 79 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK80" description="Sticky programming lock for word 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 80 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 80 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK81" description="Sticky programming lock for word 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 81 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 81 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK82" description="Sticky programming lock for word 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 82 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 82 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK83" description="Sticky programming lock for word 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 83 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 83 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK84" description="Sticky programming lock for word 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 84 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 84 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK85" description="Sticky programming lock for word 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 85 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 85 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK86" description="Sticky programming lock for word 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 86 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 86 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK87" description="Sticky programming lock for word 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 87 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 87 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK88" description="Sticky programming lock for word 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 88 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 88 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK89" description="Sticky programming lock for word 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 89 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 89 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK90" description="Sticky programming lock for word 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 90 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 90 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK91" description="Sticky programming lock for word 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 91 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 91 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK92" description="Sticky programming lock for word 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 92 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 92 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK93" description="Sticky programming lock for word 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 93 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 93 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK94" description="Sticky programming lock for word 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 94 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 94 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK95" description="Sticky programming lock for word 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 95 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 95 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK3" description="BSEC sticky programming lock register 3" start="+0x80C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK96" description="Sticky programming lock for word 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 96 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 96 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK97" description="Sticky programming lock for word 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 97 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 97 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK98" description="Sticky programming lock for word 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 98 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 98 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK99" description="Sticky programming lock for word 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 99 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 99 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK100" description="Sticky programming lock for word 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 100 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 100 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK101" description="Sticky programming lock for word 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 101 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 101 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK102" description="Sticky programming lock for word 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 102 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 102 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK103" description="Sticky programming lock for word 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 103 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 103 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK104" description="Sticky programming lock for word 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 104 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 104 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK105" description="Sticky programming lock for word 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 105 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 105 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK106" description="Sticky programming lock for word 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 106 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 106 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK107" description="Sticky programming lock for word 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 107 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 107 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK108" description="Sticky programming lock for word 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 108 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 108 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK109" description="Sticky programming lock for word 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 109 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 109 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK110" description="Sticky programming lock for word 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 110 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 110 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK111" description="Sticky programming lock for word 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 111 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 111 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK112" description="Sticky programming lock for word 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 112 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 112 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK113" description="Sticky programming lock for word 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 113 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 113 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK114" description="Sticky programming lock for word 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 114 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 114 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK115" description="Sticky programming lock for word 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 115 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 115 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK116" description="Sticky programming lock for word 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 116 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 116 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK117" description="Sticky programming lock for word 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 117 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 117 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK118" description="Sticky programming lock for word 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 118 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 118 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK119" description="Sticky programming lock for word 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 119 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 119 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK120" description="Sticky programming lock for word 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 120 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 120 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK121" description="Sticky programming lock for word 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 121 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 121 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK122" description="Sticky programming lock for word 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 122 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 122 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK123" description="Sticky programming lock for word 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 123 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 123 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK124" description="Sticky programming lock for word 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 124 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 124 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK125" description="Sticky programming lock for word 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 125 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 125 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK126" description="Sticky programming lock for word 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 126 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 126 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK127" description="Sticky programming lock for word 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 127 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 127 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK4" description="BSEC sticky programming lock register 4" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK128" description="Sticky programming lock for word 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 128 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 128 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK129" description="Sticky programming lock for word 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 129 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 129 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK130" description="Sticky programming lock for word 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 130 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 130 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK131" description="Sticky programming lock for word 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 131 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 131 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK132" description="Sticky programming lock for word 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 132 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 132 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK133" description="Sticky programming lock for word 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 133 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 133 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK134" description="Sticky programming lock for word 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 134 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 134 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK135" description="Sticky programming lock for word 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 135 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 135 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK136" description="Sticky programming lock for word 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 136 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 136 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK137" description="Sticky programming lock for word 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 137 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 137 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK138" description="Sticky programming lock for word 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 138 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 138 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK139" description="Sticky programming lock for word 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 139 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 139 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK140" description="Sticky programming lock for word 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 140 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 140 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK141" description="Sticky programming lock for word 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 141 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 141 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK142" description="Sticky programming lock for word 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 142 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 142 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK143" description="Sticky programming lock for word 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 143 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 143 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK144" description="Sticky programming lock for word 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 144 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 144 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK145" description="Sticky programming lock for word 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 145 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 145 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK146" description="Sticky programming lock for word 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 146 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 146 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK147" description="Sticky programming lock for word 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 147 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 147 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK148" description="Sticky programming lock for word 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 148 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 148 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK149" description="Sticky programming lock for word 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 149 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 149 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK150" description="Sticky programming lock for word 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 150 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 150 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK151" description="Sticky programming lock for word 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 151 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 151 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK152" description="Sticky programming lock for word 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 152 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 152 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK153" description="Sticky programming lock for word 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 153 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 153 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK154" description="Sticky programming lock for word 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 154 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 154 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK155" description="Sticky programming lock for word 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 155 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 155 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK156" description="Sticky programming lock for word 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 156 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 156 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK157" description="Sticky programming lock for word 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 157 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 157 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK158" description="Sticky programming lock for word 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 158 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 158 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK159" description="Sticky programming lock for word 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 159 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 159 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK5" description="BSEC sticky programming lock register 5" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK160" description="Sticky programming lock for word 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 160 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 160 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK161" description="Sticky programming lock for word 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 161 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 161 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK162" description="Sticky programming lock for word 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 162 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 162 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK163" description="Sticky programming lock for word 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 163 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 163 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK164" description="Sticky programming lock for word 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 164 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 164 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK165" description="Sticky programming lock for word 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 165 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 165 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK166" description="Sticky programming lock for word 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 166 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 166 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK167" description="Sticky programming lock for word 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 167 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 167 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK168" description="Sticky programming lock for word 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 168 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 168 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK169" description="Sticky programming lock for word 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 169 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 169 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK170" description="Sticky programming lock for word 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 170 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 170 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK171" description="Sticky programming lock for word 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 171 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 171 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK172" description="Sticky programming lock for word 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 172 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 172 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK173" description="Sticky programming lock for word 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 173 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 173 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK174" description="Sticky programming lock for word 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 174 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 174 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK175" description="Sticky programming lock for word 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 175 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 175 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK176" description="Sticky programming lock for word 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 176 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 176 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK177" description="Sticky programming lock for word 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 177 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 177 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK178" description="Sticky programming lock for word 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 178 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 178 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK179" description="Sticky programming lock for word 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 179 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 179 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK180" description="Sticky programming lock for word 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 180 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 180 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK181" description="Sticky programming lock for word 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 181 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 181 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK182" description="Sticky programming lock for word 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 182 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 182 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK183" description="Sticky programming lock for word 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 183 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 183 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK184" description="Sticky programming lock for word 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 184 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 184 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK185" description="Sticky programming lock for word 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 185 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 185 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK186" description="Sticky programming lock for word 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 186 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 186 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK187" description="Sticky programming lock for word 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 187 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 187 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK188" description="Sticky programming lock for word 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 188 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 188 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK189" description="Sticky programming lock for word 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 189 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 189 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK190" description="Sticky programming lock for word 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 190 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 190 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK191" description="Sticky programming lock for word 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 191 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 191 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK6" description="BSEC sticky programming lock register 6" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK192" description="Sticky programming lock for word 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 192 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 192 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK193" description="Sticky programming lock for word 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 193 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 193 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK194" description="Sticky programming lock for word 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 194 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 194 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK195" description="Sticky programming lock for word 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 195 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 195 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK196" description="Sticky programming lock for word 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 196 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 196 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK197" description="Sticky programming lock for word 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 197 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 197 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK198" description="Sticky programming lock for word 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 198 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 198 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK199" description="Sticky programming lock for word 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 199 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 199 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK200" description="Sticky programming lock for word 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 200 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 200 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK201" description="Sticky programming lock for word 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 201 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 201 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK202" description="Sticky programming lock for word 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 202 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 202 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK203" description="Sticky programming lock for word 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 203 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 203 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK204" description="Sticky programming lock for word 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 204 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 204 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK205" description="Sticky programming lock for word 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 205 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 205 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK206" description="Sticky programming lock for word 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 206 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 206 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK207" description="Sticky programming lock for word 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 207 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 207 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK208" description="Sticky programming lock for word 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 208 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 208 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK209" description="Sticky programming lock for word 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 209 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 209 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK210" description="Sticky programming lock for word 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 210 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 210 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK211" description="Sticky programming lock for word 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 211 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 211 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK212" description="Sticky programming lock for word 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 212 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 212 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK213" description="Sticky programming lock for word 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 213 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 213 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK214" description="Sticky programming lock for word 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 214 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 214 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK215" description="Sticky programming lock for word 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 215 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 215 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK216" description="Sticky programming lock for word 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 216 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 216 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK217" description="Sticky programming lock for word 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 217 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 217 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK218" description="Sticky programming lock for word 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 218 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 218 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK219" description="Sticky programming lock for word 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 219 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 219 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK220" description="Sticky programming lock for word 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 220 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 220 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK221" description="Sticky programming lock for word 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 221 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 221 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK222" description="Sticky programming lock for word 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 222 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 222 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK223" description="Sticky programming lock for word 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 223 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 223 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK7" description="BSEC sticky programming lock register 7" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK224" description="Sticky programming lock for word 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 224 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 224 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK225" description="Sticky programming lock for word 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 225 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 225 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK226" description="Sticky programming lock for word 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 226 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 226 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK227" description="Sticky programming lock for word 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 227 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 227 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK228" description="Sticky programming lock for word 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 228 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 228 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK229" description="Sticky programming lock for word 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 229 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 229 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK230" description="Sticky programming lock for word 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 230 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 230 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK231" description="Sticky programming lock for word 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 231 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 231 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK232" description="Sticky programming lock for word 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 232 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 232 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK233" description="Sticky programming lock for word 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 233 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 233 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK234" description="Sticky programming lock for word 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 234 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 234 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK235" description="Sticky programming lock for word 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 235 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 235 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK236" description="Sticky programming lock for word 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 236 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 236 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK237" description="Sticky programming lock for word 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 237 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 237 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK238" description="Sticky programming lock for word 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 238 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 238 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK239" description="Sticky programming lock for word 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 239 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 239 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK240" description="Sticky programming lock for word 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 240 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 240 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK241" description="Sticky programming lock for word 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 241 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 241 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK242" description="Sticky programming lock for word 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 242 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 242 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK243" description="Sticky programming lock for word 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 243 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 243 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK244" description="Sticky programming lock for word 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 244 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 244 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK245" description="Sticky programming lock for word 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 245 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 245 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK246" description="Sticky programming lock for word 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 246 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 246 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK247" description="Sticky programming lock for word 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 247 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 247 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK248" description="Sticky programming lock for word 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 248 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 248 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK249" description="Sticky programming lock for word 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 249 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 249 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK250" description="Sticky programming lock for word 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 250 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 250 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK251" description="Sticky programming lock for word 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 251 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 251 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK252" description="Sticky programming lock for word 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 252 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 252 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK253" description="Sticky programming lock for word 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 253 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 253 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK254" description="Sticky programming lock for word 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 254 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 254 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK255" description="Sticky programming lock for word 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 255 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 255 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK8" description="BSEC sticky programming lock register 8" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK256" description="Sticky programming lock for word 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 256 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 256 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK257" description="Sticky programming lock for word 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 257 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 257 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK258" description="Sticky programming lock for word 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 258 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 258 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK259" description="Sticky programming lock for word 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 259 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 259 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK260" description="Sticky programming lock for word 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 260 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 260 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK261" description="Sticky programming lock for word 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 261 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 261 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK262" description="Sticky programming lock for word 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 262 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 262 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK263" description="Sticky programming lock for word 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 263 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 263 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK264" description="Sticky programming lock for word 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 264 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 264 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK265" description="Sticky programming lock for word 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 265 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 265 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK266" description="Sticky programming lock for word 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 266 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 266 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK267" description="Sticky programming lock for word 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 267 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 267 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK268" description="Sticky programming lock for word 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 268 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 268 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK269" description="Sticky programming lock for word 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 269 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 269 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK270" description="Sticky programming lock for word 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 270 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 270 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK271" description="Sticky programming lock for word 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 271 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 271 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK272" description="Sticky programming lock for word 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 272 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 272 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK273" description="Sticky programming lock for word 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 273 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 273 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK274" description="Sticky programming lock for word 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 274 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 274 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK275" description="Sticky programming lock for word 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 275 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 275 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK276" description="Sticky programming lock for word 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 276 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 276 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK277" description="Sticky programming lock for word 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 277 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 277 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK278" description="Sticky programming lock for word 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 278 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 278 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK279" description="Sticky programming lock for word 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 279 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 279 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK280" description="Sticky programming lock for word 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 280 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 280 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK281" description="Sticky programming lock for word 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 281 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 281 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK282" description="Sticky programming lock for word 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 282 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 282 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK283" description="Sticky programming lock for word 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 283 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 283 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK284" description="Sticky programming lock for word 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 284 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 284 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK285" description="Sticky programming lock for word 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 285 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 285 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK286" description="Sticky programming lock for word 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 286 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 286 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK287" description="Sticky programming lock for word 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 287 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 287 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK9" description="BSEC sticky programming lock register 9" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK288" description="Sticky programming lock for word 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 288 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 288 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK289" description="Sticky programming lock for word 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 289 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 289 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK290" description="Sticky programming lock for word 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 290 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 290 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK291" description="Sticky programming lock for word 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 291 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 291 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK292" description="Sticky programming lock for word 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 292 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 292 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK293" description="Sticky programming lock for word 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 293 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 293 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK294" description="Sticky programming lock for word 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 294 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 294 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK295" description="Sticky programming lock for word 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 295 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 295 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK296" description="Sticky programming lock for word 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 296 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 296 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK297" description="Sticky programming lock for word 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 297 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 297 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK298" description="Sticky programming lock for word 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 298 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 298 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK299" description="Sticky programming lock for word 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 299 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 299 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK300" description="Sticky programming lock for word 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 300 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 300 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK301" description="Sticky programming lock for word 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 301 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 301 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK302" description="Sticky programming lock for word 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 302 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 302 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK303" description="Sticky programming lock for word 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 303 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 303 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK304" description="Sticky programming lock for word 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 304 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 304 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK305" description="Sticky programming lock for word 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 305 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 305 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK306" description="Sticky programming lock for word 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 306 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 306 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK307" description="Sticky programming lock for word 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 307 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 307 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK308" description="Sticky programming lock for word 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 308 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 308 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK309" description="Sticky programming lock for word 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 309 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 309 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK310" description="Sticky programming lock for word 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 310 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 310 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK311" description="Sticky programming lock for word 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 311 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 311 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK312" description="Sticky programming lock for word 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 312 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 312 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK313" description="Sticky programming lock for word 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 313 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 313 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK314" description="Sticky programming lock for word 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 314 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 314 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK315" description="Sticky programming lock for word 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 315 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 315 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK316" description="Sticky programming lock for word 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 316 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 316 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK317" description="Sticky programming lock for word 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 317 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 317 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK318" description="Sticky programming lock for word 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 318 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 318 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK319" description="Sticky programming lock for word 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 319 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 319 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK10" description="BSEC sticky programming lock register 10" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK320" description="Sticky programming lock for word 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 320 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 320 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK321" description="Sticky programming lock for word 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 321 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 321 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK322" description="Sticky programming lock for word 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 322 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 322 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK323" description="Sticky programming lock for word 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 323 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 323 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK324" description="Sticky programming lock for word 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 324 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 324 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK325" description="Sticky programming lock for word 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 325 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 325 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK326" description="Sticky programming lock for word 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 326 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 326 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK327" description="Sticky programming lock for word 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 327 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 327 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK328" description="Sticky programming lock for word 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 328 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 328 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK329" description="Sticky programming lock for word 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 329 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 329 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK330" description="Sticky programming lock for word 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 330 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 330 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK331" description="Sticky programming lock for word 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 331 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 331 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK332" description="Sticky programming lock for word 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 332 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 332 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK333" description="Sticky programming lock for word 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 333 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 333 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK334" description="Sticky programming lock for word 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 334 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 334 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK335" description="Sticky programming lock for word 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 335 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 335 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK336" description="Sticky programming lock for word 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 336 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 336 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK337" description="Sticky programming lock for word 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 337 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 337 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK338" description="Sticky programming lock for word 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 338 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 338 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK339" description="Sticky programming lock for word 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 339 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 339 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK340" description="Sticky programming lock for word 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 340 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 340 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK341" description="Sticky programming lock for word 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 341 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 341 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK342" description="Sticky programming lock for word 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 342 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 342 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK343" description="Sticky programming lock for word 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 343 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 343 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK344" description="Sticky programming lock for word 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 344 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 344 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK345" description="Sticky programming lock for word 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 345 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 345 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK346" description="Sticky programming lock for word 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 346 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 346 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK347" description="Sticky programming lock for word 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 347 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 347 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK348" description="Sticky programming lock for word 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 348 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 348 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK349" description="Sticky programming lock for word 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 349 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 349 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK350" description="Sticky programming lock for word 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 350 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 350 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK351" description="Sticky programming lock for word 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 351 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 351 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK11" description="BSEC sticky programming lock register 11" start="+0x82C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK352" description="Sticky programming lock for word 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 352 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 352 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK353" description="Sticky programming lock for word 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 353 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 353 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK354" description="Sticky programming lock for word 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 354 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 354 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK355" description="Sticky programming lock for word 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 355 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 355 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK356" description="Sticky programming lock for word 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 356 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 356 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK357" description="Sticky programming lock for word 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 357 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 357 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK358" description="Sticky programming lock for word 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 358 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 358 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK359" description="Sticky programming lock for word 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 359 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 359 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK360" description="Sticky programming lock for word 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 360 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 360 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK361" description="Sticky programming lock for word 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 361 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 361 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK362" description="Sticky programming lock for word 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 362 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 362 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK363" description="Sticky programming lock for word 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 363 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 363 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK364" description="Sticky programming lock for word 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 364 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 364 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK365" description="Sticky programming lock for word 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 365 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 365 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK366" description="Sticky programming lock for word 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 366 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 366 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK367" description="Sticky programming lock for word 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 367 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 367 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK368" description="Sticky programming lock for word 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 368 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 368 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK369" description="Sticky programming lock for word 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 369 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 369 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK370" description="Sticky programming lock for word 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 370 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 370 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK371" description="Sticky programming lock for word 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 371 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 371 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK372" description="Sticky programming lock for word 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 372 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 372 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK373" description="Sticky programming lock for word 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 373 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 373 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK374" description="Sticky programming lock for word 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 374 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 374 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK375" description="Sticky programming lock for word 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 375 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 375 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK376" description="Sticky programming lock for word 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 376 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 376 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK377" description="Sticky programming lock for word 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 377 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 377 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK378" description="Sticky programming lock for word 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 378 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 378 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK379" description="Sticky programming lock for word 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 379 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 379 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK380" description="Sticky programming lock for word 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 380 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 380 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK381" description="Sticky programming lock for word 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 381 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 381 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK382" description="Sticky programming lock for word 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 382 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 382 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK383" description="Sticky programming lock for word 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 383 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 383 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK0" description="BSEC sticky write lock register 0" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK0" description="sticky write lock for shadow register 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR0 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR0 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK1" description="sticky write lock for shadow register 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR1 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR1 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK2" description="sticky write lock for shadow register 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR2 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR2 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK3" description="sticky write lock for shadow register 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR3 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR3 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK4" description="sticky write lock for shadow register 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR4 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR4 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK5" description="sticky write lock for shadow register 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR5 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR5 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK6" description="sticky write lock for shadow register 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR6 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR6 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK7" description="sticky write lock for shadow register 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR7 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR7 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK8" description="sticky write lock for shadow register 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR8 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR8 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK9" description="sticky write lock for shadow register 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR9 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR9 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK10" description="sticky write lock for shadow register 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR10 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR10 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK11" description="sticky write lock for shadow register 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR11 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR11 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK12" description="sticky write lock for shadow register 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR12 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR12 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK13" description="sticky write lock for shadow register 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR13 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR13 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK14" description="sticky write lock for shadow register 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR14 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR14 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK15" description="sticky write lock for shadow register 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR15 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR15 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK16" description="sticky write lock for shadow register 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR16 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR16 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK17" description="sticky write lock for shadow register 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR17 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR17 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK18" description="sticky write lock for shadow register 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR18 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR18 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK19" description="sticky write lock for shadow register 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR19 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR19 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK20" description="sticky write lock for shadow register 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR20 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR20 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK21" description="sticky write lock for shadow register 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR21 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR21 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK22" description="sticky write lock for shadow register 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR22 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR22 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK23" description="sticky write lock for shadow register 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR23 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR23 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK24" description="sticky write lock for shadow register 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR24 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR24 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK25" description="sticky write lock for shadow register 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR25 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR25 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK26" description="sticky write lock for shadow register 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR26 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR26 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK27" description="sticky write lock for shadow register 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR27 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR27 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK28" description="sticky write lock for shadow register 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR28 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR28 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK29" description="sticky write lock for shadow register 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR29 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR29 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK30" description="sticky write lock for shadow register 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR30 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR30 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK31" description="sticky write lock for shadow register 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR31 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR31 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK1" description="BSEC sticky write lock register 1" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK32" description="sticky write lock for shadow register 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR32 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR32 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK33" description="sticky write lock for shadow register 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR33 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR33 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK34" description="sticky write lock for shadow register 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR34 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR34 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK35" description="sticky write lock for shadow register 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR35 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR35 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK36" description="sticky write lock for shadow register 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR36 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR36 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK37" description="sticky write lock for shadow register 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR37 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR37 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK38" description="sticky write lock for shadow register 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR38 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR38 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK39" description="sticky write lock for shadow register 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR39 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR39 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK40" description="sticky write lock for shadow register 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR40 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR40 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK41" description="sticky write lock for shadow register 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR41 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR41 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK42" description="sticky write lock for shadow register 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR42 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR42 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK43" description="sticky write lock for shadow register 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR43 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR43 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK44" description="sticky write lock for shadow register 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR44 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR44 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK45" description="sticky write lock for shadow register 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR45 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR45 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK46" description="sticky write lock for shadow register 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR46 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR46 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK47" description="sticky write lock for shadow register 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR47 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR47 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK48" description="sticky write lock for shadow register 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR48 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR48 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK49" description="sticky write lock for shadow register 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR49 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR49 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK50" description="sticky write lock for shadow register 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR50 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR50 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK51" description="sticky write lock for shadow register 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR51 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR51 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK52" description="sticky write lock for shadow register 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR52 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR52 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK53" description="sticky write lock for shadow register 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR53 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR53 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK54" description="sticky write lock for shadow register 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR54 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR54 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK55" description="sticky write lock for shadow register 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR55 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR55 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK56" description="sticky write lock for shadow register 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR56 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR56 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK57" description="sticky write lock for shadow register 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR57 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR57 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK58" description="sticky write lock for shadow register 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR58 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR58 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK59" description="sticky write lock for shadow register 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR59 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR59 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK60" description="sticky write lock for shadow register 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR60 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR60 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK61" description="sticky write lock for shadow register 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR61 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR61 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK62" description="sticky write lock for shadow register 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR62 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR62 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK63" description="sticky write lock for shadow register 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR63 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR63 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK2" description="BSEC sticky write lock register 2" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK64" description="sticky write lock for shadow register 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR64 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR64 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK65" description="sticky write lock for shadow register 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR65 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR65 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK66" description="sticky write lock for shadow register 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR66 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR66 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK67" description="sticky write lock for shadow register 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR67 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR67 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK68" description="sticky write lock for shadow register 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR68 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR68 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK69" description="sticky write lock for shadow register 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR69 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR69 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK70" description="sticky write lock for shadow register 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR70 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR70 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK71" description="sticky write lock for shadow register 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR71 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR71 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK72" description="sticky write lock for shadow register 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR72 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR72 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK73" description="sticky write lock for shadow register 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR73 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR73 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK74" description="sticky write lock for shadow register 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR74 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR74 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK75" description="sticky write lock for shadow register 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR75 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR75 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK76" description="sticky write lock for shadow register 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR76 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR76 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK77" description="sticky write lock for shadow register 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR77 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR77 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK78" description="sticky write lock for shadow register 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR78 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR78 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK79" description="sticky write lock for shadow register 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR79 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR79 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK80" description="sticky write lock for shadow register 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR80 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR80 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK81" description="sticky write lock for shadow register 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR81 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR81 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK82" description="sticky write lock for shadow register 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR82 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR82 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK83" description="sticky write lock for shadow register 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR83 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR83 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK84" description="sticky write lock for shadow register 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR84 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR84 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK85" description="sticky write lock for shadow register 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR85 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR85 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK86" description="sticky write lock for shadow register 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR86 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR86 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK87" description="sticky write lock for shadow register 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR87 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR87 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK88" description="sticky write lock for shadow register 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR88 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR88 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK89" description="sticky write lock for shadow register 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR89 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR89 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK90" description="sticky write lock for shadow register 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR90 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR90 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK91" description="sticky write lock for shadow register 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR91 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR91 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK92" description="sticky write lock for shadow register 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR92 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR92 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK93" description="sticky write lock for shadow register 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR93 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR93 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK94" description="sticky write lock for shadow register 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR94 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR94 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK95" description="sticky write lock for shadow register 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR95 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR95 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK3" description="BSEC sticky write lock register 3" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK96" description="sticky write lock for shadow register 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR96 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR96 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK97" description="sticky write lock for shadow register 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR97 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR97 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK98" description="sticky write lock for shadow register 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR98 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR98 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK99" description="sticky write lock for shadow register 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR99 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR99 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK100" description="sticky write lock for shadow register 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR100 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR100 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK101" description="sticky write lock for shadow register 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR101 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR101 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK102" description="sticky write lock for shadow register 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR102 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR102 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK103" description="sticky write lock for shadow register 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR103 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR103 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK104" description="sticky write lock for shadow register 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR104 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR104 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK105" description="sticky write lock for shadow register 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR105 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR105 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK106" description="sticky write lock for shadow register 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR106 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR106 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK107" description="sticky write lock for shadow register 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR107 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR107 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK108" description="sticky write lock for shadow register 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR108 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR108 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK109" description="sticky write lock for shadow register 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR109 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR109 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK110" description="sticky write lock for shadow register 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR110 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR110 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK111" description="sticky write lock for shadow register 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR111 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR111 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK112" description="sticky write lock for shadow register 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR112 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR112 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK113" description="sticky write lock for shadow register 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR113 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR113 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK114" description="sticky write lock for shadow register 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR114 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR114 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK115" description="sticky write lock for shadow register 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR115 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR115 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK116" description="sticky write lock for shadow register 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR116 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR116 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK117" description="sticky write lock for shadow register 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR117 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR117 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK118" description="sticky write lock for shadow register 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR118 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR118 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK119" description="sticky write lock for shadow register 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR119 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR119 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK120" description="sticky write lock for shadow register 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR120 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR120 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK121" description="sticky write lock for shadow register 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR121 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR121 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK122" description="sticky write lock for shadow register 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR122 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR122 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK123" description="sticky write lock for shadow register 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR123 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR123 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK124" description="sticky write lock for shadow register 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR124 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR124 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK125" description="sticky write lock for shadow register 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR125 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR125 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK126" description="sticky write lock for shadow register 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR126 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR126 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK127" description="sticky write lock for shadow register 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR127 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR127 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK4" description="BSEC sticky write lock register 4" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK128" description="sticky write lock for shadow register 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR128 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR128 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK129" description="sticky write lock for shadow register 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR129 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR129 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK130" description="sticky write lock for shadow register 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR130 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR130 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK131" description="sticky write lock for shadow register 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR131 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR131 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK132" description="sticky write lock for shadow register 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR132 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR132 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK133" description="sticky write lock for shadow register 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR133 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR133 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK134" description="sticky write lock for shadow register 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR134 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR134 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK135" description="sticky write lock for shadow register 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR135 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR135 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK136" description="sticky write lock for shadow register 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR136 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR136 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK137" description="sticky write lock for shadow register 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR137 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR137 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK138" description="sticky write lock for shadow register 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR138 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR138 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK139" description="sticky write lock for shadow register 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR139 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR139 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK140" description="sticky write lock for shadow register 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR140 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR140 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK141" description="sticky write lock for shadow register 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR141 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR141 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK142" description="sticky write lock for shadow register 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR142 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR142 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK143" description="sticky write lock for shadow register 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR143 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR143 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK144" description="sticky write lock for shadow register 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR144 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR144 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK145" description="sticky write lock for shadow register 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR145 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR145 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK146" description="sticky write lock for shadow register 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR146 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR146 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK147" description="sticky write lock for shadow register 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR147 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR147 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK148" description="sticky write lock for shadow register 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR148 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR148 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK149" description="sticky write lock for shadow register 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR149 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR149 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK150" description="sticky write lock for shadow register 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR150 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR150 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK151" description="sticky write lock for shadow register 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR151 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR151 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK152" description="sticky write lock for shadow register 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR152 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR152 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK153" description="sticky write lock for shadow register 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR153 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR153 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK154" description="sticky write lock for shadow register 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR154 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR154 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK155" description="sticky write lock for shadow register 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR155 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR155 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK156" description="sticky write lock for shadow register 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR156 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR156 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK157" description="sticky write lock for shadow register 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR157 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR157 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK158" description="sticky write lock for shadow register 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR158 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR158 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK159" description="sticky write lock for shadow register 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR159 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR159 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK5" description="BSEC sticky write lock register 5" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK160" description="sticky write lock for shadow register 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR160 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR160 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK161" description="sticky write lock for shadow register 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR161 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR161 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK162" description="sticky write lock for shadow register 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR162 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR162 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK163" description="sticky write lock for shadow register 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR163 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR163 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK164" description="sticky write lock for shadow register 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR164 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR164 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK165" description="sticky write lock for shadow register 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR165 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR165 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK166" description="sticky write lock for shadow register 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR166 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR166 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK167" description="sticky write lock for shadow register 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR167 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR167 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK168" description="sticky write lock for shadow register 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR168 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR168 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK169" description="sticky write lock for shadow register 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR169 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR169 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK170" description="sticky write lock for shadow register 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR170 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR170 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK171" description="sticky write lock for shadow register 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR171 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR171 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK172" description="sticky write lock for shadow register 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR172 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR172 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK173" description="sticky write lock for shadow register 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR173 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR173 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK174" description="sticky write lock for shadow register 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR174 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR174 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK175" description="sticky write lock for shadow register 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR175 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR175 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK176" description="sticky write lock for shadow register 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR176 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR176 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK177" description="sticky write lock for shadow register 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR177 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR177 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK178" description="sticky write lock for shadow register 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR178 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR178 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK179" description="sticky write lock for shadow register 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR179 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR179 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK180" description="sticky write lock for shadow register 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR180 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR180 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK181" description="sticky write lock for shadow register 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR181 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR181 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK182" description="sticky write lock for shadow register 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR182 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR182 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK183" description="sticky write lock for shadow register 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR183 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR183 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK184" description="sticky write lock for shadow register 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR184 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR184 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK185" description="sticky write lock for shadow register 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR185 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR185 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK186" description="sticky write lock for shadow register 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR186 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR186 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK187" description="sticky write lock for shadow register 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR187 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR187 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK188" description="sticky write lock for shadow register 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR188 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR188 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK189" description="sticky write lock for shadow register 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR189 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR189 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK190" description="sticky write lock for shadow register 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR190 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR190 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK191" description="sticky write lock for shadow register 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR191 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR191 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK6" description="BSEC sticky write lock register 6" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK192" description="sticky write lock for shadow register 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR192 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR192 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK193" description="sticky write lock for shadow register 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR193 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR193 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK194" description="sticky write lock for shadow register 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR194 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR194 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK195" description="sticky write lock for shadow register 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR195 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR195 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK196" description="sticky write lock for shadow register 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR196 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR196 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK197" description="sticky write lock for shadow register 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR197 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR197 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK198" description="sticky write lock for shadow register 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR198 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR198 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK199" description="sticky write lock for shadow register 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR199 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR199 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK200" description="sticky write lock for shadow register 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR200 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR200 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK201" description="sticky write lock for shadow register 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR201 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR201 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK202" description="sticky write lock for shadow register 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR202 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR202 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK203" description="sticky write lock for shadow register 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR203 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR203 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK204" description="sticky write lock for shadow register 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR204 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR204 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK205" description="sticky write lock for shadow register 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR205 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR205 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK206" description="sticky write lock for shadow register 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR206 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR206 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK207" description="sticky write lock for shadow register 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR207 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR207 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK208" description="sticky write lock for shadow register 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR208 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR208 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK209" description="sticky write lock for shadow register 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR209 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR209 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK210" description="sticky write lock for shadow register 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR210 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR210 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK211" description="sticky write lock for shadow register 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR211 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR211 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK212" description="sticky write lock for shadow register 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR212 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR212 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK213" description="sticky write lock for shadow register 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR213 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR213 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK214" description="sticky write lock for shadow register 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR214 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR214 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK215" description="sticky write lock for shadow register 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR215 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR215 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK216" description="sticky write lock for shadow register 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR216 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR216 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK217" description="sticky write lock for shadow register 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR217 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR217 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK218" description="sticky write lock for shadow register 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR218 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR218 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK219" description="sticky write lock for shadow register 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR219 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR219 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK220" description="sticky write lock for shadow register 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR220 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR220 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK221" description="sticky write lock for shadow register 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR221 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR221 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK222" description="sticky write lock for shadow register 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR222 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR222 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK223" description="sticky write lock for shadow register 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR223 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR223 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK7" description="BSEC sticky write lock register 7" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK224" description="sticky write lock for shadow register 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR224 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR224 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK225" description="sticky write lock for shadow register 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR225 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR225 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK226" description="sticky write lock for shadow register 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR226 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR226 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK227" description="sticky write lock for shadow register 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR227 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR227 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK228" description="sticky write lock for shadow register 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR228 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR228 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK229" description="sticky write lock for shadow register 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR229 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR229 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK230" description="sticky write lock for shadow register 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR230 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR230 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK231" description="sticky write lock for shadow register 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR231 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR231 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK232" description="sticky write lock for shadow register 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR232 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR232 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK233" description="sticky write lock for shadow register 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR233 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR233 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK234" description="sticky write lock for shadow register 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR234 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR234 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK235" description="sticky write lock for shadow register 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR235 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR235 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK236" description="sticky write lock for shadow register 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR236 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR236 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK237" description="sticky write lock for shadow register 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR237 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR237 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK238" description="sticky write lock for shadow register 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR238 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR238 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK239" description="sticky write lock for shadow register 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR239 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR239 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK240" description="sticky write lock for shadow register 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR240 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR240 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK241" description="sticky write lock for shadow register 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR241 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR241 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK242" description="sticky write lock for shadow register 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR242 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR242 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK243" description="sticky write lock for shadow register 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR243 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR243 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK244" description="sticky write lock for shadow register 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR244 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR244 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK245" description="sticky write lock for shadow register 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR245 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR245 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK246" description="sticky write lock for shadow register 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR246 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR246 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK247" description="sticky write lock for shadow register 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR247 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR247 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK248" description="sticky write lock for shadow register 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR248 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR248 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK249" description="sticky write lock for shadow register 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR249 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR249 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK250" description="sticky write lock for shadow register 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR250 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR250 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK251" description="sticky write lock for shadow register 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR251 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR251 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK252" description="sticky write lock for shadow register 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR252 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR252 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK253" description="sticky write lock for shadow register 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR253 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR253 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK254" description="sticky write lock for shadow register 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR254 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR254 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK255" description="sticky write lock for shadow register 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR255 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR255 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK8" description="BSEC sticky write lock register 8" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK256" description="sticky write lock for shadow register 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR256 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR256 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK257" description="sticky write lock for shadow register 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR257 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR257 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK258" description="sticky write lock for shadow register 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR258 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR258 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK259" description="sticky write lock for shadow register 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR259 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR259 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK260" description="sticky write lock for shadow register 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR260 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR260 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK261" description="sticky write lock for shadow register 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR261 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR261 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK262" description="sticky write lock for shadow register 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR262 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR262 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK263" description="sticky write lock for shadow register 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR263 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR263 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK264" description="sticky write lock for shadow register 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR264 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR264 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK265" description="sticky write lock for shadow register 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR265 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR265 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK266" description="sticky write lock for shadow register 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR266 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR266 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK267" description="sticky write lock for shadow register 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR267 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR267 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK268" description="sticky write lock for shadow register 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR268 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR268 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK269" description="sticky write lock for shadow register 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR269 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR269 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK270" description="sticky write lock for shadow register 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR270 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR270 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK271" description="sticky write lock for shadow register 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR271 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR271 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK272" description="sticky write lock for shadow register 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR272 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR272 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK273" description="sticky write lock for shadow register 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR273 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR273 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK274" description="sticky write lock for shadow register 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR274 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR274 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK275" description="sticky write lock for shadow register 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR275 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR275 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK276" description="sticky write lock for shadow register 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR276 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR276 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK277" description="sticky write lock for shadow register 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR277 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR277 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK278" description="sticky write lock for shadow register 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR278 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR278 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK279" description="sticky write lock for shadow register 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR279 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR279 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK280" description="sticky write lock for shadow register 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR280 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR280 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK281" description="sticky write lock for shadow register 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR281 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR281 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK282" description="sticky write lock for shadow register 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR282 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR282 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK283" description="sticky write lock for shadow register 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR283 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR283 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK284" description="sticky write lock for shadow register 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR284 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR284 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK285" description="sticky write lock for shadow register 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR285 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR285 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK286" description="sticky write lock for shadow register 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR286 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR286 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK287" description="sticky write lock for shadow register 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR287 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR287 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK9" description="BSEC sticky write lock register 9" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK288" description="sticky write lock for shadow register 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR288 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR288 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK289" description="sticky write lock for shadow register 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR289 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR289 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK290" description="sticky write lock for shadow register 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR290 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR290 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK291" description="sticky write lock for shadow register 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR291 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR291 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK292" description="sticky write lock for shadow register 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR292 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR292 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK293" description="sticky write lock for shadow register 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR293 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR293 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK294" description="sticky write lock for shadow register 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR294 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR294 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK295" description="sticky write lock for shadow register 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR295 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR295 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK296" description="sticky write lock for shadow register 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR296 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR296 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK297" description="sticky write lock for shadow register 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR297 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR297 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK298" description="sticky write lock for shadow register 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR298 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR298 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK299" description="sticky write lock for shadow register 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR299 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR299 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK300" description="sticky write lock for shadow register 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR300 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR300 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK301" description="sticky write lock for shadow register 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR301 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR301 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK302" description="sticky write lock for shadow register 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR302 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR302 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK303" description="sticky write lock for shadow register 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR303 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR303 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK304" description="sticky write lock for shadow register 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR304 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR304 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK305" description="sticky write lock for shadow register 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR305 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR305 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK306" description="sticky write lock for shadow register 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR306 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR306 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK307" description="sticky write lock for shadow register 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR307 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR307 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK308" description="sticky write lock for shadow register 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR308 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR308 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK309" description="sticky write lock for shadow register 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR309 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR309 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK310" description="sticky write lock for shadow register 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR310 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR310 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK311" description="sticky write lock for shadow register 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR311 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR311 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK312" description="sticky write lock for shadow register 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR312 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR312 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK313" description="sticky write lock for shadow register 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR313 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR313 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK314" description="sticky write lock for shadow register 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR314 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR314 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK315" description="sticky write lock for shadow register 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR315 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR315 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK316" description="sticky write lock for shadow register 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR316 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR316 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK317" description="sticky write lock for shadow register 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR317 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR317 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK318" description="sticky write lock for shadow register 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR318 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR318 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK319" description="sticky write lock for shadow register 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR319 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR319 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK10" description="BSEC sticky write lock register 10" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK320" description="sticky write lock for shadow register 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR320 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR320 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK321" description="sticky write lock for shadow register 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR321 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR321 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK322" description="sticky write lock for shadow register 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR322 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR322 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK323" description="sticky write lock for shadow register 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR323 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR323 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK324" description="sticky write lock for shadow register 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR324 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR324 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK325" description="sticky write lock for shadow register 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR325 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR325 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK326" description="sticky write lock for shadow register 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR326 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR326 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK327" description="sticky write lock for shadow register 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR327 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR327 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK328" description="sticky write lock for shadow register 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR328 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR328 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK329" description="sticky write lock for shadow register 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR329 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR329 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK330" description="sticky write lock for shadow register 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR330 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR330 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK331" description="sticky write lock for shadow register 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR331 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR331 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK332" description="sticky write lock for shadow register 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR332 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR332 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK333" description="sticky write lock for shadow register 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR333 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR333 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK334" description="sticky write lock for shadow register 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR334 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR334 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK335" description="sticky write lock for shadow register 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR335 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR335 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK336" description="sticky write lock for shadow register 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR336 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR336 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK337" description="sticky write lock for shadow register 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR337 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR337 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK338" description="sticky write lock for shadow register 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR338 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR338 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK339" description="sticky write lock for shadow register 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR339 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR339 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK340" description="sticky write lock for shadow register 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR340 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR340 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK341" description="sticky write lock for shadow register 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR341 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR341 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK342" description="sticky write lock for shadow register 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR342 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR342 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK343" description="sticky write lock for shadow register 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR343 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR343 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK344" description="sticky write lock for shadow register 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR344 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR344 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK345" description="sticky write lock for shadow register 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR345 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR345 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK346" description="sticky write lock for shadow register 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR346 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR346 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK347" description="sticky write lock for shadow register 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR347 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR347 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK348" description="sticky write lock for shadow register 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR348 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR348 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK349" description="sticky write lock for shadow register 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR349 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR349 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK350" description="sticky write lock for shadow register 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR350 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR350 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK351" description="sticky write lock for shadow register 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR351 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR351 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK11" description="BSEC sticky write lock register 11" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK352" description="sticky write lock for shadow register 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR352 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR352 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK353" description="sticky write lock for shadow register 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR353 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR353 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK354" description="sticky write lock for shadow register 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR354 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR354 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK355" description="sticky write lock for shadow register 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR355 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR355 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK356" description="sticky write lock for shadow register 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR356 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR356 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK357" description="sticky write lock for shadow register 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR357 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR357 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK358" description="sticky write lock for shadow register 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR358 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR358 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK359" description="sticky write lock for shadow register 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR359 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR359 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK360" description="sticky write lock for shadow register 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR360 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR360 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK361" description="sticky write lock for shadow register 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR361 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR361 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK362" description="sticky write lock for shadow register 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR362 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR362 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK363" description="sticky write lock for shadow register 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR363 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR363 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK364" description="sticky write lock for shadow register 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR364 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR364 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK365" description="sticky write lock for shadow register 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR365 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR365 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK366" description="sticky write lock for shadow register 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR366 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR366 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK367" description="sticky write lock for shadow register 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR367 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR367 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK368" description="sticky write lock for shadow register 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR368 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR368 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK369" description="sticky write lock for shadow register 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR369 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR369 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK370" description="sticky write lock for shadow register 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR370 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR370 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK371" description="sticky write lock for shadow register 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR371 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR371 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK372" description="sticky write lock for shadow register 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR372 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR372 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK373" description="sticky write lock for shadow register 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR373 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR373 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK374" description="sticky write lock for shadow register 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR374 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR374 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK375" description="sticky write lock for shadow register 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR375 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR375 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK376" description="sticky write lock for shadow register 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR376 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR376 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK377" description="sticky write lock for shadow register 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR377 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR377 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK378" description="sticky write lock for shadow register 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR378 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR378 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK379" description="sticky write lock for shadow register 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR379 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR379 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK380" description="sticky write lock for shadow register 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR380 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR380 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK381" description="sticky write lock for shadow register 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR381 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR381 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK382" description="sticky write lock for shadow register 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR382 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR382 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK383" description="sticky write lock for shadow register 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR383 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR383 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK0" description="BSEC sticky reload lock register 0" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK0" description="sticky reload lock for fuse word 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 0 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 0 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK1" description="sticky reload lock for fuse word 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 1 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 1 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK2" description="sticky reload lock for fuse word 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 2 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 2 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK3" description="sticky reload lock for fuse word 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 3 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 3 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK4" description="sticky reload lock for fuse word 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 4 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 4 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK5" description="sticky reload lock for fuse word 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 5 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 5 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK6" description="sticky reload lock for fuse word 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 6 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 6 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK7" description="sticky reload lock for fuse word 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 7 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 7 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK8" description="sticky reload lock for fuse word 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 8 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 8 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK9" description="sticky reload lock for fuse word 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 9 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 9 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK10" description="sticky reload lock for fuse word 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 10 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 10 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK11" description="sticky reload lock for fuse word 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 11 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 11 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK12" description="sticky reload lock for fuse word 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 12 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 12 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK13" description="sticky reload lock for fuse word 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 13 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 13 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK14" description="sticky reload lock for fuse word 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 14 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 14 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK15" description="sticky reload lock for fuse word 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 15 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 15 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK16" description="sticky reload lock for fuse word 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 16 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 16 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK17" description="sticky reload lock for fuse word 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 17 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 17 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK18" description="sticky reload lock for fuse word 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 18 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 18 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK19" description="sticky reload lock for fuse word 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 19 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 19 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK20" description="sticky reload lock for fuse word 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 20 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 20 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK21" description="sticky reload lock for fuse word 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 21 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 21 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK22" description="sticky reload lock for fuse word 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 22 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 22 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK23" description="sticky reload lock for fuse word 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 23 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 23 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK24" description="sticky reload lock for fuse word 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 24 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 24 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK25" description="sticky reload lock for fuse word 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 25 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 25 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK26" description="sticky reload lock for fuse word 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 26 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 26 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK27" description="sticky reload lock for fuse word 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 27 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 27 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK28" description="sticky reload lock for fuse word 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 28 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 28 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK29" description="sticky reload lock for fuse word 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 29 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 29 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK30" description="sticky reload lock for fuse word 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 30 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 30 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK31" description="sticky reload lock for fuse word 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 31 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 31 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK1" description="BSEC sticky reload lock register 1" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK32" description="sticky reload lock for fuse word 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 32 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 32 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK33" description="sticky reload lock for fuse word 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 33 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 33 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK34" description="sticky reload lock for fuse word 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 34 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 34 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK35" description="sticky reload lock for fuse word 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 35 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 35 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK36" description="sticky reload lock for fuse word 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 36 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 36 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK37" description="sticky reload lock for fuse word 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 37 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 37 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK38" description="sticky reload lock for fuse word 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 38 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 38 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK39" description="sticky reload lock for fuse word 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 39 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 39 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK40" description="sticky reload lock for fuse word 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 40 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 40 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK41" description="sticky reload lock for fuse word 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 41 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 41 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK42" description="sticky reload lock for fuse word 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 42 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 42 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK43" description="sticky reload lock for fuse word 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 43 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 43 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK44" description="sticky reload lock for fuse word 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 44 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 44 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK45" description="sticky reload lock for fuse word 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 45 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 45 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK46" description="sticky reload lock for fuse word 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 46 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 46 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK47" description="sticky reload lock for fuse word 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 47 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 47 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK48" description="sticky reload lock for fuse word 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 48 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 48 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK49" description="sticky reload lock for fuse word 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 49 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 49 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK50" description="sticky reload lock for fuse word 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 50 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 50 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK51" description="sticky reload lock for fuse word 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 51 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 51 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK52" description="sticky reload lock for fuse word 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 52 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 52 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK53" description="sticky reload lock for fuse word 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 53 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 53 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK54" description="sticky reload lock for fuse word 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 54 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 54 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK55" description="sticky reload lock for fuse word 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 55 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 55 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK56" description="sticky reload lock for fuse word 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 56 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 56 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK57" description="sticky reload lock for fuse word 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 57 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 57 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK58" description="sticky reload lock for fuse word 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 58 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 58 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK59" description="sticky reload lock for fuse word 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 59 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 59 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK60" description="sticky reload lock for fuse word 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 60 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 60 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK61" description="sticky reload lock for fuse word 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 61 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 61 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK62" description="sticky reload lock for fuse word 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 62 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 62 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK63" description="sticky reload lock for fuse word 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 63 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 63 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK2" description="BSEC sticky reload lock register 2" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK64" description="sticky reload lock for fuse word 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 64 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 64 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK65" description="sticky reload lock for fuse word 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 65 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 65 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK66" description="sticky reload lock for fuse word 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 66 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 66 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK67" description="sticky reload lock for fuse word 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 67 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 67 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK68" description="sticky reload lock for fuse word 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 68 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 68 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK69" description="sticky reload lock for fuse word 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 69 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 69 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK70" description="sticky reload lock for fuse word 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 70 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 70 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK71" description="sticky reload lock for fuse word 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 71 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 71 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK72" description="sticky reload lock for fuse word 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 72 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 72 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK73" description="sticky reload lock for fuse word 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 73 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 73 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK74" description="sticky reload lock for fuse word 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 74 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 74 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK75" description="sticky reload lock for fuse word 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 75 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 75 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK76" description="sticky reload lock for fuse word 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 76 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 76 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK77" description="sticky reload lock for fuse word 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 77 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 77 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK78" description="sticky reload lock for fuse word 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 78 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 78 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK79" description="sticky reload lock for fuse word 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 79 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 79 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK80" description="sticky reload lock for fuse word 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 80 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 80 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK81" description="sticky reload lock for fuse word 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 81 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 81 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK82" description="sticky reload lock for fuse word 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 82 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 82 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK83" description="sticky reload lock for fuse word 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 83 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 83 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK84" description="sticky reload lock for fuse word 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 84 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 84 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK85" description="sticky reload lock for fuse word 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 85 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 85 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK86" description="sticky reload lock for fuse word 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 86 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 86 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK87" description="sticky reload lock for fuse word 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 87 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 87 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK88" description="sticky reload lock for fuse word 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 88 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 88 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK89" description="sticky reload lock for fuse word 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 89 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 89 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK90" description="sticky reload lock for fuse word 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 90 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 90 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK91" description="sticky reload lock for fuse word 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 91 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 91 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK92" description="sticky reload lock for fuse word 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 92 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 92 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK93" description="sticky reload lock for fuse word 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 93 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 93 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK94" description="sticky reload lock for fuse word 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 94 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 94 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK95" description="sticky reload lock for fuse word 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 95 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 95 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK3" description="BSEC sticky reload lock register 3" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK96" description="sticky reload lock for fuse word 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 96 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 96 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK97" description="sticky reload lock for fuse word 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 97 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 97 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK98" description="sticky reload lock for fuse word 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 98 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 98 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK99" description="sticky reload lock for fuse word 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 99 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 99 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK100" description="sticky reload lock for fuse word 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 100 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 100 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK101" description="sticky reload lock for fuse word 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 101 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 101 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK102" description="sticky reload lock for fuse word 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 102 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 102 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK103" description="sticky reload lock for fuse word 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 103 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 103 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK104" description="sticky reload lock for fuse word 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 104 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 104 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK105" description="sticky reload lock for fuse word 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 105 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 105 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK106" description="sticky reload lock for fuse word 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 106 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 106 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK107" description="sticky reload lock for fuse word 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 107 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 107 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK108" description="sticky reload lock for fuse word 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 108 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 108 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK109" description="sticky reload lock for fuse word 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 109 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 109 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK110" description="sticky reload lock for fuse word 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 110 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 110 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK111" description="sticky reload lock for fuse word 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 111 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 111 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK112" description="sticky reload lock for fuse word 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 112 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 112 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK113" description="sticky reload lock for fuse word 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 113 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 113 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK114" description="sticky reload lock for fuse word 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 114 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 114 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK115" description="sticky reload lock for fuse word 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 115 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 115 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK116" description="sticky reload lock for fuse word 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 116 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 116 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK117" description="sticky reload lock for fuse word 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 117 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 117 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK118" description="sticky reload lock for fuse word 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 118 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 118 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK119" description="sticky reload lock for fuse word 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 119 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 119 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK120" description="sticky reload lock for fuse word 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 120 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 120 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK121" description="sticky reload lock for fuse word 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 121 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 121 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK122" description="sticky reload lock for fuse word 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 122 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 122 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK123" description="sticky reload lock for fuse word 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 123 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 123 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK124" description="sticky reload lock for fuse word 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 124 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 124 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK125" description="sticky reload lock for fuse word 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 125 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 125 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK126" description="sticky reload lock for fuse word 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 126 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 126 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK127" description="sticky reload lock for fuse word 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 127 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 127 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK4" description="BSEC sticky reload lock register 4" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK128" description="sticky reload lock for fuse word 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 128 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 128 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK129" description="sticky reload lock for fuse word 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 129 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 129 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK130" description="sticky reload lock for fuse word 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 130 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 130 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK131" description="sticky reload lock for fuse word 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 131 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 131 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK132" description="sticky reload lock for fuse word 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 132 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 132 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK133" description="sticky reload lock for fuse word 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 133 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 133 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK134" description="sticky reload lock for fuse word 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 134 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 134 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK135" description="sticky reload lock for fuse word 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 135 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 135 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK136" description="sticky reload lock for fuse word 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 136 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 136 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK137" description="sticky reload lock for fuse word 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 137 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 137 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK138" description="sticky reload lock for fuse word 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 138 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 138 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK139" description="sticky reload lock for fuse word 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 139 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 139 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK140" description="sticky reload lock for fuse word 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 140 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 140 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK141" description="sticky reload lock for fuse word 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 141 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 141 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK142" description="sticky reload lock for fuse word 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 142 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 142 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK143" description="sticky reload lock for fuse word 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 143 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 143 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK144" description="sticky reload lock for fuse word 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 144 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 144 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK145" description="sticky reload lock for fuse word 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 145 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 145 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK146" description="sticky reload lock for fuse word 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 146 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 146 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK147" description="sticky reload lock for fuse word 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 147 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 147 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK148" description="sticky reload lock for fuse word 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 148 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 148 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK149" description="sticky reload lock for fuse word 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 149 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 149 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK150" description="sticky reload lock for fuse word 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 150 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 150 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK151" description="sticky reload lock for fuse word 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 151 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 151 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK152" description="sticky reload lock for fuse word 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 152 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 152 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK153" description="sticky reload lock for fuse word 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 153 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 153 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK154" description="sticky reload lock for fuse word 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 154 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 154 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK155" description="sticky reload lock for fuse word 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 155 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 155 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK156" description="sticky reload lock for fuse word 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 156 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 156 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK157" description="sticky reload lock for fuse word 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 157 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 157 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK158" description="sticky reload lock for fuse word 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 158 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 158 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK159" description="sticky reload lock for fuse word 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 159 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 159 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK5" description="BSEC sticky reload lock register 5" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK160" description="sticky reload lock for fuse word 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 160 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 160 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK161" description="sticky reload lock for fuse word 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 161 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 161 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK162" description="sticky reload lock for fuse word 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 162 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 162 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK163" description="sticky reload lock for fuse word 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 163 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 163 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK164" description="sticky reload lock for fuse word 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 164 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 164 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK165" description="sticky reload lock for fuse word 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 165 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 165 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK166" description="sticky reload lock for fuse word 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 166 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 166 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK167" description="sticky reload lock for fuse word 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 167 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 167 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK168" description="sticky reload lock for fuse word 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 168 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 168 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK169" description="sticky reload lock for fuse word 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 169 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 169 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK170" description="sticky reload lock for fuse word 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 170 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 170 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK171" description="sticky reload lock for fuse word 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 171 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 171 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK172" description="sticky reload lock for fuse word 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 172 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 172 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK173" description="sticky reload lock for fuse word 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 173 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 173 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK174" description="sticky reload lock for fuse word 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 174 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 174 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK175" description="sticky reload lock for fuse word 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 175 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 175 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK176" description="sticky reload lock for fuse word 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 176 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 176 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK177" description="sticky reload lock for fuse word 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 177 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 177 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK178" description="sticky reload lock for fuse word 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 178 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 178 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK179" description="sticky reload lock for fuse word 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 179 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 179 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK180" description="sticky reload lock for fuse word 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 180 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 180 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK181" description="sticky reload lock for fuse word 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 181 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 181 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK182" description="sticky reload lock for fuse word 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 182 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 182 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK183" description="sticky reload lock for fuse word 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 183 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 183 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK184" description="sticky reload lock for fuse word 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 184 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 184 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK185" description="sticky reload lock for fuse word 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 185 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 185 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK186" description="sticky reload lock for fuse word 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 186 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 186 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK187" description="sticky reload lock for fuse word 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 187 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 187 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK188" description="sticky reload lock for fuse word 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 188 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 188 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK189" description="sticky reload lock for fuse word 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 189 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 189 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK190" description="sticky reload lock for fuse word 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 190 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 190 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK191" description="sticky reload lock for fuse word 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 191 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 191 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK6" description="BSEC sticky reload lock register 6" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK192" description="sticky reload lock for fuse word 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 192 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 192 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK193" description="sticky reload lock for fuse word 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 193 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 193 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK194" description="sticky reload lock for fuse word 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 194 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 194 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK195" description="sticky reload lock for fuse word 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 195 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 195 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK196" description="sticky reload lock for fuse word 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 196 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 196 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK197" description="sticky reload lock for fuse word 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 197 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 197 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK198" description="sticky reload lock for fuse word 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 198 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 198 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK199" description="sticky reload lock for fuse word 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 199 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 199 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK200" description="sticky reload lock for fuse word 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 200 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 200 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK201" description="sticky reload lock for fuse word 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 201 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 201 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK202" description="sticky reload lock for fuse word 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 202 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 202 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK203" description="sticky reload lock for fuse word 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 203 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 203 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK204" description="sticky reload lock for fuse word 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 204 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 204 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK205" description="sticky reload lock for fuse word 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 205 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 205 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK206" description="sticky reload lock for fuse word 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 206 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 206 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK207" description="sticky reload lock for fuse word 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 207 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 207 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK208" description="sticky reload lock for fuse word 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 208 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 208 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK209" description="sticky reload lock for fuse word 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 209 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 209 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK210" description="sticky reload lock for fuse word 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 210 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 210 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK211" description="sticky reload lock for fuse word 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 211 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 211 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK212" description="sticky reload lock for fuse word 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 212 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 212 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK213" description="sticky reload lock for fuse word 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 213 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 213 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK214" description="sticky reload lock for fuse word 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 214 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 214 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK215" description="sticky reload lock for fuse word 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 215 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 215 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK216" description="sticky reload lock for fuse word 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 216 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 216 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK217" description="sticky reload lock for fuse word 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 217 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 217 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK218" description="sticky reload lock for fuse word 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 218 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 218 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK219" description="sticky reload lock for fuse word 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 219 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 219 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK220" description="sticky reload lock for fuse word 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 220 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 220 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK221" description="sticky reload lock for fuse word 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 221 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 221 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK222" description="sticky reload lock for fuse word 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 222 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 222 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK223" description="sticky reload lock for fuse word 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 223 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 223 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK7" description="BSEC sticky reload lock register 7" start="+0x89C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK224" description="sticky reload lock for fuse word 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 224 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 224 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK225" description="sticky reload lock for fuse word 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 225 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 225 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK226" description="sticky reload lock for fuse word 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 226 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 226 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK227" description="sticky reload lock for fuse word 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 227 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 227 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK228" description="sticky reload lock for fuse word 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 228 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 228 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK229" description="sticky reload lock for fuse word 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 229 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 229 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK230" description="sticky reload lock for fuse word 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 230 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 230 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK231" description="sticky reload lock for fuse word 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 231 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 231 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK232" description="sticky reload lock for fuse word 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 232 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 232 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK233" description="sticky reload lock for fuse word 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 233 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 233 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK234" description="sticky reload lock for fuse word 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 234 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 234 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK235" description="sticky reload lock for fuse word 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 235 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 235 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK236" description="sticky reload lock for fuse word 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 236 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 236 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK237" description="sticky reload lock for fuse word 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 237 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 237 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK238" description="sticky reload lock for fuse word 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 238 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 238 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK239" description="sticky reload lock for fuse word 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 239 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 239 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK240" description="sticky reload lock for fuse word 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 240 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 240 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK241" description="sticky reload lock for fuse word 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 241 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 241 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK242" description="sticky reload lock for fuse word 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 242 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 242 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK243" description="sticky reload lock for fuse word 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 243 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 243 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK244" description="sticky reload lock for fuse word 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 244 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 244 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK245" description="sticky reload lock for fuse word 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 245 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 245 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK246" description="sticky reload lock for fuse word 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 246 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 246 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK247" description="sticky reload lock for fuse word 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 247 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 247 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK248" description="sticky reload lock for fuse word 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 248 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 248 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK249" description="sticky reload lock for fuse word 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 249 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 249 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK250" description="sticky reload lock for fuse word 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 250 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 250 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK251" description="sticky reload lock for fuse word 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 251 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 251 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK252" description="sticky reload lock for fuse word 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 252 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 252 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK253" description="sticky reload lock for fuse word 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 253 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 253 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK254" description="sticky reload lock for fuse word 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 254 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 254 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK255" description="sticky reload lock for fuse word 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 255 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 255 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK8" description="BSEC sticky reload lock register 8" start="+0x8A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK256" description="sticky reload lock for fuse word 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 256 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 256 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK257" description="sticky reload lock for fuse word 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 257 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 257 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK258" description="sticky reload lock for fuse word 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 258 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 258 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK259" description="sticky reload lock for fuse word 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 259 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 259 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK260" description="sticky reload lock for fuse word 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 260 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 260 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK261" description="sticky reload lock for fuse word 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 261 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 261 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK262" description="sticky reload lock for fuse word 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 262 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 262 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK263" description="sticky reload lock for fuse word 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 263 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 263 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK264" description="sticky reload lock for fuse word 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 264 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 264 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK265" description="sticky reload lock for fuse word 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 265 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 265 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK266" description="sticky reload lock for fuse word 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 266 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 266 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK267" description="sticky reload lock for fuse word 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 267 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 267 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK268" description="sticky reload lock for fuse word 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 268 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 268 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK269" description="sticky reload lock for fuse word 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 269 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 269 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK270" description="sticky reload lock for fuse word 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 270 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 270 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK271" description="sticky reload lock for fuse word 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 271 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 271 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK272" description="sticky reload lock for fuse word 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 272 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 272 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK273" description="sticky reload lock for fuse word 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 273 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 273 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK274" description="sticky reload lock for fuse word 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 274 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 274 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK275" description="sticky reload lock for fuse word 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 275 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 275 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK276" description="sticky reload lock for fuse word 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 276 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 276 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK277" description="sticky reload lock for fuse word 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 277 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 277 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK278" description="sticky reload lock for fuse word 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 278 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 278 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK279" description="sticky reload lock for fuse word 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 279 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 279 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK280" description="sticky reload lock for fuse word 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 280 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 280 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK281" description="sticky reload lock for fuse word 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 281 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 281 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK282" description="sticky reload lock for fuse word 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 282 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 282 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK283" description="sticky reload lock for fuse word 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 283 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 283 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK284" description="sticky reload lock for fuse word 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 284 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 284 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK285" description="sticky reload lock for fuse word 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 285 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 285 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK286" description="sticky reload lock for fuse word 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 286 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 286 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK287" description="sticky reload lock for fuse word 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 287 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 287 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK9" description="BSEC sticky reload lock register 9" start="+0x8A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK288" description="sticky reload lock for fuse word 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 288 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 288 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK289" description="sticky reload lock for fuse word 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 289 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 289 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK290" description="sticky reload lock for fuse word 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 290 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 290 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK291" description="sticky reload lock for fuse word 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 291 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 291 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK292" description="sticky reload lock for fuse word 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 292 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 292 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK293" description="sticky reload lock for fuse word 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 293 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 293 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK294" description="sticky reload lock for fuse word 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 294 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 294 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK295" description="sticky reload lock for fuse word 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 295 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 295 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK296" description="sticky reload lock for fuse word 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 296 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 296 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK297" description="sticky reload lock for fuse word 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 297 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 297 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK298" description="sticky reload lock for fuse word 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 298 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 298 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK299" description="sticky reload lock for fuse word 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 299 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 299 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK300" description="sticky reload lock for fuse word 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 300 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 300 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK301" description="sticky reload lock for fuse word 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 301 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 301 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK302" description="sticky reload lock for fuse word 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 302 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 302 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK303" description="sticky reload lock for fuse word 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 303 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 303 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK304" description="sticky reload lock for fuse word 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 304 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 304 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK305" description="sticky reload lock for fuse word 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 305 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 305 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK306" description="sticky reload lock for fuse word 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 306 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 306 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK307" description="sticky reload lock for fuse word 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 307 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 307 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK308" description="sticky reload lock for fuse word 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 308 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 308 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK309" description="sticky reload lock for fuse word 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 309 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 309 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK310" description="sticky reload lock for fuse word 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 310 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 310 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK311" description="sticky reload lock for fuse word 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 311 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 311 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK312" description="sticky reload lock for fuse word 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 312 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 312 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK313" description="sticky reload lock for fuse word 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 313 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 313 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK314" description="sticky reload lock for fuse word 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 314 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 314 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK315" description="sticky reload lock for fuse word 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 315 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 315 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK316" description="sticky reload lock for fuse word 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 316 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 316 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK317" description="sticky reload lock for fuse word 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 317 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 317 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK318" description="sticky reload lock for fuse word 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 318 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 318 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK319" description="sticky reload lock for fuse word 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 319 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 319 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK10" description="BSEC sticky reload lock register 10" start="+0x8A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK320" description="sticky reload lock for fuse word 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 320 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 320 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK321" description="sticky reload lock for fuse word 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 321 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 321 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK322" description="sticky reload lock for fuse word 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 322 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 322 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK323" description="sticky reload lock for fuse word 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 323 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 323 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK324" description="sticky reload lock for fuse word 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 324 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 324 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK325" description="sticky reload lock for fuse word 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 325 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 325 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK326" description="sticky reload lock for fuse word 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 326 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 326 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK327" description="sticky reload lock for fuse word 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 327 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 327 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK328" description="sticky reload lock for fuse word 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 328 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 328 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK329" description="sticky reload lock for fuse word 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 329 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 329 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK330" description="sticky reload lock for fuse word 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 330 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 330 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK331" description="sticky reload lock for fuse word 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 331 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 331 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK332" description="sticky reload lock for fuse word 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 332 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 332 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK333" description="sticky reload lock for fuse word 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 333 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 333 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK334" description="sticky reload lock for fuse word 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 334 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 334 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK335" description="sticky reload lock for fuse word 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 335 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 335 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK336" description="sticky reload lock for fuse word 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 336 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 336 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK337" description="sticky reload lock for fuse word 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 337 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 337 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK338" description="sticky reload lock for fuse word 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 338 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 338 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK339" description="sticky reload lock for fuse word 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 339 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 339 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK340" description="sticky reload lock for fuse word 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 340 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 340 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK341" description="sticky reload lock for fuse word 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 341 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 341 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK342" description="sticky reload lock for fuse word 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 342 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 342 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK343" description="sticky reload lock for fuse word 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 343 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 343 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK344" description="sticky reload lock for fuse word 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 344 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 344 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK345" description="sticky reload lock for fuse word 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 345 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 345 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK346" description="sticky reload lock for fuse word 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 346 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 346 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK347" description="sticky reload lock for fuse word 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 347 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 347 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK348" description="sticky reload lock for fuse word 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 348 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 348 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK349" description="sticky reload lock for fuse word 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 349 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 349 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK350" description="sticky reload lock for fuse word 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 350 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 350 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK351" description="sticky reload lock for fuse word 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 351 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 351 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK11" description="BSEC sticky reload lock register 11" start="+0x8AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK352" description="sticky reload lock for fuse word 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 352 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 352 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK353" description="sticky reload lock for fuse word 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 353 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 353 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK354" description="sticky reload lock for fuse word 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 354 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 354 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK355" description="sticky reload lock for fuse word 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 355 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 355 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK356" description="sticky reload lock for fuse word 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 356 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 356 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK357" description="sticky reload lock for fuse word 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 357 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 357 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK358" description="sticky reload lock for fuse word 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 358 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 358 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK359" description="sticky reload lock for fuse word 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 359 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 359 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK360" description="sticky reload lock for fuse word 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 360 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 360 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK361" description="sticky reload lock for fuse word 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 361 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 361 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK362" description="sticky reload lock for fuse word 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 362 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 362 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK363" description="sticky reload lock for fuse word 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 363 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 363 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK364" description="sticky reload lock for fuse word 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 364 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 364 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK365" description="sticky reload lock for fuse word 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 365 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 365 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK366" description="sticky reload lock for fuse word 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 366 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 366 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK367" description="sticky reload lock for fuse word 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 367 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 367 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK368" description="sticky reload lock for fuse word 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 368 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 368 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK369" description="sticky reload lock for fuse word 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 369 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 369 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK370" description="sticky reload lock for fuse word 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 370 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 370 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK371" description="sticky reload lock for fuse word 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 371 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 371 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK372" description="sticky reload lock for fuse word 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 372 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 372 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK373" description="sticky reload lock for fuse word 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 373 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 373 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK374" description="sticky reload lock for fuse word 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 374 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 374 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK375" description="sticky reload lock for fuse word 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 375 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 375 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK376" description="sticky reload lock for fuse word 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 376 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 376 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK377" description="sticky reload lock for fuse word 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 377 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 377 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK378" description="sticky reload lock for fuse word 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 378 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 378 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK379" description="sticky reload lock for fuse word 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 379 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 379 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK380" description="sticky reload lock for fuse word 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 380 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 380 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK381" description="sticky reload lock for fuse word 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 381 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 381 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK382" description="sticky reload lock for fuse word 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 382 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 382 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK383" description="sticky reload lock for fuse word 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 383 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 383 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR0" description="BSEC OTP valid register 0" start="+0x8C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF0" description="Valid flag for shadow register 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 0 was last reloaded. The value read from BSEC_FVR0 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 0 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF1" description="Valid flag for shadow register 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 1 was last reloaded. The value read from BSEC_FVR1 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 1 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF2" description="Valid flag for shadow register 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 2 was last reloaded. The value read from BSEC_FVR2 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 2 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF3" description="Valid flag for shadow register 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 3 was last reloaded. The value read from BSEC_FVR3 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 3 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF4" description="Valid flag for shadow register 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 4 was last reloaded. The value read from BSEC_FVR4 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 4 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF5" description="Valid flag for shadow register 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 5 was last reloaded. The value read from BSEC_FVR5 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 5 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF6" description="Valid flag for shadow register 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 6 was last reloaded. The value read from BSEC_FVR6 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 6 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF7" description="Valid flag for shadow register 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 7 was last reloaded. The value read from BSEC_FVR7 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 7 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF8" description="Valid flag for shadow register 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 8 was last reloaded. The value read from BSEC_FVR8 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 8 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF9" description="Valid flag for shadow register 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 9 was last reloaded. The value read from BSEC_FVR9 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 9 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF10" description="Valid flag for shadow register 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 10 was last reloaded. The value read from BSEC_FVR10 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 10 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF11" description="Valid flag for shadow register 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 11 was last reloaded. The value read from BSEC_FVR11 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 11 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF12" description="Valid flag for shadow register 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 12 was last reloaded. The value read from BSEC_FVR12 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 12 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF13" description="Valid flag for shadow register 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 13 was last reloaded. The value read from BSEC_FVR13 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 13 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF14" description="Valid flag for shadow register 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 14 was last reloaded. The value read from BSEC_FVR14 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 14 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF15" description="Valid flag for shadow register 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 15 was last reloaded. The value read from BSEC_FVR15 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 15 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF16" description="Valid flag for shadow register 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 16 was last reloaded. The value read from BSEC_FVR16 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 16 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF17" description="Valid flag for shadow register 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 17 was last reloaded. The value read from BSEC_FVR17 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 17 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF18" description="Valid flag for shadow register 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 18 was last reloaded. The value read from BSEC_FVR18 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 18 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF19" description="Valid flag for shadow register 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 19 was last reloaded. The value read from BSEC_FVR19 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 19 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF20" description="Valid flag for shadow register 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 20 was last reloaded. The value read from BSEC_FVR20 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 20 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF21" description="Valid flag for shadow register 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 21 was last reloaded. The value read from BSEC_FVR21 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 21 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF22" description="Valid flag for shadow register 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 22 was last reloaded. The value read from BSEC_FVR22 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 22 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF23" description="Valid flag for shadow register 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 23 was last reloaded. The value read from BSEC_FVR23 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 23 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF24" description="Valid flag for shadow register 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 24 was last reloaded. The value read from BSEC_FVR24 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 24 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF25" description="Valid flag for shadow register 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 25 was last reloaded. The value read from BSEC_FVR25 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 25 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF26" description="Valid flag for shadow register 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 26 was last reloaded. The value read from BSEC_FVR26 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 26 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF27" description="Valid flag for shadow register 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 27 was last reloaded. The value read from BSEC_FVR27 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 27 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF28" description="Valid flag for shadow register 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 28 was last reloaded. The value read from BSEC_FVR28 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 28 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF29" description="Valid flag for shadow register 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 29 was last reloaded. The value read from BSEC_FVR29 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 29 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF30" description="Valid flag for shadow register 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 30 was last reloaded. The value read from BSEC_FVR30 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 30 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF31" description="Valid flag for shadow register 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 31 was last reloaded. The value read from BSEC_FVR31 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 31 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR1" description="BSEC OTP valid register 1" start="+0x8C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF32" description="Valid flag for shadow register 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 32 was last reloaded. The value read from BSEC_FVR32 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 32 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF33" description="Valid flag for shadow register 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 33 was last reloaded. The value read from BSEC_FVR33 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 33 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF34" description="Valid flag for shadow register 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 34 was last reloaded. The value read from BSEC_FVR34 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 34 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF35" description="Valid flag for shadow register 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 35 was last reloaded. The value read from BSEC_FVR35 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 35 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF36" description="Valid flag for shadow register 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 36 was last reloaded. The value read from BSEC_FVR36 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 36 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF37" description="Valid flag for shadow register 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 37 was last reloaded. The value read from BSEC_FVR37 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 37 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF38" description="Valid flag for shadow register 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 38 was last reloaded. The value read from BSEC_FVR38 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 38 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF39" description="Valid flag for shadow register 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 39 was last reloaded. The value read from BSEC_FVR39 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 39 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF40" description="Valid flag for shadow register 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 40 was last reloaded. The value read from BSEC_FVR40 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 40 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF41" description="Valid flag for shadow register 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 41 was last reloaded. The value read from BSEC_FVR41 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 41 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF42" description="Valid flag for shadow register 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 42 was last reloaded. The value read from BSEC_FVR42 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 42 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF43" description="Valid flag for shadow register 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 43 was last reloaded. The value read from BSEC_FVR43 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 43 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF44" description="Valid flag for shadow register 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 44 was last reloaded. The value read from BSEC_FVR44 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 44 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF45" description="Valid flag for shadow register 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 45 was last reloaded. The value read from BSEC_FVR45 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 45 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF46" description="Valid flag for shadow register 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 46 was last reloaded. The value read from BSEC_FVR46 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 46 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF47" description="Valid flag for shadow register 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 47 was last reloaded. The value read from BSEC_FVR47 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 47 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF48" description="Valid flag for shadow register 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 48 was last reloaded. The value read from BSEC_FVR48 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 48 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF49" description="Valid flag for shadow register 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 49 was last reloaded. The value read from BSEC_FVR49 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 49 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF50" description="Valid flag for shadow register 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 50 was last reloaded. The value read from BSEC_FVR50 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 50 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF51" description="Valid flag for shadow register 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 51 was last reloaded. The value read from BSEC_FVR51 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 51 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF52" description="Valid flag for shadow register 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 52 was last reloaded. The value read from BSEC_FVR52 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 52 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF53" description="Valid flag for shadow register 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 53 was last reloaded. The value read from BSEC_FVR53 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 53 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF54" description="Valid flag for shadow register 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 54 was last reloaded. The value read from BSEC_FVR54 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 54 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF55" description="Valid flag for shadow register 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 55 was last reloaded. The value read from BSEC_FVR55 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 55 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF56" description="Valid flag for shadow register 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 56 was last reloaded. The value read from BSEC_FVR56 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 56 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF57" description="Valid flag for shadow register 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 57 was last reloaded. The value read from BSEC_FVR57 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 57 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF58" description="Valid flag for shadow register 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 58 was last reloaded. The value read from BSEC_FVR58 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 58 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF59" description="Valid flag for shadow register 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 59 was last reloaded. The value read from BSEC_FVR59 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 59 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF60" description="Valid flag for shadow register 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 60 was last reloaded. The value read from BSEC_FVR60 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 60 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF61" description="Valid flag for shadow register 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 61 was last reloaded. The value read from BSEC_FVR61 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 61 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF62" description="Valid flag for shadow register 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 62 was last reloaded. The value read from BSEC_FVR62 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 62 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF63" description="Valid flag for shadow register 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 63 was last reloaded. The value read from BSEC_FVR63 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 63 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR2" description="BSEC OTP valid register 2" start="+0x8C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF64" description="Valid flag for shadow register 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 64 was last reloaded. The value read from BSEC_FVR64 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 64 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF65" description="Valid flag for shadow register 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 65 was last reloaded. The value read from BSEC_FVR65 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 65 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF66" description="Valid flag for shadow register 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 66 was last reloaded. The value read from BSEC_FVR66 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 66 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF67" description="Valid flag for shadow register 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 67 was last reloaded. The value read from BSEC_FVR67 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 67 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF68" description="Valid flag for shadow register 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 68 was last reloaded. The value read from BSEC_FVR68 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 68 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF69" description="Valid flag for shadow register 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 69 was last reloaded. The value read from BSEC_FVR69 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 69 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF70" description="Valid flag for shadow register 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 70 was last reloaded. The value read from BSEC_FVR70 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 70 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF71" description="Valid flag for shadow register 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 71 was last reloaded. The value read from BSEC_FVR71 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 71 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF72" description="Valid flag for shadow register 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 72 was last reloaded. The value read from BSEC_FVR72 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 72 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF73" description="Valid flag for shadow register 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 73 was last reloaded. The value read from BSEC_FVR73 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 73 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF74" description="Valid flag for shadow register 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 74 was last reloaded. The value read from BSEC_FVR74 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 74 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF75" description="Valid flag for shadow register 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 75 was last reloaded. The value read from BSEC_FVR75 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 75 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF76" description="Valid flag for shadow register 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 76 was last reloaded. The value read from BSEC_FVR76 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 76 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF77" description="Valid flag for shadow register 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 77 was last reloaded. The value read from BSEC_FVR77 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 77 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF78" description="Valid flag for shadow register 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 78 was last reloaded. The value read from BSEC_FVR78 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 78 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF79" description="Valid flag for shadow register 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 79 was last reloaded. The value read from BSEC_FVR79 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 79 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF80" description="Valid flag for shadow register 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 80 was last reloaded. The value read from BSEC_FVR80 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 80 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF81" description="Valid flag for shadow register 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 81 was last reloaded. The value read from BSEC_FVR81 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 81 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF82" description="Valid flag for shadow register 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 82 was last reloaded. The value read from BSEC_FVR82 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 82 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF83" description="Valid flag for shadow register 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 83 was last reloaded. The value read from BSEC_FVR83 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 83 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF84" description="Valid flag for shadow register 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 84 was last reloaded. The value read from BSEC_FVR84 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 84 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF85" description="Valid flag for shadow register 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 85 was last reloaded. The value read from BSEC_FVR85 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 85 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF86" description="Valid flag for shadow register 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 86 was last reloaded. The value read from BSEC_FVR86 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 86 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF87" description="Valid flag for shadow register 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 87 was last reloaded. The value read from BSEC_FVR87 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 87 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF88" description="Valid flag for shadow register 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 88 was last reloaded. The value read from BSEC_FVR88 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 88 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF89" description="Valid flag for shadow register 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 89 was last reloaded. The value read from BSEC_FVR89 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 89 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF90" description="Valid flag for shadow register 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 90 was last reloaded. The value read from BSEC_FVR90 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 90 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF91" description="Valid flag for shadow register 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 91 was last reloaded. The value read from BSEC_FVR91 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 91 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF92" description="Valid flag for shadow register 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 92 was last reloaded. The value read from BSEC_FVR92 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 92 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF93" description="Valid flag for shadow register 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 93 was last reloaded. The value read from BSEC_FVR93 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 93 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF94" description="Valid flag for shadow register 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 94 was last reloaded. The value read from BSEC_FVR94 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 94 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF95" description="Valid flag for shadow register 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 95 was last reloaded. The value read from BSEC_FVR95 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 95 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR3" description="BSEC OTP valid register 3" start="+0x8CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF96" description="Valid flag for shadow register 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 96 was last reloaded. The value read from BSEC_FVR96 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 96 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF97" description="Valid flag for shadow register 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 97 was last reloaded. The value read from BSEC_FVR97 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 97 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF98" description="Valid flag for shadow register 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 98 was last reloaded. The value read from BSEC_FVR98 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 98 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF99" description="Valid flag for shadow register 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 99 was last reloaded. The value read from BSEC_FVR99 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 99 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF100" description="Valid flag for shadow register 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 100 was last reloaded. The value read from BSEC_FVR100 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 100 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF101" description="Valid flag for shadow register 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 101 was last reloaded. The value read from BSEC_FVR101 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 101 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF102" description="Valid flag for shadow register 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 102 was last reloaded. The value read from BSEC_FVR102 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 102 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF103" description="Valid flag for shadow register 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 103 was last reloaded. The value read from BSEC_FVR103 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 103 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF104" description="Valid flag for shadow register 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 104 was last reloaded. The value read from BSEC_FVR104 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 104 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF105" description="Valid flag for shadow register 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 105 was last reloaded. The value read from BSEC_FVR105 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 105 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF106" description="Valid flag for shadow register 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 106 was last reloaded. The value read from BSEC_FVR106 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 106 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF107" description="Valid flag for shadow register 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 107 was last reloaded. The value read from BSEC_FVR107 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 107 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF108" description="Valid flag for shadow register 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 108 was last reloaded. The value read from BSEC_FVR108 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 108 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF109" description="Valid flag for shadow register 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 109 was last reloaded. The value read from BSEC_FVR109 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 109 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF110" description="Valid flag for shadow register 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 110 was last reloaded. The value read from BSEC_FVR110 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 110 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF111" description="Valid flag for shadow register 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 111 was last reloaded. The value read from BSEC_FVR111 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 111 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF112" description="Valid flag for shadow register 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 112 was last reloaded. The value read from BSEC_FVR112 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 112 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF113" description="Valid flag for shadow register 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 113 was last reloaded. The value read from BSEC_FVR113 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 113 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF114" description="Valid flag for shadow register 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 114 was last reloaded. The value read from BSEC_FVR114 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 114 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF115" description="Valid flag for shadow register 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 115 was last reloaded. The value read from BSEC_FVR115 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 115 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF116" description="Valid flag for shadow register 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 116 was last reloaded. The value read from BSEC_FVR116 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 116 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF117" description="Valid flag for shadow register 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 117 was last reloaded. The value read from BSEC_FVR117 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 117 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF118" description="Valid flag for shadow register 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 118 was last reloaded. The value read from BSEC_FVR118 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 118 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF119" description="Valid flag for shadow register 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 119 was last reloaded. The value read from BSEC_FVR119 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 119 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF120" description="Valid flag for shadow register 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 120 was last reloaded. The value read from BSEC_FVR120 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 120 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF121" description="Valid flag for shadow register 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 121 was last reloaded. The value read from BSEC_FVR121 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 121 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF122" description="Valid flag for shadow register 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 122 was last reloaded. The value read from BSEC_FVR122 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 122 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF123" description="Valid flag for shadow register 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 123 was last reloaded. The value read from BSEC_FVR123 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 123 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF124" description="Valid flag for shadow register 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 124 was last reloaded. The value read from BSEC_FVR124 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 124 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF125" description="Valid flag for shadow register 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 125 was last reloaded. The value read from BSEC_FVR125 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 125 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF126" description="Valid flag for shadow register 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 126 was last reloaded. The value read from BSEC_FVR126 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 126 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF127" description="Valid flag for shadow register 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 127 was last reloaded. The value read from BSEC_FVR127 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 127 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR4" description="BSEC OTP valid register 4" start="+0x8D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF128" description="Valid flag for shadow register 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 128 was last reloaded. The value read from BSEC_FVR128 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 128 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF129" description="Valid flag for shadow register 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 129 was last reloaded. The value read from BSEC_FVR129 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 129 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF130" description="Valid flag for shadow register 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 130 was last reloaded. The value read from BSEC_FVR130 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 130 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF131" description="Valid flag for shadow register 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 131 was last reloaded. The value read from BSEC_FVR131 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 131 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF132" description="Valid flag for shadow register 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 132 was last reloaded. The value read from BSEC_FVR132 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 132 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF133" description="Valid flag for shadow register 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 133 was last reloaded. The value read from BSEC_FVR133 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 133 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF134" description="Valid flag for shadow register 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 134 was last reloaded. The value read from BSEC_FVR134 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 134 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF135" description="Valid flag for shadow register 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 135 was last reloaded. The value read from BSEC_FVR135 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 135 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF136" description="Valid flag for shadow register 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 136 was last reloaded. The value read from BSEC_FVR136 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 136 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF137" description="Valid flag for shadow register 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 137 was last reloaded. The value read from BSEC_FVR137 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 137 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF138" description="Valid flag for shadow register 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 138 was last reloaded. The value read from BSEC_FVR138 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 138 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF139" description="Valid flag for shadow register 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 139 was last reloaded. The value read from BSEC_FVR139 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 139 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF140" description="Valid flag for shadow register 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 140 was last reloaded. The value read from BSEC_FVR140 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 140 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF141" description="Valid flag for shadow register 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 141 was last reloaded. The value read from BSEC_FVR141 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 141 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF142" description="Valid flag for shadow register 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 142 was last reloaded. The value read from BSEC_FVR142 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 142 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF143" description="Valid flag for shadow register 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 143 was last reloaded. The value read from BSEC_FVR143 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 143 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF144" description="Valid flag for shadow register 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 144 was last reloaded. The value read from BSEC_FVR144 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 144 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF145" description="Valid flag for shadow register 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 145 was last reloaded. The value read from BSEC_FVR145 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 145 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF146" description="Valid flag for shadow register 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 146 was last reloaded. The value read from BSEC_FVR146 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 146 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF147" description="Valid flag for shadow register 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 147 was last reloaded. The value read from BSEC_FVR147 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 147 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF148" description="Valid flag for shadow register 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 148 was last reloaded. The value read from BSEC_FVR148 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 148 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF149" description="Valid flag for shadow register 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 149 was last reloaded. The value read from BSEC_FVR149 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 149 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF150" description="Valid flag for shadow register 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 150 was last reloaded. The value read from BSEC_FVR150 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 150 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF151" description="Valid flag for shadow register 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 151 was last reloaded. The value read from BSEC_FVR151 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 151 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF152" description="Valid flag for shadow register 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 152 was last reloaded. The value read from BSEC_FVR152 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 152 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF153" description="Valid flag for shadow register 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 153 was last reloaded. The value read from BSEC_FVR153 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 153 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF154" description="Valid flag for shadow register 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 154 was last reloaded. The value read from BSEC_FVR154 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 154 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF155" description="Valid flag for shadow register 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 155 was last reloaded. The value read from BSEC_FVR155 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 155 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF156" description="Valid flag for shadow register 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 156 was last reloaded. The value read from BSEC_FVR156 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 156 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF157" description="Valid flag for shadow register 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 157 was last reloaded. The value read from BSEC_FVR157 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 157 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF158" description="Valid flag for shadow register 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 158 was last reloaded. The value read from BSEC_FVR158 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 158 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF159" description="Valid flag for shadow register 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 159 was last reloaded. The value read from BSEC_FVR159 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 159 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR5" description="BSEC OTP valid register 5" start="+0x8D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF160" description="Valid flag for shadow register 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 160 was last reloaded. The value read from BSEC_FVR160 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 160 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF161" description="Valid flag for shadow register 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 161 was last reloaded. The value read from BSEC_FVR161 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 161 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF162" description="Valid flag for shadow register 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 162 was last reloaded. The value read from BSEC_FVR162 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 162 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF163" description="Valid flag for shadow register 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 163 was last reloaded. The value read from BSEC_FVR163 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 163 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF164" description="Valid flag for shadow register 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 164 was last reloaded. The value read from BSEC_FVR164 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 164 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF165" description="Valid flag for shadow register 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 165 was last reloaded. The value read from BSEC_FVR165 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 165 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF166" description="Valid flag for shadow register 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 166 was last reloaded. The value read from BSEC_FVR166 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 166 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF167" description="Valid flag for shadow register 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 167 was last reloaded. The value read from BSEC_FVR167 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 167 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF168" description="Valid flag for shadow register 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 168 was last reloaded. The value read from BSEC_FVR168 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 168 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF169" description="Valid flag for shadow register 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 169 was last reloaded. The value read from BSEC_FVR169 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 169 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF170" description="Valid flag for shadow register 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 170 was last reloaded. The value read from BSEC_FVR170 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 170 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF171" description="Valid flag for shadow register 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 171 was last reloaded. The value read from BSEC_FVR171 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 171 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF172" description="Valid flag for shadow register 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 172 was last reloaded. The value read from BSEC_FVR172 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 172 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF173" description="Valid flag for shadow register 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 173 was last reloaded. The value read from BSEC_FVR173 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 173 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF174" description="Valid flag for shadow register 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 174 was last reloaded. The value read from BSEC_FVR174 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 174 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF175" description="Valid flag for shadow register 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 175 was last reloaded. The value read from BSEC_FVR175 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 175 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF176" description="Valid flag for shadow register 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 176 was last reloaded. The value read from BSEC_FVR176 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 176 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF177" description="Valid flag for shadow register 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 177 was last reloaded. The value read from BSEC_FVR177 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 177 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF178" description="Valid flag for shadow register 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 178 was last reloaded. The value read from BSEC_FVR178 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 178 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF179" description="Valid flag for shadow register 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 179 was last reloaded. The value read from BSEC_FVR179 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 179 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF180" description="Valid flag for shadow register 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 180 was last reloaded. The value read from BSEC_FVR180 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 180 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF181" description="Valid flag for shadow register 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 181 was last reloaded. The value read from BSEC_FVR181 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 181 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF182" description="Valid flag for shadow register 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 182 was last reloaded. The value read from BSEC_FVR182 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 182 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF183" description="Valid flag for shadow register 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 183 was last reloaded. The value read from BSEC_FVR183 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 183 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF184" description="Valid flag for shadow register 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 184 was last reloaded. The value read from BSEC_FVR184 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 184 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF185" description="Valid flag for shadow register 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 185 was last reloaded. The value read from BSEC_FVR185 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 185 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF186" description="Valid flag for shadow register 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 186 was last reloaded. The value read from BSEC_FVR186 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 186 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF187" description="Valid flag for shadow register 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 187 was last reloaded. The value read from BSEC_FVR187 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 187 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF188" description="Valid flag for shadow register 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 188 was last reloaded. The value read from BSEC_FVR188 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 188 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF189" description="Valid flag for shadow register 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 189 was last reloaded. The value read from BSEC_FVR189 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 189 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF190" description="Valid flag for shadow register 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 190 was last reloaded. The value read from BSEC_FVR190 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 190 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF191" description="Valid flag for shadow register 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 191 was last reloaded. The value read from BSEC_FVR191 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 191 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR6" description="BSEC OTP valid register 6" start="+0x8D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF192" description="Valid flag for shadow register 192" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 192 was last reloaded. The value read from BSEC_FVR192 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 192 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF193" description="Valid flag for shadow register 193" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 193 was last reloaded. The value read from BSEC_FVR193 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 193 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF194" description="Valid flag for shadow register 194" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 194 was last reloaded. The value read from BSEC_FVR194 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 194 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF195" description="Valid flag for shadow register 195" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 195 was last reloaded. The value read from BSEC_FVR195 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 195 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF196" description="Valid flag for shadow register 196" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 196 was last reloaded. The value read from BSEC_FVR196 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 196 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF197" description="Valid flag for shadow register 197" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 197 was last reloaded. The value read from BSEC_FVR197 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 197 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF198" description="Valid flag for shadow register 198" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 198 was last reloaded. The value read from BSEC_FVR198 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 198 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF199" description="Valid flag for shadow register 199" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 199 was last reloaded. The value read from BSEC_FVR199 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 199 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF200" description="Valid flag for shadow register 200" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 200 was last reloaded. The value read from BSEC_FVR200 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 200 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF201" description="Valid flag for shadow register 201" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 201 was last reloaded. The value read from BSEC_FVR201 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 201 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF202" description="Valid flag for shadow register 202" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 202 was last reloaded. The value read from BSEC_FVR202 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 202 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF203" description="Valid flag for shadow register 203" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 203 was last reloaded. The value read from BSEC_FVR203 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 203 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF204" description="Valid flag for shadow register 204" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 204 was last reloaded. The value read from BSEC_FVR204 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 204 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF205" description="Valid flag for shadow register 205" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 205 was last reloaded. The value read from BSEC_FVR205 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 205 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF206" description="Valid flag for shadow register 206" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 206 was last reloaded. The value read from BSEC_FVR206 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 206 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF207" description="Valid flag for shadow register 207" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 207 was last reloaded. The value read from BSEC_FVR207 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 207 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF208" description="Valid flag for shadow register 208" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 208 was last reloaded. The value read from BSEC_FVR208 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 208 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF209" description="Valid flag for shadow register 209" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 209 was last reloaded. The value read from BSEC_FVR209 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 209 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF210" description="Valid flag for shadow register 210" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 210 was last reloaded. The value read from BSEC_FVR210 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 210 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF211" description="Valid flag for shadow register 211" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 211 was last reloaded. The value read from BSEC_FVR211 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 211 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF212" description="Valid flag for shadow register 212" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 212 was last reloaded. The value read from BSEC_FVR212 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 212 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF213" description="Valid flag for shadow register 213" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 213 was last reloaded. The value read from BSEC_FVR213 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 213 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF214" description="Valid flag for shadow register 214" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 214 was last reloaded. The value read from BSEC_FVR214 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 214 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF215" description="Valid flag for shadow register 215" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 215 was last reloaded. The value read from BSEC_FVR215 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 215 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF216" description="Valid flag for shadow register 216" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 216 was last reloaded. The value read from BSEC_FVR216 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 216 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF217" description="Valid flag for shadow register 217" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 217 was last reloaded. The value read from BSEC_FVR217 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 217 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF218" description="Valid flag for shadow register 218" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 218 was last reloaded. The value read from BSEC_FVR218 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 218 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF219" description="Valid flag for shadow register 219" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 219 was last reloaded. The value read from BSEC_FVR219 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 219 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF220" description="Valid flag for shadow register 220" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 220 was last reloaded. The value read from BSEC_FVR220 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 220 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF221" description="Valid flag for shadow register 221" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 221 was last reloaded. The value read from BSEC_FVR221 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 221 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF222" description="Valid flag for shadow register 222" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 222 was last reloaded. The value read from BSEC_FVR222 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 222 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF223" description="Valid flag for shadow register 223" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 223 was last reloaded. The value read from BSEC_FVR223 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 223 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR7" description="BSEC OTP valid register 7" start="+0x8DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF224" description="Valid flag for shadow register 224" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 224 was last reloaded. The value read from BSEC_FVR224 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 224 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF225" description="Valid flag for shadow register 225" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 225 was last reloaded. The value read from BSEC_FVR225 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 225 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF226" description="Valid flag for shadow register 226" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 226 was last reloaded. The value read from BSEC_FVR226 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 226 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF227" description="Valid flag for shadow register 227" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 227 was last reloaded. The value read from BSEC_FVR227 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 227 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF228" description="Valid flag for shadow register 228" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 228 was last reloaded. The value read from BSEC_FVR228 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 228 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF229" description="Valid flag for shadow register 229" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 229 was last reloaded. The value read from BSEC_FVR229 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 229 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF230" description="Valid flag for shadow register 230" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 230 was last reloaded. The value read from BSEC_FVR230 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 230 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF231" description="Valid flag for shadow register 231" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 231 was last reloaded. The value read from BSEC_FVR231 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 231 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF232" description="Valid flag for shadow register 232" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 232 was last reloaded. The value read from BSEC_FVR232 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 232 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF233" description="Valid flag for shadow register 233" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 233 was last reloaded. The value read from BSEC_FVR233 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 233 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF234" description="Valid flag for shadow register 234" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 234 was last reloaded. The value read from BSEC_FVR234 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 234 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF235" description="Valid flag for shadow register 235" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 235 was last reloaded. The value read from BSEC_FVR235 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 235 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF236" description="Valid flag for shadow register 236" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 236 was last reloaded. The value read from BSEC_FVR236 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 236 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF237" description="Valid flag for shadow register 237" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 237 was last reloaded. The value read from BSEC_FVR237 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 237 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF238" description="Valid flag for shadow register 238" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 238 was last reloaded. The value read from BSEC_FVR238 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 238 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF239" description="Valid flag for shadow register 239" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 239 was last reloaded. The value read from BSEC_FVR239 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 239 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF240" description="Valid flag for shadow register 240" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 240 was last reloaded. The value read from BSEC_FVR240 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 240 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF241" description="Valid flag for shadow register 241" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 241 was last reloaded. The value read from BSEC_FVR241 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 241 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF242" description="Valid flag for shadow register 242" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 242 was last reloaded. The value read from BSEC_FVR242 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 242 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF243" description="Valid flag for shadow register 243" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 243 was last reloaded. The value read from BSEC_FVR243 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 243 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF244" description="Valid flag for shadow register 244" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 244 was last reloaded. The value read from BSEC_FVR244 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 244 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF245" description="Valid flag for shadow register 245" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 245 was last reloaded. The value read from BSEC_FVR245 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 245 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF246" description="Valid flag for shadow register 246" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 246 was last reloaded. The value read from BSEC_FVR246 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 246 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF247" description="Valid flag for shadow register 247" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 247 was last reloaded. The value read from BSEC_FVR247 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 247 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF248" description="Valid flag for shadow register 248" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 248 was last reloaded. The value read from BSEC_FVR248 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 248 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF249" description="Valid flag for shadow register 249" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 249 was last reloaded. The value read from BSEC_FVR249 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 249 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF250" description="Valid flag for shadow register 250" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 250 was last reloaded. The value read from BSEC_FVR250 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 250 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF251" description="Valid flag for shadow register 251" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 251 was last reloaded. The value read from BSEC_FVR251 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 251 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF252" description="Valid flag for shadow register 252" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 252 was last reloaded. The value read from BSEC_FVR252 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 252 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF253" description="Valid flag for shadow register 253" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 253 was last reloaded. The value read from BSEC_FVR253 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 253 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF254" description="Valid flag for shadow register 254" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 254 was last reloaded. The value read from BSEC_FVR254 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 254 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF255" description="Valid flag for shadow register 255" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 255 was last reloaded. The value read from BSEC_FVR255 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 255 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR8" description="BSEC OTP valid register 8" start="+0x8E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF256" description="Valid flag for shadow register 256" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 256 was last reloaded. The value read from BSEC_FVR256 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 256 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF257" description="Valid flag for shadow register 257" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 257 was last reloaded. The value read from BSEC_FVR257 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 257 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF258" description="Valid flag for shadow register 258" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 258 was last reloaded. The value read from BSEC_FVR258 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 258 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF259" description="Valid flag for shadow register 259" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 259 was last reloaded. The value read from BSEC_FVR259 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 259 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF260" description="Valid flag for shadow register 260" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 260 was last reloaded. The value read from BSEC_FVR260 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 260 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF261" description="Valid flag for shadow register 261" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 261 was last reloaded. The value read from BSEC_FVR261 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 261 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF262" description="Valid flag for shadow register 262" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 262 was last reloaded. The value read from BSEC_FVR262 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 262 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF263" description="Valid flag for shadow register 263" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 263 was last reloaded. The value read from BSEC_FVR263 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 263 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF264" description="Valid flag for shadow register 264" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 264 was last reloaded. The value read from BSEC_FVR264 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 264 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF265" description="Valid flag for shadow register 265" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 265 was last reloaded. The value read from BSEC_FVR265 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 265 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF266" description="Valid flag for shadow register 266" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 266 was last reloaded. The value read from BSEC_FVR266 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 266 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF267" description="Valid flag for shadow register 267" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 267 was last reloaded. The value read from BSEC_FVR267 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 267 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF268" description="Valid flag for shadow register 268" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 268 was last reloaded. The value read from BSEC_FVR268 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 268 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF269" description="Valid flag for shadow register 269" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 269 was last reloaded. The value read from BSEC_FVR269 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 269 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF270" description="Valid flag for shadow register 270" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 270 was last reloaded. The value read from BSEC_FVR270 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 270 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF271" description="Valid flag for shadow register 271" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 271 was last reloaded. The value read from BSEC_FVR271 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 271 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF272" description="Valid flag for shadow register 272" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 272 was last reloaded. The value read from BSEC_FVR272 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 272 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF273" description="Valid flag for shadow register 273" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 273 was last reloaded. The value read from BSEC_FVR273 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 273 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF274" description="Valid flag for shadow register 274" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 274 was last reloaded. The value read from BSEC_FVR274 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 274 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF275" description="Valid flag for shadow register 275" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 275 was last reloaded. The value read from BSEC_FVR275 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 275 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF276" description="Valid flag for shadow register 276" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 276 was last reloaded. The value read from BSEC_FVR276 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 276 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF277" description="Valid flag for shadow register 277" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 277 was last reloaded. The value read from BSEC_FVR277 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 277 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF278" description="Valid flag for shadow register 278" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 278 was last reloaded. The value read from BSEC_FVR278 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 278 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF279" description="Valid flag for shadow register 279" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 279 was last reloaded. The value read from BSEC_FVR279 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 279 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF280" description="Valid flag for shadow register 280" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 280 was last reloaded. The value read from BSEC_FVR280 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 280 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF281" description="Valid flag for shadow register 281" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 281 was last reloaded. The value read from BSEC_FVR281 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 281 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF282" description="Valid flag for shadow register 282" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 282 was last reloaded. The value read from BSEC_FVR282 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 282 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF283" description="Valid flag for shadow register 283" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 283 was last reloaded. The value read from BSEC_FVR283 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 283 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF284" description="Valid flag for shadow register 284" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 284 was last reloaded. The value read from BSEC_FVR284 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 284 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF285" description="Valid flag for shadow register 285" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 285 was last reloaded. The value read from BSEC_FVR285 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 285 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF286" description="Valid flag for shadow register 286" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 286 was last reloaded. The value read from BSEC_FVR286 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 286 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF287" description="Valid flag for shadow register 287" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 287 was last reloaded. The value read from BSEC_FVR287 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 287 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR9" description="BSEC OTP valid register 9" start="+0x8E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF288" description="Valid flag for shadow register 288" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 288 was last reloaded. The value read from BSEC_FVR288 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 288 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF289" description="Valid flag for shadow register 289" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 289 was last reloaded. The value read from BSEC_FVR289 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 289 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF290" description="Valid flag for shadow register 290" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 290 was last reloaded. The value read from BSEC_FVR290 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 290 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF291" description="Valid flag for shadow register 291" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 291 was last reloaded. The value read from BSEC_FVR291 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 291 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF292" description="Valid flag for shadow register 292" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 292 was last reloaded. The value read from BSEC_FVR292 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 292 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF293" description="Valid flag for shadow register 293" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 293 was last reloaded. The value read from BSEC_FVR293 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 293 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF294" description="Valid flag for shadow register 294" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 294 was last reloaded. The value read from BSEC_FVR294 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 294 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF295" description="Valid flag for shadow register 295" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 295 was last reloaded. The value read from BSEC_FVR295 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 295 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF296" description="Valid flag for shadow register 296" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 296 was last reloaded. The value read from BSEC_FVR296 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 296 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF297" description="Valid flag for shadow register 297" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 297 was last reloaded. The value read from BSEC_FVR297 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 297 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF298" description="Valid flag for shadow register 298" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 298 was last reloaded. The value read from BSEC_FVR298 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 298 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF299" description="Valid flag for shadow register 299" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 299 was last reloaded. The value read from BSEC_FVR299 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 299 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF300" description="Valid flag for shadow register 300" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 300 was last reloaded. The value read from BSEC_FVR300 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 300 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF301" description="Valid flag for shadow register 301" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 301 was last reloaded. The value read from BSEC_FVR301 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 301 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF302" description="Valid flag for shadow register 302" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 302 was last reloaded. The value read from BSEC_FVR302 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 302 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF303" description="Valid flag for shadow register 303" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 303 was last reloaded. The value read from BSEC_FVR303 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 303 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF304" description="Valid flag for shadow register 304" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 304 was last reloaded. The value read from BSEC_FVR304 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 304 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF305" description="Valid flag for shadow register 305" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 305 was last reloaded. The value read from BSEC_FVR305 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 305 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF306" description="Valid flag for shadow register 306" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 306 was last reloaded. The value read from BSEC_FVR306 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 306 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF307" description="Valid flag for shadow register 307" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 307 was last reloaded. The value read from BSEC_FVR307 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 307 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF308" description="Valid flag for shadow register 308" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 308 was last reloaded. The value read from BSEC_FVR308 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 308 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF309" description="Valid flag for shadow register 309" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 309 was last reloaded. The value read from BSEC_FVR309 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 309 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF310" description="Valid flag for shadow register 310" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 310 was last reloaded. The value read from BSEC_FVR310 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 310 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF311" description="Valid flag for shadow register 311" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 311 was last reloaded. The value read from BSEC_FVR311 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 311 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF312" description="Valid flag for shadow register 312" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 312 was last reloaded. The value read from BSEC_FVR312 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 312 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF313" description="Valid flag for shadow register 313" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 313 was last reloaded. The value read from BSEC_FVR313 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 313 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF314" description="Valid flag for shadow register 314" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 314 was last reloaded. The value read from BSEC_FVR314 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 314 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF315" description="Valid flag for shadow register 315" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 315 was last reloaded. The value read from BSEC_FVR315 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 315 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF316" description="Valid flag for shadow register 316" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 316 was last reloaded. The value read from BSEC_FVR316 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 316 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF317" description="Valid flag for shadow register 317" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 317 was last reloaded. The value read from BSEC_FVR317 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 317 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF318" description="Valid flag for shadow register 318" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 318 was last reloaded. The value read from BSEC_FVR318 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 318 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF319" description="Valid flag for shadow register 319" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 319 was last reloaded. The value read from BSEC_FVR319 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 319 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR10" description="BSEC OTP valid register 10" start="+0x8E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF320" description="Valid flag for shadow register 320" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 320 was last reloaded. The value read from BSEC_FVR320 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 320 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF321" description="Valid flag for shadow register 321" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 321 was last reloaded. The value read from BSEC_FVR321 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 321 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF322" description="Valid flag for shadow register 322" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 322 was last reloaded. The value read from BSEC_FVR322 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 322 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF323" description="Valid flag for shadow register 323" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 323 was last reloaded. The value read from BSEC_FVR323 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 323 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF324" description="Valid flag for shadow register 324" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 324 was last reloaded. The value read from BSEC_FVR324 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 324 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF325" description="Valid flag for shadow register 325" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 325 was last reloaded. The value read from BSEC_FVR325 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 325 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF326" description="Valid flag for shadow register 326" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 326 was last reloaded. The value read from BSEC_FVR326 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 326 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF327" description="Valid flag for shadow register 327" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 327 was last reloaded. The value read from BSEC_FVR327 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 327 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF328" description="Valid flag for shadow register 328" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 328 was last reloaded. The value read from BSEC_FVR328 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 328 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF329" description="Valid flag for shadow register 329" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 329 was last reloaded. The value read from BSEC_FVR329 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 329 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF330" description="Valid flag for shadow register 330" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 330 was last reloaded. The value read from BSEC_FVR330 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 330 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF331" description="Valid flag for shadow register 331" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 331 was last reloaded. The value read from BSEC_FVR331 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 331 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF332" description="Valid flag for shadow register 332" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 332 was last reloaded. The value read from BSEC_FVR332 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 332 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF333" description="Valid flag for shadow register 333" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 333 was last reloaded. The value read from BSEC_FVR333 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 333 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF334" description="Valid flag for shadow register 334" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 334 was last reloaded. The value read from BSEC_FVR334 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 334 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF335" description="Valid flag for shadow register 335" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 335 was last reloaded. The value read from BSEC_FVR335 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 335 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF336" description="Valid flag for shadow register 336" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 336 was last reloaded. The value read from BSEC_FVR336 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 336 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF337" description="Valid flag for shadow register 337" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 337 was last reloaded. The value read from BSEC_FVR337 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 337 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF338" description="Valid flag for shadow register 338" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 338 was last reloaded. The value read from BSEC_FVR338 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 338 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF339" description="Valid flag for shadow register 339" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 339 was last reloaded. The value read from BSEC_FVR339 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 339 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF340" description="Valid flag for shadow register 340" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 340 was last reloaded. The value read from BSEC_FVR340 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 340 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF341" description="Valid flag for shadow register 341" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 341 was last reloaded. The value read from BSEC_FVR341 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 341 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF342" description="Valid flag for shadow register 342" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 342 was last reloaded. The value read from BSEC_FVR342 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 342 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF343" description="Valid flag for shadow register 343" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 343 was last reloaded. The value read from BSEC_FVR343 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 343 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF344" description="Valid flag for shadow register 344" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 344 was last reloaded. The value read from BSEC_FVR344 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 344 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF345" description="Valid flag for shadow register 345" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 345 was last reloaded. The value read from BSEC_FVR345 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 345 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF346" description="Valid flag for shadow register 346" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 346 was last reloaded. The value read from BSEC_FVR346 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 346 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF347" description="Valid flag for shadow register 347" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 347 was last reloaded. The value read from BSEC_FVR347 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 347 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF348" description="Valid flag for shadow register 348" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 348 was last reloaded. The value read from BSEC_FVR348 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 348 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF349" description="Valid flag for shadow register 349" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 349 was last reloaded. The value read from BSEC_FVR349 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 349 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF350" description="Valid flag for shadow register 350" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 350 was last reloaded. The value read from BSEC_FVR350 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 350 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF351" description="Valid flag for shadow register 351" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 351 was last reloaded. The value read from BSEC_FVR351 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 351 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR11" description="BSEC OTP valid register 11" start="+0x8EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF352" description="Valid flag for shadow register 352" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 352 was last reloaded. The value read from BSEC_FVR352 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 352 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF353" description="Valid flag for shadow register 353" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 353 was last reloaded. The value read from BSEC_FVR353 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 353 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF354" description="Valid flag for shadow register 354" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 354 was last reloaded. The value read from BSEC_FVR354 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 354 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF355" description="Valid flag for shadow register 355" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 355 was last reloaded. The value read from BSEC_FVR355 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 355 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF356" description="Valid flag for shadow register 356" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 356 was last reloaded. The value read from BSEC_FVR356 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 356 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF357" description="Valid flag for shadow register 357" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 357 was last reloaded. The value read from BSEC_FVR357 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 357 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF358" description="Valid flag for shadow register 358" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 358 was last reloaded. The value read from BSEC_FVR358 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 358 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF359" description="Valid flag for shadow register 359" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 359 was last reloaded. The value read from BSEC_FVR359 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 359 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF360" description="Valid flag for shadow register 360" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 360 was last reloaded. The value read from BSEC_FVR360 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 360 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF361" description="Valid flag for shadow register 361" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 361 was last reloaded. The value read from BSEC_FVR361 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 361 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF362" description="Valid flag for shadow register 362" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 362 was last reloaded. The value read from BSEC_FVR362 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 362 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF363" description="Valid flag for shadow register 363" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 363 was last reloaded. The value read from BSEC_FVR363 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 363 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF364" description="Valid flag for shadow register 364" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 364 was last reloaded. The value read from BSEC_FVR364 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 364 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF365" description="Valid flag for shadow register 365" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 365 was last reloaded. The value read from BSEC_FVR365 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 365 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF366" description="Valid flag for shadow register 366" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 366 was last reloaded. The value read from BSEC_FVR366 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 366 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF367" description="Valid flag for shadow register 367" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 367 was last reloaded. The value read from BSEC_FVR367 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 367 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF368" description="Valid flag for shadow register 368" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 368 was last reloaded. The value read from BSEC_FVR368 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 368 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF369" description="Valid flag for shadow register 369" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 369 was last reloaded. The value read from BSEC_FVR369 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 369 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF370" description="Valid flag for shadow register 370" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 370 was last reloaded. The value read from BSEC_FVR370 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 370 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF371" description="Valid flag for shadow register 371" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 371 was last reloaded. The value read from BSEC_FVR371 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 371 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF372" description="Valid flag for shadow register 372" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 372 was last reloaded. The value read from BSEC_FVR372 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 372 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF373" description="Valid flag for shadow register 373" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 373 was last reloaded. The value read from BSEC_FVR373 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 373 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF374" description="Valid flag for shadow register 374" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 374 was last reloaded. The value read from BSEC_FVR374 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 374 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF375" description="Valid flag for shadow register 375" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 375 was last reloaded. The value read from BSEC_FVR375 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 375 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF376" description="Valid flag for shadow register 376" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 376 was last reloaded. The value read from BSEC_FVR376 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 376 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF377" description="Valid flag for shadow register 377" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 377 was last reloaded. The value read from BSEC_FVR377 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 377 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF378" description="Valid flag for shadow register 378" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 378 was last reloaded. The value read from BSEC_FVR378 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 378 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF379" description="Valid flag for shadow register 379" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 379 was last reloaded. The value read from BSEC_FVR379 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 379 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF380" description="Valid flag for shadow register 380" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 380 was last reloaded. The value read from BSEC_FVR380 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 380 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF381" description="Valid flag for shadow register 381" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 381 was last reloaded. The value read from BSEC_FVR381 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 381 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF382" description="Valid flag for shadow register 382" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 382 was last reloaded. The value read from BSEC_FVR382 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 382 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF383" description="Valid flag for shadow register 383" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 383 was last reloaded. The value read from BSEC_FVR383 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 383 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR0" description="BSEC shadowed fuses status register 0" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW0" description="Shadowed fuse word 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 0 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR0 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR0 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW1" description="Shadowed fuse word 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 1 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR1 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR1 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW2" description="Shadowed fuse word 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 2 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR2 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR2 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW3" description="Shadowed fuse word 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 3 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR3 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR3 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW4" description="Shadowed fuse word 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 4 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR4 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR4 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW5" description="Shadowed fuse word 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 5 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR5 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR5 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW6" description="Shadowed fuse word 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 6 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR6 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR6 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW7" description="Shadowed fuse word 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 7 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR7 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR7 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW8" description="Shadowed fuse word 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 8 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR8 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR8 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW9" description="Shadowed fuse word 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 9 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR9 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR9 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW10" description="Shadowed fuse word 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 10 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR10 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR10 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW11" description="Shadowed fuse word 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 11 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR11 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR11 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW12" description="Shadowed fuse word 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 12 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR12 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR12 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW13" description="Shadowed fuse word 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 13 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR13 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR13 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW14" description="Shadowed fuse word 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 14 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR14 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR14 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW15" description="Shadowed fuse word 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 15 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR15 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR15 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW16" description="Shadowed fuse word 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 16 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR16 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR16 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW17" description="Shadowed fuse word 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 17 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR17 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR17 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW18" description="Shadowed fuse word 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 18 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR18 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR18 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW19" description="Shadowed fuse word 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 19 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR19 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR19 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW20" description="Shadowed fuse word 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 20 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR20 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR20 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW21" description="Shadowed fuse word 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 21 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR21 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR21 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW22" description="Shadowed fuse word 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 22 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR22 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR22 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW23" description="Shadowed fuse word 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 23 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR23 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR23 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW24" description="Shadowed fuse word 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 24 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR24 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR24 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW25" description="Shadowed fuse word 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 25 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR25 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR25 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW26" description="Shadowed fuse word 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 26 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR26 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR26 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW27" description="Shadowed fuse word 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 27 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR27 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR27 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW28" description="Shadowed fuse word 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 28 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR28 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR28 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW29" description="Shadowed fuse word 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 29 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR29 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR29 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW30" description="Shadowed fuse word 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 30 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR30 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR30 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW31" description="Shadowed fuse word 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 31 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR31 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR31 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR1" description="BSEC shadowed fuses status register 1" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW32" description="Shadowed fuse word 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 32 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR32 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR32 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW33" description="Shadowed fuse word 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 33 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR33 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR33 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW34" description="Shadowed fuse word 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 34 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR34 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR34 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW35" description="Shadowed fuse word 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 35 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR35 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR35 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW36" description="Shadowed fuse word 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 36 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR36 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR36 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW37" description="Shadowed fuse word 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 37 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR37 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR37 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW38" description="Shadowed fuse word 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 38 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR38 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR38 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW39" description="Shadowed fuse word 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 39 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR39 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR39 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW40" description="Shadowed fuse word 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 40 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR40 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR40 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW41" description="Shadowed fuse word 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 41 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR41 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR41 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW42" description="Shadowed fuse word 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 42 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR42 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR42 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW43" description="Shadowed fuse word 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 43 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR43 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR43 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW44" description="Shadowed fuse word 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 44 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR44 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR44 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW45" description="Shadowed fuse word 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 45 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR45 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR45 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW46" description="Shadowed fuse word 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 46 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR46 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR46 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW47" description="Shadowed fuse word 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 47 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR47 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR47 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW48" description="Shadowed fuse word 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 48 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR48 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR48 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW49" description="Shadowed fuse word 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 49 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR49 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR49 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW50" description="Shadowed fuse word 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 50 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR50 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR50 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW51" description="Shadowed fuse word 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 51 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR51 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR51 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW52" description="Shadowed fuse word 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 52 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR52 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR52 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW53" description="Shadowed fuse word 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 53 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR53 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR53 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW54" description="Shadowed fuse word 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 54 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR54 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR54 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW55" description="Shadowed fuse word 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 55 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR55 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR55 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW56" description="Shadowed fuse word 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 56 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR56 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR56 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW57" description="Shadowed fuse word 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 57 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR57 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR57 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW58" description="Shadowed fuse word 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 58 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR58 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR58 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW59" description="Shadowed fuse word 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 59 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR59 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR59 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW60" description="Shadowed fuse word 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 60 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR60 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR60 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW61" description="Shadowed fuse word 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 61 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR61 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR61 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW62" description="Shadowed fuse word 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 62 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR62 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR62 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW63" description="Shadowed fuse word 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 63 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR63 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR63 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR2" description="BSEC shadowed fuses status register 2" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW64" description="Shadowed fuse word 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 64 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR64 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR64 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW65" description="Shadowed fuse word 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 65 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR65 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR65 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW66" description="Shadowed fuse word 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 66 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR66 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR66 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW67" description="Shadowed fuse word 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 67 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR67 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR67 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW68" description="Shadowed fuse word 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 68 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR68 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR68 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW69" description="Shadowed fuse word 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 69 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR69 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR69 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW70" description="Shadowed fuse word 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 70 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR70 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR70 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW71" description="Shadowed fuse word 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 71 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR71 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR71 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW72" description="Shadowed fuse word 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 72 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR72 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR72 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW73" description="Shadowed fuse word 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 73 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR73 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR73 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW74" description="Shadowed fuse word 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 74 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR74 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR74 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW75" description="Shadowed fuse word 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 75 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR75 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR75 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW76" description="Shadowed fuse word 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 76 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR76 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR76 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW77" description="Shadowed fuse word 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 77 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR77 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR77 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW78" description="Shadowed fuse word 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 78 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR78 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR78 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW79" description="Shadowed fuse word 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 79 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR79 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR79 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW80" description="Shadowed fuse word 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 80 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR80 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR80 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW81" description="Shadowed fuse word 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 81 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR81 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR81 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW82" description="Shadowed fuse word 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 82 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR82 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR82 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW83" description="Shadowed fuse word 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 83 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR83 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR83 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW84" description="Shadowed fuse word 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 84 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR84 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR84 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW85" description="Shadowed fuse word 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 85 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR85 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR85 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW86" description="Shadowed fuse word 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 86 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR86 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR86 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW87" description="Shadowed fuse word 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 87 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR87 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR87 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW88" description="Shadowed fuse word 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 88 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR88 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR88 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW89" description="Shadowed fuse word 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 89 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR89 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR89 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW90" description="Shadowed fuse word 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 90 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR90 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR90 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW91" description="Shadowed fuse word 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 91 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR91 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR91 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW92" description="Shadowed fuse word 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 92 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR92 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR92 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW93" description="Shadowed fuse word 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 93 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR93 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR93 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW94" description="Shadowed fuse word 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 94 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR94 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR94 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW95" description="Shadowed fuse word 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 95 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR95 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR95 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR3" description="BSEC shadowed fuses status register 3" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW96" description="Shadowed fuse word 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 96 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR96 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR96 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW97" description="Shadowed fuse word 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 97 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR97 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR97 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW98" description="Shadowed fuse word 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 98 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR98 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR98 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW99" description="Shadowed fuse word 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 99 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR99 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR99 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW100" description="Shadowed fuse word 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 100 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR100 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR100 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW101" description="Shadowed fuse word 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 101 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR101 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR101 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW102" description="Shadowed fuse word 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 102 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR102 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR102 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW103" description="Shadowed fuse word 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 103 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR103 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR103 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW104" description="Shadowed fuse word 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 104 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR104 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR104 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW105" description="Shadowed fuse word 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 105 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR105 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR105 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW106" description="Shadowed fuse word 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 106 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR106 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR106 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW107" description="Shadowed fuse word 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 107 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR107 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR107 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW108" description="Shadowed fuse word 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 108 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR108 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR108 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW109" description="Shadowed fuse word 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 109 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR109 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR109 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW110" description="Shadowed fuse word 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 110 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR110 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR110 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW111" description="Shadowed fuse word 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 111 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR111 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR111 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW112" description="Shadowed fuse word 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 112 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR112 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR112 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW113" description="Shadowed fuse word 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 113 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR113 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR113 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW114" description="Shadowed fuse word 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 114 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR114 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR114 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW115" description="Shadowed fuse word 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 115 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR115 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR115 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW116" description="Shadowed fuse word 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 116 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR116 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR116 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW117" description="Shadowed fuse word 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 117 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR117 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR117 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW118" description="Shadowed fuse word 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 118 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR118 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR118 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW119" description="Shadowed fuse word 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 119 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR119 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR119 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW120" description="Shadowed fuse word 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 120 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR120 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR120 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW121" description="Shadowed fuse word 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 121 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR121 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR121 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW122" description="Shadowed fuse word 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 122 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR122 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR122 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW123" description="Shadowed fuse word 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 123 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR123 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR123 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW124" description="Shadowed fuse word 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 124 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR124 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR124 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW125" description="Shadowed fuse word 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 125 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR125 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR125 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW126" description="Shadowed fuse word 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 126 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR126 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR126 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW127" description="Shadowed fuse word 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 127 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR127 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR127 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR4" description="BSEC shadowed fuses status register 4" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW128" description="Shadowed fuse word 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 128 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR128 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR128 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW129" description="Shadowed fuse word 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 129 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR129 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR129 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW130" description="Shadowed fuse word 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 130 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR130 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR130 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW131" description="Shadowed fuse word 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 131 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR131 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR131 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW132" description="Shadowed fuse word 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 132 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR132 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR132 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW133" description="Shadowed fuse word 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 133 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR133 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR133 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW134" description="Shadowed fuse word 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 134 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR134 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR134 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW135" description="Shadowed fuse word 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 135 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR135 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR135 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW136" description="Shadowed fuse word 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 136 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR136 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR136 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW137" description="Shadowed fuse word 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 137 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR137 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR137 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW138" description="Shadowed fuse word 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 138 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR138 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR138 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW139" description="Shadowed fuse word 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 139 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR139 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR139 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW140" description="Shadowed fuse word 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 140 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR140 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR140 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW141" description="Shadowed fuse word 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 141 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR141 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR141 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW142" description="Shadowed fuse word 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 142 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR142 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR142 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW143" description="Shadowed fuse word 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 143 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR143 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR143 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW144" description="Shadowed fuse word 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 144 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR144 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR144 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW145" description="Shadowed fuse word 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 145 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR145 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR145 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW146" description="Shadowed fuse word 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 146 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR146 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR146 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW147" description="Shadowed fuse word 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 147 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR147 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR147 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW148" description="Shadowed fuse word 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 148 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR148 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR148 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW149" description="Shadowed fuse word 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 149 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR149 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR149 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW150" description="Shadowed fuse word 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 150 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR150 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR150 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW151" description="Shadowed fuse word 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 151 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR151 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR151 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW152" description="Shadowed fuse word 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 152 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR152 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR152 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW153" description="Shadowed fuse word 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 153 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR153 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR153 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW154" description="Shadowed fuse word 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 154 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR154 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR154 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW155" description="Shadowed fuse word 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 155 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR155 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR155 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW156" description="Shadowed fuse word 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 156 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR156 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR156 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW157" description="Shadowed fuse word 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 157 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR157 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR157 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW158" description="Shadowed fuse word 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 158 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR158 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR158 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW159" description="Shadowed fuse word 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 159 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR159 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR159 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR5" description="BSEC shadowed fuses status register 5" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW160" description="Shadowed fuse word 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 160 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR160 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR160 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW161" description="Shadowed fuse word 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 161 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR161 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR161 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW162" description="Shadowed fuse word 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 162 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR162 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR162 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW163" description="Shadowed fuse word 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 163 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR163 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR163 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW164" description="Shadowed fuse word 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 164 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR164 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR164 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW165" description="Shadowed fuse word 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 165 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR165 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR165 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW166" description="Shadowed fuse word 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 166 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR166 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR166 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW167" description="Shadowed fuse word 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 167 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR167 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR167 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW168" description="Shadowed fuse word 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 168 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR168 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR168 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW169" description="Shadowed fuse word 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 169 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR169 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR169 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW170" description="Shadowed fuse word 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 170 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR170 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR170 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW171" description="Shadowed fuse word 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 171 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR171 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR171 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW172" description="Shadowed fuse word 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 172 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR172 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR172 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW173" description="Shadowed fuse word 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 173 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR173 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR173 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW174" description="Shadowed fuse word 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 174 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR174 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR174 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW175" description="Shadowed fuse word 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 175 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR175 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR175 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW176" description="Shadowed fuse word 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 176 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR176 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR176 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW177" description="Shadowed fuse word 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 177 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR177 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR177 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW178" description="Shadowed fuse word 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 178 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR178 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR178 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW179" description="Shadowed fuse word 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 179 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR179 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR179 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW180" description="Shadowed fuse word 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 180 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR180 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR180 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW181" description="Shadowed fuse word 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 181 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR181 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR181 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW182" description="Shadowed fuse word 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 182 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR182 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR182 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW183" description="Shadowed fuse word 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 183 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR183 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR183 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW184" description="Shadowed fuse word 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 184 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR184 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR184 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW185" description="Shadowed fuse word 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 185 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR185 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR185 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW186" description="Shadowed fuse word 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 186 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR186 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR186 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW187" description="Shadowed fuse word 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 187 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR187 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR187 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW188" description="Shadowed fuse word 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 188 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR188 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR188 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW189" description="Shadowed fuse word 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 189 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR189 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR189 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW190" description="Shadowed fuse word 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 190 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR190 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR190 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW191" description="Shadowed fuse word 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 191 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR191 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR191 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR6" description="BSEC shadowed fuses status register 6" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW192" description="Shadowed fuse word 192" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 192 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR192 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR192 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW193" description="Shadowed fuse word 193" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 193 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR193 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR193 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW194" description="Shadowed fuse word 194" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 194 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR194 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR194 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW195" description="Shadowed fuse word 195" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 195 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR195 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR195 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW196" description="Shadowed fuse word 196" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 196 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR196 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR196 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW197" description="Shadowed fuse word 197" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 197 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR197 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR197 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW198" description="Shadowed fuse word 198" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 198 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR198 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR198 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW199" description="Shadowed fuse word 199" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 199 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR199 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR199 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW200" description="Shadowed fuse word 200" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 200 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR200 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR200 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW201" description="Shadowed fuse word 201" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 201 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR201 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR201 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW202" description="Shadowed fuse word 202" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 202 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR202 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR202 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW203" description="Shadowed fuse word 203" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 203 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR203 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR203 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW204" description="Shadowed fuse word 204" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 204 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR204 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR204 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW205" description="Shadowed fuse word 205" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 205 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR205 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR205 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW206" description="Shadowed fuse word 206" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 206 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR206 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR206 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW207" description="Shadowed fuse word 207" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 207 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR207 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR207 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW208" description="Shadowed fuse word 208" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 208 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR208 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR208 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW209" description="Shadowed fuse word 209" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 209 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR209 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR209 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW210" description="Shadowed fuse word 210" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 210 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR210 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR210 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW211" description="Shadowed fuse word 211" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 211 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR211 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR211 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW212" description="Shadowed fuse word 212" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 212 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR212 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR212 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW213" description="Shadowed fuse word 213" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 213 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR213 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR213 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW214" description="Shadowed fuse word 214" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 214 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR214 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR214 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW215" description="Shadowed fuse word 215" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 215 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR215 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR215 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW216" description="Shadowed fuse word 216" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 216 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR216 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR216 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW217" description="Shadowed fuse word 217" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 217 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR217 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR217 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW218" description="Shadowed fuse word 218" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 218 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR218 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR218 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW219" description="Shadowed fuse word 219" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 219 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR219 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR219 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW220" description="Shadowed fuse word 220" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 220 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR220 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR220 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW221" description="Shadowed fuse word 221" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 221 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR221 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR221 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW222" description="Shadowed fuse word 222" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 222 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR222 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR222 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW223" description="Shadowed fuse word 223" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 223 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR223 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR223 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR7" description="BSEC shadowed fuses status register 7" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW224" description="Shadowed fuse word 224" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 224 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR224 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR224 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW225" description="Shadowed fuse word 225" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 225 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR225 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR225 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW226" description="Shadowed fuse word 226" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 226 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR226 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR226 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW227" description="Shadowed fuse word 227" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 227 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR227 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR227 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW228" description="Shadowed fuse word 228" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 228 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR228 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR228 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW229" description="Shadowed fuse word 229" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 229 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR229 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR229 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW230" description="Shadowed fuse word 230" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 230 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR230 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR230 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW231" description="Shadowed fuse word 231" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 231 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR231 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR231 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW232" description="Shadowed fuse word 232" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 232 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR232 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR232 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW233" description="Shadowed fuse word 233" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 233 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR233 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR233 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW234" description="Shadowed fuse word 234" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 234 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR234 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR234 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW235" description="Shadowed fuse word 235" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 235 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR235 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR235 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW236" description="Shadowed fuse word 236" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 236 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR236 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR236 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW237" description="Shadowed fuse word 237" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 237 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR237 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR237 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW238" description="Shadowed fuse word 238" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 238 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR238 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR238 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW239" description="Shadowed fuse word 239" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 239 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR239 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR239 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW240" description="Shadowed fuse word 240" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 240 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR240 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR240 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW241" description="Shadowed fuse word 241" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 241 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR241 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR241 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW242" description="Shadowed fuse word 242" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 242 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR242 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR242 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW243" description="Shadowed fuse word 243" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 243 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR243 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR243 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW244" description="Shadowed fuse word 244" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 244 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR244 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR244 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW245" description="Shadowed fuse word 245" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 245 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR245 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR245 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW246" description="Shadowed fuse word 246" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 246 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR246 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR246 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW247" description="Shadowed fuse word 247" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 247 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR247 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR247 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW248" description="Shadowed fuse word 248" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 248 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR248 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR248 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW249" description="Shadowed fuse word 249" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 249 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR249 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR249 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW250" description="Shadowed fuse word 250" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 250 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR250 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR250 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW251" description="Shadowed fuse word 251" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 251 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR251 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR251 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW252" description="Shadowed fuse word 252" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 252 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR252 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR252 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW253" description="Shadowed fuse word 253" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 253 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR253 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR253 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW254" description="Shadowed fuse word 254" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 254 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR254 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR254 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW255" description="Shadowed fuse word 255" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 255 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR255 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR255 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR8" description="BSEC shadowed fuses status register 8" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW256" description="Shadowed fuse word 256" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 256 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR256 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR256 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW257" description="Shadowed fuse word 257" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 257 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR257 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR257 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW258" description="Shadowed fuse word 258" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 258 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR258 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR258 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW259" description="Shadowed fuse word 259" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 259 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR259 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR259 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW260" description="Shadowed fuse word 260" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 260 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR260 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR260 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW261" description="Shadowed fuse word 261" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 261 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR261 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR261 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW262" description="Shadowed fuse word 262" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 262 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR262 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR262 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW263" description="Shadowed fuse word 263" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 263 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR263 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR263 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW264" description="Shadowed fuse word 264" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 264 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR264 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR264 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW265" description="Shadowed fuse word 265" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 265 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR265 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR265 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW266" description="Shadowed fuse word 266" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 266 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR266 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR266 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW267" description="Shadowed fuse word 267" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 267 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR267 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR267 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW268" description="Shadowed fuse word 268" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 268 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR268 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR268 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW269" description="Shadowed fuse word 269" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 269 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR269 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR269 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW270" description="Shadowed fuse word 270" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 270 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR270 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR270 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW271" description="Shadowed fuse word 271" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 271 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR271 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR271 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW272" description="Shadowed fuse word 272" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 272 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR272 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR272 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW273" description="Shadowed fuse word 273" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 273 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR273 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR273 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW274" description="Shadowed fuse word 274" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 274 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR274 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR274 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW275" description="Shadowed fuse word 275" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 275 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR275 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR275 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW276" description="Shadowed fuse word 276" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 276 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR276 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR276 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW277" description="Shadowed fuse word 277" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 277 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR277 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR277 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW278" description="Shadowed fuse word 278" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 278 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR278 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR278 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW279" description="Shadowed fuse word 279" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 279 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR279 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR279 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW280" description="Shadowed fuse word 280" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 280 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR280 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR280 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW281" description="Shadowed fuse word 281" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 281 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR281 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR281 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW282" description="Shadowed fuse word 282" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 282 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR282 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR282 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW283" description="Shadowed fuse word 283" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 283 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR283 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR283 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW284" description="Shadowed fuse word 284" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 284 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR284 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR284 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW285" description="Shadowed fuse word 285" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 285 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR285 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR285 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW286" description="Shadowed fuse word 286" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 286 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR286 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR286 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW287" description="Shadowed fuse word 287" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 287 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR287 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR287 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR9" description="BSEC shadowed fuses status register 9" start="+0x964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW288" description="Shadowed fuse word 288" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 288 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR288 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR288 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW289" description="Shadowed fuse word 289" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 289 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR289 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR289 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW290" description="Shadowed fuse word 290" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 290 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR290 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR290 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW291" description="Shadowed fuse word 291" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 291 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR291 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR291 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW292" description="Shadowed fuse word 292" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 292 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR292 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR292 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW293" description="Shadowed fuse word 293" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 293 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR293 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR293 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW294" description="Shadowed fuse word 294" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 294 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR294 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR294 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW295" description="Shadowed fuse word 295" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 295 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR295 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR295 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW296" description="Shadowed fuse word 296" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 296 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR296 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR296 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW297" description="Shadowed fuse word 297" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 297 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR297 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR297 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW298" description="Shadowed fuse word 298" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 298 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR298 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR298 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW299" description="Shadowed fuse word 299" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 299 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR299 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR299 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW300" description="Shadowed fuse word 300" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 300 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR300 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR300 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW301" description="Shadowed fuse word 301" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 301 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR301 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR301 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW302" description="Shadowed fuse word 302" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 302 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR302 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR302 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW303" description="Shadowed fuse word 303" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 303 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR303 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR303 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW304" description="Shadowed fuse word 304" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 304 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR304 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR304 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW305" description="Shadowed fuse word 305" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 305 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR305 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR305 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW306" description="Shadowed fuse word 306" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 306 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR306 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR306 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW307" description="Shadowed fuse word 307" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 307 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR307 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR307 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW308" description="Shadowed fuse word 308" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 308 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR308 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR308 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW309" description="Shadowed fuse word 309" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 309 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR309 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR309 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW310" description="Shadowed fuse word 310" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 310 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR310 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR310 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW311" description="Shadowed fuse word 311" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 311 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR311 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR311 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW312" description="Shadowed fuse word 312" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 312 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR312 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR312 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW313" description="Shadowed fuse word 313" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 313 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR313 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR313 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW314" description="Shadowed fuse word 314" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 314 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR314 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR314 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW315" description="Shadowed fuse word 315" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 315 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR315 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR315 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW316" description="Shadowed fuse word 316" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 316 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR316 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR316 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW317" description="Shadowed fuse word 317" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 317 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR317 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR317 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW318" description="Shadowed fuse word 318" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 318 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR318 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR318 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW319" description="Shadowed fuse word 319" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 319 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR319 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR319 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR10" description="BSEC shadowed fuses status register 10" start="+0x968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW320" description="Shadowed fuse word 320" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 320 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR320 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR320 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW321" description="Shadowed fuse word 321" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 321 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR321 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR321 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW322" description="Shadowed fuse word 322" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 322 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR322 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR322 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW323" description="Shadowed fuse word 323" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 323 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR323 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR323 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW324" description="Shadowed fuse word 324" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 324 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR324 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR324 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW325" description="Shadowed fuse word 325" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 325 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR325 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR325 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW326" description="Shadowed fuse word 326" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 326 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR326 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR326 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW327" description="Shadowed fuse word 327" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 327 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR327 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR327 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW328" description="Shadowed fuse word 328" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 328 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR328 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR328 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW329" description="Shadowed fuse word 329" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 329 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR329 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR329 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW330" description="Shadowed fuse word 330" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 330 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR330 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR330 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW331" description="Shadowed fuse word 331" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 331 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR331 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR331 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW332" description="Shadowed fuse word 332" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 332 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR332 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR332 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW333" description="Shadowed fuse word 333" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 333 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR333 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR333 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW334" description="Shadowed fuse word 334" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 334 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR334 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR334 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW335" description="Shadowed fuse word 335" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 335 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR335 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR335 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW336" description="Shadowed fuse word 336" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 336 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR336 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR336 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW337" description="Shadowed fuse word 337" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 337 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR337 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR337 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW338" description="Shadowed fuse word 338" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 338 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR338 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR338 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW339" description="Shadowed fuse word 339" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 339 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR339 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR339 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW340" description="Shadowed fuse word 340" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 340 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR340 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR340 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW341" description="Shadowed fuse word 341" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 341 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR341 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR341 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW342" description="Shadowed fuse word 342" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 342 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR342 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR342 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW343" description="Shadowed fuse word 343" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 343 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR343 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR343 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW344" description="Shadowed fuse word 344" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 344 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR344 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR344 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW345" description="Shadowed fuse word 345" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 345 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR345 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR345 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW346" description="Shadowed fuse word 346" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 346 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR346 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR346 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW347" description="Shadowed fuse word 347" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 347 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR347 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR347 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW348" description="Shadowed fuse word 348" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 348 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR348 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR348 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW349" description="Shadowed fuse word 349" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 349 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR349 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR349 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW350" description="Shadowed fuse word 350" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 350 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR350 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR350 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW351" description="Shadowed fuse word 351" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 351 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR351 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR351 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR11" description="BSEC shadowed fuses status register 11" start="+0x96C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW352" description="Shadowed fuse word 352" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 352 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR352 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR352 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW353" description="Shadowed fuse word 353" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 353 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR353 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR353 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW354" description="Shadowed fuse word 354" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 354 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR354 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR354 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW355" description="Shadowed fuse word 355" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 355 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR355 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR355 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW356" description="Shadowed fuse word 356" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 356 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR356 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR356 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW357" description="Shadowed fuse word 357" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 357 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR357 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR357 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW358" description="Shadowed fuse word 358" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 358 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR358 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR358 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW359" description="Shadowed fuse word 359" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 359 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR359 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR359 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW360" description="Shadowed fuse word 360" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 360 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR360 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR360 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW361" description="Shadowed fuse word 361" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 361 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR361 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR361 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW362" description="Shadowed fuse word 362" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 362 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR362 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR362 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW363" description="Shadowed fuse word 363" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 363 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR363 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR363 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW364" description="Shadowed fuse word 364" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 364 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR364 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR364 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW365" description="Shadowed fuse word 365" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 365 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR365 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR365 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW366" description="Shadowed fuse word 366" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 366 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR366 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR366 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW367" description="Shadowed fuse word 367" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 367 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR367 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR367 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW368" description="Shadowed fuse word 368" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 368 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR368 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR368 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW369" description="Shadowed fuse word 369" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 369 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR369 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR369 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW370" description="Shadowed fuse word 370" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 370 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR370 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR370 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW371" description="Shadowed fuse word 371" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 371 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR371 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR371 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW372" description="Shadowed fuse word 372" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 372 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR372 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR372 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW373" description="Shadowed fuse word 373" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 373 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR373 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR373 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW374" description="Shadowed fuse word 374" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 374 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR374 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR374 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW375" description="Shadowed fuse word 375" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 375 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR375 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR375 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW376" description="Shadowed fuse word 376" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 376 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR376 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR376 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW377" description="Shadowed fuse word 377" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 377 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR377 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR377 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW378" description="Shadowed fuse word 378" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 378 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR378 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR378 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW379" description="Shadowed fuse word 379" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 379 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR379 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR379 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW380" description="Shadowed fuse word 380" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 380 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR380 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR380 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW381" description="Shadowed fuse word 381" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 381 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR381 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR381 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW382" description="Shadowed fuse word 382" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 382 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR382 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR382 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW383" description="Shadowed fuse word 383" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 383 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR383 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR383 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPCR" description="BSEC OTP control register" start="+0xC04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDR" description="Fuse word address" start="0" size="9" access="Read/Write" />
+      <BitField name="PROG" description="Fuse word programming" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word read operation is required" start="0x0" />
+        <Enum name="B_0x1" description="Fuse word programming operation is required" start="0x1" />
+      </BitField>
+      <BitField name="PPLOCK" description="Permanent programming lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word at address ADDR[8:0] is programmed normally." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word at address ADDR[8:0] is locked, preventing further modifications." start="0x1" />
+      </BitField>
+      <BitField name="LASTCID" description="Last CID" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_WDR" description="BSEC write data register" start="+0xC08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRDATA" description="OTP write data" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_SCRATCHR0" description="BSEC scratch register 0" start="+0xE00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR1" description="BSEC scratch register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR2" description="BSEC scratch register 2" start="+0xE08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR3" description="BSEC scratch register 3" start="+0xE0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_LOCKR" description="BSEC lock register" start="+0xE10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GWLOCK" description="Global write lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to BSEC registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to BSEC registers are ignored (fuse programming and fuse reload disabled)" start="0x1" />
+      </BitField>
+      <BitField name="HKLOCK" description="Hardware key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Derived hardware unique key (DHUK) in SAES peripheral is usable if HVALID is set in BSEC_SR" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK) in SAES peripheral is not usable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_JTAGINR" description="BSEC JTAG input register" start="+0xE14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATAIN" description="JTAG input data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_JTAGOUTR" description="BSEC JTAG output register" start="+0xE18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATAOUT" description="JTAG output data" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_UNMAPR" description="BSEC unmap register" start="+0xE24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNMAP" description="Unmap key" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SR" description="BSEC status register" start="+0xE40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HVALID" description="Hardware key valid" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Derived hardware unique key (DHUK) feature cannot be used in SAES peripheral" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK) feature can be used in SAES peripheral" start="0x1" />
+      </BitField>
+      <BitField name="DBGREQ" description="debug request" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Host debugger is not requesting debug" start="0x0" />
+        <Enum name="B_0x1" description="Host debugger is requesting debug" start="0x1" />
+      </BitField>
+      <BitField name="NVSTATE" description="Non-volatile state" start="26" size="6" access="ReadOnly">
+        <Enum name="B_0x16" description="BSEC is in open state" start="0x16" />
+        <Enum name="B_0x0D" description="BSEC is in closed state" start="0x0D" />
+        <Enum name="B_0x7" description="BSEC is in invalid state." start="0x7" />
+        <Enum name="B_0x23" description="BSEC is in invalid state, with an active confirmed tamper triggered in the device." start="0x23" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPSR" description="BSEC OTP status register" start="+0xE44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSY" description="Busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSEC is idle" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is busy" start="0x1" />
+      </BitField>
+      <BitField name="INIT_DONE" description="Initialization done" start="1" size="1" access="ReadOnly" />
+      <BitField name="HIDEUP" description="Hide upper fuse words" start="2" size="1" access="ReadOnly" />
+      <BitField name="OTPNVIR" description="OTP not virgin" start="4" size="1" access="ReadOnly" />
+      <BitField name="OTPERR" description="OTP with error" start="5" size="1" access="ReadOnly" />
+      <BitField name="OTPSEC" description="OTP with single error correction" start="6" size="1" access="ReadOnly" />
+      <BitField name="PROGFAIL" description="Programming failed" start="16" size="1" access="ReadOnly" />
+      <BitField name="DISTURBF" description="Disturb flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="DEDF" description="Double error detection flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="SECF" description="Single error correction flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="PPLF" description="Permanent programming lock flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="PPLMF" description="Permanent programming lock mismatch flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="AMEF" description="Addresses mismatch error flag " start="22" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_EPOCHR0" description="BSEC epoch register" start="+0xE80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPOCH" description="epoch" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_EPOCHR1" description="BSEC epoch register" start="+0xE84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPOCH" description="epoch" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_EPOCH_SELR" description="BSEC epoch select register" start="+0xE88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPSEL" description="Epoch selection. This value is wired out to the SAES peripheral." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES peripheral uses BSEC_EPOCHR0 as EPOCH value." start="0x0" />
+        <Enum name="B_0x1" description="SAES peripheral uses BSEC_EPOCHR1 as EPOCH value." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_DBGCR" description="BSEC Debug" start="+0xE8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNLOCK" description="any other value: debug not authorized (provided BSEC state is not OPEN)" start="8" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="non-secure debug authorized when the level indicated in BSEC_HDPLSR is greater than or equal to the level given by AUTH_HDPL" start="0xB4" />
+      </BitField>
+      <BitField name="AUTH_HDPL" description="level at which debug may be opened." start="16" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="Level 0" start="0xB4" />
+        <Enum name="B_0x51" description="Level 1" start="0x51" />
+        <Enum name="B_0x8A" description="Level 2" start="0x8A" />
+        <Enum name="B_0x6F" description="Level 3" start="0x6F" />
+      </BitField>
+      <BitField name="AUTH_SEC" description="any other value: secure debug not authorized (provided BSEC state is not OPEN)" start="24" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="secure debug authorized when UNLOCK = 0xB4 and the level indicated in BSEC_HDPLSR is greater than or equal to the level indicated by AUTH_HDPL" start="0xB4" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_AP_UNLOCK" description="BSEC AP Unlock" start="+0xE90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNLOCK" description="any other value: do not unlock" start="0" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="unlock the DBG_MCU AP interface." start="0xB4" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_HDPLSR" description="BSEC HDPL" start="+0xE94" size="4" reset_value="0x000000B4" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPL" description="current HDPL" start="0" size="8" access="ReadOnly">
+        <Enum name="B_0xB4" description="Level 0" start="0xB4" />
+        <Enum name="B_0x51" description="Level 1" start="0x51" />
+        <Enum name="B_0x8A" description="Level 2" start="0x8A" />
+        <Enum name="B_0x6F" description="Level 3" start="0x6F" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_HDPLCR" description="BSEC HDPL control" start="+0xE98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INCR_HDPL" description="Increment HDPL" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_NEXTLR" description="BSEC Next HDPL" start="+0xE9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INCR" description="Increment" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR0" description="BSEC write once scratch register 0" start="+0xF40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR1" description="BSEC write once scratch register 1" start="+0xF44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR2" description="BSEC write once scratch register 2" start="+0xF48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR3" description="BSEC write once scratch register 3" start="+0xF4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR4" description="BSEC write once scratch register 4" start="+0xF50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR5" description="BSEC write once scratch register 5" start="+0xF54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR6" description="BSEC write once scratch register 6" start="+0xF58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR7" description="BSEC write once scratch register 7" start="+0xF5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_HRCR" description="BSEC hot reset count register" start="+0xFE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRC" description="hot reset counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_WRCR" description="BSEC warm reset count register" start="+0xFEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRC" description="Warm reset counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="BSEC_S" description="Boot and security control" start="0x56009000">
+    <Register name="BSEC_FVR0" description="BSEC fuse word 0 value register" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR1" description="BSEC fuse word 1 value register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR2" description="BSEC fuse word 2 value register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR3" description="BSEC fuse word 3 value register" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR4" description="BSEC fuse word 4 value register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR5" description="BSEC fuse word 5 value register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR6" description="BSEC fuse word 6 value register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR7" description="BSEC fuse word 7 value register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR8" description="BSEC fuse word 8 value register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR9" description="BSEC fuse word 9 value register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR10" description="BSEC fuse word 10 value register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR11" description="BSEC fuse word 11 value register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR12" description="BSEC fuse word 12 value register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR13" description="BSEC fuse word 13 value register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR14" description="BSEC fuse word 14 value register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR15" description="BSEC fuse word 15 value register" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR16" description="BSEC fuse word 16 value register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR17" description="BSEC fuse word 17 value register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR18" description="BSEC fuse word 18 value register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR19" description="BSEC fuse word 19 value register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR20" description="BSEC fuse word 20 value register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR21" description="BSEC fuse word 21 value register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR22" description="BSEC fuse word 22 value register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR23" description="BSEC fuse word 23 value register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR24" description="BSEC fuse word 24 value register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR25" description="BSEC fuse word 25 value register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR26" description="BSEC fuse word 26 value register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR27" description="BSEC fuse word 27 value register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR28" description="BSEC fuse word 28 value register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR29" description="BSEC fuse word 29 value register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR30" description="BSEC fuse word 30 value register" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR31" description="BSEC fuse word 31 value register" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR32" description="BSEC fuse word 32 value register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR33" description="BSEC fuse word 33 value register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR34" description="BSEC fuse word 34 value register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR35" description="BSEC fuse word 35 value register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR36" description="BSEC fuse word 36 value register" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR37" description="BSEC fuse word 37 value register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR38" description="BSEC fuse word 38 value register" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR39" description="BSEC fuse word 39 value register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR40" description="BSEC fuse word 40 value register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR41" description="BSEC fuse word 41 value register" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR42" description="BSEC fuse word 42 value register" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR43" description="BSEC fuse word 43 value register" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR44" description="BSEC fuse word 44 value register" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR45" description="BSEC fuse word 45 value register" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR46" description="BSEC fuse word 46 value register" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR47" description="BSEC fuse word 47 value register" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR48" description="BSEC fuse word 48 value register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR49" description="BSEC fuse word 49 value register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR50" description="BSEC fuse word 50 value register" start="+0xC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR51" description="BSEC fuse word 51 value register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR52" description="BSEC fuse word 52 value register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR53" description="BSEC fuse word 53 value register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR54" description="BSEC fuse word 54 value register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR55" description="BSEC fuse word 55 value register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR56" description="BSEC fuse word 56 value register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR57" description="BSEC fuse word 57 value register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR58" description="BSEC fuse word 58 value register" start="+0xE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR59" description="BSEC fuse word 59 value register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR60" description="BSEC fuse word 60 value register" start="+0xF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR61" description="BSEC fuse word 61 value register" start="+0xF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR62" description="BSEC fuse word 62 value register" start="+0xF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR63" description="BSEC fuse word 63 value register" start="+0xFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR64" description="BSEC fuse word 64 value register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR65" description="BSEC fuse word 65 value register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR66" description="BSEC fuse word 66 value register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR67" description="BSEC fuse word 67 value register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR68" description="BSEC fuse word 68 value register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR69" description="BSEC fuse word 69 value register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR70" description="BSEC fuse word 70 value register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR71" description="BSEC fuse word 71 value register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR72" description="BSEC fuse word 72 value register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR73" description="BSEC fuse word 73 value register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR74" description="BSEC fuse word 74 value register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR75" description="BSEC fuse word 75 value register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR76" description="BSEC fuse word 76 value register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR77" description="BSEC fuse word 77 value register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR78" description="BSEC fuse word 78 value register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR79" description="BSEC fuse word 79 value register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR80" description="BSEC fuse word 80 value register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR81" description="BSEC fuse word 81 value register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR82" description="BSEC fuse word 82 value register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR83" description="BSEC fuse word 83 value register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR84" description="BSEC fuse word 84 value register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR85" description="BSEC fuse word 85 value register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR86" description="BSEC fuse word 86 value register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR87" description="BSEC fuse word 87 value register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR88" description="BSEC fuse word 88 value register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR89" description="BSEC fuse word 89 value register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR90" description="BSEC fuse word 90 value register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR91" description="BSEC fuse word 91 value register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR92" description="BSEC fuse word 92 value register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR93" description="BSEC fuse word 93 value register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR94" description="BSEC fuse word 94 value register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR95" description="BSEC fuse word 95 value register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR96" description="BSEC fuse word 96 value register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR97" description="BSEC fuse word 97 value register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR98" description="BSEC fuse word 98 value register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR99" description="BSEC fuse word 99 value register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR100" description="BSEC fuse word 100 value register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR101" description="BSEC fuse word 101 value register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR102" description="BSEC fuse word 102 value register" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR103" description="BSEC fuse word 103 value register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR104" description="BSEC fuse word 104 value register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR105" description="BSEC fuse word 105 value register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR106" description="BSEC fuse word 106 value register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR107" description="BSEC fuse word 107 value register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR108" description="BSEC fuse word 108 value register" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR109" description="BSEC fuse word 109 value register" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR110" description="BSEC fuse word 110 value register" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR111" description="BSEC fuse word 111 value register" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR112" description="BSEC fuse word 112 value register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR113" description="BSEC fuse word 113 value register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR114" description="BSEC fuse word 114 value register" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR115" description="BSEC fuse word 115 value register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR116" description="BSEC fuse word 116 value register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR117" description="BSEC fuse word 117 value register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR118" description="BSEC fuse word 118 value register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR119" description="BSEC fuse word 119 value register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR120" description="BSEC fuse word 120 value register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR121" description="BSEC fuse word 121 value register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR122" description="BSEC fuse word 122 value register" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR123" description="BSEC fuse word 123 value register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR124" description="BSEC fuse word 124 value register" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR125" description="BSEC fuse word 125 value register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR126" description="BSEC fuse word 126 value register" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR127" description="BSEC fuse word 127 value register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR128" description="BSEC fuse word 128 value register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR129" description="BSEC fuse word 129 value register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR130" description="BSEC fuse word 130 value register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR131" description="BSEC fuse word 131 value register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR132" description="BSEC fuse word 132 value register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR133" description="BSEC fuse word 133 value register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR134" description="BSEC fuse word 134 value register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR135" description="BSEC fuse word 135 value register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR136" description="BSEC fuse word 136 value register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR137" description="BSEC fuse word 137 value register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR138" description="BSEC fuse word 138 value register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR139" description="BSEC fuse word 139 value register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR140" description="BSEC fuse word 140 value register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR141" description="BSEC fuse word 141 value register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR142" description="BSEC fuse word 142 value register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR143" description="BSEC fuse word 143 value register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR144" description="BSEC fuse word 144 value register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR145" description="BSEC fuse word 145 value register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR146" description="BSEC fuse word 146 value register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR147" description="BSEC fuse word 147 value register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR148" description="BSEC fuse word 148 value register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR149" description="BSEC fuse word 149 value register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR150" description="BSEC fuse word 150 value register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR151" description="BSEC fuse word 151 value register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR152" description="BSEC fuse word 152 value register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR153" description="BSEC fuse word 153 value register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR154" description="BSEC fuse word 154 value register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR155" description="BSEC fuse word 155 value register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR156" description="BSEC fuse word 156 value register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR157" description="BSEC fuse word 157 value register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR158" description="BSEC fuse word 158 value register" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR159" description="BSEC fuse word 159 value register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR160" description="BSEC fuse word 160 value register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR161" description="BSEC fuse word 161 value register" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR162" description="BSEC fuse word 162 value register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR163" description="BSEC fuse word 163 value register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR164" description="BSEC fuse word 164 value register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR165" description="BSEC fuse word 165 value register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR166" description="BSEC fuse word 166 value register" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR167" description="BSEC fuse word 167 value register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR168" description="BSEC fuse word 168 value register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR169" description="BSEC fuse word 169 value register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR170" description="BSEC fuse word 170 value register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR171" description="BSEC fuse word 171 value register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR172" description="BSEC fuse word 172 value register" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR173" description="BSEC fuse word 173 value register" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR174" description="BSEC fuse word 174 value register" start="+0x2B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR175" description="BSEC fuse word 175 value register" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR176" description="BSEC fuse word 176 value register" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR177" description="BSEC fuse word 177 value register" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR178" description="BSEC fuse word 178 value register" start="+0x2C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR179" description="BSEC fuse word 179 value register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR180" description="BSEC fuse word 180 value register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR181" description="BSEC fuse word 181 value register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR182" description="BSEC fuse word 182 value register" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR183" description="BSEC fuse word 183 value register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR184" description="BSEC fuse word 184 value register" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR185" description="BSEC fuse word 185 value register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR186" description="BSEC fuse word 186 value register" start="+0x2E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR187" description="BSEC fuse word 187 value register" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR188" description="BSEC fuse word 188 value register" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR189" description="BSEC fuse word 189 value register" start="+0x2F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR190" description="BSEC fuse word 190 value register" start="+0x2F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR191" description="BSEC fuse word 191 value register" start="+0x2FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR192" description="BSEC fuse word 192 value register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR193" description="BSEC fuse word 193 value register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR194" description="BSEC fuse word 194 value register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR195" description="BSEC fuse word 195 value register" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR196" description="BSEC fuse word 196 value register" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR197" description="BSEC fuse word 197 value register" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR198" description="BSEC fuse word 198 value register" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR199" description="BSEC fuse word 199 value register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR200" description="BSEC fuse word 200 value register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR201" description="BSEC fuse word 201 value register" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR202" description="BSEC fuse word 202 value register" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR203" description="BSEC fuse word 203 value register" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR204" description="BSEC fuse word 204 value register" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR205" description="BSEC fuse word 205 value register" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR206" description="BSEC fuse word 206 value register" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR207" description="BSEC fuse word 207 value register" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR208" description="BSEC fuse word 208 value register" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR209" description="BSEC fuse word 209 value register" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR210" description="BSEC fuse word 210 value register" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR211" description="BSEC fuse word 211 value register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR212" description="BSEC fuse word 212 value register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR213" description="BSEC fuse word 213 value register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR214" description="BSEC fuse word 214 value register" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR215" description="BSEC fuse word 215 value register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR216" description="BSEC fuse word 216 value register" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR217" description="BSEC fuse word 217 value register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR218" description="BSEC fuse word 218 value register" start="+0x368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR219" description="BSEC fuse word 219 value register" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR220" description="BSEC fuse word 220 value register" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR221" description="BSEC fuse word 221 value register" start="+0x374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR222" description="BSEC fuse word 222 value register" start="+0x378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR223" description="BSEC fuse word 223 value register" start="+0x37C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR224" description="BSEC fuse word 224 value register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR225" description="BSEC fuse word 225 value register" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR226" description="BSEC fuse word 226 value register" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR227" description="BSEC fuse word 227 value register" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR228" description="BSEC fuse word 228 value register" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR229" description="BSEC fuse word 229 value register" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR230" description="BSEC fuse word 230 value register" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR231" description="BSEC fuse word 231 value register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR232" description="BSEC fuse word 232 value register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR233" description="BSEC fuse word 233 value register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR234" description="BSEC fuse word 234 value register" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR235" description="BSEC fuse word 235 value register" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR236" description="BSEC fuse word 236 value register" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR237" description="BSEC fuse word 237 value register" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR238" description="BSEC fuse word 238 value register" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR239" description="BSEC fuse word 239 value register" start="+0x3BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR240" description="BSEC fuse word 240 value register" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR241" description="BSEC fuse word 241 value register" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR242" description="BSEC fuse word 242 value register" start="+0x3C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR243" description="BSEC fuse word 243 value register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR244" description="BSEC fuse word 244 value register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR245" description="BSEC fuse word 245 value register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR246" description="BSEC fuse word 246 value register" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR247" description="BSEC fuse word 247 value register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR248" description="BSEC fuse word 248 value register" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR249" description="BSEC fuse word 249 value register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR250" description="BSEC fuse word 250 value register" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR251" description="BSEC fuse word 251 value register" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR252" description="BSEC fuse word 252 value register" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR253" description="BSEC fuse word 253 value register" start="+0x3F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR254" description="BSEC fuse word 254 value register" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR255" description="BSEC fuse word 255 value register" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR256" description="BSEC fuse word 256 value register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR257" description="BSEC fuse word 257 value register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR258" description="BSEC fuse word 258 value register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR259" description="BSEC fuse word 259 value register" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR260" description="BSEC fuse word 260 value register" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR261" description="BSEC fuse word 261 value register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR262" description="BSEC fuse word 262 value register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR263" description="BSEC fuse word 263 value register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR264" description="BSEC fuse word 264 value register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR265" description="BSEC fuse word 265 value register" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR266" description="BSEC fuse word 266 value register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR267" description="BSEC fuse word 267 value register" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR268" description="BSEC fuse word 268 value register" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR269" description="BSEC fuse word 269 value register" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR270" description="BSEC fuse word 270 value register" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR271" description="BSEC fuse word 271 value register" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR272" description="BSEC fuse word 272 value register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR273" description="BSEC fuse word 273 value register" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR274" description="BSEC fuse word 274 value register" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR275" description="BSEC fuse word 275 value register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR276" description="BSEC fuse word 276 value register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR277" description="BSEC fuse word 277 value register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR278" description="BSEC fuse word 278 value register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR279" description="BSEC fuse word 279 value register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR280" description="BSEC fuse word 280 value register" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR281" description="BSEC fuse word 281 value register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR282" description="BSEC fuse word 282 value register" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR283" description="BSEC fuse word 283 value register" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR284" description="BSEC fuse word 284 value register" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR285" description="BSEC fuse word 285 value register" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR286" description="BSEC fuse word 286 value register" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR287" description="BSEC fuse word 287 value register" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR288" description="BSEC fuse word 288 value register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR289" description="BSEC fuse word 289 value register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR290" description="BSEC fuse word 290 value register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR291" description="BSEC fuse word 291 value register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR292" description="BSEC fuse word 292 value register" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR293" description="BSEC fuse word 293 value register" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR294" description="BSEC fuse word 294 value register" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR295" description="BSEC fuse word 295 value register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR296" description="BSEC fuse word 296 value register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR297" description="BSEC fuse word 297 value register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR298" description="BSEC fuse word 298 value register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR299" description="BSEC fuse word 299 value register" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR300" description="BSEC fuse word 300 value register" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR301" description="BSEC fuse word 301 value register" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR302" description="BSEC fuse word 302 value register" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR303" description="BSEC fuse word 303 value register" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR304" description="BSEC fuse word 304 value register" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR305" description="BSEC fuse word 305 value register" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR306" description="BSEC fuse word 306 value register" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR307" description="BSEC fuse word 307 value register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR308" description="BSEC fuse word 308 value register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR309" description="BSEC fuse word 309 value register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR310" description="BSEC fuse word 310 value register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR311" description="BSEC fuse word 311 value register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR312" description="BSEC fuse word 312 value register" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR313" description="BSEC fuse word 313 value register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR314" description="BSEC fuse word 314 value register" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR315" description="BSEC fuse word 315 value register" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR316" description="BSEC fuse word 316 value register" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR317" description="BSEC fuse word 317 value register" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR318" description="BSEC fuse word 318 value register" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR319" description="BSEC fuse word 319 value register" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR320" description="BSEC fuse word 320 value register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR321" description="BSEC fuse word 321 value register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR322" description="BSEC fuse word 322 value register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR323" description="BSEC fuse word 323 value register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR324" description="BSEC fuse word 324 value register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR325" description="BSEC fuse word 325 value register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR326" description="BSEC fuse word 326 value register" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR327" description="BSEC fuse word 327 value register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR328" description="BSEC fuse word 328 value register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR329" description="BSEC fuse word 329 value register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR330" description="BSEC fuse word 330 value register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR331" description="BSEC fuse word 331 value register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR332" description="BSEC fuse word 332 value register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR333" description="BSEC fuse word 333 value register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR334" description="BSEC fuse word 334 value register" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR335" description="BSEC fuse word 335 value register" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR336" description="BSEC fuse word 336 value register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR337" description="BSEC fuse word 337 value register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR338" description="BSEC fuse word 338 value register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR339" description="BSEC fuse word 339 value register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR340" description="BSEC fuse word 340 value register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR341" description="BSEC fuse word 341 value register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR342" description="BSEC fuse word 342 value register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR343" description="BSEC fuse word 343 value register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR344" description="BSEC fuse word 344 value register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR345" description="BSEC fuse word 345 value register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR346" description="BSEC fuse word 346 value register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR347" description="BSEC fuse word 347 value register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR348" description="BSEC fuse word 348 value register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR349" description="BSEC fuse word 349 value register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR350" description="BSEC fuse word 350 value register" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR351" description="BSEC fuse word 351 value register" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR352" description="BSEC fuse word 352 value register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR353" description="BSEC fuse word 353 value register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR354" description="BSEC fuse word 354 value register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR355" description="BSEC fuse word 355 value register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR356" description="BSEC fuse word 356 value register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR357" description="BSEC fuse word 357 value register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR358" description="BSEC fuse word 358 value register" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR359" description="BSEC fuse word 359 value register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR360" description="BSEC fuse word 360 value register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR361" description="BSEC fuse word 361 value register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR362" description="BSEC fuse word 362 value register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR363" description="BSEC fuse word 363 value register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR364" description="BSEC fuse word 364 value register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR365" description="BSEC fuse word 365 value register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR366" description="BSEC fuse word 366 value register" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR367" description="BSEC fuse word 367 value register" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR368" description="BSEC fuse word 368 value register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR369" description="BSEC fuse word 369 value register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR370" description="BSEC fuse word 370 value register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR371" description="BSEC fuse word 371 value register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR372" description="BSEC fuse word 372 value register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR373" description="BSEC fuse word 373 value register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR374" description="BSEC fuse word 374 value register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_FVR375" description="BSEC fuse word 375 value register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FV" description="fuse value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SPLOCK0" description="BSEC sticky programming lock register 0" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK0" description="Sticky programming lock for word 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 0 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 0 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK1" description="Sticky programming lock for word 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 1 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 1 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK2" description="Sticky programming lock for word 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 2 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 2 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK3" description="Sticky programming lock for word 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 3 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 3 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK4" description="Sticky programming lock for word 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 4 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 4 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK5" description="Sticky programming lock for word 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 5 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 5 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK6" description="Sticky programming lock for word 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 6 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 6 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK7" description="Sticky programming lock for word 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 7 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 7 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK8" description="Sticky programming lock for word 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 8 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 8 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK9" description="Sticky programming lock for word 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 9 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 9 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK10" description="Sticky programming lock for word 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 10 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 10 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK11" description="Sticky programming lock for word 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 11 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 11 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK12" description="Sticky programming lock for word 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 12 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 12 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK13" description="Sticky programming lock for word 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 13 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 13 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK14" description="Sticky programming lock for word 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 14 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 14 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK15" description="Sticky programming lock for word 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 15 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 15 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK16" description="Sticky programming lock for word 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 16 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 16 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK17" description="Sticky programming lock for word 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 17 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 17 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK18" description="Sticky programming lock for word 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 18 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 18 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK19" description="Sticky programming lock for word 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 19 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 19 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK20" description="Sticky programming lock for word 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 20 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 20 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK21" description="Sticky programming lock for word 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 21 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 21 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK22" description="Sticky programming lock for word 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 22 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 22 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK23" description="Sticky programming lock for word 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 23 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 23 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK24" description="Sticky programming lock for word 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 24 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 24 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK25" description="Sticky programming lock for word 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 25 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 25 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK26" description="Sticky programming lock for word 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 26 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 26 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK27" description="Sticky programming lock for word 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 27 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 27 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK28" description="Sticky programming lock for word 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 28 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 28 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK29" description="Sticky programming lock for word 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 29 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 29 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK30" description="Sticky programming lock for word 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 30 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 30 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK31" description="Sticky programming lock for word 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 31 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 31 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK1" description="BSEC sticky programming lock register 1" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK32" description="Sticky programming lock for word 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 32 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 32 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK33" description="Sticky programming lock for word 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 33 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 33 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK34" description="Sticky programming lock for word 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 34 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 34 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK35" description="Sticky programming lock for word 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 35 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 35 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK36" description="Sticky programming lock for word 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 36 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 36 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK37" description="Sticky programming lock for word 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 37 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 37 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK38" description="Sticky programming lock for word 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 38 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 38 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK39" description="Sticky programming lock for word 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 39 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 39 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK40" description="Sticky programming lock for word 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 40 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 40 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK41" description="Sticky programming lock for word 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 41 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 41 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK42" description="Sticky programming lock for word 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 42 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 42 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK43" description="Sticky programming lock for word 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 43 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 43 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK44" description="Sticky programming lock for word 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 44 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 44 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK45" description="Sticky programming lock for word 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 45 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 45 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK46" description="Sticky programming lock for word 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 46 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 46 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK47" description="Sticky programming lock for word 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 47 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 47 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK48" description="Sticky programming lock for word 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 48 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 48 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK49" description="Sticky programming lock for word 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 49 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 49 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK50" description="Sticky programming lock for word 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 50 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 50 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK51" description="Sticky programming lock for word 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 51 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 51 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK52" description="Sticky programming lock for word 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 52 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 52 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK53" description="Sticky programming lock for word 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 53 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 53 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK54" description="Sticky programming lock for word 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 54 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 54 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK55" description="Sticky programming lock for word 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 55 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 55 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK56" description="Sticky programming lock for word 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 56 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 56 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK57" description="Sticky programming lock for word 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 57 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 57 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK58" description="Sticky programming lock for word 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 58 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 58 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK59" description="Sticky programming lock for word 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 59 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 59 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK60" description="Sticky programming lock for word 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 60 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 60 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK61" description="Sticky programming lock for word 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 61 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 61 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK62" description="Sticky programming lock for word 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 62 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 62 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK63" description="Sticky programming lock for word 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 63 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 63 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK2" description="BSEC sticky programming lock register 2" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK64" description="Sticky programming lock for word 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 64 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 64 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK65" description="Sticky programming lock for word 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 65 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 65 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK66" description="Sticky programming lock for word 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 66 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 66 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK67" description="Sticky programming lock for word 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 67 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 67 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK68" description="Sticky programming lock for word 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 68 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 68 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK69" description="Sticky programming lock for word 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 69 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 69 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK70" description="Sticky programming lock for word 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 70 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 70 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK71" description="Sticky programming lock for word 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 71 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 71 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK72" description="Sticky programming lock for word 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 72 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 72 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK73" description="Sticky programming lock for word 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 73 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 73 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK74" description="Sticky programming lock for word 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 74 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 74 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK75" description="Sticky programming lock for word 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 75 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 75 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK76" description="Sticky programming lock for word 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 76 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 76 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK77" description="Sticky programming lock for word 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 77 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 77 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK78" description="Sticky programming lock for word 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 78 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 78 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK79" description="Sticky programming lock for word 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 79 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 79 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK80" description="Sticky programming lock for word 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 80 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 80 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK81" description="Sticky programming lock for word 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 81 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 81 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK82" description="Sticky programming lock for word 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 82 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 82 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK83" description="Sticky programming lock for word 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 83 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 83 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK84" description="Sticky programming lock for word 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 84 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 84 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK85" description="Sticky programming lock for word 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 85 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 85 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK86" description="Sticky programming lock for word 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 86 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 86 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK87" description="Sticky programming lock for word 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 87 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 87 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK88" description="Sticky programming lock for word 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 88 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 88 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK89" description="Sticky programming lock for word 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 89 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 89 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK90" description="Sticky programming lock for word 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 90 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 90 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK91" description="Sticky programming lock for word 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 91 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 91 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK92" description="Sticky programming lock for word 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 92 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 92 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK93" description="Sticky programming lock for word 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 93 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 93 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK94" description="Sticky programming lock for word 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 94 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 94 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK95" description="Sticky programming lock for word 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 95 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 95 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK3" description="BSEC sticky programming lock register 3" start="+0x80C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK96" description="Sticky programming lock for word 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 96 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 96 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK97" description="Sticky programming lock for word 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 97 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 97 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK98" description="Sticky programming lock for word 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 98 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 98 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK99" description="Sticky programming lock for word 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 99 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 99 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK100" description="Sticky programming lock for word 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 100 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 100 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK101" description="Sticky programming lock for word 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 101 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 101 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK102" description="Sticky programming lock for word 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 102 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 102 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK103" description="Sticky programming lock for word 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 103 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 103 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK104" description="Sticky programming lock for word 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 104 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 104 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK105" description="Sticky programming lock for word 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 105 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 105 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK106" description="Sticky programming lock for word 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 106 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 106 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK107" description="Sticky programming lock for word 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 107 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 107 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK108" description="Sticky programming lock for word 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 108 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 108 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK109" description="Sticky programming lock for word 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 109 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 109 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK110" description="Sticky programming lock for word 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 110 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 110 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK111" description="Sticky programming lock for word 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 111 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 111 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK112" description="Sticky programming lock for word 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 112 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 112 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK113" description="Sticky programming lock for word 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 113 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 113 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK114" description="Sticky programming lock for word 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 114 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 114 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK115" description="Sticky programming lock for word 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 115 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 115 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK116" description="Sticky programming lock for word 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 116 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 116 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK117" description="Sticky programming lock for word 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 117 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 117 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK118" description="Sticky programming lock for word 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 118 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 118 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK119" description="Sticky programming lock for word 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 119 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 119 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK120" description="Sticky programming lock for word 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 120 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 120 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK121" description="Sticky programming lock for word 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 121 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 121 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK122" description="Sticky programming lock for word 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 122 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 122 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK123" description="Sticky programming lock for word 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 123 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 123 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK124" description="Sticky programming lock for word 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 124 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 124 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK125" description="Sticky programming lock for word 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 125 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 125 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK126" description="Sticky programming lock for word 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 126 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 126 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK127" description="Sticky programming lock for word 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 127 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 127 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK4" description="BSEC sticky programming lock register 4" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK128" description="Sticky programming lock for word 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 128 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 128 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK129" description="Sticky programming lock for word 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 129 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 129 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK130" description="Sticky programming lock for word 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 130 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 130 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK131" description="Sticky programming lock for word 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 131 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 131 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK132" description="Sticky programming lock for word 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 132 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 132 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK133" description="Sticky programming lock for word 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 133 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 133 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK134" description="Sticky programming lock for word 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 134 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 134 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK135" description="Sticky programming lock for word 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 135 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 135 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK136" description="Sticky programming lock for word 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 136 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 136 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK137" description="Sticky programming lock for word 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 137 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 137 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK138" description="Sticky programming lock for word 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 138 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 138 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK139" description="Sticky programming lock for word 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 139 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 139 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK140" description="Sticky programming lock for word 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 140 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 140 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK141" description="Sticky programming lock for word 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 141 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 141 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK142" description="Sticky programming lock for word 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 142 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 142 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK143" description="Sticky programming lock for word 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 143 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 143 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK144" description="Sticky programming lock for word 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 144 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 144 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK145" description="Sticky programming lock for word 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 145 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 145 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK146" description="Sticky programming lock for word 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 146 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 146 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK147" description="Sticky programming lock for word 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 147 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 147 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK148" description="Sticky programming lock for word 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 148 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 148 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK149" description="Sticky programming lock for word 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 149 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 149 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK150" description="Sticky programming lock for word 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 150 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 150 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK151" description="Sticky programming lock for word 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 151 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 151 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK152" description="Sticky programming lock for word 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 152 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 152 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK153" description="Sticky programming lock for word 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 153 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 153 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK154" description="Sticky programming lock for word 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 154 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 154 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK155" description="Sticky programming lock for word 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 155 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 155 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK156" description="Sticky programming lock for word 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 156 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 156 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK157" description="Sticky programming lock for word 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 157 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 157 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK158" description="Sticky programming lock for word 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 158 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 158 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK159" description="Sticky programming lock for word 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 159 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 159 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK5" description="BSEC sticky programming lock register 5" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK160" description="Sticky programming lock for word 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 160 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 160 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK161" description="Sticky programming lock for word 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 161 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 161 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK162" description="Sticky programming lock for word 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 162 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 162 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK163" description="Sticky programming lock for word 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 163 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 163 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK164" description="Sticky programming lock for word 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 164 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 164 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK165" description="Sticky programming lock for word 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 165 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 165 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK166" description="Sticky programming lock for word 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 166 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 166 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK167" description="Sticky programming lock for word 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 167 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 167 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK168" description="Sticky programming lock for word 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 168 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 168 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK169" description="Sticky programming lock for word 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 169 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 169 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK170" description="Sticky programming lock for word 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 170 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 170 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK171" description="Sticky programming lock for word 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 171 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 171 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK172" description="Sticky programming lock for word 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 172 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 172 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK173" description="Sticky programming lock for word 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 173 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 173 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK174" description="Sticky programming lock for word 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 174 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 174 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK175" description="Sticky programming lock for word 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 175 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 175 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK176" description="Sticky programming lock for word 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 176 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 176 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK177" description="Sticky programming lock for word 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 177 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 177 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK178" description="Sticky programming lock for word 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 178 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 178 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK179" description="Sticky programming lock for word 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 179 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 179 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK180" description="Sticky programming lock for word 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 180 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 180 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK181" description="Sticky programming lock for word 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 181 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 181 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK182" description="Sticky programming lock for word 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 182 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 182 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK183" description="Sticky programming lock for word 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 183 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 183 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK184" description="Sticky programming lock for word 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 184 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 184 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK185" description="Sticky programming lock for word 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 185 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 185 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK186" description="Sticky programming lock for word 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 186 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 186 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK187" description="Sticky programming lock for word 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 187 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 187 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK188" description="Sticky programming lock for word 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 188 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 188 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK189" description="Sticky programming lock for word 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 189 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 189 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK190" description="Sticky programming lock for word 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 190 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 190 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK191" description="Sticky programming lock for word 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 191 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 191 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK6" description="BSEC sticky programming lock register 6" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK192" description="Sticky programming lock for word 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 192 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 192 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK193" description="Sticky programming lock for word 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 193 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 193 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK194" description="Sticky programming lock for word 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 194 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 194 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK195" description="Sticky programming lock for word 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 195 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 195 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK196" description="Sticky programming lock for word 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 196 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 196 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK197" description="Sticky programming lock for word 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 197 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 197 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK198" description="Sticky programming lock for word 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 198 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 198 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK199" description="Sticky programming lock for word 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 199 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 199 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK200" description="Sticky programming lock for word 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 200 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 200 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK201" description="Sticky programming lock for word 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 201 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 201 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK202" description="Sticky programming lock for word 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 202 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 202 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK203" description="Sticky programming lock for word 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 203 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 203 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK204" description="Sticky programming lock for word 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 204 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 204 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK205" description="Sticky programming lock for word 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 205 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 205 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK206" description="Sticky programming lock for word 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 206 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 206 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK207" description="Sticky programming lock for word 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 207 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 207 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK208" description="Sticky programming lock for word 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 208 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 208 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK209" description="Sticky programming lock for word 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 209 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 209 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK210" description="Sticky programming lock for word 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 210 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 210 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK211" description="Sticky programming lock for word 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 211 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 211 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK212" description="Sticky programming lock for word 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 212 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 212 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK213" description="Sticky programming lock for word 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 213 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 213 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK214" description="Sticky programming lock for word 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 214 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 214 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK215" description="Sticky programming lock for word 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 215 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 215 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK216" description="Sticky programming lock for word 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 216 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 216 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK217" description="Sticky programming lock for word 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 217 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 217 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK218" description="Sticky programming lock for word 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 218 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 218 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK219" description="Sticky programming lock for word 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 219 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 219 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK220" description="Sticky programming lock for word 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 220 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 220 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK221" description="Sticky programming lock for word 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 221 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 221 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK222" description="Sticky programming lock for word 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 222 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 222 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK223" description="Sticky programming lock for word 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 223 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 223 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK7" description="BSEC sticky programming lock register 7" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK224" description="Sticky programming lock for word 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 224 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 224 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK225" description="Sticky programming lock for word 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 225 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 225 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK226" description="Sticky programming lock for word 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 226 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 226 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK227" description="Sticky programming lock for word 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 227 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 227 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK228" description="Sticky programming lock for word 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 228 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 228 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK229" description="Sticky programming lock for word 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 229 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 229 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK230" description="Sticky programming lock for word 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 230 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 230 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK231" description="Sticky programming lock for word 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 231 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 231 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK232" description="Sticky programming lock for word 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 232 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 232 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK233" description="Sticky programming lock for word 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 233 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 233 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK234" description="Sticky programming lock for word 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 234 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 234 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK235" description="Sticky programming lock for word 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 235 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 235 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK236" description="Sticky programming lock for word 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 236 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 236 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK237" description="Sticky programming lock for word 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 237 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 237 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK238" description="Sticky programming lock for word 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 238 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 238 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK239" description="Sticky programming lock for word 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 239 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 239 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK240" description="Sticky programming lock for word 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 240 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 240 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK241" description="Sticky programming lock for word 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 241 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 241 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK242" description="Sticky programming lock for word 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 242 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 242 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK243" description="Sticky programming lock for word 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 243 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 243 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK244" description="Sticky programming lock for word 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 244 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 244 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK245" description="Sticky programming lock for word 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 245 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 245 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK246" description="Sticky programming lock for word 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 246 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 246 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK247" description="Sticky programming lock for word 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 247 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 247 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK248" description="Sticky programming lock for word 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 248 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 248 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK249" description="Sticky programming lock for word 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 249 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 249 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK250" description="Sticky programming lock for word 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 250 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 250 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK251" description="Sticky programming lock for word 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 251 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 251 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK252" description="Sticky programming lock for word 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 252 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 252 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK253" description="Sticky programming lock for word 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 253 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 253 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK254" description="Sticky programming lock for word 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 254 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 254 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK255" description="Sticky programming lock for word 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 255 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 255 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK8" description="BSEC sticky programming lock register 8" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK256" description="Sticky programming lock for word 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 256 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 256 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK257" description="Sticky programming lock for word 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 257 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 257 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK258" description="Sticky programming lock for word 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 258 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 258 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK259" description="Sticky programming lock for word 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 259 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 259 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK260" description="Sticky programming lock for word 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 260 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 260 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK261" description="Sticky programming lock for word 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 261 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 261 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK262" description="Sticky programming lock for word 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 262 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 262 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK263" description="Sticky programming lock for word 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 263 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 263 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK264" description="Sticky programming lock for word 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 264 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 264 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK265" description="Sticky programming lock for word 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 265 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 265 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK266" description="Sticky programming lock for word 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 266 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 266 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK267" description="Sticky programming lock for word 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 267 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 267 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK268" description="Sticky programming lock for word 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 268 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 268 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK269" description="Sticky programming lock for word 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 269 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 269 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK270" description="Sticky programming lock for word 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 270 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 270 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK271" description="Sticky programming lock for word 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 271 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 271 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK272" description="Sticky programming lock for word 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 272 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 272 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK273" description="Sticky programming lock for word 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 273 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 273 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK274" description="Sticky programming lock for word 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 274 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 274 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK275" description="Sticky programming lock for word 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 275 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 275 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK276" description="Sticky programming lock for word 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 276 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 276 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK277" description="Sticky programming lock for word 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 277 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 277 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK278" description="Sticky programming lock for word 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 278 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 278 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK279" description="Sticky programming lock for word 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 279 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 279 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK280" description="Sticky programming lock for word 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 280 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 280 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK281" description="Sticky programming lock for word 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 281 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 281 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK282" description="Sticky programming lock for word 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 282 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 282 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK283" description="Sticky programming lock for word 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 283 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 283 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK284" description="Sticky programming lock for word 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 284 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 284 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK285" description="Sticky programming lock for word 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 285 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 285 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK286" description="Sticky programming lock for word 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 286 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 286 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK287" description="Sticky programming lock for word 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 287 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 287 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK9" description="BSEC sticky programming lock register 9" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK288" description="Sticky programming lock for word 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 288 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 288 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK289" description="Sticky programming lock for word 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 289 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 289 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK290" description="Sticky programming lock for word 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 290 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 290 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK291" description="Sticky programming lock for word 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 291 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 291 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK292" description="Sticky programming lock for word 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 292 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 292 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK293" description="Sticky programming lock for word 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 293 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 293 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK294" description="Sticky programming lock for word 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 294 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 294 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK295" description="Sticky programming lock for word 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 295 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 295 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK296" description="Sticky programming lock for word 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 296 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 296 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK297" description="Sticky programming lock for word 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 297 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 297 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK298" description="Sticky programming lock for word 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 298 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 298 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK299" description="Sticky programming lock for word 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 299 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 299 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK300" description="Sticky programming lock for word 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 300 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 300 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK301" description="Sticky programming lock for word 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 301 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 301 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK302" description="Sticky programming lock for word 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 302 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 302 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK303" description="Sticky programming lock for word 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 303 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 303 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK304" description="Sticky programming lock for word 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 304 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 304 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK305" description="Sticky programming lock for word 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 305 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 305 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK306" description="Sticky programming lock for word 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 306 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 306 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK307" description="Sticky programming lock for word 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 307 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 307 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK308" description="Sticky programming lock for word 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 308 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 308 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK309" description="Sticky programming lock for word 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 309 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 309 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK310" description="Sticky programming lock for word 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 310 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 310 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK311" description="Sticky programming lock for word 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 311 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 311 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK312" description="Sticky programming lock for word 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 312 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 312 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK313" description="Sticky programming lock for word 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 313 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 313 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK314" description="Sticky programming lock for word 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 314 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 314 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK315" description="Sticky programming lock for word 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 315 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 315 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK316" description="Sticky programming lock for word 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 316 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 316 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK317" description="Sticky programming lock for word 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 317 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 317 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK318" description="Sticky programming lock for word 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 318 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 318 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK319" description="Sticky programming lock for word 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 319 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 319 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK10" description="BSEC sticky programming lock register 10" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK320" description="Sticky programming lock for word 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 320 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 320 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK321" description="Sticky programming lock for word 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 321 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 321 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK322" description="Sticky programming lock for word 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 322 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 322 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK323" description="Sticky programming lock for word 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 323 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 323 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK324" description="Sticky programming lock for word 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 324 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 324 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK325" description="Sticky programming lock for word 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 325 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 325 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK326" description="Sticky programming lock for word 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 326 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 326 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK327" description="Sticky programming lock for word 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 327 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 327 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK328" description="Sticky programming lock for word 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 328 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 328 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK329" description="Sticky programming lock for word 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 329 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 329 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK330" description="Sticky programming lock for word 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 330 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 330 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK331" description="Sticky programming lock for word 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 331 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 331 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK332" description="Sticky programming lock for word 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 332 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 332 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK333" description="Sticky programming lock for word 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 333 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 333 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK334" description="Sticky programming lock for word 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 334 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 334 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK335" description="Sticky programming lock for word 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 335 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 335 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK336" description="Sticky programming lock for word 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 336 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 336 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK337" description="Sticky programming lock for word 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 337 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 337 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK338" description="Sticky programming lock for word 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 338 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 338 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK339" description="Sticky programming lock for word 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 339 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 339 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK340" description="Sticky programming lock for word 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 340 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 340 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK341" description="Sticky programming lock for word 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 341 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 341 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK342" description="Sticky programming lock for word 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 342 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 342 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK343" description="Sticky programming lock for word 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 343 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 343 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK344" description="Sticky programming lock for word 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 344 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 344 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK345" description="Sticky programming lock for word 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 345 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 345 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK346" description="Sticky programming lock for word 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 346 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 346 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK347" description="Sticky programming lock for word 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 347 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 347 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK348" description="Sticky programming lock for word 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 348 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 348 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK349" description="Sticky programming lock for word 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 349 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 349 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK350" description="Sticky programming lock for word 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 350 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 350 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK351" description="Sticky programming lock for word 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 351 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 351 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SPLOCK11" description="BSEC sticky programming lock register 11" start="+0x82C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPLOCK352" description="Sticky programming lock for word 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 352 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 352 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK353" description="Sticky programming lock for word 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 353 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 353 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK354" description="Sticky programming lock for word 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 354 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 354 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK355" description="Sticky programming lock for word 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 355 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 355 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK356" description="Sticky programming lock for word 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 356 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 356 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK357" description="Sticky programming lock for word 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 357 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 357 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK358" description="Sticky programming lock for word 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 358 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 358 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK359" description="Sticky programming lock for word 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 359 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 359 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK360" description="Sticky programming lock for word 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 360 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 360 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK361" description="Sticky programming lock for word 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 361 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 361 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK362" description="Sticky programming lock for word 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 362 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 362 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK363" description="Sticky programming lock for word 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 363 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 363 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK364" description="Sticky programming lock for word 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 364 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 364 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK365" description="Sticky programming lock for word 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 365 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 365 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK366" description="Sticky programming lock for word 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 366 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 366 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK367" description="Sticky programming lock for word 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 367 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 367 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK368" description="Sticky programming lock for word 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 368 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 368 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK369" description="Sticky programming lock for word 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 369 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 369 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK370" description="Sticky programming lock for word 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 370 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 370 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK371" description="Sticky programming lock for word 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 371 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 371 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK372" description="Sticky programming lock for word 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 372 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 372 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK373" description="Sticky programming lock for word 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 373 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 373 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK374" description="Sticky programming lock for word 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 374 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 374 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK375" description="Sticky programming lock for word 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 375 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 375 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK376" description="Sticky programming lock for word 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 376 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 376 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK377" description="Sticky programming lock for word 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 377 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 377 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK378" description="Sticky programming lock for word 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 378 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 378 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK379" description="Sticky programming lock for word 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 379 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 379 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK380" description="Sticky programming lock for word 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 380 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 380 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK381" description="Sticky programming lock for word 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 381 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 381 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK382" description="Sticky programming lock for word 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 382 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 382 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SPLOCK383" description="Sticky programming lock for word 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 383 can be burnt in fuse memory array" start="0x0" />
+        <Enum name="B_0x1" description="Attempt to program fuse word 383 in OTP memory array is silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK0" description="BSEC sticky write lock register 0" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK0" description="sticky write lock for shadow register 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR0 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR0 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK1" description="sticky write lock for shadow register 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR1 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR1 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK2" description="sticky write lock for shadow register 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR2 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR2 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK3" description="sticky write lock for shadow register 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR3 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR3 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK4" description="sticky write lock for shadow register 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR4 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR4 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK5" description="sticky write lock for shadow register 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR5 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR5 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK6" description="sticky write lock for shadow register 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR6 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR6 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK7" description="sticky write lock for shadow register 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR7 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR7 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK8" description="sticky write lock for shadow register 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR8 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR8 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK9" description="sticky write lock for shadow register 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR9 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR9 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK10" description="sticky write lock for shadow register 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR10 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR10 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK11" description="sticky write lock for shadow register 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR11 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR11 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK12" description="sticky write lock for shadow register 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR12 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR12 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK13" description="sticky write lock for shadow register 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR13 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR13 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK14" description="sticky write lock for shadow register 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR14 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR14 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK15" description="sticky write lock for shadow register 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR15 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR15 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK16" description="sticky write lock for shadow register 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR16 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR16 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK17" description="sticky write lock for shadow register 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR17 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR17 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK18" description="sticky write lock for shadow register 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR18 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR18 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK19" description="sticky write lock for shadow register 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR19 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR19 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK20" description="sticky write lock for shadow register 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR20 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR20 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK21" description="sticky write lock for shadow register 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR21 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR21 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK22" description="sticky write lock for shadow register 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR22 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR22 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK23" description="sticky write lock for shadow register 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR23 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR23 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK24" description="sticky write lock for shadow register 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR24 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR24 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK25" description="sticky write lock for shadow register 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR25 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR25 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK26" description="sticky write lock for shadow register 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR26 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR26 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK27" description="sticky write lock for shadow register 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR27 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR27 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK28" description="sticky write lock for shadow register 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR28 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR28 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK29" description="sticky write lock for shadow register 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR29 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR29 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK30" description="sticky write lock for shadow register 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR30 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR30 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK31" description="sticky write lock for shadow register 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR31 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR31 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK1" description="BSEC sticky write lock register 1" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK32" description="sticky write lock for shadow register 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR32 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR32 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK33" description="sticky write lock for shadow register 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR33 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR33 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK34" description="sticky write lock for shadow register 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR34 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR34 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK35" description="sticky write lock for shadow register 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR35 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR35 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK36" description="sticky write lock for shadow register 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR36 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR36 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK37" description="sticky write lock for shadow register 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR37 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR37 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK38" description="sticky write lock for shadow register 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR38 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR38 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK39" description="sticky write lock for shadow register 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR39 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR39 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK40" description="sticky write lock for shadow register 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR40 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR40 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK41" description="sticky write lock for shadow register 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR41 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR41 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK42" description="sticky write lock for shadow register 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR42 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR42 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK43" description="sticky write lock for shadow register 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR43 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR43 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK44" description="sticky write lock for shadow register 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR44 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR44 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK45" description="sticky write lock for shadow register 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR45 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR45 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK46" description="sticky write lock for shadow register 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR46 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR46 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK47" description="sticky write lock for shadow register 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR47 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR47 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK48" description="sticky write lock for shadow register 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR48 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR48 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK49" description="sticky write lock for shadow register 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR49 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR49 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK50" description="sticky write lock for shadow register 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR50 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR50 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK51" description="sticky write lock for shadow register 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR51 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR51 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK52" description="sticky write lock for shadow register 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR52 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR52 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK53" description="sticky write lock for shadow register 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR53 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR53 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK54" description="sticky write lock for shadow register 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR54 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR54 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK55" description="sticky write lock for shadow register 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR55 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR55 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK56" description="sticky write lock for shadow register 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR56 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR56 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK57" description="sticky write lock for shadow register 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR57 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR57 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK58" description="sticky write lock for shadow register 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR58 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR58 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK59" description="sticky write lock for shadow register 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR59 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR59 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK60" description="sticky write lock for shadow register 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR60 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR60 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK61" description="sticky write lock for shadow register 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR61 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR61 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK62" description="sticky write lock for shadow register 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR62 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR62 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK63" description="sticky write lock for shadow register 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR63 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR63 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK2" description="BSEC sticky write lock register 2" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK64" description="sticky write lock for shadow register 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR64 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR64 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK65" description="sticky write lock for shadow register 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR65 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR65 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK66" description="sticky write lock for shadow register 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR66 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR66 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK67" description="sticky write lock for shadow register 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR67 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR67 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK68" description="sticky write lock for shadow register 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR68 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR68 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK69" description="sticky write lock for shadow register 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR69 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR69 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK70" description="sticky write lock for shadow register 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR70 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR70 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK71" description="sticky write lock for shadow register 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR71 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR71 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK72" description="sticky write lock for shadow register 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR72 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR72 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK73" description="sticky write lock for shadow register 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR73 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR73 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK74" description="sticky write lock for shadow register 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR74 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR74 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK75" description="sticky write lock for shadow register 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR75 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR75 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK76" description="sticky write lock for shadow register 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR76 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR76 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK77" description="sticky write lock for shadow register 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR77 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR77 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK78" description="sticky write lock for shadow register 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR78 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR78 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK79" description="sticky write lock for shadow register 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR79 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR79 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK80" description="sticky write lock for shadow register 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR80 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR80 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK81" description="sticky write lock for shadow register 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR81 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR81 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK82" description="sticky write lock for shadow register 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR82 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR82 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK83" description="sticky write lock for shadow register 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR83 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR83 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK84" description="sticky write lock for shadow register 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR84 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR84 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK85" description="sticky write lock for shadow register 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR85 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR85 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK86" description="sticky write lock for shadow register 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR86 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR86 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK87" description="sticky write lock for shadow register 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR87 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR87 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK88" description="sticky write lock for shadow register 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR88 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR88 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK89" description="sticky write lock for shadow register 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR89 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR89 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK90" description="sticky write lock for shadow register 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR90 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR90 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK91" description="sticky write lock for shadow register 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR91 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR91 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK92" description="sticky write lock for shadow register 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR92 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR92 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK93" description="sticky write lock for shadow register 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR93 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR93 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK94" description="sticky write lock for shadow register 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR94 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR94 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK95" description="sticky write lock for shadow register 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR95 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR95 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK3" description="BSEC sticky write lock register 3" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK96" description="sticky write lock for shadow register 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR96 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR96 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK97" description="sticky write lock for shadow register 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR97 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR97 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK98" description="sticky write lock for shadow register 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR98 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR98 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK99" description="sticky write lock for shadow register 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR99 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR99 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK100" description="sticky write lock for shadow register 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR100 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR100 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK101" description="sticky write lock for shadow register 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR101 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR101 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK102" description="sticky write lock for shadow register 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR102 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR102 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK103" description="sticky write lock for shadow register 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR103 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR103 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK104" description="sticky write lock for shadow register 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR104 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR104 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK105" description="sticky write lock for shadow register 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR105 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR105 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK106" description="sticky write lock for shadow register 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR106 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR106 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK107" description="sticky write lock for shadow register 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR107 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR107 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK108" description="sticky write lock for shadow register 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR108 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR108 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK109" description="sticky write lock for shadow register 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR109 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR109 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK110" description="sticky write lock for shadow register 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR110 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR110 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK111" description="sticky write lock for shadow register 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR111 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR111 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK112" description="sticky write lock for shadow register 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR112 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR112 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK113" description="sticky write lock for shadow register 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR113 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR113 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK114" description="sticky write lock for shadow register 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR114 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR114 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK115" description="sticky write lock for shadow register 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR115 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR115 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK116" description="sticky write lock for shadow register 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR116 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR116 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK117" description="sticky write lock for shadow register 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR117 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR117 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK118" description="sticky write lock for shadow register 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR118 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR118 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK119" description="sticky write lock for shadow register 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR119 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR119 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK120" description="sticky write lock for shadow register 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR120 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR120 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK121" description="sticky write lock for shadow register 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR121 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR121 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK122" description="sticky write lock for shadow register 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR122 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR122 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK123" description="sticky write lock for shadow register 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR123 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR123 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK124" description="sticky write lock for shadow register 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR124 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR124 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK125" description="sticky write lock for shadow register 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR125 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR125 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK126" description="sticky write lock for shadow register 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR126 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR126 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK127" description="sticky write lock for shadow register 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR127 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR127 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK4" description="BSEC sticky write lock register 4" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK128" description="sticky write lock for shadow register 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR128 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR128 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK129" description="sticky write lock for shadow register 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR129 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR129 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK130" description="sticky write lock for shadow register 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR130 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR130 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK131" description="sticky write lock for shadow register 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR131 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR131 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK132" description="sticky write lock for shadow register 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR132 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR132 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK133" description="sticky write lock for shadow register 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR133 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR133 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK134" description="sticky write lock for shadow register 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR134 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR134 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK135" description="sticky write lock for shadow register 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR135 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR135 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK136" description="sticky write lock for shadow register 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR136 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR136 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK137" description="sticky write lock for shadow register 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR137 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR137 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK138" description="sticky write lock for shadow register 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR138 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR138 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK139" description="sticky write lock for shadow register 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR139 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR139 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK140" description="sticky write lock for shadow register 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR140 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR140 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK141" description="sticky write lock for shadow register 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR141 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR141 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK142" description="sticky write lock for shadow register 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR142 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR142 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK143" description="sticky write lock for shadow register 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR143 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR143 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK144" description="sticky write lock for shadow register 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR144 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR144 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK145" description="sticky write lock for shadow register 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR145 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR145 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK146" description="sticky write lock for shadow register 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR146 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR146 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK147" description="sticky write lock for shadow register 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR147 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR147 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK148" description="sticky write lock for shadow register 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR148 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR148 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK149" description="sticky write lock for shadow register 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR149 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR149 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK150" description="sticky write lock for shadow register 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR150 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR150 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK151" description="sticky write lock for shadow register 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR151 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR151 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK152" description="sticky write lock for shadow register 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR152 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR152 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK153" description="sticky write lock for shadow register 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR153 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR153 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK154" description="sticky write lock for shadow register 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR154 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR154 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK155" description="sticky write lock for shadow register 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR155 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR155 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK156" description="sticky write lock for shadow register 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR156 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR156 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK157" description="sticky write lock for shadow register 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR157 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR157 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK158" description="sticky write lock for shadow register 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR158 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR158 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK159" description="sticky write lock for shadow register 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR159 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR159 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK5" description="BSEC sticky write lock register 5" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK160" description="sticky write lock for shadow register 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR160 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR160 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK161" description="sticky write lock for shadow register 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR161 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR161 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK162" description="sticky write lock for shadow register 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR162 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR162 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK163" description="sticky write lock for shadow register 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR163 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR163 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK164" description="sticky write lock for shadow register 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR164 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR164 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK165" description="sticky write lock for shadow register 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR165 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR165 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK166" description="sticky write lock for shadow register 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR166 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR166 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK167" description="sticky write lock for shadow register 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR167 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR167 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK168" description="sticky write lock for shadow register 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR168 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR168 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK169" description="sticky write lock for shadow register 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR169 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR169 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK170" description="sticky write lock for shadow register 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR170 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR170 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK171" description="sticky write lock for shadow register 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR171 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR171 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK172" description="sticky write lock for shadow register 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR172 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR172 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK173" description="sticky write lock for shadow register 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR173 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR173 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK174" description="sticky write lock for shadow register 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR174 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR174 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK175" description="sticky write lock for shadow register 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR175 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR175 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK176" description="sticky write lock for shadow register 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR176 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR176 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK177" description="sticky write lock for shadow register 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR177 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR177 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK178" description="sticky write lock for shadow register 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR178 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR178 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK179" description="sticky write lock for shadow register 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR179 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR179 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK180" description="sticky write lock for shadow register 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR180 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR180 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK181" description="sticky write lock for shadow register 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR181 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR181 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK182" description="sticky write lock for shadow register 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR182 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR182 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK183" description="sticky write lock for shadow register 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR183 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR183 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK184" description="sticky write lock for shadow register 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR184 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR184 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK185" description="sticky write lock for shadow register 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR185 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR185 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK186" description="sticky write lock for shadow register 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR186 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR186 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK187" description="sticky write lock for shadow register 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR187 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR187 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK188" description="sticky write lock for shadow register 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR188 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR188 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK189" description="sticky write lock for shadow register 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR189 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR189 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK190" description="sticky write lock for shadow register 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR190 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR190 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK191" description="sticky write lock for shadow register 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR191 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR191 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK6" description="BSEC sticky write lock register 6" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK192" description="sticky write lock for shadow register 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR192 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR192 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK193" description="sticky write lock for shadow register 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR193 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR193 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK194" description="sticky write lock for shadow register 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR194 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR194 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK195" description="sticky write lock for shadow register 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR195 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR195 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK196" description="sticky write lock for shadow register 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR196 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR196 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK197" description="sticky write lock for shadow register 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR197 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR197 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK198" description="sticky write lock for shadow register 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR198 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR198 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK199" description="sticky write lock for shadow register 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR199 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR199 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK200" description="sticky write lock for shadow register 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR200 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR200 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK201" description="sticky write lock for shadow register 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR201 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR201 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK202" description="sticky write lock for shadow register 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR202 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR202 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK203" description="sticky write lock for shadow register 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR203 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR203 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK204" description="sticky write lock for shadow register 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR204 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR204 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK205" description="sticky write lock for shadow register 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR205 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR205 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK206" description="sticky write lock for shadow register 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR206 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR206 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK207" description="sticky write lock for shadow register 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR207 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR207 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK208" description="sticky write lock for shadow register 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR208 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR208 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK209" description="sticky write lock for shadow register 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR209 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR209 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK210" description="sticky write lock for shadow register 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR210 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR210 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK211" description="sticky write lock for shadow register 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR211 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR211 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK212" description="sticky write lock for shadow register 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR212 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR212 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK213" description="sticky write lock for shadow register 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR213 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR213 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK214" description="sticky write lock for shadow register 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR214 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR214 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK215" description="sticky write lock for shadow register 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR215 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR215 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK216" description="sticky write lock for shadow register 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR216 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR216 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK217" description="sticky write lock for shadow register 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR217 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR217 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK218" description="sticky write lock for shadow register 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR218 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR218 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK219" description="sticky write lock for shadow register 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR219 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR219 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK220" description="sticky write lock for shadow register 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR220 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR220 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK221" description="sticky write lock for shadow register 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR221 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR221 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK222" description="sticky write lock for shadow register 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR222 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR222 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK223" description="sticky write lock for shadow register 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR223 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR223 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK7" description="BSEC sticky write lock register 7" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK224" description="sticky write lock for shadow register 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR224 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR224 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK225" description="sticky write lock for shadow register 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR225 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR225 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK226" description="sticky write lock for shadow register 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR226 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR226 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK227" description="sticky write lock for shadow register 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR227 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR227 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK228" description="sticky write lock for shadow register 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR228 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR228 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK229" description="sticky write lock for shadow register 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR229 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR229 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK230" description="sticky write lock for shadow register 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR230 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR230 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK231" description="sticky write lock for shadow register 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR231 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR231 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK232" description="sticky write lock for shadow register 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR232 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR232 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK233" description="sticky write lock for shadow register 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR233 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR233 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK234" description="sticky write lock for shadow register 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR234 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR234 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK235" description="sticky write lock for shadow register 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR235 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR235 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK236" description="sticky write lock for shadow register 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR236 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR236 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK237" description="sticky write lock for shadow register 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR237 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR237 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK238" description="sticky write lock for shadow register 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR238 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR238 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK239" description="sticky write lock for shadow register 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR239 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR239 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK240" description="sticky write lock for shadow register 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR240 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR240 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK241" description="sticky write lock for shadow register 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR241 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR241 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK242" description="sticky write lock for shadow register 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR242 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR242 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK243" description="sticky write lock for shadow register 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR243 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR243 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK244" description="sticky write lock for shadow register 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR244 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR244 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK245" description="sticky write lock for shadow register 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR245 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR245 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK246" description="sticky write lock for shadow register 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR246 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR246 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK247" description="sticky write lock for shadow register 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR247 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR247 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK248" description="sticky write lock for shadow register 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR248 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR248 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK249" description="sticky write lock for shadow register 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR249 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR249 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK250" description="sticky write lock for shadow register 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR250 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR250 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK251" description="sticky write lock for shadow register 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR251 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR251 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK252" description="sticky write lock for shadow register 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR252 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR252 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK253" description="sticky write lock for shadow register 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR253 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR253 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK254" description="sticky write lock for shadow register 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR254 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR254 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK255" description="sticky write lock for shadow register 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR255 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR255 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK8" description="BSEC sticky write lock register 8" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK256" description="sticky write lock for shadow register 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR256 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR256 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK257" description="sticky write lock for shadow register 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR257 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR257 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK258" description="sticky write lock for shadow register 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR258 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR258 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK259" description="sticky write lock for shadow register 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR259 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR259 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK260" description="sticky write lock for shadow register 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR260 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR260 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK261" description="sticky write lock for shadow register 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR261 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR261 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK262" description="sticky write lock for shadow register 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR262 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR262 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK263" description="sticky write lock for shadow register 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR263 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR263 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK264" description="sticky write lock for shadow register 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR264 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR264 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK265" description="sticky write lock for shadow register 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR265 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR265 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK266" description="sticky write lock for shadow register 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR266 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR266 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK267" description="sticky write lock for shadow register 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR267 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR267 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK268" description="sticky write lock for shadow register 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR268 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR268 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK269" description="sticky write lock for shadow register 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR269 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR269 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK270" description="sticky write lock for shadow register 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR270 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR270 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK271" description="sticky write lock for shadow register 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR271 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR271 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK272" description="sticky write lock for shadow register 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR272 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR272 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK273" description="sticky write lock for shadow register 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR273 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR273 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK274" description="sticky write lock for shadow register 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR274 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR274 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK275" description="sticky write lock for shadow register 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR275 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR275 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK276" description="sticky write lock for shadow register 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR276 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR276 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK277" description="sticky write lock for shadow register 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR277 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR277 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK278" description="sticky write lock for shadow register 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR278 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR278 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK279" description="sticky write lock for shadow register 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR279 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR279 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK280" description="sticky write lock for shadow register 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR280 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR280 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK281" description="sticky write lock for shadow register 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR281 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR281 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK282" description="sticky write lock for shadow register 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR282 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR282 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK283" description="sticky write lock for shadow register 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR283 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR283 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK284" description="sticky write lock for shadow register 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR284 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR284 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK285" description="sticky write lock for shadow register 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR285 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR285 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK286" description="sticky write lock for shadow register 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR286 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR286 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK287" description="sticky write lock for shadow register 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR287 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR287 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK9" description="BSEC sticky write lock register 9" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK288" description="sticky write lock for shadow register 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR288 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR288 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK289" description="sticky write lock for shadow register 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR289 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR289 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK290" description="sticky write lock for shadow register 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR290 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR290 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK291" description="sticky write lock for shadow register 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR291 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR291 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK292" description="sticky write lock for shadow register 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR292 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR292 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK293" description="sticky write lock for shadow register 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR293 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR293 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK294" description="sticky write lock for shadow register 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR294 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR294 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK295" description="sticky write lock for shadow register 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR295 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR295 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK296" description="sticky write lock for shadow register 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR296 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR296 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK297" description="sticky write lock for shadow register 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR297 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR297 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK298" description="sticky write lock for shadow register 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR298 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR298 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK299" description="sticky write lock for shadow register 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR299 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR299 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK300" description="sticky write lock for shadow register 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR300 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR300 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK301" description="sticky write lock for shadow register 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR301 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR301 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK302" description="sticky write lock for shadow register 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR302 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR302 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK303" description="sticky write lock for shadow register 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR303 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR303 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK304" description="sticky write lock for shadow register 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR304 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR304 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK305" description="sticky write lock for shadow register 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR305 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR305 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK306" description="sticky write lock for shadow register 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR306 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR306 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK307" description="sticky write lock for shadow register 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR307 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR307 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK308" description="sticky write lock for shadow register 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR308 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR308 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK309" description="sticky write lock for shadow register 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR309 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR309 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK310" description="sticky write lock for shadow register 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR310 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR310 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK311" description="sticky write lock for shadow register 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR311 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR311 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK312" description="sticky write lock for shadow register 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR312 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR312 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK313" description="sticky write lock for shadow register 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR313 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR313 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK314" description="sticky write lock for shadow register 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR314 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR314 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK315" description="sticky write lock for shadow register 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR315 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR315 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK316" description="sticky write lock for shadow register 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR316 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR316 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK317" description="sticky write lock for shadow register 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR317 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR317 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK318" description="sticky write lock for shadow register 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR318 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR318 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK319" description="sticky write lock for shadow register 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR319 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR319 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK10" description="BSEC sticky write lock register 10" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK320" description="sticky write lock for shadow register 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR320 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR320 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK321" description="sticky write lock for shadow register 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR321 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR321 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK322" description="sticky write lock for shadow register 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR322 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR322 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK323" description="sticky write lock for shadow register 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR323 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR323 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK324" description="sticky write lock for shadow register 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR324 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR324 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK325" description="sticky write lock for shadow register 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR325 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR325 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK326" description="sticky write lock for shadow register 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR326 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR326 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK327" description="sticky write lock for shadow register 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR327 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR327 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK328" description="sticky write lock for shadow register 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR328 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR328 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK329" description="sticky write lock for shadow register 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR329 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR329 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK330" description="sticky write lock for shadow register 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR330 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR330 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK331" description="sticky write lock for shadow register 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR331 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR331 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK332" description="sticky write lock for shadow register 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR332 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR332 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK333" description="sticky write lock for shadow register 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR333 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR333 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK334" description="sticky write lock for shadow register 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR334 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR334 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK335" description="sticky write lock for shadow register 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR335 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR335 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK336" description="sticky write lock for shadow register 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR336 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR336 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK337" description="sticky write lock for shadow register 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR337 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR337 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK338" description="sticky write lock for shadow register 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR338 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR338 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK339" description="sticky write lock for shadow register 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR339 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR339 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK340" description="sticky write lock for shadow register 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR340 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR340 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK341" description="sticky write lock for shadow register 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR341 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR341 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK342" description="sticky write lock for shadow register 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR342 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR342 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK343" description="sticky write lock for shadow register 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR343 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR343 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK344" description="sticky write lock for shadow register 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR344 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR344 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK345" description="sticky write lock for shadow register 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR345 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR345 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK346" description="sticky write lock for shadow register 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR346 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR346 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK347" description="sticky write lock for shadow register 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR347 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR347 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK348" description="sticky write lock for shadow register 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR348 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR348 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK349" description="sticky write lock for shadow register 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR349 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR349 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK350" description="sticky write lock for shadow register 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR350 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR350 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK351" description="sticky write lock for shadow register 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR351 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR351 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SWLOCK11" description="BSEC sticky write lock register 11" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLOCK352" description="sticky write lock for shadow register 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR352 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR352 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK353" description="sticky write lock for shadow register 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR353 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR353 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK354" description="sticky write lock for shadow register 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR354 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR354 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK355" description="sticky write lock for shadow register 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR355 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR355 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK356" description="sticky write lock for shadow register 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR356 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR356 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK357" description="sticky write lock for shadow register 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR357 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR357 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK358" description="sticky write lock for shadow register 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR358 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR358 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK359" description="sticky write lock for shadow register 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR359 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR359 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK360" description="sticky write lock for shadow register 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR360 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR360 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK361" description="sticky write lock for shadow register 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR361 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR361 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK362" description="sticky write lock for shadow register 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR362 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR362 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK363" description="sticky write lock for shadow register 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR363 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR363 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK364" description="sticky write lock for shadow register 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR364 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR364 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK365" description="sticky write lock for shadow register 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR365 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR365 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK366" description="sticky write lock for shadow register 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR366 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR366 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK367" description="sticky write lock for shadow register 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR367 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR367 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK368" description="sticky write lock for shadow register 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR368 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR368 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK369" description="sticky write lock for shadow register 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR369 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR369 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK370" description="sticky write lock for shadow register 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR370 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR370 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK371" description="sticky write lock for shadow register 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR371 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR371 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK372" description="sticky write lock for shadow register 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR372 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR372 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK373" description="sticky write lock for shadow register 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR373 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR373 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK374" description="sticky write lock for shadow register 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR374 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR374 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK375" description="sticky write lock for shadow register 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR375 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR375 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK376" description="sticky write lock for shadow register 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR376 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR376 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK377" description="sticky write lock for shadow register 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR377 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR377 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK378" description="sticky write lock for shadow register 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR378 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR378 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK379" description="sticky write lock for shadow register 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR379 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR379 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK380" description="sticky write lock for shadow register 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR380 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR380 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK381" description="sticky write lock for shadow register 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR381 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR381 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK382" description="sticky write lock for shadow register 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR382 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR382 are silently ignored" start="0x1" />
+      </BitField>
+      <BitField name="SWLOCK383" description="sticky write lock for shadow register 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write to shadow register BSEC_FVR383 is allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to shadow register BSEC_FVR383 are silently ignored" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK0" description="BSEC sticky reload lock register 0" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK0" description="sticky reload lock for fuse word 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 0 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 0 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK1" description="sticky reload lock for fuse word 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 1 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 1 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK2" description="sticky reload lock for fuse word 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 2 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 2 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK3" description="sticky reload lock for fuse word 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 3 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 3 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK4" description="sticky reload lock for fuse word 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 4 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 4 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK5" description="sticky reload lock for fuse word 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 5 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 5 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK6" description="sticky reload lock for fuse word 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 6 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 6 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK7" description="sticky reload lock for fuse word 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 7 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 7 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK8" description="sticky reload lock for fuse word 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 8 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 8 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK9" description="sticky reload lock for fuse word 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 9 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 9 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK10" description="sticky reload lock for fuse word 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 10 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 10 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK11" description="sticky reload lock for fuse word 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 11 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 11 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK12" description="sticky reload lock for fuse word 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 12 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 12 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK13" description="sticky reload lock for fuse word 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 13 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 13 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK14" description="sticky reload lock for fuse word 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 14 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 14 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK15" description="sticky reload lock for fuse word 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 15 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 15 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK16" description="sticky reload lock for fuse word 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 16 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 16 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK17" description="sticky reload lock for fuse word 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 17 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 17 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK18" description="sticky reload lock for fuse word 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 18 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 18 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK19" description="sticky reload lock for fuse word 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 19 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 19 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK20" description="sticky reload lock for fuse word 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 20 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 20 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK21" description="sticky reload lock for fuse word 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 21 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 21 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK22" description="sticky reload lock for fuse word 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 22 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 22 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK23" description="sticky reload lock for fuse word 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 23 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 23 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK24" description="sticky reload lock for fuse word 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 24 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 24 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK25" description="sticky reload lock for fuse word 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 25 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 25 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK26" description="sticky reload lock for fuse word 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 26 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 26 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK27" description="sticky reload lock for fuse word 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 27 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 27 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK28" description="sticky reload lock for fuse word 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 28 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 28 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK29" description="sticky reload lock for fuse word 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 29 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 29 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK30" description="sticky reload lock for fuse word 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 30 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 30 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK31" description="sticky reload lock for fuse word 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 31 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 31 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK1" description="BSEC sticky reload lock register 1" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK32" description="sticky reload lock for fuse word 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 32 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 32 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK33" description="sticky reload lock for fuse word 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 33 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 33 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK34" description="sticky reload lock for fuse word 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 34 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 34 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK35" description="sticky reload lock for fuse word 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 35 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 35 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK36" description="sticky reload lock for fuse word 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 36 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 36 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK37" description="sticky reload lock for fuse word 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 37 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 37 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK38" description="sticky reload lock for fuse word 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 38 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 38 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK39" description="sticky reload lock for fuse word 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 39 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 39 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK40" description="sticky reload lock for fuse word 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 40 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 40 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK41" description="sticky reload lock for fuse word 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 41 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 41 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK42" description="sticky reload lock for fuse word 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 42 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 42 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK43" description="sticky reload lock for fuse word 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 43 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 43 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK44" description="sticky reload lock for fuse word 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 44 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 44 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK45" description="sticky reload lock for fuse word 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 45 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 45 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK46" description="sticky reload lock for fuse word 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 46 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 46 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK47" description="sticky reload lock for fuse word 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 47 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 47 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK48" description="sticky reload lock for fuse word 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 48 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 48 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK49" description="sticky reload lock for fuse word 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 49 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 49 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK50" description="sticky reload lock for fuse word 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 50 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 50 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK51" description="sticky reload lock for fuse word 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 51 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 51 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK52" description="sticky reload lock for fuse word 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 52 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 52 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK53" description="sticky reload lock for fuse word 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 53 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 53 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK54" description="sticky reload lock for fuse word 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 54 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 54 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK55" description="sticky reload lock for fuse word 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 55 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 55 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK56" description="sticky reload lock for fuse word 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 56 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 56 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK57" description="sticky reload lock for fuse word 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 57 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 57 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK58" description="sticky reload lock for fuse word 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 58 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 58 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK59" description="sticky reload lock for fuse word 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 59 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 59 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK60" description="sticky reload lock for fuse word 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 60 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 60 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK61" description="sticky reload lock for fuse word 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 61 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 61 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK62" description="sticky reload lock for fuse word 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 62 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 62 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK63" description="sticky reload lock for fuse word 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 63 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 63 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK2" description="BSEC sticky reload lock register 2" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK64" description="sticky reload lock for fuse word 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 64 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 64 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK65" description="sticky reload lock for fuse word 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 65 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 65 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK66" description="sticky reload lock for fuse word 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 66 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 66 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK67" description="sticky reload lock for fuse word 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 67 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 67 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK68" description="sticky reload lock for fuse word 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 68 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 68 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK69" description="sticky reload lock for fuse word 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 69 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 69 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK70" description="sticky reload lock for fuse word 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 70 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 70 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK71" description="sticky reload lock for fuse word 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 71 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 71 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK72" description="sticky reload lock for fuse word 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 72 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 72 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK73" description="sticky reload lock for fuse word 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 73 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 73 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK74" description="sticky reload lock for fuse word 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 74 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 74 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK75" description="sticky reload lock for fuse word 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 75 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 75 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK76" description="sticky reload lock for fuse word 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 76 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 76 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK77" description="sticky reload lock for fuse word 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 77 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 77 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK78" description="sticky reload lock for fuse word 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 78 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 78 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK79" description="sticky reload lock for fuse word 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 79 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 79 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK80" description="sticky reload lock for fuse word 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 80 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 80 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK81" description="sticky reload lock for fuse word 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 81 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 81 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK82" description="sticky reload lock for fuse word 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 82 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 82 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK83" description="sticky reload lock for fuse word 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 83 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 83 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK84" description="sticky reload lock for fuse word 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 84 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 84 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK85" description="sticky reload lock for fuse word 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 85 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 85 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK86" description="sticky reload lock for fuse word 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 86 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 86 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK87" description="sticky reload lock for fuse word 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 87 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 87 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK88" description="sticky reload lock for fuse word 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 88 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 88 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK89" description="sticky reload lock for fuse word 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 89 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 89 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK90" description="sticky reload lock for fuse word 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 90 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 90 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK91" description="sticky reload lock for fuse word 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 91 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 91 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK92" description="sticky reload lock for fuse word 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 92 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 92 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK93" description="sticky reload lock for fuse word 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 93 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 93 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK94" description="sticky reload lock for fuse word 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 94 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 94 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK95" description="sticky reload lock for fuse word 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 95 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 95 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK3" description="BSEC sticky reload lock register 3" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK96" description="sticky reload lock for fuse word 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 96 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 96 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK97" description="sticky reload lock for fuse word 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 97 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 97 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK98" description="sticky reload lock for fuse word 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 98 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 98 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK99" description="sticky reload lock for fuse word 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 99 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 99 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK100" description="sticky reload lock for fuse word 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 100 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 100 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK101" description="sticky reload lock for fuse word 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 101 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 101 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK102" description="sticky reload lock for fuse word 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 102 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 102 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK103" description="sticky reload lock for fuse word 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 103 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 103 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK104" description="sticky reload lock for fuse word 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 104 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 104 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK105" description="sticky reload lock for fuse word 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 105 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 105 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK106" description="sticky reload lock for fuse word 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 106 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 106 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK107" description="sticky reload lock for fuse word 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 107 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 107 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK108" description="sticky reload lock for fuse word 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 108 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 108 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK109" description="sticky reload lock for fuse word 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 109 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 109 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK110" description="sticky reload lock for fuse word 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 110 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 110 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK111" description="sticky reload lock for fuse word 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 111 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 111 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK112" description="sticky reload lock for fuse word 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 112 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 112 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK113" description="sticky reload lock for fuse word 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 113 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 113 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK114" description="sticky reload lock for fuse word 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 114 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 114 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK115" description="sticky reload lock for fuse word 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 115 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 115 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK116" description="sticky reload lock for fuse word 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 116 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 116 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK117" description="sticky reload lock for fuse word 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 117 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 117 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK118" description="sticky reload lock for fuse word 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 118 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 118 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK119" description="sticky reload lock for fuse word 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 119 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 119 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK120" description="sticky reload lock for fuse word 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 120 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 120 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK121" description="sticky reload lock for fuse word 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 121 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 121 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK122" description="sticky reload lock for fuse word 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 122 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 122 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK123" description="sticky reload lock for fuse word 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 123 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 123 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK124" description="sticky reload lock for fuse word 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 124 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 124 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK125" description="sticky reload lock for fuse word 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 125 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 125 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK126" description="sticky reload lock for fuse word 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 126 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 126 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK127" description="sticky reload lock for fuse word 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 127 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 127 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK4" description="BSEC sticky reload lock register 4" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK128" description="sticky reload lock for fuse word 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 128 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 128 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK129" description="sticky reload lock for fuse word 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 129 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 129 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK130" description="sticky reload lock for fuse word 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 130 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 130 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK131" description="sticky reload lock for fuse word 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 131 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 131 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK132" description="sticky reload lock for fuse word 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 132 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 132 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK133" description="sticky reload lock for fuse word 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 133 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 133 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK134" description="sticky reload lock for fuse word 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 134 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 134 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK135" description="sticky reload lock for fuse word 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 135 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 135 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK136" description="sticky reload lock for fuse word 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 136 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 136 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK137" description="sticky reload lock for fuse word 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 137 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 137 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK138" description="sticky reload lock for fuse word 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 138 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 138 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK139" description="sticky reload lock for fuse word 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 139 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 139 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK140" description="sticky reload lock for fuse word 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 140 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 140 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK141" description="sticky reload lock for fuse word 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 141 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 141 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK142" description="sticky reload lock for fuse word 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 142 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 142 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK143" description="sticky reload lock for fuse word 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 143 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 143 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK144" description="sticky reload lock for fuse word 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 144 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 144 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK145" description="sticky reload lock for fuse word 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 145 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 145 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK146" description="sticky reload lock for fuse word 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 146 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 146 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK147" description="sticky reload lock for fuse word 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 147 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 147 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK148" description="sticky reload lock for fuse word 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 148 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 148 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK149" description="sticky reload lock for fuse word 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 149 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 149 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK150" description="sticky reload lock for fuse word 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 150 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 150 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK151" description="sticky reload lock for fuse word 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 151 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 151 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK152" description="sticky reload lock for fuse word 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 152 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 152 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK153" description="sticky reload lock for fuse word 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 153 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 153 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK154" description="sticky reload lock for fuse word 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 154 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 154 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK155" description="sticky reload lock for fuse word 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 155 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 155 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK156" description="sticky reload lock for fuse word 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 156 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 156 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK157" description="sticky reload lock for fuse word 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 157 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 157 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK158" description="sticky reload lock for fuse word 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 158 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 158 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK159" description="sticky reload lock for fuse word 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 159 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 159 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK5" description="BSEC sticky reload lock register 5" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK160" description="sticky reload lock for fuse word 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 160 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 160 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK161" description="sticky reload lock for fuse word 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 161 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 161 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK162" description="sticky reload lock for fuse word 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 162 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 162 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK163" description="sticky reload lock for fuse word 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 163 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 163 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK164" description="sticky reload lock for fuse word 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 164 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 164 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK165" description="sticky reload lock for fuse word 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 165 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 165 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK166" description="sticky reload lock for fuse word 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 166 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 166 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK167" description="sticky reload lock for fuse word 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 167 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 167 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK168" description="sticky reload lock for fuse word 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 168 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 168 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK169" description="sticky reload lock for fuse word 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 169 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 169 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK170" description="sticky reload lock for fuse word 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 170 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 170 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK171" description="sticky reload lock for fuse word 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 171 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 171 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK172" description="sticky reload lock for fuse word 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 172 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 172 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK173" description="sticky reload lock for fuse word 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 173 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 173 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK174" description="sticky reload lock for fuse word 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 174 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 174 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK175" description="sticky reload lock for fuse word 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 175 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 175 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK176" description="sticky reload lock for fuse word 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 176 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 176 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK177" description="sticky reload lock for fuse word 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 177 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 177 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK178" description="sticky reload lock for fuse word 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 178 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 178 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK179" description="sticky reload lock for fuse word 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 179 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 179 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK180" description="sticky reload lock for fuse word 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 180 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 180 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK181" description="sticky reload lock for fuse word 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 181 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 181 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK182" description="sticky reload lock for fuse word 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 182 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 182 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK183" description="sticky reload lock for fuse word 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 183 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 183 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK184" description="sticky reload lock for fuse word 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 184 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 184 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK185" description="sticky reload lock for fuse word 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 185 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 185 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK186" description="sticky reload lock for fuse word 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 186 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 186 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK187" description="sticky reload lock for fuse word 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 187 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 187 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK188" description="sticky reload lock for fuse word 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 188 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 188 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK189" description="sticky reload lock for fuse word 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 189 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 189 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK190" description="sticky reload lock for fuse word 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 190 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 190 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK191" description="sticky reload lock for fuse word 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 191 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 191 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK6" description="BSEC sticky reload lock register 6" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK192" description="sticky reload lock for fuse word 192" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 192 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 192 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK193" description="sticky reload lock for fuse word 193" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 193 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 193 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK194" description="sticky reload lock for fuse word 194" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 194 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 194 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK195" description="sticky reload lock for fuse word 195" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 195 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 195 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK196" description="sticky reload lock for fuse word 196" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 196 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 196 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK197" description="sticky reload lock for fuse word 197" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 197 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 197 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK198" description="sticky reload lock for fuse word 198" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 198 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 198 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK199" description="sticky reload lock for fuse word 199" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 199 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 199 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK200" description="sticky reload lock for fuse word 200" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 200 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 200 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK201" description="sticky reload lock for fuse word 201" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 201 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 201 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK202" description="sticky reload lock for fuse word 202" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 202 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 202 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK203" description="sticky reload lock for fuse word 203" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 203 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 203 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK204" description="sticky reload lock for fuse word 204" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 204 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 204 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK205" description="sticky reload lock for fuse word 205" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 205 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 205 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK206" description="sticky reload lock for fuse word 206" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 206 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 206 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK207" description="sticky reload lock for fuse word 207" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 207 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 207 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK208" description="sticky reload lock for fuse word 208" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 208 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 208 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK209" description="sticky reload lock for fuse word 209" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 209 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 209 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK210" description="sticky reload lock for fuse word 210" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 210 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 210 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK211" description="sticky reload lock for fuse word 211" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 211 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 211 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK212" description="sticky reload lock for fuse word 212" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 212 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 212 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK213" description="sticky reload lock for fuse word 213" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 213 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 213 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK214" description="sticky reload lock for fuse word 214" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 214 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 214 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK215" description="sticky reload lock for fuse word 215" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 215 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 215 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK216" description="sticky reload lock for fuse word 216" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 216 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 216 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK217" description="sticky reload lock for fuse word 217" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 217 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 217 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK218" description="sticky reload lock for fuse word 218" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 218 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 218 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK219" description="sticky reload lock for fuse word 219" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 219 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 219 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK220" description="sticky reload lock for fuse word 220" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 220 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 220 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK221" description="sticky reload lock for fuse word 221" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 221 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 221 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK222" description="sticky reload lock for fuse word 222" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 222 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 222 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK223" description="sticky reload lock for fuse word 223" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 223 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 223 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK7" description="BSEC sticky reload lock register 7" start="+0x89C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK224" description="sticky reload lock for fuse word 224" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 224 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 224 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK225" description="sticky reload lock for fuse word 225" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 225 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 225 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK226" description="sticky reload lock for fuse word 226" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 226 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 226 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK227" description="sticky reload lock for fuse word 227" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 227 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 227 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK228" description="sticky reload lock for fuse word 228" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 228 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 228 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK229" description="sticky reload lock for fuse word 229" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 229 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 229 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK230" description="sticky reload lock for fuse word 230" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 230 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 230 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK231" description="sticky reload lock for fuse word 231" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 231 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 231 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK232" description="sticky reload lock for fuse word 232" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 232 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 232 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK233" description="sticky reload lock for fuse word 233" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 233 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 233 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK234" description="sticky reload lock for fuse word 234" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 234 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 234 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK235" description="sticky reload lock for fuse word 235" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 235 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 235 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK236" description="sticky reload lock for fuse word 236" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 236 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 236 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK237" description="sticky reload lock for fuse word 237" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 237 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 237 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK238" description="sticky reload lock for fuse word 238" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 238 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 238 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK239" description="sticky reload lock for fuse word 239" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 239 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 239 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK240" description="sticky reload lock for fuse word 240" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 240 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 240 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK241" description="sticky reload lock for fuse word 241" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 241 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 241 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK242" description="sticky reload lock for fuse word 242" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 242 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 242 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK243" description="sticky reload lock for fuse word 243" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 243 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 243 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK244" description="sticky reload lock for fuse word 244" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 244 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 244 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK245" description="sticky reload lock for fuse word 245" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 245 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 245 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK246" description="sticky reload lock for fuse word 246" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 246 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 246 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK247" description="sticky reload lock for fuse word 247" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 247 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 247 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK248" description="sticky reload lock for fuse word 248" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 248 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 248 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK249" description="sticky reload lock for fuse word 249" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 249 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 249 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK250" description="sticky reload lock for fuse word 250" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 250 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 250 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK251" description="sticky reload lock for fuse word 251" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 251 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 251 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK252" description="sticky reload lock for fuse word 252" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 252 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 252 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK253" description="sticky reload lock for fuse word 253" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 253 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 253 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK254" description="sticky reload lock for fuse word 254" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 254 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 254 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK255" description="sticky reload lock for fuse word 255" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 255 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 255 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK8" description="BSEC sticky reload lock register 8" start="+0x8A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK256" description="sticky reload lock for fuse word 256" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 256 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 256 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK257" description="sticky reload lock for fuse word 257" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 257 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 257 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK258" description="sticky reload lock for fuse word 258" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 258 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 258 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK259" description="sticky reload lock for fuse word 259" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 259 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 259 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK260" description="sticky reload lock for fuse word 260" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 260 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 260 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK261" description="sticky reload lock for fuse word 261" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 261 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 261 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK262" description="sticky reload lock for fuse word 262" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 262 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 262 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK263" description="sticky reload lock for fuse word 263" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 263 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 263 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK264" description="sticky reload lock for fuse word 264" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 264 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 264 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK265" description="sticky reload lock for fuse word 265" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 265 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 265 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK266" description="sticky reload lock for fuse word 266" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 266 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 266 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK267" description="sticky reload lock for fuse word 267" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 267 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 267 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK268" description="sticky reload lock for fuse word 268" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 268 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 268 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK269" description="sticky reload lock for fuse word 269" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 269 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 269 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK270" description="sticky reload lock for fuse word 270" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 270 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 270 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK271" description="sticky reload lock for fuse word 271" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 271 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 271 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK272" description="sticky reload lock for fuse word 272" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 272 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 272 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK273" description="sticky reload lock for fuse word 273" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 273 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 273 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK274" description="sticky reload lock for fuse word 274" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 274 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 274 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK275" description="sticky reload lock for fuse word 275" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 275 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 275 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK276" description="sticky reload lock for fuse word 276" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 276 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 276 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK277" description="sticky reload lock for fuse word 277" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 277 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 277 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK278" description="sticky reload lock for fuse word 278" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 278 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 278 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK279" description="sticky reload lock for fuse word 279" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 279 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 279 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK280" description="sticky reload lock for fuse word 280" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 280 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 280 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK281" description="sticky reload lock for fuse word 281" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 281 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 281 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK282" description="sticky reload lock for fuse word 282" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 282 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 282 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK283" description="sticky reload lock for fuse word 283" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 283 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 283 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK284" description="sticky reload lock for fuse word 284" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 284 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 284 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK285" description="sticky reload lock for fuse word 285" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 285 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 285 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK286" description="sticky reload lock for fuse word 286" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 286 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 286 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK287" description="sticky reload lock for fuse word 287" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 287 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 287 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK9" description="BSEC sticky reload lock register 9" start="+0x8A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK288" description="sticky reload lock for fuse word 288" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 288 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 288 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK289" description="sticky reload lock for fuse word 289" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 289 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 289 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK290" description="sticky reload lock for fuse word 290" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 290 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 290 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK291" description="sticky reload lock for fuse word 291" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 291 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 291 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK292" description="sticky reload lock for fuse word 292" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 292 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 292 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK293" description="sticky reload lock for fuse word 293" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 293 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 293 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK294" description="sticky reload lock for fuse word 294" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 294 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 294 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK295" description="sticky reload lock for fuse word 295" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 295 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 295 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK296" description="sticky reload lock for fuse word 296" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 296 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 296 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK297" description="sticky reload lock for fuse word 297" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 297 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 297 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK298" description="sticky reload lock for fuse word 298" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 298 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 298 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK299" description="sticky reload lock for fuse word 299" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 299 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 299 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK300" description="sticky reload lock for fuse word 300" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 300 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 300 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK301" description="sticky reload lock for fuse word 301" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 301 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 301 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK302" description="sticky reload lock for fuse word 302" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 302 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 302 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK303" description="sticky reload lock for fuse word 303" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 303 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 303 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK304" description="sticky reload lock for fuse word 304" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 304 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 304 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK305" description="sticky reload lock for fuse word 305" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 305 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 305 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK306" description="sticky reload lock for fuse word 306" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 306 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 306 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK307" description="sticky reload lock for fuse word 307" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 307 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 307 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK308" description="sticky reload lock for fuse word 308" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 308 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 308 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK309" description="sticky reload lock for fuse word 309" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 309 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 309 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK310" description="sticky reload lock for fuse word 310" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 310 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 310 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK311" description="sticky reload lock for fuse word 311" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 311 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 311 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK312" description="sticky reload lock for fuse word 312" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 312 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 312 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK313" description="sticky reload lock for fuse word 313" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 313 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 313 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK314" description="sticky reload lock for fuse word 314" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 314 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 314 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK315" description="sticky reload lock for fuse word 315" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 315 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 315 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK316" description="sticky reload lock for fuse word 316" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 316 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 316 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK317" description="sticky reload lock for fuse word 317" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 317 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 317 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK318" description="sticky reload lock for fuse word 318" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 318 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 318 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK319" description="sticky reload lock for fuse word 319" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 319 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 319 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK10" description="BSEC sticky reload lock register 10" start="+0x8A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK320" description="sticky reload lock for fuse word 320" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 320 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 320 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK321" description="sticky reload lock for fuse word 321" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 321 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 321 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK322" description="sticky reload lock for fuse word 322" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 322 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 322 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK323" description="sticky reload lock for fuse word 323" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 323 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 323 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK324" description="sticky reload lock for fuse word 324" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 324 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 324 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK325" description="sticky reload lock for fuse word 325" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 325 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 325 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK326" description="sticky reload lock for fuse word 326" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 326 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 326 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK327" description="sticky reload lock for fuse word 327" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 327 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 327 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK328" description="sticky reload lock for fuse word 328" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 328 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 328 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK329" description="sticky reload lock for fuse word 329" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 329 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 329 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK330" description="sticky reload lock for fuse word 330" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 330 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 330 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK331" description="sticky reload lock for fuse word 331" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 331 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 331 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK332" description="sticky reload lock for fuse word 332" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 332 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 332 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK333" description="sticky reload lock for fuse word 333" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 333 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 333 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK334" description="sticky reload lock for fuse word 334" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 334 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 334 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK335" description="sticky reload lock for fuse word 335" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 335 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 335 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK336" description="sticky reload lock for fuse word 336" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 336 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 336 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK337" description="sticky reload lock for fuse word 337" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 337 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 337 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK338" description="sticky reload lock for fuse word 338" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 338 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 338 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK339" description="sticky reload lock for fuse word 339" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 339 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 339 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK340" description="sticky reload lock for fuse word 340" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 340 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 340 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK341" description="sticky reload lock for fuse word 341" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 341 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 341 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK342" description="sticky reload lock for fuse word 342" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 342 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 342 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK343" description="sticky reload lock for fuse word 343" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 343 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 343 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK344" description="sticky reload lock for fuse word 344" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 344 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 344 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK345" description="sticky reload lock for fuse word 345" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 345 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 345 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK346" description="sticky reload lock for fuse word 346" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 346 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 346 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK347" description="sticky reload lock for fuse word 347" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 347 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 347 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK348" description="sticky reload lock for fuse word 348" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 348 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 348 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK349" description="sticky reload lock for fuse word 349" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 349 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 349 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK350" description="sticky reload lock for fuse word 350" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 350 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 350 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK351" description="sticky reload lock for fuse word 351" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 351 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 351 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SRLOCK11" description="BSEC sticky reload lock register 11" start="+0x8AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRLOCK352" description="sticky reload lock for fuse word 352" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 352 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 352 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK353" description="sticky reload lock for fuse word 353" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 353 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 353 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK354" description="sticky reload lock for fuse word 354" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 354 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 354 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK355" description="sticky reload lock for fuse word 355" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 355 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 355 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK356" description="sticky reload lock for fuse word 356" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 356 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 356 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK357" description="sticky reload lock for fuse word 357" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 357 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 357 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK358" description="sticky reload lock for fuse word 358" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 358 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 358 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK359" description="sticky reload lock for fuse word 359" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 359 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 359 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK360" description="sticky reload lock for fuse word 360" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 360 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 360 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK361" description="sticky reload lock for fuse word 361" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 361 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 361 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK362" description="sticky reload lock for fuse word 362" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 362 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 362 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK363" description="sticky reload lock for fuse word 363" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 363 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 363 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK364" description="sticky reload lock for fuse word 364" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 364 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 364 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK365" description="sticky reload lock for fuse word 365" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 365 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 365 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK366" description="sticky reload lock for fuse word 366" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 366 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 366 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK367" description="sticky reload lock for fuse word 367" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 367 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 367 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK368" description="sticky reload lock for fuse word 368" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 368 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 368 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK369" description="sticky reload lock for fuse word 369" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 369 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 369 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK370" description="sticky reload lock for fuse word 370" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 370 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 370 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK371" description="sticky reload lock for fuse word 371" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 371 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 371 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK372" description="sticky reload lock for fuse word 372" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 372 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 372 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK373" description="sticky reload lock for fuse word 373" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 373 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 373 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK374" description="sticky reload lock for fuse word 374" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 374 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 374 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK375" description="sticky reload lock for fuse word 375" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 375 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 375 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK376" description="sticky reload lock for fuse word 376" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 376 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 376 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK377" description="sticky reload lock for fuse word 377" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 377 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 377 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK378" description="sticky reload lock for fuse word 378" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 378 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 378 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK379" description="sticky reload lock for fuse word 379" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 379 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 379 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK380" description="sticky reload lock for fuse word 380" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 380 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 380 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK381" description="sticky reload lock for fuse word 381" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 381 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 381 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK382" description="sticky reload lock for fuse word 382" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 382 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 382 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SRLOCK383" description="sticky reload lock for fuse word 383" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word 383 loading through BSEC_OTPCR is authorized." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word 383 loading through BSEC_OTPCR is denied until next cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR0" description="BSEC OTP valid register 0" start="+0x8C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF0" description="Valid flag for shadow register 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 0 was last reloaded. The value read from BSEC_FVR0 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 0 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF1" description="Valid flag for shadow register 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 1 was last reloaded. The value read from BSEC_FVR1 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 1 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF2" description="Valid flag for shadow register 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 2 was last reloaded. The value read from BSEC_FVR2 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 2 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF3" description="Valid flag for shadow register 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 3 was last reloaded. The value read from BSEC_FVR3 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 3 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF4" description="Valid flag for shadow register 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 4 was last reloaded. The value read from BSEC_FVR4 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 4 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF5" description="Valid flag for shadow register 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 5 was last reloaded. The value read from BSEC_FVR5 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 5 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF6" description="Valid flag for shadow register 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 6 was last reloaded. The value read from BSEC_FVR6 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 6 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF7" description="Valid flag for shadow register 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 7 was last reloaded. The value read from BSEC_FVR7 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 7 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF8" description="Valid flag for shadow register 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 8 was last reloaded. The value read from BSEC_FVR8 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 8 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF9" description="Valid flag for shadow register 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 9 was last reloaded. The value read from BSEC_FVR9 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 9 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF10" description="Valid flag for shadow register 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 10 was last reloaded. The value read from BSEC_FVR10 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 10 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF11" description="Valid flag for shadow register 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 11 was last reloaded. The value read from BSEC_FVR11 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 11 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF12" description="Valid flag for shadow register 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 12 was last reloaded. The value read from BSEC_FVR12 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 12 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF13" description="Valid flag for shadow register 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 13 was last reloaded. The value read from BSEC_FVR13 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 13 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF14" description="Valid flag for shadow register 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 14 was last reloaded. The value read from BSEC_FVR14 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 14 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF15" description="Valid flag for shadow register 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 15 was last reloaded. The value read from BSEC_FVR15 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 15 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF16" description="Valid flag for shadow register 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 16 was last reloaded. The value read from BSEC_FVR16 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 16 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF17" description="Valid flag for shadow register 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 17 was last reloaded. The value read from BSEC_FVR17 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 17 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF18" description="Valid flag for shadow register 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 18 was last reloaded. The value read from BSEC_FVR18 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 18 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF19" description="Valid flag for shadow register 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 19 was last reloaded. The value read from BSEC_FVR19 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 19 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF20" description="Valid flag for shadow register 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 20 was last reloaded. The value read from BSEC_FVR20 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 20 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF21" description="Valid flag for shadow register 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 21 was last reloaded. The value read from BSEC_FVR21 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 21 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF22" description="Valid flag for shadow register 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 22 was last reloaded. The value read from BSEC_FVR22 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 22 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF23" description="Valid flag for shadow register 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 23 was last reloaded. The value read from BSEC_FVR23 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 23 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF24" description="Valid flag for shadow register 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 24 was last reloaded. The value read from BSEC_FVR24 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 24 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF25" description="Valid flag for shadow register 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 25 was last reloaded. The value read from BSEC_FVR25 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 25 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF26" description="Valid flag for shadow register 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 26 was last reloaded. The value read from BSEC_FVR26 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 26 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF27" description="Valid flag for shadow register 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 27 was last reloaded. The value read from BSEC_FVR27 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 27 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF28" description="Valid flag for shadow register 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 28 was last reloaded. The value read from BSEC_FVR28 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 28 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF29" description="Valid flag for shadow register 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 29 was last reloaded. The value read from BSEC_FVR29 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 29 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF30" description="Valid flag for shadow register 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 30 was last reloaded. The value read from BSEC_FVR30 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 30 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF31" description="Valid flag for shadow register 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 31 was last reloaded. The value read from BSEC_FVR31 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 31 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR1" description="BSEC OTP valid register 1" start="+0x8C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF32" description="Valid flag for shadow register 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 32 was last reloaded. The value read from BSEC_FVR32 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 32 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF33" description="Valid flag for shadow register 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 33 was last reloaded. The value read from BSEC_FVR33 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 33 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF34" description="Valid flag for shadow register 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 34 was last reloaded. The value read from BSEC_FVR34 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 34 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF35" description="Valid flag for shadow register 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 35 was last reloaded. The value read from BSEC_FVR35 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 35 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF36" description="Valid flag for shadow register 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 36 was last reloaded. The value read from BSEC_FVR36 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 36 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF37" description="Valid flag for shadow register 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 37 was last reloaded. The value read from BSEC_FVR37 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 37 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF38" description="Valid flag for shadow register 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 38 was last reloaded. The value read from BSEC_FVR38 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 38 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF39" description="Valid flag for shadow register 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 39 was last reloaded. The value read from BSEC_FVR39 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 39 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF40" description="Valid flag for shadow register 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 40 was last reloaded. The value read from BSEC_FVR40 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 40 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF41" description="Valid flag for shadow register 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 41 was last reloaded. The value read from BSEC_FVR41 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 41 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF42" description="Valid flag for shadow register 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 42 was last reloaded. The value read from BSEC_FVR42 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 42 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF43" description="Valid flag for shadow register 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 43 was last reloaded. The value read from BSEC_FVR43 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 43 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF44" description="Valid flag for shadow register 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 44 was last reloaded. The value read from BSEC_FVR44 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 44 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF45" description="Valid flag for shadow register 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 45 was last reloaded. The value read from BSEC_FVR45 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 45 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF46" description="Valid flag for shadow register 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 46 was last reloaded. The value read from BSEC_FVR46 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 46 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF47" description="Valid flag for shadow register 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 47 was last reloaded. The value read from BSEC_FVR47 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 47 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF48" description="Valid flag for shadow register 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 48 was last reloaded. The value read from BSEC_FVR48 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 48 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF49" description="Valid flag for shadow register 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 49 was last reloaded. The value read from BSEC_FVR49 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 49 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF50" description="Valid flag for shadow register 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 50 was last reloaded. The value read from BSEC_FVR50 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 50 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF51" description="Valid flag for shadow register 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 51 was last reloaded. The value read from BSEC_FVR51 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 51 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF52" description="Valid flag for shadow register 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 52 was last reloaded. The value read from BSEC_FVR52 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 52 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF53" description="Valid flag for shadow register 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 53 was last reloaded. The value read from BSEC_FVR53 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 53 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF54" description="Valid flag for shadow register 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 54 was last reloaded. The value read from BSEC_FVR54 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 54 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF55" description="Valid flag for shadow register 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 55 was last reloaded. The value read from BSEC_FVR55 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 55 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF56" description="Valid flag for shadow register 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 56 was last reloaded. The value read from BSEC_FVR56 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 56 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF57" description="Valid flag for shadow register 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 57 was last reloaded. The value read from BSEC_FVR57 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 57 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF58" description="Valid flag for shadow register 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 58 was last reloaded. The value read from BSEC_FVR58 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 58 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF59" description="Valid flag for shadow register 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 59 was last reloaded. The value read from BSEC_FVR59 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 59 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF60" description="Valid flag for shadow register 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 60 was last reloaded. The value read from BSEC_FVR60 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 60 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF61" description="Valid flag for shadow register 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 61 was last reloaded. The value read from BSEC_FVR61 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 61 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF62" description="Valid flag for shadow register 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 62 was last reloaded. The value read from BSEC_FVR62 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 62 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF63" description="Valid flag for shadow register 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 63 was last reloaded. The value read from BSEC_FVR63 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 63 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR2" description="BSEC OTP valid register 2" start="+0x8C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF64" description="Valid flag for shadow register 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 64 was last reloaded. The value read from BSEC_FVR64 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 64 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF65" description="Valid flag for shadow register 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 65 was last reloaded. The value read from BSEC_FVR65 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 65 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF66" description="Valid flag for shadow register 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 66 was last reloaded. The value read from BSEC_FVR66 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 66 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF67" description="Valid flag for shadow register 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 67 was last reloaded. The value read from BSEC_FVR67 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 67 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF68" description="Valid flag for shadow register 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 68 was last reloaded. The value read from BSEC_FVR68 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 68 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF69" description="Valid flag for shadow register 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 69 was last reloaded. The value read from BSEC_FVR69 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 69 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF70" description="Valid flag for shadow register 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 70 was last reloaded. The value read from BSEC_FVR70 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 70 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF71" description="Valid flag for shadow register 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 71 was last reloaded. The value read from BSEC_FVR71 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 71 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF72" description="Valid flag for shadow register 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 72 was last reloaded. The value read from BSEC_FVR72 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 72 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF73" description="Valid flag for shadow register 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 73 was last reloaded. The value read from BSEC_FVR73 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 73 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF74" description="Valid flag for shadow register 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 74 was last reloaded. The value read from BSEC_FVR74 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 74 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF75" description="Valid flag for shadow register 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 75 was last reloaded. The value read from BSEC_FVR75 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 75 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF76" description="Valid flag for shadow register 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 76 was last reloaded. The value read from BSEC_FVR76 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 76 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF77" description="Valid flag for shadow register 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 77 was last reloaded. The value read from BSEC_FVR77 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 77 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF78" description="Valid flag for shadow register 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 78 was last reloaded. The value read from BSEC_FVR78 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 78 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF79" description="Valid flag for shadow register 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 79 was last reloaded. The value read from BSEC_FVR79 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 79 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF80" description="Valid flag for shadow register 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 80 was last reloaded. The value read from BSEC_FVR80 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 80 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF81" description="Valid flag for shadow register 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 81 was last reloaded. The value read from BSEC_FVR81 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 81 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF82" description="Valid flag for shadow register 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 82 was last reloaded. The value read from BSEC_FVR82 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 82 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF83" description="Valid flag for shadow register 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 83 was last reloaded. The value read from BSEC_FVR83 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 83 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF84" description="Valid flag for shadow register 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 84 was last reloaded. The value read from BSEC_FVR84 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 84 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF85" description="Valid flag for shadow register 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 85 was last reloaded. The value read from BSEC_FVR85 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 85 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF86" description="Valid flag for shadow register 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 86 was last reloaded. The value read from BSEC_FVR86 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 86 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF87" description="Valid flag for shadow register 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 87 was last reloaded. The value read from BSEC_FVR87 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 87 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF88" description="Valid flag for shadow register 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 88 was last reloaded. The value read from BSEC_FVR88 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 88 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF89" description="Valid flag for shadow register 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 89 was last reloaded. The value read from BSEC_FVR89 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 89 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF90" description="Valid flag for shadow register 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 90 was last reloaded. The value read from BSEC_FVR90 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 90 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF91" description="Valid flag for shadow register 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 91 was last reloaded. The value read from BSEC_FVR91 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 91 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF92" description="Valid flag for shadow register 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 92 was last reloaded. The value read from BSEC_FVR92 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 92 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF93" description="Valid flag for shadow register 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 93 was last reloaded. The value read from BSEC_FVR93 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 93 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF94" description="Valid flag for shadow register 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 94 was last reloaded. The value read from BSEC_FVR94 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 94 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF95" description="Valid flag for shadow register 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 95 was last reloaded. The value read from BSEC_FVR95 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 95 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR3" description="BSEC OTP valid register 3" start="+0x8CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF96" description="Valid flag for shadow register 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 96 was last reloaded. The value read from BSEC_FVR96 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 96 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF97" description="Valid flag for shadow register 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 97 was last reloaded. The value read from BSEC_FVR97 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 97 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF98" description="Valid flag for shadow register 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 98 was last reloaded. The value read from BSEC_FVR98 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 98 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF99" description="Valid flag for shadow register 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 99 was last reloaded. The value read from BSEC_FVR99 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 99 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF100" description="Valid flag for shadow register 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 100 was last reloaded. The value read from BSEC_FVR100 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 100 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF101" description="Valid flag for shadow register 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 101 was last reloaded. The value read from BSEC_FVR101 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 101 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF102" description="Valid flag for shadow register 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 102 was last reloaded. The value read from BSEC_FVR102 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 102 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF103" description="Valid flag for shadow register 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 103 was last reloaded. The value read from BSEC_FVR103 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 103 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF104" description="Valid flag for shadow register 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 104 was last reloaded. The value read from BSEC_FVR104 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 104 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF105" description="Valid flag for shadow register 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 105 was last reloaded. The value read from BSEC_FVR105 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 105 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF106" description="Valid flag for shadow register 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 106 was last reloaded. The value read from BSEC_FVR106 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 106 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF107" description="Valid flag for shadow register 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 107 was last reloaded. The value read from BSEC_FVR107 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 107 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF108" description="Valid flag for shadow register 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 108 was last reloaded. The value read from BSEC_FVR108 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 108 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF109" description="Valid flag for shadow register 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 109 was last reloaded. The value read from BSEC_FVR109 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 109 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF110" description="Valid flag for shadow register 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 110 was last reloaded. The value read from BSEC_FVR110 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 110 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF111" description="Valid flag for shadow register 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 111 was last reloaded. The value read from BSEC_FVR111 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 111 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF112" description="Valid flag for shadow register 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 112 was last reloaded. The value read from BSEC_FVR112 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 112 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF113" description="Valid flag for shadow register 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 113 was last reloaded. The value read from BSEC_FVR113 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 113 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF114" description="Valid flag for shadow register 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 114 was last reloaded. The value read from BSEC_FVR114 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 114 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF115" description="Valid flag for shadow register 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 115 was last reloaded. The value read from BSEC_FVR115 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 115 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF116" description="Valid flag for shadow register 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 116 was last reloaded. The value read from BSEC_FVR116 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 116 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF117" description="Valid flag for shadow register 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 117 was last reloaded. The value read from BSEC_FVR117 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 117 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF118" description="Valid flag for shadow register 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 118 was last reloaded. The value read from BSEC_FVR118 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 118 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF119" description="Valid flag for shadow register 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 119 was last reloaded. The value read from BSEC_FVR119 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 119 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF120" description="Valid flag for shadow register 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 120 was last reloaded. The value read from BSEC_FVR120 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 120 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF121" description="Valid flag for shadow register 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 121 was last reloaded. The value read from BSEC_FVR121 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 121 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF122" description="Valid flag for shadow register 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 122 was last reloaded. The value read from BSEC_FVR122 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 122 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF123" description="Valid flag for shadow register 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 123 was last reloaded. The value read from BSEC_FVR123 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 123 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF124" description="Valid flag for shadow register 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 124 was last reloaded. The value read from BSEC_FVR124 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 124 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF125" description="Valid flag for shadow register 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 125 was last reloaded. The value read from BSEC_FVR125 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 125 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF126" description="Valid flag for shadow register 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 126 was last reloaded. The value read from BSEC_FVR126 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 126 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF127" description="Valid flag for shadow register 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 127 was last reloaded. The value read from BSEC_FVR127 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 127 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR4" description="BSEC OTP valid register 4" start="+0x8D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF128" description="Valid flag for shadow register 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 128 was last reloaded. The value read from BSEC_FVR128 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 128 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF129" description="Valid flag for shadow register 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 129 was last reloaded. The value read from BSEC_FVR129 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 129 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF130" description="Valid flag for shadow register 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 130 was last reloaded. The value read from BSEC_FVR130 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 130 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF131" description="Valid flag for shadow register 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 131 was last reloaded. The value read from BSEC_FVR131 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 131 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF132" description="Valid flag for shadow register 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 132 was last reloaded. The value read from BSEC_FVR132 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 132 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF133" description="Valid flag for shadow register 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 133 was last reloaded. The value read from BSEC_FVR133 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 133 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF134" description="Valid flag for shadow register 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 134 was last reloaded. The value read from BSEC_FVR134 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 134 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF135" description="Valid flag for shadow register 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 135 was last reloaded. The value read from BSEC_FVR135 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 135 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF136" description="Valid flag for shadow register 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 136 was last reloaded. The value read from BSEC_FVR136 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 136 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF137" description="Valid flag for shadow register 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 137 was last reloaded. The value read from BSEC_FVR137 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 137 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF138" description="Valid flag for shadow register 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 138 was last reloaded. The value read from BSEC_FVR138 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 138 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF139" description="Valid flag for shadow register 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 139 was last reloaded. The value read from BSEC_FVR139 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 139 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF140" description="Valid flag for shadow register 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 140 was last reloaded. The value read from BSEC_FVR140 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 140 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF141" description="Valid flag for shadow register 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 141 was last reloaded. The value read from BSEC_FVR141 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 141 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF142" description="Valid flag for shadow register 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 142 was last reloaded. The value read from BSEC_FVR142 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 142 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF143" description="Valid flag for shadow register 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 143 was last reloaded. The value read from BSEC_FVR143 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 143 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF144" description="Valid flag for shadow register 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 144 was last reloaded. The value read from BSEC_FVR144 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 144 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF145" description="Valid flag for shadow register 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 145 was last reloaded. The value read from BSEC_FVR145 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 145 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF146" description="Valid flag for shadow register 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 146 was last reloaded. The value read from BSEC_FVR146 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 146 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF147" description="Valid flag for shadow register 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 147 was last reloaded. The value read from BSEC_FVR147 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 147 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF148" description="Valid flag for shadow register 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 148 was last reloaded. The value read from BSEC_FVR148 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 148 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF149" description="Valid flag for shadow register 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 149 was last reloaded. The value read from BSEC_FVR149 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 149 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF150" description="Valid flag for shadow register 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 150 was last reloaded. The value read from BSEC_FVR150 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 150 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF151" description="Valid flag for shadow register 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 151 was last reloaded. The value read from BSEC_FVR151 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 151 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF152" description="Valid flag for shadow register 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 152 was last reloaded. The value read from BSEC_FVR152 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 152 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF153" description="Valid flag for shadow register 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 153 was last reloaded. The value read from BSEC_FVR153 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 153 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF154" description="Valid flag for shadow register 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 154 was last reloaded. The value read from BSEC_FVR154 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 154 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF155" description="Valid flag for shadow register 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 155 was last reloaded. The value read from BSEC_FVR155 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 155 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF156" description="Valid flag for shadow register 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 156 was last reloaded. The value read from BSEC_FVR156 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 156 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF157" description="Valid flag for shadow register 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 157 was last reloaded. The value read from BSEC_FVR157 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 157 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF158" description="Valid flag for shadow register 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 158 was last reloaded. The value read from BSEC_FVR158 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 158 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF159" description="Valid flag for shadow register 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 159 was last reloaded. The value read from BSEC_FVR159 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 159 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR5" description="BSEC OTP valid register 5" start="+0x8D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF160" description="Valid flag for shadow register 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 160 was last reloaded. The value read from BSEC_FVR160 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 160 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF161" description="Valid flag for shadow register 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 161 was last reloaded. The value read from BSEC_FVR161 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 161 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF162" description="Valid flag for shadow register 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 162 was last reloaded. The value read from BSEC_FVR162 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 162 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF163" description="Valid flag for shadow register 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 163 was last reloaded. The value read from BSEC_FVR163 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 163 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF164" description="Valid flag for shadow register 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 164 was last reloaded. The value read from BSEC_FVR164 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 164 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF165" description="Valid flag for shadow register 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 165 was last reloaded. The value read from BSEC_FVR165 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 165 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF166" description="Valid flag for shadow register 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 166 was last reloaded. The value read from BSEC_FVR166 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 166 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF167" description="Valid flag for shadow register 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 167 was last reloaded. The value read from BSEC_FVR167 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 167 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF168" description="Valid flag for shadow register 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 168 was last reloaded. The value read from BSEC_FVR168 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 168 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF169" description="Valid flag for shadow register 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 169 was last reloaded. The value read from BSEC_FVR169 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 169 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF170" description="Valid flag for shadow register 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 170 was last reloaded. The value read from BSEC_FVR170 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 170 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF171" description="Valid flag for shadow register 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 171 was last reloaded. The value read from BSEC_FVR171 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 171 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF172" description="Valid flag for shadow register 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 172 was last reloaded. The value read from BSEC_FVR172 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 172 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF173" description="Valid flag for shadow register 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 173 was last reloaded. The value read from BSEC_FVR173 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 173 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF174" description="Valid flag for shadow register 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 174 was last reloaded. The value read from BSEC_FVR174 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 174 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF175" description="Valid flag for shadow register 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 175 was last reloaded. The value read from BSEC_FVR175 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 175 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF176" description="Valid flag for shadow register 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 176 was last reloaded. The value read from BSEC_FVR176 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 176 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF177" description="Valid flag for shadow register 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 177 was last reloaded. The value read from BSEC_FVR177 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 177 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF178" description="Valid flag for shadow register 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 178 was last reloaded. The value read from BSEC_FVR178 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 178 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF179" description="Valid flag for shadow register 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 179 was last reloaded. The value read from BSEC_FVR179 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 179 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF180" description="Valid flag for shadow register 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 180 was last reloaded. The value read from BSEC_FVR180 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 180 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF181" description="Valid flag for shadow register 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 181 was last reloaded. The value read from BSEC_FVR181 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 181 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF182" description="Valid flag for shadow register 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 182 was last reloaded. The value read from BSEC_FVR182 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 182 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF183" description="Valid flag for shadow register 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 183 was last reloaded. The value read from BSEC_FVR183 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 183 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF184" description="Valid flag for shadow register 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 184 was last reloaded. The value read from BSEC_FVR184 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 184 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF185" description="Valid flag for shadow register 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 185 was last reloaded. The value read from BSEC_FVR185 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 185 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF186" description="Valid flag for shadow register 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 186 was last reloaded. The value read from BSEC_FVR186 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 186 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF187" description="Valid flag for shadow register 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 187 was last reloaded. The value read from BSEC_FVR187 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 187 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF188" description="Valid flag for shadow register 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 188 was last reloaded. The value read from BSEC_FVR188 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 188 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF189" description="Valid flag for shadow register 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 189 was last reloaded. The value read from BSEC_FVR189 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 189 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF190" description="Valid flag for shadow register 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 190 was last reloaded. The value read from BSEC_FVR190 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 190 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF191" description="Valid flag for shadow register 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 191 was last reloaded. The value read from BSEC_FVR191 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 191 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR6" description="BSEC OTP valid register 6" start="+0x8D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF192" description="Valid flag for shadow register 192" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 192 was last reloaded. The value read from BSEC_FVR192 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 192 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF193" description="Valid flag for shadow register 193" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 193 was last reloaded. The value read from BSEC_FVR193 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 193 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF194" description="Valid flag for shadow register 194" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 194 was last reloaded. The value read from BSEC_FVR194 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 194 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF195" description="Valid flag for shadow register 195" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 195 was last reloaded. The value read from BSEC_FVR195 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 195 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF196" description="Valid flag for shadow register 196" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 196 was last reloaded. The value read from BSEC_FVR196 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 196 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF197" description="Valid flag for shadow register 197" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 197 was last reloaded. The value read from BSEC_FVR197 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 197 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF198" description="Valid flag for shadow register 198" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 198 was last reloaded. The value read from BSEC_FVR198 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 198 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF199" description="Valid flag for shadow register 199" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 199 was last reloaded. The value read from BSEC_FVR199 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 199 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF200" description="Valid flag for shadow register 200" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 200 was last reloaded. The value read from BSEC_FVR200 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 200 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF201" description="Valid flag for shadow register 201" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 201 was last reloaded. The value read from BSEC_FVR201 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 201 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF202" description="Valid flag for shadow register 202" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 202 was last reloaded. The value read from BSEC_FVR202 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 202 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF203" description="Valid flag for shadow register 203" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 203 was last reloaded. The value read from BSEC_FVR203 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 203 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF204" description="Valid flag for shadow register 204" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 204 was last reloaded. The value read from BSEC_FVR204 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 204 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF205" description="Valid flag for shadow register 205" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 205 was last reloaded. The value read from BSEC_FVR205 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 205 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF206" description="Valid flag for shadow register 206" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 206 was last reloaded. The value read from BSEC_FVR206 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 206 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF207" description="Valid flag for shadow register 207" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 207 was last reloaded. The value read from BSEC_FVR207 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 207 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF208" description="Valid flag for shadow register 208" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 208 was last reloaded. The value read from BSEC_FVR208 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 208 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF209" description="Valid flag for shadow register 209" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 209 was last reloaded. The value read from BSEC_FVR209 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 209 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF210" description="Valid flag for shadow register 210" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 210 was last reloaded. The value read from BSEC_FVR210 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 210 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF211" description="Valid flag for shadow register 211" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 211 was last reloaded. The value read from BSEC_FVR211 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 211 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF212" description="Valid flag for shadow register 212" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 212 was last reloaded. The value read from BSEC_FVR212 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 212 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF213" description="Valid flag for shadow register 213" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 213 was last reloaded. The value read from BSEC_FVR213 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 213 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF214" description="Valid flag for shadow register 214" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 214 was last reloaded. The value read from BSEC_FVR214 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 214 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF215" description="Valid flag for shadow register 215" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 215 was last reloaded. The value read from BSEC_FVR215 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 215 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF216" description="Valid flag for shadow register 216" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 216 was last reloaded. The value read from BSEC_FVR216 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 216 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF217" description="Valid flag for shadow register 217" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 217 was last reloaded. The value read from BSEC_FVR217 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 217 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF218" description="Valid flag for shadow register 218" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 218 was last reloaded. The value read from BSEC_FVR218 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 218 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF219" description="Valid flag for shadow register 219" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 219 was last reloaded. The value read from BSEC_FVR219 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 219 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF220" description="Valid flag for shadow register 220" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 220 was last reloaded. The value read from BSEC_FVR220 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 220 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF221" description="Valid flag for shadow register 221" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 221 was last reloaded. The value read from BSEC_FVR221 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 221 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF222" description="Valid flag for shadow register 222" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 222 was last reloaded. The value read from BSEC_FVR222 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 222 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF223" description="Valid flag for shadow register 223" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 223 was last reloaded. The value read from BSEC_FVR223 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 223 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR7" description="BSEC OTP valid register 7" start="+0x8DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF224" description="Valid flag for shadow register 224" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 224 was last reloaded. The value read from BSEC_FVR224 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 224 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF225" description="Valid flag for shadow register 225" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 225 was last reloaded. The value read from BSEC_FVR225 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 225 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF226" description="Valid flag for shadow register 226" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 226 was last reloaded. The value read from BSEC_FVR226 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 226 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF227" description="Valid flag for shadow register 227" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 227 was last reloaded. The value read from BSEC_FVR227 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 227 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF228" description="Valid flag for shadow register 228" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 228 was last reloaded. The value read from BSEC_FVR228 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 228 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF229" description="Valid flag for shadow register 229" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 229 was last reloaded. The value read from BSEC_FVR229 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 229 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF230" description="Valid flag for shadow register 230" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 230 was last reloaded. The value read from BSEC_FVR230 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 230 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF231" description="Valid flag for shadow register 231" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 231 was last reloaded. The value read from BSEC_FVR231 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 231 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF232" description="Valid flag for shadow register 232" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 232 was last reloaded. The value read from BSEC_FVR232 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 232 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF233" description="Valid flag for shadow register 233" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 233 was last reloaded. The value read from BSEC_FVR233 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 233 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF234" description="Valid flag for shadow register 234" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 234 was last reloaded. The value read from BSEC_FVR234 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 234 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF235" description="Valid flag for shadow register 235" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 235 was last reloaded. The value read from BSEC_FVR235 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 235 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF236" description="Valid flag for shadow register 236" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 236 was last reloaded. The value read from BSEC_FVR236 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 236 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF237" description="Valid flag for shadow register 237" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 237 was last reloaded. The value read from BSEC_FVR237 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 237 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF238" description="Valid flag for shadow register 238" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 238 was last reloaded. The value read from BSEC_FVR238 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 238 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF239" description="Valid flag for shadow register 239" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 239 was last reloaded. The value read from BSEC_FVR239 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 239 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF240" description="Valid flag for shadow register 240" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 240 was last reloaded. The value read from BSEC_FVR240 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 240 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF241" description="Valid flag for shadow register 241" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 241 was last reloaded. The value read from BSEC_FVR241 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 241 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF242" description="Valid flag for shadow register 242" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 242 was last reloaded. The value read from BSEC_FVR242 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 242 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF243" description="Valid flag for shadow register 243" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 243 was last reloaded. The value read from BSEC_FVR243 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 243 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF244" description="Valid flag for shadow register 244" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 244 was last reloaded. The value read from BSEC_FVR244 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 244 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF245" description="Valid flag for shadow register 245" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 245 was last reloaded. The value read from BSEC_FVR245 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 245 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF246" description="Valid flag for shadow register 246" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 246 was last reloaded. The value read from BSEC_FVR246 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 246 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF247" description="Valid flag for shadow register 247" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 247 was last reloaded. The value read from BSEC_FVR247 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 247 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF248" description="Valid flag for shadow register 248" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 248 was last reloaded. The value read from BSEC_FVR248 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 248 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF249" description="Valid flag for shadow register 249" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 249 was last reloaded. The value read from BSEC_FVR249 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 249 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF250" description="Valid flag for shadow register 250" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 250 was last reloaded. The value read from BSEC_FVR250 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 250 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF251" description="Valid flag for shadow register 251" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 251 was last reloaded. The value read from BSEC_FVR251 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 251 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF252" description="Valid flag for shadow register 252" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 252 was last reloaded. The value read from BSEC_FVR252 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 252 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF253" description="Valid flag for shadow register 253" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 253 was last reloaded. The value read from BSEC_FVR253 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 253 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF254" description="Valid flag for shadow register 254" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 254 was last reloaded. The value read from BSEC_FVR254 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 254 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF255" description="Valid flag for shadow register 255" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 255 was last reloaded. The value read from BSEC_FVR255 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 255 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR8" description="BSEC OTP valid register 8" start="+0x8E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF256" description="Valid flag for shadow register 256" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 256 was last reloaded. The value read from BSEC_FVR256 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 256 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF257" description="Valid flag for shadow register 257" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 257 was last reloaded. The value read from BSEC_FVR257 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 257 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF258" description="Valid flag for shadow register 258" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 258 was last reloaded. The value read from BSEC_FVR258 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 258 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF259" description="Valid flag for shadow register 259" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 259 was last reloaded. The value read from BSEC_FVR259 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 259 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF260" description="Valid flag for shadow register 260" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 260 was last reloaded. The value read from BSEC_FVR260 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 260 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF261" description="Valid flag for shadow register 261" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 261 was last reloaded. The value read from BSEC_FVR261 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 261 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF262" description="Valid flag for shadow register 262" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 262 was last reloaded. The value read from BSEC_FVR262 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 262 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF263" description="Valid flag for shadow register 263" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 263 was last reloaded. The value read from BSEC_FVR263 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 263 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF264" description="Valid flag for shadow register 264" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 264 was last reloaded. The value read from BSEC_FVR264 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 264 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF265" description="Valid flag for shadow register 265" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 265 was last reloaded. The value read from BSEC_FVR265 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 265 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF266" description="Valid flag for shadow register 266" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 266 was last reloaded. The value read from BSEC_FVR266 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 266 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF267" description="Valid flag for shadow register 267" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 267 was last reloaded. The value read from BSEC_FVR267 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 267 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF268" description="Valid flag for shadow register 268" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 268 was last reloaded. The value read from BSEC_FVR268 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 268 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF269" description="Valid flag for shadow register 269" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 269 was last reloaded. The value read from BSEC_FVR269 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 269 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF270" description="Valid flag for shadow register 270" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 270 was last reloaded. The value read from BSEC_FVR270 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 270 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF271" description="Valid flag for shadow register 271" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 271 was last reloaded. The value read from BSEC_FVR271 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 271 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF272" description="Valid flag for shadow register 272" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 272 was last reloaded. The value read from BSEC_FVR272 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 272 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF273" description="Valid flag for shadow register 273" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 273 was last reloaded. The value read from BSEC_FVR273 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 273 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF274" description="Valid flag for shadow register 274" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 274 was last reloaded. The value read from BSEC_FVR274 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 274 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF275" description="Valid flag for shadow register 275" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 275 was last reloaded. The value read from BSEC_FVR275 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 275 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF276" description="Valid flag for shadow register 276" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 276 was last reloaded. The value read from BSEC_FVR276 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 276 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF277" description="Valid flag for shadow register 277" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 277 was last reloaded. The value read from BSEC_FVR277 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 277 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF278" description="Valid flag for shadow register 278" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 278 was last reloaded. The value read from BSEC_FVR278 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 278 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF279" description="Valid flag for shadow register 279" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 279 was last reloaded. The value read from BSEC_FVR279 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 279 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF280" description="Valid flag for shadow register 280" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 280 was last reloaded. The value read from BSEC_FVR280 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 280 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF281" description="Valid flag for shadow register 281" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 281 was last reloaded. The value read from BSEC_FVR281 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 281 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF282" description="Valid flag for shadow register 282" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 282 was last reloaded. The value read from BSEC_FVR282 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 282 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF283" description="Valid flag for shadow register 283" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 283 was last reloaded. The value read from BSEC_FVR283 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 283 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF284" description="Valid flag for shadow register 284" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 284 was last reloaded. The value read from BSEC_FVR284 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 284 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF285" description="Valid flag for shadow register 285" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 285 was last reloaded. The value read from BSEC_FVR285 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 285 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF286" description="Valid flag for shadow register 286" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 286 was last reloaded. The value read from BSEC_FVR286 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 286 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF287" description="Valid flag for shadow register 287" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 287 was last reloaded. The value read from BSEC_FVR287 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 287 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR9" description="BSEC OTP valid register 9" start="+0x8E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF288" description="Valid flag for shadow register 288" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 288 was last reloaded. The value read from BSEC_FVR288 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 288 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF289" description="Valid flag for shadow register 289" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 289 was last reloaded. The value read from BSEC_FVR289 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 289 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF290" description="Valid flag for shadow register 290" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 290 was last reloaded. The value read from BSEC_FVR290 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 290 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF291" description="Valid flag for shadow register 291" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 291 was last reloaded. The value read from BSEC_FVR291 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 291 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF292" description="Valid flag for shadow register 292" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 292 was last reloaded. The value read from BSEC_FVR292 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 292 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF293" description="Valid flag for shadow register 293" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 293 was last reloaded. The value read from BSEC_FVR293 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 293 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF294" description="Valid flag for shadow register 294" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 294 was last reloaded. The value read from BSEC_FVR294 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 294 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF295" description="Valid flag for shadow register 295" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 295 was last reloaded. The value read from BSEC_FVR295 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 295 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF296" description="Valid flag for shadow register 296" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 296 was last reloaded. The value read from BSEC_FVR296 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 296 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF297" description="Valid flag for shadow register 297" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 297 was last reloaded. The value read from BSEC_FVR297 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 297 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF298" description="Valid flag for shadow register 298" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 298 was last reloaded. The value read from BSEC_FVR298 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 298 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF299" description="Valid flag for shadow register 299" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 299 was last reloaded. The value read from BSEC_FVR299 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 299 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF300" description="Valid flag for shadow register 300" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 300 was last reloaded. The value read from BSEC_FVR300 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 300 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF301" description="Valid flag for shadow register 301" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 301 was last reloaded. The value read from BSEC_FVR301 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 301 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF302" description="Valid flag for shadow register 302" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 302 was last reloaded. The value read from BSEC_FVR302 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 302 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF303" description="Valid flag for shadow register 303" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 303 was last reloaded. The value read from BSEC_FVR303 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 303 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF304" description="Valid flag for shadow register 304" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 304 was last reloaded. The value read from BSEC_FVR304 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 304 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF305" description="Valid flag for shadow register 305" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 305 was last reloaded. The value read from BSEC_FVR305 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 305 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF306" description="Valid flag for shadow register 306" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 306 was last reloaded. The value read from BSEC_FVR306 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 306 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF307" description="Valid flag for shadow register 307" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 307 was last reloaded. The value read from BSEC_FVR307 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 307 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF308" description="Valid flag for shadow register 308" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 308 was last reloaded. The value read from BSEC_FVR308 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 308 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF309" description="Valid flag for shadow register 309" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 309 was last reloaded. The value read from BSEC_FVR309 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 309 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF310" description="Valid flag for shadow register 310" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 310 was last reloaded. The value read from BSEC_FVR310 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 310 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF311" description="Valid flag for shadow register 311" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 311 was last reloaded. The value read from BSEC_FVR311 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 311 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF312" description="Valid flag for shadow register 312" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 312 was last reloaded. The value read from BSEC_FVR312 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 312 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF313" description="Valid flag for shadow register 313" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 313 was last reloaded. The value read from BSEC_FVR313 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 313 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF314" description="Valid flag for shadow register 314" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 314 was last reloaded. The value read from BSEC_FVR314 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 314 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF315" description="Valid flag for shadow register 315" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 315 was last reloaded. The value read from BSEC_FVR315 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 315 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF316" description="Valid flag for shadow register 316" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 316 was last reloaded. The value read from BSEC_FVR316 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 316 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF317" description="Valid flag for shadow register 317" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 317 was last reloaded. The value read from BSEC_FVR317 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 317 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF318" description="Valid flag for shadow register 318" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 318 was last reloaded. The value read from BSEC_FVR318 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 318 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF319" description="Valid flag for shadow register 319" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 319 was last reloaded. The value read from BSEC_FVR319 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 319 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR10" description="BSEC OTP valid register 10" start="+0x8E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF320" description="Valid flag for shadow register 320" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 320 was last reloaded. The value read from BSEC_FVR320 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 320 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF321" description="Valid flag for shadow register 321" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 321 was last reloaded. The value read from BSEC_FVR321 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 321 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF322" description="Valid flag for shadow register 322" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 322 was last reloaded. The value read from BSEC_FVR322 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 322 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF323" description="Valid flag for shadow register 323" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 323 was last reloaded. The value read from BSEC_FVR323 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 323 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF324" description="Valid flag for shadow register 324" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 324 was last reloaded. The value read from BSEC_FVR324 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 324 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF325" description="Valid flag for shadow register 325" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 325 was last reloaded. The value read from BSEC_FVR325 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 325 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF326" description="Valid flag for shadow register 326" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 326 was last reloaded. The value read from BSEC_FVR326 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 326 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF327" description="Valid flag for shadow register 327" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 327 was last reloaded. The value read from BSEC_FVR327 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 327 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF328" description="Valid flag for shadow register 328" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 328 was last reloaded. The value read from BSEC_FVR328 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 328 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF329" description="Valid flag for shadow register 329" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 329 was last reloaded. The value read from BSEC_FVR329 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 329 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF330" description="Valid flag for shadow register 330" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 330 was last reloaded. The value read from BSEC_FVR330 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 330 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF331" description="Valid flag for shadow register 331" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 331 was last reloaded. The value read from BSEC_FVR331 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 331 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF332" description="Valid flag for shadow register 332" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 332 was last reloaded. The value read from BSEC_FVR332 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 332 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF333" description="Valid flag for shadow register 333" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 333 was last reloaded. The value read from BSEC_FVR333 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 333 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF334" description="Valid flag for shadow register 334" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 334 was last reloaded. The value read from BSEC_FVR334 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 334 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF335" description="Valid flag for shadow register 335" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 335 was last reloaded. The value read from BSEC_FVR335 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 335 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF336" description="Valid flag for shadow register 336" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 336 was last reloaded. The value read from BSEC_FVR336 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 336 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF337" description="Valid flag for shadow register 337" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 337 was last reloaded. The value read from BSEC_FVR337 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 337 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF338" description="Valid flag for shadow register 338" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 338 was last reloaded. The value read from BSEC_FVR338 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 338 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF339" description="Valid flag for shadow register 339" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 339 was last reloaded. The value read from BSEC_FVR339 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 339 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF340" description="Valid flag for shadow register 340" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 340 was last reloaded. The value read from BSEC_FVR340 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 340 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF341" description="Valid flag for shadow register 341" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 341 was last reloaded. The value read from BSEC_FVR341 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 341 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF342" description="Valid flag for shadow register 342" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 342 was last reloaded. The value read from BSEC_FVR342 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 342 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF343" description="Valid flag for shadow register 343" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 343 was last reloaded. The value read from BSEC_FVR343 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 343 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF344" description="Valid flag for shadow register 344" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 344 was last reloaded. The value read from BSEC_FVR344 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 344 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF345" description="Valid flag for shadow register 345" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 345 was last reloaded. The value read from BSEC_FVR345 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 345 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF346" description="Valid flag for shadow register 346" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 346 was last reloaded. The value read from BSEC_FVR346 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 346 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF347" description="Valid flag for shadow register 347" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 347 was last reloaded. The value read from BSEC_FVR347 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 347 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF348" description="Valid flag for shadow register 348" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 348 was last reloaded. The value read from BSEC_FVR348 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 348 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF349" description="Valid flag for shadow register 349" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 349 was last reloaded. The value read from BSEC_FVR349 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 349 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF350" description="Valid flag for shadow register 350" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 350 was last reloaded. The value read from BSEC_FVR350 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 350 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF351" description="Valid flag for shadow register 351" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 351 was last reloaded. The value read from BSEC_FVR351 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 351 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPVLDR11" description="BSEC OTP valid register 11" start="+0x8EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLDF352" description="Valid flag for shadow register 352" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 352 was last reloaded. The value read from BSEC_FVR352 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 352 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF353" description="Valid flag for shadow register 353" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 353 was last reloaded. The value read from BSEC_FVR353 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 353 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF354" description="Valid flag for shadow register 354" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 354 was last reloaded. The value read from BSEC_FVR354 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 354 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF355" description="Valid flag for shadow register 355" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 355 was last reloaded. The value read from BSEC_FVR355 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 355 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF356" description="Valid flag for shadow register 356" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 356 was last reloaded. The value read from BSEC_FVR356 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 356 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF357" description="Valid flag for shadow register 357" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 357 was last reloaded. The value read from BSEC_FVR357 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 357 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF358" description="Valid flag for shadow register 358" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 358 was last reloaded. The value read from BSEC_FVR358 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 358 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF359" description="Valid flag for shadow register 359" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 359 was last reloaded. The value read from BSEC_FVR359 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 359 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF360" description="Valid flag for shadow register 360" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 360 was last reloaded. The value read from BSEC_FVR360 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 360 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF361" description="Valid flag for shadow register 361" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 361 was last reloaded. The value read from BSEC_FVR361 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 361 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF362" description="Valid flag for shadow register 362" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 362 was last reloaded. The value read from BSEC_FVR362 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 362 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF363" description="Valid flag for shadow register 363" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 363 was last reloaded. The value read from BSEC_FVR363 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 363 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF364" description="Valid flag for shadow register 364" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 364 was last reloaded. The value read from BSEC_FVR364 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 364 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF365" description="Valid flag for shadow register 365" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 365 was last reloaded. The value read from BSEC_FVR365 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 365 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF366" description="Valid flag for shadow register 366" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 366 was last reloaded. The value read from BSEC_FVR366 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 366 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF367" description="Valid flag for shadow register 367" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 367 was last reloaded. The value read from BSEC_FVR367 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 367 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF368" description="Valid flag for shadow register 368" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 368 was last reloaded. The value read from BSEC_FVR368 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 368 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF369" description="Valid flag for shadow register 369" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 369 was last reloaded. The value read from BSEC_FVR369 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 369 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF370" description="Valid flag for shadow register 370" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 370 was last reloaded. The value read from BSEC_FVR370 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 370 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF371" description="Valid flag for shadow register 371" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 371 was last reloaded. The value read from BSEC_FVR371 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 371 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF372" description="Valid flag for shadow register 372" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 372 was last reloaded. The value read from BSEC_FVR372 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 372 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF373" description="Valid flag for shadow register 373" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 373 was last reloaded. The value read from BSEC_FVR373 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 373 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF374" description="Valid flag for shadow register 374" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 374 was last reloaded. The value read from BSEC_FVR374 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 374 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF375" description="Valid flag for shadow register 375" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 375 was last reloaded. The value read from BSEC_FVR375 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 375 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF376" description="Valid flag for shadow register 376" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 376 was last reloaded. The value read from BSEC_FVR376 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 376 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF377" description="Valid flag for shadow register 377" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 377 was last reloaded. The value read from BSEC_FVR377 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 377 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF378" description="Valid flag for shadow register 378" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 378 was last reloaded. The value read from BSEC_FVR378 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 378 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF379" description="Valid flag for shadow register 379" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 379 was last reloaded. The value read from BSEC_FVR379 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 379 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF380" description="Valid flag for shadow register 380" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 380 was last reloaded. The value read from BSEC_FVR380 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 380 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF381" description="Valid flag for shadow register 381" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 381 was last reloaded. The value read from BSEC_FVR381 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 381 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF382" description="Valid flag for shadow register 382" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 382 was last reloaded. The value read from BSEC_FVR382 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 382 was done without error." start="0x1" />
+      </BitField>
+      <BitField name="VLDF383" description="Valid flag for shadow register 383" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="An error occurred while fuse word 383 was last reloaded. The value read from BSEC_FVR383 register cannot be relied on." start="0x0" />
+        <Enum name="B_0x1" description="Last reload of fuse word 383 was done without error." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR0" description="BSEC shadowed fuses status register 0" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW0" description="Shadowed fuse word 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 0 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR0 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR0 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW1" description="Shadowed fuse word 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 1 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR1 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR1 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW2" description="Shadowed fuse word 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 2 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR2 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR2 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW3" description="Shadowed fuse word 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 3 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR3 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR3 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW4" description="Shadowed fuse word 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 4 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR4 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR4 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW5" description="Shadowed fuse word 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 5 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR5 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR5 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW6" description="Shadowed fuse word 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 6 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR6 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR6 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW7" description="Shadowed fuse word 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 7 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR7 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR7 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW8" description="Shadowed fuse word 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 8 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR8 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR8 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW9" description="Shadowed fuse word 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 9 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR9 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR9 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW10" description="Shadowed fuse word 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 10 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR10 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR10 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW11" description="Shadowed fuse word 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 11 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR11 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR11 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW12" description="Shadowed fuse word 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 12 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR12 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR12 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW13" description="Shadowed fuse word 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 13 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR13 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR13 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW14" description="Shadowed fuse word 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 14 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR14 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR14 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW15" description="Shadowed fuse word 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 15 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR15 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR15 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW16" description="Shadowed fuse word 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 16 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR16 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR16 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW17" description="Shadowed fuse word 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 17 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR17 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR17 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW18" description="Shadowed fuse word 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 18 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR18 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR18 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW19" description="Shadowed fuse word 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 19 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR19 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR19 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW20" description="Shadowed fuse word 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 20 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR20 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR20 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW21" description="Shadowed fuse word 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 21 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR21 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR21 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW22" description="Shadowed fuse word 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 22 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR22 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR22 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW23" description="Shadowed fuse word 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 23 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR23 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR23 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW24" description="Shadowed fuse word 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 24 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR24 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR24 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW25" description="Shadowed fuse word 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 25 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR25 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR25 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW26" description="Shadowed fuse word 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 26 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR26 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR26 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW27" description="Shadowed fuse word 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 27 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR27 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR27 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW28" description="Shadowed fuse word 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 28 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR28 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR28 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW29" description="Shadowed fuse word 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 29 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR29 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR29 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW30" description="Shadowed fuse word 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 30 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR30 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR30 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW31" description="Shadowed fuse word 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 31 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR31 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR31 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR1" description="BSEC shadowed fuses status register 1" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW32" description="Shadowed fuse word 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 32 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR32 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR32 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW33" description="Shadowed fuse word 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 33 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR33 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR33 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW34" description="Shadowed fuse word 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 34 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR34 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR34 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW35" description="Shadowed fuse word 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 35 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR35 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR35 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW36" description="Shadowed fuse word 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 36 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR36 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR36 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW37" description="Shadowed fuse word 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 37 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR37 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR37 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW38" description="Shadowed fuse word 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 38 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR38 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR38 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW39" description="Shadowed fuse word 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 39 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR39 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR39 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW40" description="Shadowed fuse word 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 40 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR40 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR40 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW41" description="Shadowed fuse word 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 41 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR41 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR41 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW42" description="Shadowed fuse word 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 42 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR42 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR42 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW43" description="Shadowed fuse word 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 43 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR43 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR43 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW44" description="Shadowed fuse word 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 44 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR44 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR44 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW45" description="Shadowed fuse word 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 45 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR45 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR45 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW46" description="Shadowed fuse word 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 46 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR46 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR46 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW47" description="Shadowed fuse word 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 47 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR47 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR47 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW48" description="Shadowed fuse word 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 48 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR48 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR48 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW49" description="Shadowed fuse word 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 49 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR49 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR49 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW50" description="Shadowed fuse word 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 50 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR50 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR50 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW51" description="Shadowed fuse word 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 51 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR51 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR51 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW52" description="Shadowed fuse word 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 52 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR52 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR52 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW53" description="Shadowed fuse word 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 53 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR53 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR53 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW54" description="Shadowed fuse word 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 54 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR54 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR54 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW55" description="Shadowed fuse word 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 55 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR55 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR55 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW56" description="Shadowed fuse word 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 56 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR56 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR56 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW57" description="Shadowed fuse word 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 57 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR57 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR57 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW58" description="Shadowed fuse word 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 58 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR58 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR58 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW59" description="Shadowed fuse word 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 59 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR59 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR59 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW60" description="Shadowed fuse word 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 60 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR60 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR60 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW61" description="Shadowed fuse word 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 61 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR61 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR61 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW62" description="Shadowed fuse word 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 62 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR62 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR62 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW63" description="Shadowed fuse word 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 63 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR63 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR63 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR2" description="BSEC shadowed fuses status register 2" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW64" description="Shadowed fuse word 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 64 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR64 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR64 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW65" description="Shadowed fuse word 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 65 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR65 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR65 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW66" description="Shadowed fuse word 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 66 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR66 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR66 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW67" description="Shadowed fuse word 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 67 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR67 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR67 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW68" description="Shadowed fuse word 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 68 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR68 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR68 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW69" description="Shadowed fuse word 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 69 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR69 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR69 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW70" description="Shadowed fuse word 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 70 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR70 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR70 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW71" description="Shadowed fuse word 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 71 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR71 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR71 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW72" description="Shadowed fuse word 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 72 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR72 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR72 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW73" description="Shadowed fuse word 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 73 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR73 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR73 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW74" description="Shadowed fuse word 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 74 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR74 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR74 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW75" description="Shadowed fuse word 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 75 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR75 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR75 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW76" description="Shadowed fuse word 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 76 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR76 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR76 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW77" description="Shadowed fuse word 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 77 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR77 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR77 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW78" description="Shadowed fuse word 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 78 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR78 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR78 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW79" description="Shadowed fuse word 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 79 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR79 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR79 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW80" description="Shadowed fuse word 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 80 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR80 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR80 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW81" description="Shadowed fuse word 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 81 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR81 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR81 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW82" description="Shadowed fuse word 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 82 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR82 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR82 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW83" description="Shadowed fuse word 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 83 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR83 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR83 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW84" description="Shadowed fuse word 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 84 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR84 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR84 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW85" description="Shadowed fuse word 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 85 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR85 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR85 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW86" description="Shadowed fuse word 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 86 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR86 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR86 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW87" description="Shadowed fuse word 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 87 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR87 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR87 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW88" description="Shadowed fuse word 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 88 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR88 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR88 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW89" description="Shadowed fuse word 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 89 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR89 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR89 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW90" description="Shadowed fuse word 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 90 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR90 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR90 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW91" description="Shadowed fuse word 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 91 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR91 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR91 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW92" description="Shadowed fuse word 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 92 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR92 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR92 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW93" description="Shadowed fuse word 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 93 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR93 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR93 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW94" description="Shadowed fuse word 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 94 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR94 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR94 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW95" description="Shadowed fuse word 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 95 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR95 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR95 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR3" description="BSEC shadowed fuses status register 3" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW96" description="Shadowed fuse word 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 96 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR96 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR96 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW97" description="Shadowed fuse word 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 97 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR97 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR97 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW98" description="Shadowed fuse word 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 98 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR98 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR98 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW99" description="Shadowed fuse word 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 99 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR99 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR99 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW100" description="Shadowed fuse word 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 100 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR100 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR100 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW101" description="Shadowed fuse word 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 101 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR101 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR101 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW102" description="Shadowed fuse word 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 102 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR102 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR102 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW103" description="Shadowed fuse word 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 103 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR103 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR103 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW104" description="Shadowed fuse word 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 104 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR104 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR104 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW105" description="Shadowed fuse word 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 105 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR105 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR105 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW106" description="Shadowed fuse word 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 106 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR106 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR106 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW107" description="Shadowed fuse word 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 107 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR107 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR107 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW108" description="Shadowed fuse word 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 108 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR108 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR108 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW109" description="Shadowed fuse word 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 109 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR109 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR109 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW110" description="Shadowed fuse word 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 110 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR110 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR110 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW111" description="Shadowed fuse word 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 111 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR111 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR111 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW112" description="Shadowed fuse word 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 112 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR112 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR112 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW113" description="Shadowed fuse word 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 113 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR113 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR113 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW114" description="Shadowed fuse word 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 114 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR114 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR114 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW115" description="Shadowed fuse word 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 115 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR115 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR115 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW116" description="Shadowed fuse word 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 116 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR116 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR116 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW117" description="Shadowed fuse word 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 117 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR117 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR117 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW118" description="Shadowed fuse word 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 118 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR118 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR118 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW119" description="Shadowed fuse word 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 119 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR119 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR119 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW120" description="Shadowed fuse word 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 120 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR120 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR120 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW121" description="Shadowed fuse word 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 121 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR121 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR121 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW122" description="Shadowed fuse word 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 122 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR122 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR122 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW123" description="Shadowed fuse word 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 123 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR123 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR123 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW124" description="Shadowed fuse word 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 124 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR124 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR124 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW125" description="Shadowed fuse word 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 125 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR125 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR125 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW126" description="Shadowed fuse word 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 126 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR126 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR126 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW127" description="Shadowed fuse word 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 127 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR127 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR127 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR4" description="BSEC shadowed fuses status register 4" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW128" description="Shadowed fuse word 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 128 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR128 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR128 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW129" description="Shadowed fuse word 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 129 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR129 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR129 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW130" description="Shadowed fuse word 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 130 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR130 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR130 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW131" description="Shadowed fuse word 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 131 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR131 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR131 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW132" description="Shadowed fuse word 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 132 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR132 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR132 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW133" description="Shadowed fuse word 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 133 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR133 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR133 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW134" description="Shadowed fuse word 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 134 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR134 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR134 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW135" description="Shadowed fuse word 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 135 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR135 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR135 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW136" description="Shadowed fuse word 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 136 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR136 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR136 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW137" description="Shadowed fuse word 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 137 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR137 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR137 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW138" description="Shadowed fuse word 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 138 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR138 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR138 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW139" description="Shadowed fuse word 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 139 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR139 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR139 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW140" description="Shadowed fuse word 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 140 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR140 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR140 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW141" description="Shadowed fuse word 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 141 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR141 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR141 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW142" description="Shadowed fuse word 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 142 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR142 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR142 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW143" description="Shadowed fuse word 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 143 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR143 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR143 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW144" description="Shadowed fuse word 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 144 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR144 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR144 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW145" description="Shadowed fuse word 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 145 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR145 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR145 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW146" description="Shadowed fuse word 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 146 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR146 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR146 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW147" description="Shadowed fuse word 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 147 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR147 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR147 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW148" description="Shadowed fuse word 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 148 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR148 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR148 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW149" description="Shadowed fuse word 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 149 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR149 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR149 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW150" description="Shadowed fuse word 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 150 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR150 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR150 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW151" description="Shadowed fuse word 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 151 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR151 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR151 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW152" description="Shadowed fuse word 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 152 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR152 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR152 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW153" description="Shadowed fuse word 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 153 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR153 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR153 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW154" description="Shadowed fuse word 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 154 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR154 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR154 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW155" description="Shadowed fuse word 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 155 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR155 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR155 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW156" description="Shadowed fuse word 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 156 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR156 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR156 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW157" description="Shadowed fuse word 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 157 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR157 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR157 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW158" description="Shadowed fuse word 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 158 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR158 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR158 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW159" description="Shadowed fuse word 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 159 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR159 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR159 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR5" description="BSEC shadowed fuses status register 5" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW160" description="Shadowed fuse word 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 160 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR160 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR160 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW161" description="Shadowed fuse word 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 161 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR161 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR161 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW162" description="Shadowed fuse word 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 162 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR162 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR162 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW163" description="Shadowed fuse word 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 163 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR163 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR163 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW164" description="Shadowed fuse word 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 164 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR164 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR164 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW165" description="Shadowed fuse word 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 165 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR165 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR165 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW166" description="Shadowed fuse word 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 166 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR166 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR166 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW167" description="Shadowed fuse word 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 167 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR167 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR167 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW168" description="Shadowed fuse word 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 168 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR168 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR168 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW169" description="Shadowed fuse word 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 169 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR169 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR169 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW170" description="Shadowed fuse word 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 170 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR170 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR170 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW171" description="Shadowed fuse word 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 171 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR171 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR171 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW172" description="Shadowed fuse word 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 172 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR172 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR172 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW173" description="Shadowed fuse word 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 173 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR173 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR173 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW174" description="Shadowed fuse word 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 174 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR174 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR174 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW175" description="Shadowed fuse word 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 175 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR175 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR175 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW176" description="Shadowed fuse word 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 176 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR176 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR176 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW177" description="Shadowed fuse word 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 177 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR177 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR177 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW178" description="Shadowed fuse word 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 178 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR178 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR178 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW179" description="Shadowed fuse word 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 179 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR179 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR179 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW180" description="Shadowed fuse word 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 180 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR180 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR180 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW181" description="Shadowed fuse word 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 181 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR181 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR181 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW182" description="Shadowed fuse word 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 182 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR182 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR182 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW183" description="Shadowed fuse word 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 183 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR183 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR183 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW184" description="Shadowed fuse word 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 184 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR184 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR184 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW185" description="Shadowed fuse word 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 185 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR185 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR185 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW186" description="Shadowed fuse word 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 186 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR186 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR186 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW187" description="Shadowed fuse word 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 187 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR187 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR187 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW188" description="Shadowed fuse word 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 188 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR188 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR188 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW189" description="Shadowed fuse word 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 189 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR189 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR189 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW190" description="Shadowed fuse word 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 190 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR190 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR190 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW191" description="Shadowed fuse word 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 191 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR191 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR191 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR6" description="BSEC shadowed fuses status register 6" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW192" description="Shadowed fuse word 192" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 192 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR192 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR192 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW193" description="Shadowed fuse word 193" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 193 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR193 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR193 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW194" description="Shadowed fuse word 194" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 194 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR194 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR194 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW195" description="Shadowed fuse word 195" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 195 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR195 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR195 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW196" description="Shadowed fuse word 196" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 196 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR196 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR196 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW197" description="Shadowed fuse word 197" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 197 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR197 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR197 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW198" description="Shadowed fuse word 198" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 198 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR198 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR198 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW199" description="Shadowed fuse word 199" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 199 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR199 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR199 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW200" description="Shadowed fuse word 200" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 200 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR200 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR200 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW201" description="Shadowed fuse word 201" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 201 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR201 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR201 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW202" description="Shadowed fuse word 202" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 202 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR202 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR202 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW203" description="Shadowed fuse word 203" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 203 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR203 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR203 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW204" description="Shadowed fuse word 204" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 204 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR204 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR204 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW205" description="Shadowed fuse word 205" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 205 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR205 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR205 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW206" description="Shadowed fuse word 206" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 206 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR206 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR206 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW207" description="Shadowed fuse word 207" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 207 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR207 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR207 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW208" description="Shadowed fuse word 208" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 208 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR208 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR208 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW209" description="Shadowed fuse word 209" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 209 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR209 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR209 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW210" description="Shadowed fuse word 210" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 210 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR210 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR210 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW211" description="Shadowed fuse word 211" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 211 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR211 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR211 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW212" description="Shadowed fuse word 212" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 212 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR212 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR212 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW213" description="Shadowed fuse word 213" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 213 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR213 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR213 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW214" description="Shadowed fuse word 214" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 214 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR214 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR214 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW215" description="Shadowed fuse word 215" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 215 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR215 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR215 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW216" description="Shadowed fuse word 216" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 216 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR216 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR216 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW217" description="Shadowed fuse word 217" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 217 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR217 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR217 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW218" description="Shadowed fuse word 218" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 218 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR218 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR218 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW219" description="Shadowed fuse word 219" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 219 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR219 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR219 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW220" description="Shadowed fuse word 220" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 220 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR220 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR220 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW221" description="Shadowed fuse word 221" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 221 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR221 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR221 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW222" description="Shadowed fuse word 222" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 222 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR222 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR222 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW223" description="Shadowed fuse word 223" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 223 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR223 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR223 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR7" description="BSEC shadowed fuses status register 7" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW224" description="Shadowed fuse word 224" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 224 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR224 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR224 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW225" description="Shadowed fuse word 225" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 225 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR225 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR225 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW226" description="Shadowed fuse word 226" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 226 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR226 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR226 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW227" description="Shadowed fuse word 227" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 227 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR227 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR227 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW228" description="Shadowed fuse word 228" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 228 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR228 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR228 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW229" description="Shadowed fuse word 229" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 229 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR229 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR229 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW230" description="Shadowed fuse word 230" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 230 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR230 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR230 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW231" description="Shadowed fuse word 231" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 231 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR231 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR231 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW232" description="Shadowed fuse word 232" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 232 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR232 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR232 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW233" description="Shadowed fuse word 233" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 233 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR233 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR233 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW234" description="Shadowed fuse word 234" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 234 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR234 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR234 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW235" description="Shadowed fuse word 235" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 235 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR235 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR235 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW236" description="Shadowed fuse word 236" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 236 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR236 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR236 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW237" description="Shadowed fuse word 237" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 237 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR237 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR237 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW238" description="Shadowed fuse word 238" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 238 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR238 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR238 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW239" description="Shadowed fuse word 239" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 239 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR239 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR239 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW240" description="Shadowed fuse word 240" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 240 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR240 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR240 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW241" description="Shadowed fuse word 241" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 241 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR241 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR241 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW242" description="Shadowed fuse word 242" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 242 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR242 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR242 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW243" description="Shadowed fuse word 243" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 243 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR243 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR243 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW244" description="Shadowed fuse word 244" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 244 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR244 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR244 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW245" description="Shadowed fuse word 245" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 245 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR245 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR245 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW246" description="Shadowed fuse word 246" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 246 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR246 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR246 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW247" description="Shadowed fuse word 247" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 247 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR247 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR247 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW248" description="Shadowed fuse word 248" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 248 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR248 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR248 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW249" description="Shadowed fuse word 249" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 249 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR249 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR249 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW250" description="Shadowed fuse word 250" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 250 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR250 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR250 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW251" description="Shadowed fuse word 251" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 251 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR251 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR251 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW252" description="Shadowed fuse word 252" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 252 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR252 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR252 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW253" description="Shadowed fuse word 253" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 253 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR253 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR253 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW254" description="Shadowed fuse word 254" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 254 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR254 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR254 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW255" description="Shadowed fuse word 255" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 255 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR255 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR255 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR8" description="BSEC shadowed fuses status register 8" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW256" description="Shadowed fuse word 256" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 256 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR256 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR256 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW257" description="Shadowed fuse word 257" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 257 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR257 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR257 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW258" description="Shadowed fuse word 258" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 258 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR258 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR258 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW259" description="Shadowed fuse word 259" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 259 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR259 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR259 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW260" description="Shadowed fuse word 260" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 260 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR260 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR260 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW261" description="Shadowed fuse word 261" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 261 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR261 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR261 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW262" description="Shadowed fuse word 262" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 262 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR262 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR262 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW263" description="Shadowed fuse word 263" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 263 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR263 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR263 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW264" description="Shadowed fuse word 264" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 264 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR264 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR264 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW265" description="Shadowed fuse word 265" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 265 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR265 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR265 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW266" description="Shadowed fuse word 266" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 266 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR266 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR266 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW267" description="Shadowed fuse word 267" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 267 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR267 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR267 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW268" description="Shadowed fuse word 268" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 268 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR268 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR268 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW269" description="Shadowed fuse word 269" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 269 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR269 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR269 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW270" description="Shadowed fuse word 270" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 270 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR270 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR270 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW271" description="Shadowed fuse word 271" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 271 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR271 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR271 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW272" description="Shadowed fuse word 272" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 272 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR272 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR272 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW273" description="Shadowed fuse word 273" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 273 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR273 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR273 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW274" description="Shadowed fuse word 274" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 274 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR274 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR274 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW275" description="Shadowed fuse word 275" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 275 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR275 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR275 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW276" description="Shadowed fuse word 276" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 276 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR276 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR276 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW277" description="Shadowed fuse word 277" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 277 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR277 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR277 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW278" description="Shadowed fuse word 278" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 278 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR278 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR278 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW279" description="Shadowed fuse word 279" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 279 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR279 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR279 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW280" description="Shadowed fuse word 280" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 280 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR280 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR280 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW281" description="Shadowed fuse word 281" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 281 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR281 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR281 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW282" description="Shadowed fuse word 282" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 282 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR282 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR282 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW283" description="Shadowed fuse word 283" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 283 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR283 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR283 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW284" description="Shadowed fuse word 284" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 284 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR284 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR284 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW285" description="Shadowed fuse word 285" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 285 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR285 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR285 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW286" description="Shadowed fuse word 286" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 286 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR286 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR286 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW287" description="Shadowed fuse word 287" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 287 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR287 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR287 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR9" description="BSEC shadowed fuses status register 9" start="+0x964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW288" description="Shadowed fuse word 288" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 288 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR288 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR288 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW289" description="Shadowed fuse word 289" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 289 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR289 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR289 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW290" description="Shadowed fuse word 290" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 290 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR290 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR290 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW291" description="Shadowed fuse word 291" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 291 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR291 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR291 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW292" description="Shadowed fuse word 292" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 292 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR292 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR292 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW293" description="Shadowed fuse word 293" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 293 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR293 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR293 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW294" description="Shadowed fuse word 294" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 294 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR294 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR294 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW295" description="Shadowed fuse word 295" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 295 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR295 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR295 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW296" description="Shadowed fuse word 296" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 296 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR296 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR296 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW297" description="Shadowed fuse word 297" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 297 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR297 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR297 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW298" description="Shadowed fuse word 298" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 298 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR298 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR298 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW299" description="Shadowed fuse word 299" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 299 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR299 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR299 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW300" description="Shadowed fuse word 300" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 300 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR300 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR300 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW301" description="Shadowed fuse word 301" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 301 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR301 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR301 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW302" description="Shadowed fuse word 302" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 302 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR302 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR302 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW303" description="Shadowed fuse word 303" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 303 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR303 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR303 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW304" description="Shadowed fuse word 304" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 304 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR304 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR304 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW305" description="Shadowed fuse word 305" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 305 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR305 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR305 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW306" description="Shadowed fuse word 306" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 306 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR306 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR306 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW307" description="Shadowed fuse word 307" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 307 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR307 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR307 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW308" description="Shadowed fuse word 308" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 308 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR308 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR308 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW309" description="Shadowed fuse word 309" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 309 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR309 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR309 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW310" description="Shadowed fuse word 310" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 310 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR310 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR310 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW311" description="Shadowed fuse word 311" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 311 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR311 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR311 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW312" description="Shadowed fuse word 312" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 312 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR312 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR312 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW313" description="Shadowed fuse word 313" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 313 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR313 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR313 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW314" description="Shadowed fuse word 314" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 314 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR314 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR314 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW315" description="Shadowed fuse word 315" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 315 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR315 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR315 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW316" description="Shadowed fuse word 316" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 316 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR316 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR316 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW317" description="Shadowed fuse word 317" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 317 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR317 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR317 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW318" description="Shadowed fuse word 318" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 318 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR318 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR318 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW319" description="Shadowed fuse word 319" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 319 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR319 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR319 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR10" description="BSEC shadowed fuses status register 10" start="+0x968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW320" description="Shadowed fuse word 320" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 320 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR320 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR320 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW321" description="Shadowed fuse word 321" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 321 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR321 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR321 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW322" description="Shadowed fuse word 322" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 322 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR322 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR322 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW323" description="Shadowed fuse word 323" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 323 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR323 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR323 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW324" description="Shadowed fuse word 324" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 324 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR324 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR324 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW325" description="Shadowed fuse word 325" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 325 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR325 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR325 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW326" description="Shadowed fuse word 326" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 326 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR326 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR326 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW327" description="Shadowed fuse word 327" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 327 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR327 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR327 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW328" description="Shadowed fuse word 328" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 328 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR328 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR328 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW329" description="Shadowed fuse word 329" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 329 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR329 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR329 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW330" description="Shadowed fuse word 330" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 330 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR330 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR330 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW331" description="Shadowed fuse word 331" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 331 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR331 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR331 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW332" description="Shadowed fuse word 332" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 332 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR332 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR332 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW333" description="Shadowed fuse word 333" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 333 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR333 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR333 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW334" description="Shadowed fuse word 334" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 334 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR334 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR334 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW335" description="Shadowed fuse word 335" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 335 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR335 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR335 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW336" description="Shadowed fuse word 336" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 336 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR336 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR336 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW337" description="Shadowed fuse word 337" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 337 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR337 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR337 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW338" description="Shadowed fuse word 338" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 338 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR338 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR338 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW339" description="Shadowed fuse word 339" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 339 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR339 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR339 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW340" description="Shadowed fuse word 340" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 340 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR340 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR340 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW341" description="Shadowed fuse word 341" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 341 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR341 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR341 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW342" description="Shadowed fuse word 342" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 342 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR342 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR342 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW343" description="Shadowed fuse word 343" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 343 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR343 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR343 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW344" description="Shadowed fuse word 344" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 344 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR344 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR344 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW345" description="Shadowed fuse word 345" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 345 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR345 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR345 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW346" description="Shadowed fuse word 346" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 346 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR346 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR346 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW347" description="Shadowed fuse word 347" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 347 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR347 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR347 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW348" description="Shadowed fuse word 348" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 348 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR348 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR348 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW349" description="Shadowed fuse word 349" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 349 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR349 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR349 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW350" description="Shadowed fuse word 350" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 350 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR350 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR350 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW351" description="Shadowed fuse word 351" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 351 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR351 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR351 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_SFSR11" description="BSEC shadowed fuses status register 11" start="+0x96C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFW352" description="Shadowed fuse word 352" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 352 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR352 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR352 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW353" description="Shadowed fuse word 353" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 353 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR353 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR353 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW354" description="Shadowed fuse word 354" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 354 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR354 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR354 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW355" description="Shadowed fuse word 355" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 355 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR355 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR355 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW356" description="Shadowed fuse word 356" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 356 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR356 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR356 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW357" description="Shadowed fuse word 357" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 357 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR357 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR357 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW358" description="Shadowed fuse word 358" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 358 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR358 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR358 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW359" description="Shadowed fuse word 359" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 359 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR359 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR359 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW360" description="Shadowed fuse word 360" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 360 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR360 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR360 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW361" description="Shadowed fuse word 361" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 361 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR361 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR361 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW362" description="Shadowed fuse word 362" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 362 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR362 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR362 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW363" description="Shadowed fuse word 363" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 363 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR363 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR363 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW364" description="Shadowed fuse word 364" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 364 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR364 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR364 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW365" description="Shadowed fuse word 365" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 365 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR365 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR365 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW366" description="Shadowed fuse word 366" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 366 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR366 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR366 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW367" description="Shadowed fuse word 367" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 367 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR367 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR367 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW368" description="Shadowed fuse word 368" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 368 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR368 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR368 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW369" description="Shadowed fuse word 369" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 369 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR369 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR369 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW370" description="Shadowed fuse word 370" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 370 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR370 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR370 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW371" description="Shadowed fuse word 371" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 371 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR371 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR371 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW372" description="Shadowed fuse word 372" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 372 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR372 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR372 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW373" description="Shadowed fuse word 373" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 373 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR373 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR373 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW374" description="Shadowed fuse word 374" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 374 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR374 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR374 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW375" description="Shadowed fuse word 375" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 375 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR375 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR375 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW376" description="Shadowed fuse word 376" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 376 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR376 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR376 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW377" description="Shadowed fuse word 377" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 377 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR377 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR377 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW378" description="Shadowed fuse word 378" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 378 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR378 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR378 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW379" description="Shadowed fuse word 379" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 379 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR379 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR379 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW380" description="Shadowed fuse word 380" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 380 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR380 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR380 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW381" description="Shadowed fuse word 381" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 381 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR381 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR381 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW382" description="Shadowed fuse word 382" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 382 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR382 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR382 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+      <BitField name="SFW383" description="Shadowed fuse word 383" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Fuse word 383 is not shadowed. Fuse value must be reloaded using BSEC_OTPCR before reading BSEC_FVR383 register." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word is shadowed in BSEC_FVR383 register. Reloading the fuse value using BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or warm reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPCR" description="BSEC OTP control register" start="+0xC04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDR" description="Fuse word address" start="0" size="9" access="Read/Write" />
+      <BitField name="PROG" description="Fuse word programming" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word read operation is required" start="0x0" />
+        <Enum name="B_0x1" description="Fuse word programming operation is required" start="0x1" />
+      </BitField>
+      <BitField name="PPLOCK" description="Permanent programming lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fuse word at address ADDR[8:0] is programmed normally." start="0x0" />
+        <Enum name="B_0x1" description="Fuse word at address ADDR[8:0] is locked, preventing further modifications." start="0x1" />
+      </BitField>
+      <BitField name="LASTCID" description="Last CID" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_WDR" description="BSEC write data register" start="+0xC08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRDATA" description="OTP write data" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_SCRATCHR0" description="BSEC scratch register 0" start="+0xE00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR1" description="BSEC scratch register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR2" description="BSEC scratch register 2" start="+0xE08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SCRATCHR3" description="BSEC scratch register 3" start="+0xE0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDATA" description="Scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_LOCKR" description="BSEC lock register" start="+0xE10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GWLOCK" description="Global write lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to BSEC registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to BSEC registers are ignored (fuse programming and fuse reload disabled)" start="0x1" />
+      </BitField>
+      <BitField name="HKLOCK" description="Hardware key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Derived hardware unique key (DHUK) in SAES peripheral is usable if HVALID is set in BSEC_SR" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK) in SAES peripheral is not usable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_JTAGINR" description="BSEC JTAG input register" start="+0xE14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATAIN" description="JTAG input data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_JTAGOUTR" description="BSEC JTAG output register" start="+0xE18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATAOUT" description="JTAG output data" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_UNMAPR" description="BSEC unmap register" start="+0xE24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNMAP" description="Unmap key" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_SR" description="BSEC status register" start="+0xE40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HVALID" description="Hardware key valid" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Derived hardware unique key (DHUK) feature cannot be used in SAES peripheral" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK) feature can be used in SAES peripheral" start="0x1" />
+      </BitField>
+      <BitField name="DBGREQ" description="debug request" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Host debugger is not requesting debug" start="0x0" />
+        <Enum name="B_0x1" description="Host debugger is requesting debug" start="0x1" />
+      </BitField>
+      <BitField name="NVSTATE" description="Non-volatile state" start="26" size="6" access="ReadOnly">
+        <Enum name="B_0x16" description="BSEC is in open state" start="0x16" />
+        <Enum name="B_0x0D" description="BSEC is in closed state" start="0x0D" />
+        <Enum name="B_0x7" description="BSEC is in invalid state." start="0x7" />
+        <Enum name="B_0x23" description="BSEC is in invalid state, with an active confirmed tamper triggered in the device." start="0x23" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_OTPSR" description="BSEC OTP status register" start="+0xE44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSY" description="Busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSEC is idle" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is busy" start="0x1" />
+      </BitField>
+      <BitField name="INIT_DONE" description="Initialization done" start="1" size="1" access="ReadOnly" />
+      <BitField name="HIDEUP" description="Hide upper fuse words" start="2" size="1" access="ReadOnly" />
+      <BitField name="OTPNVIR" description="OTP not virgin" start="4" size="1" access="ReadOnly" />
+      <BitField name="OTPERR" description="OTP with error" start="5" size="1" access="ReadOnly" />
+      <BitField name="OTPSEC" description="OTP with single error correction" start="6" size="1" access="ReadOnly" />
+      <BitField name="PROGFAIL" description="Programming failed" start="16" size="1" access="ReadOnly" />
+      <BitField name="DISTURBF" description="Disturb flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="DEDF" description="Double error detection flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="SECF" description="Single error correction flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="PPLF" description="Permanent programming lock flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="PPLMF" description="Permanent programming lock mismatch flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="AMEF" description="Addresses mismatch error flag " start="22" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_EPOCHR0" description="BSEC epoch register" start="+0xE80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPOCH" description="epoch" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_EPOCHR1" description="BSEC epoch register" start="+0xE84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPOCH" description="epoch" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_EPOCH_SELR" description="BSEC epoch select register" start="+0xE88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPSEL" description="Epoch selection. This value is wired out to the SAES peripheral." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES peripheral uses BSEC_EPOCHR0 as EPOCH value." start="0x0" />
+        <Enum name="B_0x1" description="SAES peripheral uses BSEC_EPOCHR1 as EPOCH value." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_DBGCR" description="BSEC Debug" start="+0xE8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNLOCK" description="any other value: debug not authorized (provided BSEC state is not OPEN)" start="8" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="non-secure debug authorized when the level indicated in BSEC_HDPLSR is greater than or equal to the level given by AUTH_HDPL" start="0xB4" />
+      </BitField>
+      <BitField name="AUTH_HDPL" description="level at which debug may be opened." start="16" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="Level 0" start="0xB4" />
+        <Enum name="B_0x51" description="Level 1" start="0x51" />
+        <Enum name="B_0x8A" description="Level 2" start="0x8A" />
+        <Enum name="B_0x6F" description="Level 3" start="0x6F" />
+      </BitField>
+      <BitField name="AUTH_SEC" description="any other value: secure debug not authorized (provided BSEC state is not OPEN)" start="24" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="secure debug authorized when UNLOCK = 0xB4 and the level indicated in BSEC_HDPLSR is greater than or equal to the level indicated by AUTH_HDPL" start="0xB4" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_AP_UNLOCK" description="BSEC AP Unlock" start="+0xE90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UNLOCK" description="any other value: do not unlock" start="0" size="8" access="Read/Write">
+        <Enum name="B_0xB4" description="unlock the DBG_MCU AP interface." start="0xB4" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_HDPLSR" description="BSEC HDPL" start="+0xE94" size="4" reset_value="0x000000B4" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPL" description="current HDPL" start="0" size="8" access="ReadOnly">
+        <Enum name="B_0xB4" description="Level 0" start="0xB4" />
+        <Enum name="B_0x51" description="Level 1" start="0x51" />
+        <Enum name="B_0x8A" description="Level 2" start="0x8A" />
+        <Enum name="B_0x6F" description="Level 3" start="0x6F" />
+      </BitField>
+    </Register>
+    <Register name="BSEC_HDPLCR" description="BSEC HDPL control" start="+0xE98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INCR_HDPL" description="Increment HDPL" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="BSEC_NEXTLR" description="BSEC Next HDPL" start="+0xE9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INCR" description="Increment" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR0" description="BSEC write once scratch register 0" start="+0xF40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR1" description="BSEC write once scratch register 1" start="+0xF44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR2" description="BSEC write once scratch register 2" start="+0xF48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR3" description="BSEC write once scratch register 3" start="+0xF4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR4" description="BSEC write once scratch register 4" start="+0xF50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR5" description="BSEC write once scratch register 5" start="+0xF54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR6" description="BSEC write once scratch register 6" start="+0xF58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_WOSCR7" description="BSEC write once scratch register 7" start="+0xF5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WOSDATA" description="Write once scratch data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="BSEC_HRCR" description="BSEC hot reset count register" start="+0xFE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRC" description="hot reset counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="BSEC_WRCR" description="BSEC warm reset count register" start="+0xFEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRC" description="Warm reset counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CACHEAXI" description="AXI cache" start="0x480DFC00">
+    <Register name="CACHEAXI_CR1" description="CACHEAXI control register 1" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache mode disabled (CACHEAXI bypassed, or in SRAM mode if option supported)" start="0x0" />
+        <Enum name="B_0x1" description="cache mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="CACHEINV" description="full cache invalidation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="invalidate entire cache (all cache lines valid bit = 0)" start="0x1" />
+      </BitField>
+      <BitField name="RHITMEN" description="read-hit monitor enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RMISSMEN" description="read-miss monitor enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RHITMRST" description="read-hit monitor reset" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="RMISSMRST" description="read-miss monitor reset" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WHITMEN" description="write-hit monitor enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WMISSMEN" description="write-miss monitor enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WHITMRST" description="write-hit monitor reset" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="WMISSMRST" description="write-miss monitor reset" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="RAMMEN" description="read-allocate miss monitor enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-allocate miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-allocate miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAMMEN" description="write-allocate miss monitor enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-allocate miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-allocate miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RAMMRST" description="read-allocate miss monitor reset" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-allocate miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WAMMRST" description="write-allocate miss monitor reset" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-allocate miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WTMEN" description="write-through monitor enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-through monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-through monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVIMEN" description="eviction monitor enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache eviction monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache eviction monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTMRST" description="write-through monitor reset" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-through monitor" start="0x1" />
+      </BitField>
+      <BitField name="EVIMRST" description="eviction monitor reset" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache eviction monitor" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_SR" description="CACHEAXI status register" start="+0x004" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSYF" description="full invalidate busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHEINV operation" start="0x0" />
+        <Enum name="B_0x1" description="cache executing a full invalidate CACHEINV operation" start="0x1" />
+      </BitField>
+      <BitField name="BSYENDF" description="full invalidate busy end flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy or in idle" start="0x0" />
+        <Enum name="B_0x1" description="full invalidate CACHEINV operation finished" start="0x1" />
+      </BitField>
+      <BitField name="ERRF" description="cache error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no error" start="0x0" />
+        <Enum name="B_0x1" description="an error occurred during the operation (eviction or clean operation write-back error)." start="0x1" />
+      </BitField>
+      <BitField name="BUSYCMDF" description="command busy flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHECMD command" start="0x0" />
+        <Enum name="B_0x1" description="cache busy on a CACHECMD command (clean or clean-and-invalidate an address range)" start="0x1" />
+      </BitField>
+      <BitField name="CMDENDF" description="command end flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy or in idle" start="0x0" />
+        <Enum name="B_0x1" description="CACHECMD command finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_IER" description="CACHEAXI interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSYENDIE" description="interrupt enable on busy end" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled on busy end" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled on busy end" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="interrupt enable on cache error" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on error" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on error" start="0x1" />
+      </BitField>
+      <BitField name="CMDENDIE" description="interrupt enable on command end " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on command end" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on command end" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_FCR" description="CACHEAXI flag clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CBSYENDF" description="clear full invalidate busy end flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears BSYENDF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="clear cache error flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears ERRF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+      <BitField name="CCMDENDF" description="clear command end flag" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears CMDENDF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_RHMONR" description="CACHEAXI read-hit monitor register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RHITMON" description="cache read-hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_RMMONR" description="CACHEAXI read-miss monitor register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMISSMON" description="cache read-miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_RAMMONR" description="CACHEAXI read-allocate miss monitor register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMMON" description="cache read-allocate miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_EVIMONR" description="CACHEAXI eviction monitor register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EVIMON" description="cache eviction monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WHMONR" description="CACHEAXI write-hit monitor register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHITMON" description="cache write-hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WMMONR" description="CACHEAXI write-miss monitor register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WMISSMON" description="cache write-miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WAMMONR" description="CACHEAXI write-allocate miss monitor register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WAMMON" description="cache write-allocate miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WTMONR" description="CACHEAXI write-through monitor register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WTMON" description="cache write-through monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_CR2" description="CACHEAXI control register 2" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STARTCMD" description="starts maintenance range command (maintenance operation defined in CACHECMD)." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="command operation (cache maintenance) finished" start="0x0" />
+        <Enum name="B_0x1" description="start maintenance command (cache maintenance)" start="0x1" />
+      </BitField>
+      <BitField name="CACHECMD" description="cache command maintenance operation (clean or clean-and-invalidate an address range)" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no operation" start="0x0" />
+        <Enum name="B_0x1" description="clean range" start="0x1" />
+        <Enum name="B_0x3" description="clean and invalidate range" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_CMDRSADDRR" description="CACHEAXI command range start address register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDSTARTADDR" description="start address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" start="6" size="26" access="Read/Write" />
+    </Register>
+    <Register name="CACHEAXI_CMDREADDRR" description="CACHEAXI command range end address register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDENDADDR" description="end address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" start="6" size="26" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CACHEAXI_S" description="AXI cache" start="0x580DFC00">
+    <Register name="CACHEAXI_CR1" description="CACHEAXI control register 1" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache mode disabled (CACHEAXI bypassed, or in SRAM mode if option supported)" start="0x0" />
+        <Enum name="B_0x1" description="cache mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="CACHEINV" description="full cache invalidation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="invalidate entire cache (all cache lines valid bit = 0)" start="0x1" />
+      </BitField>
+      <BitField name="RHITMEN" description="read-hit monitor enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RMISSMEN" description="read-miss monitor enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RHITMRST" description="read-hit monitor reset" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="RMISSMRST" description="read-miss monitor reset" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WHITMEN" description="write-hit monitor enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WMISSMEN" description="write-miss monitor enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WHITMRST" description="write-hit monitor reset" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="WMISSMRST" description="write-miss monitor reset" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="RAMMEN" description="read-allocate miss monitor enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache read-allocate miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache read-allocate miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAMMEN" description="write-allocate miss monitor enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-allocate miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-allocate miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="RAMMRST" description="read-allocate miss monitor reset" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache read-allocate miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WAMMRST" description="write-allocate miss monitor reset" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-allocate miss monitor" start="0x1" />
+      </BitField>
+      <BitField name="WTMEN" description="write-through monitor enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache write-through monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache write-through monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVIMEN" description="eviction monitor enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache eviction monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache eviction monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTMRST" description="write-through monitor reset" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache write-through monitor" start="0x1" />
+      </BitField>
+      <BitField name="EVIMRST" description="eviction monitor reset" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache eviction monitor" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_SR" description="CACHEAXI status register" start="+0x004" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSYF" description="full invalidate busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHEINV operation" start="0x0" />
+        <Enum name="B_0x1" description="cache executing a full invalidate CACHEINV operation" start="0x1" />
+      </BitField>
+      <BitField name="BSYENDF" description="full invalidate busy end flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy or in idle" start="0x0" />
+        <Enum name="B_0x1" description="full invalidate CACHEINV operation finished" start="0x1" />
+      </BitField>
+      <BitField name="ERRF" description="cache error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no error" start="0x0" />
+        <Enum name="B_0x1" description="an error occurred during the operation (eviction or clean operation write-back error)." start="0x1" />
+      </BitField>
+      <BitField name="BUSYCMDF" description="command busy flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHECMD command" start="0x0" />
+        <Enum name="B_0x1" description="cache busy on a CACHECMD command (clean or clean-and-invalidate an address range)" start="0x1" />
+      </BitField>
+      <BitField name="CMDENDF" description="command end flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy or in idle" start="0x0" />
+        <Enum name="B_0x1" description="CACHECMD command finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_IER" description="CACHEAXI interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSYENDIE" description="interrupt enable on busy end" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled on busy end" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled on busy end" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="interrupt enable on cache error" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on error" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on error" start="0x1" />
+      </BitField>
+      <BitField name="CMDENDIE" description="interrupt enable on command end " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on command end" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on command end" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_FCR" description="CACHEAXI flag clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CBSYENDF" description="clear full invalidate busy end flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears BSYENDF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="clear cache error flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears ERRF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+      <BitField name="CCMDENDF" description="clear command end flag" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears CMDENDF flag in CACHEAXI_SR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_RHMONR" description="CACHEAXI read-hit monitor register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RHITMON" description="cache read-hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_RMMONR" description="CACHEAXI read-miss monitor register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMISSMON" description="cache read-miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_RAMMONR" description="CACHEAXI read-allocate miss monitor register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMMON" description="cache read-allocate miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_EVIMONR" description="CACHEAXI eviction monitor register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EVIMON" description="cache eviction monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WHMONR" description="CACHEAXI write-hit monitor register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHITMON" description="cache write-hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WMMONR" description="CACHEAXI write-miss monitor register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WMISSMON" description="cache write-miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WAMMONR" description="CACHEAXI write-allocate miss monitor register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WAMMON" description="cache write-allocate miss monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_WTMONR" description="CACHEAXI write-through monitor register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WTMON" description="cache write-through monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CACHEAXI_CR2" description="CACHEAXI control register 2" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STARTCMD" description="starts maintenance range command (maintenance operation defined in CACHECMD)." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="command operation (cache maintenance) finished" start="0x0" />
+        <Enum name="B_0x1" description="start maintenance command (cache maintenance)" start="0x1" />
+      </BitField>
+      <BitField name="CACHECMD" description="cache command maintenance operation (clean or clean-and-invalidate an address range)" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no operation" start="0x0" />
+        <Enum name="B_0x1" description="clean range" start="0x1" />
+        <Enum name="B_0x3" description="clean and invalidate range" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="CACHEAXI_CMDRSADDRR" description="CACHEAXI command range start address register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDSTARTADDR" description="start address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" start="6" size="26" access="Read/Write" />
+    </Register>
+    <Register name="CACHEAXI_CMDREADDRR" description="CACHEAXI command range end address register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDENDADDR" description="end address of range to which the cache maintenance command specified in CACHEAXI_CR2.CACHECMD field applies" start="6" size="26" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRC" description="Cyclic redundancy check calculation unit" start="0x46024C00">
+    <Register name="CRC_DR" description="CRC data register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data register bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_IDR" description="CRC independent data register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDR" description="General-purpose 32-bit data register bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_CR" description="CRC control register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESET" description="RESET bit" start="0" size="1" access="Read/Write" />
+      <BitField name="POLYSIZE" description="Polynomial size" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="32 bit polynomial" start="0x0" />
+        <Enum name="B_0x1" description="16 bit polynomial" start="0x1" />
+        <Enum name="B_0x2" description="8 bit polynomial" start="0x2" />
+        <Enum name="B_0x3" description="7 bit polynomial" start="0x3" />
+      </BitField>
+      <BitField name="REV_IN" description="Reverse input data" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Bit order not affected (RTYPE_IN = 0 or 1)" start="0x0" />
+        <Enum name="B_0x1" description="Bit reversal done by byte (RTYPE_IN = 0) or half-word reversal done by word (RTYPE_IN = 1)" start="0x1" />
+        <Enum name="B_0x2" description="Bit reversal done by half-word (RTYPE_IN = 0) or byte reversal done by word (RTYPE_IN = 1)" start="0x2" />
+        <Enum name="B_0x3" description="Bit reversal done by word (RTYPE_IN = 0) or bit order is not affected (RTYPE_IN = 1)" start="0x3" />
+      </BitField>
+      <BitField name="REV_OUT" description="Reverse output data" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Bit order not affected (RTYPE_OUT = 0 or 1)" start="0x0" />
+        <Enum name="B_0x1" description="Bit-reversed output format (RTYPE_OUT = 0) or half-word reversal done by word (RTYPE_OUT = 1)" start="0x1" />
+        <Enum name="B_0x2" description="Bit order not affected (RTYPE_OUT = 0) or byte reversal done by word (RTYPE_OUT = 1)" start="0x2" />
+        <Enum name="B_0x3" description="Bit order not affected (RTYPE_OUT = 0 or 1)" start="0x3" />
+      </BitField>
+      <BitField name="RTYPE_IN" description="Reverse type input" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit level input" start="0x0" />
+        <Enum name="B_0x1" description="Byte or half-word level input" start="0x1" />
+      </BitField>
+      <BitField name="RTYPE_OUT" description="Reverse type output" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit level output" start="0x0" />
+        <Enum name="B_0x1" description="Byte or half-word level output" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRC_INIT" description="CRC initial value" start="+0x10" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_INIT" description="Programmable initial CRC value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_POL" description="CRC polynomial" start="+0x14" size="4" reset_value="0x04C11DB7" reset_mask="0xFFFFFFFF">
+      <BitField name="POL" description="Programmable polynomial " start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRC_S" description="Cyclic redundancy check calculation unit" start="0x56024C00">
+    <Register name="CRC_DR" description="CRC data register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data register bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_IDR" description="CRC independent data register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDR" description="General-purpose 32-bit data register bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_CR" description="CRC control register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESET" description="RESET bit" start="0" size="1" access="Read/Write" />
+      <BitField name="POLYSIZE" description="Polynomial size" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="32 bit polynomial" start="0x0" />
+        <Enum name="B_0x1" description="16 bit polynomial" start="0x1" />
+        <Enum name="B_0x2" description="8 bit polynomial" start="0x2" />
+        <Enum name="B_0x3" description="7 bit polynomial" start="0x3" />
+      </BitField>
+      <BitField name="REV_IN" description="Reverse input data" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Bit order not affected (RTYPE_IN = 0 or 1)" start="0x0" />
+        <Enum name="B_0x1" description="Bit reversal done by byte (RTYPE_IN = 0) or half-word reversal done by word (RTYPE_IN = 1)" start="0x1" />
+        <Enum name="B_0x2" description="Bit reversal done by half-word (RTYPE_IN = 0) or byte reversal done by word (RTYPE_IN = 1)" start="0x2" />
+        <Enum name="B_0x3" description="Bit reversal done by word (RTYPE_IN = 0) or bit order is not affected (RTYPE_IN = 1)" start="0x3" />
+      </BitField>
+      <BitField name="REV_OUT" description="Reverse output data" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Bit order not affected (RTYPE_OUT = 0 or 1)" start="0x0" />
+        <Enum name="B_0x1" description="Bit-reversed output format (RTYPE_OUT = 0) or half-word reversal done by word (RTYPE_OUT = 1)" start="0x1" />
+        <Enum name="B_0x2" description="Bit order not affected (RTYPE_OUT = 0) or byte reversal done by word (RTYPE_OUT = 1)" start="0x2" />
+        <Enum name="B_0x3" description="Bit order not affected (RTYPE_OUT = 0 or 1)" start="0x3" />
+      </BitField>
+      <BitField name="RTYPE_IN" description="Reverse type input" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit level input" start="0x0" />
+        <Enum name="B_0x1" description="Byte or half-word level input" start="0x1" />
+      </BitField>
+      <BitField name="RTYPE_OUT" description="Reverse type output" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit level output" start="0x0" />
+        <Enum name="B_0x1" description="Byte or half-word level output" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRC_INIT" description="CRC initial value" start="+0x10" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_INIT" description="Programmable initial CRC value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRC_POL" description="CRC polynomial" start="+0x14" size="4" reset_value="0x04C11DB7" reset_mask="0xFFFFFFFF">
+      <BitField name="POL" description="Programmable polynomial " start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRYP" description="Cryptographic processor" start="0x44020800">
+    <Register name="CRYP_CR" description="CRYP control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALGODIR" description="Algorithm direction" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encryption" start="0x0" />
+        <Enum name="B_0x1" description="Decryption" start="0x1" />
+      </BitField>
+      <BitField name="ALGOMODE" description="ALGOMODE[2:0]: Algorithm mode" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="Electronic codebook (ECB)" start="0x4" />
+        <Enum name="B_0x5" description="Cipher Block Chaining (CBC)" start="0x5" />
+        <Enum name="B_0x6" description="Counter mode (CTR)" start="0x6" />
+        <Enum name="B_0x7" description="AES key preparation for ECB or CBC decryption" start="0x7" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No swapping (32-bit data)." start="0x0" />
+        <Enum name="B_0x1" description="Half-word swapping (16-bit data)." start="0x1" />
+        <Enum name="B_0x2" description="Byte swapping (8-bit data)." start="0x2" />
+        <Enum name="B_0x3" description="Bit-level swapping." start="0x3" />
+      </BitField>
+      <BitField name="KEYSIZE" description="Key size selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="128-bits" start="0x0" />
+        <Enum name="B_0x1" description="192 bits" start="0x1" />
+        <Enum name="B_0x2" description="256 bits" start="0x2" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRYPEN" description="CRYP enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRYP enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCM_CCMPH" description="GCM or CCM phase selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Initialization phase" start="0x0" />
+        <Enum name="B_0x1" description="Header phase" start="0x1" />
+        <Enum name="B_0x2" description="Payload phase" start="0x2" />
+        <Enum name="B_0x3" description="Final phase" start="0x3" />
+      </BitField>
+      <BitField name="ALGOMODE_1" description="ALGOMODE[3]" start="19" size="1" access="Read/Write" />
+      <BitField name="NPBLB" description="Number of padding bytes in last block" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="All bytes are valid (no padding)" start="0x0" />
+        <Enum name="B_0x1" description="Padding for the last LSB byte" start="0x1" />
+        <Enum name="B_0xF" description="Padding for the 15 LSB bytes of last block." start="0xF" />
+      </BitField>
+      <BitField name="KMOD" description="Key mode selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Normal-key mode. Key registers are freely usable." start="0x0" />
+        <Enum name="B_0x2" description="Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register." start="0x2" />
+      </BitField>
+      <BitField name="IPRST" description="CRYP peripheral software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_SR" description="CRYP status register" start="+0x04" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="IFEM" description="Input FIFO empty flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Input FIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is empty" start="0x1" />
+      </BitField>
+      <BitField name="IFNF" description="Input FIFO not full flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Input FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="OFNE" description="Output FIFO not empty flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Output FIFO is empty" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is not empty" start="0x1" />
+      </BitField>
+      <BitField name="OFFU" description="Output FIFO full flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Output FIFO is not full" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is full" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy bit" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle" start="0x0" />
+        <Enum name="B_0x1" description="Busy" start="0x1" />
+      </BitField>
+      <BitField name="KERF" description="Key error flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No key error detected" start="0x0" />
+        <Enum name="B_0x1" description="Key information failed to load into key registers" start="0x1" />
+      </BitField>
+      <BitField name="KEYVALID" description="Key valid flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Key not valid" start="0x0" />
+        <Enum name="B_0x1" description="Key valid" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_DINR" description="CRYP data input register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="Data input" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_DOUTR" description="CRYP data output register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="Data output" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CRYP_DMACR" description="CRYP DMA control register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIEN" description="DMA input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Incoming data transfer to CRYP via DMA is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Incoming data transfer to CRYP via DMA is disabled" start="0x1" />
+      </BitField>
+      <BitField name="DOEN" description="DMA output enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Outgoing data transfer from CRYP via DMA is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Outgoing data transfer from CRYP via DMA is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_IMSCR" description="CRYP interrupt mask set/clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIM" description="Input FIFO service interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input FIFO interrupt is disabled (masked), masked interrupt status (INMIS) stays cleared" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO interrupt is enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="OUTIM" description="Output FIFO service interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output FIFO interrupt is disabled (masked), masked interrupt status (OUTMIS) stays cleared" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO interrupt is enabled (not masked)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_RISR" description="CRYP raw interrupt status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INRIS" description="Input FIFO service raw interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input FIFO event detected" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO empty or not full detected; an interrupt is generated if CRYPEN is set and if INIM bit is set in CRYP_IMSCR register" start="0x1" />
+      </BitField>
+      <BitField name="OUTRIS" description="Output FIFO service raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No output FIFO event detected" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO full or not empty detected; an interrupt is generated if OUTIM bit is set in CRYP_IMSCR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_MISR" description="CRYP masked interrupt status register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INMIS" description="Input FIFO service masked interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input FIFO event detected or INIM mask cleared in CRYP_IMSCR or CRYPEN bit cleared." start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO empty or not full detected, with an interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="OUTMIS" description="Output FIFO service masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No output FIFO event detected or OUTIM mask cleared in CRYP_IMSCR" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO full or not empty detected, with an interrupt pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_K0LR" description="CRYP key register 0L" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K0RR" description="CRYP key register 0R" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K1LR" description="CRYP key register 1L" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K1RR" description="CRYP key register 1R" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K2LR" description="CRYP key register 2L" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K2RR" description="CRYP key register 2R" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K3LR" description="CRYP key register 3L" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K3RR" description="CRYP key register 3R" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_IV0LR" description="CRYP initialization vector register 0L" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV0RR" description="CRYP initialization vector register 0R" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV1LR" description="CRYP initialization vector register 1L" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV1RR" description="CRYP initialization vector register 1R" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM0R" description="CRYP context swap GCM-CCM registers" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM1R" description="CRYP context swap GCM-CCM registers" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM2R" description="CRYP context swap GCM-CCM registers" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM3R" description="CRYP context swap GCM-CCM registers" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM4R" description="CRYP context swap GCM-CCM registers" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM5R" description="CRYP context swap GCM-CCM registers" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM6R" description="CRYP context swap GCM-CCM registers" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM7R" description="CRYP context swap GCM-CCM registers" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM0R" description="CRYP context swap GCM registers" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM1R" description="CRYP context swap GCM registers" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM2R" description="CRYP context swap GCM registers" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM3R" description="CRYP context swap GCM registers" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM4R" description="CRYP context swap GCM registers" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM5R" description="CRYP context swap GCM registers" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM6R" description="CRYP context swap GCM registers" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM7R" description="CRYP context swap GCM registers" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRYP_S" description="Cryptographic processor" start="0x54020800">
+    <Register name="CRYP_CR" description="CRYP control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALGODIR" description="Algorithm direction" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encryption" start="0x0" />
+        <Enum name="B_0x1" description="Decryption" start="0x1" />
+      </BitField>
+      <BitField name="ALGOMODE" description="ALGOMODE[2:0]: Algorithm mode" start="3" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="Electronic codebook (ECB)" start="0x4" />
+        <Enum name="B_0x5" description="Cipher Block Chaining (CBC)" start="0x5" />
+        <Enum name="B_0x6" description="Counter mode (CTR)" start="0x6" />
+        <Enum name="B_0x7" description="AES key preparation for ECB or CBC decryption" start="0x7" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No swapping (32-bit data)." start="0x0" />
+        <Enum name="B_0x1" description="Half-word swapping (16-bit data)." start="0x1" />
+        <Enum name="B_0x2" description="Byte swapping (8-bit data)." start="0x2" />
+        <Enum name="B_0x3" description="Bit-level swapping." start="0x3" />
+      </BitField>
+      <BitField name="KEYSIZE" description="Key size selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="128-bits" start="0x0" />
+        <Enum name="B_0x1" description="192 bits" start="0x1" />
+        <Enum name="B_0x2" description="256 bits" start="0x2" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRYPEN" description="CRYP enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRYP enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCM_CCMPH" description="GCM or CCM phase selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Initialization phase" start="0x0" />
+        <Enum name="B_0x1" description="Header phase" start="0x1" />
+        <Enum name="B_0x2" description="Payload phase" start="0x2" />
+        <Enum name="B_0x3" description="Final phase" start="0x3" />
+      </BitField>
+      <BitField name="ALGOMODE_1" description="ALGOMODE[3]" start="19" size="1" access="Read/Write" />
+      <BitField name="NPBLB" description="Number of padding bytes in last block" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="All bytes are valid (no padding)" start="0x0" />
+        <Enum name="B_0x1" description="Padding for the last LSB byte" start="0x1" />
+        <Enum name="B_0xF" description="Padding for the 15 LSB bytes of last block." start="0xF" />
+      </BitField>
+      <BitField name="KMOD" description="Key mode selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Normal-key mode. Key registers are freely usable." start="0x0" />
+        <Enum name="B_0x2" description="Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register." start="0x2" />
+      </BitField>
+      <BitField name="IPRST" description="CRYP peripheral software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_SR" description="CRYP status register" start="+0x04" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="IFEM" description="Input FIFO empty flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Input FIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is empty" start="0x1" />
+      </BitField>
+      <BitField name="IFNF" description="Input FIFO not full flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Input FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="OFNE" description="Output FIFO not empty flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Output FIFO is empty" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is not empty" start="0x1" />
+      </BitField>
+      <BitField name="OFFU" description="Output FIFO full flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Output FIFO is not full" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is full" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy bit" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle" start="0x0" />
+        <Enum name="B_0x1" description="Busy" start="0x1" />
+      </BitField>
+      <BitField name="KERF" description="Key error flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No key error detected" start="0x0" />
+        <Enum name="B_0x1" description="Key information failed to load into key registers" start="0x1" />
+      </BitField>
+      <BitField name="KEYVALID" description="Key valid flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Key not valid" start="0x0" />
+        <Enum name="B_0x1" description="Key valid" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_DINR" description="CRYP data input register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="Data input" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_DOUTR" description="CRYP data output register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="Data output" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="CRYP_DMACR" description="CRYP DMA control register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIEN" description="DMA input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Incoming data transfer to CRYP via DMA is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Incoming data transfer to CRYP via DMA is disabled" start="0x1" />
+      </BitField>
+      <BitField name="DOEN" description="DMA output enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Outgoing data transfer from CRYP via DMA is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Outgoing data transfer from CRYP via DMA is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_IMSCR" description="CRYP interrupt mask set/clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIM" description="Input FIFO service interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input FIFO interrupt is disabled (masked), masked interrupt status (INMIS) stays cleared" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO interrupt is enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="OUTIM" description="Output FIFO service interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output FIFO interrupt is disabled (masked), masked interrupt status (OUTMIS) stays cleared" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO interrupt is enabled (not masked)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_RISR" description="CRYP raw interrupt status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INRIS" description="Input FIFO service raw interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input FIFO event detected" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO empty or not full detected; an interrupt is generated if CRYPEN is set and if INIM bit is set in CRYP_IMSCR register" start="0x1" />
+      </BitField>
+      <BitField name="OUTRIS" description="Output FIFO service raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No output FIFO event detected" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO full or not empty detected; an interrupt is generated if OUTIM bit is set in CRYP_IMSCR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_MISR" description="CRYP masked interrupt status register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INMIS" description="Input FIFO service masked interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input FIFO event detected or INIM mask cleared in CRYP_IMSCR or CRYPEN bit cleared." start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO empty or not full detected, with an interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="OUTMIS" description="Output FIFO service masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No output FIFO event detected or OUTIM mask cleared in CRYP_IMSCR" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO full or not empty detected, with an interrupt pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CRYP_K0LR" description="CRYP key register 0L" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K0RR" description="CRYP key register 0R" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K1LR" description="CRYP key register 1L" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K1RR" description="CRYP key register 1R" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K2LR" description="CRYP key register 2L" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K2RR" description="CRYP key register 2R" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K3LR" description="CRYP key register 3L" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_K3RR" description="CRYP key register 3R" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="K" description="Key bit x" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CRYP_IV0LR" description="CRYP initialization vector register 0L" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV0RR" description="CRYP initialization vector register 0R" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV1LR" description="CRYP initialization vector register 1L" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_IV1RR" description="CRYP initialization vector register 1R" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector bit x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM0R" description="CRYP context swap GCM-CCM registers" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM1R" description="CRYP context swap GCM-CCM registers" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM2R" description="CRYP context swap GCM-CCM registers" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM3R" description="CRYP context swap GCM-CCM registers" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM4R" description="CRYP context swap GCM-CCM registers" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM5R" description="CRYP context swap GCM-CCM registers" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM6R" description="CRYP context swap GCM-CCM registers" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCMCCM7R" description="CRYP context swap GCM-CCM registers" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCMCCM" description="Context swap for GCM/GMAC and CCM modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM0R" description="CRYP context swap GCM registers" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM1R" description="CRYP context swap GCM registers" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM2R" description="CRYP context swap GCM registers" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM3R" description="CRYP context swap GCM registers" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM4R" description="CRYP context swap GCM registers" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM5R" description="CRYP context swap GCM registers" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM6R" description="CRYP context swap GCM registers" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CRYP_CSGCM7R" description="CRYP context swap GCM registers" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSGCM" description="Context swap for GCM/GMAC modes" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CSI" description="CSI-2 Host" start="0x48006000">
+    <Register name="CSI_CR" description="CSI-2 Host control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSIEN" description="CSI-2 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI-2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="VC0START" description="Virtual channel 0 start" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 0 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC0STOP" description="Virtual channel 0 stop" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 0 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC1START" description="Virtual channel 1 start" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 1 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC1STOP" description="Virtual channel 1 stop" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 1 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC2START" description="Virtual channel 2 start" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 2 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC2STOP" description="Virtual channel 2 stop" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 2 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC3START" description="Virtual channel 3 start" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 3 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC3STOP" description="Virtual channel 3 stop " start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 3 processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PCR" description="CSI-2 Host DPHY_RX control register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDOWN" description="Power down" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Active state" start="0x0" />
+        <Enum name="B_0x1" description="Power down the D-PHY_RX" start="0x1" />
+      </BitField>
+      <BitField name="CLEN" description="Clock lane enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock lanes disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock lanes enabled" start="0x1" />
+      </BitField>
+      <BitField name="DL0EN" description="D-PHY_RX data lane 0 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data lane 0 module is in shutdown mode." start="0x0" />
+        <Enum name="B_0x1" description="Enable the data lane 0 module." start="0x1" />
+      </BitField>
+      <BitField name="DL1EN" description="D-PHY_RX data lane 1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data lane 1 module is in shutdown mode." start="0x0" />
+        <Enum name="B_0x1" description="Enable the data lane 1 module." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR1" description="CSI-2 Host virtual channel 0 configuration register 1" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR2" description="CSI-2 Host virtual channel 0 configuration register 2" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR3" description="CSI-2 Host virtual channel 0 configuration register 3" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR4" description="CSI-2 Host virtual channel 0 configuration register 4" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR1" description="CSI-2 Host virtual channel 1 configuration register 1" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR2" description="CSI-2 Host virtual channel 1 configuration register 2" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR3" description="CSI-2 Host virtual channel 1 configuration register 3" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR4" description="CSI-2 Host virtual channel 1 configuration register 4" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR1" description="CSI-2 Host virtual channel 2 configuration register 1" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR2" description="CSI-2 Host virtual channel 2 configuration register 2" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR3" description="CSI-2 Host virtual channel 2 configuration register 3" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR4" description="CSI-2 Host virtual channel 2 configuration register 4" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR1" description="CSI-2 Host virtual channel 3 configuration register 1" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR2" description="CSI-2 Host virtual channel 3 configuration register 2" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR3" description="CSI-2 Host virtual channel 3 configuration register 3" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR4" description="CSI-2 Host virtual channel 3 configuration register 4" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_LB0CFGR" description="CSI-2 Host line byte 0 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB1CFGR" description="CSI-2 Host line byte 1 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB2CFGR" description="CSI-2 Host line byte 2 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB3CFGR" description="CSI-2 Host line byte 3 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM0CFGR" description="CSI-2 Host timer 0 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM1CFGR" description="CSI-2 Host timer 1 configuration register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM2CFGR" description="CSI-2 Host timer 2 configuration register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM3CFGR" description="CSI-2 Host timer 3 configuration register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LMCFGR" description="CSI-2 Host lane merger configuration register" start="+0x70" size="4" reset_value="0x43210200" reset_mask="0xFFFFFFFF">
+      <BitField name="LANENB" description="Number of lanes" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="1 lane for the reception" start="0x1" />
+        <Enum name="B_0x2" description="2 lanes for the reception" start="0x2" />
+      </BitField>
+      <BitField name="DL0MAP" description="Physical mapping of logical data lane 0" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="Physical data lane 0 connected to logical data lane 0" start="0x1" />
+        <Enum name="B_0x2" description="Physical data lane 0 connected to logical data lane 1" start="0x2" />
+      </BitField>
+      <BitField name="DL1MAP" description="Physical mapping of logical data lane 1" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="Physical data lane 1 connected to logical data lane 0" start="0x1" />
+        <Enum name="B_0x2" description="Physical data lane 1 connected to logical data lane 1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PRGITR" description="CSI-2 Host program interrupt register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0VC" description="Line/byte counter 0 linked to a virtual channel" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 0 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 0 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 0 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 0 event" start="0x3" />
+      </BitField>
+      <BitField name="LB0EN" description="Line/byte 0 counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 0 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 0 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB1VC" description="Line/byte counter 1 linked to a virtual channel" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 1 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 1 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 1 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 1 event" start="0x3" />
+      </BitField>
+      <BitField name="LB1EN" description="Line/byte 1 counter enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 1 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 1 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB2VC" description="Line/byte counter 2 linked to a virtual channel" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 2 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 2 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 2 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 2 event" start="0x3" />
+      </BitField>
+      <BitField name="LB2EN" description="Line/byte 2 counter enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 2 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 2 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB3VC" description="Line/byte counter 3 linked to a virtual channel" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 3 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 3 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 3 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 3 event" start="0x3" />
+      </BitField>
+      <BitField name="LB3EN" description="Line/byte 3 counter enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 3 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 3 counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM0VC" description="TIM0 base time linked to a virtual channel" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM0 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM0 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM0 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM0 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM0EOF" description="TIM0 base time starting from the EOF" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected e as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM0EN" description="TIM0 base time enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 0 clock cycle counter not active" start="0x0" />
+        <Enum name="B_0x1" description="Timer 0 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM1VC" description="TIM1 base time linked to a virtual channel" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM1 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM1 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM1 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM1 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM1EOF" description="TIM1 base time starting from the EOF" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM1EN" description="TIM1 base time enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 1 clock cycle counter not active." start="0x0" />
+        <Enum name="B_0x1" description="Timer 1 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM2VC" description="TIM2 base time linked to a virtual channel" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM2 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM2 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM2 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM2 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM2EOF" description="TIM2 base time starting from the EOF" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM2EN" description="TIM2 base time enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 2 clock cycle counter not active." start="0x0" />
+        <Enum name="B_0x1" description="Timer 2 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM3VC" description="TIM3 base time linked to a virtual channel" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM3 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM3 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM3 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM3 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM3EOF" description="TIM3 base time starting from the EOF" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM3EN" description="TIM3 base time enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 3 clock cycle counter not active" start="0x0" />
+        <Enum name="B_0x1" description="Timer 3 clock cycle counter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_WDR" description="CSI-2 Host watchdog register" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Watchdog counter" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CSI_IER0" description="CSI-2 Host interrupt enable register 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0IE" description="Line/byte counter 0 interrupt enable " start="0" size="1" access="Read/Write" />
+      <BitField name="LB1IE" description="Line/byte counter 1 interrupt enable " start="1" size="1" access="Read/Write" />
+      <BitField name="LB2IE" description="Line/byte counter 2 interrupt enable " start="2" size="1" access="Read/Write" />
+      <BitField name="LB3IE" description="Line/byte counter 3 interrupt enable " start="3" size="1" access="Read/Write" />
+      <BitField name="TIM0IE" description="Timer 0 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM1IE" description="Timer 1 interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM2IE" description="Timer 2 interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM3IE" description="Timer 3 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF0IE" description="SOF for virtual channel 0 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF1IE" description="SOF for virtual channel 1 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="SOF2IE" description="SOF for virtual channel 2 interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF3IE" description="SOF for virtual channel 3 interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF0IE" description="EOF for virtual channel 0 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF1IE" description="EOF for virtual channel 1 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF2IE" description="EOF for virtual channel 2 interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF3IE" description="EOF for virtual channel 3 interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPKTIE" description="Short packet interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Short packet detection interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Short packet detection interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCFIFOFIE" description="Clock changer FIFO full interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on clock changer FIFO full detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on clock changer FIFO full detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCERRIE" description="CRC error interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on CRC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on CRC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECCERRIE" description="ECC error interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on ECC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on ECC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="CECCERRIE" description="Corrected ECC error interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on corrected ECC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on corrected ECC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDERRIE" description="Data type ID error interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on reception of reserved data type disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on reception of reserved data type enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPKTERRIE" description="Short packet error interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on short packet error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on short packet error enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDERRIE" description="Watchdog error interrupt enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on watchdog error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on watchdog error enabled" start="0x1" />
+      </BitField>
+      <BitField name="SYNCERRIE" description="Invalid synchronization error interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on invalid synchronization error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on invalid synchronization error enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_IER1" description="CSI-2 Host interrupt enable register 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESOTDL0IE" description="SOT error interrupt enable on lane 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 SOT interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 SOT interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTSYNCDL0IE" description="SOT synchronization interrupt error enable on lane 0" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 SOT synchronization interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 SOT synchronization interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="EESCDL0IE" description="D-PHY_RX lane 0 escape entry error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 unrecognized escape entry command interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 unrecognized escape entry command interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESYNCESCDL0IE" description="D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 low-power data transmission interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 low-power data transmission Interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECTRLDL0IE" description="D-PHY_RX lane 0 control error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 control error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 control error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTDL1IE" description="SOT error interrupt enable on lane 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 SOT interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 SOT interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTSYNCDL1IE" description="SOT synchronization interrupt error enable on lane 1" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 SOT synchronization interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 SOT synchronization interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="EESCDL1IE" description="D-PHY_RX lane 1 escape entry error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 unrecognized escape entry command interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 unrecognized escape entry command interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESYNCESCDL1IE" description="D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 low-power data transmission interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 low-power data transmission Interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECTRLDL1IE" description="D-PHY_RX lane 1 control error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 control error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 control error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_SR0" description="CSI-2 Host status register 0" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0F" description="Line/byte counter 0 flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="LB1F" description="Line/byte counter 1 flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="LB2F" description="Line/byte counter 2 flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="LB3F" description="Line/byte counter 3 flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TIM0F" description="Timer 0 flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TIM1F" description="Timer 1 flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TIM2F" description="Timer 2 flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="TIM3F" description="Timer 3 flag" start="7" size="1" access="ReadOnly" />
+      <BitField name="SOF0F" description="SOF flag for virtual channel 0" start="8" size="1" access="ReadOnly" />
+      <BitField name="SOF1F" description="SOF flag for virtual channel 1 " start="9" size="1" access="ReadOnly" />
+      <BitField name="SOF2F" description="SOF flag for virtual channel 2" start="10" size="1" access="ReadOnly" />
+      <BitField name="SOF3F" description="SOF flag for virtual channel 3 " start="11" size="1" access="ReadOnly" />
+      <BitField name="EOF0F" description="EOF flag for virtual channel 0 " start="12" size="1" access="ReadOnly" />
+      <BitField name="EOF1F" description="EOF flag for virtual channel 1 " start="13" size="1" access="ReadOnly" />
+      <BitField name="EOF2F" description="EOF flag for virtual channel 2 " start="14" size="1" access="ReadOnly" />
+      <BitField name="EOF3F" description="EOF flag for virtual channel 3 " start="15" size="1" access="ReadOnly" />
+      <BitField name="SPKTF" description="Short packet flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="VC0STATEF" description="Virtual channel 0 state flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC1STATEF" description="Virtual channel 1 state flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC2STATEF" description="Virtual channel 2 state flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC3STATEF" description="Virtual channel 3 state flag" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="CCFIFOFF" description="Clock changer FIFO full flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="CRCERRF" description="CRC error flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ECCERRF" description="ECC error flag" start="25" size="1" access="ReadOnly" />
+      <BitField name="CECCERRF" description="Corrected ECC error flag" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDERRF" description="Data type ID error flag" start="27" size="1" access="ReadOnly" />
+      <BitField name="SPKTERRF" description="Short packet error flag" start="28" size="1" access="ReadOnly" />
+      <BitField name="WDERRF" description="Watchdog error flag" start="29" size="1" access="ReadOnly" />
+      <BitField name="SYNCERRF" description="Invalid synchronization error flag" start="30" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_SR1" description="CSI-2 Host status register 1" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESOTDL0F" description="SOT error flag on lane 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="ESOTSYNCDL0F" description="SOT synchronization error flag on lane 0" start="1" size="1" access="ReadOnly" />
+      <BitField name="EESCDL0F" description="D-PHY_RX lane 0 escape entry error flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="ESYNCESCDL0F" description="D-PHY_RX lane 0 low-power data transmission synchronization error flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="ECTRLDL0F" description="D-PHY_RX lane 0 control error flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ESOTDL1F" description="SOT error flag on lane 1" start="8" size="1" access="ReadOnly" />
+      <BitField name="ESOTSYNCDL1F" description="SOT synchronization error flag on lane 1" start="9" size="1" access="ReadOnly" />
+      <BitField name="EESCDL1F" description="D-PHY_RX lane 1 escape entry error flag" start="10" size="1" access="ReadOnly" />
+      <BitField name="ESYNCESCDL1F" description="D-PHY_RX lane 1 low-power data transmission synchronization error flag" start="11" size="1" access="ReadOnly" />
+      <BitField name="ECTRLDL1F" description="D-PHY_RX lane 1 control error flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ACTDL0F" description="D-PHY_RX lane 0 high-speed reception active" start="16" size="1" access="ReadOnly" />
+      <BitField name="SYNCDL0F" description="D-PHY_RX lane 0 receiver synchronization observed" start="17" size="1" access="ReadOnly" />
+      <BitField name="SKCALDL0F" description="D-PHY_RX lane 0 high-speed skew calibration" start="18" size="1" access="ReadOnly" />
+      <BitField name="STOPDL0F" description="D-PHY_RX receiver data lane 0 in stop state" start="19" size="1" access="ReadOnly" />
+      <BitField name="ULPNDL0F" description="D-PHY_RX receiver ultra-low-power state (not) active on data lane 0" start="20" size="1" access="ReadOnly" />
+      <BitField name="ACTDL1F" description="D-PHY_RX lane 1 high-speed reception active" start="22" size="1" access="ReadOnly" />
+      <BitField name="SYNCDL1F" description="D-PHY_RX lane 1 receiver synchronization observed" start="23" size="1" access="ReadOnly" />
+      <BitField name="SKCALDL1F" description="D-PHY_RX lane 1 high-speed skew calibration" start="24" size="1" access="ReadOnly" />
+      <BitField name="STOPDL1F" description="D-PHY_RX receiver data lane 1 in stop state" start="25" size="1" access="ReadOnly" />
+      <BitField name="ULPNDL1F" description="D-PHY_RX receiver ultra-low-power state (not) active on data lane 1" start="26" size="1" access="ReadOnly" />
+      <BitField name="STOPCLF" description="D-PHY_RX receiver in stop state for the clock lane" start="28" size="1" access="ReadOnly" />
+      <BitField name="ULPNACTF" description="D-PHY_RX receiver ULP state (not) active" start="29" size="1" access="ReadOnly" />
+      <BitField name="ULPNCLF" description="D-PHY_RX receiver Ultra-Low power state (not) on clock lane." start="30" size="1" access="ReadOnly" />
+      <BitField name="ACTCLF" description="D-PHY_RX receiver clock active flag" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_FCR0" description="CSI-2 Host flag clear register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLB0F" description="Clear line/byte counter 0 flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CLB1F" description="Clear line/byte counter 1 flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CLB2F" description="Clear line/byte counter 2 flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CLB3F" description="Clear line/byte counter 3 flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTIM0F" description="Clear timer 0 flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CTIM1F" description="Clear timer 1 flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CTIM2F" description="Clear timer 2 flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CTIM3F" description="Clear timer 3 flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="CSOF0F" description="Clear SOF flag for virtual channel 0 " start="8" size="1" access="WriteOnly" />
+      <BitField name="CSOF1F" description="Clear SOF flag for virtual channel 1 " start="9" size="1" access="WriteOnly" />
+      <BitField name="CSOF2F" description="Clear SOF flag for virtual channel 2" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSOF3F" description="Clear SOF flag for virtual channel 3 " start="11" size="1" access="WriteOnly" />
+      <BitField name="CEOF0F" description="Clear EOF flag for virtual channel 0 " start="12" size="1" access="WriteOnly" />
+      <BitField name="CEOF1F" description="Clear EOF flag for virtual channel 1 " start="13" size="1" access="WriteOnly" />
+      <BitField name="CEOF2F" description="Clear EOF flag for virtual channel 2 " start="14" size="1" access="WriteOnly" />
+      <BitField name="CEOF3F" description="Clear EOF flag for virtual channel 3 " start="15" size="1" access="WriteOnly" />
+      <BitField name="CSPKTF" description="Clear short packet flag" start="16" size="1" access="WriteOnly" />
+      <BitField name="CCCFIFOFF" description="Clear clock changer FIFO full flag" start="21" size="1" access="WriteOnly" />
+      <BitField name="CCRCERRF" description="Clear CRC error flag" start="24" size="1" access="WriteOnly" />
+      <BitField name="CECCERRF" description="Clear ECC error flag" start="25" size="1" access="WriteOnly" />
+      <BitField name="CCECCERRF" description="Clear corrected ECC error flag" start="26" size="1" access="WriteOnly" />
+      <BitField name="CIDERRF" description="Clear data type ID error flag" start="27" size="1" access="WriteOnly" />
+      <BitField name="CSPKTERRF" description="Clear short packet error flag" start="28" size="1" access="WriteOnly" />
+      <BitField name="CWDERRF" description="Clear watchdog error flag" start="29" size="1" access="WriteOnly" />
+      <BitField name="CSYNCERRF" description="Clear invalid synchronization error flag" start="30" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="CSI_FCR1" description="CSI-2 Host flag clear register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CESOTDL0F" description="Clear SOT error flag on lane 0" start="0" size="1" access="WriteOnly" />
+      <BitField name="CESOTSYNCDL0F" description="Clear SOT synchronization error flag on lane 0" start="1" size="1" access="WriteOnly" />
+      <BitField name="CEESCDL0F" description="Clear D-PHY_RX lane 0 escape entry error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CESYNCESCDL0F" description="Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CECTRLDL0F" description="Clear D-PHY_RX lane 0 control error flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CESOTDL1F" description="Clear SOT error flag on lane 1" start="8" size="1" access="WriteOnly" />
+      <BitField name="CESOTSYNCDL1F" description="Clear SOT synchronization error flag on lane 1" start="9" size="1" access="WriteOnly" />
+      <BitField name="CEESCDL1F" description="Clear D-PHY_RX lane 1 escape entry error flag" start="10" size="1" access="WriteOnly" />
+      <BitField name="CESYNCESCDL1F" description="Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="CECTRLDL1F" description="Clear D-PHY_RX lane 1 control error flag" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="CSI_SPDFR" description="CSI-2 Host short packet data field register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAFIELD" description="Data field " start="0" size="16" access="ReadOnly" />
+      <BitField name="DATATYPE" description="Data type class" start="16" size="6" access="ReadOnly" />
+      <BitField name="VCHANNEL" description="Virtual channel" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_ERR1" description="CSI-2 Host error register 1" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCDTERR" description="Data type having a CRC error" start="0" size="6" access="ReadOnly" />
+      <BitField name="CRCVCERR" description="Virtual channel having a CRC error" start="6" size="2" access="ReadOnly" />
+      <BitField name="CECCDTERR" description="Data type having a corrected ECC error" start="8" size="6" access="ReadOnly" />
+      <BitField name="CECCVCERR" description="Virtual channel having a corrected ECC error" start="14" size="2" access="ReadOnly" />
+      <BitField name="IDDTERR" description="Data type in error " start="16" size="6" access="ReadOnly" />
+      <BitField name="IDVCERR" description="Virtual channel having ID error" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_ERR2" description="CSI-2 Host error register 2" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPKTDTERR" description="Data type having a short packet error" start="0" size="6" access="ReadOnly" />
+      <BitField name="SPKTVCERR" description="Virtual channel having a short packet error" start="6" size="2" access="ReadOnly" />
+      <BitField name="WDVCERR" description="Virtual channel having a watchdog error" start="16" size="2" access="ReadOnly" />
+      <BitField name="SYNCVCERR" description="Virtual channel having synchronization error" start="18" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_PRCR" description="CSI PHY reset control register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEN" description="When set to 0, this bit places the digital section of the D-PHY in the reset state." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PHY is disabled (in reset state)." start="0x0" />
+        <Enum name="B_0x1" description="PHY is enabled (out of reset state)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PMCR" description="CSI PHY mode control register" start="+0x1004" size="4" reset_value="0x00011003" reset_mask="0xFFFFFFFF">
+      <BitField name="FRXMDL0" description="Force to Rx mode the data lane 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="FRXMDL1" description="Force to Rx mode the data lane 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTXSMDL0" description="Force to Tx Stop mode the data lane 0" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTDL" description="Disable turn-around data lane 0" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTDL0" description="Turn-around request data lane 0" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No request" start="0x0" />
+        <Enum name="B_0x1" description="Request for turn-around for DL0" start="0x1" />
+      </BitField>
+      <BitField name="TUESDL0" description="Tx ULP escape-mode data lane 0" start="12" size="1" access="Read/Write" />
+      <BitField name="TUEXDL0" description="Tx ULP exit sequence data lane 0" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CSI_PFCR" description="CSI PHY frequency control register" start="+0x1008" size="4" reset_value="0x00000017" reset_mask="0xFFFFFFFF">
+      <BitField name="CCFR" description="Configuration clock frequency range selection" start="0" size="6" access="Read/Write" />
+      <BitField name="HSFR" description="PHY high-speed frequency range selection" start="8" size="7" access="Read/Write" />
+      <BitField name="DLD" description="Data lane direction of lane 0" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx" start="0x0" />
+        <Enum name="B_0x1" description="Tx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PTCR0" description="CSI PHY test control register 0" start="+0x1010" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TCKEN" description="Test-interface clock enable for the TDI bus into the PHY" start="0" size="1" access="Read/Write" />
+      <BitField name="TRSEN" description="Test-interface reset enable for the TDI bus into the PHY" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CSI_PTCR1" description="CSI PHY test control register 1" start="+0x1014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDI" description="Test-interface data in" start="0" size="8" access="Read/Write" />
+      <BitField name="TWM" description="Test-interface write mode selector" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data write operation is set on the rising edge of the testclk signal." start="0x0" />
+        <Enum name="B_0x1" description="Address write operation is set on the falling edge of the testclk signal." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PTSR" description="CSI PHY test status register" start="+0x1018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDO" description="CSI PHY test interface data output bus for read-back and internal probing functionalities" start="0" size="8" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CSI_S" description="CSI-2 Host" start="0x58006000">
+    <Register name="CSI_CR" description="CSI-2 Host control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSIEN" description="CSI-2 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI-2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="VC0START" description="Virtual channel 0 start" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 0 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC0STOP" description="Virtual channel 0 stop" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 0 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC1START" description="Virtual channel 1 start" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 1 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC1STOP" description="Virtual channel 1 stop" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 1 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC2START" description="Virtual channel 2 start" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 2 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC2STOP" description="Virtual channel 2 stop" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 2 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC3START" description="Virtual channel 3 start" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to start the virtual channel 3 processing" start="0x1" />
+      </BitField>
+      <BitField name="VC3STOP" description="Virtual channel 3 stop " start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Pulse generation to stop the virtual channel 3 processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PCR" description="CSI-2 Host DPHY_RX control register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDOWN" description="Power down" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Active state" start="0x0" />
+        <Enum name="B_0x1" description="Power down the D-PHY_RX" start="0x1" />
+      </BitField>
+      <BitField name="CLEN" description="Clock lane enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock lanes disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock lanes enabled" start="0x1" />
+      </BitField>
+      <BitField name="DL0EN" description="D-PHY_RX data lane 0 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data lane 0 module is in shutdown mode." start="0x0" />
+        <Enum name="B_0x1" description="Enable the data lane 0 module." start="0x1" />
+      </BitField>
+      <BitField name="DL1EN" description="D-PHY_RX data lane 1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data lane 1 module is in shutdown mode." start="0x0" />
+        <Enum name="B_0x1" description="Enable the data lane 1 module." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR1" description="CSI-2 Host virtual channel 0 configuration register 1" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR2" description="CSI-2 Host virtual channel 0 configuration register 2" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR3" description="CSI-2 Host virtual channel 0 configuration register 3" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC0CFGR4" description="CSI-2 Host virtual channel 0 configuration register 4" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR1" description="CSI-2 Host virtual channel 1 configuration register 1" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR2" description="CSI-2 Host virtual channel 1 configuration register 2" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR3" description="CSI-2 Host virtual channel 1 configuration register 3" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC1CFGR4" description="CSI-2 Host virtual channel 1 configuration register 4" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR1" description="CSI-2 Host virtual channel 2 configuration register 1" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR2" description="CSI-2 Host virtual channel 2 configuration register 2" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR3" description="CSI-2 Host virtual channel 2 configuration register 3" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC2CFGR4" description="CSI-2 Host virtual channel 2 configuration register 4" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR1" description="CSI-2 Host virtual channel 3 configuration register 1" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALLDT" description="All data types enable for the virtual channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type capture managed individually" start="0x0" />
+        <Enum name="B_0x1" description="All data types captured for virtual channel x" start="0x1" />
+      </BitField>
+      <BitField name="DT0EN" description="Data type 0 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 0 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 0 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT1EN" description="Data type 1 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 1 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 1 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT2EN" description="Data type 2 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 2 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 2 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT3EN" description="Data type 3 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 3 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 3 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT4EN" description="Data type 4 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 4 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 4 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT5EN" description="Data type 5 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 5 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 5 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DT6EN" description="Data type 6 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data type 6 for virtual channel x is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Data type 6 for virtual channel x is enabled." start="0x1" />
+      </BitField>
+      <BitField name="CDTFT" description="Common format for all data types" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT0" description="Data type 0 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT0FT" description="Data type 0 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR2" description="CSI-2 Host virtual channel 3 configuration register 2" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT1" description="Data type 1 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT1FT" description="Data type 1 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7 -it words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8 -it words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12 -it words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14 -it words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16 -it words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT2" description="Data type 2 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT2FT" description="Data type 2 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR3" description="CSI-2 Host virtual channel 3 configuration register 3" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT3" description="Data type 3 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT3FT" description="Data type 3 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT4" description="Data type 4 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT4FT" description="Data type 4 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_VC3CFGR4" description="CSI-2 Host virtual channel 3 configuration register 4" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DT5" description="Data type 5 class selection for virtual channel x" start="0" size="6" access="Read/Write" />
+      <BitField name="DT5FT" description="Data type 5 format" start="8" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+      <BitField name="DT6" description="Data type 6 class selection for virtual channel x" start="16" size="6" access="Read/Write" />
+      <BitField name="DT6FT" description="Data type 6 format" start="24" size="5" access="Read/Write">
+        <Enum name="BPP6" description="6-bit words (for example RAW6, RGB666)" start="0x0" />
+        <Enum name="BPP7" description="7-bit words (for example RAW7)" start="0x1" />
+        <Enum name="BPP8" description="8-bit words (for example RAW8, YUV 8 bits, RGB888, RGB444, RGB555, RGB565, JPEG)" start="0x2" />
+        <Enum name="BPP10" description="10-bit words (for example RAW10, YUV 10 bits)" start="0x3" />
+        <Enum name="BPP12" description="12-bit words (for example RAW12)" start="0x4" />
+        <Enum name="BPP14" description="14-bit words (for example RAW14)" start="0x5" />
+        <Enum name="BPP16" description="16-bit words (for example RAW16)" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="CSI_LB0CFGR" description="CSI-2 Host line byte 0 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB1CFGR" description="CSI-2 Host line byte 1 configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB2CFGR" description="CSI-2 Host line byte 2 configuration register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LB3CFGR" description="CSI-2 Host line byte 3 configuration register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTECNT" description="Byte counter" start="0" size="16" access="Read/Write" />
+      <BitField name="LINECNT" description="Line counter " start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM0CFGR" description="CSI-2 Host timer 0 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM1CFGR" description="CSI-2 Host timer 1 configuration register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM2CFGR" description="CSI-2 Host timer 2 configuration register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_TIM3CFGR" description="CSI-2 Host timer 3 configuration register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="Clock cycle counter" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="CSI_LMCFGR" description="CSI-2 Host lane merger configuration register" start="+0x70" size="4" reset_value="0x43210200" reset_mask="0xFFFFFFFF">
+      <BitField name="LANENB" description="Number of lanes" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="1 lane for the reception" start="0x1" />
+        <Enum name="B_0x2" description="2 lanes for the reception" start="0x2" />
+      </BitField>
+      <BitField name="DL0MAP" description="Physical mapping of logical data lane 0" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="Physical data lane 0 connected to logical data lane 0" start="0x1" />
+        <Enum name="B_0x2" description="Physical data lane 0 connected to logical data lane 1" start="0x2" />
+      </BitField>
+      <BitField name="DL1MAP" description="Physical mapping of logical data lane 1" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x1" description="Physical data lane 1 connected to logical data lane 0" start="0x1" />
+        <Enum name="B_0x2" description="Physical data lane 1 connected to logical data lane 1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PRGITR" description="CSI-2 Host program interrupt register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0VC" description="Line/byte counter 0 linked to a virtual channel" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 0 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 0 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 0 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 0 event" start="0x3" />
+      </BitField>
+      <BitField name="LB0EN" description="Line/byte 0 counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 0 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 0 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB1VC" description="Line/byte counter 1 linked to a virtual channel" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 1 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 1 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 1 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 1 event" start="0x3" />
+      </BitField>
+      <BitField name="LB1EN" description="Line/byte 1 counter enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 1 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 1 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB2VC" description="Line/byte counter 2 linked to a virtual channel" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 2 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 2 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 2 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 2 event" start="0x3" />
+      </BitField>
+      <BitField name="LB2EN" description="Line/byte 2 counter enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 2 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 2 counter active" start="0x1" />
+      </BitField>
+      <BitField name="LB3VC" description="Line/byte counter 3 linked to a virtual channel" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the line/byte counter 3 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the line/byte counter 3 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the line/byte counter 3 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the line/byte counter 3 event" start="0x3" />
+      </BitField>
+      <BitField name="LB3EN" description="Line/byte 3 counter enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line/byte 3 counter stopped" start="0x0" />
+        <Enum name="B_0x1" description="Line/byte 3 counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM0VC" description="TIM0 base time linked to a virtual channel" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM0 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM0 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM0 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM0 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM0EOF" description="TIM0 base time starting from the EOF" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected e as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM0EN" description="TIM0 base time enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 0 clock cycle counter not active" start="0x0" />
+        <Enum name="B_0x1" description="Timer 0 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM1VC" description="TIM1 base time linked to a virtual channel" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM1 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM1 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM1 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM1 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM1EOF" description="TIM1 base time starting from the EOF" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM1EN" description="TIM1 base time enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 1 clock cycle counter not active." start="0x0" />
+        <Enum name="B_0x1" description="Timer 1 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM2VC" description="TIM2 base time linked to a virtual channel" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM2 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM2 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM2 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM2 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM2EOF" description="TIM2 base time starting from the EOF" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM2EN" description="TIM2 base time enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 2 clock cycle counter not active." start="0x0" />
+        <Enum name="B_0x1" description="Timer 2 clock cycle counter active" start="0x1" />
+      </BitField>
+      <BitField name="TIM3VC" description="TIM3 base time linked to a virtual channel" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Virtual channel 0 used to generate the TIM3 event" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel 1 used to generate the TIM3 event" start="0x1" />
+        <Enum name="B_0x2" description="Virtual channel 2 used to generate the TIM3 event" start="0x2" />
+        <Enum name="B_0x3" description="Virtual channel 3 used to generate the TIM3 event" start="0x3" />
+      </BitField>
+      <BitField name="TIM3EOF" description="TIM3 base time starting from the EOF" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF selected as starting point for the counter" start="0x0" />
+        <Enum name="B_0x1" description="EOF selected as starting point for the counter" start="0x1" />
+      </BitField>
+      <BitField name="TIM3EN" description="TIM3 base time enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 3 clock cycle counter not active" start="0x0" />
+        <Enum name="B_0x1" description="Timer 3 clock cycle counter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_WDR" description="CSI-2 Host watchdog register" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Watchdog counter" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="CSI_IER0" description="CSI-2 Host interrupt enable register 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0IE" description="Line/byte counter 0 interrupt enable " start="0" size="1" access="Read/Write" />
+      <BitField name="LB1IE" description="Line/byte counter 1 interrupt enable " start="1" size="1" access="Read/Write" />
+      <BitField name="LB2IE" description="Line/byte counter 2 interrupt enable " start="2" size="1" access="Read/Write" />
+      <BitField name="LB3IE" description="Line/byte counter 3 interrupt enable " start="3" size="1" access="Read/Write" />
+      <BitField name="TIM0IE" description="Timer 0 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM1IE" description="Timer 1 interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM2IE" description="Timer 2 interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM3IE" description="Timer 3 interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timer 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timer 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF0IE" description="SOF for virtual channel 0 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF1IE" description="SOF for virtual channel 1 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="SOF2IE" description="SOF for virtual channel 2 interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOF3IE" description="SOF for virtual channel 3 interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SOF on virtual channel 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SOF on virtual channel 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF0IE" description="EOF for virtual channel 0 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF1IE" description="EOF for virtual channel 1 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF2IE" description="EOF for virtual channel 2 interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOF3IE" description="EOF for virtual channel 3 interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOF on virtual channel 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOF on virtual channel 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPKTIE" description="Short packet interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Short packet detection interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Short packet detection interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCFIFOFIE" description="Clock changer FIFO full interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on clock changer FIFO full detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on clock changer FIFO full detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCERRIE" description="CRC error interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on CRC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on CRC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECCERRIE" description="ECC error interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on ECC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on ECC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="CECCERRIE" description="Corrected ECC error interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on corrected ECC error detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on corrected ECC error detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDERRIE" description="Data type ID error interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on reception of reserved data type disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on reception of reserved data type enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPKTERRIE" description="Short packet error interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on short packet error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on short packet error enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDERRIE" description="Watchdog error interrupt enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on watchdog error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on watchdog error enabled" start="0x1" />
+      </BitField>
+      <BitField name="SYNCERRIE" description="Invalid synchronization error interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt on invalid synchronization error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt on invalid synchronization error enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_IER1" description="CSI-2 Host interrupt enable register 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESOTDL0IE" description="SOT error interrupt enable on lane 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 SOT interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 SOT interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTSYNCDL0IE" description="SOT synchronization interrupt error enable on lane 0" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 SOT synchronization interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 SOT synchronization interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="EESCDL0IE" description="D-PHY_RX lane 0 escape entry error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 unrecognized escape entry command interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 unrecognized escape entry command interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESYNCESCDL0IE" description="D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 low-power data transmission interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 low-power data transmission Interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECTRLDL0IE" description="D-PHY_RX lane 0 control error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 0 control error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 0 control error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTDL1IE" description="SOT error interrupt enable on lane 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 SOT interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 SOT interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESOTSYNCDL1IE" description="SOT synchronization interrupt error enable on lane 1" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 SOT synchronization interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 SOT synchronization interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="EESCDL1IE" description="D-PHY_RX lane 1 escape entry error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 unrecognized escape entry command interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 unrecognized escape entry command interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ESYNCESCDL1IE" description="D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 low-power data transmission interrupt error disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 low-power data transmission Interrupt error enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECTRLDL1IE" description="D-PHY_RX lane 1 control error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lane 1 control error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Lane 1 control error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_SR0" description="CSI-2 Host status register 0" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LB0F" description="Line/byte counter 0 flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="LB1F" description="Line/byte counter 1 flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="LB2F" description="Line/byte counter 2 flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="LB3F" description="Line/byte counter 3 flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TIM0F" description="Timer 0 flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TIM1F" description="Timer 1 flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TIM2F" description="Timer 2 flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="TIM3F" description="Timer 3 flag" start="7" size="1" access="ReadOnly" />
+      <BitField name="SOF0F" description="SOF flag for virtual channel 0" start="8" size="1" access="ReadOnly" />
+      <BitField name="SOF1F" description="SOF flag for virtual channel 1 " start="9" size="1" access="ReadOnly" />
+      <BitField name="SOF2F" description="SOF flag for virtual channel 2" start="10" size="1" access="ReadOnly" />
+      <BitField name="SOF3F" description="SOF flag for virtual channel 3 " start="11" size="1" access="ReadOnly" />
+      <BitField name="EOF0F" description="EOF flag for virtual channel 0 " start="12" size="1" access="ReadOnly" />
+      <BitField name="EOF1F" description="EOF flag for virtual channel 1 " start="13" size="1" access="ReadOnly" />
+      <BitField name="EOF2F" description="EOF flag for virtual channel 2 " start="14" size="1" access="ReadOnly" />
+      <BitField name="EOF3F" description="EOF flag for virtual channel 3 " start="15" size="1" access="ReadOnly" />
+      <BitField name="SPKTF" description="Short packet flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="VC0STATEF" description="Virtual channel 0 state flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC1STATEF" description="Virtual channel 1 state flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC2STATEF" description="Virtual channel 2 state flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="VC3STATEF" description="Virtual channel 3 state flag" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Virtual channel inactive" start="0x0" />
+        <Enum name="B_0x1" description="Virtual channel active" start="0x1" />
+      </BitField>
+      <BitField name="CCFIFOFF" description="Clock changer FIFO full flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="CRCERRF" description="CRC error flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ECCERRF" description="ECC error flag" start="25" size="1" access="ReadOnly" />
+      <BitField name="CECCERRF" description="Corrected ECC error flag" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDERRF" description="Data type ID error flag" start="27" size="1" access="ReadOnly" />
+      <BitField name="SPKTERRF" description="Short packet error flag" start="28" size="1" access="ReadOnly" />
+      <BitField name="WDERRF" description="Watchdog error flag" start="29" size="1" access="ReadOnly" />
+      <BitField name="SYNCERRF" description="Invalid synchronization error flag" start="30" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_SR1" description="CSI-2 Host status register 1" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESOTDL0F" description="SOT error flag on lane 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="ESOTSYNCDL0F" description="SOT synchronization error flag on lane 0" start="1" size="1" access="ReadOnly" />
+      <BitField name="EESCDL0F" description="D-PHY_RX lane 0 escape entry error flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="ESYNCESCDL0F" description="D-PHY_RX lane 0 low-power data transmission synchronization error flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="ECTRLDL0F" description="D-PHY_RX lane 0 control error flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ESOTDL1F" description="SOT error flag on lane 1" start="8" size="1" access="ReadOnly" />
+      <BitField name="ESOTSYNCDL1F" description="SOT synchronization error flag on lane 1" start="9" size="1" access="ReadOnly" />
+      <BitField name="EESCDL1F" description="D-PHY_RX lane 1 escape entry error flag" start="10" size="1" access="ReadOnly" />
+      <BitField name="ESYNCESCDL1F" description="D-PHY_RX lane 1 low-power data transmission synchronization error flag" start="11" size="1" access="ReadOnly" />
+      <BitField name="ECTRLDL1F" description="D-PHY_RX lane 1 control error flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ACTDL0F" description="D-PHY_RX lane 0 high-speed reception active" start="16" size="1" access="ReadOnly" />
+      <BitField name="SYNCDL0F" description="D-PHY_RX lane 0 receiver synchronization observed" start="17" size="1" access="ReadOnly" />
+      <BitField name="SKCALDL0F" description="D-PHY_RX lane 0 high-speed skew calibration" start="18" size="1" access="ReadOnly" />
+      <BitField name="STOPDL0F" description="D-PHY_RX receiver data lane 0 in stop state" start="19" size="1" access="ReadOnly" />
+      <BitField name="ULPNDL0F" description="D-PHY_RX receiver ultra-low-power state (not) active on data lane 0" start="20" size="1" access="ReadOnly" />
+      <BitField name="ACTDL1F" description="D-PHY_RX lane 1 high-speed reception active" start="22" size="1" access="ReadOnly" />
+      <BitField name="SYNCDL1F" description="D-PHY_RX lane 1 receiver synchronization observed" start="23" size="1" access="ReadOnly" />
+      <BitField name="SKCALDL1F" description="D-PHY_RX lane 1 high-speed skew calibration" start="24" size="1" access="ReadOnly" />
+      <BitField name="STOPDL1F" description="D-PHY_RX receiver data lane 1 in stop state" start="25" size="1" access="ReadOnly" />
+      <BitField name="ULPNDL1F" description="D-PHY_RX receiver ultra-low-power state (not) active on data lane 1" start="26" size="1" access="ReadOnly" />
+      <BitField name="STOPCLF" description="D-PHY_RX receiver in stop state for the clock lane" start="28" size="1" access="ReadOnly" />
+      <BitField name="ULPNACTF" description="D-PHY_RX receiver ULP state (not) active" start="29" size="1" access="ReadOnly" />
+      <BitField name="ULPNCLF" description="D-PHY_RX receiver Ultra-Low power state (not) on clock lane." start="30" size="1" access="ReadOnly" />
+      <BitField name="ACTCLF" description="D-PHY_RX receiver clock active flag" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_FCR0" description="CSI-2 Host flag clear register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLB0F" description="Clear line/byte counter 0 flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CLB1F" description="Clear line/byte counter 1 flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CLB2F" description="Clear line/byte counter 2 flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CLB3F" description="Clear line/byte counter 3 flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTIM0F" description="Clear timer 0 flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CTIM1F" description="Clear timer 1 flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CTIM2F" description="Clear timer 2 flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CTIM3F" description="Clear timer 3 flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="CSOF0F" description="Clear SOF flag for virtual channel 0 " start="8" size="1" access="WriteOnly" />
+      <BitField name="CSOF1F" description="Clear SOF flag for virtual channel 1 " start="9" size="1" access="WriteOnly" />
+      <BitField name="CSOF2F" description="Clear SOF flag for virtual channel 2" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSOF3F" description="Clear SOF flag for virtual channel 3 " start="11" size="1" access="WriteOnly" />
+      <BitField name="CEOF0F" description="Clear EOF flag for virtual channel 0 " start="12" size="1" access="WriteOnly" />
+      <BitField name="CEOF1F" description="Clear EOF flag for virtual channel 1 " start="13" size="1" access="WriteOnly" />
+      <BitField name="CEOF2F" description="Clear EOF flag for virtual channel 2 " start="14" size="1" access="WriteOnly" />
+      <BitField name="CEOF3F" description="Clear EOF flag for virtual channel 3 " start="15" size="1" access="WriteOnly" />
+      <BitField name="CSPKTF" description="Clear short packet flag" start="16" size="1" access="WriteOnly" />
+      <BitField name="CCCFIFOFF" description="Clear clock changer FIFO full flag" start="21" size="1" access="WriteOnly" />
+      <BitField name="CCRCERRF" description="Clear CRC error flag" start="24" size="1" access="WriteOnly" />
+      <BitField name="CECCERRF" description="Clear ECC error flag" start="25" size="1" access="WriteOnly" />
+      <BitField name="CCECCERRF" description="Clear corrected ECC error flag" start="26" size="1" access="WriteOnly" />
+      <BitField name="CIDERRF" description="Clear data type ID error flag" start="27" size="1" access="WriteOnly" />
+      <BitField name="CSPKTERRF" description="Clear short packet error flag" start="28" size="1" access="WriteOnly" />
+      <BitField name="CWDERRF" description="Clear watchdog error flag" start="29" size="1" access="WriteOnly" />
+      <BitField name="CSYNCERRF" description="Clear invalid synchronization error flag" start="30" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="CSI_FCR1" description="CSI-2 Host flag clear register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CESOTDL0F" description="Clear SOT error flag on lane 0" start="0" size="1" access="WriteOnly" />
+      <BitField name="CESOTSYNCDL0F" description="Clear SOT synchronization error flag on lane 0" start="1" size="1" access="WriteOnly" />
+      <BitField name="CEESCDL0F" description="Clear D-PHY_RX lane 0 escape entry error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CESYNCESCDL0F" description="Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CECTRLDL0F" description="Clear D-PHY_RX lane 0 control error flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CESOTDL1F" description="Clear SOT error flag on lane 1" start="8" size="1" access="WriteOnly" />
+      <BitField name="CESOTSYNCDL1F" description="Clear SOT synchronization error flag on lane 1" start="9" size="1" access="WriteOnly" />
+      <BitField name="CEESCDL1F" description="Clear D-PHY_RX lane 1 escape entry error flag" start="10" size="1" access="WriteOnly" />
+      <BitField name="CESYNCESCDL1F" description="Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="CECTRLDL1F" description="Clear D-PHY_RX lane 1 control error flag" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="CSI_SPDFR" description="CSI-2 Host short packet data field register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAFIELD" description="Data field " start="0" size="16" access="ReadOnly" />
+      <BitField name="DATATYPE" description="Data type class" start="16" size="6" access="ReadOnly" />
+      <BitField name="VCHANNEL" description="Virtual channel" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_ERR1" description="CSI-2 Host error register 1" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCDTERR" description="Data type having a CRC error" start="0" size="6" access="ReadOnly" />
+      <BitField name="CRCVCERR" description="Virtual channel having a CRC error" start="6" size="2" access="ReadOnly" />
+      <BitField name="CECCDTERR" description="Data type having a corrected ECC error" start="8" size="6" access="ReadOnly" />
+      <BitField name="CECCVCERR" description="Virtual channel having a corrected ECC error" start="14" size="2" access="ReadOnly" />
+      <BitField name="IDDTERR" description="Data type in error " start="16" size="6" access="ReadOnly" />
+      <BitField name="IDVCERR" description="Virtual channel having ID error" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_ERR2" description="CSI-2 Host error register 2" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPKTDTERR" description="Data type having a short packet error" start="0" size="6" access="ReadOnly" />
+      <BitField name="SPKTVCERR" description="Virtual channel having a short packet error" start="6" size="2" access="ReadOnly" />
+      <BitField name="WDVCERR" description="Virtual channel having a watchdog error" start="16" size="2" access="ReadOnly" />
+      <BitField name="SYNCVCERR" description="Virtual channel having synchronization error" start="18" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="CSI_PRCR" description="CSI PHY reset control register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEN" description="When set to 0, this bit places the digital section of the D-PHY in the reset state." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PHY is disabled (in reset state)." start="0x0" />
+        <Enum name="B_0x1" description="PHY is enabled (out of reset state)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PMCR" description="CSI PHY mode control register" start="+0x1004" size="4" reset_value="0x00011003" reset_mask="0xFFFFFFFF">
+      <BitField name="FRXMDL0" description="Force to Rx mode the data lane 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="FRXMDL1" description="Force to Rx mode the data lane 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTXSMDL0" description="Force to Tx Stop mode the data lane 0" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTDL" description="Disable turn-around data lane 0" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTDL0" description="Turn-around request data lane 0" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No request" start="0x0" />
+        <Enum name="B_0x1" description="Request for turn-around for DL0" start="0x1" />
+      </BitField>
+      <BitField name="TUESDL0" description="Tx ULP escape-mode data lane 0" start="12" size="1" access="Read/Write" />
+      <BitField name="TUEXDL0" description="Tx ULP exit sequence data lane 0" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CSI_PFCR" description="CSI PHY frequency control register" start="+0x1008" size="4" reset_value="0x00000017" reset_mask="0xFFFFFFFF">
+      <BitField name="CCFR" description="Configuration clock frequency range selection" start="0" size="6" access="Read/Write" />
+      <BitField name="HSFR" description="PHY high-speed frequency range selection" start="8" size="7" access="Read/Write" />
+      <BitField name="DLD" description="Data lane direction of lane 0" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx" start="0x0" />
+        <Enum name="B_0x1" description="Tx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PTCR0" description="CSI PHY test control register 0" start="+0x1010" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TCKEN" description="Test-interface clock enable for the TDI bus into the PHY" start="0" size="1" access="Read/Write" />
+      <BitField name="TRSEN" description="Test-interface reset enable for the TDI bus into the PHY" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CSI_PTCR1" description="CSI PHY test control register 1" start="+0x1014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDI" description="Test-interface data in" start="0" size="8" access="Read/Write" />
+      <BitField name="TWM" description="Test-interface write mode selector" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data write operation is set on the rising edge of the testclk signal." start="0x0" />
+        <Enum name="B_0x1" description="Address write operation is set on the falling edge of the testclk signal." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CSI_PTSR" description="CSI PHY test status register" start="+0x1018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDO" description="CSI PHY test interface data output bus for read-back and internal probing functionalities" start="0" size="8" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DBGMCU" description="Microcontroller debug unit" start="0x44001000">
+    <Register name="DBGMCU_IDCODE" description="DBGMCU identity code register" start="+0x000" size="4" reset_value="0x00006486" reset_mask="0x0000FFFF">
+      <BitField name="DEV_ID" description="Device ID" start="0" size="12" access="ReadOnly">
+        <Enum name="B_0x486" description="STM32N6xx" start="0x486" />
+      </BitField>
+      <BitField name="REV_ID" description="Revision" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DBGMCU_CR" description="DBGMCU configuration register" start="+0x004" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_SLEEP" description="Allow debug in Sleep mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. Peripheral clock are stopped automatically in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop disabled. Peripheral clock continues to run, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBG_STOP" description="Allow debug in Stop mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. All clocks are disabled automatically in Stop mode" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop disabled. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBG_STANDBY" description="Allow debug in Standby mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. All clocks are disabled and the Vless thansub&gt;DDless than/sub&gt; domain powered down automatically in Standby mode." start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop/power down disabled. All active clocks and oscillators continue to run during Standby mode, and the Vless thansub&gt;DDless than/sub&gt; domain supply is maintained, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBGCLKEN" description="Debug clock enable through software" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Debug clock is off." start="0x0" />
+        <Enum name="B_0x1" description="Debug clock is on." start="0x1" />
+      </BitField>
+      <BitField name="TRACECLKEN" description="TPIU export clock enable through software" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TPIU clock is off." start="0x0" />
+        <Enum name="B_0x1" description="TPIU clock is on." start="0x1" />
+      </BitField>
+      <BitField name="DBTRGOEN" description="DBTRGIO connection control" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBTRGIO connected to DBTRGIN" start="0x0" />
+        <Enum name="B_0x1" description="DBTRGIO connected to DBTRGOUT" start="0x1" />
+      </BitField>
+      <BitField name="HLT_TSGEN_EN" description="TSGEN halt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="TSGEN stops counting when processor is in halt." start="0x1" />
+        <Enum name="B_0x0" description="TSGEN keeps on counting when processor is in halt." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB1LFZ1" description="DBGMCU APB1L peripheral freeze register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM2_STOP" description="TIM2 stop in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM2 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM2 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM3_STOP" description="TIM3 stop in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM3 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM3 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM4_STOP" description="TIM4 stop in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM5_STOP" description="TIM5 stop in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM5 continues to operate while Cortex-M55 is in debug mod.e" start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM5 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM6_STOP" description="TIM6 stop in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM6 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM6 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM7_STOP" description="TIM7 stop in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM7 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM7 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM12_STOP" description="TIM12 stop in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM12 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM12 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM13_STOP" description="TIM13 stop in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM13 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM13 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM14_STOP" description="TIM14 stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM14 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM14 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM1_STOP" description="LPTIM1 stop in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_WWDG1_STOP" description="WWDG1 stop in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. WWDG1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. WWDG1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM10_STOP" description="TIM10 stop in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM10 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM10 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM11_STOP" description="TIM11 stop in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM11 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM11 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C1_STOP" description="I2C1 SMBUS timeout stop in debug" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C2_STOP" description="I2C2 SMBUS timeout stop in debug" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C3_STOP" description="I2C3 SMBUS timeout stop in debug" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C3 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C3 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I3C1_STOP" description="I3C1 SMBUS timeout stop in debug" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I3C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I3C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I3C2_STOP" description="I3C2 SMBUS timeout stop in debug" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I3C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I3C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB1HFZ1" description="DBGMCU APB1H peripheral freeze register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_FDCAN_STOP" description="FDCAN stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. FDCAN continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. FDCAN is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB2FZ1" description="DBGMCU APB2 peripheral freeze register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM1_STOP" description="TIM1 stop in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM8_STOP" description="TIM8 stop in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM8 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM8 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM18_STOP" description="TIM18 stop in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM18 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM18 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM15_STOP" description="TIM15 stop in debug" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM15 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM15 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM16_STOP" description="TIM16 stop in debug" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM16 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM16 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM17_STOP" description="TIM17 stop in debug" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM17 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM17 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM9_STOP" description="TIM9 stop in debug" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM9 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM9 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB4FZ1" description="DBGMCU APB4 peripheral freeze register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_I2C4_STOP" description="I2C4 stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM2_STOP" description="LPTIM2 stop in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM2 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM2 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM3_STOP" description="LPTIM3 stop in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM3 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM3 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM4_STOP" description="LPTIM4 stop in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM5_STOP" description="LPTIM5 stop in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM5 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM5 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_RTC_STOP" description="RTC clock is suspended in debug" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. Real time clock continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. Real time clock is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_IWDG_STOP" description="WWDG stop in debug" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. IWDG continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. IWDG is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB5FZ1" description="DBGMCU APB5 peripheral freeze register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_GFXTIM_STOP" description="GFXTIM stop in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GFX timer continues counting while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GFX timer is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_AHB1FZ1" description="DBGMCU AHB1 peripheral freeze register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_GPDMA1_CH0_STOP" description="GPDMA1_CHn suspend in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH1_STOP" description="GPDMA1_CHn suspend in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH2_STOP" description="GPDMA1_CHn suspend in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH3_STOP" description="GPDMA1_CHn suspend in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH4_STOP" description="GPDMA1_CHn suspend in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH5_STOP" description="GPDMA1_CHn suspend in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH6_STOP" description="GPDMA1_CHn suspend in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH7_STOP" description="GPDMA1_CHn suspend in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH8_STOP" description="GPDMA1_CHn suspend in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH9_STOP" description="GPDMA1_CHn suspend in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH10_STOP" description="GPDMA1_CHn suspend in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH11_STOP" description="GPDMA1_CHn suspend in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH12_STOP" description="GPDMA1_CHn suspend in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH13_STOP" description="GPDMA1_CHn suspend in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH14_STOP" description="GPDMA1_CHn suspend in debug" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH15_STOP" description="GPDMA1_CHn suspend in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_AHB5FZ1" description="DBGMCU AHB5 peripheral freeze register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_HPDMA1_CH0_STOP" description="HPDMA3_CHn suspend in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH1_STOP" description="HPDMA3_CHn suspend in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH2_STOP" description="HPDMA3_CHn suspend in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH3_STOP" description="HPDMA3_CHn suspend in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH4_STOP" description="HPDMA3_CHn suspend in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH5_STOP" description="HPDMA3_CHn suspend in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH6_STOP" description="HPDMA3_CHn suspend in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH7_STOP" description="HPDMA3_CHn suspend in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH8_STOP" description="HPDMA3_CHn suspend in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH9_STOP" description="HPDMA3_CHn suspend in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH10_STOP" description="HPDMA3_CHn suspend in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH11_STOP" description="HPDMA3_CHn suspend in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH12_STOP" description="HPDMA3_CHn suspend in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH13_STOP" description="HPDMA3_CHn suspend in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH14_STOP" description="HPDMA3_CHn suspend in debug" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH15_STOP" description="HPDMA3_CHn suspend in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="NPU_DBG_FREEZE" description="NPU stop in debug mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. The NPU continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. NPU is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_SR" description="DBGMCU status register" start="+0x0FC" size="4" reset_value="0x00010003" reset_mask="0xFFFFFFFF">
+      <BitField name="AP0_PRESENT" description="Access point 0 presence" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="AP present" start="0x1" />
+      </BitField>
+      <BitField name="AP1_PRESENT" description="Access point 1 presence" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="AP present" start="0x1" />
+      </BitField>
+      <BitField name="AP0_ENABLE" description="Access point 0 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Always enable" start="0x1" />
+      </BitField>
+      <BitField name="AP1_ENABLE" description="Access point 1 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="AP disabled (debug access locked)" start="0x0" />
+        <Enum name="B_0x1" description="AP enabled (debug access open)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_HOST" description="DBGMCU host authentication register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MESSAGE" description="Mailbox between debugger and processor" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_DEV" description="DBGMCU device authentication register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MESSAGE" description="Mailbox between debugger and processor" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_ACK" description="DBGMCU message read acknowledge authentication register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOST_ACK" description="Access status to DBG_AUTH_HOST register" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Debugger has written DBG_AUTH_HOST." start="0x1" />
+        <Enum name="B_0x0" description="Processor has read DBG_AUTH_HOST." start="0x0" />
+      </BitField>
+      <BitField name="DEVICE_ACK" description="Access status to DBG_AUTH_DEV register" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Processor has written DBG_AUTH_DEV." start="0x1" />
+        <Enum name="B_0x0" description="Debugger has read DBG_AUTH_DEV." start="0x0" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DBGMCU_S" description="Microcontroller debug unit" start="0x54001000">
+    <Register name="DBGMCU_IDCODE" description="DBGMCU identity code register" start="+0x000" size="4" reset_value="0x00006486" reset_mask="0x0000FFFF">
+      <BitField name="DEV_ID" description="Device ID" start="0" size="12" access="ReadOnly">
+        <Enum name="B_0x486" description="STM32N6xx" start="0x486" />
+      </BitField>
+      <BitField name="REV_ID" description="Revision" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DBGMCU_CR" description="DBGMCU configuration register" start="+0x004" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_SLEEP" description="Allow debug in Sleep mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. Peripheral clock are stopped automatically in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop disabled. Peripheral clock continues to run, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBG_STOP" description="Allow debug in Stop mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. All clocks are disabled automatically in Stop mode" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop disabled. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBG_STANDBY" description="Allow debug in Standby mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. All clocks are disabled and the Vless thansub&gt;DDless than/sub&gt; domain powered down automatically in Standby mode." start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock stop/power down disabled. All active clocks and oscillators continue to run during Standby mode, and the Vless thansub&gt;DDless than/sub&gt; domain supply is maintained, allowing full debug capability." start="0x1" />
+      </BitField>
+      <BitField name="DBGCLKEN" description="Debug clock enable through software" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Debug clock is off." start="0x0" />
+        <Enum name="B_0x1" description="Debug clock is on." start="0x1" />
+      </BitField>
+      <BitField name="TRACECLKEN" description="TPIU export clock enable through software" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TPIU clock is off." start="0x0" />
+        <Enum name="B_0x1" description="TPIU clock is on." start="0x1" />
+      </BitField>
+      <BitField name="DBTRGOEN" description="DBTRGIO connection control" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBTRGIO connected to DBTRGIN" start="0x0" />
+        <Enum name="B_0x1" description="DBTRGIO connected to DBTRGOUT" start="0x1" />
+      </BitField>
+      <BitField name="HLT_TSGEN_EN" description="TSGEN halt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="TSGEN stops counting when processor is in halt." start="0x1" />
+        <Enum name="B_0x0" description="TSGEN keeps on counting when processor is in halt." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB1LFZ1" description="DBGMCU APB1L peripheral freeze register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM2_STOP" description="TIM2 stop in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM2 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM2 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM3_STOP" description="TIM3 stop in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM3 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM3 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM4_STOP" description="TIM4 stop in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM5_STOP" description="TIM5 stop in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM5 continues to operate while Cortex-M55 is in debug mod.e" start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM5 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM6_STOP" description="TIM6 stop in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM6 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM6 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM7_STOP" description="TIM7 stop in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM7 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM7 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM12_STOP" description="TIM12 stop in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM12 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM12 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM13_STOP" description="TIM13 stop in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM13 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM13 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM14_STOP" description="TIM14 stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM14 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM14 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM1_STOP" description="LPTIM1 stop in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_WWDG1_STOP" description="WWDG1 stop in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. WWDG1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. WWDG1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM10_STOP" description="TIM10 stop in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM10 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM10 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM11_STOP" description="TIM11 stop in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM11 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM11 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C1_STOP" description="I2C1 SMBUS timeout stop in debug" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C2_STOP" description="I2C2 SMBUS timeout stop in debug" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I2C3_STOP" description="I2C3 SMBUS timeout stop in debug" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C3 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C3 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I3C1_STOP" description="I3C1 SMBUS timeout stop in debug" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I3C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I3C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_I3C2_STOP" description="I3C2 SMBUS timeout stop in debug" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I3C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I3C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB1HFZ1" description="DBGMCU APB1H peripheral freeze register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_FDCAN_STOP" description="FDCAN stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. FDCAN continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. FDCAN is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB2FZ1" description="DBGMCU APB2 peripheral freeze register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM1_STOP" description="TIM1 stop in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM1 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM1 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM8_STOP" description="TIM8 stop in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM8 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM8 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM18_STOP" description="TIM18 stop in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM18 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM18 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM15_STOP" description="TIM15 stop in debug" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM15 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM15 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM16_STOP" description="TIM16 stop in debug" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM16 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM16 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM17_STOP" description="TIM17 stop in debug" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM17 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM17 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_TIM9_STOP" description="TIM9 stop in debug" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. TIM9 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. TIM9 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB4FZ1" description="DBGMCU APB4 peripheral freeze register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_I2C4_STOP" description="I2C4 stop in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. I2C4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. I2C4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM2_STOP" description="LPTIM2 stop in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM2 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM2 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM3_STOP" description="LPTIM3 stop in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM3 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM3 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM4_STOP" description="LPTIM4 stop in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM4 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM4 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_LPTIM5_STOP" description="LPTIM5 stop in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. LPTIM5 continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. LPTIM5 is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_RTC_STOP" description="RTC clock is suspended in debug" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. Real time clock continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. Real time clock is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_IWDG_STOP" description="WWDG stop in debug" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. IWDG continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. IWDG is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_APB5FZ1" description="DBGMCU APB5 peripheral freeze register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_GFXTIM_STOP" description="GFXTIM stop in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GFX timer continues counting while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GFX timer is frozen while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_AHB1FZ1" description="DBGMCU AHB1 peripheral freeze register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_GPDMA1_CH0_STOP" description="GPDMA1_CHn suspend in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH1_STOP" description="GPDMA1_CHn suspend in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH2_STOP" description="GPDMA1_CHn suspend in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH3_STOP" description="GPDMA1_CHn suspend in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH4_STOP" description="GPDMA1_CHn suspend in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH5_STOP" description="GPDMA1_CHn suspend in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH6_STOP" description="GPDMA1_CHn suspend in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH7_STOP" description="GPDMA1_CHn suspend in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH8_STOP" description="GPDMA1_CHn suspend in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH9_STOP" description="GPDMA1_CHn suspend in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH10_STOP" description="GPDMA1_CHn suspend in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH11_STOP" description="GPDMA1_CHn suspend in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH12_STOP" description="GPDMA1_CHn suspend in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH13_STOP" description="GPDMA1_CHn suspend in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH14_STOP" description="GPDMA1_CHn suspend in debug" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_GPDMA1_CH15_STOP" description="GPDMA1_CHn suspend in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. GPDMA1_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. GPDMA1_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_AHB5FZ1" description="DBGMCU AHB5 peripheral freeze register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_HPDMA1_CH0_STOP" description="HPDMA3_CHn suspend in debug" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH1_STOP" description="HPDMA3_CHn suspend in debug" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH2_STOP" description="HPDMA3_CHn suspend in debug" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH3_STOP" description="HPDMA3_CHn suspend in debug" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH4_STOP" description="HPDMA3_CHn suspend in debug" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH5_STOP" description="HPDMA3_CHn suspend in debug" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH6_STOP" description="HPDMA3_CHn suspend in debug" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH7_STOP" description="HPDMA3_CHn suspend in debug" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH8_STOP" description="HPDMA3_CHn suspend in debug" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH9_STOP" description="HPDMA3_CHn suspend in debug" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH10_STOP" description="HPDMA3_CHn suspend in debug" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH11_STOP" description="HPDMA3_CHn suspend in debug" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH12_STOP" description="HPDMA3_CHn suspend in debug" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH13_STOP" description="HPDMA3_CHn suspend in debug" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH14_STOP" description="HPDMA3_CHn suspend in debug" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="DBG_HPDMA1_CH15_STOP" description="HPDMA3_CHn suspend in debug" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. HPDMA3_CHn continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. HPDMA3_CHn is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+      <BitField name="NPU_DBG_FREEZE" description="NPU stop in debug mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. The NPU continues to operate while Cortex-M55 is in debug mode." start="0x0" />
+        <Enum name="B_0x1" description="Stop in debug. NPU is suspended while Cortex-M55 is in debug mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_SR" description="DBGMCU status register" start="+0x0FC" size="4" reset_value="0x00010003" reset_mask="0xFFFFFFFF">
+      <BitField name="AP0_PRESENT" description="Access point 0 presence" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="AP present" start="0x1" />
+      </BitField>
+      <BitField name="AP1_PRESENT" description="Access point 1 presence" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="AP present" start="0x1" />
+      </BitField>
+      <BitField name="AP0_ENABLE" description="Access point 0 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Always enable" start="0x1" />
+      </BitField>
+      <BitField name="AP1_ENABLE" description="Access point 1 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="AP disabled (debug access locked)" start="0x0" />
+        <Enum name="B_0x1" description="AP enabled (debug access open)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_HOST" description="DBGMCU host authentication register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MESSAGE" description="Mailbox between debugger and processor" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_DEV" description="DBGMCU device authentication register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MESSAGE" description="Mailbox between debugger and processor" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DBGMCU_DBG_AUTH_ACK" description="DBGMCU message read acknowledge authentication register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOST_ACK" description="Access status to DBG_AUTH_HOST register" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Debugger has written DBG_AUTH_HOST." start="0x1" />
+        <Enum name="B_0x0" description="Processor has read DBG_AUTH_HOST." start="0x0" />
+      </BitField>
+      <BitField name="DEVICE_ACK" description="Access status to DBG_AUTH_DEV register" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Processor has written DBG_AUTH_DEV." start="0x1" />
+        <Enum name="B_0x0" description="Debugger has read DBG_AUTH_DEV." start="0x0" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DCMI" description="Digital camera interface" start="0x48028400">
+    <Register name="DCMI_CR" description="DCMI control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPTURE" description="Capture enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture enabled" start="0x1" />
+      </BitField>
+      <BitField name="CM" description="Capture mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CROP" description="Crop feature" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four." start="0x0" />
+        <Enum name="B_0x1" description="Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured." start="0x1" />
+      </BitField>
+      <BitField name="JPEG" description="JPEG format" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Uncompressed video format" start="0x0" />
+        <Enum name="B_0x1" description="This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode." start="0x1" />
+      </BitField>
+      <BitField name="ESS" description="Embedded synchronization select" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals." start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow." start="0x1" />
+      </BitField>
+      <BitField name="PCKPOL" description="Pixel clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active" start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="Horizontal synchronization polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI_HSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="DCMI_HSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="Vertical synchronization polarity" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI_VSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="DCMI_VSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="FCRC" description="Frame capture rate control" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured." start="0x0" />
+        <Enum name="B_0x1" description="Every alternate frame captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One frame out of four captured (75% bandwidth reduction)" start="0x2" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every pixel clock." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 10-bit data on every pixel clock." start="0x1" />
+        <Enum name="B_0x2" description="Interface captures 12-bit data on every pixel clock." start="0x2" />
+        <Enum name="B_0x3" description="Interface captures 14-bit data on every pixel clock." start="0x3" />
+      </BitField>
+      <BitField name="ENABLE" description="DCMI enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI disabled" start="0x0" />
+        <Enum name="B_0x1" description="DCMI enabled" start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Byte Select mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received data." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures every other byte from the received data." start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four." start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four." start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Odd/Even Byte Select (Byte Select Start)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first data (byte or double byte) from the frame/line start, second one being dropped." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second data (byte or double byte) from the frame/line start, first one being dropped." start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Line Select mode" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received lines." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two." start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Odd/Even Line Select (Line Select Start)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first line after the frame start, second one being dropped." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second line from the frame start, first one being dropped." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_SR" description="DCMI status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSYNC" description="Horizontal synchronization" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active line" start="0x0" />
+        <Enum name="B_0x1" description="synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="VSYNC" description="Vertical synchronization" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active frame" start="0x0" />
+        <Enum name="B_0x1" description="synchronization between frames" start="0x1" />
+      </BitField>
+      <BitField name="FNE" description="FIFO not empty" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO contains valid data." start="0x1" />
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_RIS" description="DCMI raw interrupt status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_RIS" description="Capture complete raw interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new capture" start="0x0" />
+        <Enum name="B_0x1" description="A frame has been captured." start="0x1" />
+      </BitField>
+      <BitField name="OVR_RIS" description="Overrun raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and the data FIFO is corrupted." start="0x1" />
+      </BitField>
+      <BitField name="ERR_RIS" description="Synchronization error raw interrupt status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_RIS" description="DCMI_VSYNC raw interrupt status" start="3" size="1" access="ReadOnly" />
+      <BitField name="LINE_RIS" description="Line raw interrupt status" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DCMI_IER" description="DCMI interrupt enable register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_IE" description="Capture complete interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated at the end of each received frame/crop window (in crop mode)." start="0x1" />
+      </BitField>
+      <BitField name="OVR_IE" description="Overrun interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+      <BitField name="ERR_IE" description="Synchronization error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_IE" description="DCMI_VSYNC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state." start="0x1" />
+      </BitField>
+      <BitField name="LINE_IE" description="Line interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated when a line has been completely received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_MIS" description="DCMI masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_MIS" description="Capture complete masked interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated after a complete capture." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="OVR_MIS" description="Overrun masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on overrun." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="ERR_MIS" description="Synchronization error masked interrupt status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on a synchronization error." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_MIS" description="VSYNC masked interrupt status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on DCMI_VSYNC transitions." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="LINE_MIS" description="Line masked interrupt status" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_ICR" description="DCMI interrupt clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_ISC" description="Capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="OVR_ISC" description="Overrun interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="ERR_ISC" description="Synchronization error interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="VSYNC_ISC" description="Vertical Synchronization interrupt status clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="LINE_ISC" description="line interrupt status clear" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMI_ESCR" description="DCMI embedded synchronization code register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSC" description="Frame start delimiter code" start="0" size="8" access="Read/Write" />
+      <BitField name="LSC" description="Line start delimiter code" start="8" size="8" access="Read/Write" />
+      <BitField name="LEC" description="Line end delimiter code" start="16" size="8" access="Read/Write" />
+      <BitField name="FEC" description="Frame end delimiter code" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMI_ESUR" description="DCMI embedded synchronization unmask register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSU" description="Frame start delimiter unmask" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the frame start delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the frame start delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="LSU" description="Line start delimiter unmask" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line start delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the line start delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="LEU" description="Line end delimiter unmask" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the line end delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="FEU" description="Frame end delimiter unmask" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the frame end delimiter with the received data." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_CWSTRT" description="DCMI crop window start" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFCNT" description="Horizontal offset count" start="0" size="14" access="Read/Write" />
+      <BitField name="VST" description="Vertical start line count" start="16" size="13" access="Read/Write">
+        <Enum name="B_0x0000" description="line 1" start="0x0000" />
+        <Enum name="B_0x0001" description="line 2" start="0x0001" />
+        <Enum name="B_0x0002" description="line 3" start="0x0002" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_CWSIZE" description="DCMI crop window size" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPCNT" description="Capture count" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="1 pixel" start="0x0000" />
+        <Enum name="B_0x0001" description="2 pixels" start="0x0001" />
+        <Enum name="B_0x0002" description="3 pixels" start="0x0002" />
+      </BitField>
+      <BitField name="VLINE" description="Vertical line count" start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="1 line" start="0x0000" />
+        <Enum name="B_0x0001" description="2 lines" start="0x0001" />
+        <Enum name="B_0x0002" description="3 lines" start="0x0002" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_DR" description="DCMI data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTE0" description="Data byte 0" start="0" size="8" access="ReadOnly" />
+      <BitField name="BYTE1" description="Data byte 1" start="8" size="8" access="ReadOnly" />
+      <BitField name="BYTE2" description="Data byte 2" start="16" size="8" access="ReadOnly" />
+      <BitField name="BYTE3" description="Data byte 3" start="24" size="8" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DCMI_S" description="Digital camera interface" start="0x58028400">
+    <Register name="DCMI_CR" description="DCMI control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPTURE" description="Capture enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture enabled" start="0x1" />
+      </BitField>
+      <BitField name="CM" description="Capture mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CROP" description="Crop feature" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four." start="0x0" />
+        <Enum name="B_0x1" description="Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured." start="0x1" />
+      </BitField>
+      <BitField name="JPEG" description="JPEG format" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Uncompressed video format" start="0x0" />
+        <Enum name="B_0x1" description="This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode." start="0x1" />
+      </BitField>
+      <BitField name="ESS" description="Embedded synchronization select" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals." start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow." start="0x1" />
+      </BitField>
+      <BitField name="PCKPOL" description="Pixel clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active" start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="Horizontal synchronization polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI_HSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="DCMI_HSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="Vertical synchronization polarity" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI_VSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="DCMI_VSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="FCRC" description="Frame capture rate control" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured." start="0x0" />
+        <Enum name="B_0x1" description="Every alternate frame captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One frame out of four captured (75% bandwidth reduction)" start="0x2" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every pixel clock." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 10-bit data on every pixel clock." start="0x1" />
+        <Enum name="B_0x2" description="Interface captures 12-bit data on every pixel clock." start="0x2" />
+        <Enum name="B_0x3" description="Interface captures 14-bit data on every pixel clock." start="0x3" />
+      </BitField>
+      <BitField name="ENABLE" description="DCMI enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI disabled" start="0x0" />
+        <Enum name="B_0x1" description="DCMI enabled" start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Byte Select mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received data." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures every other byte from the received data." start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four." start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four." start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Odd/Even Byte Select (Byte Select Start)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first data (byte or double byte) from the frame/line start, second one being dropped." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second data (byte or double byte) from the frame/line start, first one being dropped." start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Line Select mode" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received lines." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two." start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Odd/Even Line Select (Line Select Start)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first line after the frame start, second one being dropped." start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second line from the frame start, first one being dropped." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_SR" description="DCMI status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSYNC" description="Horizontal synchronization" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active line" start="0x0" />
+        <Enum name="B_0x1" description="synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="VSYNC" description="Vertical synchronization" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active frame" start="0x0" />
+        <Enum name="B_0x1" description="synchronization between frames" start="0x1" />
+      </BitField>
+      <BitField name="FNE" description="FIFO not empty" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO contains valid data." start="0x1" />
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_RIS" description="DCMI raw interrupt status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_RIS" description="Capture complete raw interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new capture" start="0x0" />
+        <Enum name="B_0x1" description="A frame has been captured." start="0x1" />
+      </BitField>
+      <BitField name="OVR_RIS" description="Overrun raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and the data FIFO is corrupted." start="0x1" />
+      </BitField>
+      <BitField name="ERR_RIS" description="Synchronization error raw interrupt status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_RIS" description="DCMI_VSYNC raw interrupt status" start="3" size="1" access="ReadOnly" />
+      <BitField name="LINE_RIS" description="Line raw interrupt status" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DCMI_IER" description="DCMI interrupt enable register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_IE" description="Capture complete interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated at the end of each received frame/crop window (in crop mode)." start="0x1" />
+      </BitField>
+      <BitField name="OVR_IE" description="Overrun interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+      <BitField name="ERR_IE" description="Synchronization error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_IE" description="DCMI_VSYNC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state." start="0x1" />
+      </BitField>
+      <BitField name="LINE_IE" description="Line interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated when a line has been completely received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_MIS" description="DCMI masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_MIS" description="Capture complete masked interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated after a complete capture." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="OVR_MIS" description="Overrun masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on overrun." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="ERR_MIS" description="Synchronization error masked interrupt status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on a synchronization error." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set." start="0x1" />
+      </BitField>
+      <BitField name="VSYNC_MIS" description="VSYNC masked interrupt status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated on DCMI_VSYNC transitions." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+      <BitField name="LINE_MIS" description="Line masked interrupt status" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_ICR" description="DCMI interrupt clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME_ISC" description="Capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="OVR_ISC" description="Overrun interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="ERR_ISC" description="Synchronization error interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="VSYNC_ISC" description="Vertical Synchronization interrupt status clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="LINE_ISC" description="line interrupt status clear" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMI_ESCR" description="DCMI embedded synchronization code register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSC" description="Frame start delimiter code" start="0" size="8" access="Read/Write" />
+      <BitField name="LSC" description="Line start delimiter code" start="8" size="8" access="Read/Write" />
+      <BitField name="LEC" description="Line end delimiter code" start="16" size="8" access="Read/Write" />
+      <BitField name="FEC" description="Frame end delimiter code" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMI_ESUR" description="DCMI embedded synchronization unmask register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSU" description="Frame start delimiter unmask" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the frame start delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the frame start delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="LSU" description="Line start delimiter unmask" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line start delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the line start delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="LEU" description="Line end delimiter unmask" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the line end delimiter with the received data." start="0x1" />
+      </BitField>
+      <BitField name="FEU" description="Frame end delimiter unmask" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the frame end delimiter with the received data." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_CWSTRT" description="DCMI crop window start" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFCNT" description="Horizontal offset count" start="0" size="14" access="Read/Write" />
+      <BitField name="VST" description="Vertical start line count" start="16" size="13" access="Read/Write">
+        <Enum name="B_0x0000" description="line 1" start="0x0000" />
+        <Enum name="B_0x0001" description="line 2" start="0x0001" />
+        <Enum name="B_0x0002" description="line 3" start="0x0002" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_CWSIZE" description="DCMI crop window size" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPCNT" description="Capture count" start="0" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="1 pixel" start="0x0000" />
+        <Enum name="B_0x0001" description="2 pixels" start="0x0001" />
+        <Enum name="B_0x0002" description="3 pixels" start="0x0002" />
+      </BitField>
+      <BitField name="VLINE" description="Vertical line count" start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="1 line" start="0x0000" />
+        <Enum name="B_0x0001" description="2 lines" start="0x0001" />
+        <Enum name="B_0x0002" description="3 lines" start="0x0002" />
+      </BitField>
+    </Register>
+    <Register name="DCMI_DR" description="DCMI data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTE0" description="Data byte 0" start="0" size="8" access="ReadOnly" />
+      <BitField name="BYTE1" description="Data byte 1" start="8" size="8" access="ReadOnly" />
+      <BitField name="BYTE2" description="Data byte 2" start="16" size="8" access="ReadOnly" />
+      <BitField name="BYTE3" description="Data byte 3" start="24" size="8" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DCMIPP" description="Digital camera interface pixel pipeline" start="0x48002000">
+    <Register name="DCMIPP_IPGR1" description="DCMIPP IPPLUG global register 1" start="+0x000" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMORYPAGE" description="Memory page size, as power of 2 of 64-byte units:" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+      </BitField>
+      <BitField name="QOS_MODE" description="Quality of service" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPGR2" description="DCMIPP IPPLUG global register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSTART" description="Request to lock the IP-Plug, to allow reconfiguration." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No lock requested, IP-Plug runs on demand by background HW." start="0x0" />
+        <Enum name="B_0x1" description="Lock requested: IP-Plug freezes shortly (see IDLE bit when lock is active)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPGR3" description="DCMIPP IPPLUG global register 3" start="+0x008" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLE" description="Status of IP-Plug" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="IP-Plug is running (on demand by background HW)" start="0x0" />
+        <Enum name="B_0x1" description="IP-Plug is currently locked and can be reconfigured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPGR8" description="DCMIPP IPPLUG identification register" start="+0x01C" size="4" reset_value="0xAA040314" reset_mask="0xFFFFFFFF">
+      <BitField name="DID" description="Division identifier (0x14)" start="0" size="6" access="ReadOnly" />
+      <BitField name="REVID" description="Revision identifier (0x03)" start="8" size="5" access="ReadOnly" />
+      <BitField name="ARCHIID" description="Architecture identifier (0x04)" start="16" size="5" access="ReadOnly" />
+      <BitField name="IPPID" description="IP identifier (0xAA)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_IPC1R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x20" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC1R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x24" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC1R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x28" size="4" reset_value="0x007F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC2R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x30" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC2R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x34" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC2R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x38" size="4" reset_value="0x013F0080" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC3R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x40" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC3R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x44" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC3R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x48" size="4" reset_value="0x018F0140" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC4R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x50" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC4R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x54" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC4R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x58" size="4" reset_value="0x01BF0190" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC5R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x60" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC5R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x64" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC5R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x68" size="4" reset_value="0x027F01C0" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_PRCR" description="DCMIPP parallel interface control register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESS" description="Embedded synchronization select" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals." start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow." start="0x1" />
+      </BitField>
+      <BitField name="PCKPOL" description="Pixel clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active" start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="Horizontal synchronization polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="HSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="Vertical synchronization polarity" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="VSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every pixel clock" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 10-bit data on every pixel clock" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures 12-bit data on every pixel clock" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures 14-bit data on every pixel clock" start="0x3" />
+        <Enum name="B_0x4" description="Interface captures 16-bit data on every pixel clock" start="0x4" />
+      </BitField>
+      <BitField name="ENABLE" description="Parallel interface enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parallel interface disabled to lower power consumption" start="0x0" />
+        <Enum name="B_0x1" description="Parallel interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="FORMAT" description="Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format)." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x1E" description="YUV422" start="0x1E" />
+        <Enum name="B_0x22" description="RGB565" start="0x22" />
+        <Enum name="B_0x24" description="RGB888 (= YUV444)" start="0x24" />
+        <Enum name="B_0x2A" description="RAW8" start="0x2A" />
+        <Enum name="B_0x2B" description="RAW10" start="0x2B" />
+        <Enum name="B_0x2C" description="RAW12" start="0x2C" />
+        <Enum name="B_0x2D" description="RAW14" start="0x2D" />
+        <Enum name="B_0x4A" description="monochrome 8-bit" start="0x4A" />
+        <Enum name="B_0x4B" description="monochrome 10-bit" start="0x4B" />
+        <Enum name="B_0x4C" description="monochrome 12-bit" start="0x4C" />
+        <Enum name="B_0x4D" description="monochrome 14-bit" start="0x4D" />
+        <Enum name="B_0x5A" description="byte stream (JPEG, compressed video)" start="0x5A" />
+      </BitField>
+      <BitField name="SWAPCYCLES" description="Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default" start="0x0" />
+        <Enum name="B_0x1" description="Swap active: the data of cycle 1 is used before the data of cycle 0." start="0x1" />
+      </BitField>
+      <BitField name="SWAPBITS" description="Swap LSB vs. MSB within each received component" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="As received" start="0x0" />
+        <Enum name="B_0x1" description="Swapped MSB vs. LSB" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRESCR" description="DCMIPP parallel interface embedded synchronization code register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSC" description="Frame start delimiter code" start="0" size="8" access="Read/Write" />
+      <BitField name="LSC" description="Line start delimiter code" start="8" size="8" access="Read/Write" />
+      <BitField name="LEC" description="Line end delimiter code" start="16" size="8" access="Read/Write" />
+      <BitField name="FEC" description="Frame end delimiter code" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_PRESUR" description="DCMIPP parallel interface embedded synchronization unmask register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSU" description="Frame start delimiter unmask" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FSC byte in DCMIPP_ESCR is masked while comparing the frame start delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FSC byte in DCMIPP_ESCR is compared while comparing the frame start delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="LSU" description="Line start delimiter unmask" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LSC byte in DCMIPP_ESCR is masked while comparing the line start delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LSC byte in DCMIPP_ESCR is compared while comparing the line start delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="LEU" description="Line end delimiter unmask" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LEC byte in DCMIPP_ESCR is masked while comparing the line end delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LEC byte in DCMIPP_ESCR is compared while comparing the line end delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="FEU" description="Frame end delimiter unmask" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FEC byte in DCMIPP_ESCR is masked while comparing the frame end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FEC byte in DCMIPP_ESCR is compared while comparing the frame end delimiter with the received data" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRIER" description="DCMIPP parallel interface interrupt enable register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERRIE" description="Synchronization error interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRSR" description="DCMIPP parallel interface status register" start="+0x1F8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERRF" description="Synchronization error raw interrupt status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="HSYNC" description="This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active line" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="VSYNC" description="This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active frame" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between frames" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRFCR" description="DCMIPP parallel interface interrupt clear register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CERRF" description="Synchronization error interrupt status clear" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_CMCR" description="DCMIPP common configuration register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSEL" description="input selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2" start="0x1" />
+      </BitField>
+      <BitField name="PSFC" description="Pipe selection for the frame counter" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Frame counter mapped to Pipe0" start="0x0" />
+        <Enum name="B_0x1" description="Frame counter mapped to Pipe1" start="0x1" />
+        <Enum name="B_0x2" description="Frame counter mapped to Pipe2" start="0x2" />
+      </BitField>
+      <BitField name="CFC" description="Clear frame counter" start="4" size="1" access="WriteOnly" />
+      <BitField name="SWAPRB" description="Swap R/U and B/V" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RGB/VYU" start="0x0" />
+        <Enum name="B_0x1" description="BGR/UYV" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMFRCR" description="DCMIPP common frame counter register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRMCNT" description="Frame counter, read-only, loops around." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_CMIER" description="DCMIPP common interrupt enable register" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATXERRIE" description="AXI transfer error interrupt enable for IPPLUG" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="PRERRIE" description="Limit interrupt enable for the parallel Interface" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0LINEIE" description="Multi-line capture complete interrupt enable for Pipe0" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0FRAMEIE" description="Frame capture complete interrupt enable for Pipe0" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0VSYNCIE" description="Vertical sync interrupt enable for Pipe0" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0LIMITIE" description="Limit interrupt enable for Pipe0" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0OVRIE" description="Overrun interrupt enable for Pipe0" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1LINEIE" description="Multi-line capture complete interrupt status clear for Pipe1" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1FRAMEIE" description="Frame capture complete interrupt enable for Pipe1" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1VSYNCIE" description="Vertical sync interrupt enable for Pipe1" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1OVRIE" description="Overrun interrupt enable for Pipe1" start="23" size="1" access="Read/Write" />
+      <BitField name="P2LINEIE" description="Multi-line capture complete interrupt enable for Pipe2" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2FRAMEIE" description="Frame capture complete interrupt enable for Pipe2" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2VSYNCIE" description="Vertical sync interrupt enable for Pipe2" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2OVRIE" description="Overrun interrupt status enable for Pipe2" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMSR1" description="DCMIPP common status register 1" start="+0x3F4" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="PRHSYNC" description="This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active line" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="PRVSYNC" description="This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active frame" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between frames" start="0x1" />
+      </BitField>
+      <BitField name="P0LSTLINE" description="Last line LSB bit, sampled at Frame capture complete event for Pipe0" start="8" size="1" access="ReadOnly" />
+      <BitField name="P0LSTFRM" description="Last frame LSB bit, sampled at Frame capture complete event for Pipe0" start="9" size="1" access="ReadOnly" />
+      <BitField name="P0CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe0" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+      <BitField name="P1LSTLINE" description="Last line LSB bit, sampled at Frame capture complete event for Pipe1" start="16" size="1" access="ReadOnly" />
+      <BitField name="P1LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event for Pipe1" start="17" size="1" access="ReadOnly" />
+      <BitField name="P1CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe1" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+      <BitField name="P2LSTLINE" description="Last line LSB bit, sampled at frame capture complete event for Pipe2" start="24" size="1" access="ReadOnly" />
+      <BitField name="P2LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event for Pipe2" start="25" size="1" access="ReadOnly" />
+      <BitField name="P2CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe2" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMSR2" description="DCMIPP common status register 2" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATXERRF" description="AXI transfer error interrupt status flag for the IPPLUG." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No AXI transfer error detected" start="0x0" />
+        <Enum name="B_0x1" description="AXI transfer error occurred on an AXI client. This bit signals an error on a client without any specific hardware action, the software must handle the situation (normally used when debugging software application code)." start="0x1" />
+      </BitField>
+      <BitField name="PRERRF" description="Synchronization error raw interrupt status for the parallel interface." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="P0LINEF" description="Multi-line capture completed raw interrupt status for Pipe0" start="8" size="1" access="ReadOnly" />
+      <BitField name="P0FRAMEF" description="Frame capture completed raw interrupt status for Pipe0" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P0VSYNCF" description="VSYNC raw interrupt status for Pipe0" start="10" size="1" access="ReadOnly" />
+      <BitField name="P0LIMITF" description="Limit raw interrupt status for Pipe0" start="14" size="1" access="ReadOnly" />
+      <BitField name="P0OVRF" description="Overrun raw interrupt status for Pipe0" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="P1LINEF" description="Multi-line capture completed raw interrupt status for Pipe1" start="16" size="1" access="ReadOnly" />
+      <BitField name="P1FRAMEF" description="Frame capture completed raw interrupt status for Pipe1" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P1VSYNCF" description="VSYNC raw interrupt status for Pipe1" start="18" size="1" access="ReadOnly" />
+      <BitField name="P1OVRF" description="Overrun raw interrupt status for Pipe1" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="P2LINEF" description="Multi-line capture completed raw interrupt status for Pipe2" start="24" size="1" access="ReadOnly" />
+      <BitField name="P2FRAMEF" description="Frame capture completed raw interrupt status for Pipe2" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P2VSYNCF" description="VSYNC raw interrupt status for Pipe2" start="26" size="1" access="ReadOnly" />
+      <BitField name="P2OVRF" description="Overrun raw interrupt status for Pipe2" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMFCR" description="DCMIPP common interrupt clear register" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CATXERRF" description="AXI transfer error interrupt status clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="CPRERRF" description="Synchronization error interrupt status clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CP0LINEF" description="Multi-line capture complete interrupt status clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="CP0FRAMEF" description="Frame capture complete interrupt status clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="CP0VSYNCF" description="Vertical synchronization interrupt status clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="CP0LIMITF" description="limit interrupt status clear" start="14" size="1" access="WriteOnly" />
+      <BitField name="CP0OVRF" description="Overrun interrupt status clear" start="15" size="1" access="WriteOnly" />
+      <BitField name="CP1LINEF" description="Multi-line capture complete interrupt status clear" start="16" size="1" access="WriteOnly" />
+      <BitField name="CP1FRAMEF" description="Frame capture complete interrupt status clear" start="17" size="1" access="WriteOnly" />
+      <BitField name="CP1VSYNCF" description="Vertical synchronization interrupt status clear" start="18" size="1" access="WriteOnly" />
+      <BitField name="CP1OVRF" description="Overrun interrupt status clear" start="23" size="1" access="WriteOnly" />
+      <BitField name="CP2LINEF" description="Multi-line capture complete interrupt status clear" start="24" size="1" access="WriteOnly" />
+      <BitField name="CP2FRAMEF" description="Frame capture complete interrupt status clear" start="25" size="1" access="WriteOnly" />
+      <BitField name="CP2VSYNCF" description="Vertical synchronization interrupt status clear" start="26" size="1" access="WriteOnly" />
+      <BitField name="CP2OVRF" description="Overrun interrupt status clear" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P0FSCR" description="DCMIPP Pipe0 flow selection configuration register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type selection ID A" start="0" size="6" access="Read/Write" />
+      <BitField name="DTIDB" description="Data type selection ID B" start="8" size="6" access="Read/Write" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe" start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe" start="0x1" />
+        <Enum name="B_0x2" description="All data types from the selected virtual channel (except the DTIDA or DTIDB) are forwarded in the pipe" start="0x2" />
+        <Enum name="B_0x3" description="All data types of the selected virtual channel VC are forwarded in the pipe" start="0x3" />
+      </BitField>
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0FCTCR" description="DCMIPP Pipe0 flow control configuration register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame, and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0SCSTR" description="DCMIPP Pipe0 stat/crop start register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 words wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0SCSZR" description="DCMIPP Pipe0 stat/crop size register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 word wide (data 32-bit)" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="POSNEG" description="This bit is set and cleared by software. It has a meaning only if ENABLE bit is set." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Positive area, the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART" start="0x0" />
+        <Enum name="B_0x1" description="Negative area, the area excluding the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART" start="0x1" />
+      </BitField>
+      <BitField name="ENABLE" description="This bit is set and cleared by software." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass. All the data are computed, if the statistic data are sent within the frame, they are sent to the processing pipe as pixels data." start="0x0" />
+        <Enum name="B_0x1" description="Enable. Depending on bit POSNEG value, the rectangle defined by VSIZE, HSIZE, VSTART and HSTART can be used to extract or to remove some data (statistical extraction or removal, or basic 2D crop features)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0DCCNTR" description="DCMIPP Pipe0 dump counter register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Number of data dumped during the frame." start="0" size="26" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0DCLMTR" description="DCMIPP Pipe0 dump limit register" start="+0x5B4" size="4" reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="LIMIT" description="Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation." start="0" size="24" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled, no check on the amount of 32-bit words transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enabled, check done versus limit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0PPCR" description="DCMIPP Pipe0 pixel packer configuration register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWAPYUV" description="Swaps, within a 32-bit word, byte 0-vs-1 and byte 2-vs-3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Outputs the provided words, as described in Section 34.10: Pixel format description." start="0x0" />
+        <Enum name="B_0x1" description="Swaps the bytes from provided words, byte 0-vs.-1 and 2-vs.-3" start="0x1" />
+      </BitField>
+      <BitField name="PAD" description="Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Aligns on LSB (and pads null bits on MSB), for backward compatibility with former DCMI." start="0x0" />
+        <Enum name="B_0x1" description="Aligns on MSB (and pads null bits on LSB), for better ease of software or GPU." start="0x1" />
+      </BitField>
+      <BitField name="HEADEREN" description="CSI header dump enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI-2 headers are not dumped" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 headers are dumped as a 32-bit word." start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Byte select mode" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received data" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 1 data out of 2" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four" start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Odd/even byte select (byte select start)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures the first data (byte or double byte) from the frame/line start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second data (byte or double byte) from the frame/line start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Line select mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received lines" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two" start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Odd/even line select (line select start)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first line after the frame start, second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second line from the frame start, first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe0 always dumps to memory address set by DCMIPP_P0PPM0AR1." start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P0PPM0AR1 to DCMIPP_P0PPM0AR2 alternatively on each frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0PPM0AR1" description="DCMIPP Pipe0 pixel packer Memory0 address register 1" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0PPM0AR2" description="DCMIPP Pipe0 pixel packer Memory0 address register 2" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0STM0AR" description="DCMIPP Pipe0 status Memory0 address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0IER" description="DCMIPP Pipe0 interrupt enable register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="LIMITIE" description="Limit interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the limit is reached" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when the limit is reached" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0SR" description="DCMIPP Pipe0 status register" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="LIMITF" description="Limit raw interrupt status" start="6" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number that can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0FCR" description="DCMIPP Pipe0 interrupt clear register" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="CLIMITF" description="limit interrupt status clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CFSCR" description="DCMIPP Pipe0 current flow selection configuration register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type selection ID A" start="0" size="6" access="ReadOnly" />
+      <BitField name="DTIDB" description="Current data type selection ID B" start="8" size="6" access="ReadOnly" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe." start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe." start="0x1" />
+        <Enum name="B_0x2" description="All Datatypes from the selected virtual channel, except the DTIDA or DTIDB are forwarded into the pipe." start="0x2" />
+        <Enum name="B_0x3" description="All Datatypes of the selected virtual channel VC are forwarded in the pipe." start="0x3" />
+      </BitField>
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CFCTCR" description="DCMIPP Pipe0 current flow control configuration register" start="+0x700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame, and then transfers a single frame through the AXI master. At the end of the frame the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CSCSTR" description="DCMIPP Pipe0 current stat/crop start register" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 words wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CSCSZR" description="DCMIPP Pipe0 current stat/crop size register" start="+0x708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 word wide (data 32-bit)." start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high." start="16" size="12" access="ReadOnly" />
+      <BitField name="POSNEG" description="Current value of the POSNEG bit" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Positive area. The rectangle defined by VSIZE,HSIZE, and VSTART, HSTART is the active area." start="0x0" />
+        <Enum name="B_0x1" description="Negative area. The active area is the area excluding the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART." start="0x1" />
+      </BitField>
+      <BitField name="ENABLE" description="Current value of the ENABLE bit" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass. All data are computed, if the statistics data are sent within the frame, they are sent to the processing pipe as pixels data." start="0x0" />
+        <Enum name="B_0x1" description="Enable: Depending on bit POSNEG value, the rectangle defined by the VSIZE, HSIZE, VSTART, HSTART can be used to extract or to remove certain amount of data (statistical extraction or removal, or basic 2D crop features)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CPPCR" description="DCMIPP Pipe0 current pixel packer configuration register" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWAPYUV" description="Swaps, within a 32-bit word, byte 0 vs. 1 and byte 2 vs. 3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Outputs the provided words, as described in Section 34.10: Pixel format description." start="0x0" />
+        <Enum name="B_0x1" description="Swaps the bytes from provided words, byte 0 vs. 1 and 2 vs. 3." start="0x1" />
+      </BitField>
+      <BitField name="PAD" description="Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Aligns on LSB (and pads null bits on MSB), for backward compatibility with former DCMI" start="0x0" />
+        <Enum name="B_0x1" description="Aligns on MSB (and pads null bits on LSB), for better ease of software or GPU" start="0x1" />
+      </BitField>
+      <BitField name="HEADEREN" description="Current CSI header dump enable" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CSI-2 headers are not dumped." start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 headers are dumped as a 32-bit words." start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Current Byte select mode" start="7" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures all received data" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one data out of two" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four" start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Current odd/even byte select (byte select start)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures the first data (byte or double byte) from the frame/line start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second data (byte or double byte) from the frame/line start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Current Line select mode" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures all received lines" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two" start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Current odd/even line select (ine select start)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures the first line after the frame start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second line from the frame start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Current amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe0 is always dump to memory address set by DCMIPP_P0PPM0AR1 register" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P0PPM0AR1 register to DCMIPP_P0PPM0AR2 register alternatively on each frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CPPM0AR1" description="DCMIPP Pipe0 current pixel packer Memory0 address register 1" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CPPM0AR2" description="DCMIPP Pipe0 current pixel packer Memory0 address register 2" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1FSCR" description="DCMIPP Pipe1 flow selection configuration register" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type selection ID A" start="0" size="6" access="Read/Write" />
+      <BitField name="DTIDB" description="Data type selection ID B" start="8" size="6" access="Read/Write" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe" start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe" start="0x1" />
+      </BitField>
+      <BitField name="PIPEDIFF" description="Differentiates Pipe2 from Pipe1" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe2 receives the same data as Pipe1 (Ie data filtered by Pipe1 configuration for VC and DTIDA/DTIDB and DTMODE mode, as well as FDTF and FDTFEN bit)." start="0x0" />
+        <Enum name="B_0x1" description="Pipe1 gets pixels from only VC and DT configured in Pipe1, processed by all block belonging to the image processing functional block (ie, demosaicing, auto exposure, statistics, contrast enhancement)." start="0x1" />
+      </BitField>
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="FDTF" description="Force Datatype format." start="24" size="6" access="Read/Write" />
+      <BitField name="FDTFEN" description="Force Datatype format enable." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable force Datatype format. The Datatype format used by the pipe is the one defined into DTIDx1: Enable force Datatype format. When the Datatype DTIDx is detected by the pipe, the real pixel format considered by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 Host. It allows to handle, for instance, 3D sensors camera using user data type in bottom-up approach, and to explicitly define the pixel format to be handled by the pipe. Note that the flow is first selected using the DTMODE and DTIDA/B, and then, if selected, its data type may be forced with the to FDTC using FDTFEN = 1." start="0x0" />
+      </BitField>
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1SRCR" description="DCMIPP Pipe1 stat removal configuration register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LASTLINE" description="Amount of following lines to keep when CROPEN = 1. If LASTLINE = 0 all pixels after FIRSTLINEDEL are fed through." start="0" size="12" access="Read/Write" />
+      <BitField name="FIRSTLINEDEL" description="Amount of first lines to delete when CROPEN = 1" start="12" size="3" access="Read/Write" />
+      <BitField name="CROPEN" description="Crop line enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No crop (all pixels are fed through)" start="0x0" />
+        <Enum name="B_0x1" description="Crop" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BPRCR" description="DCMIPP Pipe1 bad pixel removal control register" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: bad pixel removal is not active, all pixels are transmitted through" start="0x0" />
+        <Enum name="B_0x1" description="Enable: if bad pixel are detected, they are replaced by corrected pixels" start="0x1" />
+      </BitField>
+      <BitField name="STRENGTH" description="Strength (aggressiveness) of the bad pixel detection" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="The filter is fairly tolerant: only a few pixels are declared bad, due to their high noise" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BPRSR" description="DCMIPP Pipe1 bad pixel removal status register" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADCNT" description="Amount of detected bad pixels" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1DECR" description="DCMIPP Pipe1 decimation register" start="+0x830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted (for raw Bayer data, two lines of components every four)" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted (for raw Bayer data, two lines of components every four)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BLCCR" description="DCMIPP Pipe1 black level calibration control register" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Black level calibration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: black level calibration is not active, all pixels are transmitted non-modified." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the BLC R, G, B are subtracted." start="0x1" />
+      </BitField>
+      <BitField name="BLCB" description="Black level calibration - Blue" start="8" size="8" access="Read/Write" />
+      <BitField name="BLCG" description="Black level calibration - Green" start="16" size="8" access="Read/Write" />
+      <BitField name="BLCR" description="Black level calibration - Red" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1EXCR1" description="DCMIPP Pipe1 exposure control register 1" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Exposure control (multiplication and shift) of all red, green and blue" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: exposure multiplier and shift are not applied" start="0x0" />
+        <Enum name="B_0x1" description="Enable: the exposure multiplication and shift is applied" start="0x1" />
+      </BitField>
+      <BitField name="MULTR" description="Exposure multiplier - Red" start="20" size="8" access="Read/Write" />
+      <BitField name="SHFR" description="Exposure shift - Red" start="28" size="3" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1EXCR2" description="DCMIPP Pipe1 exposure control register 2" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MULTB" description="Exposure multiplier - Blue" start="4" size="8" access="Read/Write" />
+      <BitField name="SHFB" description="Exposure shift - Blue" start="12" size="3" access="Read/Write" />
+      <BitField name="MULTG" description="Exposure multiplier - Green" start="20" size="8" access="Read/Write" />
+      <BitField name="SHFG" description="Exposure shift - Green" start="28" size="3" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1ST1CR" description="DCMIPP Pipe1 statistics1 control register" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All Pixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST2CR" description="DCMIPP Pipe1 statistics 2 control register" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated" start="0x0" />
+        <Enum name="B_0x1" description="Enabled: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240." start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST3CR" description="DCMIPP Pipe1 statistics 3 control register" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated" start="0x0" />
+        <Enum name="B_0x1" description="Enabled: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240." start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1STSTR" description="DCMIPP Pipe1 statistics window start register" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STSZR" description="DCMIPP Pipe1 statistics window size register" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CROPEN" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are used to compute the statistics" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSTART, HSTART, VSIZE, HSIZE is used for statistics." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST1SR" description="DCMIPP Pipe1 statistics 1 status register" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1ST2SR" description="DCMIPP Pipe1 statistics 2 status register" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1ST3SR" description="DCMIPP Pipe1 statistics 3 status register" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1DMCR" description="DCMIPP Pipe1 demosaicing configuration register" start="+0x870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass" start="0x0" />
+        <Enum name="B_0x1" description="Enable demosaicing" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Raw Bayer type" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="RGGB" start="0x0" />
+        <Enum name="B_0x1" description="GRBG" start="0x1" />
+        <Enum name="B_0x2" description="GBRG" start="0x2" />
+        <Enum name="B_0x3" description="BGGR" start="0x3" />
+      </BitField>
+      <BitField name="PEAK" description="Strength of the peak detection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No peak detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="LINEV" description="Strength of the vertical line detection" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No vertical line detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="LINEH" description="Strength of the horizontal line detection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No horizontal line detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="EDGE" description="Strength of the edge detection" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No edge detection, pure linear interpolation" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCR" description="DCMIPP Pipe1 ColorConv configuration register" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="output samples type used while CLAMP is activated" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="Clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCRR1" description="DCMIPP Pipe1 ColorConv red coefficient register 1" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Coefficient row 1 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RG" description="Coefficient row 1 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCRR2" description="DCMIPP Pipe1 ColorConv red coefficient register 2" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Coefficient row 1 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RA" description="Coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCGR1" description="DCMIPP Pipe1 ColorConv green coefficient register 1" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Coefficient row 2 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GG" description="Coefficient row 2 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCGR2" description="DCMIPP Pipe1 ColorConv green coefficient register 2" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Coefficient row 2 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GA" description="Coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCBR1" description="DCMIPP Pipex ColorConv blue coefficient register 1" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Coefficient row 3 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BG" description="Coefficient row 3 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCBR2" description="DCMIPP Pipe1 ColorConv blue coefficient register 2" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Coefficient row 3 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BA" description="Coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR1" description="DCMIPP Pipe1 contrast control register 1" start="+0x8A0" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, pixels are forwarded idle." start="0x0" />
+        <Enum name="B_0x1" description="Enable, contrast enhancement is applied on pixels." start="0x1" />
+      </BitField>
+      <BitField name="LUM0" description="Luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR2" description="DCMIPP Pipe1 contrast control register 2" start="+0x8A4" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM4" description="Luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" start="1" size="6" access="Read/Write" />
+      <BitField name="LUM3" description="Luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+      <BitField name="LUM2" description="Luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" start="17" size="6" access="Read/Write" />
+      <BitField name="LUM1" description="Luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" start="25" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR3" description="DCMIPP Pipe1 contrast control register 3" start="+0x8A8" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM8" description="Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" start="1" size="6" access="Read/Write" />
+      <BitField name="LUM7" description="Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+      <BitField name="LUM6" description="Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" start="17" size="6" access="Read/Write" />
+      <BitField name="LUM5" description="Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" start="25" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1FCTCR" description="DCMIPP Pipex flow control configuration register" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode. The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame). Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CRSTR" description="DCMIPP Pipex crop window start register" start="+0x904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CRSZR" description="DCMIPP Pipex crop window size register" start="+0x908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="16" size="12" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DCCR" description="DCMIPP Pipex decimation register" start="+0x90C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DSCR" description="DCMIPP Pipex downsize configuration register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="Read/Write" />
+      <BitField name="VDIV" description="Vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DSRTIOR" description="DCMIPP Pipex downsize ratio register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="Read/Write" />
+      <BitField name="VRATIO" description="Vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1DSSZR" description="DCMIPP Pipex downsize destination size register" start="+0x918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CMRICR" description="DCMIPP Pipex common ROI configuration register" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Region of interest line size width" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Region of interest 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Region of interest 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Region of interest 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Region of interest 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Region of interest 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Region of interest 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Region of interest 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Region of interest 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1RI1CR1" description="DCMIPP Pipe1 ROI1 configuration register 1" start="+0x924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI1CR2" description="DCMIPP Pipe1 ROI1 configuration register 2" start="+0x928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI2CR1" description="DCMIPP Pipe1 ROI2 configuration register 1" start="+0x92C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI2CR2" description="DCMIPP Pipe1 ROI2 configuration register 2" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI3CR1" description="DCMIPP Pipe1 ROI3 configuration register 1" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI3CR2" description="DCMIPP Pipe1 ROI3 configuration register 2" start="+0x938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI4CR1" description="DCMIPP Pipe1 ROI4 configuration register 1" start="+0x93C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI4CR2" description="DCMIPP Pipe1 ROI4 configuration register 2" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI5CR1" description="DCMIPP Pipe1 ROI5 configuration register 1" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI5CR2" description="DCMIPP Pipe1 ROI5 configuration register 2" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI6CR1" description="DCMIPP Pipe1 ROI6 configuration register 1" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI6CR2" description="DCMIPP Pipe1 ROI6 configuration register 2" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI7CR1" description="DCMIPP Pipe1 ROI7 configuration register 1" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI7CR2" description="DCMIPP Pipe1 ROI7 configuration register 2" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI8CR1" description="DCMIPP Pipe1 ROI8 configuration register 1" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI8CR2" description="DCMIPP Pipe1 ROI8 configuration register 2" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1GMCR" description="DCMIPP Pipex gamma configuration register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Gamma is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1YUVCR" description="DCMIPP Pipe1 YUVConv configuration register" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Output samples type used while CLAMP is activated" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="Clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1YUVRR1" description="DCMIPP Pipe1 YUVConv red coefficient register 1" start="+0x984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Coefficient row 1 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RG" description="Coefficient row 1 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVRR2" description="DCMIPP Pipe1 YUVConv red coefficient register 2" start="+0x988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Coefficient row 1 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RA" description="Coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVGR1" description="DCMIPP Pipe1 YUVConv green coefficient register 1" start="+0x98C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Coefficient row 2 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GG" description="Coefficient row 2 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVGR2" description="DCMIPP Pipe1 YUVConv green coefficient register 2" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Coefficient row 2 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GA" description="Coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVBR1" description="DCMIPP Pipe1 YUVConv blue coefficient register 1" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Coefficient row 3 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BG" description="Coefficient row 3 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVBR2" description="DCMIPP Pipe1 YUV blue coefficient register 2" start="+0x998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Coefficient row 3 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BA" description="Coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPCR" description="DCMIPP Pipe1 pixel packer configuration register" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="RGB888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888 (with A = 0xFF)" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888 (with A = 0xFF)" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (32 bpp, FOURCC = AYUV, with A = 0xFF)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (16 bpp, FOURCC = YUYV)" start="0x6" />
+        <Enum name="B_0x7" description="YUV422 2-buffer (16 bpp, FOURCC = none)" start="0x7" />
+        <Enum name="B_0x8" description="YUV420 2-buffer (12 bpp, FOURCC = NV21), NV12 available with SWAPRB = 1" start="0x8" />
+        <Enum name="B_0x9" description="YUV420 3-buffer (12 bpp, FOURCC = YV12)" start="0x9" />
+        <Enum name="B_0xA" description="YUV422 1-buffer (16 bpp, FOURCC = UYVY)" start="0xA" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and U-vs-V components if YUV" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE Event and Interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe1 always drains out the pixels to memory address set by DCMIPP_P1PPM0AR1, and DCMIPP_P1PPM1AR1 as well as DCMIPP_P1PPM2AR1 in case of semi-planar or multi-planar buffer configuration" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Output pixels address location switches from DCMIPP_P1PPM0AR1 to DCMIPP_P1PPM0AR2 alternatively on each frame. For the semi- and multi-planar operations, the output pixels switches from/to DCMIPP_P1PPM1AR1 to/from DCMIPP_P1PPM1AR2. Memory buffer switches from/to DCMIPP_P1PPM2AR1 to/from DCMIPP_P1PPM2AR2 for multi-planar operations." start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo. " start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit. " start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1PPM0AR1" description="DCMIPP Pipe1 pixel packer Memory0 address register 1" start="+0x9C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM0AR2" description="DCMIPP Pipe1 pixel packer Memory0 address register 2" start="+0x9C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM0PR" description="DCMIPP Pipex pixel packer Memory0 pitch register" start="+0x9CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM0AR" description="DCMIPP Pipex status Memory0 address register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1AR1" description="DCMIPP Pipex pixel packer Memory1 address register 1" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1AR2" description="DCMIPP Pipex pixel packer Memory1 address register 2" start="+0x9D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1PR" description="DCMIPP Pipex pixel packer Memory1 pitch register" start="+0x9DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM1AR" description="DCMIPP Pipex status Memory1 address register" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1PPM2AR1" description="DCMIPP Pipex pixel packer memory2 address register 1" start="+0x9E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM2AR2" description="DCMIPP Pipex pixel packer memory2 address register 2" start="+0x9E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM2AR" description="DCMIPP Pipex status Memory2 address register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1IER" description="DCMIPP Pipe1 interrupt enable register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1SR" description="DCMIPP Pipe1 status register" start="+0x9F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured." start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted." start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number, which can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1FCR" description="DCMIPP Pipe1 interrupt clear register" start="+0x9FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CFSCR" description="DCMIPP Pipe1 current flow selection configuration register" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type ID A" start="0" size="6" access="ReadOnly" />
+      <BitField name="DTIDB" description="Current data type ID B" start="8" size="6" access="ReadOnly" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Only flow DTID A from the selected virtual channel is forwarded in the pipe." start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and DTIDB from the selected virtual channel are forwarded in the pipe. This combination is valid only if the FDTFEN bit is set." start="0x1" />
+      </BitField>
+      <BitField name="PIPEDIFF" description="Current differentiates Pipe2 vs. Pipe1" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe2 gets Pipe1 pixels after their processing in shared Gamma, StatRemoval, Demosaicing. Pipe2 shares the same VC DTID of Pipe1 when a CSI2 camera sensor is plugged." start="0x0" />
+        <Enum name="B_0x1" description="Pipe1 gets pixels from only VC/DTID configured in pipe1, processed by all including Gamma, StatRemoval, Demosaicing. Pipe2 gets pixels from only VC/DTID configured in Pipe2, processed from Crop only (Gamma common with Pipe1, no StatRem, no demosaicing)" start="0x1" />
+      </BitField>
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="FDTF" description="Current force data type format" start="24" size="6" access="ReadOnly" />
+      <BitField name="FDTFEN" description="Current force data type format enable" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When the data type DTIDx is detected by the pipe, the real pixel format considering by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host. It allows to handle, for instance, 3D sensors camera with user data type in bottom-up approach, and to explicitly define the pixel format to be handled by the pipe." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CBPRCR" description="DCMIPP Pipe1 current bad pixel removal register" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current status of enable bit" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: bad pixel removal is not active, all pixels are transmitted through" start="0x0" />
+        <Enum name="B_0x1" description="Enable: if bad pixel are detected, they are replaced by corrected pixels." start="0x1" />
+      </BitField>
+      <BitField name="STRENGTH" description="Current strength (aggressiveness) of the bad pixel detection:" start="1" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="the filter is fairly tolerant: only a few pixels are declared bad, due to their high noise." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CBLCCR" description="DCMIPP Pipe1 current black level calibration control register" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="For current black level calibration" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: black level calibration is not active, all pixels are transmitted non-modified." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the BLCR, G, B are subtracted." start="0x1" />
+      </BitField>
+      <BitField name="BLCB" description="Current black level calibration - Blue" start="8" size="8" access="ReadOnly" />
+      <BitField name="BLCG" description="Current black level calibration - Green" start="16" size="8" access="ReadOnly" />
+      <BitField name="BLCR" description="Current black level calibration - Red" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CEXCR1" description="DCMIPP Pipe1 current exposure control register 1" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="for exposure control (multiplication and shift)" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: exposure multiplier and shift are not applied." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the exposure multiplication and shift is applied." start="0x1" />
+      </BitField>
+      <BitField name="MULTR" description="Current exposure multiplier - Red" start="20" size="8" access="ReadOnly" />
+      <BitField name="SHFR" description="Current exposure shift - Red" start="28" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CEXCR2" description="DCMIPP Pipe1 current exposure control register 2" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MULTB" description="Current exposure multiplier - Blue" start="4" size="8" access="ReadOnly" />
+      <BitField name="SHFB" description="Current exposure shift - Blue" start="12" size="3" access="ReadOnly" />
+      <BitField name="MULTG" description="Current exposure multiplier - Green" start="20" size="8" access="ReadOnly" />
+      <BitField name="SHFG" description="Current exposure shift - Green" start="28" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST1CR" description="DCMIPP Pipe1 current statistics 1 control register" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current enable bit value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Current source of statistics" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Current statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Current accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST2CR" description="DCMIPP Pipe1 current statistics 2 control register" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST3CR" description="DCMIPP Pipe1 current statistics 3 control register" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CSTSTR" description="DCMIPP Pipe1 current statistics window start register" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CSTSZR" description="DCMIPP Pipe1 current statistics window size register" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CROPEN" description="Current CROPEN bit value" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are used to compute the statistics." start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSTART, HSTART, VSIZE, HSIZE, are used for statistics." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCCR" description="DCMIPP Pipe1 current ColorConv configuration register" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current value applied" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Output samples type used while CLAMP is activated" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCRR1" description="DCMIPP Pipe1 current ColorConv red coefficient register 1" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Current coefficient row 1 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="RG" description="Current coefficient row 1 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCRR2" description="DCMIPP Pipe1 current ColorConv red coefficient register 2" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Current coefficient row 1 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="RA" description="Current coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCGR1" description="DCMIPP Pipe1 current ColorConv green coefficient register 1" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Current coefficient row 2 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="GG" description="Current coefficient row 2 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCGR2" description="DCMIPP Pipe1 current ColorConv green coefficient register 2" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Current coefficient row 2 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="GA" description="Current coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCBR1" description="DCMIPP Pipex current ColorConv blue coefficient register 1" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Current coefficient row 3 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="BG" description="Current coefficient row 3 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCBR2" description="DCMIPP Pipe1 current ColorConv blue coefficient register 2" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Current coefficient row 3 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="BA" description="Current coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR1" description="DCMIPP Pipe1 current contrast control register 1" start="+0xAA0" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current ENABLE bit value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, pixels are forwarded idle." start="0x0" />
+        <Enum name="B_0x1" description="Enable, contrast enhancement is applied on pixels." start="0x1" />
+      </BitField>
+      <BitField name="LUM0" description="Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR2" description="DCMIPP Pipe1 current contrast control register 2" start="+0xAA4" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM4" description="Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" start="1" size="6" access="ReadOnly" />
+      <BitField name="LUM3" description="Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+      <BitField name="LUM2" description="Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" start="17" size="6" access="ReadOnly" />
+      <BitField name="LUM1" description="Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" start="25" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR3" description="DCMIPP Pipe1 current contrast control register 3" start="+0xAA8" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM8" description="Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" start="1" size="6" access="ReadOnly" />
+      <BitField name="LUM7" description="Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+      <BitField name="LUM6" description="Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" start="17" size="6" access="ReadOnly" />
+      <BitField name="LUM5" description="Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" start="25" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CFCTCR" description="DCMIPP Pipex current flow control configuration register" start="+0xB00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - Received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCRSTR" description="DCMIPP Pipex current crop window start register" start="+0xB04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCRSZR" description="DCMIPP Pipex current crop window size register" start="+0xB08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current ENABLE bit value." start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDCCR" description="DCMIPP Pipex current decimation register" start="+0xB0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDSCR" description="DCMIPP Pipex current downsize configuration register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Current horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="ReadOnly" />
+      <BitField name="VDIV" description="Current vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current value of bit ENABLE" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDSRTIOR" description="DCMIPP Pipex current downsize ratio register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Current horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="ReadOnly" />
+      <BitField name="VRATIO" description="Current vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CDSSZR" description="DCMIPP Pipex current downsize destination size register" start="+0xB18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCMRICR" description="DCMIPP Pipex current common ROI configuration register" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Current region of interest line size width" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Current region of interest 1 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Current region of interest 2 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Current region of interest 3 enable" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Current region of interest 4 enable" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Current region of interest 5 enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Current region of interest 6 enable" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Current region of interest 7 enable" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Current region of interest 8 enable" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CRI1CR1" description="DCMIPP Pipe1 current ROI1 configuration register 1" start="+0xB24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI1CR2" description="DCMIPP Pipe1 current ROI1 configuration register 2" start="+0xB28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI2CR1" description="DCMIPP Pipe1 current ROI2 configuration register 1" start="+0xB2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI2CR2" description="DCMIPP Pipe1 current ROI2 configuration register 2" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI3CR1" description="DCMIPP Pipe1 current ROI3 configuration register 1" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI3CR2" description="DCMIPP Pipe1 current ROI3 configuration register 2" start="+0xB38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI4CR1" description="DCMIPP Pipe1 current ROI4 configuration register 1" start="+0xB3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI4CR2" description="DCMIPP Pipe1 current ROI4 configuration register 2" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI5CR1" description="DCMIPP Pipe1 current ROI5 configuration register 1" start="+0xB44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI5CR2" description="DCMIPP Pipe1 current ROI5 configuration register 2" start="+0xB48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI6CR1" description="DCMIPP Pipe1 current ROI6 configuration register 1" start="+0xB4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI6CR2" description="DCMIPP Pipe1 current ROI6 configuration register 2" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI7CR1" description="DCMIPP Pipe1 current ROI7 configuration register 1" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI7CR2" description="DCMIPP Pipe1 current ROI7 configuration register 2" start="+0xB58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI8CR1" description="DCMIPP Pipe1 current ROI8 configuration register 1" start="+0xB5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI8CR2" description="DCMIPP Pipe1 current ROI8 configuration register 2" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPCR" description="DCMIPP Pipe1 current pixel packer configuration register" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="RGB888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888 (with A = 0xFF)" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888 (with A = 0xFF)" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (32 bpp, FOURCC = AYUV, with A = 0xFF)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (16 bpp, FOURCC = YUYV)" start="0x6" />
+        <Enum name="B_0x7" description="YUV422 2-buffer (16 bpp, FOURCC = none)" start="0x7" />
+        <Enum name="B_0x8" description="YUV420 2-buffer (12 bpp, FOURCC = NV21), NV12 available with SWAPRB = 1" start="0x8" />
+        <Enum name="B_0x9" description="YUV420 3-buffer (12 bpp, FOURCC = YV12)" start="0x9" />
+        <Enum name="B_0xA" description="YUV422 1-buffer (16 bpp, FOURCC = UYVY)" start="0xA" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and U-vs-V components if YUV" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE Event and Interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe1 always drains out the pixels to memory address set by DCMIPP_P1PPM0AR1, and DCMIPP_P1PPM1AR1 as well as DCMIPP_P1PPM2AR1 in case of semi-planar or multi-planar buffer configuration" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Output pixels address location switches from DCMIPP_P1PPM0AR1 to DCMIPP_P1PPM0AR2 alternatively on each frame. For the semi- and multi-planar operations, the output pixels switches from/to DCMIPP_P1PPM1AR1 to/from DCMIPP_P1PPM1AR2. Memory buffer switches from/to DCMIPP_P1PPM2AR1 to/from DCMIPP_P1PPM2AR2 for multi-planar operations." start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CPPM0AR1" description="DCMIPP Pipe1 current pixel packer Memory0 address register 1" start="+0xBC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM0AR2" description="DCMIPP Pipe1 current pixel packer Memory0 address register 2" start="+0xBC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM0PR" description="DCMIPP Pipex current pixel packer Memory0 pitch register" start="+0xBCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Current number of bytes between the address of two consecutive lines." start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1AR1" description="DCMIPP Pipex current pixel packer Memory1 address register 1" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1AR2" description="DCMIPP Pipex current pixel packer Memory1 address register 2" start="+0xBD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1PR" description="DCMIPP Pipex current pixel packer Memory1 pitch register" start="+0xBDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Current number of bytes between the address of two consecutive lines" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM2AR1" description="DCMIPP Pipex current pixel packer Memory2 address register 1" start="+0xBE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM2AR2" description="DCMIPP Pipex current pixel packer Memory2 address register 1" start="+0xBE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2FSCR" description="DCMIPP Pipe2 flow selection configuration register" start="+0xC04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type ID" start="0" size="6" access="Read/Write" />
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="FDTF" description="Force data type format" start="24" size="6" access="Read/Write" />
+      <BitField name="FDTFEN" description="Force data type format enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When the data type DTIDA is detected by the pipe, the real pixel format considered by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PipeN disabled" start="0x0" />
+        <Enum name="B_0x1" description="PipeN enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2FCTCR" description="DCMIPP Pipex flow control configuration register" start="+0xD00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode. The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame). Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CRSTR" description="DCMIPP Pipex crop window start register" start="+0xD04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2CRSZR" description="DCMIPP Pipex crop window size register" start="+0xD08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="16" size="12" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DCCR" description="DCMIPP Pipex decimation register" start="+0xD0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DSCR" description="DCMIPP Pipex downsize configuration register" start="+0xD10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="Read/Write" />
+      <BitField name="VDIV" description="Vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DSRTIOR" description="DCMIPP Pipex downsize ratio register" start="+0xD14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="Read/Write" />
+      <BitField name="VRATIO" description="Vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2DSSZR" description="DCMIPP Pipex downsize destination size register" start="+0xD18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2CMRICR" description="DCMIPP Pipex common ROI configuration register" start="+0xD20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Region of interest line size width" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Region of interest 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Region of interest 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Region of interest 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Region of interest 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Region of interest 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Region of interest 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Region of interest 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Region of interest 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2RI1CR1" description="DCMIPP Pipe2 ROI1 configuration register 1" start="+0xD24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI1CR2" description="DCMIPP Pipe2 ROI1 configuration register 2" start="+0xD28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI2CR1" description="DCMIPP Pipe2 ROI2 configuration register 1" start="+0xD2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI2CR2" description="DCMIPP Pipe2 ROI2 configuration register 2" start="+0xD30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI3CR1" description="DCMIPP Pipe2 ROI3 configuration register 1" start="+0xD34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI3CR2" description="DCMIPP Pipe2 ROI3 configuration register 2" start="+0xD38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI4CR1" description="DCMIPP Pipe2 ROI4 configuration register 1" start="+0xD3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI4CR2" description="DCMIPP Pipe2 ROI4 configuration register 2" start="+0xD40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI5CR1" description="DCMIPP Pipe2 ROI5 configuration register 1" start="+0xD44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI5CR2" description="DCMIPP Pipe2 ROI5 configuration register 2" start="+0xD48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI6CR1" description="DCMIPP Pipe2 ROI6 configuration register 1" start="+0xD4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI6CR2" description="DCMIPP Pipe2 ROI6 configuration register 2" start="+0xD50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI7CR1" description="DCMIPP Pipe2 ROI7 configuration register 1" start="+0xD54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI7CR2" description="DCMIPP Pipe2 ROI7 configuration register 2" start="+0xD58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI8CR1" description="DCMIPP Pipe2 ROI8 configuration register 1" start="+0xD5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI8CR2" description="DCMIPP Pipe2 ROI8 configuration register 2" start="+0xD60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2GMCR" description="DCMIPP Pipex gamma configuration register" start="+0xD70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Gamma is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2PPCR" description="DCMIPP Pipe2 pixel packer configuration register" start="+0xDC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format (only coplanar formats are supported in Pipe2)" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="RG/B888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (FOURCC = AYUV)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (FOURCC = YUYV)" start="0x6" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active." start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe2 is always dump to memory address set by DCMIPP_P2PPM0AR1" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P2PPM0AR1 register to DCMIPP_P2PPM0AR2 register alternatively on each frame" start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2PPM0AR1" description="DCMIPP Pipe2 pixel packer Memory0 address register 1" start="+0xDC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2PPM0AR2" description="DCMIPP Pipe2 pixel packer Memory0 address register 2" start="+0xDC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2PPM0PR" description="DCMIPP Pipex pixel packer Memory0 pitch register" start="+0xDCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2STM0AR" description="DCMIPP Pipex status Memory0 address register" start="+0xDD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2IER" description="DCMIPP Pipe2 interrupt enable register" start="+0xDF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2SR" description="DCMIPP Pipe2 status register" start="+0xDF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and data of this frame are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2FCR" description="DCMIPP Pipe2 interrupt clear register" start="+0xDFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CFSCR" description="DCMIPP Pipe2 current flow selection configuration register" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type ID" start="0" size="6" access="ReadOnly" />
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="FDTF" description="Current force data type format" start="24" size="6" access="ReadOnly" />
+      <BitField name="FDTFEN" description="Current force data type format enable" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When data type DTIDA is detected by the pipe, the real pixel format considering by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CFCTCR" description="DCMIPP Pipex current flow control configuration register" start="+0xF00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - Received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CCRSTR" description="DCMIPP Pipex current crop window start register" start="+0xF04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CCRSZR" description="DCMIPP Pipex current crop window size register" start="+0xF08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current ENABLE bit value." start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDCCR" description="DCMIPP Pipex current decimation register" start="+0xF0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDSCR" description="DCMIPP Pipex current downsize configuration register" start="+0xF10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Current horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="ReadOnly" />
+      <BitField name="VDIV" description="Current vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current value of bit ENABLE" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDSRTIOR" description="DCMIPP Pipex current downsize ratio register" start="+0xF14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Current horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="ReadOnly" />
+      <BitField name="VRATIO" description="Current vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CDSSZR" description="DCMIPP Pipex current downsize destination size register" start="+0xF18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CCMRICR" description="DCMIPP Pipex current common ROI configuration register" start="+0xF20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Current region of interest line size width" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Current region of interest 1 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Current region of interest 2 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Current region of interest 3 enable" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Current region of interest 4 enable" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Current region of interest 5 enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Current region of interest 6 enable" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Current region of interest 7 enable" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Current region of interest 8 enable" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CRI1CR1" description="DCMIPP Pipe2 current ROI1 configuration register 1" start="+0xF24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI1CR2" description="DCMIPP Pipe2 current ROI1 configuration register 2" start="+0xF28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI2CR1" description="DCMIPP Pipe2 current ROI2 configuration register 1" start="+0xF2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI2CR2" description="DCMIPP Pipe2 current ROI2 configuration register 2" start="+0xF30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI3CR1" description="DCMIPP Pipe2 current ROI3 configuration register 1" start="+0xF34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI3CR2" description="DCMIPP Pipe2 current ROI3 configuration register 2" start="+0xF38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI4CR1" description="DCMIPP Pipe2 current ROI4 configuration register 1" start="+0xF3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI4CR2" description="DCMIPP Pipe2 current ROI4 configuration register 2" start="+0xF40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI5CR1" description="DCMIPP Pipe2 current ROI5 configuration register 1" start="+0xF44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI5CR2" description="DCMIPP Pipe2 current ROI5 configuration register 2" start="+0xF48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI6CR1" description="DCMIPP Pipe2 current ROI6 configuration register 1" start="+0xF4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI6CR2" description="DCMIPP Pipe2 current ROI6 configuration register 2" start="+0xF50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI7CR1" description="DCMIPP Pipe2 current ROI7 configuration register 1" start="+0xF54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI7CR2" description="DCMIPP Pipe2 current ROI7 configuration register 2" start="+0xF58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI8CR1" description="DCMIPP Pipe2 current ROI8 configuration register 1" start="+0xF5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI8CR2" description="DCMIPP Pipe2 current ROI8 configuration register 2" start="+0xF60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CPPCR" description="DCMIPP Pipe2 current pixel packer configuration register" start="+0xFC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format (only coplanar formats are supported in Pipe2)" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="RG/B888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (FOURCC = AYUV)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (FOURCC = YUYV)" start="0x6" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active." start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe2 is always dump to memory address set by DCMIPP_P2PPM0AR1" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P2PPM0AR1 register to DCMIPP_P2PPM0AR2 register alternatively on each frame" start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CPPM0AR1" description="DCMIPP Pipe2 current pixel packer Memory0 address register 1" start="+0xFC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CPPM0AR2" description="DCMIPP Pipe2 current pixel packer Memory0 address register 2" start="+0xFC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DCMIPP_S" description="Digital camera interface pixel pipeline" start="0x58002000">
+    <Register name="DCMIPP_IPGR1" description="DCMIPP IPPLUG global register 1" start="+0x000" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMORYPAGE" description="Memory page size, as power of 2 of 64-byte units:" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+      </BitField>
+      <BitField name="QOS_MODE" description="Quality of service" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPGR2" description="DCMIPP IPPLUG global register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSTART" description="Request to lock the IP-Plug, to allow reconfiguration." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No lock requested, IP-Plug runs on demand by background HW." start="0x0" />
+        <Enum name="B_0x1" description="Lock requested: IP-Plug freezes shortly (see IDLE bit when lock is active)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPGR3" description="DCMIPP IPPLUG global register 3" start="+0x008" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLE" description="Status of IP-Plug" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="IP-Plug is running (on demand by background HW)" start="0x0" />
+        <Enum name="B_0x1" description="IP-Plug is currently locked and can be reconfigured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPGR8" description="DCMIPP IPPLUG identification register" start="+0x01C" size="4" reset_value="0xAA040314" reset_mask="0xFFFFFFFF">
+      <BitField name="DID" description="Division identifier (0x14)" start="0" size="6" access="ReadOnly" />
+      <BitField name="REVID" description="Revision identifier (0x03)" start="8" size="5" access="ReadOnly" />
+      <BitField name="ARCHIID" description="Architecture identifier (0x04)" start="16" size="5" access="ReadOnly" />
+      <BitField name="IPPID" description="IP identifier (0xAA)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_IPC1R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x20" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC1R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x24" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC1R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x28" size="4" reset_value="0x007F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC2R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x30" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC2R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x34" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC2R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x38" size="4" reset_value="0x013F0080" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC3R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x40" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC3R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x44" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC3R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x48" size="4" reset_value="0x018F0140" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC4R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x50" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC4R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x54" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC4R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x58" size="4" reset_value="0x01BF0190" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_IPC5R1" description="DCMIPP IPPLUG Clientx register 1" start="+0x60" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="TRAFFIC" description="Burst size as power of 2 of 8-byte units" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="8 bytes" start="0x0" />
+        <Enum name="B_0x1" description="16 bytes" start="0x1" />
+      </BitField>
+      <BitField name="OTR" description="Maximum outstanding transactions" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No outstanding transaction limitation (except via FIFO size)" start="0x0" />
+        <Enum name="B_0x1" description="Maximum two outstanding transactions ongoing." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC5R2" description="DCMIPP IPPLUG Clientx register 2" start="+0x64" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVCMAPPING" description="Non-user, must be kept at reset value." start="8" size="4" access="Read/Write" />
+      <BitField name="WLRU" description="Ratio for WLRU[3:0] arbitration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Ratio part = 1" start="0x0" />
+        <Enum name="B_0x1" description="Ratio part = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_IPC5R3" description="DCMIPP IPPLUG Clientx register 3" start="+0x68" size="4" reset_value="0x027F01C0" reset_mask="0xFFFFFFFF">
+      <BitField name="DPREGSTART" description="Start word (AXI width = 64 bits) of the FIFO of Clientx." start="0" size="10" access="Read/Write" />
+      <BitField name="DPREGEND" description="End word (AXI width = 64 bits) of the FIFO of Clientx." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_PRCR" description="DCMIPP parallel interface control register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESS" description="Embedded synchronization select" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals." start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow." start="0x1" />
+      </BitField>
+      <BitField name="PCKPOL" description="Pixel clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active" start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="Horizontal synchronization polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="HSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="Vertical synchronization polarity" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSYNC active low" start="0x0" />
+        <Enum name="B_0x1" description="VSYNC active high" start="0x1" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every pixel clock" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 10-bit data on every pixel clock" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures 12-bit data on every pixel clock" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures 14-bit data on every pixel clock" start="0x3" />
+        <Enum name="B_0x4" description="Interface captures 16-bit data on every pixel clock" start="0x4" />
+      </BitField>
+      <BitField name="ENABLE" description="Parallel interface enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parallel interface disabled to lower power consumption" start="0x0" />
+        <Enum name="B_0x1" description="Parallel interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="FORMAT" description="Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format)." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x1E" description="YUV422" start="0x1E" />
+        <Enum name="B_0x22" description="RGB565" start="0x22" />
+        <Enum name="B_0x24" description="RGB888 (= YUV444)" start="0x24" />
+        <Enum name="B_0x2A" description="RAW8" start="0x2A" />
+        <Enum name="B_0x2B" description="RAW10" start="0x2B" />
+        <Enum name="B_0x2C" description="RAW12" start="0x2C" />
+        <Enum name="B_0x2D" description="RAW14" start="0x2D" />
+        <Enum name="B_0x4A" description="monochrome 8-bit" start="0x4A" />
+        <Enum name="B_0x4B" description="monochrome 10-bit" start="0x4B" />
+        <Enum name="B_0x4C" description="monochrome 12-bit" start="0x4C" />
+        <Enum name="B_0x4D" description="monochrome 14-bit" start="0x4D" />
+        <Enum name="B_0x5A" description="byte stream (JPEG, compressed video)" start="0x5A" />
+      </BitField>
+      <BitField name="SWAPCYCLES" description="Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default" start="0x0" />
+        <Enum name="B_0x1" description="Swap active: the data of cycle 1 is used before the data of cycle 0." start="0x1" />
+      </BitField>
+      <BitField name="SWAPBITS" description="Swap LSB vs. MSB within each received component" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="As received" start="0x0" />
+        <Enum name="B_0x1" description="Swapped MSB vs. LSB" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRESCR" description="DCMIPP parallel interface embedded synchronization code register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSC" description="Frame start delimiter code" start="0" size="8" access="Read/Write" />
+      <BitField name="LSC" description="Line start delimiter code" start="8" size="8" access="Read/Write" />
+      <BitField name="LEC" description="Line end delimiter code" start="16" size="8" access="Read/Write" />
+      <BitField name="FEC" description="Frame end delimiter code" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_PRESUR" description="DCMIPP parallel interface embedded synchronization unmask register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSU" description="Frame start delimiter unmask" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FSC byte in DCMIPP_ESCR is masked while comparing the frame start delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FSC byte in DCMIPP_ESCR is compared while comparing the frame start delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="LSU" description="Line start delimiter unmask" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LSC byte in DCMIPP_ESCR is masked while comparing the line start delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LSC byte in DCMIPP_ESCR is compared while comparing the line start delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="LEU" description="Line end delimiter unmask" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the LEC byte in DCMIPP_ESCR is masked while comparing the line end delimiter with the received data" start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the LEC byte in DCMIPP_ESCR is compared while comparing the line end delimiter with the received data" start="0x1" />
+      </BitField>
+      <BitField name="FEU" description="Frame end delimiter unmask" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="The corresponding bit in the FEC byte in DCMIPP_ESCR is masked while comparing the frame end delimiter with the received data." start="0x0" />
+        <Enum name="B_0x1" description="The corresponding bit in the FEC byte in DCMIPP_ESCR is compared while comparing the frame end delimiter with the received data" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRIER" description="DCMIPP parallel interface interrupt enable register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERRIE" description="Synchronization error interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the embedded synchronization codes are not received in the correct order." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRSR" description="DCMIPP parallel interface status register" start="+0x1F8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERRF" description="Synchronization error raw interrupt status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="HSYNC" description="This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active line" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="VSYNC" description="This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active frame" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between frames" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_PRFCR" description="DCMIPP parallel interface interrupt clear register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CERRF" description="Synchronization error interrupt status clear" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_CMCR" description="DCMIPP common configuration register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSEL" description="input selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMI" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2" start="0x1" />
+      </BitField>
+      <BitField name="PSFC" description="Pipe selection for the frame counter" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Frame counter mapped to Pipe0" start="0x0" />
+        <Enum name="B_0x1" description="Frame counter mapped to Pipe1" start="0x1" />
+        <Enum name="B_0x2" description="Frame counter mapped to Pipe2" start="0x2" />
+      </BitField>
+      <BitField name="CFC" description="Clear frame counter" start="4" size="1" access="WriteOnly" />
+      <BitField name="SWAPRB" description="Swap R/U and B/V" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RGB/VYU" start="0x0" />
+        <Enum name="B_0x1" description="BGR/UYV" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMFRCR" description="DCMIPP common frame counter register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRMCNT" description="Frame counter, read-only, loops around." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_CMIER" description="DCMIPP common interrupt enable register" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATXERRIE" description="AXI transfer error interrupt enable for IPPLUG" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="PRERRIE" description="Limit interrupt enable for the parallel Interface" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0LINEIE" description="Multi-line capture complete interrupt enable for Pipe0" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0FRAMEIE" description="Frame capture complete interrupt enable for Pipe0" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0VSYNCIE" description="Vertical sync interrupt enable for Pipe0" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0LIMITIE" description="Limit interrupt enable for Pipe0" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P0OVRIE" description="Overrun interrupt enable for Pipe0" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1LINEIE" description="Multi-line capture complete interrupt status clear for Pipe1" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1FRAMEIE" description="Frame capture complete interrupt enable for Pipe1" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1VSYNCIE" description="Vertical sync interrupt enable for Pipe1" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+      <BitField name="P1OVRIE" description="Overrun interrupt enable for Pipe1" start="23" size="1" access="Read/Write" />
+      <BitField name="P2LINEIE" description="Multi-line capture complete interrupt enable for Pipe2" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2FRAMEIE" description="Frame capture complete interrupt enable for Pipe2" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2VSYNCIE" description="Vertical sync interrupt enable for Pipe2" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="P2OVRIE" description="Overrun interrupt status enable for Pipe2" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMSR1" description="DCMIPP common status register 1" start="+0x3F4" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="PRHSYNC" description="This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active line" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between lines" start="0x1" />
+      </BitField>
+      <BitField name="PRVSYNC" description="This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Active frame" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization between frames" start="0x1" />
+      </BitField>
+      <BitField name="P0LSTLINE" description="Last line LSB bit, sampled at Frame capture complete event for Pipe0" start="8" size="1" access="ReadOnly" />
+      <BitField name="P0LSTFRM" description="Last frame LSB bit, sampled at Frame capture complete event for Pipe0" start="9" size="1" access="ReadOnly" />
+      <BitField name="P0CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe0" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+      <BitField name="P1LSTLINE" description="Last line LSB bit, sampled at Frame capture complete event for Pipe1" start="16" size="1" access="ReadOnly" />
+      <BitField name="P1LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event for Pipe1" start="17" size="1" access="ReadOnly" />
+      <BitField name="P1CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe1" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+      <BitField name="P2LSTLINE" description="Last line LSB bit, sampled at frame capture complete event for Pipe2" start="24" size="1" access="ReadOnly" />
+      <BitField name="P2LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event for Pipe2" start="25" size="1" access="ReadOnly" />
+      <BitField name="P2CPTACT" description="Active frame capture (active from start-of-frame to frame complete) for Pipe2" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture currently active" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMSR2" description="DCMIPP common status register 2" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATXERRF" description="AXI transfer error interrupt status flag for the IPPLUG." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No AXI transfer error detected" start="0x0" />
+        <Enum name="B_0x1" description="AXI transfer error occurred on an AXI client. This bit signals an error on a client without any specific hardware action, the software must handle the situation (normally used when debugging software application code)." start="0x1" />
+      </BitField>
+      <BitField name="PRERRF" description="Synchronization error raw interrupt status for the parallel interface." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error detected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded synchronization characters are not received in the correct order." start="0x1" />
+      </BitField>
+      <BitField name="P0LINEF" description="Multi-line capture completed raw interrupt status for Pipe0" start="8" size="1" access="ReadOnly" />
+      <BitField name="P0FRAMEF" description="Frame capture completed raw interrupt status for Pipe0" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P0VSYNCF" description="VSYNC raw interrupt status for Pipe0" start="10" size="1" access="ReadOnly" />
+      <BitField name="P0LIMITF" description="Limit raw interrupt status for Pipe0" start="14" size="1" access="ReadOnly" />
+      <BitField name="P0OVRF" description="Overrun raw interrupt status for Pipe0" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="P1LINEF" description="Multi-line capture completed raw interrupt status for Pipe1" start="16" size="1" access="ReadOnly" />
+      <BitField name="P1FRAMEF" description="Frame capture completed raw interrupt status for Pipe1" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P1VSYNCF" description="VSYNC raw interrupt status for Pipe1" start="18" size="1" access="ReadOnly" />
+      <BitField name="P1OVRF" description="Overrun raw interrupt status for Pipe1" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="P2LINEF" description="Multi-line capture completed raw interrupt status for Pipe2" start="24" size="1" access="ReadOnly" />
+      <BitField name="P2FRAMEF" description="Frame capture completed raw interrupt status for Pipe2" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="P2VSYNCF" description="VSYNC raw interrupt status for Pipe2" start="26" size="1" access="ReadOnly" />
+      <BitField name="P2OVRF" description="Overrun raw interrupt status for Pipe2" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_CMFCR" description="DCMIPP common interrupt clear register" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CATXERRF" description="AXI transfer error interrupt status clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="CPRERRF" description="Synchronization error interrupt status clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CP0LINEF" description="Multi-line capture complete interrupt status clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="CP0FRAMEF" description="Frame capture complete interrupt status clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="CP0VSYNCF" description="Vertical synchronization interrupt status clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="CP0LIMITF" description="limit interrupt status clear" start="14" size="1" access="WriteOnly" />
+      <BitField name="CP0OVRF" description="Overrun interrupt status clear" start="15" size="1" access="WriteOnly" />
+      <BitField name="CP1LINEF" description="Multi-line capture complete interrupt status clear" start="16" size="1" access="WriteOnly" />
+      <BitField name="CP1FRAMEF" description="Frame capture complete interrupt status clear" start="17" size="1" access="WriteOnly" />
+      <BitField name="CP1VSYNCF" description="Vertical synchronization interrupt status clear" start="18" size="1" access="WriteOnly" />
+      <BitField name="CP1OVRF" description="Overrun interrupt status clear" start="23" size="1" access="WriteOnly" />
+      <BitField name="CP2LINEF" description="Multi-line capture complete interrupt status clear" start="24" size="1" access="WriteOnly" />
+      <BitField name="CP2FRAMEF" description="Frame capture complete interrupt status clear" start="25" size="1" access="WriteOnly" />
+      <BitField name="CP2VSYNCF" description="Vertical synchronization interrupt status clear" start="26" size="1" access="WriteOnly" />
+      <BitField name="CP2OVRF" description="Overrun interrupt status clear" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P0FSCR" description="DCMIPP Pipe0 flow selection configuration register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type selection ID A" start="0" size="6" access="Read/Write" />
+      <BitField name="DTIDB" description="Data type selection ID B" start="8" size="6" access="Read/Write" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe" start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe" start="0x1" />
+        <Enum name="B_0x2" description="All data types from the selected virtual channel (except the DTIDA or DTIDB) are forwarded in the pipe" start="0x2" />
+        <Enum name="B_0x3" description="All data types of the selected virtual channel VC are forwarded in the pipe" start="0x3" />
+      </BitField>
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0FCTCR" description="DCMIPP Pipe0 flow control configuration register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame, and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0SCSTR" description="DCMIPP Pipe0 stat/crop start register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 words wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0SCSZR" description="DCMIPP Pipe0 stat/crop size register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 word wide (data 32-bit)" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="POSNEG" description="This bit is set and cleared by software. It has a meaning only if ENABLE bit is set." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Positive area, the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART" start="0x0" />
+        <Enum name="B_0x1" description="Negative area, the area excluding the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART" start="0x1" />
+      </BitField>
+      <BitField name="ENABLE" description="This bit is set and cleared by software." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass. All the data are computed, if the statistic data are sent within the frame, they are sent to the processing pipe as pixels data." start="0x0" />
+        <Enum name="B_0x1" description="Enable. Depending on bit POSNEG value, the rectangle defined by VSIZE, HSIZE, VSTART and HSTART can be used to extract or to remove some data (statistical extraction or removal, or basic 2D crop features)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0DCCNTR" description="DCMIPP Pipe0 dump counter register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Number of data dumped during the frame." start="0" size="26" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0DCLMTR" description="DCMIPP Pipe0 dump limit register" start="+0x5B4" size="4" reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="LIMIT" description="Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation." start="0" size="24" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled, no check on the amount of 32-bit words transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enabled, check done versus limit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0PPCR" description="DCMIPP Pipe0 pixel packer configuration register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWAPYUV" description="Swaps, within a 32-bit word, byte 0-vs-1 and byte 2-vs-3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Outputs the provided words, as described in Section 34.10: Pixel format description." start="0x0" />
+        <Enum name="B_0x1" description="Swaps the bytes from provided words, byte 0-vs.-1 and 2-vs.-3" start="0x1" />
+      </BitField>
+      <BitField name="PAD" description="Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Aligns on LSB (and pads null bits on MSB), for backward compatibility with former DCMI." start="0x0" />
+        <Enum name="B_0x1" description="Aligns on MSB (and pads null bits on LSB), for better ease of software or GPU." start="0x1" />
+      </BitField>
+      <BitField name="HEADEREN" description="CSI header dump enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI-2 headers are not dumped" start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 headers are dumped as a 32-bit word." start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Byte select mode" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received data" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures 1 data out of 2" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four" start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Odd/even byte select (byte select start)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures the first data (byte or double byte) from the frame/line start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second data (byte or double byte) from the frame/line start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Line select mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures all received lines" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two" start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Odd/even line select (line select start)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures first line after the frame start, second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures second line from the frame start, first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe0 always dumps to memory address set by DCMIPP_P0PPM0AR1." start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P0PPM0AR1 to DCMIPP_P0PPM0AR2 alternatively on each frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0PPM0AR1" description="DCMIPP Pipe0 pixel packer Memory0 address register 1" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0PPM0AR2" description="DCMIPP Pipe0 pixel packer Memory0 address register 2" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P0STM0AR" description="DCMIPP Pipe0 status Memory0 address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0IER" description="DCMIPP Pipe0 interrupt enable register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="LIMITIE" description="Limit interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the limit is reached" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when the limit is reached" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0SR" description="DCMIPP Pipe0 status register" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="LIMITF" description="Limit raw interrupt status" start="6" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number that can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0FCR" description="DCMIPP Pipe0 interrupt clear register" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="CLIMITF" description="limit interrupt status clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CFSCR" description="DCMIPP Pipe0 current flow selection configuration register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type selection ID A" start="0" size="6" access="ReadOnly" />
+      <BitField name="DTIDB" description="Current data type selection ID B" start="8" size="6" access="ReadOnly" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe." start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe." start="0x1" />
+        <Enum name="B_0x2" description="All Datatypes from the selected virtual channel, except the DTIDA or DTIDB are forwarded into the pipe." start="0x2" />
+        <Enum name="B_0x3" description="All Datatypes of the selected virtual channel VC are forwarded in the pipe." start="0x3" />
+      </BitField>
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CFCTCR" description="DCMIPP Pipe0 current flow control configuration register" start="+0x700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame, and then transfers a single frame through the AXI master. At the end of the frame the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CSCSTR" description="DCMIPP Pipe0 current stat/crop start register" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 words wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CSCSZR" description="DCMIPP Pipe0 current stat/crop size register" start="+0x708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 word wide (data 32-bit)." start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high." start="16" size="12" access="ReadOnly" />
+      <BitField name="POSNEG" description="Current value of the POSNEG bit" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Positive area. The rectangle defined by VSIZE,HSIZE, and VSTART, HSTART is the active area." start="0x0" />
+        <Enum name="B_0x1" description="Negative area. The active area is the area excluding the rectangle defined by VSIZE, HSIZE, and VSTART, HSTART." start="0x1" />
+      </BitField>
+      <BitField name="ENABLE" description="Current value of the ENABLE bit" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass. All data are computed, if the statistics data are sent within the frame, they are sent to the processing pipe as pixels data." start="0x0" />
+        <Enum name="B_0x1" description="Enable: Depending on bit POSNEG value, the rectangle defined by the VSIZE, HSIZE, VSTART, HSTART can be used to extract or to remove certain amount of data (statistical extraction or removal, or basic 2D crop features)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CPPCR" description="DCMIPP Pipe0 current pixel packer configuration register" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWAPYUV" description="Swaps, within a 32-bit word, byte 0 vs. 1 and byte 2 vs. 3. It corresponds, for YUV422 pixels formats, to swap between UYVY and YUYV." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Outputs the provided words, as described in Section 34.10: Pixel format description." start="0x0" />
+        <Enum name="B_0x1" description="Swaps the bytes from provided words, byte 0 vs. 1 and 2 vs. 3." start="0x1" />
+      </BitField>
+      <BitField name="PAD" description="Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Aligns on LSB (and pads null bits on MSB), for backward compatibility with former DCMI" start="0x0" />
+        <Enum name="B_0x1" description="Aligns on MSB (and pads null bits on LSB), for better ease of software or GPU" start="0x1" />
+      </BitField>
+      <BitField name="HEADEREN" description="Current CSI header dump enable" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CSI-2 headers are not dumped." start="0x0" />
+        <Enum name="B_0x1" description="CSI-2 headers are dumped as a 32-bit words." start="0x1" />
+      </BitField>
+      <BitField name="BSM" description="Current Byte select mode" start="7" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures all received data" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one data out of two" start="0x1" />
+        <Enum name="B_0x2" description="Interface captures one byte out of four" start="0x2" />
+        <Enum name="B_0x3" description="Interface captures two bytes out of four" start="0x3" />
+      </BitField>
+      <BitField name="OEBS" description="Current odd/even byte select (byte select start)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures the first data (byte or double byte) from the frame/line start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second data (byte or double byte) from the frame/line start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Current Line select mode" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures all received lines" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures one line out of two" start="0x1" />
+      </BitField>
+      <BitField name="OELS" description="Current odd/even line select (ine select start)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interface captures the first line after the frame start, the second one is dropped" start="0x0" />
+        <Enum name="B_0x1" description="Interface captures the second line from the frame start, the first one is dropped" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Current amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe0 is always dump to memory address set by DCMIPP_P0PPM0AR1 register" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P0PPM0AR1 register to DCMIPP_P0PPM0AR2 register alternatively on each frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P0CPPM0AR1" description="DCMIPP Pipe0 current pixel packer Memory0 address register 1" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P0CPPM0AR2" description="DCMIPP Pipe0 current pixel packer Memory0 address register 2" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1FSCR" description="DCMIPP Pipe1 flow selection configuration register" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type selection ID A" start="0" size="6" access="Read/Write" />
+      <BitField name="DTIDB" description="Data type selection ID B" start="8" size="6" access="Read/Write" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Only flow DTIDA from the selected virtual channel is forwarded in the pipe" start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and/or DTIDB from the selected virtual channel are forwarded in the pipe" start="0x1" />
+      </BitField>
+      <BitField name="PIPEDIFF" description="Differentiates Pipe2 from Pipe1" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe2 receives the same data as Pipe1 (Ie data filtered by Pipe1 configuration for VC and DTIDA/DTIDB and DTMODE mode, as well as FDTF and FDTFEN bit)." start="0x0" />
+        <Enum name="B_0x1" description="Pipe1 gets pixels from only VC and DT configured in Pipe1, processed by all block belonging to the image processing functional block (ie, demosaicing, auto exposure, statistics, contrast enhancement)." start="0x1" />
+      </BitField>
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="FDTF" description="Force Datatype format." start="24" size="6" access="Read/Write" />
+      <BitField name="FDTFEN" description="Force Datatype format enable." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable force Datatype format. The Datatype format used by the pipe is the one defined into DTIDx1: Enable force Datatype format. When the Datatype DTIDx is detected by the pipe, the real pixel format considered by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 Host. It allows to handle, for instance, 3D sensors camera using user data type in bottom-up approach, and to explicitly define the pixel format to be handled by the pipe. Note that the flow is first selected using the DTMODE and DTIDA/B, and then, if selected, its data type may be forced with the to FDTC using FDTFEN = 1." start="0x0" />
+      </BitField>
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1SRCR" description="DCMIPP Pipe1 stat removal configuration register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LASTLINE" description="Amount of following lines to keep when CROPEN = 1. If LASTLINE = 0 all pixels after FIRSTLINEDEL are fed through." start="0" size="12" access="Read/Write" />
+      <BitField name="FIRSTLINEDEL" description="Amount of first lines to delete when CROPEN = 1" start="12" size="3" access="Read/Write" />
+      <BitField name="CROPEN" description="Crop line enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No crop (all pixels are fed through)" start="0x0" />
+        <Enum name="B_0x1" description="Crop" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BPRCR" description="DCMIPP Pipe1 bad pixel removal control register" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: bad pixel removal is not active, all pixels are transmitted through" start="0x0" />
+        <Enum name="B_0x1" description="Enable: if bad pixel are detected, they are replaced by corrected pixels" start="0x1" />
+      </BitField>
+      <BitField name="STRENGTH" description="Strength (aggressiveness) of the bad pixel detection" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="The filter is fairly tolerant: only a few pixels are declared bad, due to their high noise" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BPRSR" description="DCMIPP Pipe1 bad pixel removal status register" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADCNT" description="Amount of detected bad pixels" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1DECR" description="DCMIPP Pipe1 decimation register" start="+0x830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted (for raw Bayer data, two lines of components every four)" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted (for raw Bayer data, two lines of components every four)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1BLCCR" description="DCMIPP Pipe1 black level calibration control register" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Black level calibration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: black level calibration is not active, all pixels are transmitted non-modified." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the BLC R, G, B are subtracted." start="0x1" />
+      </BitField>
+      <BitField name="BLCB" description="Black level calibration - Blue" start="8" size="8" access="Read/Write" />
+      <BitField name="BLCG" description="Black level calibration - Green" start="16" size="8" access="Read/Write" />
+      <BitField name="BLCR" description="Black level calibration - Red" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1EXCR1" description="DCMIPP Pipe1 exposure control register 1" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Exposure control (multiplication and shift) of all red, green and blue" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: exposure multiplier and shift are not applied" start="0x0" />
+        <Enum name="B_0x1" description="Enable: the exposure multiplication and shift is applied" start="0x1" />
+      </BitField>
+      <BitField name="MULTR" description="Exposure multiplier - Red" start="20" size="8" access="Read/Write" />
+      <BitField name="SHFR" description="Exposure shift - Red" start="28" size="3" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1EXCR2" description="DCMIPP Pipe1 exposure control register 2" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MULTB" description="Exposure multiplier - Blue" start="4" size="8" access="Read/Write" />
+      <BitField name="SHFB" description="Exposure shift - Blue" start="12" size="3" access="Read/Write" />
+      <BitField name="MULTG" description="Exposure multiplier - Green" start="20" size="8" access="Read/Write" />
+      <BitField name="SHFG" description="Exposure shift - Green" start="28" size="3" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1ST1CR" description="DCMIPP Pipe1 statistics1 control register" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All Pixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST2CR" description="DCMIPP Pipe1 statistics 2 control register" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated" start="0x0" />
+        <Enum name="B_0x1" description="Enabled: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240." start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST3CR" description="DCMIPP Pipe1 statistics 3 control register" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated" start="0x0" />
+        <Enum name="B_0x1" description="Enabled: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256." start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240." start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="Read/Write" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1STSTR" description="DCMIPP Pipe1 statistics window start register" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STSZR" description="DCMIPP Pipe1 statistics window size register" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CROPEN" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are used to compute the statistics" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSTART, HSTART, VSIZE, HSIZE is used for statistics." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1ST1SR" description="DCMIPP Pipe1 statistics 1 status register" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1ST2SR" description="DCMIPP Pipe1 statistics 2 status register" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1ST3SR" description="DCMIPP Pipe1 statistics 3 status register" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACCU" description="accumulation result, divided by 256." start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1DMCR" description="DCMIPP Pipe1 demosaicing configuration register" start="+0x870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass" start="0x0" />
+        <Enum name="B_0x1" description="Enable demosaicing" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Raw Bayer type" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="RGGB" start="0x0" />
+        <Enum name="B_0x1" description="GRBG" start="0x1" />
+        <Enum name="B_0x2" description="GBRG" start="0x2" />
+        <Enum name="B_0x3" description="BGGR" start="0x3" />
+      </BitField>
+      <BitField name="PEAK" description="Strength of the peak detection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No peak detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="LINEV" description="Strength of the vertical line detection" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No vertical line detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="LINEH" description="Strength of the horizontal line detection" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No horizontal line detection, pure linear interpolation" start="0x0" />
+      </BitField>
+      <BitField name="EDGE" description="Strength of the edge detection" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No edge detection, pure linear interpolation" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCR" description="DCMIPP Pipe1 ColorConv configuration register" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="output samples type used while CLAMP is activated" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="Clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCRR1" description="DCMIPP Pipe1 ColorConv red coefficient register 1" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Coefficient row 1 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RG" description="Coefficient row 1 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCRR2" description="DCMIPP Pipe1 ColorConv red coefficient register 2" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Coefficient row 1 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RA" description="Coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCGR1" description="DCMIPP Pipe1 ColorConv green coefficient register 1" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Coefficient row 2 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GG" description="Coefficient row 2 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCGR2" description="DCMIPP Pipe1 ColorConv green coefficient register 2" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Coefficient row 2 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GA" description="Coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCBR1" description="DCMIPP Pipex ColorConv blue coefficient register 1" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Coefficient row 3 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BG" description="Coefficient row 3 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CCBR2" description="DCMIPP Pipe1 ColorConv blue coefficient register 2" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Coefficient row 3 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BA" description="Coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR1" description="DCMIPP Pipe1 contrast control register 1" start="+0x8A0" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, pixels are forwarded idle." start="0x0" />
+        <Enum name="B_0x1" description="Enable, contrast enhancement is applied on pixels." start="0x1" />
+      </BitField>
+      <BitField name="LUM0" description="Luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR2" description="DCMIPP Pipe1 contrast control register 2" start="+0x8A4" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM4" description="Luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" start="1" size="6" access="Read/Write" />
+      <BitField name="LUM3" description="Luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+      <BitField name="LUM2" description="Luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" start="17" size="6" access="Read/Write" />
+      <BitField name="LUM1" description="Luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" start="25" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CTCR3" description="DCMIPP Pipe1 contrast control register 3" start="+0x8A8" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM8" description="Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" start="1" size="6" access="Read/Write" />
+      <BitField name="LUM7" description="Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" start="9" size="6" access="Read/Write" />
+      <BitField name="LUM6" description="Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" start="17" size="6" access="Read/Write" />
+      <BitField name="LUM5" description="Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" start="25" size="6" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1FCTCR" description="DCMIPP Pipex flow control configuration register" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode. The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame). Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CRSTR" description="DCMIPP Pipex crop window start register" start="+0x904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CRSZR" description="DCMIPP Pipex crop window size register" start="+0x908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="16" size="12" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DCCR" description="DCMIPP Pipex decimation register" start="+0x90C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DSCR" description="DCMIPP Pipex downsize configuration register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="Read/Write" />
+      <BitField name="VDIV" description="Vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1DSRTIOR" description="DCMIPP Pipex downsize ratio register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="Read/Write" />
+      <BitField name="VRATIO" description="Vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1DSSZR" description="DCMIPP Pipex downsize destination size register" start="+0x918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1CMRICR" description="DCMIPP Pipex common ROI configuration register" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Region of interest line size width" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Region of interest 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Region of interest 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Region of interest 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Region of interest 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Region of interest 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Region of interest 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Region of interest 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Region of interest 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1RI1CR1" description="DCMIPP Pipe1 ROI1 configuration register 1" start="+0x924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI1CR2" description="DCMIPP Pipe1 ROI1 configuration register 2" start="+0x928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI2CR1" description="DCMIPP Pipe1 ROI2 configuration register 1" start="+0x92C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI2CR2" description="DCMIPP Pipe1 ROI2 configuration register 2" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI3CR1" description="DCMIPP Pipe1 ROI3 configuration register 1" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI3CR2" description="DCMIPP Pipe1 ROI3 configuration register 2" start="+0x938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI4CR1" description="DCMIPP Pipe1 ROI4 configuration register 1" start="+0x93C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI4CR2" description="DCMIPP Pipe1 ROI4 configuration register 2" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI5CR1" description="DCMIPP Pipe1 ROI5 configuration register 1" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI5CR2" description="DCMIPP Pipe1 ROI5 configuration register 2" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI6CR1" description="DCMIPP Pipe1 ROI6 configuration register 1" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI6CR2" description="DCMIPP Pipe1 ROI6 configuration register 2" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI7CR1" description="DCMIPP Pipe1 ROI7 configuration register 1" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI7CR2" description="DCMIPP Pipe1 ROI7 configuration register 2" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI8CR1" description="DCMIPP Pipe1 ROI8 configuration register 1" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1RI8CR2" description="DCMIPP Pipe1 ROI8 configuration register 2" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1GMCR" description="DCMIPP Pipex gamma configuration register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Gamma is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1YUVCR" description="DCMIPP Pipe1 YUVConv configuration register" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Output samples type used while CLAMP is activated" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="Clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1YUVRR1" description="DCMIPP Pipe1 YUVConv red coefficient register 1" start="+0x984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Coefficient row 1 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RG" description="Coefficient row 1 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVRR2" description="DCMIPP Pipe1 YUVConv red coefficient register 2" start="+0x988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Coefficient row 1 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="RA" description="Coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVGR1" description="DCMIPP Pipe1 YUVConv green coefficient register 1" start="+0x98C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Coefficient row 2 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GG" description="Coefficient row 2 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVGR2" description="DCMIPP Pipe1 YUVConv green coefficient register 2" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Coefficient row 2 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="GA" description="Coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVBR1" description="DCMIPP Pipe1 YUVConv blue coefficient register 1" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Coefficient row 3 column 1 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BG" description="Coefficient row 3 column 2 of the matrix" start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1YUVBR2" description="DCMIPP Pipe1 YUV blue coefficient register 2" start="+0x998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Coefficient row 3 column 3 of the matrix" start="0" size="11" access="Read/Write" />
+      <BitField name="BA" description="Coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPCR" description="DCMIPP Pipe1 pixel packer configuration register" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="RGB888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888 (with A = 0xFF)" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888 (with A = 0xFF)" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (32 bpp, FOURCC = AYUV, with A = 0xFF)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (16 bpp, FOURCC = YUYV)" start="0x6" />
+        <Enum name="B_0x7" description="YUV422 2-buffer (16 bpp, FOURCC = none)" start="0x7" />
+        <Enum name="B_0x8" description="YUV420 2-buffer (12 bpp, FOURCC = NV21), NV12 available with SWAPRB = 1" start="0x8" />
+        <Enum name="B_0x9" description="YUV420 3-buffer (12 bpp, FOURCC = YV12)" start="0x9" />
+        <Enum name="B_0xA" description="YUV422 1-buffer (16 bpp, FOURCC = UYVY)" start="0xA" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and U-vs-V components if YUV" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE Event and Interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe1 always drains out the pixels to memory address set by DCMIPP_P1PPM0AR1, and DCMIPP_P1PPM1AR1 as well as DCMIPP_P1PPM2AR1 in case of semi-planar or multi-planar buffer configuration" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Output pixels address location switches from DCMIPP_P1PPM0AR1 to DCMIPP_P1PPM0AR2 alternatively on each frame. For the semi- and multi-planar operations, the output pixels switches from/to DCMIPP_P1PPM1AR1 to/from DCMIPP_P1PPM1AR2. Memory buffer switches from/to DCMIPP_P1PPM2AR1 to/from DCMIPP_P1PPM2AR2 for multi-planar operations." start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo. " start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit. " start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1PPM0AR1" description="DCMIPP Pipe1 pixel packer Memory0 address register 1" start="+0x9C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM0AR2" description="DCMIPP Pipe1 pixel packer Memory0 address register 2" start="+0x9C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM0PR" description="DCMIPP Pipex pixel packer Memory0 pitch register" start="+0x9CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM0AR" description="DCMIPP Pipex status Memory0 address register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1AR1" description="DCMIPP Pipex pixel packer Memory1 address register 1" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1AR2" description="DCMIPP Pipex pixel packer Memory1 address register 2" start="+0x9D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM1PR" description="DCMIPP Pipex pixel packer Memory1 pitch register" start="+0x9DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM1AR" description="DCMIPP Pipex status Memory1 address register" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1PPM2AR1" description="DCMIPP Pipex pixel packer memory2 address register 1" start="+0x9E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1PPM2AR2" description="DCMIPP Pipex pixel packer memory2 address register 2" start="+0x9E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P1STM2AR" description="DCMIPP Pipex status Memory2 address register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1IER" description="DCMIPP Pipe1 interrupt enable register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1SR" description="DCMIPP Pipe1 status register" start="+0x9F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured." start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and this frame data are corrupted." start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number, which can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1FCR" description="DCMIPP Pipe1 interrupt clear register" start="+0x9FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CFSCR" description="DCMIPP Pipe1 current flow selection configuration register" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type ID A" start="0" size="6" access="ReadOnly" />
+      <BitField name="DTIDB" description="Current data type ID B" start="8" size="6" access="ReadOnly" />
+      <BitField name="DTMODE" description="Flow selection mode" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Only flow DTID A from the selected virtual channel is forwarded in the pipe." start="0x0" />
+        <Enum name="B_0x1" description="Flows DTIDA and DTIDB from the selected virtual channel are forwarded in the pipe. This combination is valid only if the FDTFEN bit is set." start="0x1" />
+      </BitField>
+      <BitField name="PIPEDIFF" description="Current differentiates Pipe2 vs. Pipe1" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe2 gets Pipe1 pixels after their processing in shared Gamma, StatRemoval, Demosaicing. Pipe2 shares the same VC DTID of Pipe1 when a CSI2 camera sensor is plugged." start="0x0" />
+        <Enum name="B_0x1" description="Pipe1 gets pixels from only VC/DTID configured in pipe1, processed by all including Gamma, StatRemoval, Demosaicing. Pipe2 gets pixels from only VC/DTID configured in Pipe2, processed from Crop only (Gamma common with Pipe1, no StatRem, no demosaicing)" start="0x1" />
+      </BitField>
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="FDTF" description="Current force data type format" start="24" size="6" access="ReadOnly" />
+      <BitField name="FDTFEN" description="Current force data type format enable" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When the data type DTIDx is detected by the pipe, the real pixel format considering by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host. It allows to handle, for instance, 3D sensors camera with user data type in bottom-up approach, and to explicitly define the pixel format to be handled by the pipe." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CBPRCR" description="DCMIPP Pipe1 current bad pixel removal register" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current status of enable bit" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: bad pixel removal is not active, all pixels are transmitted through" start="0x0" />
+        <Enum name="B_0x1" description="Enable: if bad pixel are detected, they are replaced by corrected pixels." start="0x1" />
+      </BitField>
+      <BitField name="STRENGTH" description="Current strength (aggressiveness) of the bad pixel detection:" start="1" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="the filter is fairly tolerant: only a few pixels are declared bad, due to their high noise." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CBLCCR" description="DCMIPP Pipe1 current black level calibration control register" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="For current black level calibration" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: black level calibration is not active, all pixels are transmitted non-modified." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the BLCR, G, B are subtracted." start="0x1" />
+      </BitField>
+      <BitField name="BLCB" description="Current black level calibration - Blue" start="8" size="8" access="ReadOnly" />
+      <BitField name="BLCG" description="Current black level calibration - Green" start="16" size="8" access="ReadOnly" />
+      <BitField name="BLCR" description="Current black level calibration - Red" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CEXCR1" description="DCMIPP Pipe1 current exposure control register 1" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="for exposure control (multiplication and shift)" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass: exposure multiplier and shift are not applied." start="0x0" />
+        <Enum name="B_0x1" description="Enable: the exposure multiplication and shift is applied." start="0x1" />
+      </BitField>
+      <BitField name="MULTR" description="Current exposure multiplier - Red" start="20" size="8" access="ReadOnly" />
+      <BitField name="SHFR" description="Current exposure shift - Red" start="28" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CEXCR2" description="DCMIPP Pipe1 current exposure control register 2" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MULTB" description="Current exposure multiplier - Blue" start="4" size="8" access="ReadOnly" />
+      <BitField name="SHFB" description="Current exposure shift - Blue" start="12" size="3" access="ReadOnly" />
+      <BitField name="MULTG" description="Current exposure multiplier - Green" start="20" size="8" access="ReadOnly" />
+      <BitField name="SHFG" description="Current exposure shift - Green" start="28" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST1CR" description="DCMIPP Pipe1 current statistics 1 control register" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current enable bit value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Current source of statistics" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Current statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Current accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST2CR" description="DCMIPP Pipe1 current statistics 2 control register" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CST3CR" description="DCMIPP Pipe1 current statistics 3 control register" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disabled: statistics are not accumulated." start="0x0" />
+        <Enum name="B_0x1" description="Enable: statistics are accumulated" start="0x1" />
+      </BitField>
+      <BitField name="BINS" description="Current bin definition" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="AllPixels: Accu is incremented of Component, if 0 less than or equal to Component less than 256" start="0x0" />
+        <Enum name="B_0x1" description="NoExt16: Accu is incremented of Component, if 16 less than or equal to Component less than 240" start="0x1" />
+      </BitField>
+      <BitField name="SRC" description="Statistics source" start="4" size="3" access="ReadOnly" />
+      <BitField name="MODE" description="Statistics mode" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Average: accumulates the 8-bit component value of the considered pixel components." start="0x0" />
+        <Enum name="B_0x1" description="Bins: accumulates 256 for each considered pixel component fitting a bin dynamic." start="0x1" />
+      </BitField>
+      <BitField name="ACCU" description="Accumulation result, divided by 256." start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CSTSTR" description="DCMIPP Pipe1 current statistics window start register" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CSTSZR" description="DCMIPP Pipe1 current statistics window size register" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CROPEN" description="Current CROPEN bit value" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are used to compute the statistics." start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSTART, HSTART, VSIZE, HSIZE, are used for statistics." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCCR" description="DCMIPP Pipe1 current ColorConv configuration register" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current value applied" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ColorConv is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="ColorConv is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TYPE" description="Output samples type used while CLAMP is activated" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="clamped to [16;235] for Y and to [16;240] for U and V" start="0x0" />
+        <Enum name="B_0x1" description="clamped to [16;235] for R, G and B" start="0x1" />
+      </BitField>
+      <BitField name="CLAMP" description="Clamp the output samples" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not activated (clamped to [0;255] by default)" start="0x0" />
+        <Enum name="B_0x1" description="Activated, depending on TYPE" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCCRR1" description="DCMIPP Pipe1 current ColorConv red coefficient register 1" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RR" description="Current coefficient row 1 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="RG" description="Current coefficient row 1 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCRR2" description="DCMIPP Pipe1 current ColorConv red coefficient register 2" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RB" description="Current coefficient row 1 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="RA" description="Current coefficient row 1 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCGR1" description="DCMIPP Pipe1 current ColorConv green coefficient register 1" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GR" description="Current coefficient row 2 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="GG" description="Current coefficient row 2 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCGR2" description="DCMIPP Pipe1 current ColorConv green coefficient register 2" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="Current coefficient row 2 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="GA" description="Current coefficient row 2 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCBR1" description="DCMIPP Pipex current ColorConv blue coefficient register 1" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Current coefficient row 3 column 1 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="BG" description="Current coefficient row 3 column 2 of the matrix" start="16" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCCBR2" description="DCMIPP Pipe1 current ColorConv blue coefficient register 2" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BB" description="Current coefficient row 3 column 3 of the matrix" start="0" size="11" access="ReadOnly" />
+      <BitField name="BA" description="Current coefficient row 3 of the added column (signed integer value)" start="16" size="10" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR1" description="DCMIPP Pipe1 current contrast control register 1" start="+0xAA0" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Current ENABLE bit value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, pixels are forwarded idle." start="0x0" />
+        <Enum name="B_0x1" description="Enable, contrast enhancement is applied on pixels." start="0x1" />
+      </BitField>
+      <BitField name="LUM0" description="Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR2" description="DCMIPP Pipe1 current contrast control register 2" start="+0xAA4" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM4" description="Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16)" start="1" size="6" access="ReadOnly" />
+      <BitField name="LUM3" description="Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+      <BitField name="LUM2" description="Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16)" start="17" size="6" access="ReadOnly" />
+      <BitField name="LUM1" description="Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16)" start="25" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCTCR3" description="DCMIPP Pipe1 current contrast control register 3" start="+0xAA8" size="4" reset_value="0x20202020" reset_mask="0xFFFFFFFF">
+      <BitField name="LUM8" description="Luminance increase for input luminance of 256 (increase is idle with LUMx = 16)" start="1" size="6" access="ReadOnly" />
+      <BitField name="LUM7" description="Luminance increase for input luminance of 224 (increase is idle with LUMx = 16)" start="9" size="6" access="ReadOnly" />
+      <BitField name="LUM6" description="Luminance increase for input luminance of 192 (increase is idle with LUMx = 16)" start="17" size="6" access="ReadOnly" />
+      <BitField name="LUM5" description="Luminance increase for input luminance of 160 (increase is idle with LUMx = 16)" start="25" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CFCTCR" description="DCMIPP Pipex current flow control configuration register" start="+0xB00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - Received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CCRSTR" description="DCMIPP Pipex current crop window start register" start="+0xB04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCRSZR" description="DCMIPP Pipex current crop window size register" start="+0xB08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current ENABLE bit value." start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDCCR" description="DCMIPP Pipex current decimation register" start="+0xB0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDSCR" description="DCMIPP Pipex current downsize configuration register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Current horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="ReadOnly" />
+      <BitField name="VDIV" description="Current vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current value of bit ENABLE" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CDSRTIOR" description="DCMIPP Pipex current downsize ratio register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Current horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="ReadOnly" />
+      <BitField name="VRATIO" description="Current vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CDSSZR" description="DCMIPP Pipex current downsize destination size register" start="+0xB18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CCMRICR" description="DCMIPP Pipex current common ROI configuration register" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Current region of interest line size width" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Current region of interest 1 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Current region of interest 2 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Current region of interest 3 enable" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Current region of interest 4 enable" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Current region of interest 5 enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Current region of interest 6 enable" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Current region of interest 7 enable" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Current region of interest 8 enable" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CRI1CR1" description="DCMIPP Pipe1 current ROI1 configuration register 1" start="+0xB24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI1CR2" description="DCMIPP Pipe1 current ROI1 configuration register 2" start="+0xB28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI2CR1" description="DCMIPP Pipe1 current ROI2 configuration register 1" start="+0xB2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI2CR2" description="DCMIPP Pipe1 current ROI2 configuration register 2" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI3CR1" description="DCMIPP Pipe1 current ROI3 configuration register 1" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI3CR2" description="DCMIPP Pipe1 current ROI3 configuration register 2" start="+0xB38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI4CR1" description="DCMIPP Pipe1 current ROI4 configuration register 1" start="+0xB3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI4CR2" description="DCMIPP Pipe1 current ROI4 configuration register 2" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI5CR1" description="DCMIPP Pipe1 current ROI5 configuration register 1" start="+0xB44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI5CR2" description="DCMIPP Pipe1 current ROI5 configuration register 2" start="+0xB48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI6CR1" description="DCMIPP Pipe1 current ROI6 configuration register 1" start="+0xB4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI6CR2" description="DCMIPP Pipe1 current ROI6 configuration register 2" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI7CR1" description="DCMIPP Pipe1 current ROI7 configuration register 1" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI7CR2" description="DCMIPP Pipe1 current ROI7 configuration register 2" start="+0xB58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI8CR1" description="DCMIPP Pipe1 current ROI8 configuration register 1" start="+0xB5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CRI8CR2" description="DCMIPP Pipe1 current ROI8 configuration register 2" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPCR" description="DCMIPP Pipe1 current pixel packer configuration register" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="RGB888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888 (with A = 0xFF)" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888 (with A = 0xFF)" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (32 bpp, FOURCC = AYUV, with A = 0xFF)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (16 bpp, FOURCC = YUYV)" start="0x6" />
+        <Enum name="B_0x7" description="YUV422 2-buffer (16 bpp, FOURCC = none)" start="0x7" />
+        <Enum name="B_0x8" description="YUV420 2-buffer (12 bpp, FOURCC = NV21), NV12 available with SWAPRB = 1" start="0x8" />
+        <Enum name="B_0x9" description="YUV420 3-buffer (12 bpp, FOURCC = YV12)" start="0x9" />
+        <Enum name="B_0xA" description="YUV422 1-buffer (16 bpp, FOURCC = UYVY)" start="0xA" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and U-vs-V components if YUV" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active" start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE Event and Interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after one line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe1 always drains out the pixels to memory address set by DCMIPP_P1PPM0AR1, and DCMIPP_P1PPM1AR1 as well as DCMIPP_P1PPM2AR1 in case of semi-planar or multi-planar buffer configuration" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Output pixels address location switches from DCMIPP_P1PPM0AR1 to DCMIPP_P1PPM0AR2 alternatively on each frame. For the semi- and multi-planar operations, the output pixels switches from/to DCMIPP_P1PPM1AR1 to/from DCMIPP_P1PPM1AR2. Memory buffer switches from/to DCMIPP_P1PPM2AR1 to/from DCMIPP_P1PPM2AR2 for multi-planar operations." start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P1CPPM0AR1" description="DCMIPP Pipe1 current pixel packer Memory0 address register 1" start="+0xBC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM0AR2" description="DCMIPP Pipe1 current pixel packer Memory0 address register 2" start="+0xBC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM0PR" description="DCMIPP Pipex current pixel packer Memory0 pitch register" start="+0xBCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Current number of bytes between the address of two consecutive lines." start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1AR1" description="DCMIPP Pipex current pixel packer Memory1 address register 1" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1AR2" description="DCMIPP Pipex current pixel packer Memory1 address register 2" start="+0xBD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory1 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM1PR" description="DCMIPP Pipex current pixel packer Memory1 pitch register" start="+0xBDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Current number of bytes between the address of two consecutive lines" start="0" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM2AR1" description="DCMIPP Pipex current pixel packer Memory2 address register 1" start="+0xBE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P1CPPM2AR2" description="DCMIPP Pipex current pixel packer Memory2 address register 1" start="+0xBE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M2A" description="Memory 2 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2FSCR" description="DCMIPP Pipe2 flow selection configuration register" start="+0xC04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Data type ID" start="0" size="6" access="Read/Write" />
+      <BitField name="VC" description="Flow selection mode" start="19" size="2" access="Read/Write" />
+      <BitField name="FDTF" description="Force data type format" start="24" size="6" access="Read/Write" />
+      <BitField name="FDTFEN" description="Force data type format enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When the data type DTIDA is detected by the pipe, the real pixel format considered by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Activation of PipeN" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PipeN disabled" start="0x0" />
+        <Enum name="B_0x1" description="PipeN enabled, can start capturing with CPTMODE, CPTREQ, CPTACK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2FCTCR" description="DCMIPP Pipex flow control configuration register" start="+0xD00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous grab mode. The received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame). Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture not requested for next frame" start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CRSTR" description="DCMIPP Pipex crop window start register" start="+0xD04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2CRSZR" description="DCMIPP Pipex crop window size register" start="+0xD08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide. If the value is maintained at 0 when enabling the crop by means of the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high. If the value is maintained at 0 when enabling the crop thanks to the ENABLE bit, the value is forced internally at 0xFFE, which is the maximum value." start="16" size="12" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DCCR" description="DCMIPP Pipex decimation register" start="+0xD0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DSCR" description="DCMIPP Pipex downsize configuration register" start="+0xD10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="Read/Write" />
+      <BitField name="VDIV" description="Vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="Read/Write" />
+      <BitField name="ENABLE" description="None" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2DSRTIOR" description="DCMIPP Pipex downsize ratio register" start="+0xD14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="Read/Write" />
+      <BitField name="VRATIO" description="Vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2DSSZR" description="DCMIPP Pipex downsize destination size register" start="+0xD18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2CMRICR" description="DCMIPP Pipex common ROI configuration register" start="+0xD20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Region of interest line size width" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Region of interest 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Region of interest 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Region of interest 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Region of interest 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Region of interest 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Region of interest 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Region of interest 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Region of interest 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2RI1CR1" description="DCMIPP Pipe2 ROI1 configuration register 1" start="+0xD24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI1CR2" description="DCMIPP Pipe2 ROI1 configuration register 2" start="+0xD28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI2CR1" description="DCMIPP Pipe2 ROI2 configuration register 1" start="+0xD2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI2CR2" description="DCMIPP Pipe2 ROI2 configuration register 2" start="+0xD30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI3CR1" description="DCMIPP Pipe2 ROI3 configuration register 1" start="+0xD34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI3CR2" description="DCMIPP Pipe2 ROI3 configuration register 2" start="+0xD38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI4CR1" description="DCMIPP Pipe2 ROI4 configuration register 1" start="+0xD3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI4CR2" description="DCMIPP Pipe2 ROI4 configuration register 2" start="+0xD40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI5CR1" description="DCMIPP Pipe2 ROI5 configuration register 1" start="+0xD44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI5CR2" description="DCMIPP Pipe2 ROI5 configuration register 2" start="+0xD48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI6CR1" description="DCMIPP Pipe2 ROI6 configuration register 1" start="+0xD4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI6CR2" description="DCMIPP Pipe2 ROI6 configuration register 2" start="+0xD50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI7CR1" description="DCMIPP Pipe2 ROI7 configuration register 1" start="+0xD54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI7CR2" description="DCMIPP Pipe2 ROI7 configuration register 2" start="+0xD58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI8CR1" description="DCMIPP Pipe2 ROI8 configuration register 1" start="+0xD5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="CLB" description="Color line blue" start="12" size="2" access="Read/Write" />
+      <BitField name="CLG" description="Color line green" start="14" size="2" access="Read/Write" />
+      <BitField name="VSTART" description="Vertical start, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+      <BitField name="CLR" description="Color line red" start="28" size="2" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2RI8CR2" description="DCMIPP Pipe2 ROI8 configuration register 2" start="+0xD60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="Read/Write" />
+      <BitField name="VSIZE" description="Vertical size, from 0 to 4094 pixels high" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2GMCR" description="DCMIPP Pipex gamma configuration register" start="+0xD70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Gamma is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2PPCR" description="DCMIPP Pipe2 pixel packer configuration register" start="+0xDC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format (only coplanar formats are supported in Pipe2)" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="RG/B888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (FOURCC = AYUV)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (FOURCC = YUYV)" start="0x6" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active." start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe2 is always dump to memory address set by DCMIPP_P2PPM0AR1" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P2PPM0AR1 register to DCMIPP_P2PPM0AR2 register alternatively on each frame" start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2PPM0AR1" description="DCMIPP Pipe2 pixel packer Memory0 address register 1" start="+0xDC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2PPM0AR2" description="DCMIPP Pipe2 pixel packer Memory0 address register 2" start="+0xDC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2PPM0PR" description="DCMIPP Pipex pixel packer Memory0 pitch register" start="+0xDCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PITCH" description="Number of bytes between the address of two consecutive lines." start="0" size="15" access="Read/Write" />
+    </Register>
+    <Register name="DCMIPP_P2STM0AR" description="DCMIPP Pipex status Memory0 address register" start="+0xDD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2IER" description="DCMIPP Pipe2 interrupt enable register" start="+0xDF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEIE" description="Multi-line capture completed interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation when the line is received" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a group of lines (or last line reached)" start="0x1" />
+      </BitField>
+      <BitField name="FRAMEIE" description="Frame capture completed interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated after the full capture of a cropped frame" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCIE" description="VSYNC interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated on each VSYNC (captured or not)" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2SR" description="DCMIPP Pipe2 status register" start="+0xDF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINEF" description="Multi-line capture completed raw interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRAMEF" description="Frame capture completed raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No capture or ongoing capture" start="0x0" />
+        <Enum name="B_0x1" description="All data of a frame have been captured" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCF" description="VSYNC raw interrupt status" start="2" size="1" access="ReadOnly" />
+      <BitField name="OVRF" description="Overrun raw interrupt status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data buffer overrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="A data buffer overrun occurred and data of this frame are corrupted" start="0x1" />
+      </BitField>
+      <BitField name="LSTLINE" description="Last line LSB bit, sampled at frame capture complete event." start="16" size="1" access="ReadOnly" />
+      <BitField name="LSTFRM" description="Last frame LSB bit, sampled at frame capture complete event. The information is extracted from the frame data number which can be delivered by the camera through the CSI2 interface." start="17" size="1" access="ReadOnly" />
+      <BitField name="CPTACT" description="Capture immediate status" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture currently inactive" start="0x0" />
+        <Enum name="B_0x1" description="Capture currently active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2FCR" description="DCMIPP Pipe2 interrupt clear register" start="+0xDFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLINEF" description="Multi-line capture complete interrupt status clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="CFRAMEF" description="Frame capture complete interrupt status clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="CVSYNCF" description="Vertical synchronization interrupt status clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="COVRF" description="Overrun interrupt status clear" start="7" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CFSCR" description="DCMIPP Pipe2 current flow selection configuration register" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTIDA" description="Current data type ID" start="0" size="6" access="ReadOnly" />
+      <BitField name="VC" description="Current flow selection mode" start="19" size="2" access="ReadOnly" />
+      <BitField name="FDTF" description="Current force data type format" start="24" size="6" access="ReadOnly" />
+      <BitField name="FDTFEN" description="Current force data type format enable" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable force data type format. The data type format used by the pipe is the one defined into DTIDx" start="0x0" />
+        <Enum name="B_0x1" description="Enable force data type format. When data type DTIDA is detected by the pipe, the real pixel format considering by the pipe is the one set into the FDTF[5:0] bit field instead of the physical one received by the CSI2 host." start="0x1" />
+      </BitField>
+      <BitField name="PIPEN" description="Current activation of PipeN" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Pipe disabled" start="0x0" />
+        <Enum name="B_0x1" description="Pipe enabled, can start capturing with CPTMODE, CPTREQ, CPTACK." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CFCTCR" description="DCMIPP Pipex current flow control configuration register" start="+0xF00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRATE" description="Frame capture rate control" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="All frames are captured" start="0x0" />
+        <Enum name="B_0x1" description="One out of two frames captured (50% bandwidth reduction)" start="0x1" />
+        <Enum name="B_0x2" description="One out of four frames captured (75% bandwidth reduction)" start="0x2" />
+        <Enum name="B_0x3" description="One out of eight frames captured (87% bandwidth reduction)" start="0x3" />
+      </BitField>
+      <BitField name="CPTMODE" description="Capture mode" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Continuous grab mode - Received data are transferred into the destination memory through the AXI master." start="0x0" />
+        <Enum name="B_0x1" description="Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset." start="0x1" />
+      </BitField>
+      <BitField name="CPTREQ" description="Capture requested" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Capture not requested for next frame." start="0x0" />
+        <Enum name="B_0x1" description="Capture requested for next frame." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CCRSTR" description="DCMIPP Pipex current crop window start register" start="+0xF04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CCRSZR" description="DCMIPP Pipex current crop window size register" start="+0xF08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current ENABLE bit value." start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Bypass, all pixels are transmitted through (no need to set any start and size values)" start="0x0" />
+        <Enum name="B_0x1" description="Enable, only the rectangle defined by VSIZE, HSIZE, VSTART, HSTART is transmitted." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDCCR" description="DCMIPP Pipex current decimation register" start="+0xF0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bypass: decimation is not active, all pixels are transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC" start="0x1" />
+      </BitField>
+      <BitField name="HDEC" description="Horizontal decimation ratio" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no horizontal decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+      <BitField name="VDEC" description="Vertical decimation ratio" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="All pixels are transmitted, no vertical decimation" start="0x0" />
+        <Enum name="B_0x1" description="One line out of two transmitted" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDSCR" description="DCMIPP Pipex current downsize configuration register" start="+0xF10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDIV" description="Current horizontal division factor, from 128 (8x) to 1023 (1x)" start="0" size="10" access="ReadOnly" />
+      <BitField name="VDIV" description="Current vertical division factor, from 128 (8x) to 1023 (1x)" start="16" size="10" access="ReadOnly" />
+      <BitField name="ENABLE" description="Current value of bit ENABLE" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Down scaler is bypassed" start="0x0" />
+        <Enum name="B_0x1" description="Down scaler is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CDSRTIOR" description="DCMIPP Pipex current downsize ratio register" start="+0xF14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HRATIO" description="Current horizontal ratio, from 8192 (1x) to 65535 (8x)" start="0" size="16" access="ReadOnly" />
+      <BitField name="VRATIO" description="Current vertical ratio, from 8192 (1x) to 65535 (8x)" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CDSSZR" description="DCMIPP Pipex current downsize destination size register" start="+0xF18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CCMRICR" description="DCMIPP Pipex current common ROI configuration register" start="+0xF20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROILSZ" description="Current region of interest line size width" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Line width 1 pixel" start="0x0" />
+        <Enum name="B_0x1" description="Line width 2 pixels" start="0x1" />
+        <Enum name="B_0x2" description="Line width 4 pixels" start="0x2" />
+        <Enum name="B_0x3" description="Line width 8 pixels" start="0x3" />
+      </BitField>
+      <BitField name="ROI1EN" description="Current region of interest 1 enable" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI2EN" description="Current region of interest 2 enable" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI3EN" description="Current region of interest 3 enable" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI4EN" description="Current region of interest 4 enable" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI5EN" description="Current region of interest 5 enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI6EN" description="Current region of interest 6 enable" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI7EN" description="Current region of interest 7 enable" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+      <BitField name="ROI8EN" description="Current region of interest 8 enable" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable ROI" start="0x0" />
+        <Enum name="B_0x1" description="Enable ROI" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CRI1CR1" description="DCMIPP Pipe2 current ROI1 configuration register 1" start="+0xF24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI1CR2" description="DCMIPP Pipe2 current ROI1 configuration register 2" start="+0xF28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI2CR1" description="DCMIPP Pipe2 current ROI2 configuration register 1" start="+0xF2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI2CR2" description="DCMIPP Pipe2 current ROI2 configuration register 2" start="+0xF30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI3CR1" description="DCMIPP Pipe2 current ROI3 configuration register 1" start="+0xF34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI3CR2" description="DCMIPP Pipe2 current ROI3 configuration register 2" start="+0xF38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI4CR1" description="DCMIPP Pipe2 current ROI4 configuration register 1" start="+0xF3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI4CR2" description="DCMIPP Pipe2 current ROI4 configuration register 2" start="+0xF40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI5CR1" description="DCMIPP Pipe2 current ROI5 configuration register 1" start="+0xF44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI5CR2" description="DCMIPP Pipe2 current ROI5 configuration register 2" start="+0xF48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI6CR1" description="DCMIPP Pipe2 current ROI6 configuration register 1" start="+0xF4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI6CR2" description="DCMIPP Pipe2 current ROI6 configuration register 2" start="+0xF50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI7CR1" description="DCMIPP Pipe2 current ROI7 configuration register 1" start="+0xF54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI7CR2" description="DCMIPP Pipe2 current ROI7 configuration register 2" start="+0xF58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI8CR1" description="DCMIPP Pipe2 current ROI8 configuration register 1" start="+0xF5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSTART" description="Current horizontal start, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="CLB" description="Current color line blue" start="12" size="2" access="ReadOnly" />
+      <BitField name="CLG" description="Current color line green" start="14" size="2" access="ReadOnly" />
+      <BitField name="VSTART" description="Current vertical start, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+      <BitField name="CLR" description="Current color line red" start="28" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CRI8CR2" description="DCMIPP Pipe2 current ROI8 configuration register 2" start="+0xF60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIZE" description="Current horizontal size, from 0 to 4094 pixels wide" start="0" size="12" access="ReadOnly" />
+      <BitField name="VSIZE" description="Current vertical size, from 0 to 4094 pixels high" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CPPCR" description="DCMIPP Pipe2 current pixel packer configuration register" start="+0xFC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORMAT" description="Memory format (only coplanar formats are supported in Pipe2)" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="RG/B888 or YUV444 1-buffer" start="0x0" />
+        <Enum name="B_0x1" description="RGB565 1-buffer" start="0x1" />
+        <Enum name="B_0x2" description="ARGB8888" start="0x2" />
+        <Enum name="B_0x3" description="RGBA8888" start="0x3" />
+        <Enum name="B_0x4" description="monochrome Y8 or G8 1-buffer" start="0x4" />
+        <Enum name="B_0x5" description="YUV444 1-buffer (FOURCC = AYUV)" start="0x5" />
+        <Enum name="B_0x6" description="YUV422 1-buffer (FOURCC = YUYV)" start="0x6" />
+      </BitField>
+      <BitField name="SWAPRB" description="Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No swap of R-vs-B (U-vs-V)" start="0x0" />
+        <Enum name="B_0x1" description="Swap active." start="0x1" />
+      </BitField>
+      <BitField name="LINEMULT" description="Amount of capture completed lines for LINE event and interrupt" start="13" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Event after every line" start="0x0" />
+        <Enum name="B_0x1" description="Event after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Event after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Event after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Event after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Event after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Event after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Event after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="DBM" description="Double buffer mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double buffer mode activated. Pipe2 is always dump to memory address set by DCMIPP_P2PPM0AR1" start="0x0" />
+        <Enum name="B_0x1" description="Double buffer mode activated. Dump address location switches from DCMIPP_P2PPM0AR1 register to DCMIPP_P2PPM0AR2 register alternatively on each frame" start="0x1" />
+      </BitField>
+      <BitField name="LMAWM" description="Line multi address wrapping modulo" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Wraps address after every line" start="0x0" />
+        <Enum name="B_0x1" description="Wraps address after two lines" start="0x1" />
+        <Enum name="B_0x2" description="Wraps address after four lines" start="0x2" />
+        <Enum name="B_0x3" description="Wraps address after eight lines" start="0x3" />
+        <Enum name="B_0x4" description="Wraps address after sixteen lines" start="0x4" />
+        <Enum name="B_0x5" description="Wraps address after 32 lines" start="0x5" />
+        <Enum name="B_0x6" description="Wraps address after 64 lines" start="0x6" />
+        <Enum name="B_0x7" description="Wraps address after 128 lines" start="0x7" />
+      </BitField>
+      <BitField name="LMAWE" description="Line multi address wrapping enable bit" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Line multi address wrapping disabled." start="0x0" />
+        <Enum name="B_0x1" description="Line multi address wrapping enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DCMIPP_P2CPPM0AR1" description="DCMIPP Pipe2 current pixel packer Memory0 address register 1" start="+0xFC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="DCMIPP_P2CPPM0AR2" description="DCMIPP Pipe2 current pixel packer Memory0 address register 2" start="+0xFC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory0 address" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DLYBSD" description="DLYBSD address block description" start="0x48028000">
+    <Register name="DLYBSD_CFG" description="Delay block SDMMC DLL configuration" start="+0x0" size="4" access="Read/Write" reset_value="0x00400000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_EN" description="DLL enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL" description="selection of RX delay" start="1" size="6" access="Read/Write" />
+      <BitField name="SDMMC_DLL_BYP_EN" description="DLL configuration" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lock mode" start="0x0" />
+        <Enum name="B_0x1" description="Pure delay" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC_DLL_BYP_CMD" description="Bypass command" start="17" size="5" access="Read/Write" />
+      <BitField name="SDMMC_DLL_ANTIGLITCH_EN" description="Antiglitch logic enabled when 1" start="22" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DLYBSD_STATUS" description="Delay block SDMMC DLL status" start="+0x4" size="4" access="Read/Write" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_LOCK" description="SDMMC DLL lock" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL_ACK" description="SDMMC RX delay selection acknowledge" start="1" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DLYBSD_S" description="DLYBSD address block description" start="0x58028000">
+    <Register name="DLYBSD_CFG" description="Delay block SDMMC DLL configuration" start="+0x0" size="4" access="Read/Write" reset_value="0x00400000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_EN" description="DLL enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL" description="selection of RX delay" start="1" size="6" access="Read/Write" />
+      <BitField name="SDMMC_DLL_BYP_EN" description="DLL configuration" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lock mode" start="0x0" />
+        <Enum name="B_0x1" description="Pure delay" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC_DLL_BYP_CMD" description="Bypass command" start="17" size="5" access="Read/Write" />
+      <BitField name="SDMMC_DLL_ANTIGLITCH_EN" description="Antiglitch logic enabled when 1" start="22" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DLYBSD_STATUS" description="Delay block SDMMC DLL status" start="+0x4" size="4" access="Read/Write" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_LOCK" description="SDMMC DLL lock" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL_ACK" description="SDMMC RX delay selection acknowledge" start="1" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DLYBSD2" description="DLYBSD address block description" start="0x48026C00">
+    <Register name="DLYBSD_CFG" description="Delay block SDMMC DLL configuration" start="+0x0" size="4" access="Read/Write" reset_value="0x00400000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_EN" description="DLL enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL" description="selection of RX delay" start="1" size="6" access="Read/Write" />
+      <BitField name="SDMMC_DLL_BYP_EN" description="DLL configuration" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lock mode" start="0x0" />
+        <Enum name="B_0x1" description="Pure delay" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC_DLL_BYP_CMD" description="Bypass command" start="17" size="5" access="Read/Write" />
+      <BitField name="SDMMC_DLL_ANTIGLITCH_EN" description="Antiglitch logic enabled when 1" start="22" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DLYBSD_STATUS" description="Delay block SDMMC DLL status" start="+0x4" size="4" access="Read/Write" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_LOCK" description="SDMMC DLL lock" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL_ACK" description="SDMMC RX delay selection acknowledge" start="1" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DLYBSD2_S" description="DLYBSD address block description" start="0x58026C00">
+    <Register name="DLYBSD_CFG" description="Delay block SDMMC DLL configuration" start="+0x0" size="4" access="Read/Write" reset_value="0x00400000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_EN" description="DLL enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL" description="selection of RX delay" start="1" size="6" access="Read/Write" />
+      <BitField name="SDMMC_DLL_BYP_EN" description="DLL configuration" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lock mode" start="0x0" />
+        <Enum name="B_0x1" description="Pure delay" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC_DLL_BYP_CMD" description="Bypass command" start="17" size="5" access="Read/Write" />
+      <BitField name="SDMMC_DLL_ANTIGLITCH_EN" description="Antiglitch logic enabled when 1" start="22" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DLYBSD_STATUS" description="Delay block SDMMC DLL status" start="+0x4" size="4" access="Read/Write" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC_DLL_LOCK" description="SDMMC DLL lock" start="0" size="1" access="Read/Write" />
+      <BitField name="SDMMC_RX_TAP_SEL_ACK" description="SDMMC RX delay selection acknowledge" start="1" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMA2D" description="Chrom-ART Accelerator controller" start="0x48021000">
+    <Register name="DMA2D_CR" description="DMA2D control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="START" description="Start" start="0" size="1" access="Read/Write" />
+      <BitField name="SUSP" description="Suspend" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer not suspended" start="0x0" />
+        <Enum name="B_0x1" description="Transfer suspended" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transfer abort requested" start="0x0" />
+        <Enum name="B_0x1" description="Transfer abort requested" start="0x1" />
+      </BitField>
+      <BitField name="LOM" description="Line offset mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line offsets expressed in pixels" start="0x0" />
+        <Enum name="B_0x1" description="Line offsets expressed in bytes" start="0x1" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error (TE) interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete (TC) interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TWIE" description="Transfer watermark (TW) interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TW interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TW interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CAEIE" description="CLUT access error (CAE) interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CAE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTCIE" description="CLUT transfer complete (CTC) interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CEIE" description="Configuration error (CE) interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="DMA2D mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Memory-to-memory (FG fetch only)" start="0x0" />
+        <Enum name="B_0x1" description="Memory-to-memory with PFC (FG fetch only with FG PFC active)" start="0x1" />
+        <Enum name="B_0x2" description="Memory-to-memory with blending (FG and BG fetch with PFC and blending)" start="0x2" />
+        <Enum name="B_0x3" description="Register-to-memory (no FG nor BG, only output stage active)" start="0x3" />
+        <Enum name="B_0x4" description="Memory-to-memory with blending and fixed color FG (BG fetch only with FG and BG PFC active)" start="0x4" />
+        <Enum name="B_0x5" description="Memory-to-memory with blending and fixed color BG (FG fetch only with FG and BG PFC active)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="DMA2D_ISR" description="DMA2D interrupt status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF" description="Transfer error interrupt flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCIF" description="Transfer complete interrupt flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TWIF" description="Transfer watermark interrupt flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="CAEIF" description="CLUT access error interrupt flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="CTCIF" description="CLUT transfer complete interrupt flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="CEIF" description="Configuration error interrupt flag" start="5" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DMA2D_IFCR" description="DMA2D interrupt flag clear register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF" description="Clear transfer error interrupt flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CTCIF" description="Clear transfer complete interrupt flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CTWIF" description="Clear transfer watermark interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CAECIF" description="Clear CLUT access error interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CCTCIF" description="Clear CLUT transfer complete interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="CCEIF" description="Clear configuration error interrupt flag" start="5" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGMAR" description="DMA2D foreground memory address register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address, address of the data used for the foreground image" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGOR" description="DMA2D foreground offset register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGMAR" description="DMA2D background memory address register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address, address of the data used for the background image" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGOR" description="DMA2D background offset register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGPFCCR" description="DMA2D foreground PFC control register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+        <Enum name="B_0x5" description="L8" start="0x5" />
+        <Enum name="B_0x6" description="AL44" start="0x6" />
+        <Enum name="B_0x7" description="AL88" start="0x7" />
+        <Enum name="B_0x8" description="L4" start="0x8" />
+        <Enum name="B_0x9" description="A8" start="0x9" />
+        <Enum name="B_0xA" description="A4" start="0xA" />
+        <Enum name="B_0xB" description="YCbCr" start="0xB" />
+      </BitField>
+      <BitField name="CCM" description="CLUT color mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start" start="5" size="1" access="Read/Write" />
+      <BitField name="CS" description="CLUT size" start="8" size="8" access="Read/Write" />
+      <BitField name="AM" description="Alpha mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No modification of the foreground image alpha channel value" start="0x0" />
+        <Enum name="B_0x1" description="Replace original foreground image alpha channel value by ALPHA[7: 0]" start="0x1" />
+        <Enum name="B_0x2" description="Replace original foreground image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value" start="0x2" />
+      </BitField>
+      <BitField name="CSS" description="Chroma subsampling" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="4:4:4 (no chroma subsampling)" start="0x0" />
+        <Enum name="B_0x1" description="4:2:2" start="0x1" />
+        <Enum name="B_0x2" description="4:2:0" start="0x2" />
+      </BitField>
+      <BitField name="AI" description="Alpha inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+      <BitField name="ALPHA" description="Alpha value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCOLR" description="DMA2D foreground color register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value for the A4 or A8 mode of the foreground image" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value for the A4 or A8 mode of the foreground image" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value for the A4 or A8 mode of the foreground image" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGPFCCR" description="DMA2D background PFC control register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+        <Enum name="B_0x5" description="L8" start="0x5" />
+        <Enum name="B_0x6" description="AL44" start="0x6" />
+        <Enum name="B_0x7" description="AL88" start="0x7" />
+        <Enum name="B_0x8" description="L4" start="0x8" />
+        <Enum name="B_0x9" description="A8" start="0x9" />
+        <Enum name="B_0xA" description="A4" start="0xA" />
+      </BitField>
+      <BitField name="CCM" description="CLUT color mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start" start="5" size="1" access="Read/Write" />
+      <BitField name="CS" description="CLUT size" start="8" size="8" access="Read/Write" />
+      <BitField name="AM" description="Alpha mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No modification of the foreground image alpha channel value" start="0x0" />
+        <Enum name="B_0x1" description="Replace original background image alpha channel value by ALPHA[7: 0]" start="0x1" />
+        <Enum name="B_0x2" description="Replace original background image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value" start="0x2" />
+      </BitField>
+      <BitField name="AI" description="Alpha Inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+      <BitField name="ALPHA" description="Alpha value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCOLR" description="DMA2D background color register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value for the A4 or A8 mode of the background" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value for the A4 or A8 mode of the background" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value for the A4 or A8 mode of the background" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCMAR" description="DMA2D foreground CLUT memory address register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCMAR" description="DMA2D background CLUT memory address register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OPFCCR" description="DMA2D output PFC control register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+      </BitField>
+      <BitField name="SB" description="Swap bytes" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bytes in regular order in the output FIFO" start="0x0" />
+        <Enum name="B_0x1" description="Bytes swapped two by two in the output FIFO" start="0x1" />
+      </BitField>
+      <BitField name="AI" description="Alpha Inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DMA2D_OCOLR_RGB888" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB8888 or RGB888" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB8888 or RGB888" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB8888 or RGB888 mode" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_RGB565" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in RGB565 mode" start="0" size="5" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in RGB565 mode" start="5" size="6" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in RGB565 mode" start="11" size="5" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_ARGB1555" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB1555 mode" start="0" size="5" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB1555 mode" start="5" size="5" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB1555 mode" start="10" size="5" access="Read/Write" />
+      <BitField name="A" description="Alpha channel value of the output color in ARGB1555 mode" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_ARGB4444" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB4444 mode" start="0" size="4" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB4444 mode" start="4" size="4" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB4444 mode" start="8" size="4" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha channel of the output color value in ARGB4444" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OMAR" description="DMA2D output memory address register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OOR" description="DMA2D output offset register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_NLR" description="DMA2D number of line register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NL" description="Number of lines of the area to be transferred." start="0" size="16" access="Read/Write" />
+      <BitField name="PL" description="Pixel per lines per lines of the area to be transferred" start="16" size="14" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_LWR" description="DMA2D line watermark register" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LW" description="Line watermark for interrupt generation" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_AMTCR" description="DMA2D AXI master timer configuration register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Dead-time functionality enable" start="0" size="1" access="Read/Write" />
+      <BitField name="DT" description="Dead time" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT0" description="DMA2D foreground CLUT" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT1" description="DMA2D foreground CLUT" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT2" description="DMA2D foreground CLUT" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT3" description="DMA2D foreground CLUT" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT4" description="DMA2D foreground CLUT" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT5" description="DMA2D foreground CLUT" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT6" description="DMA2D foreground CLUT" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT7" description="DMA2D foreground CLUT" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT8" description="DMA2D foreground CLUT" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT9" description="DMA2D foreground CLUT" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT10" description="DMA2D foreground CLUT" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT11" description="DMA2D foreground CLUT" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT12" description="DMA2D foreground CLUT" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT13" description="DMA2D foreground CLUT" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT14" description="DMA2D foreground CLUT" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT15" description="DMA2D foreground CLUT" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT16" description="DMA2D foreground CLUT" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT17" description="DMA2D foreground CLUT" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT18" description="DMA2D foreground CLUT" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT19" description="DMA2D foreground CLUT" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT20" description="DMA2D foreground CLUT" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT21" description="DMA2D foreground CLUT" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT22" description="DMA2D foreground CLUT" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT23" description="DMA2D foreground CLUT" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT24" description="DMA2D foreground CLUT" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT25" description="DMA2D foreground CLUT" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT26" description="DMA2D foreground CLUT" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT27" description="DMA2D foreground CLUT" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT28" description="DMA2D foreground CLUT" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT29" description="DMA2D foreground CLUT" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT30" description="DMA2D foreground CLUT" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT31" description="DMA2D foreground CLUT" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT32" description="DMA2D foreground CLUT" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT33" description="DMA2D foreground CLUT" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT34" description="DMA2D foreground CLUT" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT35" description="DMA2D foreground CLUT" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT36" description="DMA2D foreground CLUT" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT37" description="DMA2D foreground CLUT" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT38" description="DMA2D foreground CLUT" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT39" description="DMA2D foreground CLUT" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT40" description="DMA2D foreground CLUT" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT41" description="DMA2D foreground CLUT" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT42" description="DMA2D foreground CLUT" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT43" description="DMA2D foreground CLUT" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT44" description="DMA2D foreground CLUT" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT45" description="DMA2D foreground CLUT" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT46" description="DMA2D foreground CLUT" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT47" description="DMA2D foreground CLUT" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT48" description="DMA2D foreground CLUT" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT49" description="DMA2D foreground CLUT" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT50" description="DMA2D foreground CLUT" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT51" description="DMA2D foreground CLUT" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT52" description="DMA2D foreground CLUT" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT53" description="DMA2D foreground CLUT" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT54" description="DMA2D foreground CLUT" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT55" description="DMA2D foreground CLUT" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT56" description="DMA2D foreground CLUT" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT57" description="DMA2D foreground CLUT" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT58" description="DMA2D foreground CLUT" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT59" description="DMA2D foreground CLUT" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT60" description="DMA2D foreground CLUT" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT61" description="DMA2D foreground CLUT" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT62" description="DMA2D foreground CLUT" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT63" description="DMA2D foreground CLUT" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT64" description="DMA2D foreground CLUT" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT65" description="DMA2D foreground CLUT" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT66" description="DMA2D foreground CLUT" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT67" description="DMA2D foreground CLUT" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT68" description="DMA2D foreground CLUT" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT69" description="DMA2D foreground CLUT" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT70" description="DMA2D foreground CLUT" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT71" description="DMA2D foreground CLUT" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT72" description="DMA2D foreground CLUT" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT73" description="DMA2D foreground CLUT" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT74" description="DMA2D foreground CLUT" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT75" description="DMA2D foreground CLUT" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT76" description="DMA2D foreground CLUT" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT77" description="DMA2D foreground CLUT" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT78" description="DMA2D foreground CLUT" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT79" description="DMA2D foreground CLUT" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT80" description="DMA2D foreground CLUT" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT81" description="DMA2D foreground CLUT" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT82" description="DMA2D foreground CLUT" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT83" description="DMA2D foreground CLUT" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT84" description="DMA2D foreground CLUT" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT85" description="DMA2D foreground CLUT" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT86" description="DMA2D foreground CLUT" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT87" description="DMA2D foreground CLUT" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT88" description="DMA2D foreground CLUT" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT89" description="DMA2D foreground CLUT" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT90" description="DMA2D foreground CLUT" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT91" description="DMA2D foreground CLUT" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT92" description="DMA2D foreground CLUT" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT93" description="DMA2D foreground CLUT" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT94" description="DMA2D foreground CLUT" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT95" description="DMA2D foreground CLUT" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT96" description="DMA2D foreground CLUT" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT97" description="DMA2D foreground CLUT" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT98" description="DMA2D foreground CLUT" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT99" description="DMA2D foreground CLUT" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT100" description="DMA2D foreground CLUT" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT101" description="DMA2D foreground CLUT" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT102" description="DMA2D foreground CLUT" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT103" description="DMA2D foreground CLUT" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT104" description="DMA2D foreground CLUT" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT105" description="DMA2D foreground CLUT" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT106" description="DMA2D foreground CLUT" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT107" description="DMA2D foreground CLUT" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT108" description="DMA2D foreground CLUT" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT109" description="DMA2D foreground CLUT" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT110" description="DMA2D foreground CLUT" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT111" description="DMA2D foreground CLUT" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT112" description="DMA2D foreground CLUT" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT113" description="DMA2D foreground CLUT" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT114" description="DMA2D foreground CLUT" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT115" description="DMA2D foreground CLUT" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT116" description="DMA2D foreground CLUT" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT117" description="DMA2D foreground CLUT" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT118" description="DMA2D foreground CLUT" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT119" description="DMA2D foreground CLUT" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT120" description="DMA2D foreground CLUT" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT121" description="DMA2D foreground CLUT" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT122" description="DMA2D foreground CLUT" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT123" description="DMA2D foreground CLUT" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT124" description="DMA2D foreground CLUT" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT125" description="DMA2D foreground CLUT" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT126" description="DMA2D foreground CLUT" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT127" description="DMA2D foreground CLUT" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT128" description="DMA2D foreground CLUT" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT129" description="DMA2D foreground CLUT" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT130" description="DMA2D foreground CLUT" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT131" description="DMA2D foreground CLUT" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT132" description="DMA2D foreground CLUT" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT133" description="DMA2D foreground CLUT" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT134" description="DMA2D foreground CLUT" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT135" description="DMA2D foreground CLUT" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT136" description="DMA2D foreground CLUT" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT137" description="DMA2D foreground CLUT" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT138" description="DMA2D foreground CLUT" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT139" description="DMA2D foreground CLUT" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT140" description="DMA2D foreground CLUT" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT141" description="DMA2D foreground CLUT" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT142" description="DMA2D foreground CLUT" start="+0x638" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT143" description="DMA2D foreground CLUT" start="+0x63C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT144" description="DMA2D foreground CLUT" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT145" description="DMA2D foreground CLUT" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT146" description="DMA2D foreground CLUT" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT147" description="DMA2D foreground CLUT" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT148" description="DMA2D foreground CLUT" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT149" description="DMA2D foreground CLUT" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT150" description="DMA2D foreground CLUT" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT151" description="DMA2D foreground CLUT" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT152" description="DMA2D foreground CLUT" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT153" description="DMA2D foreground CLUT" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT154" description="DMA2D foreground CLUT" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT155" description="DMA2D foreground CLUT" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT156" description="DMA2D foreground CLUT" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT157" description="DMA2D foreground CLUT" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT158" description="DMA2D foreground CLUT" start="+0x678" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT159" description="DMA2D foreground CLUT" start="+0x67C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT160" description="DMA2D foreground CLUT" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT161" description="DMA2D foreground CLUT" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT162" description="DMA2D foreground CLUT" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT163" description="DMA2D foreground CLUT" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT164" description="DMA2D foreground CLUT" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT165" description="DMA2D foreground CLUT" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT166" description="DMA2D foreground CLUT" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT167" description="DMA2D foreground CLUT" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT168" description="DMA2D foreground CLUT" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT169" description="DMA2D foreground CLUT" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT170" description="DMA2D foreground CLUT" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT171" description="DMA2D foreground CLUT" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT172" description="DMA2D foreground CLUT" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT173" description="DMA2D foreground CLUT" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT174" description="DMA2D foreground CLUT" start="+0x6B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT175" description="DMA2D foreground CLUT" start="+0x6BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT176" description="DMA2D foreground CLUT" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT177" description="DMA2D foreground CLUT" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT178" description="DMA2D foreground CLUT" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT179" description="DMA2D foreground CLUT" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT180" description="DMA2D foreground CLUT" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT181" description="DMA2D foreground CLUT" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT182" description="DMA2D foreground CLUT" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT183" description="DMA2D foreground CLUT" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT184" description="DMA2D foreground CLUT" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT185" description="DMA2D foreground CLUT" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT186" description="DMA2D foreground CLUT" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT187" description="DMA2D foreground CLUT" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT188" description="DMA2D foreground CLUT" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT189" description="DMA2D foreground CLUT" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT190" description="DMA2D foreground CLUT" start="+0x6F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT191" description="DMA2D foreground CLUT" start="+0x6FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT192" description="DMA2D foreground CLUT" start="+0x700" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT193" description="DMA2D foreground CLUT" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT194" description="DMA2D foreground CLUT" start="+0x708" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT195" description="DMA2D foreground CLUT" start="+0x70C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT196" description="DMA2D foreground CLUT" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT197" description="DMA2D foreground CLUT" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT198" description="DMA2D foreground CLUT" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT199" description="DMA2D foreground CLUT" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT200" description="DMA2D foreground CLUT" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT201" description="DMA2D foreground CLUT" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT202" description="DMA2D foreground CLUT" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT203" description="DMA2D foreground CLUT" start="+0x72C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT204" description="DMA2D foreground CLUT" start="+0x730" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT205" description="DMA2D foreground CLUT" start="+0x734" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT206" description="DMA2D foreground CLUT" start="+0x738" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT207" description="DMA2D foreground CLUT" start="+0x73C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT208" description="DMA2D foreground CLUT" start="+0x740" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT209" description="DMA2D foreground CLUT" start="+0x744" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT210" description="DMA2D foreground CLUT" start="+0x748" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT211" description="DMA2D foreground CLUT" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT212" description="DMA2D foreground CLUT" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT213" description="DMA2D foreground CLUT" start="+0x754" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT214" description="DMA2D foreground CLUT" start="+0x758" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT215" description="DMA2D foreground CLUT" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT216" description="DMA2D foreground CLUT" start="+0x760" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT217" description="DMA2D foreground CLUT" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT218" description="DMA2D foreground CLUT" start="+0x768" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT219" description="DMA2D foreground CLUT" start="+0x76C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT220" description="DMA2D foreground CLUT" start="+0x770" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT221" description="DMA2D foreground CLUT" start="+0x774" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT222" description="DMA2D foreground CLUT" start="+0x778" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT223" description="DMA2D foreground CLUT" start="+0x77C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT224" description="DMA2D foreground CLUT" start="+0x780" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT225" description="DMA2D foreground CLUT" start="+0x784" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT226" description="DMA2D foreground CLUT" start="+0x788" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT227" description="DMA2D foreground CLUT" start="+0x78C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT228" description="DMA2D foreground CLUT" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT229" description="DMA2D foreground CLUT" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT230" description="DMA2D foreground CLUT" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT231" description="DMA2D foreground CLUT" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT232" description="DMA2D foreground CLUT" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT233" description="DMA2D foreground CLUT" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT234" description="DMA2D foreground CLUT" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT235" description="DMA2D foreground CLUT" start="+0x7AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT236" description="DMA2D foreground CLUT" start="+0x7B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT237" description="DMA2D foreground CLUT" start="+0x7B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT238" description="DMA2D foreground CLUT" start="+0x7B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT239" description="DMA2D foreground CLUT" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT240" description="DMA2D foreground CLUT" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT241" description="DMA2D foreground CLUT" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT242" description="DMA2D foreground CLUT" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT243" description="DMA2D foreground CLUT" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT244" description="DMA2D foreground CLUT" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT245" description="DMA2D foreground CLUT" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT246" description="DMA2D foreground CLUT" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT247" description="DMA2D foreground CLUT" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT248" description="DMA2D foreground CLUT" start="+0x7E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT249" description="DMA2D foreground CLUT" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT250" description="DMA2D foreground CLUT" start="+0x7E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT251" description="DMA2D foreground CLUT" start="+0x7EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT252" description="DMA2D foreground CLUT" start="+0x7F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT253" description="DMA2D foreground CLUT" start="+0x7F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT254" description="DMA2D foreground CLUT" start="+0x7F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT255" description="DMA2D foreground CLUT" start="+0x7FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT0" description="DMA2D background CLUT" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT1" description="DMA2D background CLUT" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT2" description="DMA2D background CLUT" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT3" description="DMA2D background CLUT" start="+0x80C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT4" description="DMA2D background CLUT" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT5" description="DMA2D background CLUT" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT6" description="DMA2D background CLUT" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT7" description="DMA2D background CLUT" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT8" description="DMA2D background CLUT" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT9" description="DMA2D background CLUT" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT10" description="DMA2D background CLUT" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT11" description="DMA2D background CLUT" start="+0x82C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT12" description="DMA2D background CLUT" start="+0x830" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT13" description="DMA2D background CLUT" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT14" description="DMA2D background CLUT" start="+0x838" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT15" description="DMA2D background CLUT" start="+0x83C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT16" description="DMA2D background CLUT" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT17" description="DMA2D background CLUT" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT18" description="DMA2D background CLUT" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT19" description="DMA2D background CLUT" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT20" description="DMA2D background CLUT" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT21" description="DMA2D background CLUT" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT22" description="DMA2D background CLUT" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT23" description="DMA2D background CLUT" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT24" description="DMA2D background CLUT" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT25" description="DMA2D background CLUT" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT26" description="DMA2D background CLUT" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT27" description="DMA2D background CLUT" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT28" description="DMA2D background CLUT" start="+0x870" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT29" description="DMA2D background CLUT" start="+0x874" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT30" description="DMA2D background CLUT" start="+0x878" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT31" description="DMA2D background CLUT" start="+0x87C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT32" description="DMA2D background CLUT" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT33" description="DMA2D background CLUT" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT34" description="DMA2D background CLUT" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT35" description="DMA2D background CLUT" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT36" description="DMA2D background CLUT" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT37" description="DMA2D background CLUT" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT38" description="DMA2D background CLUT" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT39" description="DMA2D background CLUT" start="+0x89C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT40" description="DMA2D background CLUT" start="+0x8A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT41" description="DMA2D background CLUT" start="+0x8A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT42" description="DMA2D background CLUT" start="+0x8A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT43" description="DMA2D background CLUT" start="+0x8AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT44" description="DMA2D background CLUT" start="+0x8B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT45" description="DMA2D background CLUT" start="+0x8B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT46" description="DMA2D background CLUT" start="+0x8B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT47" description="DMA2D background CLUT" start="+0x8BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT48" description="DMA2D background CLUT" start="+0x8C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT49" description="DMA2D background CLUT" start="+0x8C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT50" description="DMA2D background CLUT" start="+0x8C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT51" description="DMA2D background CLUT" start="+0x8CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT52" description="DMA2D background CLUT" start="+0x8D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT53" description="DMA2D background CLUT" start="+0x8D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT54" description="DMA2D background CLUT" start="+0x8D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT55" description="DMA2D background CLUT" start="+0x8DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT56" description="DMA2D background CLUT" start="+0x8E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT57" description="DMA2D background CLUT" start="+0x8E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT58" description="DMA2D background CLUT" start="+0x8E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT59" description="DMA2D background CLUT" start="+0x8EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT60" description="DMA2D background CLUT" start="+0x8F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT61" description="DMA2D background CLUT" start="+0x8F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT62" description="DMA2D background CLUT" start="+0x8F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT63" description="DMA2D background CLUT" start="+0x8FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT64" description="DMA2D background CLUT" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT65" description="DMA2D background CLUT" start="+0x904" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT66" description="DMA2D background CLUT" start="+0x908" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT67" description="DMA2D background CLUT" start="+0x90C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT68" description="DMA2D background CLUT" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT69" description="DMA2D background CLUT" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT70" description="DMA2D background CLUT" start="+0x918" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT71" description="DMA2D background CLUT" start="+0x91C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT72" description="DMA2D background CLUT" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT73" description="DMA2D background CLUT" start="+0x924" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT74" description="DMA2D background CLUT" start="+0x928" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT75" description="DMA2D background CLUT" start="+0x92C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT76" description="DMA2D background CLUT" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT77" description="DMA2D background CLUT" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT78" description="DMA2D background CLUT" start="+0x938" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT79" description="DMA2D background CLUT" start="+0x93C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT80" description="DMA2D background CLUT" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT81" description="DMA2D background CLUT" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT82" description="DMA2D background CLUT" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT83" description="DMA2D background CLUT" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT84" description="DMA2D background CLUT" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT85" description="DMA2D background CLUT" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT86" description="DMA2D background CLUT" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT87" description="DMA2D background CLUT" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT88" description="DMA2D background CLUT" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT89" description="DMA2D background CLUT" start="+0x964" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT90" description="DMA2D background CLUT" start="+0x968" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT91" description="DMA2D background CLUT" start="+0x96C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT92" description="DMA2D background CLUT" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT93" description="DMA2D background CLUT" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT94" description="DMA2D background CLUT" start="+0x978" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT95" description="DMA2D background CLUT" start="+0x97C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT96" description="DMA2D background CLUT" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT97" description="DMA2D background CLUT" start="+0x984" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT98" description="DMA2D background CLUT" start="+0x988" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT99" description="DMA2D background CLUT" start="+0x98C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT100" description="DMA2D background CLUT" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT101" description="DMA2D background CLUT" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT102" description="DMA2D background CLUT" start="+0x998" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT103" description="DMA2D background CLUT" start="+0x99C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT104" description="DMA2D background CLUT" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT105" description="DMA2D background CLUT" start="+0x9A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT106" description="DMA2D background CLUT" start="+0x9A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT107" description="DMA2D background CLUT" start="+0x9AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT108" description="DMA2D background CLUT" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT109" description="DMA2D background CLUT" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT110" description="DMA2D background CLUT" start="+0x9B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT111" description="DMA2D background CLUT" start="+0x9BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT112" description="DMA2D background CLUT" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT113" description="DMA2D background CLUT" start="+0x9C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT114" description="DMA2D background CLUT" start="+0x9C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT115" description="DMA2D background CLUT" start="+0x9CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT116" description="DMA2D background CLUT" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT117" description="DMA2D background CLUT" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT118" description="DMA2D background CLUT" start="+0x9D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT119" description="DMA2D background CLUT" start="+0x9DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT120" description="DMA2D background CLUT" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT121" description="DMA2D background CLUT" start="+0x9E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT122" description="DMA2D background CLUT" start="+0x9E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT123" description="DMA2D background CLUT" start="+0x9EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT124" description="DMA2D background CLUT" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT125" description="DMA2D background CLUT" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT126" description="DMA2D background CLUT" start="+0x9F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT127" description="DMA2D background CLUT" start="+0x9FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT128" description="DMA2D background CLUT" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT129" description="DMA2D background CLUT" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT130" description="DMA2D background CLUT" start="+0xA08" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT131" description="DMA2D background CLUT" start="+0xA0C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT132" description="DMA2D background CLUT" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT133" description="DMA2D background CLUT" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT134" description="DMA2D background CLUT" start="+0xA18" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT135" description="DMA2D background CLUT" start="+0xA1C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT136" description="DMA2D background CLUT" start="+0xA20" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT137" description="DMA2D background CLUT" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT138" description="DMA2D background CLUT" start="+0xA28" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT139" description="DMA2D background CLUT" start="+0xA2C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT140" description="DMA2D background CLUT" start="+0xA30" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT141" description="DMA2D background CLUT" start="+0xA34" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT142" description="DMA2D background CLUT" start="+0xA38" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT143" description="DMA2D background CLUT" start="+0xA3C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT144" description="DMA2D background CLUT" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT145" description="DMA2D background CLUT" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT146" description="DMA2D background CLUT" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT147" description="DMA2D background CLUT" start="+0xA4C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT148" description="DMA2D background CLUT" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT149" description="DMA2D background CLUT" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT150" description="DMA2D background CLUT" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT151" description="DMA2D background CLUT" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT152" description="DMA2D background CLUT" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT153" description="DMA2D background CLUT" start="+0xA64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT154" description="DMA2D background CLUT" start="+0xA68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT155" description="DMA2D background CLUT" start="+0xA6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT156" description="DMA2D background CLUT" start="+0xA70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT157" description="DMA2D background CLUT" start="+0xA74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT158" description="DMA2D background CLUT" start="+0xA78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT159" description="DMA2D background CLUT" start="+0xA7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT160" description="DMA2D background CLUT" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT161" description="DMA2D background CLUT" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT162" description="DMA2D background CLUT" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT163" description="DMA2D background CLUT" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT164" description="DMA2D background CLUT" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT165" description="DMA2D background CLUT" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT166" description="DMA2D background CLUT" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT167" description="DMA2D background CLUT" start="+0xA9C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT168" description="DMA2D background CLUT" start="+0xAA0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT169" description="DMA2D background CLUT" start="+0xAA4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT170" description="DMA2D background CLUT" start="+0xAA8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT171" description="DMA2D background CLUT" start="+0xAAC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT172" description="DMA2D background CLUT" start="+0xAB0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT173" description="DMA2D background CLUT" start="+0xAB4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT174" description="DMA2D background CLUT" start="+0xAB8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT175" description="DMA2D background CLUT" start="+0xABC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT176" description="DMA2D background CLUT" start="+0xAC0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT177" description="DMA2D background CLUT" start="+0xAC4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT178" description="DMA2D background CLUT" start="+0xAC8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT179" description="DMA2D background CLUT" start="+0xACC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT180" description="DMA2D background CLUT" start="+0xAD0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT181" description="DMA2D background CLUT" start="+0xAD4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT182" description="DMA2D background CLUT" start="+0xAD8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT183" description="DMA2D background CLUT" start="+0xADC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT184" description="DMA2D background CLUT" start="+0xAE0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT185" description="DMA2D background CLUT" start="+0xAE4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT186" description="DMA2D background CLUT" start="+0xAE8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT187" description="DMA2D background CLUT" start="+0xAEC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT188" description="DMA2D background CLUT" start="+0xAF0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT189" description="DMA2D background CLUT" start="+0xAF4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT190" description="DMA2D background CLUT" start="+0xAF8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT191" description="DMA2D background CLUT" start="+0xAFC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT192" description="DMA2D background CLUT" start="+0xB00" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT193" description="DMA2D background CLUT" start="+0xB04" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT194" description="DMA2D background CLUT" start="+0xB08" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT195" description="DMA2D background CLUT" start="+0xB0C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT196" description="DMA2D background CLUT" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT197" description="DMA2D background CLUT" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT198" description="DMA2D background CLUT" start="+0xB18" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT199" description="DMA2D background CLUT" start="+0xB1C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT200" description="DMA2D background CLUT" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT201" description="DMA2D background CLUT" start="+0xB24" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT202" description="DMA2D background CLUT" start="+0xB28" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT203" description="DMA2D background CLUT" start="+0xB2C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT204" description="DMA2D background CLUT" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT205" description="DMA2D background CLUT" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT206" description="DMA2D background CLUT" start="+0xB38" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT207" description="DMA2D background CLUT" start="+0xB3C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT208" description="DMA2D background CLUT" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT209" description="DMA2D background CLUT" start="+0xB44" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT210" description="DMA2D background CLUT" start="+0xB48" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT211" description="DMA2D background CLUT" start="+0xB4C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT212" description="DMA2D background CLUT" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT213" description="DMA2D background CLUT" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT214" description="DMA2D background CLUT" start="+0xB58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT215" description="DMA2D background CLUT" start="+0xB5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT216" description="DMA2D background CLUT" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT217" description="DMA2D background CLUT" start="+0xB64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT218" description="DMA2D background CLUT" start="+0xB68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT219" description="DMA2D background CLUT" start="+0xB6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT220" description="DMA2D background CLUT" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT221" description="DMA2D background CLUT" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT222" description="DMA2D background CLUT" start="+0xB78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT223" description="DMA2D background CLUT" start="+0xB7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT224" description="DMA2D background CLUT" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT225" description="DMA2D background CLUT" start="+0xB84" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT226" description="DMA2D background CLUT" start="+0xB88" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT227" description="DMA2D background CLUT" start="+0xB8C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT228" description="DMA2D background CLUT" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT229" description="DMA2D background CLUT" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT230" description="DMA2D background CLUT" start="+0xB98" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT231" description="DMA2D background CLUT" start="+0xB9C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT232" description="DMA2D background CLUT" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT233" description="DMA2D background CLUT" start="+0xBA4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT234" description="DMA2D background CLUT" start="+0xBA8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT235" description="DMA2D background CLUT" start="+0xBAC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT236" description="DMA2D background CLUT" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT237" description="DMA2D background CLUT" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT238" description="DMA2D background CLUT" start="+0xBB8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT239" description="DMA2D background CLUT" start="+0xBBC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT240" description="DMA2D background CLUT" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT241" description="DMA2D background CLUT" start="+0xBC4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT242" description="DMA2D background CLUT" start="+0xBC8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT243" description="DMA2D background CLUT" start="+0xBCC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT244" description="DMA2D background CLUT" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT245" description="DMA2D background CLUT" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT246" description="DMA2D background CLUT" start="+0xBD8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT247" description="DMA2D background CLUT" start="+0xBDC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT248" description="DMA2D background CLUT" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT249" description="DMA2D background CLUT" start="+0xBE4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT250" description="DMA2D background CLUT" start="+0xBE8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT251" description="DMA2D background CLUT" start="+0xBEC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT252" description="DMA2D background CLUT" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT253" description="DMA2D background CLUT" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT254" description="DMA2D background CLUT" start="+0xBF8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT255" description="DMA2D background CLUT" start="+0xBFC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMA2D_S" description="Chrom-ART Accelerator controller" start="0x58021000">
+    <Register name="DMA2D_CR" description="DMA2D control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="START" description="Start" start="0" size="1" access="Read/Write" />
+      <BitField name="SUSP" description="Suspend" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer not suspended" start="0x0" />
+        <Enum name="B_0x1" description="Transfer suspended" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transfer abort requested" start="0x0" />
+        <Enum name="B_0x1" description="Transfer abort requested" start="0x1" />
+      </BitField>
+      <BitField name="LOM" description="Line offset mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line offsets expressed in pixels" start="0x0" />
+        <Enum name="B_0x1" description="Line offsets expressed in bytes" start="0x1" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error (TE) interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete (TC) interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TWIE" description="Transfer watermark (TW) interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TW interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TW interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CAEIE" description="CLUT access error (CAE) interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CAE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTCIE" description="CLUT transfer complete (CTC) interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CEIE" description="Configuration error (CE) interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="DMA2D mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Memory-to-memory (FG fetch only)" start="0x0" />
+        <Enum name="B_0x1" description="Memory-to-memory with PFC (FG fetch only with FG PFC active)" start="0x1" />
+        <Enum name="B_0x2" description="Memory-to-memory with blending (FG and BG fetch with PFC and blending)" start="0x2" />
+        <Enum name="B_0x3" description="Register-to-memory (no FG nor BG, only output stage active)" start="0x3" />
+        <Enum name="B_0x4" description="Memory-to-memory with blending and fixed color FG (BG fetch only with FG and BG PFC active)" start="0x4" />
+        <Enum name="B_0x5" description="Memory-to-memory with blending and fixed color BG (FG fetch only with FG and BG PFC active)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="DMA2D_ISR" description="DMA2D interrupt status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF" description="Transfer error interrupt flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCIF" description="Transfer complete interrupt flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TWIF" description="Transfer watermark interrupt flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="CAEIF" description="CLUT access error interrupt flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="CTCIF" description="CLUT transfer complete interrupt flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="CEIF" description="Configuration error interrupt flag" start="5" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DMA2D_IFCR" description="DMA2D interrupt flag clear register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF" description="Clear transfer error interrupt flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CTCIF" description="Clear transfer complete interrupt flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CTWIF" description="Clear transfer watermark interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CAECIF" description="Clear CLUT access error interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CCTCIF" description="Clear CLUT transfer complete interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="CCEIF" description="Clear configuration error interrupt flag" start="5" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGMAR" description="DMA2D foreground memory address register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address, address of the data used for the foreground image" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGOR" description="DMA2D foreground offset register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGMAR" description="DMA2D background memory address register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address, address of the data used for the background image" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGOR" description="DMA2D background offset register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGPFCCR" description="DMA2D foreground PFC control register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+        <Enum name="B_0x5" description="L8" start="0x5" />
+        <Enum name="B_0x6" description="AL44" start="0x6" />
+        <Enum name="B_0x7" description="AL88" start="0x7" />
+        <Enum name="B_0x8" description="L4" start="0x8" />
+        <Enum name="B_0x9" description="A8" start="0x9" />
+        <Enum name="B_0xA" description="A4" start="0xA" />
+        <Enum name="B_0xB" description="YCbCr" start="0xB" />
+      </BitField>
+      <BitField name="CCM" description="CLUT color mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start" start="5" size="1" access="Read/Write" />
+      <BitField name="CS" description="CLUT size" start="8" size="8" access="Read/Write" />
+      <BitField name="AM" description="Alpha mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No modification of the foreground image alpha channel value" start="0x0" />
+        <Enum name="B_0x1" description="Replace original foreground image alpha channel value by ALPHA[7: 0]" start="0x1" />
+        <Enum name="B_0x2" description="Replace original foreground image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value" start="0x2" />
+      </BitField>
+      <BitField name="CSS" description="Chroma subsampling" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="4:4:4 (no chroma subsampling)" start="0x0" />
+        <Enum name="B_0x1" description="4:2:2" start="0x1" />
+        <Enum name="B_0x2" description="4:2:0" start="0x2" />
+      </BitField>
+      <BitField name="AI" description="Alpha inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+      <BitField name="ALPHA" description="Alpha value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCOLR" description="DMA2D foreground color register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value for the A4 or A8 mode of the foreground image" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value for the A4 or A8 mode of the foreground image" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value for the A4 or A8 mode of the foreground image" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGPFCCR" description="DMA2D background PFC control register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+        <Enum name="B_0x5" description="L8" start="0x5" />
+        <Enum name="B_0x6" description="AL44" start="0x6" />
+        <Enum name="B_0x7" description="AL88" start="0x7" />
+        <Enum name="B_0x8" description="L4" start="0x8" />
+        <Enum name="B_0x9" description="A8" start="0x9" />
+        <Enum name="B_0xA" description="A4" start="0xA" />
+      </BitField>
+      <BitField name="CCM" description="CLUT color mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start" start="5" size="1" access="Read/Write" />
+      <BitField name="CS" description="CLUT size" start="8" size="8" access="Read/Write" />
+      <BitField name="AM" description="Alpha mode" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No modification of the foreground image alpha channel value" start="0x0" />
+        <Enum name="B_0x1" description="Replace original background image alpha channel value by ALPHA[7: 0]" start="0x1" />
+        <Enum name="B_0x2" description="Replace original background image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value" start="0x2" />
+      </BitField>
+      <BitField name="AI" description="Alpha Inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+      <BitField name="ALPHA" description="Alpha value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCOLR" description="DMA2D background color register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value for the A4 or A8 mode of the background" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value for the A4 or A8 mode of the background" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value for the A4 or A8 mode of the background" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCMAR" description="DMA2D foreground CLUT memory address register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCMAR" description="DMA2D background CLUT memory address register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OPFCCR" description="DMA2D output PFC control register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888" start="0x0" />
+        <Enum name="B_0x1" description="RGB888" start="0x1" />
+        <Enum name="B_0x2" description="RGB565" start="0x2" />
+        <Enum name="B_0x3" description="ARGB1555" start="0x3" />
+        <Enum name="B_0x4" description="ARGB4444" start="0x4" />
+      </BitField>
+      <BitField name="SB" description="Swap bytes" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bytes in regular order in the output FIFO" start="0x0" />
+        <Enum name="B_0x1" description="Bytes swapped two by two in the output FIFO" start="0x1" />
+      </BitField>
+      <BitField name="AI" description="Alpha Inverted" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular alpha" start="0x0" />
+        <Enum name="B_0x1" description="Inverted alpha" start="0x1" />
+      </BitField>
+      <BitField name="RBS" description="Red/Blue swap" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular mode (RGB or ARGB)" start="0x0" />
+        <Enum name="B_0x1" description="Swap mode (BGR or ABGR)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DMA2D_OCOLR_RGB888" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB8888 or RGB888" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB8888 or RGB888" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB8888 or RGB888 mode" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_RGB565" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in RGB565 mode" start="0" size="5" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in RGB565 mode" start="5" size="6" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in RGB565 mode" start="11" size="5" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_ARGB1555" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB1555 mode" start="0" size="5" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB1555 mode" start="5" size="5" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB1555 mode" start="10" size="5" access="Read/Write" />
+      <BitField name="A" description="Alpha channel value of the output color in ARGB1555 mode" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OCOLR_ARGB4444" description="DMA2D output color register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue value of the output image in ARGB4444 mode" start="0" size="4" access="Read/Write" />
+      <BitField name="GREEN" description="Green value of the output image in ARGB4444 mode" start="4" size="4" access="Read/Write" />
+      <BitField name="RED" description="Red value of the output image in ARGB4444 mode" start="8" size="4" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha channel of the output color value in ARGB4444" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OMAR" description="DMA2D output memory address register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_OOR" description="DMA2D output offset register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_NLR" description="DMA2D number of line register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NL" description="Number of lines of the area to be transferred." start="0" size="16" access="Read/Write" />
+      <BitField name="PL" description="Pixel per lines per lines of the area to be transferred" start="16" size="14" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_LWR" description="DMA2D line watermark register" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LW" description="Line watermark for interrupt generation" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_AMTCR" description="DMA2D AXI master timer configuration register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Dead-time functionality enable" start="0" size="1" access="Read/Write" />
+      <BitField name="DT" description="Dead time" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT0" description="DMA2D foreground CLUT" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT1" description="DMA2D foreground CLUT" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT2" description="DMA2D foreground CLUT" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT3" description="DMA2D foreground CLUT" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT4" description="DMA2D foreground CLUT" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT5" description="DMA2D foreground CLUT" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT6" description="DMA2D foreground CLUT" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT7" description="DMA2D foreground CLUT" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT8" description="DMA2D foreground CLUT" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT9" description="DMA2D foreground CLUT" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT10" description="DMA2D foreground CLUT" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT11" description="DMA2D foreground CLUT" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT12" description="DMA2D foreground CLUT" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT13" description="DMA2D foreground CLUT" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT14" description="DMA2D foreground CLUT" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT15" description="DMA2D foreground CLUT" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT16" description="DMA2D foreground CLUT" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT17" description="DMA2D foreground CLUT" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT18" description="DMA2D foreground CLUT" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT19" description="DMA2D foreground CLUT" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT20" description="DMA2D foreground CLUT" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT21" description="DMA2D foreground CLUT" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT22" description="DMA2D foreground CLUT" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT23" description="DMA2D foreground CLUT" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT24" description="DMA2D foreground CLUT" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT25" description="DMA2D foreground CLUT" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT26" description="DMA2D foreground CLUT" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT27" description="DMA2D foreground CLUT" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT28" description="DMA2D foreground CLUT" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT29" description="DMA2D foreground CLUT" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT30" description="DMA2D foreground CLUT" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT31" description="DMA2D foreground CLUT" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT32" description="DMA2D foreground CLUT" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT33" description="DMA2D foreground CLUT" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT34" description="DMA2D foreground CLUT" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT35" description="DMA2D foreground CLUT" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT36" description="DMA2D foreground CLUT" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT37" description="DMA2D foreground CLUT" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT38" description="DMA2D foreground CLUT" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT39" description="DMA2D foreground CLUT" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT40" description="DMA2D foreground CLUT" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT41" description="DMA2D foreground CLUT" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT42" description="DMA2D foreground CLUT" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT43" description="DMA2D foreground CLUT" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT44" description="DMA2D foreground CLUT" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT45" description="DMA2D foreground CLUT" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT46" description="DMA2D foreground CLUT" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT47" description="DMA2D foreground CLUT" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT48" description="DMA2D foreground CLUT" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT49" description="DMA2D foreground CLUT" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT50" description="DMA2D foreground CLUT" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT51" description="DMA2D foreground CLUT" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT52" description="DMA2D foreground CLUT" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT53" description="DMA2D foreground CLUT" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT54" description="DMA2D foreground CLUT" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT55" description="DMA2D foreground CLUT" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT56" description="DMA2D foreground CLUT" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT57" description="DMA2D foreground CLUT" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT58" description="DMA2D foreground CLUT" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT59" description="DMA2D foreground CLUT" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT60" description="DMA2D foreground CLUT" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT61" description="DMA2D foreground CLUT" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT62" description="DMA2D foreground CLUT" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT63" description="DMA2D foreground CLUT" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT64" description="DMA2D foreground CLUT" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT65" description="DMA2D foreground CLUT" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT66" description="DMA2D foreground CLUT" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT67" description="DMA2D foreground CLUT" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT68" description="DMA2D foreground CLUT" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT69" description="DMA2D foreground CLUT" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT70" description="DMA2D foreground CLUT" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT71" description="DMA2D foreground CLUT" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT72" description="DMA2D foreground CLUT" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT73" description="DMA2D foreground CLUT" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT74" description="DMA2D foreground CLUT" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT75" description="DMA2D foreground CLUT" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT76" description="DMA2D foreground CLUT" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT77" description="DMA2D foreground CLUT" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT78" description="DMA2D foreground CLUT" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT79" description="DMA2D foreground CLUT" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT80" description="DMA2D foreground CLUT" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT81" description="DMA2D foreground CLUT" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT82" description="DMA2D foreground CLUT" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT83" description="DMA2D foreground CLUT" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT84" description="DMA2D foreground CLUT" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT85" description="DMA2D foreground CLUT" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT86" description="DMA2D foreground CLUT" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT87" description="DMA2D foreground CLUT" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT88" description="DMA2D foreground CLUT" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT89" description="DMA2D foreground CLUT" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT90" description="DMA2D foreground CLUT" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT91" description="DMA2D foreground CLUT" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT92" description="DMA2D foreground CLUT" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT93" description="DMA2D foreground CLUT" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT94" description="DMA2D foreground CLUT" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT95" description="DMA2D foreground CLUT" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT96" description="DMA2D foreground CLUT" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT97" description="DMA2D foreground CLUT" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT98" description="DMA2D foreground CLUT" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT99" description="DMA2D foreground CLUT" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT100" description="DMA2D foreground CLUT" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT101" description="DMA2D foreground CLUT" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT102" description="DMA2D foreground CLUT" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT103" description="DMA2D foreground CLUT" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT104" description="DMA2D foreground CLUT" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT105" description="DMA2D foreground CLUT" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT106" description="DMA2D foreground CLUT" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT107" description="DMA2D foreground CLUT" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT108" description="DMA2D foreground CLUT" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT109" description="DMA2D foreground CLUT" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT110" description="DMA2D foreground CLUT" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT111" description="DMA2D foreground CLUT" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT112" description="DMA2D foreground CLUT" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT113" description="DMA2D foreground CLUT" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT114" description="DMA2D foreground CLUT" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT115" description="DMA2D foreground CLUT" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT116" description="DMA2D foreground CLUT" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT117" description="DMA2D foreground CLUT" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT118" description="DMA2D foreground CLUT" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT119" description="DMA2D foreground CLUT" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT120" description="DMA2D foreground CLUT" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT121" description="DMA2D foreground CLUT" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT122" description="DMA2D foreground CLUT" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT123" description="DMA2D foreground CLUT" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT124" description="DMA2D foreground CLUT" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT125" description="DMA2D foreground CLUT" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT126" description="DMA2D foreground CLUT" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT127" description="DMA2D foreground CLUT" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT128" description="DMA2D foreground CLUT" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT129" description="DMA2D foreground CLUT" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT130" description="DMA2D foreground CLUT" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT131" description="DMA2D foreground CLUT" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT132" description="DMA2D foreground CLUT" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT133" description="DMA2D foreground CLUT" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT134" description="DMA2D foreground CLUT" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT135" description="DMA2D foreground CLUT" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT136" description="DMA2D foreground CLUT" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT137" description="DMA2D foreground CLUT" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT138" description="DMA2D foreground CLUT" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT139" description="DMA2D foreground CLUT" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT140" description="DMA2D foreground CLUT" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT141" description="DMA2D foreground CLUT" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT142" description="DMA2D foreground CLUT" start="+0x638" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT143" description="DMA2D foreground CLUT" start="+0x63C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT144" description="DMA2D foreground CLUT" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT145" description="DMA2D foreground CLUT" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT146" description="DMA2D foreground CLUT" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT147" description="DMA2D foreground CLUT" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT148" description="DMA2D foreground CLUT" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT149" description="DMA2D foreground CLUT" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT150" description="DMA2D foreground CLUT" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT151" description="DMA2D foreground CLUT" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT152" description="DMA2D foreground CLUT" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT153" description="DMA2D foreground CLUT" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT154" description="DMA2D foreground CLUT" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT155" description="DMA2D foreground CLUT" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT156" description="DMA2D foreground CLUT" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT157" description="DMA2D foreground CLUT" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT158" description="DMA2D foreground CLUT" start="+0x678" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT159" description="DMA2D foreground CLUT" start="+0x67C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT160" description="DMA2D foreground CLUT" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT161" description="DMA2D foreground CLUT" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT162" description="DMA2D foreground CLUT" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT163" description="DMA2D foreground CLUT" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT164" description="DMA2D foreground CLUT" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT165" description="DMA2D foreground CLUT" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT166" description="DMA2D foreground CLUT" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT167" description="DMA2D foreground CLUT" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT168" description="DMA2D foreground CLUT" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT169" description="DMA2D foreground CLUT" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT170" description="DMA2D foreground CLUT" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT171" description="DMA2D foreground CLUT" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT172" description="DMA2D foreground CLUT" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT173" description="DMA2D foreground CLUT" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT174" description="DMA2D foreground CLUT" start="+0x6B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT175" description="DMA2D foreground CLUT" start="+0x6BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT176" description="DMA2D foreground CLUT" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT177" description="DMA2D foreground CLUT" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT178" description="DMA2D foreground CLUT" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT179" description="DMA2D foreground CLUT" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT180" description="DMA2D foreground CLUT" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT181" description="DMA2D foreground CLUT" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT182" description="DMA2D foreground CLUT" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT183" description="DMA2D foreground CLUT" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT184" description="DMA2D foreground CLUT" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT185" description="DMA2D foreground CLUT" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT186" description="DMA2D foreground CLUT" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT187" description="DMA2D foreground CLUT" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT188" description="DMA2D foreground CLUT" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT189" description="DMA2D foreground CLUT" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT190" description="DMA2D foreground CLUT" start="+0x6F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT191" description="DMA2D foreground CLUT" start="+0x6FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT192" description="DMA2D foreground CLUT" start="+0x700" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT193" description="DMA2D foreground CLUT" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT194" description="DMA2D foreground CLUT" start="+0x708" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT195" description="DMA2D foreground CLUT" start="+0x70C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT196" description="DMA2D foreground CLUT" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT197" description="DMA2D foreground CLUT" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT198" description="DMA2D foreground CLUT" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT199" description="DMA2D foreground CLUT" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT200" description="DMA2D foreground CLUT" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT201" description="DMA2D foreground CLUT" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT202" description="DMA2D foreground CLUT" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT203" description="DMA2D foreground CLUT" start="+0x72C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT204" description="DMA2D foreground CLUT" start="+0x730" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT205" description="DMA2D foreground CLUT" start="+0x734" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT206" description="DMA2D foreground CLUT" start="+0x738" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT207" description="DMA2D foreground CLUT" start="+0x73C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT208" description="DMA2D foreground CLUT" start="+0x740" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT209" description="DMA2D foreground CLUT" start="+0x744" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT210" description="DMA2D foreground CLUT" start="+0x748" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT211" description="DMA2D foreground CLUT" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT212" description="DMA2D foreground CLUT" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT213" description="DMA2D foreground CLUT" start="+0x754" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT214" description="DMA2D foreground CLUT" start="+0x758" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT215" description="DMA2D foreground CLUT" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT216" description="DMA2D foreground CLUT" start="+0x760" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT217" description="DMA2D foreground CLUT" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT218" description="DMA2D foreground CLUT" start="+0x768" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT219" description="DMA2D foreground CLUT" start="+0x76C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT220" description="DMA2D foreground CLUT" start="+0x770" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT221" description="DMA2D foreground CLUT" start="+0x774" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT222" description="DMA2D foreground CLUT" start="+0x778" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT223" description="DMA2D foreground CLUT" start="+0x77C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT224" description="DMA2D foreground CLUT" start="+0x780" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT225" description="DMA2D foreground CLUT" start="+0x784" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT226" description="DMA2D foreground CLUT" start="+0x788" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT227" description="DMA2D foreground CLUT" start="+0x78C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT228" description="DMA2D foreground CLUT" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT229" description="DMA2D foreground CLUT" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT230" description="DMA2D foreground CLUT" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT231" description="DMA2D foreground CLUT" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT232" description="DMA2D foreground CLUT" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT233" description="DMA2D foreground CLUT" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT234" description="DMA2D foreground CLUT" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT235" description="DMA2D foreground CLUT" start="+0x7AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT236" description="DMA2D foreground CLUT" start="+0x7B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT237" description="DMA2D foreground CLUT" start="+0x7B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT238" description="DMA2D foreground CLUT" start="+0x7B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT239" description="DMA2D foreground CLUT" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT240" description="DMA2D foreground CLUT" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT241" description="DMA2D foreground CLUT" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT242" description="DMA2D foreground CLUT" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT243" description="DMA2D foreground CLUT" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT244" description="DMA2D foreground CLUT" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT245" description="DMA2D foreground CLUT" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT246" description="DMA2D foreground CLUT" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT247" description="DMA2D foreground CLUT" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT248" description="DMA2D foreground CLUT" start="+0x7E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT249" description="DMA2D foreground CLUT" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT250" description="DMA2D foreground CLUT" start="+0x7E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT251" description="DMA2D foreground CLUT" start="+0x7EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT252" description="DMA2D foreground CLUT" start="+0x7F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT253" description="DMA2D foreground CLUT" start="+0x7F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT254" description="DMA2D foreground CLUT" start="+0x7F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_FGCLUT255" description="DMA2D foreground CLUT" start="+0x7FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT0" description="DMA2D background CLUT" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT1" description="DMA2D background CLUT" start="+0x804" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT2" description="DMA2D background CLUT" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT3" description="DMA2D background CLUT" start="+0x80C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT4" description="DMA2D background CLUT" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT5" description="DMA2D background CLUT" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT6" description="DMA2D background CLUT" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT7" description="DMA2D background CLUT" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT8" description="DMA2D background CLUT" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT9" description="DMA2D background CLUT" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT10" description="DMA2D background CLUT" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT11" description="DMA2D background CLUT" start="+0x82C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT12" description="DMA2D background CLUT" start="+0x830" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT13" description="DMA2D background CLUT" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT14" description="DMA2D background CLUT" start="+0x838" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT15" description="DMA2D background CLUT" start="+0x83C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT16" description="DMA2D background CLUT" start="+0x840" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT17" description="DMA2D background CLUT" start="+0x844" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT18" description="DMA2D background CLUT" start="+0x848" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT19" description="DMA2D background CLUT" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT20" description="DMA2D background CLUT" start="+0x850" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT21" description="DMA2D background CLUT" start="+0x854" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT22" description="DMA2D background CLUT" start="+0x858" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT23" description="DMA2D background CLUT" start="+0x85C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT24" description="DMA2D background CLUT" start="+0x860" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT25" description="DMA2D background CLUT" start="+0x864" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT26" description="DMA2D background CLUT" start="+0x868" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT27" description="DMA2D background CLUT" start="+0x86C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT28" description="DMA2D background CLUT" start="+0x870" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT29" description="DMA2D background CLUT" start="+0x874" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT30" description="DMA2D background CLUT" start="+0x878" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT31" description="DMA2D background CLUT" start="+0x87C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT32" description="DMA2D background CLUT" start="+0x880" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT33" description="DMA2D background CLUT" start="+0x884" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT34" description="DMA2D background CLUT" start="+0x888" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT35" description="DMA2D background CLUT" start="+0x88C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT36" description="DMA2D background CLUT" start="+0x890" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT37" description="DMA2D background CLUT" start="+0x894" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT38" description="DMA2D background CLUT" start="+0x898" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT39" description="DMA2D background CLUT" start="+0x89C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT40" description="DMA2D background CLUT" start="+0x8A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT41" description="DMA2D background CLUT" start="+0x8A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT42" description="DMA2D background CLUT" start="+0x8A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT43" description="DMA2D background CLUT" start="+0x8AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT44" description="DMA2D background CLUT" start="+0x8B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT45" description="DMA2D background CLUT" start="+0x8B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT46" description="DMA2D background CLUT" start="+0x8B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT47" description="DMA2D background CLUT" start="+0x8BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT48" description="DMA2D background CLUT" start="+0x8C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT49" description="DMA2D background CLUT" start="+0x8C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT50" description="DMA2D background CLUT" start="+0x8C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT51" description="DMA2D background CLUT" start="+0x8CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT52" description="DMA2D background CLUT" start="+0x8D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT53" description="DMA2D background CLUT" start="+0x8D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT54" description="DMA2D background CLUT" start="+0x8D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT55" description="DMA2D background CLUT" start="+0x8DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT56" description="DMA2D background CLUT" start="+0x8E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT57" description="DMA2D background CLUT" start="+0x8E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT58" description="DMA2D background CLUT" start="+0x8E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT59" description="DMA2D background CLUT" start="+0x8EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT60" description="DMA2D background CLUT" start="+0x8F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT61" description="DMA2D background CLUT" start="+0x8F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT62" description="DMA2D background CLUT" start="+0x8F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT63" description="DMA2D background CLUT" start="+0x8FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT64" description="DMA2D background CLUT" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT65" description="DMA2D background CLUT" start="+0x904" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT66" description="DMA2D background CLUT" start="+0x908" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT67" description="DMA2D background CLUT" start="+0x90C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT68" description="DMA2D background CLUT" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT69" description="DMA2D background CLUT" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT70" description="DMA2D background CLUT" start="+0x918" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT71" description="DMA2D background CLUT" start="+0x91C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT72" description="DMA2D background CLUT" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT73" description="DMA2D background CLUT" start="+0x924" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT74" description="DMA2D background CLUT" start="+0x928" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT75" description="DMA2D background CLUT" start="+0x92C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT76" description="DMA2D background CLUT" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT77" description="DMA2D background CLUT" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT78" description="DMA2D background CLUT" start="+0x938" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT79" description="DMA2D background CLUT" start="+0x93C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT80" description="DMA2D background CLUT" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT81" description="DMA2D background CLUT" start="+0x944" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT82" description="DMA2D background CLUT" start="+0x948" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT83" description="DMA2D background CLUT" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT84" description="DMA2D background CLUT" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT85" description="DMA2D background CLUT" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT86" description="DMA2D background CLUT" start="+0x958" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT87" description="DMA2D background CLUT" start="+0x95C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT88" description="DMA2D background CLUT" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT89" description="DMA2D background CLUT" start="+0x964" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT90" description="DMA2D background CLUT" start="+0x968" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT91" description="DMA2D background CLUT" start="+0x96C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT92" description="DMA2D background CLUT" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT93" description="DMA2D background CLUT" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT94" description="DMA2D background CLUT" start="+0x978" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT95" description="DMA2D background CLUT" start="+0x97C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT96" description="DMA2D background CLUT" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT97" description="DMA2D background CLUT" start="+0x984" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT98" description="DMA2D background CLUT" start="+0x988" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT99" description="DMA2D background CLUT" start="+0x98C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT100" description="DMA2D background CLUT" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT101" description="DMA2D background CLUT" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT102" description="DMA2D background CLUT" start="+0x998" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT103" description="DMA2D background CLUT" start="+0x99C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT104" description="DMA2D background CLUT" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT105" description="DMA2D background CLUT" start="+0x9A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT106" description="DMA2D background CLUT" start="+0x9A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT107" description="DMA2D background CLUT" start="+0x9AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT108" description="DMA2D background CLUT" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT109" description="DMA2D background CLUT" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT110" description="DMA2D background CLUT" start="+0x9B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT111" description="DMA2D background CLUT" start="+0x9BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT112" description="DMA2D background CLUT" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT113" description="DMA2D background CLUT" start="+0x9C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT114" description="DMA2D background CLUT" start="+0x9C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT115" description="DMA2D background CLUT" start="+0x9CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT116" description="DMA2D background CLUT" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT117" description="DMA2D background CLUT" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT118" description="DMA2D background CLUT" start="+0x9D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT119" description="DMA2D background CLUT" start="+0x9DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT120" description="DMA2D background CLUT" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT121" description="DMA2D background CLUT" start="+0x9E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT122" description="DMA2D background CLUT" start="+0x9E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT123" description="DMA2D background CLUT" start="+0x9EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT124" description="DMA2D background CLUT" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT125" description="DMA2D background CLUT" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT126" description="DMA2D background CLUT" start="+0x9F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT127" description="DMA2D background CLUT" start="+0x9FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT128" description="DMA2D background CLUT" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT129" description="DMA2D background CLUT" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT130" description="DMA2D background CLUT" start="+0xA08" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT131" description="DMA2D background CLUT" start="+0xA0C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT132" description="DMA2D background CLUT" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT133" description="DMA2D background CLUT" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT134" description="DMA2D background CLUT" start="+0xA18" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT135" description="DMA2D background CLUT" start="+0xA1C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT136" description="DMA2D background CLUT" start="+0xA20" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT137" description="DMA2D background CLUT" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT138" description="DMA2D background CLUT" start="+0xA28" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT139" description="DMA2D background CLUT" start="+0xA2C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT140" description="DMA2D background CLUT" start="+0xA30" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT141" description="DMA2D background CLUT" start="+0xA34" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT142" description="DMA2D background CLUT" start="+0xA38" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT143" description="DMA2D background CLUT" start="+0xA3C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT144" description="DMA2D background CLUT" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT145" description="DMA2D background CLUT" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT146" description="DMA2D background CLUT" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT147" description="DMA2D background CLUT" start="+0xA4C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT148" description="DMA2D background CLUT" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT149" description="DMA2D background CLUT" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT150" description="DMA2D background CLUT" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT151" description="DMA2D background CLUT" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT152" description="DMA2D background CLUT" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT153" description="DMA2D background CLUT" start="+0xA64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT154" description="DMA2D background CLUT" start="+0xA68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT155" description="DMA2D background CLUT" start="+0xA6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT156" description="DMA2D background CLUT" start="+0xA70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT157" description="DMA2D background CLUT" start="+0xA74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT158" description="DMA2D background CLUT" start="+0xA78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT159" description="DMA2D background CLUT" start="+0xA7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT160" description="DMA2D background CLUT" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT161" description="DMA2D background CLUT" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT162" description="DMA2D background CLUT" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT163" description="DMA2D background CLUT" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT164" description="DMA2D background CLUT" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT165" description="DMA2D background CLUT" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT166" description="DMA2D background CLUT" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT167" description="DMA2D background CLUT" start="+0xA9C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT168" description="DMA2D background CLUT" start="+0xAA0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT169" description="DMA2D background CLUT" start="+0xAA4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT170" description="DMA2D background CLUT" start="+0xAA8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT171" description="DMA2D background CLUT" start="+0xAAC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT172" description="DMA2D background CLUT" start="+0xAB0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT173" description="DMA2D background CLUT" start="+0xAB4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT174" description="DMA2D background CLUT" start="+0xAB8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT175" description="DMA2D background CLUT" start="+0xABC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT176" description="DMA2D background CLUT" start="+0xAC0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT177" description="DMA2D background CLUT" start="+0xAC4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT178" description="DMA2D background CLUT" start="+0xAC8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT179" description="DMA2D background CLUT" start="+0xACC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT180" description="DMA2D background CLUT" start="+0xAD0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT181" description="DMA2D background CLUT" start="+0xAD4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT182" description="DMA2D background CLUT" start="+0xAD8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT183" description="DMA2D background CLUT" start="+0xADC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT184" description="DMA2D background CLUT" start="+0xAE0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT185" description="DMA2D background CLUT" start="+0xAE4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT186" description="DMA2D background CLUT" start="+0xAE8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT187" description="DMA2D background CLUT" start="+0xAEC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT188" description="DMA2D background CLUT" start="+0xAF0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT189" description="DMA2D background CLUT" start="+0xAF4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT190" description="DMA2D background CLUT" start="+0xAF8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT191" description="DMA2D background CLUT" start="+0xAFC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT192" description="DMA2D background CLUT" start="+0xB00" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT193" description="DMA2D background CLUT" start="+0xB04" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT194" description="DMA2D background CLUT" start="+0xB08" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT195" description="DMA2D background CLUT" start="+0xB0C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT196" description="DMA2D background CLUT" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT197" description="DMA2D background CLUT" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT198" description="DMA2D background CLUT" start="+0xB18" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT199" description="DMA2D background CLUT" start="+0xB1C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT200" description="DMA2D background CLUT" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT201" description="DMA2D background CLUT" start="+0xB24" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT202" description="DMA2D background CLUT" start="+0xB28" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT203" description="DMA2D background CLUT" start="+0xB2C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT204" description="DMA2D background CLUT" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT205" description="DMA2D background CLUT" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT206" description="DMA2D background CLUT" start="+0xB38" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT207" description="DMA2D background CLUT" start="+0xB3C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT208" description="DMA2D background CLUT" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT209" description="DMA2D background CLUT" start="+0xB44" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT210" description="DMA2D background CLUT" start="+0xB48" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT211" description="DMA2D background CLUT" start="+0xB4C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT212" description="DMA2D background CLUT" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT213" description="DMA2D background CLUT" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT214" description="DMA2D background CLUT" start="+0xB58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT215" description="DMA2D background CLUT" start="+0xB5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT216" description="DMA2D background CLUT" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT217" description="DMA2D background CLUT" start="+0xB64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT218" description="DMA2D background CLUT" start="+0xB68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT219" description="DMA2D background CLUT" start="+0xB6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT220" description="DMA2D background CLUT" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT221" description="DMA2D background CLUT" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT222" description="DMA2D background CLUT" start="+0xB78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT223" description="DMA2D background CLUT" start="+0xB7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT224" description="DMA2D background CLUT" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT225" description="DMA2D background CLUT" start="+0xB84" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT226" description="DMA2D background CLUT" start="+0xB88" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT227" description="DMA2D background CLUT" start="+0xB8C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT228" description="DMA2D background CLUT" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT229" description="DMA2D background CLUT" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT230" description="DMA2D background CLUT" start="+0xB98" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT231" description="DMA2D background CLUT" start="+0xB9C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT232" description="DMA2D background CLUT" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT233" description="DMA2D background CLUT" start="+0xBA4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT234" description="DMA2D background CLUT" start="+0xBA8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT235" description="DMA2D background CLUT" start="+0xBAC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT236" description="DMA2D background CLUT" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT237" description="DMA2D background CLUT" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT238" description="DMA2D background CLUT" start="+0xBB8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT239" description="DMA2D background CLUT" start="+0xBBC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT240" description="DMA2D background CLUT" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT241" description="DMA2D background CLUT" start="+0xBC4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT242" description="DMA2D background CLUT" start="+0xBC8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT243" description="DMA2D background CLUT" start="+0xBCC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT244" description="DMA2D background CLUT" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT245" description="DMA2D background CLUT" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT246" description="DMA2D background CLUT" start="+0xBD8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT247" description="DMA2D background CLUT" start="+0xBDC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT248" description="DMA2D background CLUT" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT249" description="DMA2D background CLUT" start="+0xBE4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT250" description="DMA2D background CLUT" start="+0xBE8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT251" description="DMA2D background CLUT" start="+0xBEC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT252" description="DMA2D background CLUT" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT253" description="DMA2D background CLUT" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT254" description="DMA2D background CLUT" start="+0xBF8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="DMA2D_BGCLUT255" description="DMA2D background CLUT" start="+0xBFC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="BLUE" description="Blue" start="0" size="8" access="Read/Write" />
+      <BitField name="GREEN" description="Green" start="8" size="8" access="Read/Write" />
+      <BitField name="RED" description="Red" start="16" size="8" access="Read/Write" />
+      <BitField name="ALPHA" description="Alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DTS" description="Digital temperature sensor" start="0x4600A000">
+    <Register name="DTS_PVTREG_LOCKR" description="DTS PVT register lock register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK" description="PVT software lock register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTLOCK_SR" description="DTS PVT lock status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SW_LOCK_STATUS" description="Software lock input status" start="0" size="1" access="ReadOnly" />
+      <BitField name="HW_LOCK_STATUS" description="Hardware lock input status" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVTTMR_CR" description="DTS PVT timer control register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_DELAY" description="Timer delay" start="0" size="16" access="Read/Write" />
+      <BitField name="TMR_RUN" description="Timer count enable bit" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTTMR_SR" description="DTS PVT timer status register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_BUSY" description="Counter busy flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TMR_DONE" description="Counter delay expiration flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVT_IER" description="DTS PVT IRQ enable register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_ENABLE" description="Timer IRQ source enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="TS_IRQ_ENABLE" description="TS IRQ source enable bit" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTIRQTRMASKR" description="DTS PVT IRQ timer mask register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_MASK" description="Timer IRQ source mask bit" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS_MR" description="DTS PVT IRQ TS mask register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_MASK" description="TS0 IRQ source mask bit" start="0" size="1" access="Read/Write" />
+      <BitField name="TS1_IRQ_MASK" description="TS1 IRQ source mask bit" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTTR_SR" description="DTS PVT IRQ timer status register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_STATUS" description="Timer IRQ status bit after masking" start="0" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS_ISR" description="DTS PVT IRQ TS status register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_STATUS" description="TS0 IRQ status bit after masking" start="0" size="1" access="ReadOnly" />
+      <BitField name="TS1_IRQ_STATUS" description="TS1 IRQ status bit after masking" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVTTMRRAW_ISR" description="DTS PVT IRQ timer raw status register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_RAW_STATUS" description="TMR IRQ status bit before masking" start="0" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TSRAW_ISR" description="DTS PVT IRQ TS raw status register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_RAW_STATUS" description="TS0 IRQ status bit before masking" start="0" size="1" access="ReadOnly" />
+      <BitField name="TS1_IRQ_RAW_STATUS" description="TS1 IRQ status bit before masking" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TSCCLKSYNTHR" description="DTS TSC clock synthesizer register" start="+0x080" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLK_SYNTH_LO" description="Synthesized clk_ts low period" start="0" size="8" access="Read/Write" />
+      <BitField name="CLK_SYNTH_HI" description="Synthesized clk_ts high period" start="8" size="8" access="Read/Write" />
+      <BitField name="CLK_SYNTH_HOLD" description="SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay" start="16" size="4" access="Read/Write" />
+      <BitField name="CLK_SYTH_EN" description="Synthesized clk_ts enable bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFDISABLER" description="DTS TSC SDIF interface disable register" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_SDIF_DISABLE" description="TS0 serial data interface (SDIF) disable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enabled" start="0x0" />
+        <Enum name="B_0x1" description="Disabled" start="0x1" />
+      </BitField>
+      <BitField name="TS1_SDIF_DISABLE" description="TS1 serial data interface (SDIF) disable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enabled" start="0x0" />
+        <Enum name="B_0x1" description="Disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_SR" description="DTS TSC SDIF status register" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_BUSY" description="SDIF busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SDIF not busy/no clock synthesizer/disable SDIF state update ongoing" start="0x0" />
+        <Enum name="B_0x1" description="SDIF busy/clock synthesizer/disable SDIF state update ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SDIF_LOCK" description="SDIF locked flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Unlocked" start="0x0" />
+        <Enum name="B_0x1" description="Locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_CR" description="DTS TSC SDIF register" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_WDATA" description="Serial interface write data" start="0" size="24" access="Read/Write" />
+      <BitField name="SDIF_ADDR" description="Serial interface register address" start="24" size="3" access="Read/Write" />
+      <BitField name="SDIF_WRN" description="Serial interface write/no read control bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIF read" start="0x0" />
+        <Enum name="B_0x1" description="SDIF write" start="0x1" />
+      </BitField>
+      <BitField name="SDIF_PROG" description="Serial interface program request" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No SDIF program request" start="0x0" />
+        <Enum name="B_0x1" description="SDIF program requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFHALTR" description="DTS TSC SDIF halt register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_STOP" description="Serial data interface (SDIF) stop " start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Not stopped" start="0x0" />
+        <Enum name="B_0x1" description="Stopped" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_CFGR" description="DTS TSC SDIF control register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_INHIBIT" description="Serial data interface (SDIF) programming inhibit " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Inhibition" start="0x0" />
+        <Enum name="B_0x1" description="TS0 inhibited/TS1 serial programming activated (SPA)" start="0x1" />
+        <Enum name="B_0x2" description="TS1 inhibited/TS0 serial programming activated (SPA)" start="0x2" />
+        <Enum name="B_0x3" description="TS1 and TS0 inhibited" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSMPL_CR" description="DTS TSC sample control register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_CTR_DISABLE" description="Sample counter disable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sample counter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Sample counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="SMPL_CTR_HOLD" description="Sample counter hold bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter not on hold" start="0x0" />
+        <Enum name="B_0x1" description="Counter on hold" start="0x1" />
+      </BitField>
+      <BitField name="SMPL_DISCARD" description="Sample discard bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data samples not discarded" start="0x0" />
+        <Enum name="B_0x1" description="Data samples discarded" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFSMPLCLRR" description="DTS TSC sample clear register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_CNTER_CLEAR" description="Sample counter clear bit " start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Counter value not cleared" start="0x0" />
+        <Enum name="B_0x1" description="Counter value cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSMPLCNTR" description="DTS TSC sample count register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_COUNT" description="Sample counter" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0_IER" description="DTS TS0 IRQ enable register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_EN_FAULT" description="Fault IRQ enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_DONE" description="Sample done IRQ enable bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMA" description="Alarm A IRQ enable bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMB" description="Alarm B IRQ enable bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0_ISR" description="DTS TS0 IRQ status register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_STATUS_FAULT" description="Fault IRQ status bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_DONE" description="Sample done IRQ status bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMA" description="Alarm A IRQ status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMB" description="Alarm B IRQ status bit" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0_ICR" description="DTS TS0 IRQ clear register" start="+0xC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_CLEAR_FAULT" description="Fault IRQ clear bit" start="0" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_DONE" description="Sample done IRQ clear bit" start="1" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMA" description="Alarm A IRQ clear bit" start="3" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMB" description="Alarm B IRQ clear bit" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS0IRQTESTR" description="DTS TS0 IRQ test register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_TEST_FAULT" description="Fault IRQ test bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_DONE" description="Sample done IRQ test bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMA" description="Alarm A IRQ test bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMB" description="Alarm B IRQ test bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0SDIFRDATAR" description="DTS TS0 SDIF RDATA register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_RDATA" description="SDIF read data" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0SDIFDONER" description="DTS TS0 SDIF done register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_SMPL_DONE" description="Sample done flag " start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new data sample available" start="0x0" />
+        <Enum name="B_0x1" description="New data sample available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TS0SDIFDATAR" description="DTS TS0 SDIF data register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAMPLE_DATA" description="Sample data. " start="0" size="16" access="ReadOnly" />
+      <BitField name="SAMPLE_TYPE" description="TS sample type" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Indicates valid data" start="0x0" />
+        <Enum name="B_0x1" description="Indicates either analog access, signature select or fault debug mode" start="0x1" />
+      </BitField>
+      <BitField name="SAMPLE_FAULT" description="Sample fault" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0ALARMA_CFGR" description="DTS TS0 alarm A configuration register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTA_THRESH" description="Alarm A hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMA_THRESH" description="Alarm A threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0ALARMB_CFGR" description="DTS TS0 alarm B configuration register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTB_THRESH" description="Alarm B hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMB_THRESH" description="Alarm B threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0HLSAMPLER" description="DTS TS0 high/low sample register" start="+0xE8" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO" description="Lowest valid data sample value received" start="0" size="16" access="ReadOnly" />
+      <BitField name="SMPL_HI" description="Highest valid data sample value received" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0HILORESETR" description="DTS TS0 high/low reset register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO_SET" description="Sample Low Set" start="0" size="1" access="WriteOnly" />
+      <BitField name="SMPL_HI_CLR" description="Sample high clear 0" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS1_IER" description="DTS TS1 IRQ enable register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_EN_FAULT" description="Fault IRQ enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_DONE" description="Sample done IRQ enable bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMA" description="Alarm A IRQ enable bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMB" description="Alarm B IRQ enable bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1_ISR" description="DTS TS1 IRQ status register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_STATUS_FAULT" description="Fault IRQ status bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_DONE" description="Sample done IRQ status bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMA" description="Alarm A IRQ status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMB" description="Alarm B IRQ status bit" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1_ICR" description="DTS TS1 IRQ clear register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_CLEAR_FAULT" description="Fault IRQ clear bit" start="0" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_DONE" description="Sample done IRQ clear bit" start="1" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMA" description="Alarm A IRQ clear bit" start="3" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMB" description="Alarm B IRQ clear bit" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS1IRQTESTR" description="DTS TS1 IRQ test register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_TEST_FAULT" description="Fault IRQ test bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_DONE" description="Sample done IRQ test bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMA" description="Alarm A IRQ test bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMB" description="Alarm B IRQ test bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1SDIFRDATAR" description="DTS TS1 SDIF RDATA register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_RDATA" description="SDIF read data" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1SDIFDONER" description="DTS TS1 SDIF done register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_SMPL_DONE" description="Sample done flag " start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new data sample available" start="0x0" />
+        <Enum name="B_0x1" description="New data sample available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TS1SDIFDATAR" description="DTS TS1 SDIF data register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAMPLE_DATA" description="Sample data. " start="0" size="16" access="ReadOnly" />
+      <BitField name="SAMPLE_TYPE" description="TS sample type" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Indicates valid data" start="0x0" />
+        <Enum name="B_0x1" description="Indicates either analog access, signature select or fault debug mode" start="0x1" />
+      </BitField>
+      <BitField name="SAMPLE_FAULT" description="Sample fault" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1ALARMA_CFGR" description="DTS TS1 alarm A configuration register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTA_THRESH" description="Alarm A hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMA_THRESH" description="Alarm A threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1ALARMB_CFGR" description="DTS TS1 alarm B configuration register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTB_THRESH" description="Alarm B hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMB_THRESH" description="Alarm B threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1HLSAMPLER" description="DTS TS1 high/low sample register" start="+0x128" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO" description="Lowest valid data sample value received" start="0" size="16" access="ReadOnly" />
+      <BitField name="SMPL_HI" description="Highest valid data sample value received" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1HILORESETR" description="DTS TS1 high/low reset register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO_SET" description="Sample Low Set" start="0" size="1" access="WriteOnly" />
+      <BitField name="SMPL_HI_CLR" description="Sample high clear 0" start="1" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DTS_S" description="Digital temperature sensor" start="0x5600A000">
+    <Register name="DTS_PVTREG_LOCKR" description="DTS PVT register lock register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK" description="PVT software lock register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTLOCK_SR" description="DTS PVT lock status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SW_LOCK_STATUS" description="Software lock input status" start="0" size="1" access="ReadOnly" />
+      <BitField name="HW_LOCK_STATUS" description="Hardware lock input status" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVTTMR_CR" description="DTS PVT timer control register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_DELAY" description="Timer delay" start="0" size="16" access="Read/Write" />
+      <BitField name="TMR_RUN" description="Timer count enable bit" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTTMR_SR" description="DTS PVT timer status register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_BUSY" description="Counter busy flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TMR_DONE" description="Counter delay expiration flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVT_IER" description="DTS PVT IRQ enable register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_ENABLE" description="Timer IRQ source enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="TS_IRQ_ENABLE" description="TS IRQ source enable bit" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTIRQTRMASKR" description="DTS PVT IRQ timer mask register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_MASK" description="Timer IRQ source mask bit" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS_MR" description="DTS PVT IRQ TS mask register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_MASK" description="TS0 IRQ source mask bit" start="0" size="1" access="Read/Write" />
+      <BitField name="TS1_IRQ_MASK" description="TS1 IRQ source mask bit" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_PVTTR_SR" description="DTS PVT IRQ timer status register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_STATUS" description="Timer IRQ status bit after masking" start="0" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS_ISR" description="DTS PVT IRQ TS status register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_STATUS" description="TS0 IRQ status bit after masking" start="0" size="1" access="ReadOnly" />
+      <BitField name="TS1_IRQ_STATUS" description="TS1 IRQ status bit after masking" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_PVTTMRRAW_ISR" description="DTS PVT IRQ timer raw status register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMR_IRQ_RAW_STATUS" description="TMR IRQ status bit before masking" start="0" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TSRAW_ISR" description="DTS PVT IRQ TS raw status register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_IRQ_RAW_STATUS" description="TS0 IRQ status bit before masking" start="0" size="1" access="ReadOnly" />
+      <BitField name="TS1_IRQ_RAW_STATUS" description="TS1 IRQ status bit before masking" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TSCCLKSYNTHR" description="DTS TSC clock synthesizer register" start="+0x080" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLK_SYNTH_LO" description="Synthesized clk_ts low period" start="0" size="8" access="Read/Write" />
+      <BitField name="CLK_SYNTH_HI" description="Synthesized clk_ts high period" start="8" size="8" access="Read/Write" />
+      <BitField name="CLK_SYNTH_HOLD" description="SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay" start="16" size="4" access="Read/Write" />
+      <BitField name="CLK_SYTH_EN" description="Synthesized clk_ts enable bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFDISABLER" description="DTS TSC SDIF interface disable register" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS0_SDIF_DISABLE" description="TS0 serial data interface (SDIF) disable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enabled" start="0x0" />
+        <Enum name="B_0x1" description="Disabled" start="0x1" />
+      </BitField>
+      <BitField name="TS1_SDIF_DISABLE" description="TS1 serial data interface (SDIF) disable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enabled" start="0x0" />
+        <Enum name="B_0x1" description="Disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_SR" description="DTS TSC SDIF status register" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_BUSY" description="SDIF busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SDIF not busy/no clock synthesizer/disable SDIF state update ongoing" start="0x0" />
+        <Enum name="B_0x1" description="SDIF busy/clock synthesizer/disable SDIF state update ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SDIF_LOCK" description="SDIF locked flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Unlocked" start="0x0" />
+        <Enum name="B_0x1" description="Locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_CR" description="DTS TSC SDIF register" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_WDATA" description="Serial interface write data" start="0" size="24" access="Read/Write" />
+      <BitField name="SDIF_ADDR" description="Serial interface register address" start="24" size="3" access="Read/Write" />
+      <BitField name="SDIF_WRN" description="Serial interface write/no read control bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIF read" start="0x0" />
+        <Enum name="B_0x1" description="SDIF write" start="0x1" />
+      </BitField>
+      <BitField name="SDIF_PROG" description="Serial interface program request" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No SDIF program request" start="0x0" />
+        <Enum name="B_0x1" description="SDIF program requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFHALTR" description="DTS TSC SDIF halt register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_STOP" description="Serial data interface (SDIF) stop " start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Not stopped" start="0x0" />
+        <Enum name="B_0x1" description="Stopped" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIF_CFGR" description="DTS TSC SDIF control register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_INHIBIT" description="Serial data interface (SDIF) programming inhibit " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Inhibition" start="0x0" />
+        <Enum name="B_0x1" description="TS0 inhibited/TS1 serial programming activated (SPA)" start="0x1" />
+        <Enum name="B_0x2" description="TS1 inhibited/TS0 serial programming activated (SPA)" start="0x2" />
+        <Enum name="B_0x3" description="TS1 and TS0 inhibited" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSMPL_CR" description="DTS TSC sample control register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_CTR_DISABLE" description="Sample counter disable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sample counter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Sample counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="SMPL_CTR_HOLD" description="Sample counter hold bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter not on hold" start="0x0" />
+        <Enum name="B_0x1" description="Counter on hold" start="0x1" />
+      </BitField>
+      <BitField name="SMPL_DISCARD" description="Sample discard bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data samples not discarded" start="0x0" />
+        <Enum name="B_0x1" description="Data samples discarded" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSDIFSMPLCLRR" description="DTS TSC sample clear register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_CNTER_CLEAR" description="Sample counter clear bit " start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Counter value not cleared" start="0x0" />
+        <Enum name="B_0x1" description="Counter value cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TSCSMPLCNTR" description="DTS TSC sample count register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_COUNT" description="Sample counter" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0_IER" description="DTS TS0 IRQ enable register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_EN_FAULT" description="Fault IRQ enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_DONE" description="Sample done IRQ enable bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMA" description="Alarm A IRQ enable bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMB" description="Alarm B IRQ enable bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0_ISR" description="DTS TS0 IRQ status register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_STATUS_FAULT" description="Fault IRQ status bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_DONE" description="Sample done IRQ status bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMA" description="Alarm A IRQ status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMB" description="Alarm B IRQ status bit" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0_ICR" description="DTS TS0 IRQ clear register" start="+0xC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_CLEAR_FAULT" description="Fault IRQ clear bit" start="0" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_DONE" description="Sample done IRQ clear bit" start="1" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMA" description="Alarm A IRQ clear bit" start="3" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMB" description="Alarm B IRQ clear bit" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS0IRQTESTR" description="DTS TS0 IRQ test register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_TEST_FAULT" description="Fault IRQ test bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_DONE" description="Sample done IRQ test bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMA" description="Alarm A IRQ test bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMB" description="Alarm B IRQ test bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0SDIFRDATAR" description="DTS TS0 SDIF RDATA register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_RDATA" description="SDIF read data" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0SDIFDONER" description="DTS TS0 SDIF done register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_SMPL_DONE" description="Sample done flag " start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new data sample available" start="0x0" />
+        <Enum name="B_0x1" description="New data sample available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TS0SDIFDATAR" description="DTS TS0 SDIF data register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAMPLE_DATA" description="Sample data. " start="0" size="16" access="ReadOnly" />
+      <BitField name="SAMPLE_TYPE" description="TS sample type" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Indicates valid data" start="0x0" />
+        <Enum name="B_0x1" description="Indicates either analog access, signature select or fault debug mode" start="0x1" />
+      </BitField>
+      <BitField name="SAMPLE_FAULT" description="Sample fault" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0ALARMA_CFGR" description="DTS TS0 alarm A configuration register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTA_THRESH" description="Alarm A hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMA_THRESH" description="Alarm A threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0ALARMB_CFGR" description="DTS TS0 alarm B configuration register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTB_THRESH" description="Alarm B hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMB_THRESH" description="Alarm B threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS0HLSAMPLER" description="DTS TS0 high/low sample register" start="+0xE8" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO" description="Lowest valid data sample value received" start="0" size="16" access="ReadOnly" />
+      <BitField name="SMPL_HI" description="Highest valid data sample value received" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS0HILORESETR" description="DTS TS0 high/low reset register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO_SET" description="Sample Low Set" start="0" size="1" access="WriteOnly" />
+      <BitField name="SMPL_HI_CLR" description="Sample high clear 0" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS1_IER" description="DTS TS1 IRQ enable register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_EN_FAULT" description="Fault IRQ enable bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_DONE" description="Sample done IRQ enable bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMA" description="Alarm A IRQ enable bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_EN_ALARMB" description="Alarm B IRQ enable bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1_ISR" description="DTS TS1 IRQ status register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_STATUS_FAULT" description="Fault IRQ status bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_DONE" description="Sample done IRQ status bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMA" description="Alarm A IRQ status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="IRQ_STATUS_ALARMB" description="Alarm B IRQ status bit" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1_ICR" description="DTS TS1 IRQ clear register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_CLEAR_FAULT" description="Fault IRQ clear bit" start="0" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_DONE" description="Sample done IRQ clear bit" start="1" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMA" description="Alarm A IRQ clear bit" start="3" size="1" access="WriteOnly" />
+      <BitField name="IRQ_CLEAR_ALARMB" description="Alarm B IRQ clear bit" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="DTS_TS1IRQTESTR" description="DTS TS1 IRQ test register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IRQ_TEST_FAULT" description="Fault IRQ test bit" start="0" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_DONE" description="Sample done IRQ test bit" start="1" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMA" description="Alarm A IRQ test bit" start="3" size="1" access="Read/Write" />
+      <BitField name="IRQ_TEST_ALARMB" description="Alarm B IRQ test bit" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1SDIFRDATAR" description="DTS TS1 SDIF RDATA register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_RDATA" description="SDIF read data" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1SDIFDONER" description="DTS TS1 SDIF done register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDIF_SMPL_DONE" description="Sample done flag " start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new data sample available" start="0x0" />
+        <Enum name="B_0x1" description="New data sample available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="DTS_TS1SDIFDATAR" description="DTS TS1 SDIF data register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAMPLE_DATA" description="Sample data. " start="0" size="16" access="ReadOnly" />
+      <BitField name="SAMPLE_TYPE" description="TS sample type" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Indicates valid data" start="0x0" />
+        <Enum name="B_0x1" description="Indicates either analog access, signature select or fault debug mode" start="0x1" />
+      </BitField>
+      <BitField name="SAMPLE_FAULT" description="Sample fault" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1ALARMA_CFGR" description="DTS TS1 alarm A configuration register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTA_THRESH" description="Alarm A hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMA_THRESH" description="Alarm A threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1ALARMB_CFGR" description="DTS TS1 alarm B configuration register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HYSTB_THRESH" description="Alarm B hysteresis threshold" start="0" size="16" access="Read/Write" />
+      <BitField name="ALARMB_THRESH" description="Alarm B threshold" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="DTS_TS1HLSAMPLER" description="DTS TS1 high/low sample register" start="+0x128" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO" description="Lowest valid data sample value received" start="0" size="16" access="ReadOnly" />
+      <BitField name="SMPL_HI" description="Highest valid data sample value received" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="DTS_TS1HILORESETR" description="DTS TS1 high/low reset register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPL_LO_SET" description="Sample Low Set" start="0" size="1" access="WriteOnly" />
+      <BitField name="SMPL_HI_CLR" description="Sample high clear 0" start="1" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ETH" description="Ethernet address block description" start="0x48036000">
+    <Register name="ETH_MACCR" description="Operating mode configuration register" start="+0x0000" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Receiver Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TE" description="Transmitter Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="PRELEN" description="Preamble Length for Transmit packets" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="7 bytes of preamble" start="0x0" />
+        <Enum name="B_0x1" description="5 bytes of preamble" start="0x1" />
+        <Enum name="B_0x2" description="3 bytes of preamble" start="0x2" />
+      </BitField>
+      <BitField name="DC" description="Deferral Check" start="4" size="1" access="Read/Write" />
+      <BitField name="BL" description="Back-Off Limit" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="k= min (n, 10)" start="0x0" />
+        <Enum name="B_0x1" description="k = min (n, 8)" start="0x1" />
+        <Enum name="B_0x2" description="k = min (n, 4)" start="0x2" />
+        <Enum name="B_0x3" description="k = min (n, 1)" start="0x3" />
+      </BitField>
+      <BitField name="DR" description="Disable Retry" start="8" size="1" access="Read/Write" />
+      <BitField name="DCRS" description="Disable Carrier Sense During Transmission" start="9" size="1" access="Read/Write" />
+      <BitField name="DO" description="Disable Receive Own" start="10" size="1" access="Read/Write" />
+      <BitField name="ECRSFD" description="Enable Carrier Sense Before Transmission in Full-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="LM" description="Loopback Mode" start="12" size="1" access="Read/Write" />
+      <BitField name="DM" description="Duplex Mode" start="13" size="1" access="Read/Write" />
+      <BitField name="FES" description="MAC Speed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10 Mbps" start="0x0" />
+        <Enum name="B_0x1" description="100 Mbps" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Port Select" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="For 1000 Mbps operations" start="0x0" />
+        <Enum name="B_0x1" description="For 10 or 100 Mbps operations" start="0x1" />
+      </BitField>
+      <BitField name="JE" description="Jumbo Packet Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="JD" description="Jabber Disable" start="17" size="1" access="Read/Write" />
+      <BitField name="BE" description="Packet Burst Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="WD" description="Watchdog Disable" start="19" size="1" access="Read/Write" />
+      <BitField name="ACS" description="Automatic Pad or CRC Stripping" start="20" size="1" access="Read/Write" />
+      <BitField name="CST" description="CRC stripping for Type packets" start="21" size="1" access="Read/Write" />
+      <BitField name="S2KP" description="IEEE 802.3as Support for 2K Packets" start="22" size="1" access="Read/Write" />
+      <BitField name="GPSLCE" description="Giant Packet Size Limit Control Enable" start="23" size="1" access="Read/Write" />
+      <BitField name="IPG" description="Inter-Packet Gap" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="96 bit times" start="0x0" />
+        <Enum name="B_0x1" description="88 bit times" start="0x1" />
+        <Enum name="B_0x2" description="80 bit times" start="0x2" />
+        <Enum name="B_0x7" description="40 bit times" start="0x7" />
+      </BitField>
+      <BitField name="IPC" description="Checksum Offload" start="27" size="1" access="Read/Write" />
+      <BitField name="SARC" description="Source Address Insertion or Replacement Control" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="the MAC inserts the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x2" />
+        <Enum name="B_0x3" description="the MAC replaces the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x3" />
+        <Enum name="B_0x6" description="the MAC inserts the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets" start="0x6" />
+        <Enum name="B_0x7" description="the MAC replaces the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x7" />
+      </BitField>
+      <BitField name="ARPEN" description="ARP Offload Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACECR" description="Extended operating mode configuration register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPSL" description="Giant Packet Size Limit" start="0" size="14" access="Read/Write" />
+      <BitField name="DCRCC" description="Disable CRC Checking for Received Packets" start="16" size="1" access="Read/Write" />
+      <BitField name="SPEN" description="Slow Protocol Detection Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="USP" description="Unicast Slow Protocol Packet Detect" start="18" size="1" access="Read/Write" />
+      <BitField name="EIPGEN" description="Extended Inter-Packet Gap Enable" start="24" size="1" access="Read/Write" />
+      <BitField name="EIPG" description="Extended Inter-Packet Gap" start="25" size="5" access="Read/Write" />
+      <BitField name="APDIM" description="ARP Packet Drop if IP Address Mismatch" start="30" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPFR" description="Packet filtering control register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="Promiscuous Mode" start="0" size="1" access="Read/Write" />
+      <BitField name="HUC" description="Hash Unicast" start="1" size="1" access="Read/Write" />
+      <BitField name="HMC" description="Hash Multicast" start="2" size="1" access="Read/Write" />
+      <BitField name="DAIF" description="DA Inverse Filtering" start="3" size="1" access="Read/Write" />
+      <BitField name="PM" description="Pass All Multicast" start="4" size="1" access="Read/Write" />
+      <BitField name="DBF" description="Disable Broadcast Packets" start="5" size="1" access="Read/Write" />
+      <BitField name="PCF" description="Pass Control Packets" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The MAC filters all control packets from reaching the application." start="0x0" />
+        <Enum name="B_0x1" description="The MAC forwards all control packets except Pause packets to the application even if they fail the Address filter." start="0x1" />
+        <Enum name="B_0x2" description="The MAC forwards all control packets to the application even if they fail the Address filter." start="0x2" />
+        <Enum name="B_0x3" description="The MAC forwards the control packets that pass the Address filter." start="0x3" />
+      </BitField>
+      <BitField name="SAIF" description="SA Inverse Filtering" start="8" size="1" access="Read/Write" />
+      <BitField name="SAF" description="Source Address Filter Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="HPF" description="Hash or Perfect Filter" start="10" size="1" access="Read/Write" />
+      <BitField name="VTFE" description="VLAN Tag Filter Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="IPFE" description="Layer 3 and Layer 4 Filter Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="DNTU" description="Drop Non-TCP/UDP over IP Packets" start="21" size="1" access="Read/Write" />
+      <BitField name="RA" description="Receive All" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACWTR" description="Watchdog timeout register" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WTO" description="Watchdog Timeout" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="2 Kbytes" start="0x0" />
+        <Enum name="B_0x1" description="3 Kbytes" start="0x1" />
+        <Enum name="B_0x2" description="4 Kbytes" start="0x2" />
+        <Enum name="B_0x3" description="5 Kbytes" start="0x3" />
+        <Enum name="B_0xC" description="14 Kbytes" start="0xC" />
+        <Enum name="B_0xD" description="15 Kbytes" start="0xD" />
+        <Enum name="B_0xE" description="16383 Bytes" start="0xE" />
+      </BitField>
+      <BitField name="PWE" description="Programmable Watchdog Enable" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACHT0R" description="Hash Table 0 register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT31T0" description="MAC Hash Table First 32 Bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACHT1R" description="Hash Table 1 register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT63T32" description="MAC Hash Table Second 32 Bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVTCR" description="VLAN tag Control register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OB" description="Operation Busy" start="0" size="1" access="Read/Write" />
+      <BitField name="CT" description="Command Type" start="1" size="1" access="Read/Write" />
+      <BitField name="OFS" description="Offset" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="ETH_MACVTDR holds MAC VLAN Tag Filter0 content" start="0x0" />
+        <Enum name="B_0x1" description="ETH_MACVTDR holds MAC VLAN Tag Filter1 content" start="0x1" />
+        <Enum name="B_0x2" description="ETH_MACVTDR holds MAC VLAN Tag Filter2 content" start="0x2" />
+        <Enum name="B_0x3" description="ETH_MACVTDR holds MAC VLAN Tag Filter3 content" start="0x3" />
+      </BitField>
+      <BitField name="ETV" description="Enable 12-Bit VLAN Tag Comparison" start="16" size="1" access="Read/Write" />
+      <BitField name="VTIM" description="VLAN Tag Inverse Match Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="ESVL" description="Enable S-VLAN" start="18" size="1" access="Read/Write" />
+      <BitField name="ERSVLM" description="Enable Receive S-VLAN Match" start="19" size="1" access="Read/Write" />
+      <BitField name="DOVLTC" description="Disable VLAN Type Check" start="20" size="1" access="Read/Write" />
+      <BitField name="EVLS" description="Enable VLAN Tag Stripping on Receive" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Do not strip" start="0x0" />
+        <Enum name="B_0x1" description="Strip if VLAN filter passes" start="0x1" />
+        <Enum name="B_0x2" description="Strip if VLAN filter fails" start="0x2" />
+        <Enum name="B_0x3" description="Always strip" start="0x3" />
+      </BitField>
+      <BitField name="EVLRXS" description="Enable VLAN Tag in Rx status" start="24" size="1" access="Read/Write" />
+      <BitField name="VTHM" description="VLAN Tag Hash Table Match Enable" start="25" size="1" access="Read/Write" />
+      <BitField name="EDVLP" description="Enable Double VLAN Processing" start="26" size="1" access="Read/Write" />
+      <BitField name="ERIVLT" description="Enable Inner VLAN Tag" start="27" size="1" access="Read/Write" />
+      <BitField name="EIVLS" description="Enable Inner VLAN Tag Stripping on Receive" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Do not strip" start="0x0" />
+        <Enum name="B_0x1" description="Strip if VLAN filter passes" start="0x1" />
+        <Enum name="B_0x2" description="Strip if VLAN filter fails" start="0x2" />
+        <Enum name="B_0x3" description="Always strip" start="0x3" />
+      </BitField>
+      <BitField name="EIVLRXS" description="Enable Inner VLAN Tag in Rx Status" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVTDR" description="VLAN tag data register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VID" description="VLAN Tag ID" start="0" size="16" access="Read/Write" />
+      <BitField name="VEN" description="VLAN Tag Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="ETV" description="12-bit or 16-bit VLAN comparison" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit VLAN" start="0x0" />
+        <Enum name="B_0x1" description="12-bit VLAN" start="0x1" />
+      </BitField>
+      <BitField name="DOVLTC" description="Disable VLAN Type Comparison" start="18" size="1" access="Read/Write" />
+      <BitField name="ERSVLM" description="Enable S-VLAN Match for received Frames" start="19" size="1" access="Read/Write" />
+      <BitField name="ERIVLT" description="Enable Inner VLAN Tag Comparison" start="20" size="1" access="Read/Write" />
+      <BitField name="DMACHEN" description="DMA Channel Number Enable" start="24" size="1" access="Read/Write" />
+      <BitField name="DMACHN" description="DMA Channel Number" start="25" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVHTR" description="VLAN Hash table register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLHT" description="VLAN Hash Table" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVIR" description="VLAN inclusion register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="VLC" description="VLAN Tag Control in Transmit Packets" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No VLAN tag deletion, insertion, or replacement" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag deletion. The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags." start="0x1" />
+        <Enum name="B_0x2" description="VLAN tag insertion. The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and 14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag." start="0x2" />
+        <Enum name="B_0x3" description="VLAN tag replacement. The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8)." start="0x3" />
+      </BitField>
+      <BitField name="VLP" description="VLAN Priority Control" start="18" size="1" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+      <BitField name="VLTI" description="VLAN Tag Input" start="20" size="1" access="Read/Write" />
+      <BitField name="CBTI" description="Channel based tag insertion" start="21" size="1" access="Read/Write" />
+      <BitField name="ADDR" description="Address" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VLAN tag for insertion in the Transmit packets from Tx Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag for insertion in the Transmit packets from Tx Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="RDWR" description="Read write control" start="30" size="1" access="Read/Write" />
+      <BitField name="BUSY" description="Busy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACVIR_alternate" description="VLAN inclusion register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACIVIR" description="Inner VLAN inclusion register" start="+0x0064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="VLC" description="VLAN Tag Control in Transmit Packets" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No VLAN tag deletion, insertion, or replacement" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag deletion" start="0x1" />
+        <Enum name="B_0x2" description="VLAN tag insertion" start="0x2" />
+        <Enum name="B_0x3" description="VLAN tag replacement" start="0x3" />
+      </BitField>
+      <BitField name="VLP" description="VLAN Priority Control" start="18" size="1" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+      <BitField name="VLTI" description="VLAN Tag Input" start="20" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACQ0TXFCR" description="Tx Queue 0 flow control register" start="+0x0070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCB_BPA" description="Flow Control Busy or Backpressure Activate" start="0" size="1" access="Read/Write" />
+      <BitField name="TFE" description="Transmit Flow Control Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="PLT" description="Pause Low Threshold" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Pause Time minus 4 Slot Times (PT -4 slot times)" start="0x0" />
+        <Enum name="B_0x1" description="Pause Time minus 28 Slot Times (PT -28 slot times)" start="0x1" />
+        <Enum name="B_0x2" description="Pause Time minus 36 Slot Times (PT -36 slot times)" start="0x2" />
+        <Enum name="B_0x3" description="Pause Time minus 144 Slot Times (PT -144 slot times)" start="0x3" />
+        <Enum name="B_0x4" description="Pause Time minus 256 Slot Times (PT -256 slot times)" start="0x4" />
+        <Enum name="B_0x5" description="Pause Time minus 512 Slot Times (PT -512 slot times)" start="0x5" />
+      </BitField>
+      <BitField name="DZPQ" description="Disable Zero-Quanta Pause" start="7" size="1" access="Read/Write" />
+      <BitField name="PT" description="Pause Time" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXFCR" description="Rx flow control register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RFE" description="Receive Flow Control Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="UP" description="Unicast Pause Packet Detect" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXQCR" description="Rx Queue control register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFQE" description="Unicast Address Filter Fail Packets Queuing Enable." start="0" size="1" access="Read/Write" />
+      <BitField name="UFFQ" description="Unicast Address Filter Fail Packets Queue." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MFFQE" description="Multicast Address Filter Fail Packets Queuing Enable." start="8" size="1" access="Read/Write" />
+      <BitField name="MFFQ" description="Multicast Address Filter Fail Packets Queue." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="VFFQE" description="VLAN Tag Filter Fail Packets Queuing Enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="VFFQ" description="VLAN Tag Filter Fail Packets Queue" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACRXQC0R" description="Rx queue control 0 register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ0EN" description="Receive Queue 0 Enable" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Queue 0 enabled for AV" start="0x1" />
+        <Enum name="B_0x2" description="Queue 0 enabled for Generic traffic" start="0x2" />
+      </BitField>
+      <BitField name="RXQ1EN" description="Receive Queue 1 Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1 enabled for AV" start="0x1" />
+        <Enum name="B_0x2" description="Queue 1 enabled for Generic traffic" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACRXQC1R" description="Rx queue control 1 register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVCPQ0" description="AV Untagged Control Packets Queue" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="AVCPQ1" description="AV Untagged Control Packets Queue" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="AVCPQ2" description="AV Untagged Control Packets Queue" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="PTPQ" description="PTP Packets Queue" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="UPQ" description="Untagged Packet Queue " start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MCBCQ" description="Multicast and Broadcast Queue " start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MCBCQEN" description="Multicast and Broadcast Queue Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="TACPQE" description="Tagged AV Control Packets Queuing Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="TPQC" description="Tagged PTP over Ethernet Packets Queuing Control" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="VLAN tagged PTPoE packets are routed as generic VLAN tagged packet (based on PSRQ for only non-AV enabled Rx queues)." start="0x0" />
+        <Enum name="B_0x1" description="VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field (this Rx Queue can be enabled for AV or non-AV traffic)" start="0x1" />
+        <Enum name="B_0x2" description="VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ." start="0x2" />
+      </BitField>
+      <BitField name="FPRQ0" description="Frame Preemption Residue Queue" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="FPRQ1" description="Frame Preemption Residue Queue" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="FPRQ2" description="Frame Preemption Residue Queue" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="OMCBCQ" description="Overriding MC-BC queue priority select" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Priority of MCBCQ is reduced and the received packet is first routed to PTPQ, AVCPQ, depending on packet type." start="0x1" />
+        <Enum name="B_0x0" description="Received Multicast/Broadcast packet is routed to MCBCQ." start="0x0" />
+      </BitField>
+      <BitField name="TBRQE" description="Type Field Based Rx Queuing Enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXQC2R" description="Rx queue control 2 register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSRQ0" description="Priorities Selected in the Receive Queue 0" start="0" size="8" access="Read/Write" />
+      <BitField name="PSRQ1" description="Priorities Selected in the Receive Queue 1" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACISR" description="Interrupt status register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RGSMIIIS" description="RGMII Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PHYIS" description="PHY Interrupt" start="3" size="1" access="ReadOnly" />
+      <BitField name="PMTIS" description="PMT Interrupt Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="LPIIS" description="LPI Interrupt Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="MMCIS" description="MMC Interrupt Status" start="8" size="1" access="ReadOnly" />
+      <BitField name="MMCRXIS" description="MMC Receive Interrupt Status" start="9" size="1" access="ReadOnly" />
+      <BitField name="MMCTXIS" description="MMC Transmit Interrupt Status" start="10" size="1" access="ReadOnly" />
+      <BitField name="TSIS" description="Timestamp Interrupt Status" start="12" size="1" access="Read/Write" />
+      <BitField name="TXSTSIS" description="Transmit Status Interrupt" start="13" size="1" access="Read/Write" />
+      <BitField name="RXSTSIS" description="Receive Status Interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="FPEIS" description="Frame Preemption Interrupt Status" start="17" size="1" access="ReadOnly" />
+      <BitField name="MDIOIS" description="MDIO Interrupt Status" start="18" size="1" access="Read/Write" />
+      <BitField name="MFTIS" description="MMC FPE Transmit Interrupt Status" start="19" size="1" access="ReadOnly" />
+      <BitField name="MFRIS" description="MMC FPE Receive Interrupt Status" start="20" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACIER" description="Interrupt enable register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RGSMIIIE" description="RGMII Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="PHYIE" description="PHY Interrupt Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="PMTIE" description="PMT Interrupt Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="LPIIE" description="LPI Interrupt Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TSIE" description="Timestamp Interrupt Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="TXSTSIE" description="Transmit Status Interrupt Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="RXSTSIE" description="Receive Status Interrupt Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="FPEIE" description="Frame Preemption Interrupt Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="MDIOIE" description="MDIO Interrupt Enable" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXTXSR" description="Rx Tx status register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TJT" description="Transmit Jabber Timeout" start="0" size="1" access="Read/Write" />
+      <BitField name="NCARR" description="No Carrier" start="1" size="1" access="Read/Write" />
+      <BitField name="LCARR" description="Loss of Carrier" start="2" size="1" access="Read/Write" />
+      <BitField name="EXDEF" description="Excessive Deferral" start="3" size="1" access="Read/Write" />
+      <BitField name="LCOL" description="Late Collision" start="4" size="1" access="Read/Write" />
+      <BitField name="EXCOL" description="Excessive Collisions" start="5" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPCSR" description="PMT control status register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDWN" description="Power Down" start="0" size="1" access="Read/Write" />
+      <BitField name="MGKPKTEN" description="Magic Packet Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="RWKPKTEN" description="Remote wake-up Packet Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="MGKPRCVD" description="Magic Packet Received" start="5" size="1" access="Read/Write" />
+      <BitField name="RWKPRCVD" description="Remote wake-up Packet Received" start="6" size="1" access="ReadOnly" />
+      <BitField name="GLBLUCAST" description="Global Unicast" start="9" size="1" access="Read/Write" />
+      <BitField name="RWKPFE" description="Remote wake-up Packet Forwarding Enable " start="10" size="1" access="Read/Write" />
+      <BitField name="RWKPTR" description="Remote wake-up FIFO Pointer" start="24" size="5" access="ReadOnly" />
+      <BitField name="RWKFILTRST" description="Remote wake-up Packet Filter Register Pointer Reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRWKPFR" description="Remote wake-up packet filter register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MACRWKPFR" description="Remote wake-up packet filter" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLCSR" description="LPI control and status register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TLPIEN" description="Transmit LPI Entry" start="0" size="1" access="ReadOnly" />
+      <BitField name="TLPIEX" description="Transmit LPI Exit" start="1" size="1" access="ReadOnly" />
+      <BitField name="RLPIEN" description="Receive LPI Entry" start="2" size="1" access="ReadOnly" />
+      <BitField name="RLPIEX" description="Receive LPI Exit" start="3" size="1" access="ReadOnly" />
+      <BitField name="TLPIST" description="Transmit LPI State" start="8" size="1" access="ReadOnly" />
+      <BitField name="RLPIST" description="Receive LPI State" start="9" size="1" access="ReadOnly" />
+      <BitField name="LPIEN" description="LPI Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="PLS" description="PHY Link Status" start="17" size="1" access="Read/Write" />
+      <BitField name="PLSEN" description="PHY Link Status Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="LPITXA" description="LPI Tx Automate" start="19" size="1" access="Read/Write" />
+      <BitField name="LPITE" description="LPI Timer Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="LPITCSE" description="LPI Tx Clock Stop Enable" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLTCR" description="LPI timers control register" start="+0x00D4" size="4" reset_value="0x03E80000" reset_mask="0xFFFFFFFF">
+      <BitField name="TWT" description="LPI TW Timer" start="0" size="16" access="Read/Write" />
+      <BitField name="LST" description="LPI LS Timer" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLETR" description="LPI entry timer register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPIET" description="LPI Entry Timer" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MAC1USTCR" description="One-microsecond-tick counter register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIC_1US_CNTR" description="1 s tick Counter" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPHYCSR" description="PHYIF control status register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TC" description="Transmit Configuration in RGMII" start="0" size="1" access="Read/Write" />
+      <BitField name="LUD" description="Link Up or Down" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Link Down" start="0x0" />
+        <Enum name="B_0x1" description="Link Up" start="0x1" />
+      </BitField>
+      <BitField name="LNKMOD" description="Link Mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Half-duplex mode" start="0x0" />
+        <Enum name="B_0x1" description="Full-duplex mode" start="0x1" />
+      </BitField>
+      <BitField name="LNKSPEED" description="Link Speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="2.5 MHz" start="0x0" />
+        <Enum name="B_0x1" description="25 MHz" start="0x1" />
+        <Enum name="B_0x2" description="125 MHz" start="0x2" />
+      </BitField>
+      <BitField name="LNKSTS" description="Link Status" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Link down" start="0x0" />
+        <Enum name="B_0x1" description="Link up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACVR" description="Version register" start="+0x0110" size="4" reset_value="0x00001052" reset_mask="0xFFFFFFFF">
+      <BitField name="SNPSVER" description="IP version" start="0" size="8" access="ReadOnly" />
+      <BitField name="USERVER" description="ST-defined version" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACDR" description="Debug register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPESTS" description="MAC GMII or MII Receive Protocol Engine Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RFCFCSTS" description="MAC Receive Packet Controller FIFO Status" start="1" size="2" access="ReadOnly" />
+      <BitField name="TPESTS" description="MAC GMII or MII Transmit Protocol Engine Status" start="16" size="1" access="ReadOnly" />
+      <BitField name="TFCSTS" description="MAC Transmit Packet Controller Status" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Waiting for one of the following:" start="0x1" />
+        <Enum name="B_0x2" description="Generating and transmitting a Pause control packet (in Full-duplex mode)" start="0x2" />
+        <Enum name="B_0x3" description="Transferring input packet for transmission" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF0R" description="HW feature 0 register" start="+0x011C" size="4" reset_value="0x0E0D73F7" reset_mask="0xFFFFFFFF">
+      <BitField name="MIISEL" description="10 or 100 Mbps Support" start="0" size="1" access="ReadOnly" />
+      <BitField name="GMIISEL" description="1000 Mbps Support" start="1" size="1" access="ReadOnly" />
+      <BitField name="HDSEL" description="Half-duplex Support" start="2" size="1" access="ReadOnly" />
+      <BitField name="PCSSEL" description="PCS Registers (TBI, SGMII, or RTBI PHY interface)" start="3" size="1" access="ReadOnly" />
+      <BitField name="VLHASH" description="VLAN Hash Filter Selected" start="4" size="1" access="ReadOnly" />
+      <BitField name="SMASEL" description="SMA (MDIO) Interface" start="5" size="1" access="ReadOnly" />
+      <BitField name="RWKSEL" description="PMT Remote wake-up Packet Enable" start="6" size="1" access="ReadOnly" />
+      <BitField name="MGKSEL" description="PMT Magic Packet Enable" start="7" size="1" access="ReadOnly" />
+      <BitField name="MMCSEL" description="RMON Module Enable" start="8" size="1" access="ReadOnly" />
+      <BitField name="ARPOFFSEL" description="ARP Offload Enabled" start="9" size="1" access="ReadOnly" />
+      <BitField name="TSSEL" description="IEEE 1588-2008 Timestamp Enabled" start="12" size="1" access="ReadOnly" />
+      <BitField name="EEESEL" description="Energy Efficient Ethernet Enabled" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXCOESEL" description="Transmit Checksum Offload Enabled" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXCOESEL" description="Receive Checksum Offload Enabled" start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDMACADRSEL" description="MAC Addresses 1-31 Selected" start="18" size="5" access="ReadOnly" />
+      <BitField name="MACADR32SEL" description="MAC Addresses 32-63 Selected" start="23" size="1" access="ReadOnly" />
+      <BitField name="MACADR64SEL" description="MAC Addresses 64-127 Selected" start="24" size="1" access="ReadOnly" />
+      <BitField name="TSSTSSEL" description="Timestamp System Time Source" start="25" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Internal" start="0x1" />
+        <Enum name="B_0x2" description="External" start="0x2" />
+        <Enum name="B_0x3" description="Both" start="0x3" />
+      </BitField>
+      <BitField name="SAVLANINS" description="Source Address or VLAN Insertion Enable" start="27" size="1" access="ReadOnly" />
+      <BitField name="ACTPHYSEL" description="Active PHY Selected" start="28" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="GMII or MII" start="0x0" />
+        <Enum name="B_0x1" description="RGMII" start="0x1" />
+        <Enum name="B_0x2" description="SGMII" start="0x2" />
+        <Enum name="B_0x3" description="TBI" start="0x3" />
+        <Enum name="B_0x4" description="RMII" start="0x4" />
+        <Enum name="B_0x5" description="RTBI" start="0x5" />
+        <Enum name="B_0x6" description="SMII" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF1R" description="HW feature 1 register" start="+0x0120" size="4" reset_value="0x11141965" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFIFOSIZE" description="MTL Receive FIFO Size" start="0" size="5" access="ReadOnly">
+        <Enum name="B_0x0" description="128 bytes" start="0x0" />
+        <Enum name="B_0x1" description="256 bytes" start="0x1" />
+        <Enum name="B_0x2" description="512 bytes" start="0x2" />
+        <Enum name="B_0x3" description="1,024 bytes" start="0x3" />
+        <Enum name="B_0x4" description="2,048 bytes" start="0x4" />
+        <Enum name="B_0x5" description="4,096 bytes" start="0x5" />
+        <Enum name="B_0x6" description="8,192 bytes" start="0x6" />
+        <Enum name="B_0x7" description="16,384 bytes" start="0x7" />
+        <Enum name="B_0x8" description="32 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="64 Kbytes" start="0x9" />
+        <Enum name="B_0xA" description="128 Kbytes" start="0xA" />
+        <Enum name="B_0xB" description="256 Kbytes" start="0xB" />
+      </BitField>
+      <BitField name="SPRAM" description="Single Port RAM Enable" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOSIZE" description="MTL Transmit FIFO Size" start="6" size="5" access="ReadOnly">
+        <Enum name="B_0x0" description="128 bytes" start="0x0" />
+        <Enum name="B_0x1" description="256 bytes" start="0x1" />
+        <Enum name="B_0x2" description="512 bytes" start="0x2" />
+        <Enum name="B_0x3" description="1,024 bytes" start="0x3" />
+        <Enum name="B_0x4" description="2,048 bytes" start="0x4" />
+        <Enum name="B_0x5" description="4,096 bytes" start="0x5" />
+        <Enum name="B_0x6" description="8,192 bytes" start="0x6" />
+        <Enum name="B_0x7" description="16,384 bytes" start="0x7" />
+        <Enum name="B_0x8" description="32 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="64 Kbytes" start="0x9" />
+        <Enum name="B_0xA" description="128 Kbytes" start="0xA" />
+      </BitField>
+      <BitField name="OSTEN" description="One-Step Timestamping Enable" start="11" size="1" access="ReadOnly" />
+      <BitField name="PTOEN" description="PTP Offload Enable" start="12" size="1" access="ReadOnly" />
+      <BitField name="ADVTHWORD" description="IEEE 1588 High Word Register Enable" start="13" size="1" access="ReadOnly" />
+      <BitField name="ADDR64" description="Address width" start="14" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="32 bits" start="0x0" />
+      </BitField>
+      <BitField name="DCBEN" description="DCB Feature Enable" start="16" size="1" access="ReadOnly" />
+      <BitField name="SPHEN" description="Split Header Feature Enable" start="17" size="1" access="ReadOnly" />
+      <BitField name="TSOEN" description="TCP Segmentation Offload Enable" start="18" size="1" access="ReadOnly" />
+      <BitField name="DBGMEMA" description="DMA Debug Registers Enable" start="19" size="1" access="ReadOnly" />
+      <BitField name="AVSEL" description="AV Feature Enable" start="20" size="1" access="ReadOnly" />
+      <BitField name="RAVSEL" description="Rx Side Only AV Feature Enable" start="21" size="1" access="ReadOnly" />
+      <BitField name="POUOST" description="One Step for PTP over UDP/IP Feature Enable" start="23" size="1" access="ReadOnly" />
+      <BitField name="HASHTBLSZ" description="Hash Table Size" start="24" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hash table" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="128" start="0x2" />
+        <Enum name="B_0x3" description="256" start="0x3" />
+      </BitField>
+      <BitField name="L3L4FNUM" description="Total number of L3 or L4 Filters" start="27" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="No L3 or L4 Filter" start="0x0" />
+        <Enum name="B_0x1" description="1 L3 or L4 Filter" start="0x1" />
+        <Enum name="B_0x2" description="2 L3 or L4 Filters" start="0x2" />
+        <Enum name="B_0x8" description="8 L3 or L4" start="0x8" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF2R" description="HW feature 2 register" start="+0x0124" size="4" reset_value="0x41041041" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQCNT" description="Number of MTL Receive Queues" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 MTL Rx queue" start="0x0" />
+        <Enum name="B_0x1" description="2 MTL Rx queues" start="0x1" />
+        <Enum name="B_0x7" description="8 MTL Rx" start="0x7" />
+      </BitField>
+      <BitField name="TXQCNT" description="Number of MTL Transmit Queues" start="6" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 MTL Tx queue" start="0x0" />
+        <Enum name="B_0x1" description="2 MTL Tx queues" start="0x1" />
+        <Enum name="B_0x7" description="8 MTL Tx" start="0x7" />
+      </BitField>
+      <BitField name="RXCHCNT" description="Number of DMA Receive Channels" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 DMA Rx Channel" start="0x0" />
+        <Enum name="B_0x1" description="2 DMA Rx Channels" start="0x1" />
+        <Enum name="B_0x7" description="8 DMA Rx" start="0x7" />
+      </BitField>
+      <BitField name="RDCSZ" description="Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Cache not configured" start="0x0" />
+        <Enum name="B_0x1" description="Four 16-byte descriptors" start="0x1" />
+        <Enum name="B_0x2" description="Eight 16-byte descriptors" start="0x2" />
+        <Enum name="B_0x3" description="Sixteen 16-byte descriptors" start="0x3" />
+      </BitField>
+      <BitField name="TXCHCNT" description="Number of DMA Transmit Channels" start="18" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 DMA Tx Channel" start="0x0" />
+        <Enum name="B_0x1" description="2 DMA Tx Channels" start="0x1" />
+        <Enum name="B_0x7" description="8 DMA Tx" start="0x7" />
+      </BitField>
+      <BitField name="TDCSZ" description="Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Cache not configured" start="0x0" />
+        <Enum name="B_0x1" description="Four 16-byte descriptors" start="0x1" />
+        <Enum name="B_0x2" description="Eight 16-byte descriptors" start="0x2" />
+        <Enum name="B_0x3" description="Sixteen 16-byte descriptors" start="0x3" />
+      </BitField>
+      <BitField name="PPSOUTNUM" description="Number of PPS Outputs" start="24" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No PPS output" start="0x0" />
+        <Enum name="B_0x1" description="1 PPS output" start="0x1" />
+        <Enum name="B_0x2" description="2 PPS outputs" start="0x2" />
+        <Enum name="B_0x3" description="3 PPS outputs" start="0x3" />
+        <Enum name="B_0x4" description="4 PPS outputs" start="0x4" />
+      </BitField>
+      <BitField name="AUXSNAPNUM" description="Number of Auxiliary Snapshot Inputs" start="28" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No auxiliary input" start="0x0" />
+        <Enum name="B_0x1" description="1 auxiliary input" start="0x1" />
+        <Enum name="B_0x2" description="2 auxiliary inputs" start="0x2" />
+        <Enum name="B_0x3" description="3 auxiliary inputs" start="0x3" />
+        <Enum name="B_0x4" description="4 auxiliary inputs" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF3R" description="HW feature 3 register" start="+0x0128" size="4" reset_value="0x0C330031" reset_mask="0xFFFFFFFF">
+      <BitField name="NRVF" description="Number of Extended VLAN Tag Filters Enabled" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No Extended Rx VLAN Filters" start="0x0" />
+        <Enum name="B_0x1" description="4 Extended Rx VLAN Filters" start="0x1" />
+        <Enum name="B_0x2" description="8 Extended Rx VLAN Filters" start="0x2" />
+        <Enum name="B_0x3" description="16 Extended Rx VLAN Filters" start="0x3" />
+        <Enum name="B_0x4" description="24 Extended Rx VLAN Filters" start="0x4" />
+        <Enum name="B_0x5" description="32 Extended Rx VLAN Filters" start="0x5" />
+      </BitField>
+      <BitField name="CBTISEL" description="Queue/Channel based VLAN tag insertion on Tx enable" start="4" size="1" access="ReadOnly" />
+      <BitField name="DVLAN" description="Double VLAN processing enable" start="5" size="1" access="ReadOnly" />
+      <BitField name="PDUPSEL" description="Broadcast/Multicast Packet Duplication" start="9" size="1" access="ReadOnly" />
+      <BitField name="FRPSEL" description="Flexible Receive Parser Selected" start="10" size="1" access="ReadOnly" />
+      <BitField name="FRPBS" description="Flexible Receive Parser Buffer size" start="11" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+      </BitField>
+      <BitField name="FRPES" description="Flexible Receive Parser Table Entries size" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 entries" start="0x0" />
+        <Enum name="B_0x1" description="128 entries" start="0x1" />
+        <Enum name="B_0x2" description="256 entries" start="0x2" />
+      </BitField>
+      <BitField name="ESTSEL" description="Enhancements to Scheduled Traffic Enable" start="16" size="1" access="ReadOnly" />
+      <BitField name="ESTDEP" description="Depth of the Gate Control List" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No depth" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="128" start="0x2" />
+        <Enum name="B_0x3" description="256" start="0x3" />
+        <Enum name="B_0x4" description="512" start="0x4" />
+        <Enum name="B_0x5" description="1024" start="0x5" />
+      </BitField>
+      <BitField name="ESTWID" description="Width of the Time Interval field in the Gate Control List" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No width" start="0x0" />
+        <Enum name="B_0x1" description="16" start="0x1" />
+        <Enum name="B_0x2" description="20" start="0x2" />
+        <Enum name="B_0x3" description="24" start="0x3" />
+      </BitField>
+      <BitField name="FPESEL" description="Frame Preemption Enable" start="26" size="1" access="ReadOnly" />
+      <BitField name="TBSSEL" description="Time-based scheduling Enable" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASP" description="Automotive Safety Package" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="None" start="0x0" />
+        <Enum name="B_0x1" description="ECC only" start="0x1" />
+        <Enum name="B_0x2" description="AS_NPPE" start="0x2" />
+        <Enum name="B_0x3" description="AS_PPE" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACMDIOAR" description="MDIO address register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="GMII Busy" start="0" size="1" access="Read/Write" />
+      <BitField name="C45E" description="Clause 45 PHY Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="GOC" description="GMII Operation Command" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="Write" start="0x1" />
+        <Enum name="B_0x2" description="Post Read Increment Address for Clause 45 PHY" start="0x2" />
+        <Enum name="B_0x3" description="Read" start="0x3" />
+      </BitField>
+      <BitField name="SKAP" description="Skip Address Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="CR" description="CSR Clock Range" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="CSR clock = 60-100 MHz; MDC clock = CSR clock/42" start="0x0" />
+        <Enum name="B_0x1" description="CSR clock = 100-150 MHz; MDC clock = CSR clock/62" start="0x1" />
+        <Enum name="B_0x2" description="CSR clock = 20-35 MHz; MDC clock = CSR clock/16" start="0x2" />
+        <Enum name="B_0x3" description="CSR clock = 35-60 MHz; MDC clock = CSR clock/26" start="0x3" />
+        <Enum name="B_0x4" description="CSR clock = 150-250 MHz; MDC clock = CSR clock/102" start="0x4" />
+        <Enum name="B_0x5" description="CSR clock = 250-300 MHz; MDC clock = CSR clock/124" start="0x5" />
+        <Enum name="B_0x6" description="CSR clock = 300-500 MHz; MDC clock = CSR clock/204" start="0x6" />
+        <Enum name="B_0x7" description="CSR clock = 500-800 MHz; MDC clock = CSR clock/324" start="0x7" />
+        <Enum name="B_0x8" description="CSR clock/4" start="0x8" />
+        <Enum name="B_0x9" description="CSR clock/6" start="0x9" />
+        <Enum name="B_0xA" description="CSR clock/8" start="0xA" />
+        <Enum name="B_0xB" description="CSR clock/10" start="0xB" />
+        <Enum name="B_0xC" description="CSR clock/12" start="0xC" />
+        <Enum name="B_0xD" description="CSR clock/14" start="0xD" />
+        <Enum name="B_0xE" description="CSR clock/16" start="0xE" />
+        <Enum name="B_0xF" description="CSR clock/18" start="0xF" />
+      </BitField>
+      <BitField name="NTC" description="Number of Training Clocks" start="12" size="3" access="Read/Write" />
+      <BitField name="RDA" description="Register/Device Address" start="16" size="5" access="Read/Write" />
+      <BitField name="PA" description="Physical Layer Address" start="21" size="5" access="Read/Write" />
+      <BitField name="BTB" description="Back to Back transactions" start="26" size="1" access="Read/Write" />
+      <BitField name="PSE" description="Preamble Suppression Enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACMDIODR" description="MDIO data register" start="+0x0204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GD" description="GMII Data" start="0" size="16" access="Read/Write" />
+      <BitField name="RA" description="Register Address" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACARPAR" description="ARP address register" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARPPA" description="ARP Protocol Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACCSRSWCR" description="CSR software control register" start="+0x0230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RCWE" description="Register Clear on Write 1 Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SEEN" description="Slave Error Response Enable" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACFPECSR" description="FPE control and status register" start="+0x0234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFPE" description="Enable Tx Frame Preemption" start="0" size="1" access="Read/Write" />
+      <BitField name="SVER" description="Send Verify mPacket" start="1" size="1" access="Read/Write" />
+      <BitField name="SRSP" description="Send Respond mPacket" start="2" size="1" access="Read/Write" />
+      <BitField name="RVER" description="Received Verify Frame" start="16" size="1" access="Read/Write" />
+      <BitField name="RRSP" description="Received Respond Frame" start="17" size="1" access="Read/Write" />
+      <BitField name="TVER" description="Transmitted Verify Frame" start="18" size="1" access="Read/Write" />
+      <BitField name="TRSP" description="Transmitted Respond Frame" start="19" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPRSTIMR" description="MAC presentation time register" start="+0x0240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPTN" description="MAC 1722 Presentation Time in ns" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPRSTIMUR" description="MAC presentation time update register" start="+0x0244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPTU" description="MAC 1722 Presentation Time Update" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA0HR" description="MAC Address 0 high register" start="+0x0300" size="4" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address0[47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACA0LR" description="MAC Address 0 low register" start="+0x304" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA1HR" description="MAC Address 1 high register" start="+0x308" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA1LR" description="MAC Address 1 low register" start="+0x30C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA2HR" description="MAC Address 2 high register" start="+0x310" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA2LR" description="MAC Address 2 low register" start="+0x314" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA3HR" description="MAC Address 3 high register" start="+0x318" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA3LR" description="MAC Address 3 low register" start="+0x31C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_CONTROL" description="MMC control register" start="+0x0700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNTRST" description="Counters Reset" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTSTOPRO" description="Counter Stop Rollover" start="1" size="1" access="Read/Write" />
+      <BitField name="RSTONRD" description="Reset on Read" start="2" size="1" access="Read/Write" />
+      <BitField name="CNTFREEZ" description="MMC Counter Freeze" start="3" size="1" access="Read/Write" />
+      <BitField name="CNTPRST" description="Counters Preset" start="4" size="1" access="Read/Write" />
+      <BitField name="CNTPRSTLVL" description="Full-Half Preset" start="5" size="1" access="Read/Write" />
+      <BitField name="UCDBC" description="Update MMC Counters for Dropped Broadcast Packets " start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_RX_INTERRUPT" description="MMC Rx interrupt register" start="+0x0704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIS" description="MMC Receive CRC Error Packet Counter Interrupt Status" start="5" size="1" access="Read/Write" />
+      <BitField name="RXALGNERPIS" description="MMC Receive Alignment Error Packet Counter Interrupt Status" start="6" size="1" access="Read/Write" />
+      <BitField name="RXUCGPIS" description="MMC Receive Unicast Good Packet Counter Interrupt Status" start="17" size="1" access="Read/Write" />
+      <BitField name="RXLPIUSCIS" description="MMC Receive LPI microsecond counter interrupt status" start="26" size="1" access="Read/Write" />
+      <BitField name="RXLPITRCIS" description="MMC Receive LPI transition counter interrupt status" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_TX_INTERRUPT" description="MMC Tx interrupt register" start="+0x0708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIS" description="MMC Transmit Single Collision Good Packet Counter Interrupt Status" start="14" size="1" access="Read/Write" />
+      <BitField name="TXMCOLGPIS" description="MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" start="15" size="1" access="Read/Write" />
+      <BitField name="TXGPKTIS" description="MMC Transmit Good Packet Counter Interrupt Status" start="21" size="1" access="Read/Write" />
+      <BitField name="TXLPIUSCIS" description="MMC Transmit LPI microsecond counter interrupt status" start="26" size="1" access="Read/Write" />
+      <BitField name="TXLPITRCIS" description="MMC Transmit LPI transition counter interrupt status" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_RX_INTERRUPT_MASK" description="MMC Rx interrupt mask register" start="+0x070C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIM" description="MMC Receive CRC Error Packet Counter Interrupt Mask" start="5" size="1" access="Read/Write" />
+      <BitField name="RXALGNERPIM" description="MMC Receive Alignment Error Packet Counter Interrupt Mask" start="6" size="1" access="Read/Write" />
+      <BitField name="RXUCGPIM" description="MMC Receive Unicast Good Packet Counter Interrupt Mask" start="17" size="1" access="Read/Write" />
+      <BitField name="RXLPIUSCIM" description="MMC Receive LPI microsecond counter interrupt Mask" start="26" size="1" access="Read/Write" />
+      <BitField name="RXLPITRCIM" description="MMC Receive LPI transition counter interrupt Mask" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_TX_INTERRUPT_MASK" description="MMC Tx interrupt mask register" start="+0x0710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIM" description="MMC Transmit Single Collision Good Packet Counter Interrupt Mask" start="14" size="1" access="Read/Write" />
+      <BitField name="TXMCOLGPIM" description="MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" start="15" size="1" access="Read/Write" />
+      <BitField name="TXGPKTIM" description="MMC Transmit Good Packet Counter Interrupt Mask" start="21" size="1" access="Read/Write" />
+      <BitField name="TXLPIUSCIM" description="MMC Transmit LPI microsecond counter interrupt Mask" start="26" size="1" access="Read/Write" />
+      <BitField name="TXLPITRCIM" description="MMC Transmit LPI transition counter interrupt Mask" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_TX_SINGLE_COLLISION_GOOD_PACKETS" description="Tx single collision good packets register" start="+0x074C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSNGLCOLG" description="Tx Single Collision Good Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS" description="Tx multiple collision good packets register" start="+0x0750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMULTCOLG" description="Tx Multiple Collision Good Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_PACKET_COUNT_GOOD" description="Tx packet count good register" start="+0x0768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXPKTG" description="Tx Packet Count Good" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_CRC_ERROR_PACKETS" description="Rx CRC error packets register" start="+0x0794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERR" description="Rx CRC Error Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_ALIGNMENT_ERROR_PACKETS" description="Rx alignment error packets register" start="+0x0798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXALGNERR" description="Rx Alignment Error Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_UNICAST_PACKETS_GOOD" description="Rx unicast packets good register" start="+0x07C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXUCASTG" description="Rx Unicast Packets Good" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_LPI_USEC_CNTR" description="Tx LPI microsecond timer register" start="+0x07EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPIUSC" description="Tx LPI Microseconds Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_LPI_TRAN_CNTR" description="Tx LPI transition counter register" start="+0x07F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPITRC" description="Tx LPI Transition counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_LPI_USEC_CNTR" description="Rx LPI microsecond counter register" start="+0x07F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPIUSC" description="Rx LPI Microseconds Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_LPI_TRAN_CNTR" description="Rx LPI transition counter register" start="+0x07F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPITRC" description="Rx LPI Transition counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_ISR" description="MMC FPE Tx interrupt status register" start="+0x08A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCIS" description="MMC Tx FPE Fragment Counter Interrupt status" start="0" size="1" access="Read/Write" />
+      <BitField name="HRCIS" description="MMC Tx Hold Request Counter Interrupt Status" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_IMR" description="MMC FPE Tx interrupt mask register" start="+0x08A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCIM" description="MMC Transmit Fragment Counter Interrupt Mask" start="0" size="1" access="Read/Write" />
+      <BitField name="HRCIM" description="MMC Transmit Hold Request Counter Interrupt Mask" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_FCR" description="MMC FPE Tx fragment counter register" start="+0x08A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFFC" description="Tx FPE Fragment counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_TX_HRCR" description="MMC Tx hold request counter register" start="+0x08AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXHRC" description="Tx Hold Request Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_RX_ISR" description="MMC FPE Rx interrupt status register" start="+0x08C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAECIS" description="MMC Rx Packet Assembly Error Counter Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PSECIS" description="MMC Rx Packet SMD Error Counter Interrupt Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="PAOCIS" description="MMC Rx Packet Assembly OK Counter Interrupt Status" start="2" size="1" access="ReadOnly" />
+      <BitField name="FCIS" description="MMC Rx FPE Fragment Counter Interrupt Status" start="3" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_RX_IMR" description="MMC FPE Rx interrupt mask register" start="+0x08C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAECIM" description="MMC Rx Packet Assembly Error Counter Interrupt Mask" start="0" size="1" access="Read/Write" />
+      <BitField name="PSECIM" description="MMC Rx Packet SMD Error Counter Interrupt Mask" start="1" size="1" access="Read/Write" />
+      <BitField name="PAOCIM" description="MMC Rx Packet Assembly OK Counter Interrupt Mask" start="2" size="1" access="Read/Write" />
+      <BitField name="FCIM" description="MMC Rx FPE Fragment Counter Interrupt Mask" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_RX_PACKET_ASM_ERR" description="MMC Rx packet assembly error register" start="+0x08C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAEC" description="Rx Packet Assembly Error Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_PACKET_SMD_ERR" description="MMC Rx packet SMD error register" start="+0x08CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSEC" description="Rx Packet SMD Error Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_PACKET_ASM_OKR" description="MMC Rx packet assembly OK register" start="+0x08D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAOC" description="Rx Packet Assembly OK Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_FPE_FRAG_CR" description="MMC Rx FPE fragments counter register" start="+0x08D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FFC" description="Rx FPE Fragment Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACL3L4C0R" description="L3 and L4 control 0 register" start="+0x0900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN0" description="Layer 3 Protocol Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="L3SAM0" description="Layer 3 IP SA Match Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="L3SAIM0" description="Layer 3 IP SA Inverse Match Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="L3DAM0" description="Layer 3 IP DA Match Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="L3DAIM0" description="Layer 3 IP DA Inverse Match Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="L3HSBM0" description="Layer 3 IP SA higher bits match" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L3HDBM0" description="Layer 3 IP DA higher bits match" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L4PEN0" description="Layer 4 Protocol Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="L4SPM0" description="Layer 4 Source Port Match Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="L4SPIM0" description="Layer 4 Source Port Inverse Match Enable" start="19" size="1" access="Read/Write" />
+      <BitField name="L4DPM0" description="Layer 4 Destination Port Match Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="L4DPIM0" description="Layer 4 Destination Port Inverse Match Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="DMCHN0" description="DMA Channel Number" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA channel 1" start="0x1" />
+      </BitField>
+      <BitField name="DMCHEN0" description="DMA Channel Select Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL4A0R" description="Layer4 Address filter 0 register" start="+0x0904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP0" description="Layer 4 Source Port Number Field" start="0" size="16" access="Read/Write" />
+      <BitField name="L4DP0" description="Layer 4 Destination Port Number Field" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A00R" description="Layer3 Address 0 filter 0 register" start="+0x0910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A00" description="Layer 3 Address 0 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A10R" description="Layer3 Address 1 filter 0 register" start="+0x0914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A10" description="Layer 3 Address 1 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A20R" description="Layer3 Address 2 filter 0 register" start="+0x0918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A20" description="Layer 3 Address 2 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A30R" description="Layer3 Address 3 filter 0 register" start="+0x091C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A30" description="Layer 3 Address 3 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3L4C1R" description="L3 and L4 control 1 register" start="+0x0930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN1" description="Layer 3 Protocol Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="L3SAM1" description="Layer 3 IP SA Match Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="L3SAIM1" description="Layer 3 IP SA Inverse Match Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="L3DAM1" description="Layer 3 IP DA Match Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="L3DAIM1" description="Layer 3 IP DA Inverse Match Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="L3HSBM1" description="Layer 3 IP SA Higher Bits Match" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L3HDBM1" description="Layer 3 IP DA higher bits match" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L4PEN1" description="Layer 4 Protocol Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="L4SPM1" description="Layer 4 Source Port Match Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="L4SPIM1" description="Layer 4 Source Port Inverse Match Enable" start="19" size="1" access="Read/Write" />
+      <BitField name="L4DPM1" description="Layer 4 Destination Port Match Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="L4DPIM1" description="Layer 4 Destination Port Inverse Match Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="DMCHN1" description="DMA Channel Number" start="24" size="1" access="Read/Write" />
+      <BitField name="DMCHEN1" description="DMA Channel Select Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL4A1R" description="Layer 4 address filter 1 register" start="+0x0934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP1" description="Layer 4 Source Port Number Field" start="0" size="16" access="Read/Write" />
+      <BitField name="L4DP1" description="Layer 4 Destination Port Number Field" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A01R" description="Layer3 address 0 filter 1 Register" start="+0x0940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A01" description="Layer 3 Address 0 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A11R" description="Layer3 address 1 filter 1 register" start="+0x0944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A11" description="Layer 3 Address 1 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A21R" description="Layer3 address 2 filter 1 Register" start="+0x0948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A21" description="Layer 3 Address 2 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A31R" description="Layer3 address 3 filter 1 register" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A31" description="Layer 3 Address 3 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MAC_IACR" description="MAC Indirect Access Control register" start="+0x0A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OB" description="Operation Busy." start="0" size="1" access="Read/Write" />
+      <BitField name="COM" description="Command type" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates a read operation." start="0x1" />
+        <Enum name="B_0x0" description="Indicates a write operation." start="0x0" />
+      </BitField>
+      <BitField name="AUTO" description="Auto-increment" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="AOFF is incremented by 1. The software should ensure not to cause a wrap condition. Byte-wise read/write is not supported when auto-increment is enabled." start="0x1" />
+        <Enum name="B_0x0" description="AOFF is not automatically incremented. The software should program the correct address offset for each access." start="0x0" />
+      </BitField>
+      <BitField name="AOFF" description="Address Offset" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IndReg0 (Indirect register 0)" start="0x0" />
+        <Enum name="B_0x1" description="IndReg1 (Indirect register 1)" start="0x1" />
+        <Enum name="B_0x7" description="IndReg7 (Indirect register 7)" start="0x7" />
+      </BitField>
+      <BitField name="MSEL" description="Mode Select" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Typ_RXQ_ (Type-based RXQ mapping)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MAC_TMRQR" description="MAC type-based Rx Queue mapping register" start="+0x0A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TYP" description="Type field Value" start="0" size="16" access="Read/Write" />
+      <BitField name="TMRQ" description="Type Match Rx Queue Number" start="16" size="3" access="Read/Write" />
+      <BitField name="PFEX" description="Preemption or Express Packet" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Express packet" start="0x0" />
+        <Enum name="B_0x1" description="Preemption packet" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACTSCR" description="Timestamp control Register" start="+0x0B00" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSENA" description="Enable Timestamp" start="0" size="1" access="Read/Write" />
+      <BitField name="TSCFUPDT" description="Fine or Coarse Timestamp Update" start="1" size="1" access="Read/Write" />
+      <BitField name="TSINIT" description="Initialize Timestamp" start="2" size="1" access="Read/Write" />
+      <BitField name="TSUPDT" description="Update Timestamp" start="3" size="1" access="Read/Write" />
+      <BitField name="TSADDREG" description="Update Addend Register" start="5" size="1" access="Read/Write" />
+      <BitField name="PTGE" description="Presentation Time Generation Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="TSENALL" description="Enable Timestamp for All Packets" start="8" size="1" access="Read/Write" />
+      <BitField name="TSCTRLSSR" description="Timestamp Digital or Binary Rollover Control" start="9" size="1" access="Read/Write" />
+      <BitField name="TSVER2ENA" description="Enable PTP Packet Processing for Version 2 Format" start="10" size="1" access="Read/Write" />
+      <BitField name="TSIPENA" description="Enable Processing of PTP over Ethernet Packets" start="11" size="1" access="Read/Write" />
+      <BitField name="TSIPV6ENA" description="Enable Processing of PTP Packets Sent over IPv6-UDP" start="12" size="1" access="Read/Write" />
+      <BitField name="TSIPV4ENA" description="Enable Processing of PTP Packets Sent over IPv4-UDP" start="13" size="1" access="Read/Write" />
+      <BitField name="TSEVNTENA" description="Enable Timestamp Snapshot for Event Messages" start="14" size="1" access="Read/Write" />
+      <BitField name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master" start="15" size="1" access="Read/Write" />
+      <BitField name="SNAPTYPSEL" description="Select PTP packets for Taking Snapshots" start="16" size="2" access="Read/Write" />
+      <BitField name="TSENMACADDR" description="Enable MAC Address for PTP Packet Filtering" start="18" size="1" access="Read/Write" />
+      <BitField name="ESTI" description="External System Time Input" start="20" size="1" access="Read/Write" />
+      <BitField name="TXTSSTSM" description="Transmit Timestamp Status Mode" start="24" size="1" access="Read/Write" />
+      <BitField name="AV8021ASMEN" description="AV 802.1AS Mode Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSSIR" description="Subsecond increment register" start="+0x0B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SSINC" description="Subsecond Increment Value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSTSR" description="System time seconds register" start="+0x0B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp Second" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACSTNR" description="System time nanoseconds register" start="+0x0B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="Timestamp subseconds" start="0" size="31" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACSTSUR" description="System time seconds update register" start="+0x0B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp Seconds" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSTNUR" description="System time nanoseconds update register" start="+0x0B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="Timestamp subseconds" start="0" size="31" access="Read/Write" />
+      <BitField name="ADDSUB" description="Add or Subtract Time" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSAR" description="Timestamp addend register" start="+0x0B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSAR" description="Timestamp Addend Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSSR" description="Timestamp status register" start="+0x0B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSOVF" description="Timestamp Seconds Overflow" start="0" size="1" access="Read/Write" />
+      <BitField name="TSTARGT0" description="Timestamp Target Time Reached" start="1" size="1" access="Read/Write" />
+      <BitField name="AUXTSTRIG" description="Auxiliary Timestamp Trigger Snapshot" start="2" size="1" access="Read/Write" />
+      <BitField name="TSTRGTERR0" description="Timestamp Target Time Error" start="3" size="1" access="Read/Write" />
+      <BitField name="TSTARGT1" description="Timestamp Target Time Reached" start="4" size="1" access="Read/Write" />
+      <BitField name="TSTRGTERR1" description="Timestamp Target Time Error" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTSSIS" description="Tx Timestamp Status Interrupt Status" start="15" size="1" access="Read/Write" />
+      <BitField name="ATSSTN" description="Auxiliary Timestamp Snapshot Trigger Identifier" start="16" size="4" access="Read/Write" />
+      <BitField name="ATSSTM" description="Auxiliary Timestamp Snapshot Trigger Missed" start="24" size="1" access="Read/Write" />
+      <BitField name="ATSNS" description="Number of Auxiliary Timestamp Snapshots" start="25" size="5" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTXTSSNR" description="Tx timestamp status nanoseconds register" start="+0x0B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSLO" description="Transmit Timestamp Status Low" start="0" size="31" access="Read/Write" />
+      <BitField name="TXTSSMIS" description="Transmit Timestamp Status Missed" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTXTSSSR" description="Tx timestamp status seconds register" start="+0x0B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSHI" description="Transmit Timestamp Status High" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACACR" description="Auxiliary control register" start="+0x0B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATSFC" description="Auxiliary Snapshot FIFO Clear" start="0" size="1" access="Read/Write" />
+      <BitField name="ATSEN0" description="Auxiliary Snapshot 0 Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="ATSEN1" description="Auxiliary Snapshot 1 Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="ATSEN2" description="Auxiliary Snapshot 2 Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="ATSEN3" description="Auxiliary Snapshot 3 Enable" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACATSNR" description="Auxiliary timestamp nanoseconds register" start="+0x0B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSLO" description="Auxiliary Timestamp" start="0" size="31" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACATSSR" description="Auxiliary timestamp seconds register" start="+0x0B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSHI" description="Auxiliary Timestamp" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTSIACR" description="Timestamp Ingress asymmetric correction register" start="+0x0B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTIAC" description="One-Step Timestamp Ingress Asymmetry Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSEACR" description="Timestamp Egress asymmetric correction register" start="+0x0B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTEAC" description="One-Step Timestamp Egress Asymmetry Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSICNR" description="Timestamp Ingress correction nanosecond register" start="+0x0B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIC" description="Timestamp Ingress Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSECNR" description="Timestamp Egress correction nanosecond register" start="+0x0B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEC" description="Timestamp Egress Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSILR" description="Timestamp Ingress Latency register" start="+0x0B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ITLSNS" description="Ingress Timestamp Latency, in subnanoseconds" start="8" size="8" access="ReadOnly" />
+      <BitField name="ITLNS" description="Ingress Timestamp Latency, in nanoseconds" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTSELR" description="Timestamp Egress Latency register" start="+0x0B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETLSNS" description="Egress Timestamp Latency, in subnanoseconds" start="8" size="8" access="ReadOnly" />
+      <BitField name="ETLNS" description="Egress Timestamp Latency, in nanoseconds" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACPPSCR" description="PPS control register" start="+0x0B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSCTRL" description="PPS Output Frequency Control" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="The binary rollover is 2 Hz, and the digital rollover is 1 Hz." start="0x1" />
+        <Enum name="B_0x2" description="The binary rollover is 4 Hz, and the digital rollover is 2 Hz." start="0x2" />
+        <Enum name="B_0x3" description="The binary rollover is 8 Hz, and the digital rollover is 4 Hz." start="0x3" />
+        <Enum name="B_0x4" description="The binary rollover is 16 Hz, and the digital rollover is 8 Hz." start="0x4" />
+        <Enum name="B_0xF" description="The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz." start="0xF" />
+      </BitField>
+      <BitField name="PPSEN0" description="Flexible PPS Output Mode Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="TRGTMODSEL0" description="Target Time Register Mode for PPS Output" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target Time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN0" description="MCGR Mode Enable for PPS0 Output" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="TIMESEL" description="Time Select" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSCR_alternate" description="PPS control register" start="+0x0B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSCMD" description="Flexible PPS Output 0 (eth_ptp_pps_out) Control" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No Command" start="0x0" />
+        <Enum name="B_0x1" description="START Single Pulse." start="0x1" />
+        <Enum name="B_0x2" description="START Pulse Train." start="0x2" />
+        <Enum name="B_0x3" description="Cancel START." start="0x3" />
+        <Enum name="B_0x4" description="STOP Pulse Train at time." start="0x4" />
+        <Enum name="B_0x5" description="STOP Pulse Train immediately." start="0x5" />
+        <Enum name="B_0x6" description="Cancel STOP Pulse train." start="0x6" />
+      </BitField>
+      <BitField name="PPSEN0" description="Flexible PPS Output 0 Mode Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="TRGTMODSEL0" description="Target Time Register Mode for PPS Output 0" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target Time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output 0 signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target Time registers are programmed only for starting or stopping the PPS output 0 signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN0" description="MCGR Mode Enable for PPS Output 0" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="PPSCMD1" description="Flexible PPS Output 1 Control" start="8" size="4" access="Read/Write" />
+      <BitField name="TRGTMODSEL1" description="Target Time Register Mode for PPS Output 1" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enabled MCGR Interrupt whose status bit is indicated by TSTARGT1 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN1" description="MCGR Mode Enable for PPS Output 1" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="TIMESEL" description="Time Select" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTS0R" description="PPS 0 target time seconds register" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSTRH0" description="PPS Target Time Seconds Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTN0R" description="PPS 0 target time nanoseconds register" start="+0xB84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TTSL0" description="Target Time Low for PPS Register" start="0" size="31" access="Read/Write" />
+      <BitField name="TRGTBUSY0" description="PPS Target Time Register Busy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSI0R" description="PPS 0 interval register" start="+0xB88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSINT0" description="PPS Output Signal Interval" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSW0R" description="PPS 0 width register" start="+0xB8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSWIDTH0" description="PPS Output Signal Width" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTS1R" description="PPS 1 target time seconds register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSTRH0" description="PPS Target Time Seconds Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTN1R" description="PPS 1 target time nanoseconds register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TTSL0" description="Target Time Low for PPS Register" start="0" size="31" access="Read/Write" />
+      <BitField name="TRGTBUSY0" description="PPS Target Time Register Busy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSI1R" description="PPS 1 interval register" start="+0xB98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSINT0" description="PPS Output Signal Interval" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSW1R" description="PPS 1 width register" start="+0xB9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSWIDTH0" description="PPS Output Signal Width" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPOCR" description="PTP Offload control register" start="+0x0BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PTOEN" description="PTP Offload Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ASYNCEN" description="Automatic PTP SYNC message Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="APDREQEN" description="Automatic PTP Pdelay_Req message Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="ASYNCTRIG" description="Automatic PTP SYNC message Trigger" start="4" size="1" access="Read/Write" />
+      <BitField name="APDREQTRIG" description="Automatic PTP Pdelay_Req message Trigger" start="5" size="1" access="Read/Write" />
+      <BitField name="DRRDIS" description="Disable PTO Delay Request/Response response generation" start="6" size="1" access="Read/Write" />
+      <BitField name="PDRDIS" description="Disable Peer Delay Response response generation" start="7" size="1" access="Read/Write" />
+      <BitField name="DN" description="Domain Number" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI0R" description="PTP Source Port Identity 0 Register" start="+0x0BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI0" description="Source Port Identity 0" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI1R" description="PTP Source port identity 1 register" start="+0x0BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI1" description="Source Port Identity 1" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI2R" description="PTP Source port identity 2 register" start="+0x0BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI2" description="Source Port Identity 2" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLMIR" description="Log message interval register" start="+0x0BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSI" description="Log Sync Interval" start="0" size="8" access="Read/Write" />
+      <BitField name="DRSYNCR" description="Delay_Req to SYNC Ratio " start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="DelayReq generated for every received SYNC" start="0x0" />
+        <Enum name="B_0x1" description="DelayReq generated every alternate reception of SYNC" start="0x1" />
+      </BitField>
+      <BitField name="LMPDRI" description="Log Min Pdelay_Req Interval" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLOMR" description="Operating mode Register" start="+0x0C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTXSTS" description="Drop Transmit Status" start="1" size="1" access="Read/Write" />
+      <BitField name="RAA" description="Receive Arbitration Algorithm" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest priority." start="0x0" />
+        <Enum name="B_0x1" description="Weighted Strict priority (WSP)" start="0x1" />
+      </BitField>
+      <BitField name="SCHALG" description="Tx Scheduling Algorithm" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Weighted round robin (WRR) algorithm" start="0x0" />
+        <Enum name="B_0x3" description="Strict priority (SP) algorithm." start="0x3" />
+      </BitField>
+      <BitField name="CNTPRST" description="Counters Preset" start="8" size="1" access="Read/Write" />
+      <BitField name="CNTCLR" description="Counters Reset" start="9" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLISR" description="Interrupt status Register" start="+0x0C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Q0IS" description="Queue 0 interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="Q1IS" description="Queue 1 interrupt status" start="1" size="1" access="ReadOnly" />
+      <BitField name="ESTIS" description="EST (TAS- 802.1Qbv) Interrupt Status" start="18" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQDMAMR" description="Rx Queue and DMA Channel Mapping Register" start="+0x0C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Q0MDMACH" description="Queue 0 Mapped to DMA Channel" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Channel 1" start="0x1" />
+      </BitField>
+      <BitField name="Q0DDMACH" description="Queue 0 Enabled for DA-based DMA Channel Selection" start="4" size="1" access="Read/Write" />
+      <BitField name="Q1MDMACH" description="Queue 1 Mapped to DMA Channel" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Channel 1" start="0x1" />
+      </BitField>
+      <BitField name="Q1DDMACH" description="Queue 1 Enabled for DA-based DMA Channel Selection" start="12" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTBSCR" description="TBS control register" start="+0x0C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESTM" description="EST offset mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EST offset mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="EST offset mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="LEOV" description="Launch expiry offset valid" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LEOS field invalid" start="0x0" />
+        <Enum name="B_0x1" description="LEOS field valid" start="0x1" />
+      </BitField>
+      <BitField name="LEGOS" description="Launch Expiry GSN Offset" start="4" size="3" access="Read/Write" />
+      <BitField name="LEOS" description="Launch Expiry Offset" start="8" size="24" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTCR" description="EST Control Register" start="+0x0C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EEST" description="Enable EST" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EST disabled" start="0x0" />
+        <Enum name="B_0x1" description="EST enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSWL" description="Switch to S/W owned list" start="1" size="1" access="Read/Write" />
+      <BitField name="DDBF" description="Do not Drop frames during Frame Size Error" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Drop" start="0x0" />
+        <Enum name="B_0x1" description="Don't drop" start="0x1" />
+      </BitField>
+      <BitField name="DFBS" description="Drop Frames causing Scheduling Error" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Don't drop" start="0x0" />
+        <Enum name="B_0x1" description="Drop" start="0x1" />
+      </BitField>
+      <BitField name="LCSE" description="Loop Count to report Scheduling Error" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="4 iterations" start="0x0" />
+        <Enum name="B_0x1" description="8 iterations" start="0x1" />
+        <Enum name="B_0x2" description="16 iterations" start="0x2" />
+        <Enum name="B_0x3" description="32 iterations" start="0x3" />
+      </BitField>
+      <BitField name="TILS" description="Time Interval Left Shift Amount" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift needed (equal to x1ns)" start="0x0" />
+        <Enum name="B_0x1" description="Left shift TI by 1 bit (equal to x2ns)" start="0x1" />
+        <Enum name="B_0x2" description="Left shift TI by 2 bits (equal to x4ns)" start="0x2" />
+        <Enum name="B_0x4" description="Left shift TI by 7 bits (equal to x128ns)" start="0x4" />
+      </BitField>
+      <BitField name="CTOV" description="Current Time Offset Value" start="12" size="12" access="Read/Write" />
+      <BitField name="PTOV" description="PTP Time Offset Value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTECR" description="EST Extended Control Register" start="+0x0C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVHD" description="Overhead Bytes Value" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTSR" description="EST Status Register" start="+0x0C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLC" description="Switch to S/W owned list Complete" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="BTRE" description="BTR Error" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="HLBF" description="Head-Of-Line Blocking due to Frame Size" start="2" size="1" access="ReadOnly" />
+      <BitField name="HLBS" description="Head-Of-Line Blocking due to Scheduling" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="CGCE" description="Constant Gate Control Error" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SWOL" description="S/W owned list" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="BTRL" description="BTR Error Loop Count" start="8" size="8" access="ReadOnly" />
+      <BitField name="CGSN" description="Current GCL slot number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLESTSCHER" description="EST Schedule Error Register" start="+0x0C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEQN" description="Schedule Error Queue Number" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTFSER" description="EST Frame size Error Register" start="+0x0C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEQN" description="Frame Size Error Queue Number" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTFSCR" description="EST Frame size Capture Register" start="+0x0C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HBFS" description="Frame Size of HLBF" start="0" size="15" access="ReadOnly" />
+      <BitField name="HBFQ" description="Queue Number of HLBF" start="16" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLESTIER" description="EST Interrupt Enable Register" start="+0x0C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IECC" description="Interrupt Enable for Switch List" start="0" size="1" access="Read/Write" />
+      <BitField name="IEBE" description="Interrupt Enable for BTR Error" start="1" size="1" access="Read/Write" />
+      <BitField name="IEHF" description="Interrupt Enable for HLBF" start="2" size="1" access="Read/Write" />
+      <BitField name="IEHS" description="Interrupt Enable for HLBS" start="3" size="1" access="Read/Write" />
+      <BitField name="CGCE" description="Interrupt Enable for CGCE" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTGCLCR" description="EST Gate Control List Register" start="+0x0C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRWO" description="Start Read/Write Operation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates the start/progress of a Read/Write operation" start="0x1" />
+      </BitField>
+      <BitField name="R1W0" description="Read 1, Write 0" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Read operation" start="0x1" />
+        <Enum name="B_0x0" description="Write operation." start="0x0" />
+      </BitField>
+      <BitField name="GCRR" description="Gate Control Related Registers" start="2" size="1" access="Read/Write" />
+      <BitField name="DBGM" description="Debug Mode" start="4" size="1" access="Read/Write" />
+      <BitField name="DBGB" description="Debug Mode Bank Select" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bank 0" start="0x0" />
+        <Enum name="B_0x1" description="Bank 1" start="0x1" />
+      </BitField>
+      <BitField name="ADDR" description="Gate Control List Address: " start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0_GCRR__EQUAL_1" description="BTR Low (31:0)" start="0x0" />
+        <Enum name="B_0x1_GCRR__EQUAL_1" description="BTR High (63:31)" start="0x1" />
+        <Enum name="B_0x2_GCRR__EQUAL_1" description="CTR Low (31:0)" start="0x2" />
+        <Enum name="B_0x3_GCRR__EQUAL_1" description="CTR High (39:32)" start="0x3" />
+        <Enum name="B_0x4_GCRR__EQUAL_1" description="TER (30:0)" start="0x4" />
+        <Enum name="B_0x5_GCRR__EQUAL_1" description="LLR (6:0)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLESTGCLDR" description="EST Gate Control List Data Register" start="+0x0C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCD" description="Gate Control Data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLFPECSR" description="FPE Frame Preemption Control Status Register" start="+0x0C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSZ" description="Additional Fragment Size" start="0" size="2" access="Read/Write" />
+      <BitField name="PEC" description="Preemption Classification" start="8" size="2" access="Read/Write" />
+      <BitField name="HRS" description="Hold/Release Status" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State." start="0x1" />
+        <Enum name="B_0x0" description="Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLFPEAR" description="FPE Frame Preemption Advance Register" start="+0x0C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HADV" description="Hold Advance" start="0" size="16" access="Read/Write" />
+      <BitField name="RADV" description="Release Advance" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0OMR" description="T0 queue 0 operating mode Register" start="+0xD00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTQ" description="Flush Transmit Queue" start="0" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Transmit Store and Forward" start="1" size="1" access="Read/Write" />
+      <BitField name="TXQEN" description="Transmit Queue Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Enable in AV mode" start="0x1" />
+        <Enum name="B_0x2" description="Enabled" start="0x2" />
+      </BitField>
+      <BitField name="TTC" description="Transmit Threshold Control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="32" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+        <Enum name="B_0x4" description="192" start="0x4" />
+        <Enum name="B_0x5" description="256" start="0x5" />
+        <Enum name="B_0x6" description="384" start="0x6" />
+        <Enum name="B_0x7" description="512" start="0x7" />
+      </BitField>
+      <BitField name="TQS" description="Transmit queue size" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0UR" description="T0 queue 0 underflow register" start="+0xD04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFRMCNT" description="Underflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="UFCNTOVF" description="Overflow Bit for Underflow Packet Counter" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0DR" description="T0 queue 0 debug register" start="+0xD08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXQPAUSED" description="Transmit Queue in Pause" start="0" size="1" access="ReadOnly" />
+      <BitField name="TRCSTS" description="MTL Tx Queue Read Controller Status" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Read state (transferring data to the MAC transmitter)" start="0x1" />
+        <Enum name="B_0x2" description="Waiting for pending Tx Status from the MAC transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the Tx queue because of the Packet Abort request from the MAC" start="0x3" />
+      </BitField>
+      <BitField name="TWCSTS" description="MTL Tx Queue Write Controller Status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXQSTS" description="MTL Tx Queue Not Empty Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="TXSTSFSTS" description="MTL Tx Status FIFO Full Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="PTXQ" description="Number of Packets in the Transmit Queue" start="16" size="3" access="ReadOnly" />
+      <BitField name="STXSTSF" description="Number of Status Words in Tx Status FIFO of Queue" start="20" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ0ESR" description="T0 queue 0 ETS status Register" start="+0xD14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABS" description="Average Bits per Slot" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ0QWR" description="Tx queue 0 quantum weight register" start="+0x0D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISCQW" description="Weights" start="0" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLQ0ICSR" description="Queue 0 interrupt control status Register" start="+0xD2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXUNFIS" description="Transmit Queue Underflow Interrupt Status" start="0" size="1" access="Read/Write" />
+      <BitField name="ABPSIS" description="Average Bits Per Slot Interrupt Status" start="1" size="1" access="Read/Write" />
+      <BitField name="TXUIE" description="Transmit Queue Underflow Interrupt Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="ABPSIE" description="Average Bits Per Slot Interrupt Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="RXOVFIS" description="Receive Queue Overflow Interrupt Status" start="16" size="1" access="Read/Write" />
+      <BitField name="RXOIE" description="Receive Queue Overflow Interrupt Enable" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0OMR" description="R0 queue 0 operating mode register" start="+0xD30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC" description="Receive Queue Threshold Control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64" start="0x0" />
+        <Enum name="B_0x1" description="32" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+      </BitField>
+      <BitField name="FUP" description="Forward Undersized Good Packets" start="3" size="1" access="Read/Write" />
+      <BitField name="FEP" description="Forward Error Packets" start="4" size="1" access="Read/Write" />
+      <BitField name="RSF" description="Receive Queue Store and Forward" start="5" size="1" access="Read/Write" />
+      <BitField name="DIS_TCP_EF" description="Disable Dropping of TCP/IP Checksum Error Packets" start="6" size="1" access="Read/Write" />
+      <BitField name="EHFC" description="Enable Hardware Flow Control" start="7" size="1" access="Read/Write" />
+      <BitField name="RFA" description="Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" start="8" size="3" access="Read/Write" />
+      <BitField name="RFD" description="Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Full minus 1 Kbyte" start="0x0" />
+        <Enum name="B_0x1" description="Full minus 1.5 Kbyte" start="0x1" />
+      </BitField>
+      <BitField name="RQS" description="Receive Queue Size" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0MPOCR" description="R0 queue 0 missed packet and overflow counter register" start="+0xD34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVFPKTCNT" description="Overflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="OVFCNTOVF" description="Overflow Counter Overflow Bit" start="11" size="1" access="Read/Write" />
+      <BitField name="MISPKTCNT" description="Missed Packet Counter" start="16" size="11" access="Read/Write" />
+      <BitField name="MISCNTOVF" description="Missed Packet Counter Overflow Bit" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0DR" description="R0 queue 0 debug register" start="+0xD38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWCSTS" description="MTL Rx Queue Write Controller Active Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RRCSTS" description="MTL Rx Queue Read Controller State" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Reading packet data" start="0x1" />
+        <Enum name="B_0x2" description="Reading packet status (or timestamp)" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the packet data and status" start="0x3" />
+      </BitField>
+      <BitField name="RXQSTS" description="MTL Rx Queue Fill-Level Status" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx queue empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue fill-level below flow-control deactivate threshold" start="0x1" />
+        <Enum name="B_0x2" description="Rx queue fill-level above flow-control activate threshold" start="0x2" />
+        <Enum name="B_0x3" description="Rx queue full" start="0x3" />
+      </BitField>
+      <BitField name="PRXQ" description="Number of Packets in Receive Queue" start="16" size="14" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQ0CR" description="R0 queue 0 control register" start="+0xD3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ_WEGT" description="Receive Queue Weight" start="0" size="3" access="Read/Write" />
+      <BitField name="RXQ_FRM_ARBIT" description="Receive Queue Packet Arbitration" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1OMR" description="T1 queue 1 operating mode Register" start="+0xD40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTQ" description="Flush Transmit Queue" start="0" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Transmit Store and Forward" start="1" size="1" access="Read/Write" />
+      <BitField name="TXQEN" description="Transmit Queue Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Enable in AV mode" start="0x1" />
+        <Enum name="B_0x2" description="Enabled" start="0x2" />
+      </BitField>
+      <BitField name="TTC" description="Transmit Threshold Control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="32" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+        <Enum name="B_0x4" description="192" start="0x4" />
+        <Enum name="B_0x5" description="256" start="0x5" />
+        <Enum name="B_0x6" description="384" start="0x6" />
+        <Enum name="B_0x7" description="512" start="0x7" />
+      </BitField>
+      <BitField name="TQS" description="Transmit queue size" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1UR" description="T1 queue 1 underflow register" start="+0xD44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFRMCNT" description="Underflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="UFCNTOVF" description="Overflow Bit for Underflow Packet Counter" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1DR" description="T1 queue 1 debug register" start="+0xD48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXQPAUSED" description="Transmit Queue in Pause" start="0" size="1" access="ReadOnly" />
+      <BitField name="TRCSTS" description="MTL Tx Queue Read Controller Status" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Read state (transferring data to the MAC transmitter)" start="0x1" />
+        <Enum name="B_0x2" description="Waiting for pending Tx Status from the MAC transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the Tx queue because of the Packet Abort request from the MAC" start="0x3" />
+      </BitField>
+      <BitField name="TWCSTS" description="MTL Tx Queue Write Controller Status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXQSTS" description="MTL Tx Queue Not Empty Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="TXSTSFSTS" description="MTL Tx Status FIFO Full Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="PTXQ" description="Number of Packets in the Transmit Queue" start="16" size="3" access="ReadOnly" />
+      <BitField name="STXSTSF" description="Number of Status Words in Tx Status FIFO of Queue" start="20" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ1ECR" description="Tx queue 1 ETS control Register" start="+0x0D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVALG" description="AV Algorithm" start="2" size="1" access="Read/Write" />
+      <BitField name="CC" description="Credit Control" start="3" size="1" access="Read/Write" />
+      <BitField name="SLC" description="Slot Count" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 Slot" start="0x0" />
+        <Enum name="B_0x1" description="2 Slots" start="0x1" />
+        <Enum name="B_0x2" description="4 Slots" start="0x2" />
+        <Enum name="B_0x3" description="8 Slots" start="0x3" />
+        <Enum name="B_0x4" description="16 Slots" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLTXQ1ESR" description="T1 queue 1 ETS status Register" start="+0xD54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABS" description="Average Bits per Slot" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ1QWR" description="Tx queue 1 quantum weight register" start="+0x0D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISCQW" description="IdleSlopeCredit or Weights" start="0" size="14" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1SSCR" description="Tx queue 1 send slope credit Register" start="+0x0D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SSC" description="sendSlopeCredit Value" start="0" size="14" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1HCR" description="Tx Queue 1 hiCredit register" start="+0x0D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HC" description="hiCredit Value" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1LCR" description="Tx queue 1 loCredit register" start="+0x0D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LC" description="loCredit Value" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLQ1ICSR" description="Queue 1 interrupt control status Register" start="+0xD6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXUNFIS" description="Transmit Queue Underflow Interrupt Status" start="0" size="1" access="Read/Write" />
+      <BitField name="ABPSIS" description="Average Bits Per Slot Interrupt Status" start="1" size="1" access="Read/Write" />
+      <BitField name="TXUIE" description="Transmit Queue Underflow Interrupt Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="ABPSIE" description="Average Bits Per Slot Interrupt Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="RXOVFIS" description="Receive Queue Overflow Interrupt Status" start="16" size="1" access="Read/Write" />
+      <BitField name="RXOIE" description="Receive Queue Overflow Interrupt Enable" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1OMR" description="R1 queue 1 operating mode register" start="+0xD70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC" description="Receive Queue Threshold Control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64" start="0x0" />
+        <Enum name="B_0x1" description="32" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+      </BitField>
+      <BitField name="FUP" description="Forward Undersized Good Packets" start="3" size="1" access="Read/Write" />
+      <BitField name="FEP" description="Forward Error Packets" start="4" size="1" access="Read/Write" />
+      <BitField name="RSF" description="Receive Queue Store and Forward" start="5" size="1" access="Read/Write" />
+      <BitField name="DIS_TCP_EF" description="Disable Dropping of TCP/IP Checksum Error Packets" start="6" size="1" access="Read/Write" />
+      <BitField name="EHFC" description="Enable Hardware Flow Control" start="7" size="1" access="Read/Write" />
+      <BitField name="RFA" description="Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" start="8" size="3" access="Read/Write" />
+      <BitField name="RFD" description="Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Full minus 1 Kbyte" start="0x0" />
+        <Enum name="B_0x1" description="Full minus 1.5 Kbyte" start="0x1" />
+      </BitField>
+      <BitField name="RQS" description="Receive Queue Size" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1MPOCR" description="R1 queue 1 missed packet and overflow counter register" start="+0xD74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVFPKTCNT" description="Overflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="OVFCNTOVF" description="Overflow Counter Overflow Bit" start="11" size="1" access="Read/Write" />
+      <BitField name="MISPKTCNT" description="Missed Packet Counter" start="16" size="11" access="Read/Write" />
+      <BitField name="MISCNTOVF" description="Missed Packet Counter Overflow Bit" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1DR" description="R1 queue 1 debug register" start="+0xD78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWCSTS" description="MTL Rx Queue Write Controller Active Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RRCSTS" description="MTL Rx Queue Read Controller State" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Reading packet data" start="0x1" />
+        <Enum name="B_0x2" description="Reading packet status (or timestamp)" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the packet data and status" start="0x3" />
+      </BitField>
+      <BitField name="RXQSTS" description="MTL Rx Queue Fill-Level Status" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx queue empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue fill-level below flow-control deactivate threshold" start="0x1" />
+        <Enum name="B_0x2" description="Rx queue fill-level above flow-control activate threshold" start="0x2" />
+        <Enum name="B_0x3" description="Rx queue full" start="0x3" />
+      </BitField>
+      <BitField name="PRXQ" description="Number of Packets in Receive Queue" start="16" size="14" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQ1CR" description="R1 queue 1 control register" start="+0xD7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ_WEGT" description="Receive Queue Weight" start="0" size="3" access="Read/Write" />
+      <BitField name="RXQ_FRM_ARBIT" description="Receive Queue Packet Arbitration" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAMR" description="DMA mode register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWR" description="Software Reset" start="0" size="1" access="Read/Write" />
+      <BitField name="TAA" description="Transmit Arbitration Algorithm " start="2" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Fixed priority. In fixed priority, Channel 0 has the lowest priority and the last channel has the highest priority." start="0x0" />
+        <Enum name="B_0x1" description="Weighted Strict priority (WSP)" start="0x1" />
+        <Enum name="B_0x2" description="Weighted Round-Robin (WRR)" start="0x2" />
+      </BitField>
+      <BitField name="DSPW" description="Descriptor Posted Write" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The descriptor writes are always non-posted." start="0x0" />
+        <Enum name="B_0x1" description="The descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor. Otherwise, the descriptor writes are always posted." start="0x1" />
+      </BitField>
+      <BitField name="TXPR" description="Transmit priority" start="11" size="1" access="Read/Write" />
+      <BitField name="INTM" description="Interrupt Mode" start="16" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMASBMR" description="System bus mode register" start="+0x1004" size="4" reset_value="0x01010000" reset_mask="0xFFFFFFFF">
+      <BitField name="FB" description="Fixed Burst Length" start="0" size="1" access="Read/Write" />
+      <BitField name="BLEN4" description="AXI Burst Length 4" start="1" size="1" access="Read/Write" />
+      <BitField name="BLEN8" description="AXI Burst Length 8" start="2" size="1" access="Read/Write" />
+      <BitField name="BLEN16" description="AXI Burst Length 16" start="3" size="1" access="Read/Write" />
+      <BitField name="BLEN32" description="AXI Burst Length 32" start="4" size="1" access="Read/Write" />
+      <BitField name="BLEN64" description="AXI Burst Length 64" start="5" size="1" access="Read/Write" />
+      <BitField name="BLEN128" description="AXI Burst Length 128" start="6" size="1" access="Read/Write" />
+      <BitField name="BLEN256" description="AXI Burst Length 256" start="7" size="1" access="Read/Write" />
+      <BitField name="AALE" description="Automatic AXI LPI enable" start="10" size="1" access="Read/Write" />
+      <BitField name="AAL" description="Address-Aligned Beats" start="12" size="1" access="Read/Write" />
+      <BitField name="ONEKBBE" description="1 Kbyte Boundary Crossing Enable for the AXI Master" start="13" size="1" access="Read/Write" />
+      <BitField name="RD_OSR_LMT" description="AXI Maximum Read Outstanding Request Limit" start="16" size="2" access="Read/Write" />
+      <BitField name="WR_OSR_LMT" description="AXI Maximum Write Outstanding Request Limit" start="24" size="2" access="Read/Write" />
+      <BitField name="LPI_XIT_PKT" description="Unlock on Magic Packet or Remote wake-up packet" start="30" size="1" access="Read/Write" />
+      <BitField name="EN_LPI" description="Enable Low Power Interface (LPI)" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAISR" description="Interrupt status register" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DC0IS" description="DMA Channel 0 Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="DC1IS" description="DMA Channel 1 Interrupt Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="MTLIS" description="MTL Interrupt Status" start="16" size="1" access="ReadOnly" />
+      <BitField name="MACIS" description="MAC Interrupt Status" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMADSR" description="Debug status register" start="+0x100C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXWHSTS" description="AXI Master Write Channel" start="0" size="1" access="ReadOnly" />
+      <BitField name="AXRHSTS" description="AXI Master Read Channel Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="RPS0" description="DMA Channel 0 Receive Process State" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Stopped (Reset or Stop Receive Command issued)" start="0x0" />
+        <Enum name="B_0x1" description="Running (Fetching Rx Transfer Descriptor)" start="0x1" />
+        <Enum name="B_0x3" description="Running (Waiting for Rx packet)" start="0x3" />
+        <Enum name="B_0x4" description="Suspended (Rx Descriptor Unavailable)" start="0x4" />
+        <Enum name="B_0x5" description="Running (Closing the Rx Descriptor)" start="0x5" />
+        <Enum name="B_0x6" description="Timestamp write state" start="0x6" />
+        <Enum name="B_0x7" description="Running (Transferring the received packet data from the Rx buffer to the system memory)" start="0x7" />
+      </BitField>
+      <BitField name="TPS0" description="DMA Channel 0 Transmit Process State" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Stopped (Reset or Stop Transmit Command issued)" start="0x0" />
+        <Enum name="B_0x1" description="Running (Fetching Tx Transfer Descriptor)" start="0x1" />
+        <Enum name="B_0x2" description="Running (Waiting for status)" start="0x2" />
+        <Enum name="B_0x3" description="Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))" start="0x3" />
+        <Enum name="B_0x4" description="Timestamp write state" start="0x4" />
+        <Enum name="B_0x6" description="Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)" start="0x6" />
+        <Enum name="B_0x7" description="Running (Closing Tx Descriptor)" start="0x7" />
+      </BitField>
+      <BitField name="RPS1" description="DMA Channel 1 Receive Process State" start="16" size="4" access="ReadOnly" />
+      <BitField name="TPS1" description="DMA Channel 1 Transmit Process State" start="20" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAA4TXACR" description="AXI4 transmit channel ACE control register" start="+0x1020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRC" description="Transmit DMA Read Descriptor Cache Control" start="0" size="4" access="Read/Write" />
+      <BitField name="TEC" description="Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" start="8" size="4" access="Read/Write" />
+      <BitField name="THC" description="Transmit DMA First Packet Buffer or TSO Header Cache Control" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAA4RXACR" description="AXI4 receive channel ACE control register" start="+0x1024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDWC" description="Receive DMA Write Descriptor Cache Control" start="0" size="4" access="Read/Write" />
+      <BitField name="RPC" description="Receive DMA Payload Cache Control" start="8" size="4" access="Read/Write" />
+      <BitField name="RHC" description="Receive DMA Header Cache Control" start="16" size="4" access="Read/Write" />
+      <BitField name="RDC" description="Receive DMA Buffer Cache Control" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAA4DACR" description="AXI4 descriptor ACE control register" start="+0x1028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDWC" description="Transmit DMA Write Descriptor Cache control " start="0" size="4" access="Read/Write" />
+      <BitField name="TDWD" description="Transmit DMA Write Descriptor Domain control " start="4" size="2" access="Read/Write" />
+      <BitField name="RDRC" description="Receive DMA Read Descriptor Cache control " start="8" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMALPIEI" description="AXI4 LPI Entry Interval register" start="+0x1040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPIEI" description="LPI Entry Interval " start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMATBSCTRL0R" description="DMA TBS control register 0" start="+0x1050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTOV" description="Fetch time offset valid" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fetch time offset invalid" start="0x0" />
+        <Enum name="B_0x1" description="Fetch time offset valid" start="0x1" />
+      </BitField>
+      <BitField name="FGOS" description="Fetch GSN offset" start="4" size="3" access="Read/Write" />
+      <BitField name="FTOS" description="Fetch time offset" start="8" size="24" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0CR" description="Channel 0 control register" start="+0x1100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSS" description="Maximum Segment Size" start="0" size="14" access="Read/Write" />
+      <BitField name="PBLX8" description="8xPBL mode" start="16" size="1" access="Read/Write" />
+      <BitField name="DSL" description="Descriptor Skip Length" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXCR" description="Channel 0 transmit control register" start="+0x1104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ST" description="Start or Stop Transmission Command" start="0" size="1" access="Read/Write" />
+      <BitField name="TCW" description="Transmit Channel Weight " start="1" size="3" access="ReadOnly" />
+      <BitField name="OSF" description="Operate on Second Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="TSE" description="TCP Segmentation Enabled" start="12" size="1" access="Read/Write" />
+      <BitField name="IPBL" description="Ignore PBL Requirement" start="15" size="1" access="Read/Write" />
+      <BitField name="TXPBL" description="Transmit Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="TQOS" description="Transmit QOS" start="24" size="4" access="Read/Write" />
+      <BitField name="EDSE" description="Enhanced Descriptor Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXCR" description="Channel 0 receive control register" start="+0x1108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SR" description="Start or Stop Receive" start="0" size="1" access="Read/Write" />
+      <BitField name="RBSZ" description="Receive Buffer size" start="1" size="14" access="Read/Write" />
+      <BitField name="RXPBL" description="Receive Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="RQOS" description="Rx AXI4 QOS." start="24" size="4" access="Read/Write" />
+      <BitField name="RPF" description="DMA Rx Channel x Packet Flush" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXDLAR" description="Channel 0 T0 descriptor list address register" start="+0x1114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDESLA" description="Start of Transmit List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXDLAR" description="Channel 0 Rx descriptor list address register" start="+0x111C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDESLA" description="Start of Receive List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXDTPR" description="Channel 0 T0 descriptor tail pointer register" start="+0x1120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDT" description="Transmit Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXDTPR" description="Channel 0 R0 descriptor tail pointer register" start="+0x1128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDT" description="Receive Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXRLR" description="Channel 0 T0 descriptor ring length register" start="+0x112C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRL" description="Transmit Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXRLR" description="Channel 0 R0 descriptor ring length register" start="+0x1130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDRL" description="Receive Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+      <BitField name="ARBS" description="Alternate Receive Buffer Size" start="17" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0IER" description="Channel 0 interrupt enable register" start="+0x1134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmit Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TXSE" description="Transmit Stopped Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TBUE" description="Transmit Buffer Unavailable Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="RIE" description="Receive Interrupt Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="RBUE" description="Receive Buffer Unavailable Enable" start="7" size="1" access="Read/Write" />
+      <BitField name="RSE" description="Receive Stopped Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="RWTE" description="Receive Watchdog Timeout Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="ETIE" description="Early Transmit Interrupt Enable" start="10" size="1" access="Read/Write" />
+      <BitField name="ERIE" description="Early Receive Interrupt Enable" start="11" size="1" access="Read/Write" />
+      <BitField name="FBEE" description="Fatal Bus Error Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CDEE" description="Context Descriptor Error Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="AIE" description="Abnormal Interrupt Summary Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="NIE" description="Normal Interrupt Summary Enable" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXIWTR" description="Channel 0 R0 interrupt watchdog timer register" start="+0x1138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWT" description="Receive Interrupt Watchdog Timer Count" start="0" size="8" access="Read/Write" />
+      <BitField name="RWTU" description="Receive Interrupt Watchdog Timer Count Units" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="256" start="0x0" />
+        <Enum name="B_0x1" description="512" start="0x1" />
+        <Enum name="B_0x2" description="1024" start="0x2" />
+        <Enum name="B_0x3" description="2048" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_DMAC0SFCSR" description="Channel 0 slot function control status register" start="+0x113C" size="4" reset_value="0x000007C0" reset_mask="0xFFFFFFFF">
+      <BitField name="ESC" description="Enable Slot Comparison" start="0" size="1" access="Read/Write" />
+      <BitField name="ASC" description="Advance Slot Check" start="1" size="1" access="Read/Write" />
+      <BitField name="SIV" description="Slot Interval Value" start="4" size="12" access="Read/Write" />
+      <BitField name="RSN" description="Reference Slot Number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CATXDR" description="Channel 0 current application transmit descriptor register" start="+0x1144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTDESAPTR" description="Application Transmit Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CARXDR" description="Channel 0 current application receive descriptor register" start="+0x114C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRDESAPTR" description="Application Receive Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CATXBR" description="Channel 0 current application transmit buffer register" start="+0x1154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTBUFAPTR" description="Application Transmit Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CARXBR" description="Channel 0 current application receive buffer register" start="+0x115C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRBUFAPTR" description="Application Receive Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0SR" description="Channel 0 status register" start="+0x1160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI" description="Transmit Interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="TPS" description="Transmit Process Stopped" start="1" size="1" access="Read/Write" />
+      <BitField name="TBU" description="Transmit Buffer Unavailable" start="2" size="1" access="Read/Write" />
+      <BitField name="RI" description="Receive Interrupt" start="6" size="1" access="Read/Write" />
+      <BitField name="RBU" description="Receive Buffer Unavailable" start="7" size="1" access="Read/Write" />
+      <BitField name="RPS" description="Receive Process Stopped" start="8" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="9" size="1" access="Read/Write" />
+      <BitField name="ETI" description="Early Transmit Interrupt" start="10" size="1" access="Read/Write" />
+      <BitField name="ERI" description="Early Receive Interrupt" start="11" size="1" access="Read/Write" />
+      <BitField name="FBE" description="Fatal Bus Error" start="12" size="1" access="Read/Write" />
+      <BitField name="CDE" description="Context Descriptor Error" start="13" size="1" access="Read/Write" />
+      <BitField name="AIS" description="Abnormal Interrupt Summary" start="14" size="1" access="Read/Write" />
+      <BitField name="NIS" description="Normal Interrupt Summary" start="15" size="1" access="Read/Write" />
+      <BitField name="TEB" description="Tx DMA Error Bits " start="16" size="3" access="ReadOnly" />
+      <BitField name="REB" description="Rx DMA Error Bits" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0MFCR" description="Channel 0 missed frame count register" start="+0x1164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MFC" description="Dropped Packet Counters" start="0" size="11" access="Read/Write" />
+      <BitField name="MFCO" description="Overflow status of the MFC Counter" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1CR" description="Channel 1 control register" start="+0x1180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSS" description="Maximum Segment Size" start="0" size="14" access="Read/Write" />
+      <BitField name="PBLX8" description="8xPBL mode" start="16" size="1" access="Read/Write" />
+      <BitField name="DSL" description="Descriptor Skip Length" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXCR" description="Channel 1 transmit control register" start="+0x1184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ST" description="Start or Stop Transmission Command" start="0" size="1" access="Read/Write" />
+      <BitField name="TCW" description="Transmit Channel Weight " start="1" size="3" access="ReadOnly" />
+      <BitField name="OSF" description="Operate on Second Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="TSE" description="TCP Segmentation Enabled" start="12" size="1" access="Read/Write" />
+      <BitField name="IPBL" description="Ignore PBL Requirement" start="15" size="1" access="Read/Write" />
+      <BitField name="TXPBL" description="Transmit Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="TQOS" description="Transmit QOS" start="24" size="4" access="Read/Write" />
+      <BitField name="EDSE" description="Enhanced Descriptor Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXCR" description="Channel 1 receive control register" start="+0x1188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SR" description="Start or Stop Receive" start="0" size="1" access="Read/Write" />
+      <BitField name="RBSZ" description="Receive Buffer size" start="1" size="14" access="Read/Write" />
+      <BitField name="RXPBL" description="Receive Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="RQOS" description="Rx AXI4 QOS." start="24" size="4" access="Read/Write" />
+      <BitField name="RPF" description="DMA Rx Channel x Packet Flush" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXDLAR" description="Channel 1 T1 descriptor list address register" start="+0x1194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDESLA" description="Start of Transmit List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXDTPR" description="Channel 1 T1 descriptor tail pointer register" start="+0x11A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDT" description="Transmit Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXDTPR" description="Channel 1 R1 descriptor tail pointer register" start="+0x11A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDT" description="Receive Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXRLR" description="Channel 1 T1 descriptor ring length register" start="+0x11AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRL" description="Transmit Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXRLR" description="Channel 1 R1 descriptor ring length register" start="+0x11B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDRL" description="Receive Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+      <BitField name="ARBS" description="Alternate Receive Buffer Size" start="17" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1IER" description="Channel 1 interrupt enable register" start="+0x11B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmit Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TXSE" description="Transmit Stopped Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TBUE" description="Transmit Buffer Unavailable Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="RIE" description="Receive Interrupt Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="RBUE" description="Receive Buffer Unavailable Enable" start="7" size="1" access="Read/Write" />
+      <BitField name="RSE" description="Receive Stopped Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="RWTE" description="Receive Watchdog Timeout Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="ETIE" description="Early Transmit Interrupt Enable" start="10" size="1" access="Read/Write" />
+      <BitField name="ERIE" description="Early Receive Interrupt Enable" start="11" size="1" access="Read/Write" />
+      <BitField name="FBEE" description="Fatal Bus Error Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CDEE" description="Context Descriptor Error Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="AIE" description="Abnormal Interrupt Summary Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="NIE" description="Normal Interrupt Summary Enable" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXIWTR" description="Channel 1 R1 interrupt watchdog timer register" start="+0x11B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWT" description="Receive Interrupt Watchdog Timer Count" start="0" size="8" access="Read/Write" />
+      <BitField name="RWTU" description="Receive Interrupt Watchdog Timer Count Units" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="256" start="0x0" />
+        <Enum name="B_0x1" description="512" start="0x1" />
+        <Enum name="B_0x2" description="1024" start="0x2" />
+        <Enum name="B_0x3" description="2048" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_DMAC1SFCSR" description="Channel 1 slot function control status register" start="+0x11BC" size="4" reset_value="0x000007C0" reset_mask="0xFFFFFFFF">
+      <BitField name="ESC" description="Enable Slot Comparison" start="0" size="1" access="Read/Write" />
+      <BitField name="ASC" description="Advance Slot Check" start="1" size="1" access="Read/Write" />
+      <BitField name="SIV" description="Slot Interval Value" start="4" size="12" access="Read/Write" />
+      <BitField name="RSN" description="Reference Slot Number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CATXDR" description="Channel 1 current application transmit descriptor register" start="+0x11C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTDESAPTR" description="Application Transmit Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CARXDR" description="Channel 1 current application receive descriptor register" start="+0x11CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRDESAPTR" description="Application Receive Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CATXBR" description="Channel 1 current application transmit buffer register" start="+0x11D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTBUFAPTR" description="Application Transmit Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CARXBR" description="Channel 1 current application receive buffer register" start="+0x11DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRBUFAPTR" description="Application Receive Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1SR" description="Channel 1 status register" start="+0x11E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI" description="Transmit Interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="TPS" description="Transmit Process Stopped" start="1" size="1" access="Read/Write" />
+      <BitField name="TBU" description="Transmit Buffer Unavailable" start="2" size="1" access="Read/Write" />
+      <BitField name="RI" description="Receive Interrupt" start="6" size="1" access="Read/Write" />
+      <BitField name="RBU" description="Receive Buffer Unavailable" start="7" size="1" access="Read/Write" />
+      <BitField name="RPS" description="Receive Process Stopped" start="8" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="9" size="1" access="Read/Write" />
+      <BitField name="ETI" description="Early Transmit Interrupt" start="10" size="1" access="Read/Write" />
+      <BitField name="ERI" description="Early Receive Interrupt" start="11" size="1" access="Read/Write" />
+      <BitField name="FBE" description="Fatal Bus Error" start="12" size="1" access="Read/Write" />
+      <BitField name="CDE" description="Context Descriptor Error" start="13" size="1" access="Read/Write" />
+      <BitField name="AIS" description="Abnormal Interrupt Summary" start="14" size="1" access="Read/Write" />
+      <BitField name="NIS" description="Normal Interrupt Summary" start="15" size="1" access="Read/Write" />
+      <BitField name="TEB" description="Tx DMA Error Bits " start="16" size="3" access="ReadOnly" />
+      <BitField name="REB" description="Rx DMA Error Bits" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1MFCR" description="Channel 1 missed frame count register" start="+0x11E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MFC" description="Dropped Packet Counters" start="0" size="11" access="Read/Write" />
+      <BitField name="MFCO" description="Overflow status of the MFC Counter" start="15" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ETH_S" description="Ethernet address block description" start="0x58036000">
+    <Register name="ETH_MACCR" description="Operating mode configuration register" start="+0x0000" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Receiver Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TE" description="Transmitter Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="PRELEN" description="Preamble Length for Transmit packets" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="7 bytes of preamble" start="0x0" />
+        <Enum name="B_0x1" description="5 bytes of preamble" start="0x1" />
+        <Enum name="B_0x2" description="3 bytes of preamble" start="0x2" />
+      </BitField>
+      <BitField name="DC" description="Deferral Check" start="4" size="1" access="Read/Write" />
+      <BitField name="BL" description="Back-Off Limit" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="k= min (n, 10)" start="0x0" />
+        <Enum name="B_0x1" description="k = min (n, 8)" start="0x1" />
+        <Enum name="B_0x2" description="k = min (n, 4)" start="0x2" />
+        <Enum name="B_0x3" description="k = min (n, 1)" start="0x3" />
+      </BitField>
+      <BitField name="DR" description="Disable Retry" start="8" size="1" access="Read/Write" />
+      <BitField name="DCRS" description="Disable Carrier Sense During Transmission" start="9" size="1" access="Read/Write" />
+      <BitField name="DO" description="Disable Receive Own" start="10" size="1" access="Read/Write" />
+      <BitField name="ECRSFD" description="Enable Carrier Sense Before Transmission in Full-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="LM" description="Loopback Mode" start="12" size="1" access="Read/Write" />
+      <BitField name="DM" description="Duplex Mode" start="13" size="1" access="Read/Write" />
+      <BitField name="FES" description="MAC Speed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10 Mbps" start="0x0" />
+        <Enum name="B_0x1" description="100 Mbps" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Port Select" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="For 1000 Mbps operations" start="0x0" />
+        <Enum name="B_0x1" description="For 10 or 100 Mbps operations" start="0x1" />
+      </BitField>
+      <BitField name="JE" description="Jumbo Packet Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="JD" description="Jabber Disable" start="17" size="1" access="Read/Write" />
+      <BitField name="BE" description="Packet Burst Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="WD" description="Watchdog Disable" start="19" size="1" access="Read/Write" />
+      <BitField name="ACS" description="Automatic Pad or CRC Stripping" start="20" size="1" access="Read/Write" />
+      <BitField name="CST" description="CRC stripping for Type packets" start="21" size="1" access="Read/Write" />
+      <BitField name="S2KP" description="IEEE 802.3as Support for 2K Packets" start="22" size="1" access="Read/Write" />
+      <BitField name="GPSLCE" description="Giant Packet Size Limit Control Enable" start="23" size="1" access="Read/Write" />
+      <BitField name="IPG" description="Inter-Packet Gap" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="96 bit times" start="0x0" />
+        <Enum name="B_0x1" description="88 bit times" start="0x1" />
+        <Enum name="B_0x2" description="80 bit times" start="0x2" />
+        <Enum name="B_0x7" description="40 bit times" start="0x7" />
+      </BitField>
+      <BitField name="IPC" description="Checksum Offload" start="27" size="1" access="Read/Write" />
+      <BitField name="SARC" description="Source Address Insertion or Replacement Control" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="the MAC inserts the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x2" />
+        <Enum name="B_0x3" description="the MAC replaces the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x3" />
+        <Enum name="B_0x6" description="the MAC inserts the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets" start="0x6" />
+        <Enum name="B_0x7" description="the MAC replaces the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets." start="0x7" />
+      </BitField>
+      <BitField name="ARPEN" description="ARP Offload Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACECR" description="Extended operating mode configuration register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPSL" description="Giant Packet Size Limit" start="0" size="14" access="Read/Write" />
+      <BitField name="DCRCC" description="Disable CRC Checking for Received Packets" start="16" size="1" access="Read/Write" />
+      <BitField name="SPEN" description="Slow Protocol Detection Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="USP" description="Unicast Slow Protocol Packet Detect" start="18" size="1" access="Read/Write" />
+      <BitField name="EIPGEN" description="Extended Inter-Packet Gap Enable" start="24" size="1" access="Read/Write" />
+      <BitField name="EIPG" description="Extended Inter-Packet Gap" start="25" size="5" access="Read/Write" />
+      <BitField name="APDIM" description="ARP Packet Drop if IP Address Mismatch" start="30" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPFR" description="Packet filtering control register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="Promiscuous Mode" start="0" size="1" access="Read/Write" />
+      <BitField name="HUC" description="Hash Unicast" start="1" size="1" access="Read/Write" />
+      <BitField name="HMC" description="Hash Multicast" start="2" size="1" access="Read/Write" />
+      <BitField name="DAIF" description="DA Inverse Filtering" start="3" size="1" access="Read/Write" />
+      <BitField name="PM" description="Pass All Multicast" start="4" size="1" access="Read/Write" />
+      <BitField name="DBF" description="Disable Broadcast Packets" start="5" size="1" access="Read/Write" />
+      <BitField name="PCF" description="Pass Control Packets" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The MAC filters all control packets from reaching the application." start="0x0" />
+        <Enum name="B_0x1" description="The MAC forwards all control packets except Pause packets to the application even if they fail the Address filter." start="0x1" />
+        <Enum name="B_0x2" description="The MAC forwards all control packets to the application even if they fail the Address filter." start="0x2" />
+        <Enum name="B_0x3" description="The MAC forwards the control packets that pass the Address filter." start="0x3" />
+      </BitField>
+      <BitField name="SAIF" description="SA Inverse Filtering" start="8" size="1" access="Read/Write" />
+      <BitField name="SAF" description="Source Address Filter Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="HPF" description="Hash or Perfect Filter" start="10" size="1" access="Read/Write" />
+      <BitField name="VTFE" description="VLAN Tag Filter Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="IPFE" description="Layer 3 and Layer 4 Filter Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="DNTU" description="Drop Non-TCP/UDP over IP Packets" start="21" size="1" access="Read/Write" />
+      <BitField name="RA" description="Receive All" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACWTR" description="Watchdog timeout register" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WTO" description="Watchdog Timeout" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="2 Kbytes" start="0x0" />
+        <Enum name="B_0x1" description="3 Kbytes" start="0x1" />
+        <Enum name="B_0x2" description="4 Kbytes" start="0x2" />
+        <Enum name="B_0x3" description="5 Kbytes" start="0x3" />
+        <Enum name="B_0xC" description="14 Kbytes" start="0xC" />
+        <Enum name="B_0xD" description="15 Kbytes" start="0xD" />
+        <Enum name="B_0xE" description="16383 Bytes" start="0xE" />
+      </BitField>
+      <BitField name="PWE" description="Programmable Watchdog Enable" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACHT0R" description="Hash Table 0 register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT31T0" description="MAC Hash Table First 32 Bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACHT1R" description="Hash Table 1 register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT63T32" description="MAC Hash Table Second 32 Bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVTCR" description="VLAN tag Control register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OB" description="Operation Busy" start="0" size="1" access="Read/Write" />
+      <BitField name="CT" description="Command Type" start="1" size="1" access="Read/Write" />
+      <BitField name="OFS" description="Offset" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="ETH_MACVTDR holds MAC VLAN Tag Filter0 content" start="0x0" />
+        <Enum name="B_0x1" description="ETH_MACVTDR holds MAC VLAN Tag Filter1 content" start="0x1" />
+        <Enum name="B_0x2" description="ETH_MACVTDR holds MAC VLAN Tag Filter2 content" start="0x2" />
+        <Enum name="B_0x3" description="ETH_MACVTDR holds MAC VLAN Tag Filter3 content" start="0x3" />
+      </BitField>
+      <BitField name="ETV" description="Enable 12-Bit VLAN Tag Comparison" start="16" size="1" access="Read/Write" />
+      <BitField name="VTIM" description="VLAN Tag Inverse Match Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="ESVL" description="Enable S-VLAN" start="18" size="1" access="Read/Write" />
+      <BitField name="ERSVLM" description="Enable Receive S-VLAN Match" start="19" size="1" access="Read/Write" />
+      <BitField name="DOVLTC" description="Disable VLAN Type Check" start="20" size="1" access="Read/Write" />
+      <BitField name="EVLS" description="Enable VLAN Tag Stripping on Receive" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Do not strip" start="0x0" />
+        <Enum name="B_0x1" description="Strip if VLAN filter passes" start="0x1" />
+        <Enum name="B_0x2" description="Strip if VLAN filter fails" start="0x2" />
+        <Enum name="B_0x3" description="Always strip" start="0x3" />
+      </BitField>
+      <BitField name="EVLRXS" description="Enable VLAN Tag in Rx status" start="24" size="1" access="Read/Write" />
+      <BitField name="VTHM" description="VLAN Tag Hash Table Match Enable" start="25" size="1" access="Read/Write" />
+      <BitField name="EDVLP" description="Enable Double VLAN Processing" start="26" size="1" access="Read/Write" />
+      <BitField name="ERIVLT" description="Enable Inner VLAN Tag" start="27" size="1" access="Read/Write" />
+      <BitField name="EIVLS" description="Enable Inner VLAN Tag Stripping on Receive" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Do not strip" start="0x0" />
+        <Enum name="B_0x1" description="Strip if VLAN filter passes" start="0x1" />
+        <Enum name="B_0x2" description="Strip if VLAN filter fails" start="0x2" />
+        <Enum name="B_0x3" description="Always strip" start="0x3" />
+      </BitField>
+      <BitField name="EIVLRXS" description="Enable Inner VLAN Tag in Rx Status" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVTDR" description="VLAN tag data register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VID" description="VLAN Tag ID" start="0" size="16" access="Read/Write" />
+      <BitField name="VEN" description="VLAN Tag Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="ETV" description="12-bit or 16-bit VLAN comparison" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit VLAN" start="0x0" />
+        <Enum name="B_0x1" description="12-bit VLAN" start="0x1" />
+      </BitField>
+      <BitField name="DOVLTC" description="Disable VLAN Type Comparison" start="18" size="1" access="Read/Write" />
+      <BitField name="ERSVLM" description="Enable S-VLAN Match for received Frames" start="19" size="1" access="Read/Write" />
+      <BitField name="ERIVLT" description="Enable Inner VLAN Tag Comparison" start="20" size="1" access="Read/Write" />
+      <BitField name="DMACHEN" description="DMA Channel Number Enable" start="24" size="1" access="Read/Write" />
+      <BitField name="DMACHN" description="DMA Channel Number" start="25" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVHTR" description="VLAN Hash table register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLHT" description="VLAN Hash Table" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACVIR" description="VLAN inclusion register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="VLC" description="VLAN Tag Control in Transmit Packets" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No VLAN tag deletion, insertion, or replacement" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag deletion. The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags." start="0x1" />
+        <Enum name="B_0x2" description="VLAN tag insertion. The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and 14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag." start="0x2" />
+        <Enum name="B_0x3" description="VLAN tag replacement. The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8)." start="0x3" />
+      </BitField>
+      <BitField name="VLP" description="VLAN Priority Control" start="18" size="1" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+      <BitField name="VLTI" description="VLAN Tag Input" start="20" size="1" access="Read/Write" />
+      <BitField name="CBTI" description="Channel based tag insertion" start="21" size="1" access="Read/Write" />
+      <BitField name="ADDR" description="Address" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VLAN tag for insertion in the Transmit packets from Tx Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag for insertion in the Transmit packets from Tx Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="RDWR" description="Read write control" start="30" size="1" access="Read/Write" />
+      <BitField name="BUSY" description="Busy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACVIR_alternate" description="VLAN inclusion register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACIVIR" description="Inner VLAN inclusion register" start="+0x0064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLAN Tag for Transmit Packets" start="0" size="16" access="Read/Write" />
+      <BitField name="VLC" description="VLAN Tag Control in Transmit Packets" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No VLAN tag deletion, insertion, or replacement" start="0x0" />
+        <Enum name="B_0x1" description="VLAN tag deletion" start="0x1" />
+        <Enum name="B_0x2" description="VLAN tag insertion" start="0x2" />
+        <Enum name="B_0x3" description="VLAN tag replacement" start="0x3" />
+      </BitField>
+      <BitField name="VLP" description="VLAN Priority Control" start="18" size="1" access="Read/Write" />
+      <BitField name="CSVL" description="C-VLAN or S-VLAN" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-LAN" start="0x0" />
+        <Enum name="B_0x1" description="S-LAN" start="0x1" />
+      </BitField>
+      <BitField name="VLTI" description="VLAN Tag Input" start="20" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACQ0TXFCR" description="Tx Queue 0 flow control register" start="+0x0070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCB_BPA" description="Flow Control Busy or Backpressure Activate" start="0" size="1" access="Read/Write" />
+      <BitField name="TFE" description="Transmit Flow Control Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="PLT" description="Pause Low Threshold" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Pause Time minus 4 Slot Times (PT -4 slot times)" start="0x0" />
+        <Enum name="B_0x1" description="Pause Time minus 28 Slot Times (PT -28 slot times)" start="0x1" />
+        <Enum name="B_0x2" description="Pause Time minus 36 Slot Times (PT -36 slot times)" start="0x2" />
+        <Enum name="B_0x3" description="Pause Time minus 144 Slot Times (PT -144 slot times)" start="0x3" />
+        <Enum name="B_0x4" description="Pause Time minus 256 Slot Times (PT -256 slot times)" start="0x4" />
+        <Enum name="B_0x5" description="Pause Time minus 512 Slot Times (PT -512 slot times)" start="0x5" />
+      </BitField>
+      <BitField name="DZPQ" description="Disable Zero-Quanta Pause" start="7" size="1" access="Read/Write" />
+      <BitField name="PT" description="Pause Time" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXFCR" description="Rx flow control register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RFE" description="Receive Flow Control Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="UP" description="Unicast Pause Packet Detect" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXQCR" description="Rx Queue control register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFQE" description="Unicast Address Filter Fail Packets Queuing Enable." start="0" size="1" access="Read/Write" />
+      <BitField name="UFFQ" description="Unicast Address Filter Fail Packets Queue." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MFFQE" description="Multicast Address Filter Fail Packets Queuing Enable." start="8" size="1" access="Read/Write" />
+      <BitField name="MFFQ" description="Multicast Address Filter Fail Packets Queue." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="VFFQE" description="VLAN Tag Filter Fail Packets Queuing Enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="VFFQ" description="VLAN Tag Filter Fail Packets Queue" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACRXQC0R" description="Rx queue control 0 register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ0EN" description="Receive Queue 0 Enable" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Queue 0 enabled for AV" start="0x1" />
+        <Enum name="B_0x2" description="Queue 0 enabled for Generic traffic" start="0x2" />
+      </BitField>
+      <BitField name="RXQ1EN" description="Receive Queue 1 Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Queue 1 enabled for AV" start="0x1" />
+        <Enum name="B_0x2" description="Queue 1 enabled for Generic traffic" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACRXQC1R" description="Rx queue control 1 register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVCPQ0" description="AV Untagged Control Packets Queue" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="AVCPQ1" description="AV Untagged Control Packets Queue" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="AVCPQ2" description="AV Untagged Control Packets Queue" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive Queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Receive Queue 1" start="0x1" />
+      </BitField>
+      <BitField name="PTPQ" description="PTP Packets Queue" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="UPQ" description="Untagged Packet Queue " start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MCBCQ" description="Multicast and Broadcast Queue " start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Rx queue 0" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="MCBCQEN" description="Multicast and Broadcast Queue Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="TACPQE" description="Tagged AV Control Packets Queuing Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="TPQC" description="Tagged PTP over Ethernet Packets Queuing Control" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="VLAN tagged PTPoE packets are routed as generic VLAN tagged packet (based on PSRQ for only non-AV enabled Rx queues)." start="0x0" />
+        <Enum name="B_0x1" description="VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field (this Rx Queue can be enabled for AV or non-AV traffic)" start="0x1" />
+        <Enum name="B_0x2" description="VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ." start="0x2" />
+      </BitField>
+      <BitField name="FPRQ0" description="Frame Preemption Residue Queue" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="FPRQ1" description="Frame Preemption Residue Queue" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="FPRQ2" description="Frame Preemption Residue Queue" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Rx queue 1" start="0x1" />
+      </BitField>
+      <BitField name="OMCBCQ" description="Overriding MC-BC queue priority select" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Priority of MCBCQ is reduced and the received packet is first routed to PTPQ, AVCPQ, depending on packet type." start="0x1" />
+        <Enum name="B_0x0" description="Received Multicast/Broadcast packet is routed to MCBCQ." start="0x0" />
+      </BitField>
+      <BitField name="TBRQE" description="Type Field Based Rx Queuing Enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXQC2R" description="Rx queue control 2 register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSRQ0" description="Priorities Selected in the Receive Queue 0" start="0" size="8" access="Read/Write" />
+      <BitField name="PSRQ1" description="Priorities Selected in the Receive Queue 1" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACISR" description="Interrupt status register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RGSMIIIS" description="RGMII Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PHYIS" description="PHY Interrupt" start="3" size="1" access="ReadOnly" />
+      <BitField name="PMTIS" description="PMT Interrupt Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="LPIIS" description="LPI Interrupt Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="MMCIS" description="MMC Interrupt Status" start="8" size="1" access="ReadOnly" />
+      <BitField name="MMCRXIS" description="MMC Receive Interrupt Status" start="9" size="1" access="ReadOnly" />
+      <BitField name="MMCTXIS" description="MMC Transmit Interrupt Status" start="10" size="1" access="ReadOnly" />
+      <BitField name="TSIS" description="Timestamp Interrupt Status" start="12" size="1" access="Read/Write" />
+      <BitField name="TXSTSIS" description="Transmit Status Interrupt" start="13" size="1" access="Read/Write" />
+      <BitField name="RXSTSIS" description="Receive Status Interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="FPEIS" description="Frame Preemption Interrupt Status" start="17" size="1" access="ReadOnly" />
+      <BitField name="MDIOIS" description="MDIO Interrupt Status" start="18" size="1" access="Read/Write" />
+      <BitField name="MFTIS" description="MMC FPE Transmit Interrupt Status" start="19" size="1" access="ReadOnly" />
+      <BitField name="MFRIS" description="MMC FPE Receive Interrupt Status" start="20" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACIER" description="Interrupt enable register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RGSMIIIE" description="RGMII Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="PHYIE" description="PHY Interrupt Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="PMTIE" description="PMT Interrupt Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="LPIIE" description="LPI Interrupt Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TSIE" description="Timestamp Interrupt Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="TXSTSIE" description="Transmit Status Interrupt Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="RXSTSIE" description="Receive Status Interrupt Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="FPEIE" description="Frame Preemption Interrupt Enable" start="17" size="1" access="Read/Write" />
+      <BitField name="MDIOIE" description="MDIO Interrupt Enable" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRXTXSR" description="Rx Tx status register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TJT" description="Transmit Jabber Timeout" start="0" size="1" access="Read/Write" />
+      <BitField name="NCARR" description="No Carrier" start="1" size="1" access="Read/Write" />
+      <BitField name="LCARR" description="Loss of Carrier" start="2" size="1" access="Read/Write" />
+      <BitField name="EXDEF" description="Excessive Deferral" start="3" size="1" access="Read/Write" />
+      <BitField name="LCOL" description="Late Collision" start="4" size="1" access="Read/Write" />
+      <BitField name="EXCOL" description="Excessive Collisions" start="5" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPCSR" description="PMT control status register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDWN" description="Power Down" start="0" size="1" access="Read/Write" />
+      <BitField name="MGKPKTEN" description="Magic Packet Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="RWKPKTEN" description="Remote wake-up Packet Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="MGKPRCVD" description="Magic Packet Received" start="5" size="1" access="Read/Write" />
+      <BitField name="RWKPRCVD" description="Remote wake-up Packet Received" start="6" size="1" access="ReadOnly" />
+      <BitField name="GLBLUCAST" description="Global Unicast" start="9" size="1" access="Read/Write" />
+      <BitField name="RWKPFE" description="Remote wake-up Packet Forwarding Enable " start="10" size="1" access="Read/Write" />
+      <BitField name="RWKPTR" description="Remote wake-up FIFO Pointer" start="24" size="5" access="ReadOnly" />
+      <BitField name="RWKFILTRST" description="Remote wake-up Packet Filter Register Pointer Reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACRWKPFR" description="Remote wake-up packet filter register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MACRWKPFR" description="Remote wake-up packet filter" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLCSR" description="LPI control and status register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TLPIEN" description="Transmit LPI Entry" start="0" size="1" access="ReadOnly" />
+      <BitField name="TLPIEX" description="Transmit LPI Exit" start="1" size="1" access="ReadOnly" />
+      <BitField name="RLPIEN" description="Receive LPI Entry" start="2" size="1" access="ReadOnly" />
+      <BitField name="RLPIEX" description="Receive LPI Exit" start="3" size="1" access="ReadOnly" />
+      <BitField name="TLPIST" description="Transmit LPI State" start="8" size="1" access="ReadOnly" />
+      <BitField name="RLPIST" description="Receive LPI State" start="9" size="1" access="ReadOnly" />
+      <BitField name="LPIEN" description="LPI Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="PLS" description="PHY Link Status" start="17" size="1" access="Read/Write" />
+      <BitField name="PLSEN" description="PHY Link Status Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="LPITXA" description="LPI Tx Automate" start="19" size="1" access="Read/Write" />
+      <BitField name="LPITE" description="LPI Timer Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="LPITCSE" description="LPI Tx Clock Stop Enable" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLTCR" description="LPI timers control register" start="+0x00D4" size="4" reset_value="0x03E80000" reset_mask="0xFFFFFFFF">
+      <BitField name="TWT" description="LPI TW Timer" start="0" size="16" access="Read/Write" />
+      <BitField name="LST" description="LPI LS Timer" start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLETR" description="LPI entry timer register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPIET" description="LPI Entry Timer" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MAC1USTCR" description="One-microsecond-tick counter register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIC_1US_CNTR" description="1 s tick Counter" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPHYCSR" description="PHYIF control status register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TC" description="Transmit Configuration in RGMII" start="0" size="1" access="Read/Write" />
+      <BitField name="LUD" description="Link Up or Down" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Link Down" start="0x0" />
+        <Enum name="B_0x1" description="Link Up" start="0x1" />
+      </BitField>
+      <BitField name="LNKMOD" description="Link Mode" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Half-duplex mode" start="0x0" />
+        <Enum name="B_0x1" description="Full-duplex mode" start="0x1" />
+      </BitField>
+      <BitField name="LNKSPEED" description="Link Speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="2.5 MHz" start="0x0" />
+        <Enum name="B_0x1" description="25 MHz" start="0x1" />
+        <Enum name="B_0x2" description="125 MHz" start="0x2" />
+      </BitField>
+      <BitField name="LNKSTS" description="Link Status" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Link down" start="0x0" />
+        <Enum name="B_0x1" description="Link up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACVR" description="Version register" start="+0x0110" size="4" reset_value="0x00001052" reset_mask="0xFFFFFFFF">
+      <BitField name="SNPSVER" description="IP version" start="0" size="8" access="ReadOnly" />
+      <BitField name="USERVER" description="ST-defined version" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACDR" description="Debug register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPESTS" description="MAC GMII or MII Receive Protocol Engine Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RFCFCSTS" description="MAC Receive Packet Controller FIFO Status" start="1" size="2" access="ReadOnly" />
+      <BitField name="TPESTS" description="MAC GMII or MII Transmit Protocol Engine Status" start="16" size="1" access="ReadOnly" />
+      <BitField name="TFCSTS" description="MAC Transmit Packet Controller Status" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Waiting for one of the following:" start="0x1" />
+        <Enum name="B_0x2" description="Generating and transmitting a Pause control packet (in Full-duplex mode)" start="0x2" />
+        <Enum name="B_0x3" description="Transferring input packet for transmission" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF0R" description="HW feature 0 register" start="+0x011C" size="4" reset_value="0x0E0D73F7" reset_mask="0xFFFFFFFF">
+      <BitField name="MIISEL" description="10 or 100 Mbps Support" start="0" size="1" access="ReadOnly" />
+      <BitField name="GMIISEL" description="1000 Mbps Support" start="1" size="1" access="ReadOnly" />
+      <BitField name="HDSEL" description="Half-duplex Support" start="2" size="1" access="ReadOnly" />
+      <BitField name="PCSSEL" description="PCS Registers (TBI, SGMII, or RTBI PHY interface)" start="3" size="1" access="ReadOnly" />
+      <BitField name="VLHASH" description="VLAN Hash Filter Selected" start="4" size="1" access="ReadOnly" />
+      <BitField name="SMASEL" description="SMA (MDIO) Interface" start="5" size="1" access="ReadOnly" />
+      <BitField name="RWKSEL" description="PMT Remote wake-up Packet Enable" start="6" size="1" access="ReadOnly" />
+      <BitField name="MGKSEL" description="PMT Magic Packet Enable" start="7" size="1" access="ReadOnly" />
+      <BitField name="MMCSEL" description="RMON Module Enable" start="8" size="1" access="ReadOnly" />
+      <BitField name="ARPOFFSEL" description="ARP Offload Enabled" start="9" size="1" access="ReadOnly" />
+      <BitField name="TSSEL" description="IEEE 1588-2008 Timestamp Enabled" start="12" size="1" access="ReadOnly" />
+      <BitField name="EEESEL" description="Energy Efficient Ethernet Enabled" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXCOESEL" description="Transmit Checksum Offload Enabled" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXCOESEL" description="Receive Checksum Offload Enabled" start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDMACADRSEL" description="MAC Addresses 1-31 Selected" start="18" size="5" access="ReadOnly" />
+      <BitField name="MACADR32SEL" description="MAC Addresses 32-63 Selected" start="23" size="1" access="ReadOnly" />
+      <BitField name="MACADR64SEL" description="MAC Addresses 64-127 Selected" start="24" size="1" access="ReadOnly" />
+      <BitField name="TSSTSSEL" description="Timestamp System Time Source" start="25" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Internal" start="0x1" />
+        <Enum name="B_0x2" description="External" start="0x2" />
+        <Enum name="B_0x3" description="Both" start="0x3" />
+      </BitField>
+      <BitField name="SAVLANINS" description="Source Address or VLAN Insertion Enable" start="27" size="1" access="ReadOnly" />
+      <BitField name="ACTPHYSEL" description="Active PHY Selected" start="28" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="GMII or MII" start="0x0" />
+        <Enum name="B_0x1" description="RGMII" start="0x1" />
+        <Enum name="B_0x2" description="SGMII" start="0x2" />
+        <Enum name="B_0x3" description="TBI" start="0x3" />
+        <Enum name="B_0x4" description="RMII" start="0x4" />
+        <Enum name="B_0x5" description="RTBI" start="0x5" />
+        <Enum name="B_0x6" description="SMII" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF1R" description="HW feature 1 register" start="+0x0120" size="4" reset_value="0x11141965" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFIFOSIZE" description="MTL Receive FIFO Size" start="0" size="5" access="ReadOnly">
+        <Enum name="B_0x0" description="128 bytes" start="0x0" />
+        <Enum name="B_0x1" description="256 bytes" start="0x1" />
+        <Enum name="B_0x2" description="512 bytes" start="0x2" />
+        <Enum name="B_0x3" description="1,024 bytes" start="0x3" />
+        <Enum name="B_0x4" description="2,048 bytes" start="0x4" />
+        <Enum name="B_0x5" description="4,096 bytes" start="0x5" />
+        <Enum name="B_0x6" description="8,192 bytes" start="0x6" />
+        <Enum name="B_0x7" description="16,384 bytes" start="0x7" />
+        <Enum name="B_0x8" description="32 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="64 Kbytes" start="0x9" />
+        <Enum name="B_0xA" description="128 Kbytes" start="0xA" />
+        <Enum name="B_0xB" description="256 Kbytes" start="0xB" />
+      </BitField>
+      <BitField name="SPRAM" description="Single Port RAM Enable" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOSIZE" description="MTL Transmit FIFO Size" start="6" size="5" access="ReadOnly">
+        <Enum name="B_0x0" description="128 bytes" start="0x0" />
+        <Enum name="B_0x1" description="256 bytes" start="0x1" />
+        <Enum name="B_0x2" description="512 bytes" start="0x2" />
+        <Enum name="B_0x3" description="1,024 bytes" start="0x3" />
+        <Enum name="B_0x4" description="2,048 bytes" start="0x4" />
+        <Enum name="B_0x5" description="4,096 bytes" start="0x5" />
+        <Enum name="B_0x6" description="8,192 bytes" start="0x6" />
+        <Enum name="B_0x7" description="16,384 bytes" start="0x7" />
+        <Enum name="B_0x8" description="32 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="64 Kbytes" start="0x9" />
+        <Enum name="B_0xA" description="128 Kbytes" start="0xA" />
+      </BitField>
+      <BitField name="OSTEN" description="One-Step Timestamping Enable" start="11" size="1" access="ReadOnly" />
+      <BitField name="PTOEN" description="PTP Offload Enable" start="12" size="1" access="ReadOnly" />
+      <BitField name="ADVTHWORD" description="IEEE 1588 High Word Register Enable" start="13" size="1" access="ReadOnly" />
+      <BitField name="ADDR64" description="Address width" start="14" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="32 bits" start="0x0" />
+      </BitField>
+      <BitField name="DCBEN" description="DCB Feature Enable" start="16" size="1" access="ReadOnly" />
+      <BitField name="SPHEN" description="Split Header Feature Enable" start="17" size="1" access="ReadOnly" />
+      <BitField name="TSOEN" description="TCP Segmentation Offload Enable" start="18" size="1" access="ReadOnly" />
+      <BitField name="DBGMEMA" description="DMA Debug Registers Enable" start="19" size="1" access="ReadOnly" />
+      <BitField name="AVSEL" description="AV Feature Enable" start="20" size="1" access="ReadOnly" />
+      <BitField name="RAVSEL" description="Rx Side Only AV Feature Enable" start="21" size="1" access="ReadOnly" />
+      <BitField name="POUOST" description="One Step for PTP over UDP/IP Feature Enable" start="23" size="1" access="ReadOnly" />
+      <BitField name="HASHTBLSZ" description="Hash Table Size" start="24" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hash table" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="128" start="0x2" />
+        <Enum name="B_0x3" description="256" start="0x3" />
+      </BitField>
+      <BitField name="L3L4FNUM" description="Total number of L3 or L4 Filters" start="27" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="No L3 or L4 Filter" start="0x0" />
+        <Enum name="B_0x1" description="1 L3 or L4 Filter" start="0x1" />
+        <Enum name="B_0x2" description="2 L3 or L4 Filters" start="0x2" />
+        <Enum name="B_0x8" description="8 L3 or L4" start="0x8" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF2R" description="HW feature 2 register" start="+0x0124" size="4" reset_value="0x41041041" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQCNT" description="Number of MTL Receive Queues" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 MTL Rx queue" start="0x0" />
+        <Enum name="B_0x1" description="2 MTL Rx queues" start="0x1" />
+        <Enum name="B_0x7" description="8 MTL Rx" start="0x7" />
+      </BitField>
+      <BitField name="TXQCNT" description="Number of MTL Transmit Queues" start="6" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 MTL Tx queue" start="0x0" />
+        <Enum name="B_0x1" description="2 MTL Tx queues" start="0x1" />
+        <Enum name="B_0x7" description="8 MTL Tx" start="0x7" />
+      </BitField>
+      <BitField name="RXCHCNT" description="Number of DMA Receive Channels" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 DMA Rx Channel" start="0x0" />
+        <Enum name="B_0x1" description="2 DMA Rx Channels" start="0x1" />
+        <Enum name="B_0x7" description="8 DMA Rx" start="0x7" />
+      </BitField>
+      <BitField name="RDCSZ" description="Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Cache not configured" start="0x0" />
+        <Enum name="B_0x1" description="Four 16-byte descriptors" start="0x1" />
+        <Enum name="B_0x2" description="Eight 16-byte descriptors" start="0x2" />
+        <Enum name="B_0x3" description="Sixteen 16-byte descriptors" start="0x3" />
+      </BitField>
+      <BitField name="TXCHCNT" description="Number of DMA Transmit Channels" start="18" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="1 DMA Tx Channel" start="0x0" />
+        <Enum name="B_0x1" description="2 DMA Tx Channels" start="0x1" />
+        <Enum name="B_0x7" description="8 DMA Tx" start="0x7" />
+      </BitField>
+      <BitField name="TDCSZ" description="Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Cache not configured" start="0x0" />
+        <Enum name="B_0x1" description="Four 16-byte descriptors" start="0x1" />
+        <Enum name="B_0x2" description="Eight 16-byte descriptors" start="0x2" />
+        <Enum name="B_0x3" description="Sixteen 16-byte descriptors" start="0x3" />
+      </BitField>
+      <BitField name="PPSOUTNUM" description="Number of PPS Outputs" start="24" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No PPS output" start="0x0" />
+        <Enum name="B_0x1" description="1 PPS output" start="0x1" />
+        <Enum name="B_0x2" description="2 PPS outputs" start="0x2" />
+        <Enum name="B_0x3" description="3 PPS outputs" start="0x3" />
+        <Enum name="B_0x4" description="4 PPS outputs" start="0x4" />
+      </BitField>
+      <BitField name="AUXSNAPNUM" description="Number of Auxiliary Snapshot Inputs" start="28" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No auxiliary input" start="0x0" />
+        <Enum name="B_0x1" description="1 auxiliary input" start="0x1" />
+        <Enum name="B_0x2" description="2 auxiliary inputs" start="0x2" />
+        <Enum name="B_0x3" description="3 auxiliary inputs" start="0x3" />
+        <Enum name="B_0x4" description="4 auxiliary inputs" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACHWF3R" description="HW feature 3 register" start="+0x0128" size="4" reset_value="0x0C330031" reset_mask="0xFFFFFFFF">
+      <BitField name="NRVF" description="Number of Extended VLAN Tag Filters Enabled" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No Extended Rx VLAN Filters" start="0x0" />
+        <Enum name="B_0x1" description="4 Extended Rx VLAN Filters" start="0x1" />
+        <Enum name="B_0x2" description="8 Extended Rx VLAN Filters" start="0x2" />
+        <Enum name="B_0x3" description="16 Extended Rx VLAN Filters" start="0x3" />
+        <Enum name="B_0x4" description="24 Extended Rx VLAN Filters" start="0x4" />
+        <Enum name="B_0x5" description="32 Extended Rx VLAN Filters" start="0x5" />
+      </BitField>
+      <BitField name="CBTISEL" description="Queue/Channel based VLAN tag insertion on Tx enable" start="4" size="1" access="ReadOnly" />
+      <BitField name="DVLAN" description="Double VLAN processing enable" start="5" size="1" access="ReadOnly" />
+      <BitField name="PDUPSEL" description="Broadcast/Multicast Packet Duplication" start="9" size="1" access="ReadOnly" />
+      <BitField name="FRPSEL" description="Flexible Receive Parser Selected" start="10" size="1" access="ReadOnly" />
+      <BitField name="FRPBS" description="Flexible Receive Parser Buffer size" start="11" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+      </BitField>
+      <BitField name="FRPES" description="Flexible Receive Parser Table Entries size" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 entries" start="0x0" />
+        <Enum name="B_0x1" description="128 entries" start="0x1" />
+        <Enum name="B_0x2" description="256 entries" start="0x2" />
+      </BitField>
+      <BitField name="ESTSEL" description="Enhancements to Scheduled Traffic Enable" start="16" size="1" access="ReadOnly" />
+      <BitField name="ESTDEP" description="Depth of the Gate Control List" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No depth" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="128" start="0x2" />
+        <Enum name="B_0x3" description="256" start="0x3" />
+        <Enum name="B_0x4" description="512" start="0x4" />
+        <Enum name="B_0x5" description="1024" start="0x5" />
+      </BitField>
+      <BitField name="ESTWID" description="Width of the Time Interval field in the Gate Control List" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No width" start="0x0" />
+        <Enum name="B_0x1" description="16" start="0x1" />
+        <Enum name="B_0x2" description="20" start="0x2" />
+        <Enum name="B_0x3" description="24" start="0x3" />
+      </BitField>
+      <BitField name="FPESEL" description="Frame Preemption Enable" start="26" size="1" access="ReadOnly" />
+      <BitField name="TBSSEL" description="Time-based scheduling Enable" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASP" description="Automotive Safety Package" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="None" start="0x0" />
+        <Enum name="B_0x1" description="ECC only" start="0x1" />
+        <Enum name="B_0x2" description="AS_NPPE" start="0x2" />
+        <Enum name="B_0x3" description="AS_PPE" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACMDIOAR" description="MDIO address register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GB" description="GMII Busy" start="0" size="1" access="Read/Write" />
+      <BitField name="C45E" description="Clause 45 PHY Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="GOC" description="GMII Operation Command" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="Write" start="0x1" />
+        <Enum name="B_0x2" description="Post Read Increment Address for Clause 45 PHY" start="0x2" />
+        <Enum name="B_0x3" description="Read" start="0x3" />
+      </BitField>
+      <BitField name="SKAP" description="Skip Address Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="CR" description="CSR Clock Range" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="CSR clock = 60-100 MHz; MDC clock = CSR clock/42" start="0x0" />
+        <Enum name="B_0x1" description="CSR clock = 100-150 MHz; MDC clock = CSR clock/62" start="0x1" />
+        <Enum name="B_0x2" description="CSR clock = 20-35 MHz; MDC clock = CSR clock/16" start="0x2" />
+        <Enum name="B_0x3" description="CSR clock = 35-60 MHz; MDC clock = CSR clock/26" start="0x3" />
+        <Enum name="B_0x4" description="CSR clock = 150-250 MHz; MDC clock = CSR clock/102" start="0x4" />
+        <Enum name="B_0x5" description="CSR clock = 250-300 MHz; MDC clock = CSR clock/124" start="0x5" />
+        <Enum name="B_0x6" description="CSR clock = 300-500 MHz; MDC clock = CSR clock/204" start="0x6" />
+        <Enum name="B_0x7" description="CSR clock = 500-800 MHz; MDC clock = CSR clock/324" start="0x7" />
+        <Enum name="B_0x8" description="CSR clock/4" start="0x8" />
+        <Enum name="B_0x9" description="CSR clock/6" start="0x9" />
+        <Enum name="B_0xA" description="CSR clock/8" start="0xA" />
+        <Enum name="B_0xB" description="CSR clock/10" start="0xB" />
+        <Enum name="B_0xC" description="CSR clock/12" start="0xC" />
+        <Enum name="B_0xD" description="CSR clock/14" start="0xD" />
+        <Enum name="B_0xE" description="CSR clock/16" start="0xE" />
+        <Enum name="B_0xF" description="CSR clock/18" start="0xF" />
+      </BitField>
+      <BitField name="NTC" description="Number of Training Clocks" start="12" size="3" access="Read/Write" />
+      <BitField name="RDA" description="Register/Device Address" start="16" size="5" access="Read/Write" />
+      <BitField name="PA" description="Physical Layer Address" start="21" size="5" access="Read/Write" />
+      <BitField name="BTB" description="Back to Back transactions" start="26" size="1" access="Read/Write" />
+      <BitField name="PSE" description="Preamble Suppression Enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACMDIODR" description="MDIO data register" start="+0x0204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GD" description="GMII Data" start="0" size="16" access="Read/Write" />
+      <BitField name="RA" description="Register Address" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACARPAR" description="ARP address register" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARPPA" description="ARP Protocol Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACCSRSWCR" description="CSR software control register" start="+0x0230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RCWE" description="Register Clear on Write 1 Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SEEN" description="Slave Error Response Enable" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACFPECSR" description="FPE control and status register" start="+0x0234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFPE" description="Enable Tx Frame Preemption" start="0" size="1" access="Read/Write" />
+      <BitField name="SVER" description="Send Verify mPacket" start="1" size="1" access="Read/Write" />
+      <BitField name="SRSP" description="Send Respond mPacket" start="2" size="1" access="Read/Write" />
+      <BitField name="RVER" description="Received Verify Frame" start="16" size="1" access="Read/Write" />
+      <BitField name="RRSP" description="Received Respond Frame" start="17" size="1" access="Read/Write" />
+      <BitField name="TVER" description="Transmitted Verify Frame" start="18" size="1" access="Read/Write" />
+      <BitField name="TRSP" description="Transmitted Respond Frame" start="19" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPRSTIMR" description="MAC presentation time register" start="+0x0240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPTN" description="MAC 1722 Presentation Time in ns" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPRSTIMUR" description="MAC presentation time update register" start="+0x0244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPTU" description="MAC 1722 Presentation Time Update" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA0HR" description="MAC Address 0 high register" start="+0x0300" size="4" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address0[47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACA0LR" description="MAC Address 0 low register" start="+0x304" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA1HR" description="MAC Address 1 high register" start="+0x308" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA1LR" description="MAC Address 1 low register" start="+0x30C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA2HR" description="MAC Address 2 high register" start="+0x310" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA2LR" description="MAC Address 2 low register" start="+0x314" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA3HR" description="MAC Address 3 high register" start="+0x318" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="MAC Address1 [47:32]" start="0" size="16" access="Read/Write" />
+      <BitField name="DCS" description="DMA Channel Select" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Rx channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Rx channel 1" start="0x1" />
+      </BitField>
+      <BitField name="MBC" description="Mask Byte Control" start="24" size="6" access="Read/Write" />
+      <BitField name="SA" description="Source Address" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DA" start="0x0" />
+        <Enum name="B_0x1" description="SA" start="0x1" />
+      </BitField>
+      <BitField name="AE" description="Address Enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACA3LR" description="MAC Address 3 low register" start="+0x31C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="MAC Address x [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_CONTROL" description="MMC control register" start="+0x0700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNTRST" description="Counters Reset" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTSTOPRO" description="Counter Stop Rollover" start="1" size="1" access="Read/Write" />
+      <BitField name="RSTONRD" description="Reset on Read" start="2" size="1" access="Read/Write" />
+      <BitField name="CNTFREEZ" description="MMC Counter Freeze" start="3" size="1" access="Read/Write" />
+      <BitField name="CNTPRST" description="Counters Preset" start="4" size="1" access="Read/Write" />
+      <BitField name="CNTPRSTLVL" description="Full-Half Preset" start="5" size="1" access="Read/Write" />
+      <BitField name="UCDBC" description="Update MMC Counters for Dropped Broadcast Packets " start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_RX_INTERRUPT" description="MMC Rx interrupt register" start="+0x0704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIS" description="MMC Receive CRC Error Packet Counter Interrupt Status" start="5" size="1" access="Read/Write" />
+      <BitField name="RXALGNERPIS" description="MMC Receive Alignment Error Packet Counter Interrupt Status" start="6" size="1" access="Read/Write" />
+      <BitField name="RXUCGPIS" description="MMC Receive Unicast Good Packet Counter Interrupt Status" start="17" size="1" access="Read/Write" />
+      <BitField name="RXLPIUSCIS" description="MMC Receive LPI microsecond counter interrupt status" start="26" size="1" access="Read/Write" />
+      <BitField name="RXLPITRCIS" description="MMC Receive LPI transition counter interrupt status" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_TX_INTERRUPT" description="MMC Tx interrupt register" start="+0x0708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIS" description="MMC Transmit Single Collision Good Packet Counter Interrupt Status" start="14" size="1" access="Read/Write" />
+      <BitField name="TXMCOLGPIS" description="MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" start="15" size="1" access="Read/Write" />
+      <BitField name="TXGPKTIS" description="MMC Transmit Good Packet Counter Interrupt Status" start="21" size="1" access="Read/Write" />
+      <BitField name="TXLPIUSCIS" description="MMC Transmit LPI microsecond counter interrupt status" start="26" size="1" access="Read/Write" />
+      <BitField name="TXLPITRCIS" description="MMC Transmit LPI transition counter interrupt status" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_RX_INTERRUPT_MASK" description="MMC Rx interrupt mask register" start="+0x070C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIM" description="MMC Receive CRC Error Packet Counter Interrupt Mask" start="5" size="1" access="Read/Write" />
+      <BitField name="RXALGNERPIM" description="MMC Receive Alignment Error Packet Counter Interrupt Mask" start="6" size="1" access="Read/Write" />
+      <BitField name="RXUCGPIM" description="MMC Receive Unicast Good Packet Counter Interrupt Mask" start="17" size="1" access="Read/Write" />
+      <BitField name="RXLPIUSCIM" description="MMC Receive LPI microsecond counter interrupt Mask" start="26" size="1" access="Read/Write" />
+      <BitField name="RXLPITRCIM" description="MMC Receive LPI transition counter interrupt Mask" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_TX_INTERRUPT_MASK" description="MMC Tx interrupt mask register" start="+0x0710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIM" description="MMC Transmit Single Collision Good Packet Counter Interrupt Mask" start="14" size="1" access="Read/Write" />
+      <BitField name="TXMCOLGPIM" description="MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" start="15" size="1" access="Read/Write" />
+      <BitField name="TXGPKTIM" description="MMC Transmit Good Packet Counter Interrupt Mask" start="21" size="1" access="Read/Write" />
+      <BitField name="TXLPIUSCIM" description="MMC Transmit LPI microsecond counter interrupt Mask" start="26" size="1" access="Read/Write" />
+      <BitField name="TXLPITRCIM" description="MMC Transmit LPI transition counter interrupt Mask" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_TX_SINGLE_COLLISION_GOOD_PACKETS" description="Tx single collision good packets register" start="+0x074C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSNGLCOLG" description="Tx Single Collision Good Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS" description="Tx multiple collision good packets register" start="+0x0750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMULTCOLG" description="Tx Multiple Collision Good Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_PACKET_COUNT_GOOD" description="Tx packet count good register" start="+0x0768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXPKTG" description="Tx Packet Count Good" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_CRC_ERROR_PACKETS" description="Rx CRC error packets register" start="+0x0794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERR" description="Rx CRC Error Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_ALIGNMENT_ERROR_PACKETS" description="Rx alignment error packets register" start="+0x0798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXALGNERR" description="Rx Alignment Error Packets" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_UNICAST_PACKETS_GOOD" description="Rx unicast packets good register" start="+0x07C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXUCASTG" description="Rx Unicast Packets Good" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_LPI_USEC_CNTR" description="Tx LPI microsecond timer register" start="+0x07EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPIUSC" description="Tx LPI Microseconds Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_TX_LPI_TRAN_CNTR" description="Tx LPI transition counter register" start="+0x07F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPITRC" description="Tx LPI Transition counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_LPI_USEC_CNTR" description="Rx LPI microsecond counter register" start="+0x07F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPIUSC" description="Rx LPI Microseconds Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_LPI_TRAN_CNTR" description="Rx LPI transition counter register" start="+0x07F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPITRC" description="Rx LPI Transition counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_ISR" description="MMC FPE Tx interrupt status register" start="+0x08A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCIS" description="MMC Tx FPE Fragment Counter Interrupt status" start="0" size="1" access="Read/Write" />
+      <BitField name="HRCIS" description="MMC Tx Hold Request Counter Interrupt Status" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_IMR" description="MMC FPE Tx interrupt mask register" start="+0x08A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCIM" description="MMC Transmit Fragment Counter Interrupt Mask" start="0" size="1" access="Read/Write" />
+      <BitField name="HRCIM" description="MMC Transmit Hold Request Counter Interrupt Mask" start="1" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MMC_FPE_TX_FCR" description="MMC FPE Tx fragment counter register" start="+0x08A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFFC" description="Tx FPE Fragment counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_TX_HRCR" description="MMC Tx hold request counter register" start="+0x08AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXHRC" description="Tx Hold Request Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_RX_ISR" description="MMC FPE Rx interrupt status register" start="+0x08C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAECIS" description="MMC Rx Packet Assembly Error Counter Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PSECIS" description="MMC Rx Packet SMD Error Counter Interrupt Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="PAOCIS" description="MMC Rx Packet Assembly OK Counter Interrupt Status" start="2" size="1" access="ReadOnly" />
+      <BitField name="FCIS" description="MMC Rx FPE Fragment Counter Interrupt Status" start="3" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MMC_FPE_RX_IMR" description="MMC FPE Rx interrupt mask register" start="+0x08C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAECIM" description="MMC Rx Packet Assembly Error Counter Interrupt Mask" start="0" size="1" access="Read/Write" />
+      <BitField name="PSECIM" description="MMC Rx Packet SMD Error Counter Interrupt Mask" start="1" size="1" access="Read/Write" />
+      <BitField name="PAOCIM" description="MMC Rx Packet Assembly OK Counter Interrupt Mask" start="2" size="1" access="Read/Write" />
+      <BitField name="FCIM" description="MMC Rx FPE Fragment Counter Interrupt Mask" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_RX_PACKET_ASM_ERR" description="MMC Rx packet assembly error register" start="+0x08C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAEC" description="Rx Packet Assembly Error Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_PACKET_SMD_ERR" description="MMC Rx packet SMD error register" start="+0x08CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSEC" description="Rx Packet SMD Error Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_PACKET_ASM_OKR" description="MMC Rx packet assembly OK register" start="+0x08D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAOC" description="Rx Packet Assembly OK Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_RX_FPE_FRAG_CR" description="MMC Rx FPE fragments counter register" start="+0x08D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FFC" description="Rx FPE Fragment Counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACL3L4C0R" description="L3 and L4 control 0 register" start="+0x0900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN0" description="Layer 3 Protocol Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="L3SAM0" description="Layer 3 IP SA Match Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="L3SAIM0" description="Layer 3 IP SA Inverse Match Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="L3DAM0" description="Layer 3 IP DA Match Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="L3DAIM0" description="Layer 3 IP DA Inverse Match Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="L3HSBM0" description="Layer 3 IP SA higher bits match" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L3HDBM0" description="Layer 3 IP DA higher bits match" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L4PEN0" description="Layer 4 Protocol Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="L4SPM0" description="Layer 4 Source Port Match Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="L4SPIM0" description="Layer 4 Source Port Inverse Match Enable" start="19" size="1" access="Read/Write" />
+      <BitField name="L4DPM0" description="Layer 4 Destination Port Match Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="L4DPIM0" description="Layer 4 Destination Port Inverse Match Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="DMCHN0" description="DMA Channel Number" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA channel 1" start="0x1" />
+      </BitField>
+      <BitField name="DMCHEN0" description="DMA Channel Select Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL4A0R" description="Layer4 Address filter 0 register" start="+0x0904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP0" description="Layer 4 Source Port Number Field" start="0" size="16" access="Read/Write" />
+      <BitField name="L4DP0" description="Layer 4 Destination Port Number Field" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A00R" description="Layer3 Address 0 filter 0 register" start="+0x0910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A00" description="Layer 3 Address 0 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A10R" description="Layer3 Address 1 filter 0 register" start="+0x0914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A10" description="Layer 3 Address 1 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A20R" description="Layer3 Address 2 filter 0 register" start="+0x0918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A20" description="Layer 3 Address 2 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A30R" description="Layer3 Address 3 filter 0 register" start="+0x091C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A30" description="Layer 3 Address 3 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3L4C1R" description="L3 and L4 control 1 register" start="+0x0930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN1" description="Layer 3 Protocol Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="L3SAM1" description="Layer 3 IP SA Match Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="L3SAIM1" description="Layer 3 IP SA Inverse Match Enable" start="3" size="1" access="Read/Write" />
+      <BitField name="L3DAM1" description="Layer 3 IP DA Match Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="L3DAIM1" description="Layer 3 IP DA Inverse Match Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="L3HSBM1" description="Layer 3 IP SA Higher Bits Match" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L3HDBM1" description="Layer 3 IP DA higher bits match" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x0_IPV4_PACKETS" description="No bits are masked." start="0x0" />
+        <Enum name="B_0x1_IPV4_PACKETS" description="LSb[0] is masked" start="0x1" />
+      </BitField>
+      <BitField name="L4PEN1" description="Layer 4 Protocol Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="L4SPM1" description="Layer 4 Source Port Match Enable" start="18" size="1" access="Read/Write" />
+      <BitField name="L4SPIM1" description="Layer 4 Source Port Inverse Match Enable" start="19" size="1" access="Read/Write" />
+      <BitField name="L4DPM1" description="Layer 4 Destination Port Match Enable" start="20" size="1" access="Read/Write" />
+      <BitField name="L4DPIM1" description="Layer 4 Destination Port Inverse Match Enable" start="21" size="1" access="Read/Write" />
+      <BitField name="DMCHN1" description="DMA Channel Number" start="24" size="1" access="Read/Write" />
+      <BitField name="DMCHEN1" description="DMA Channel Select Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL4A1R" description="Layer 4 address filter 1 register" start="+0x0934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP1" description="Layer 4 Source Port Number Field" start="0" size="16" access="Read/Write" />
+      <BitField name="L4DP1" description="Layer 4 Destination Port Number Field" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A01R" description="Layer3 address 0 filter 1 Register" start="+0x0940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A01" description="Layer 3 Address 0 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A11R" description="Layer3 address 1 filter 1 register" start="+0x0944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A11" description="Layer 3 Address 1 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A21R" description="Layer3 address 2 filter 1 Register" start="+0x0948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A21" description="Layer 3 Address 2 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACL3A31R" description="Layer3 address 3 filter 1 register" start="+0x94C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A31" description="Layer 3 Address 3 Field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MAC_IACR" description="MAC Indirect Access Control register" start="+0x0A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OB" description="Operation Busy." start="0" size="1" access="Read/Write" />
+      <BitField name="COM" description="Command type" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates a read operation." start="0x1" />
+        <Enum name="B_0x0" description="Indicates a write operation." start="0x0" />
+      </BitField>
+      <BitField name="AUTO" description="Auto-increment" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="AOFF is incremented by 1. The software should ensure not to cause a wrap condition. Byte-wise read/write is not supported when auto-increment is enabled." start="0x1" />
+        <Enum name="B_0x0" description="AOFF is not automatically incremented. The software should program the correct address offset for each access." start="0x0" />
+      </BitField>
+      <BitField name="AOFF" description="Address Offset" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IndReg0 (Indirect register 0)" start="0x0" />
+        <Enum name="B_0x1" description="IndReg1 (Indirect register 1)" start="0x1" />
+        <Enum name="B_0x7" description="IndReg7 (Indirect register 7)" start="0x7" />
+      </BitField>
+      <BitField name="MSEL" description="Mode Select" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Typ_RXQ_ (Type-based RXQ mapping)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MAC_TMRQR" description="MAC type-based Rx Queue mapping register" start="+0x0A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TYP" description="Type field Value" start="0" size="16" access="Read/Write" />
+      <BitField name="TMRQ" description="Type Match Rx Queue Number" start="16" size="3" access="Read/Write" />
+      <BitField name="PFEX" description="Preemption or Express Packet" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Express packet" start="0x0" />
+        <Enum name="B_0x1" description="Preemption packet" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MACTSCR" description="Timestamp control Register" start="+0x0B00" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSENA" description="Enable Timestamp" start="0" size="1" access="Read/Write" />
+      <BitField name="TSCFUPDT" description="Fine or Coarse Timestamp Update" start="1" size="1" access="Read/Write" />
+      <BitField name="TSINIT" description="Initialize Timestamp" start="2" size="1" access="Read/Write" />
+      <BitField name="TSUPDT" description="Update Timestamp" start="3" size="1" access="Read/Write" />
+      <BitField name="TSADDREG" description="Update Addend Register" start="5" size="1" access="Read/Write" />
+      <BitField name="PTGE" description="Presentation Time Generation Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="TSENALL" description="Enable Timestamp for All Packets" start="8" size="1" access="Read/Write" />
+      <BitField name="TSCTRLSSR" description="Timestamp Digital or Binary Rollover Control" start="9" size="1" access="Read/Write" />
+      <BitField name="TSVER2ENA" description="Enable PTP Packet Processing for Version 2 Format" start="10" size="1" access="Read/Write" />
+      <BitField name="TSIPENA" description="Enable Processing of PTP over Ethernet Packets" start="11" size="1" access="Read/Write" />
+      <BitField name="TSIPV6ENA" description="Enable Processing of PTP Packets Sent over IPv6-UDP" start="12" size="1" access="Read/Write" />
+      <BitField name="TSIPV4ENA" description="Enable Processing of PTP Packets Sent over IPv4-UDP" start="13" size="1" access="Read/Write" />
+      <BitField name="TSEVNTENA" description="Enable Timestamp Snapshot for Event Messages" start="14" size="1" access="Read/Write" />
+      <BitField name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master" start="15" size="1" access="Read/Write" />
+      <BitField name="SNAPTYPSEL" description="Select PTP packets for Taking Snapshots" start="16" size="2" access="Read/Write" />
+      <BitField name="TSENMACADDR" description="Enable MAC Address for PTP Packet Filtering" start="18" size="1" access="Read/Write" />
+      <BitField name="ESTI" description="External System Time Input" start="20" size="1" access="Read/Write" />
+      <BitField name="TXTSSTSM" description="Transmit Timestamp Status Mode" start="24" size="1" access="Read/Write" />
+      <BitField name="AV8021ASMEN" description="AV 802.1AS Mode Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSSIR" description="Subsecond increment register" start="+0x0B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SSINC" description="Subsecond Increment Value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSTSR" description="System time seconds register" start="+0x0B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp Second" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACSTNR" description="System time nanoseconds register" start="+0x0B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="Timestamp subseconds" start="0" size="31" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACSTSUR" description="System time seconds update register" start="+0x0B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp Seconds" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSTNUR" description="System time nanoseconds update register" start="+0x0B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="Timestamp subseconds" start="0" size="31" access="Read/Write" />
+      <BitField name="ADDSUB" description="Add or Subtract Time" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSAR" description="Timestamp addend register" start="+0x0B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSAR" description="Timestamp Addend Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSSR" description="Timestamp status register" start="+0x0B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSOVF" description="Timestamp Seconds Overflow" start="0" size="1" access="Read/Write" />
+      <BitField name="TSTARGT0" description="Timestamp Target Time Reached" start="1" size="1" access="Read/Write" />
+      <BitField name="AUXTSTRIG" description="Auxiliary Timestamp Trigger Snapshot" start="2" size="1" access="Read/Write" />
+      <BitField name="TSTRGTERR0" description="Timestamp Target Time Error" start="3" size="1" access="Read/Write" />
+      <BitField name="TSTARGT1" description="Timestamp Target Time Reached" start="4" size="1" access="Read/Write" />
+      <BitField name="TSTRGTERR1" description="Timestamp Target Time Error" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTSSIS" description="Tx Timestamp Status Interrupt Status" start="15" size="1" access="Read/Write" />
+      <BitField name="ATSSTN" description="Auxiliary Timestamp Snapshot Trigger Identifier" start="16" size="4" access="Read/Write" />
+      <BitField name="ATSSTM" description="Auxiliary Timestamp Snapshot Trigger Missed" start="24" size="1" access="Read/Write" />
+      <BitField name="ATSNS" description="Number of Auxiliary Timestamp Snapshots" start="25" size="5" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTXTSSNR" description="Tx timestamp status nanoseconds register" start="+0x0B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSLO" description="Transmit Timestamp Status Low" start="0" size="31" access="Read/Write" />
+      <BitField name="TXTSSMIS" description="Transmit Timestamp Status Missed" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTXTSSSR" description="Tx timestamp status seconds register" start="+0x0B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSHI" description="Transmit Timestamp Status High" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACACR" description="Auxiliary control register" start="+0x0B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATSFC" description="Auxiliary Snapshot FIFO Clear" start="0" size="1" access="Read/Write" />
+      <BitField name="ATSEN0" description="Auxiliary Snapshot 0 Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="ATSEN1" description="Auxiliary Snapshot 1 Enable" start="5" size="1" access="Read/Write" />
+      <BitField name="ATSEN2" description="Auxiliary Snapshot 2 Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="ATSEN3" description="Auxiliary Snapshot 3 Enable" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACATSNR" description="Auxiliary timestamp nanoseconds register" start="+0x0B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSLO" description="Auxiliary Timestamp" start="0" size="31" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACATSSR" description="Auxiliary timestamp seconds register" start="+0x0B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSHI" description="Auxiliary Timestamp" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTSIACR" description="Timestamp Ingress asymmetric correction register" start="+0x0B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTIAC" description="One-Step Timestamp Ingress Asymmetry Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSEACR" description="Timestamp Egress asymmetric correction register" start="+0x0B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTEAC" description="One-Step Timestamp Egress Asymmetry Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSICNR" description="Timestamp Ingress correction nanosecond register" start="+0x0B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIC" description="Timestamp Ingress Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSECNR" description="Timestamp Egress correction nanosecond register" start="+0x0B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEC" description="Timestamp Egress Correction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACTSILR" description="Timestamp Ingress Latency register" start="+0x0B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ITLSNS" description="Ingress Timestamp Latency, in subnanoseconds" start="8" size="8" access="ReadOnly" />
+      <BitField name="ITLNS" description="Ingress Timestamp Latency, in nanoseconds" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACTSELR" description="Timestamp Egress Latency register" start="+0x0B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETLSNS" description="Egress Timestamp Latency, in subnanoseconds" start="8" size="8" access="ReadOnly" />
+      <BitField name="ETLNS" description="Egress Timestamp Latency, in nanoseconds" start="16" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MACPPSCR" description="PPS control register" start="+0x0B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSCTRL" description="PPS Output Frequency Control" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="The binary rollover is 2 Hz, and the digital rollover is 1 Hz." start="0x1" />
+        <Enum name="B_0x2" description="The binary rollover is 4 Hz, and the digital rollover is 2 Hz." start="0x2" />
+        <Enum name="B_0x3" description="The binary rollover is 8 Hz, and the digital rollover is 4 Hz." start="0x3" />
+        <Enum name="B_0x4" description="The binary rollover is 16 Hz, and the digital rollover is 8 Hz." start="0x4" />
+        <Enum name="B_0xF" description="The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz." start="0xF" />
+      </BitField>
+      <BitField name="PPSEN0" description="Flexible PPS Output Mode Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="TRGTMODSEL0" description="Target Time Register Mode for PPS Output" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target Time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN0" description="MCGR Mode Enable for PPS0 Output" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="TIMESEL" description="Time Select" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSCR_alternate" description="PPS control register" start="+0x0B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSCMD" description="Flexible PPS Output 0 (eth_ptp_pps_out) Control" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No Command" start="0x0" />
+        <Enum name="B_0x1" description="START Single Pulse." start="0x1" />
+        <Enum name="B_0x2" description="START Pulse Train." start="0x2" />
+        <Enum name="B_0x3" description="Cancel START." start="0x3" />
+        <Enum name="B_0x4" description="STOP Pulse Train at time." start="0x4" />
+        <Enum name="B_0x5" description="STOP Pulse Train immediately." start="0x5" />
+        <Enum name="B_0x6" description="Cancel STOP Pulse train." start="0x6" />
+      </BitField>
+      <BitField name="PPSEN0" description="Flexible PPS Output 0 Mode Enable" start="4" size="1" access="Read/Write" />
+      <BitField name="TRGTMODSEL0" description="Target Time Register Mode for PPS Output 0" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target Time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output 0 signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target Time registers are programmed only for starting or stopping the PPS output 0 signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN0" description="MCGR Mode Enable for PPS Output 0" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="PPSCMD1" description="Flexible PPS Output 1 Control" start="8" size="4" access="Read/Write" />
+      <BitField name="TRGTMODSEL1" description="Target Time Register Mode for PPS Output 1" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Target time registers are programmed only for generating the interrupt event." start="0x0" />
+        <Enum name="B_0x1" description="Enabled MCGR Interrupt whose status bit is indicated by TSTARGT1 bit in Timestamp status register (ETH_MACTSSR) register" start="0x1" />
+        <Enum name="B_0x2" description="Target time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation." start="0x2" />
+        <Enum name="B_0x3" description="Target time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted." start="0x3" />
+      </BitField>
+      <BitField name="MCGREN1" description="MCGR Mode Enable for PPS Output 1" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PPS mode" start="0x0" />
+        <Enum name="B_0x1" description="MCGR mode" start="0x1" />
+      </BitField>
+      <BitField name="TIMESEL" description="Time Select" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTS0R" description="PPS 0 target time seconds register" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSTRH0" description="PPS Target Time Seconds Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTN0R" description="PPS 0 target time nanoseconds register" start="+0xB84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TTSL0" description="Target Time Low for PPS Register" start="0" size="31" access="Read/Write" />
+      <BitField name="TRGTBUSY0" description="PPS Target Time Register Busy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSI0R" description="PPS 0 interval register" start="+0xB88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSINT0" description="PPS Output Signal Interval" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSW0R" description="PPS 0 width register" start="+0xB8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSWIDTH0" description="PPS Output Signal Width" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTS1R" description="PPS 1 target time seconds register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSTRH0" description="PPS Target Time Seconds Register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSTTN1R" description="PPS 1 target time nanoseconds register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TTSL0" description="Target Time Low for PPS Register" start="0" size="31" access="Read/Write" />
+      <BitField name="TRGTBUSY0" description="PPS Target Time Register Busy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSI1R" description="PPS 1 interval register" start="+0xB98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSINT0" description="PPS Output Signal Interval" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPPSW1R" description="PPS 1 width register" start="+0xB9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSWIDTH0" description="PPS Output Signal Width" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACPOCR" description="PTP Offload control register" start="+0x0BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PTOEN" description="PTP Offload Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ASYNCEN" description="Automatic PTP SYNC message Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="APDREQEN" description="Automatic PTP Pdelay_Req message Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="ASYNCTRIG" description="Automatic PTP SYNC message Trigger" start="4" size="1" access="Read/Write" />
+      <BitField name="APDREQTRIG" description="Automatic PTP Pdelay_Req message Trigger" start="5" size="1" access="Read/Write" />
+      <BitField name="DRRDIS" description="Disable PTO Delay Request/Response response generation" start="6" size="1" access="Read/Write" />
+      <BitField name="PDRDIS" description="Disable Peer Delay Response response generation" start="7" size="1" access="Read/Write" />
+      <BitField name="DN" description="Domain Number" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI0R" description="PTP Source Port Identity 0 Register" start="+0x0BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI0" description="Source Port Identity 0" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI1R" description="PTP Source port identity 1 register" start="+0x0BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI1" description="Source Port Identity 1" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACSPI2R" description="PTP Source port identity 2 register" start="+0x0BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI2" description="Source Port Identity 2" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MACLMIR" description="Log message interval register" start="+0x0BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSI" description="Log Sync Interval" start="0" size="8" access="Read/Write" />
+      <BitField name="DRSYNCR" description="Delay_Req to SYNC Ratio " start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="DelayReq generated for every received SYNC" start="0x0" />
+        <Enum name="B_0x1" description="DelayReq generated every alternate reception of SYNC" start="0x1" />
+      </BitField>
+      <BitField name="LMPDRI" description="Log Min Pdelay_Req Interval" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLOMR" description="Operating mode Register" start="+0x0C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTXSTS" description="Drop Transmit Status" start="1" size="1" access="Read/Write" />
+      <BitField name="RAA" description="Receive Arbitration Algorithm" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest priority." start="0x0" />
+        <Enum name="B_0x1" description="Weighted Strict priority (WSP)" start="0x1" />
+      </BitField>
+      <BitField name="SCHALG" description="Tx Scheduling Algorithm" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Weighted round robin (WRR) algorithm" start="0x0" />
+        <Enum name="B_0x3" description="Strict priority (SP) algorithm." start="0x3" />
+      </BitField>
+      <BitField name="CNTPRST" description="Counters Preset" start="8" size="1" access="Read/Write" />
+      <BitField name="CNTCLR" description="Counters Reset" start="9" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLISR" description="Interrupt status Register" start="+0x0C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Q0IS" description="Queue 0 interrupt status" start="0" size="1" access="ReadOnly" />
+      <BitField name="Q1IS" description="Queue 1 interrupt status" start="1" size="1" access="ReadOnly" />
+      <BitField name="ESTIS" description="EST (TAS- 802.1Qbv) Interrupt Status" start="18" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQDMAMR" description="Rx Queue and DMA Channel Mapping Register" start="+0x0C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Q0MDMACH" description="Queue 0 Mapped to DMA Channel" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Channel 1" start="0x1" />
+      </BitField>
+      <BitField name="Q0DDMACH" description="Queue 0 Enabled for DA-based DMA Channel Selection" start="4" size="1" access="Read/Write" />
+      <BitField name="Q1MDMACH" description="Queue 1 Mapped to DMA Channel" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA Channel 0" start="0x0" />
+        <Enum name="B_0x1" description="DMA Channel 1" start="0x1" />
+      </BitField>
+      <BitField name="Q1DDMACH" description="Queue 1 Enabled for DA-based DMA Channel Selection" start="12" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTBSCR" description="TBS control register" start="+0x0C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESTM" description="EST offset mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EST offset mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="EST offset mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="LEOV" description="Launch expiry offset valid" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LEOS field invalid" start="0x0" />
+        <Enum name="B_0x1" description="LEOS field valid" start="0x1" />
+      </BitField>
+      <BitField name="LEGOS" description="Launch Expiry GSN Offset" start="4" size="3" access="Read/Write" />
+      <BitField name="LEOS" description="Launch Expiry Offset" start="8" size="24" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTCR" description="EST Control Register" start="+0x0C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EEST" description="Enable EST" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EST disabled" start="0x0" />
+        <Enum name="B_0x1" description="EST enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSWL" description="Switch to S/W owned list" start="1" size="1" access="Read/Write" />
+      <BitField name="DDBF" description="Do not Drop frames during Frame Size Error" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Drop" start="0x0" />
+        <Enum name="B_0x1" description="Don't drop" start="0x1" />
+      </BitField>
+      <BitField name="DFBS" description="Drop Frames causing Scheduling Error" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Don't drop" start="0x0" />
+        <Enum name="B_0x1" description="Drop" start="0x1" />
+      </BitField>
+      <BitField name="LCSE" description="Loop Count to report Scheduling Error" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="4 iterations" start="0x0" />
+        <Enum name="B_0x1" description="8 iterations" start="0x1" />
+        <Enum name="B_0x2" description="16 iterations" start="0x2" />
+        <Enum name="B_0x3" description="32 iterations" start="0x3" />
+      </BitField>
+      <BitField name="TILS" description="Time Interval Left Shift Amount" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift needed (equal to x1ns)" start="0x0" />
+        <Enum name="B_0x1" description="Left shift TI by 1 bit (equal to x2ns)" start="0x1" />
+        <Enum name="B_0x2" description="Left shift TI by 2 bits (equal to x4ns)" start="0x2" />
+        <Enum name="B_0x4" description="Left shift TI by 7 bits (equal to x128ns)" start="0x4" />
+      </BitField>
+      <BitField name="CTOV" description="Current Time Offset Value" start="12" size="12" access="Read/Write" />
+      <BitField name="PTOV" description="PTP Time Offset Value" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTECR" description="EST Extended Control Register" start="+0x0C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVHD" description="Overhead Bytes Value" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTSR" description="EST Status Register" start="+0x0C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWLC" description="Switch to S/W owned list Complete" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="BTRE" description="BTR Error" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="HLBF" description="Head-Of-Line Blocking due to Frame Size" start="2" size="1" access="ReadOnly" />
+      <BitField name="HLBS" description="Head-Of-Line Blocking due to Scheduling" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="CGCE" description="Constant Gate Control Error" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SWOL" description="S/W owned list" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Inactive" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="BTRL" description="BTR Error Loop Count" start="8" size="8" access="ReadOnly" />
+      <BitField name="CGSN" description="Current GCL slot number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLESTSCHER" description="EST Schedule Error Register" start="+0x0C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEQN" description="Schedule Error Queue Number" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTFSER" description="EST Frame size Error Register" start="+0x0C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEQN" description="Frame Size Error Queue Number" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTFSCR" description="EST Frame size Capture Register" start="+0x0C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HBFS" description="Frame Size of HLBF" start="0" size="15" access="ReadOnly" />
+      <BitField name="HBFQ" description="Queue Number of HLBF" start="16" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLESTIER" description="EST Interrupt Enable Register" start="+0x0C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IECC" description="Interrupt Enable for Switch List" start="0" size="1" access="Read/Write" />
+      <BitField name="IEBE" description="Interrupt Enable for BTR Error" start="1" size="1" access="Read/Write" />
+      <BitField name="IEHF" description="Interrupt Enable for HLBF" start="2" size="1" access="Read/Write" />
+      <BitField name="IEHS" description="Interrupt Enable for HLBS" start="3" size="1" access="Read/Write" />
+      <BitField name="CGCE" description="Interrupt Enable for CGCE" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLESTGCLCR" description="EST Gate Control List Register" start="+0x0C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRWO" description="Start Read/Write Operation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates the start/progress of a Read/Write operation" start="0x1" />
+      </BitField>
+      <BitField name="R1W0" description="Read 1, Write 0" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Read operation" start="0x1" />
+        <Enum name="B_0x0" description="Write operation." start="0x0" />
+      </BitField>
+      <BitField name="GCRR" description="Gate Control Related Registers" start="2" size="1" access="Read/Write" />
+      <BitField name="DBGM" description="Debug Mode" start="4" size="1" access="Read/Write" />
+      <BitField name="DBGB" description="Debug Mode Bank Select" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bank 0" start="0x0" />
+        <Enum name="B_0x1" description="Bank 1" start="0x1" />
+      </BitField>
+      <BitField name="ADDR" description="Gate Control List Address: " start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0_GCRR__EQUAL_1" description="BTR Low (31:0)" start="0x0" />
+        <Enum name="B_0x1_GCRR__EQUAL_1" description="BTR High (63:31)" start="0x1" />
+        <Enum name="B_0x2_GCRR__EQUAL_1" description="CTR Low (31:0)" start="0x2" />
+        <Enum name="B_0x3_GCRR__EQUAL_1" description="CTR High (39:32)" start="0x3" />
+        <Enum name="B_0x4_GCRR__EQUAL_1" description="TER (30:0)" start="0x4" />
+        <Enum name="B_0x5_GCRR__EQUAL_1" description="LLR (6:0)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLESTGCLDR" description="EST Gate Control List Data Register" start="+0x0C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GCD" description="Gate Control Data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLFPECSR" description="FPE Frame Preemption Control Status Register" start="+0x0C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSZ" description="Additional Fragment Size" start="0" size="2" access="Read/Write" />
+      <BitField name="PEC" description="Preemption Classification" start="8" size="2" access="Read/Write" />
+      <BitField name="HRS" description="Hold/Release Status" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State." start="0x1" />
+        <Enum name="B_0x0" description="Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLFPEAR" description="FPE Frame Preemption Advance Register" start="+0x0C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HADV" description="Hold Advance" start="0" size="16" access="Read/Write" />
+      <BitField name="RADV" description="Release Advance" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0OMR" description="T0 queue 0 operating mode Register" start="+0xD00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTQ" description="Flush Transmit Queue" start="0" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Transmit Store and Forward" start="1" size="1" access="Read/Write" />
+      <BitField name="TXQEN" description="Transmit Queue Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Enable in AV mode" start="0x1" />
+        <Enum name="B_0x2" description="Enabled" start="0x2" />
+      </BitField>
+      <BitField name="TTC" description="Transmit Threshold Control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="32" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+        <Enum name="B_0x4" description="192" start="0x4" />
+        <Enum name="B_0x5" description="256" start="0x5" />
+        <Enum name="B_0x6" description="384" start="0x6" />
+        <Enum name="B_0x7" description="512" start="0x7" />
+      </BitField>
+      <BitField name="TQS" description="Transmit queue size" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0UR" description="T0 queue 0 underflow register" start="+0xD04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFRMCNT" description="Underflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="UFCNTOVF" description="Overflow Bit for Underflow Packet Counter" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ0DR" description="T0 queue 0 debug register" start="+0xD08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXQPAUSED" description="Transmit Queue in Pause" start="0" size="1" access="ReadOnly" />
+      <BitField name="TRCSTS" description="MTL Tx Queue Read Controller Status" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Read state (transferring data to the MAC transmitter)" start="0x1" />
+        <Enum name="B_0x2" description="Waiting for pending Tx Status from the MAC transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the Tx queue because of the Packet Abort request from the MAC" start="0x3" />
+      </BitField>
+      <BitField name="TWCSTS" description="MTL Tx Queue Write Controller Status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXQSTS" description="MTL Tx Queue Not Empty Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="TXSTSFSTS" description="MTL Tx Status FIFO Full Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="PTXQ" description="Number of Packets in the Transmit Queue" start="16" size="3" access="ReadOnly" />
+      <BitField name="STXSTSF" description="Number of Status Words in Tx Status FIFO of Queue" start="20" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ0ESR" description="T0 queue 0 ETS status Register" start="+0xD14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABS" description="Average Bits per Slot" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ0QWR" description="Tx queue 0 quantum weight register" start="+0x0D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISCQW" description="Weights" start="0" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLQ0ICSR" description="Queue 0 interrupt control status Register" start="+0xD2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXUNFIS" description="Transmit Queue Underflow Interrupt Status" start="0" size="1" access="Read/Write" />
+      <BitField name="ABPSIS" description="Average Bits Per Slot Interrupt Status" start="1" size="1" access="Read/Write" />
+      <BitField name="TXUIE" description="Transmit Queue Underflow Interrupt Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="ABPSIE" description="Average Bits Per Slot Interrupt Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="RXOVFIS" description="Receive Queue Overflow Interrupt Status" start="16" size="1" access="Read/Write" />
+      <BitField name="RXOIE" description="Receive Queue Overflow Interrupt Enable" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0OMR" description="R0 queue 0 operating mode register" start="+0xD30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC" description="Receive Queue Threshold Control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64" start="0x0" />
+        <Enum name="B_0x1" description="32" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+      </BitField>
+      <BitField name="FUP" description="Forward Undersized Good Packets" start="3" size="1" access="Read/Write" />
+      <BitField name="FEP" description="Forward Error Packets" start="4" size="1" access="Read/Write" />
+      <BitField name="RSF" description="Receive Queue Store and Forward" start="5" size="1" access="Read/Write" />
+      <BitField name="DIS_TCP_EF" description="Disable Dropping of TCP/IP Checksum Error Packets" start="6" size="1" access="Read/Write" />
+      <BitField name="EHFC" description="Enable Hardware Flow Control" start="7" size="1" access="Read/Write" />
+      <BitField name="RFA" description="Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" start="8" size="3" access="Read/Write" />
+      <BitField name="RFD" description="Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Full minus 1 Kbyte" start="0x0" />
+        <Enum name="B_0x1" description="Full minus 1.5 Kbyte" start="0x1" />
+      </BitField>
+      <BitField name="RQS" description="Receive Queue Size" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0MPOCR" description="R0 queue 0 missed packet and overflow counter register" start="+0xD34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVFPKTCNT" description="Overflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="OVFCNTOVF" description="Overflow Counter Overflow Bit" start="11" size="1" access="Read/Write" />
+      <BitField name="MISPKTCNT" description="Missed Packet Counter" start="16" size="11" access="Read/Write" />
+      <BitField name="MISCNTOVF" description="Missed Packet Counter Overflow Bit" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ0DR" description="R0 queue 0 debug register" start="+0xD38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWCSTS" description="MTL Rx Queue Write Controller Active Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RRCSTS" description="MTL Rx Queue Read Controller State" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Reading packet data" start="0x1" />
+        <Enum name="B_0x2" description="Reading packet status (or timestamp)" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the packet data and status" start="0x3" />
+      </BitField>
+      <BitField name="RXQSTS" description="MTL Rx Queue Fill-Level Status" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx queue empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue fill-level below flow-control deactivate threshold" start="0x1" />
+        <Enum name="B_0x2" description="Rx queue fill-level above flow-control activate threshold" start="0x2" />
+        <Enum name="B_0x3" description="Rx queue full" start="0x3" />
+      </BitField>
+      <BitField name="PRXQ" description="Number of Packets in Receive Queue" start="16" size="14" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQ0CR" description="R0 queue 0 control register" start="+0xD3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ_WEGT" description="Receive Queue Weight" start="0" size="3" access="Read/Write" />
+      <BitField name="RXQ_FRM_ARBIT" description="Receive Queue Packet Arbitration" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1OMR" description="T1 queue 1 operating mode Register" start="+0xD40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTQ" description="Flush Transmit Queue" start="0" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Transmit Store and Forward" start="1" size="1" access="Read/Write" />
+      <BitField name="TXQEN" description="Transmit Queue Enable" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Not enabled" start="0x0" />
+        <Enum name="B_0x1" description="Enable in AV mode" start="0x1" />
+        <Enum name="B_0x2" description="Enabled" start="0x2" />
+      </BitField>
+      <BitField name="TTC" description="Transmit Threshold Control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="32" start="0x0" />
+        <Enum name="B_0x1" description="64" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+        <Enum name="B_0x4" description="192" start="0x4" />
+        <Enum name="B_0x5" description="256" start="0x5" />
+        <Enum name="B_0x6" description="384" start="0x6" />
+        <Enum name="B_0x7" description="512" start="0x7" />
+      </BitField>
+      <BitField name="TQS" description="Transmit queue size" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1UR" description="T1 queue 1 underflow register" start="+0xD44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFRMCNT" description="Underflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="UFCNTOVF" description="Overflow Bit for Underflow Packet Counter" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1DR" description="T1 queue 1 debug register" start="+0xD48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXQPAUSED" description="Transmit Queue in Pause" start="0" size="1" access="ReadOnly" />
+      <BitField name="TRCSTS" description="MTL Tx Queue Read Controller Status" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Read state (transferring data to the MAC transmitter)" start="0x1" />
+        <Enum name="B_0x2" description="Waiting for pending Tx Status from the MAC transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the Tx queue because of the Packet Abort request from the MAC" start="0x3" />
+      </BitField>
+      <BitField name="TWCSTS" description="MTL Tx Queue Write Controller Status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXQSTS" description="MTL Tx Queue Not Empty Status" start="4" size="1" access="ReadOnly" />
+      <BitField name="TXSTSFSTS" description="MTL Tx Status FIFO Full Status" start="5" size="1" access="ReadOnly" />
+      <BitField name="PTXQ" description="Number of Packets in the Transmit Queue" start="16" size="3" access="ReadOnly" />
+      <BitField name="STXSTSF" description="Number of Status Words in Tx Status FIFO of Queue" start="20" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ1ECR" description="Tx queue 1 ETS control Register" start="+0x0D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVALG" description="AV Algorithm" start="2" size="1" access="Read/Write" />
+      <BitField name="CC" description="Credit Control" start="3" size="1" access="Read/Write" />
+      <BitField name="SLC" description="Slot Count" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 Slot" start="0x0" />
+        <Enum name="B_0x1" description="2 Slots" start="0x1" />
+        <Enum name="B_0x2" description="4 Slots" start="0x2" />
+        <Enum name="B_0x3" description="8 Slots" start="0x3" />
+        <Enum name="B_0x4" description="16 Slots" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="ETH_MTLTXQ1ESR" description="T1 queue 1 ETS status Register" start="+0xD54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABS" description="Average Bits per Slot" start="0" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLTXQ1QWR" description="Tx queue 1 quantum weight register" start="+0x0D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISCQW" description="IdleSlopeCredit or Weights" start="0" size="14" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1SSCR" description="Tx queue 1 send slope credit Register" start="+0x0D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SSC" description="sendSlopeCredit Value" start="0" size="14" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1HCR" description="Tx Queue 1 hiCredit register" start="+0x0D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HC" description="hiCredit Value" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLTXQ1LCR" description="Tx queue 1 loCredit register" start="+0x0D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LC" description="loCredit Value" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLQ1ICSR" description="Queue 1 interrupt control status Register" start="+0xD6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXUNFIS" description="Transmit Queue Underflow Interrupt Status" start="0" size="1" access="Read/Write" />
+      <BitField name="ABPSIS" description="Average Bits Per Slot Interrupt Status" start="1" size="1" access="Read/Write" />
+      <BitField name="TXUIE" description="Transmit Queue Underflow Interrupt Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="ABPSIE" description="Average Bits Per Slot Interrupt Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="RXOVFIS" description="Receive Queue Overflow Interrupt Status" start="16" size="1" access="Read/Write" />
+      <BitField name="RXOIE" description="Receive Queue Overflow Interrupt Enable" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1OMR" description="R1 queue 1 operating mode register" start="+0xD70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC" description="Receive Queue Threshold Control" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64" start="0x0" />
+        <Enum name="B_0x1" description="32" start="0x1" />
+        <Enum name="B_0x2" description="96" start="0x2" />
+        <Enum name="B_0x3" description="128" start="0x3" />
+      </BitField>
+      <BitField name="FUP" description="Forward Undersized Good Packets" start="3" size="1" access="Read/Write" />
+      <BitField name="FEP" description="Forward Error Packets" start="4" size="1" access="Read/Write" />
+      <BitField name="RSF" description="Receive Queue Store and Forward" start="5" size="1" access="Read/Write" />
+      <BitField name="DIS_TCP_EF" description="Disable Dropping of TCP/IP Checksum Error Packets" start="6" size="1" access="Read/Write" />
+      <BitField name="EHFC" description="Enable Hardware Flow Control" start="7" size="1" access="Read/Write" />
+      <BitField name="RFA" description="Threshold for Activating Flow Control (in Half-duplex and Full-duplex)" start="8" size="3" access="Read/Write" />
+      <BitField name="RFD" description="Threshold for Deactivating Flow Control (in Half-duplex and Full-duplex modes)" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Full minus 1 Kbyte" start="0x0" />
+        <Enum name="B_0x1" description="Full minus 1.5 Kbyte" start="0x1" />
+      </BitField>
+      <BitField name="RQS" description="Receive Queue Size" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1MPOCR" description="R1 queue 1 missed packet and overflow counter register" start="+0xD74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVFPKTCNT" description="Overflow Packet Counter" start="0" size="11" access="Read/Write" />
+      <BitField name="OVFCNTOVF" description="Overflow Counter Overflow Bit" start="11" size="1" access="Read/Write" />
+      <BitField name="MISPKTCNT" description="Missed Packet Counter" start="16" size="11" access="Read/Write" />
+      <BitField name="MISCNTOVF" description="Missed Packet Counter Overflow Bit" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_MTLRXQ1DR" description="R1 queue 1 debug register" start="+0xD78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWCSTS" description="MTL Rx Queue Write Controller Active Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="RRCSTS" description="MTL Rx Queue Read Controller State" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state" start="0x0" />
+        <Enum name="B_0x1" description="Reading packet data" start="0x1" />
+        <Enum name="B_0x2" description="Reading packet status (or timestamp)" start="0x2" />
+        <Enum name="B_0x3" description="Flushing the packet data and status" start="0x3" />
+      </BitField>
+      <BitField name="RXQSTS" description="MTL Rx Queue Fill-Level Status" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx queue empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx queue fill-level below flow-control deactivate threshold" start="0x1" />
+        <Enum name="B_0x2" description="Rx queue fill-level above flow-control activate threshold" start="0x2" />
+        <Enum name="B_0x3" description="Rx queue full" start="0x3" />
+      </BitField>
+      <BitField name="PRXQ" description="Number of Packets in Receive Queue" start="16" size="14" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_MTLRXQ1CR" description="R1 queue 1 control register" start="+0xD7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQ_WEGT" description="Receive Queue Weight" start="0" size="3" access="Read/Write" />
+      <BitField name="RXQ_FRM_ARBIT" description="Receive Queue Packet Arbitration" start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAMR" description="DMA mode register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWR" description="Software Reset" start="0" size="1" access="Read/Write" />
+      <BitField name="TAA" description="Transmit Arbitration Algorithm " start="2" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="Fixed priority. In fixed priority, Channel 0 has the lowest priority and the last channel has the highest priority." start="0x0" />
+        <Enum name="B_0x1" description="Weighted Strict priority (WSP)" start="0x1" />
+        <Enum name="B_0x2" description="Weighted Round-Robin (WRR)" start="0x2" />
+      </BitField>
+      <BitField name="DSPW" description="Descriptor Posted Write" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The descriptor writes are always non-posted." start="0x0" />
+        <Enum name="B_0x1" description="The descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor. Otherwise, the descriptor writes are always posted." start="0x1" />
+      </BitField>
+      <BitField name="TXPR" description="Transmit priority" start="11" size="1" access="Read/Write" />
+      <BitField name="INTM" description="Interrupt Mode" start="16" size="2" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMASBMR" description="System bus mode register" start="+0x1004" size="4" reset_value="0x01010000" reset_mask="0xFFFFFFFF">
+      <BitField name="FB" description="Fixed Burst Length" start="0" size="1" access="Read/Write" />
+      <BitField name="BLEN4" description="AXI Burst Length 4" start="1" size="1" access="Read/Write" />
+      <BitField name="BLEN8" description="AXI Burst Length 8" start="2" size="1" access="Read/Write" />
+      <BitField name="BLEN16" description="AXI Burst Length 16" start="3" size="1" access="Read/Write" />
+      <BitField name="BLEN32" description="AXI Burst Length 32" start="4" size="1" access="Read/Write" />
+      <BitField name="BLEN64" description="AXI Burst Length 64" start="5" size="1" access="Read/Write" />
+      <BitField name="BLEN128" description="AXI Burst Length 128" start="6" size="1" access="Read/Write" />
+      <BitField name="BLEN256" description="AXI Burst Length 256" start="7" size="1" access="Read/Write" />
+      <BitField name="AALE" description="Automatic AXI LPI enable" start="10" size="1" access="Read/Write" />
+      <BitField name="AAL" description="Address-Aligned Beats" start="12" size="1" access="Read/Write" />
+      <BitField name="ONEKBBE" description="1 Kbyte Boundary Crossing Enable for the AXI Master" start="13" size="1" access="Read/Write" />
+      <BitField name="RD_OSR_LMT" description="AXI Maximum Read Outstanding Request Limit" start="16" size="2" access="Read/Write" />
+      <BitField name="WR_OSR_LMT" description="AXI Maximum Write Outstanding Request Limit" start="24" size="2" access="Read/Write" />
+      <BitField name="LPI_XIT_PKT" description="Unlock on Magic Packet or Remote wake-up packet" start="30" size="1" access="Read/Write" />
+      <BitField name="EN_LPI" description="Enable Low Power Interface (LPI)" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAISR" description="Interrupt status register" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DC0IS" description="DMA Channel 0 Interrupt Status" start="0" size="1" access="ReadOnly" />
+      <BitField name="DC1IS" description="DMA Channel 1 Interrupt Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="MTLIS" description="MTL Interrupt Status" start="16" size="1" access="ReadOnly" />
+      <BitField name="MACIS" description="MAC Interrupt Status" start="17" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMADSR" description="Debug status register" start="+0x100C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXWHSTS" description="AXI Master Write Channel" start="0" size="1" access="ReadOnly" />
+      <BitField name="AXRHSTS" description="AXI Master Read Channel Status" start="1" size="1" access="ReadOnly" />
+      <BitField name="RPS0" description="DMA Channel 0 Receive Process State" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Stopped (Reset or Stop Receive Command issued)" start="0x0" />
+        <Enum name="B_0x1" description="Running (Fetching Rx Transfer Descriptor)" start="0x1" />
+        <Enum name="B_0x3" description="Running (Waiting for Rx packet)" start="0x3" />
+        <Enum name="B_0x4" description="Suspended (Rx Descriptor Unavailable)" start="0x4" />
+        <Enum name="B_0x5" description="Running (Closing the Rx Descriptor)" start="0x5" />
+        <Enum name="B_0x6" description="Timestamp write state" start="0x6" />
+        <Enum name="B_0x7" description="Running (Transferring the received packet data from the Rx buffer to the system memory)" start="0x7" />
+      </BitField>
+      <BitField name="TPS0" description="DMA Channel 0 Transmit Process State" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Stopped (Reset or Stop Transmit Command issued)" start="0x0" />
+        <Enum name="B_0x1" description="Running (Fetching Tx Transfer Descriptor)" start="0x1" />
+        <Enum name="B_0x2" description="Running (Waiting for status)" start="0x2" />
+        <Enum name="B_0x3" description="Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))" start="0x3" />
+        <Enum name="B_0x4" description="Timestamp write state" start="0x4" />
+        <Enum name="B_0x6" description="Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)" start="0x6" />
+        <Enum name="B_0x7" description="Running (Closing Tx Descriptor)" start="0x7" />
+      </BitField>
+      <BitField name="RPS1" description="DMA Channel 1 Receive Process State" start="16" size="4" access="ReadOnly" />
+      <BitField name="TPS1" description="DMA Channel 1 Transmit Process State" start="20" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAA4TXACR" description="AXI4 transmit channel ACE control register" start="+0x1020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRC" description="Transmit DMA Read Descriptor Cache Control" start="0" size="4" access="Read/Write" />
+      <BitField name="TEC" description="Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" start="8" size="4" access="Read/Write" />
+      <BitField name="THC" description="Transmit DMA First Packet Buffer or TSO Header Cache Control" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAA4RXACR" description="AXI4 receive channel ACE control register" start="+0x1024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDWC" description="Receive DMA Write Descriptor Cache Control" start="0" size="4" access="Read/Write" />
+      <BitField name="RPC" description="Receive DMA Payload Cache Control" start="8" size="4" access="Read/Write" />
+      <BitField name="RHC" description="Receive DMA Header Cache Control" start="16" size="4" access="Read/Write" />
+      <BitField name="RDC" description="Receive DMA Buffer Cache Control" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAA4DACR" description="AXI4 descriptor ACE control register" start="+0x1028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDWC" description="Transmit DMA Write Descriptor Cache control " start="0" size="4" access="Read/Write" />
+      <BitField name="TDWD" description="Transmit DMA Write Descriptor Domain control " start="4" size="2" access="Read/Write" />
+      <BitField name="RDRC" description="Receive DMA Read Descriptor Cache control " start="8" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMALPIEI" description="AXI4 LPI Entry Interval register" start="+0x1040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPIEI" description="LPI Entry Interval " start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMATBSCTRL0R" description="DMA TBS control register 0" start="+0x1050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTOV" description="Fetch time offset valid" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Fetch time offset invalid" start="0x0" />
+        <Enum name="B_0x1" description="Fetch time offset valid" start="0x1" />
+      </BitField>
+      <BitField name="FGOS" description="Fetch GSN offset" start="4" size="3" access="Read/Write" />
+      <BitField name="FTOS" description="Fetch time offset" start="8" size="24" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0CR" description="Channel 0 control register" start="+0x1100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSS" description="Maximum Segment Size" start="0" size="14" access="Read/Write" />
+      <BitField name="PBLX8" description="8xPBL mode" start="16" size="1" access="Read/Write" />
+      <BitField name="DSL" description="Descriptor Skip Length" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXCR" description="Channel 0 transmit control register" start="+0x1104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ST" description="Start or Stop Transmission Command" start="0" size="1" access="Read/Write" />
+      <BitField name="TCW" description="Transmit Channel Weight " start="1" size="3" access="ReadOnly" />
+      <BitField name="OSF" description="Operate on Second Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="TSE" description="TCP Segmentation Enabled" start="12" size="1" access="Read/Write" />
+      <BitField name="IPBL" description="Ignore PBL Requirement" start="15" size="1" access="Read/Write" />
+      <BitField name="TXPBL" description="Transmit Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="TQOS" description="Transmit QOS" start="24" size="4" access="Read/Write" />
+      <BitField name="EDSE" description="Enhanced Descriptor Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXCR" description="Channel 0 receive control register" start="+0x1108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SR" description="Start or Stop Receive" start="0" size="1" access="Read/Write" />
+      <BitField name="RBSZ" description="Receive Buffer size" start="1" size="14" access="Read/Write" />
+      <BitField name="RXPBL" description="Receive Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="RQOS" description="Rx AXI4 QOS." start="24" size="4" access="Read/Write" />
+      <BitField name="RPF" description="DMA Rx Channel x Packet Flush" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXDLAR" description="Channel 0 T0 descriptor list address register" start="+0x1114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDESLA" description="Start of Transmit List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXDLAR" description="Channel 0 Rx descriptor list address register" start="+0x111C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDESLA" description="Start of Receive List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXDTPR" description="Channel 0 T0 descriptor tail pointer register" start="+0x1120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDT" description="Transmit Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXDTPR" description="Channel 0 R0 descriptor tail pointer register" start="+0x1128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDT" description="Receive Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0TXRLR" description="Channel 0 T0 descriptor ring length register" start="+0x112C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRL" description="Transmit Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXRLR" description="Channel 0 R0 descriptor ring length register" start="+0x1130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDRL" description="Receive Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+      <BitField name="ARBS" description="Alternate Receive Buffer Size" start="17" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0IER" description="Channel 0 interrupt enable register" start="+0x1134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmit Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TXSE" description="Transmit Stopped Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TBUE" description="Transmit Buffer Unavailable Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="RIE" description="Receive Interrupt Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="RBUE" description="Receive Buffer Unavailable Enable" start="7" size="1" access="Read/Write" />
+      <BitField name="RSE" description="Receive Stopped Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="RWTE" description="Receive Watchdog Timeout Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="ETIE" description="Early Transmit Interrupt Enable" start="10" size="1" access="Read/Write" />
+      <BitField name="ERIE" description="Early Receive Interrupt Enable" start="11" size="1" access="Read/Write" />
+      <BitField name="FBEE" description="Fatal Bus Error Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CDEE" description="Context Descriptor Error Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="AIE" description="Abnormal Interrupt Summary Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="NIE" description="Normal Interrupt Summary Enable" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC0RXIWTR" description="Channel 0 R0 interrupt watchdog timer register" start="+0x1138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWT" description="Receive Interrupt Watchdog Timer Count" start="0" size="8" access="Read/Write" />
+      <BitField name="RWTU" description="Receive Interrupt Watchdog Timer Count Units" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="256" start="0x0" />
+        <Enum name="B_0x1" description="512" start="0x1" />
+        <Enum name="B_0x2" description="1024" start="0x2" />
+        <Enum name="B_0x3" description="2048" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_DMAC0SFCSR" description="Channel 0 slot function control status register" start="+0x113C" size="4" reset_value="0x000007C0" reset_mask="0xFFFFFFFF">
+      <BitField name="ESC" description="Enable Slot Comparison" start="0" size="1" access="Read/Write" />
+      <BitField name="ASC" description="Advance Slot Check" start="1" size="1" access="Read/Write" />
+      <BitField name="SIV" description="Slot Interval Value" start="4" size="12" access="Read/Write" />
+      <BitField name="RSN" description="Reference Slot Number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CATXDR" description="Channel 0 current application transmit descriptor register" start="+0x1144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTDESAPTR" description="Application Transmit Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CARXDR" description="Channel 0 current application receive descriptor register" start="+0x114C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRDESAPTR" description="Application Receive Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CATXBR" description="Channel 0 current application transmit buffer register" start="+0x1154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTBUFAPTR" description="Application Transmit Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0CARXBR" description="Channel 0 current application receive buffer register" start="+0x115C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRBUFAPTR" description="Application Receive Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0SR" description="Channel 0 status register" start="+0x1160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI" description="Transmit Interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="TPS" description="Transmit Process Stopped" start="1" size="1" access="Read/Write" />
+      <BitField name="TBU" description="Transmit Buffer Unavailable" start="2" size="1" access="Read/Write" />
+      <BitField name="RI" description="Receive Interrupt" start="6" size="1" access="Read/Write" />
+      <BitField name="RBU" description="Receive Buffer Unavailable" start="7" size="1" access="Read/Write" />
+      <BitField name="RPS" description="Receive Process Stopped" start="8" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="9" size="1" access="Read/Write" />
+      <BitField name="ETI" description="Early Transmit Interrupt" start="10" size="1" access="Read/Write" />
+      <BitField name="ERI" description="Early Receive Interrupt" start="11" size="1" access="Read/Write" />
+      <BitField name="FBE" description="Fatal Bus Error" start="12" size="1" access="Read/Write" />
+      <BitField name="CDE" description="Context Descriptor Error" start="13" size="1" access="Read/Write" />
+      <BitField name="AIS" description="Abnormal Interrupt Summary" start="14" size="1" access="Read/Write" />
+      <BitField name="NIS" description="Normal Interrupt Summary" start="15" size="1" access="Read/Write" />
+      <BitField name="TEB" description="Tx DMA Error Bits " start="16" size="3" access="ReadOnly" />
+      <BitField name="REB" description="Rx DMA Error Bits" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC0MFCR" description="Channel 0 missed frame count register" start="+0x1164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MFC" description="Dropped Packet Counters" start="0" size="11" access="Read/Write" />
+      <BitField name="MFCO" description="Overflow status of the MFC Counter" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1CR" description="Channel 1 control register" start="+0x1180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSS" description="Maximum Segment Size" start="0" size="14" access="Read/Write" />
+      <BitField name="PBLX8" description="8xPBL mode" start="16" size="1" access="Read/Write" />
+      <BitField name="DSL" description="Descriptor Skip Length" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXCR" description="Channel 1 transmit control register" start="+0x1184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ST" description="Start or Stop Transmission Command" start="0" size="1" access="Read/Write" />
+      <BitField name="TCW" description="Transmit Channel Weight " start="1" size="3" access="ReadOnly" />
+      <BitField name="OSF" description="Operate on Second Packet" start="4" size="1" access="Read/Write" />
+      <BitField name="TSE" description="TCP Segmentation Enabled" start="12" size="1" access="Read/Write" />
+      <BitField name="IPBL" description="Ignore PBL Requirement" start="15" size="1" access="Read/Write" />
+      <BitField name="TXPBL" description="Transmit Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="TQOS" description="Transmit QOS" start="24" size="4" access="Read/Write" />
+      <BitField name="EDSE" description="Enhanced Descriptor Enable" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXCR" description="Channel 1 receive control register" start="+0x1188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SR" description="Start or Stop Receive" start="0" size="1" access="Read/Write" />
+      <BitField name="RBSZ" description="Receive Buffer size" start="1" size="14" access="Read/Write" />
+      <BitField name="RXPBL" description="Receive Programmable Burst Length" start="16" size="6" access="Read/Write" />
+      <BitField name="RQOS" description="Rx AXI4 QOS." start="24" size="4" access="Read/Write" />
+      <BitField name="RPF" description="DMA Rx Channel x Packet Flush" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXDLAR" description="Channel 1 T1 descriptor list address register" start="+0x1194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDESLA" description="Start of Transmit List" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXDTPR" description="Channel 1 T1 descriptor tail pointer register" start="+0x11A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDT" description="Transmit Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXDTPR" description="Channel 1 R1 descriptor tail pointer register" start="+0x11A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDT" description="Receive Descriptor Tail Pointer" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1TXRLR" description="Channel 1 T1 descriptor ring length register" start="+0x11AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRL" description="Transmit Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXRLR" description="Channel 1 R1 descriptor ring length register" start="+0x11B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDRL" description="Receive Descriptor Ring Length" start="0" size="10" access="Read/Write" />
+      <BitField name="ARBS" description="Alternate Receive Buffer Size" start="17" size="7" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1IER" description="Channel 1 interrupt enable register" start="+0x11B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmit Interrupt Enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TXSE" description="Transmit Stopped Enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TBUE" description="Transmit Buffer Unavailable Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="RIE" description="Receive Interrupt Enable" start="6" size="1" access="Read/Write" />
+      <BitField name="RBUE" description="Receive Buffer Unavailable Enable" start="7" size="1" access="Read/Write" />
+      <BitField name="RSE" description="Receive Stopped Enable" start="8" size="1" access="Read/Write" />
+      <BitField name="RWTE" description="Receive Watchdog Timeout Enable" start="9" size="1" access="Read/Write" />
+      <BitField name="ETIE" description="Early Transmit Interrupt Enable" start="10" size="1" access="Read/Write" />
+      <BitField name="ERIE" description="Early Receive Interrupt Enable" start="11" size="1" access="Read/Write" />
+      <BitField name="FBEE" description="Fatal Bus Error Enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CDEE" description="Context Descriptor Error Enable" start="13" size="1" access="Read/Write" />
+      <BitField name="AIE" description="Abnormal Interrupt Summary Enable" start="14" size="1" access="Read/Write" />
+      <BitField name="NIE" description="Normal Interrupt Summary Enable" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ETH_DMAC1RXIWTR" description="Channel 1 R1 interrupt watchdog timer register" start="+0x11B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWT" description="Receive Interrupt Watchdog Timer Count" start="0" size="8" access="Read/Write" />
+      <BitField name="RWTU" description="Receive Interrupt Watchdog Timer Count Units" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="256" start="0x0" />
+        <Enum name="B_0x1" description="512" start="0x1" />
+        <Enum name="B_0x2" description="1024" start="0x2" />
+        <Enum name="B_0x3" description="2048" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="ETH_DMAC1SFCSR" description="Channel 1 slot function control status register" start="+0x11BC" size="4" reset_value="0x000007C0" reset_mask="0xFFFFFFFF">
+      <BitField name="ESC" description="Enable Slot Comparison" start="0" size="1" access="Read/Write" />
+      <BitField name="ASC" description="Advance Slot Check" start="1" size="1" access="Read/Write" />
+      <BitField name="SIV" description="Slot Interval Value" start="4" size="12" access="Read/Write" />
+      <BitField name="RSN" description="Reference Slot Number" start="16" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CATXDR" description="Channel 1 current application transmit descriptor register" start="+0x11C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTDESAPTR" description="Application Transmit Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CARXDR" description="Channel 1 current application receive descriptor register" start="+0x11CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRDESAPTR" description="Application Receive Descriptor Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CATXBR" description="Channel 1 current application transmit buffer register" start="+0x11D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTBUFAPTR" description="Application Transmit Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1CARXBR" description="Channel 1 current application receive buffer register" start="+0x11DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRBUFAPTR" description="Application Receive Buffer Address Pointer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1SR" description="Channel 1 status register" start="+0x11E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI" description="Transmit Interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="TPS" description="Transmit Process Stopped" start="1" size="1" access="Read/Write" />
+      <BitField name="TBU" description="Transmit Buffer Unavailable" start="2" size="1" access="Read/Write" />
+      <BitField name="RI" description="Receive Interrupt" start="6" size="1" access="Read/Write" />
+      <BitField name="RBU" description="Receive Buffer Unavailable" start="7" size="1" access="Read/Write" />
+      <BitField name="RPS" description="Receive Process Stopped" start="8" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="9" size="1" access="Read/Write" />
+      <BitField name="ETI" description="Early Transmit Interrupt" start="10" size="1" access="Read/Write" />
+      <BitField name="ERI" description="Early Receive Interrupt" start="11" size="1" access="Read/Write" />
+      <BitField name="FBE" description="Fatal Bus Error" start="12" size="1" access="Read/Write" />
+      <BitField name="CDE" description="Context Descriptor Error" start="13" size="1" access="Read/Write" />
+      <BitField name="AIS" description="Abnormal Interrupt Summary" start="14" size="1" access="Read/Write" />
+      <BitField name="NIS" description="Normal Interrupt Summary" start="15" size="1" access="Read/Write" />
+      <BitField name="TEB" description="Tx DMA Error Bits " start="16" size="3" access="ReadOnly" />
+      <BitField name="REB" description="Rx DMA Error Bits" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="ETH_DMAC1MFCR" description="Channel 1 missed frame count register" start="+0x11E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MFC" description="Dropped Packet Counters" start="0" size="11" access="Read/Write" />
+      <BitField name="MFCO" description="Overflow status of the MFC Counter" start="15" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EXTI" description="Extended interrupts and event controller" start="0x46025000">
+    <Register name="EXTI_RTSR1" description="EXTI rising trigger selection register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT0" description="Rising trigger event configuration bit of configurable event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="RT1" description="Rising trigger event configuration bit of configurable event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="RT2" description="Rising trigger event configuration bit of configurable event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="RT3" description="Rising trigger event configuration bit of configurable event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="RT4" description="Rising trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="RT5" description="Rising trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="RT6" description="Rising trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="RT7" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="RT8" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="RT9" description="Rising trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="RT10" description="Rising trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="RT11" description="Rising trigger event configuration bit of configurable event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="RT12" description="Rising trigger event configuration bit of configurable event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="RT13" description="Rising trigger event configuration bit of configurable event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="RT14" description="Rising trigger event configuration bit of configurable event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="RT15" description="Rising trigger event configuration bit of configurable event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="RT20" description="Rising trigger event configuration bit of configurable event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT21" description="Rising trigger event configuration bit of configurable event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR1" description="EXTI falling trigger selection register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT0" description="Falling trigger event configuration bit of configurable event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="FT1" description="Falling trigger event configuration bit of configurable event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="FT2" description="Falling trigger event configuration bit of configurable event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="FT3" description="Falling trigger event configuration bit of configurable event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="FT4" description="Falling trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="FT5" description="Falling trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="FT6" description="Falling trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="FT7" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="FT8" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="FT9" description="Falling trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="FT10" description="Falling trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="FT11" description="Falling trigger event configuration bit of configurable event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="FT12" description="Falling trigger event configuration bit of configurable event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="FT13" description="Falling trigger event configuration bit of configurable event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="FT14" description="Falling trigger event configuration bit of configurable event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="FT15" description="Falling trigger event configuration bit of configurable event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="FT20" description="Falling trigger event configuration bit of configurable event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line." start="0x1" />
+      </BitField>
+      <BitField name="FT21" description="Falling trigger event configuration bit of configurable event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER1" description="EXTI software interrupt event register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI0" description="Software interrupt on event x" start="0" size="1" access="Read/Write" />
+      <BitField name="SWI1" description="Software interrupt on event x" start="1" size="1" access="Read/Write" />
+      <BitField name="SWI2" description="Software interrupt on event x" start="2" size="1" access="Read/Write" />
+      <BitField name="SWI3" description="Software interrupt on event x" start="3" size="1" access="Read/Write" />
+      <BitField name="SWI4" description="Software interrupt on event x" start="4" size="1" access="Read/Write" />
+      <BitField name="SWI5" description="Software interrupt on event x" start="5" size="1" access="Read/Write" />
+      <BitField name="SWI6" description="Software interrupt on event x" start="6" size="1" access="Read/Write" />
+      <BitField name="SWI7" description="Software interrupt on event x" start="7" size="1" access="Read/Write" />
+      <BitField name="SWI8" description="Software interrupt on event x" start="8" size="1" access="Read/Write" />
+      <BitField name="SWI9" description="Software interrupt on event x" start="9" size="1" access="Read/Write" />
+      <BitField name="SWI10" description="Software interrupt on event x" start="10" size="1" access="Read/Write" />
+      <BitField name="SWI11" description="Software interrupt on event x" start="11" size="1" access="Read/Write" />
+      <BitField name="SWI12" description="Software interrupt on event x" start="12" size="1" access="Read/Write" />
+      <BitField name="SWI13" description="Software interrupt on event x" start="13" size="1" access="Read/Write" />
+      <BitField name="SWI14" description="Software interrupt on event x" start="14" size="1" access="Read/Write" />
+      <BitField name="SWI15" description="Software interrupt on event x" start="15" size="1" access="Read/Write" />
+      <BitField name="SWI20" description="Software interrupt on event x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI21" description="Software interrupt on event x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR1" description="EXTI rising edge pending register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF0" description="Configurable event input x rising edge pending bit" start="0" size="1" access="Read/Write" />
+      <BitField name="RPIF1" description="Configurable event input x rising edge pending bit" start="1" size="1" access="Read/Write" />
+      <BitField name="RPIF2" description="Configurable event input x rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="RPIF3" description="Configurable event input x rising edge pending bit" start="3" size="1" access="Read/Write" />
+      <BitField name="RPIF4" description="Configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write" />
+      <BitField name="RPIF5" description="Configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write" />
+      <BitField name="RPIF6" description="Configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write" />
+      <BitField name="RPIF7" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="RPIF8" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="RPIF9" description="Configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write" />
+      <BitField name="RPIF10" description="Configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write" />
+      <BitField name="RPIF11" description="Configurable event input x rising edge pending bit" start="11" size="1" access="Read/Write" />
+      <BitField name="RPIF12" description="Configurable event input x rising edge pending bit" start="12" size="1" access="Read/Write" />
+      <BitField name="RPIF13" description="Configurable event input x rising edge pending bit" start="13" size="1" access="Read/Write" />
+      <BitField name="RPIF14" description="Configurable event input x rising edge pending bit" start="14" size="1" access="Read/Write" />
+      <BitField name="RPIF15" description="Configurable event input x rising edge pending bit" start="15" size="1" access="Read/Write" />
+      <BitField name="RPIF20" description="Configurable event input x rising edge pending bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF21" description="Configurable event input x rising edge pending bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR1" description="EXTI falling edge pending register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF0" description="Configurable event input x rising edge pending bit" start="0" size="1" access="Read/Write" />
+      <BitField name="FPIF1" description="Configurable event input x rising edge pending bit" start="1" size="1" access="Read/Write" />
+      <BitField name="FPIF2" description="Configurable event input x rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="FPIF3" description="Configurable event input x rising edge pending bit" start="3" size="1" access="Read/Write" />
+      <BitField name="FPIF4" description="Configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write" />
+      <BitField name="FPIF5" description="Configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write" />
+      <BitField name="FPIF6" description="Configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write" />
+      <BitField name="FPIF7" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="FPIF8" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="FPIF9" description="Configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write" />
+      <BitField name="FPIF10" description="Configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write" />
+      <BitField name="FPIF11" description="Configurable event input x rising edge pending bit" start="11" size="1" access="Read/Write" />
+      <BitField name="FPIF12" description="Configurable event input x rising edge pending bit" start="12" size="1" access="Read/Write" />
+      <BitField name="FPIF13" description="Configurable event input x rising edge pending bit" start="13" size="1" access="Read/Write" />
+      <BitField name="FPIF14" description="Configurable event input x rising edge pending bit" start="14" size="1" access="Read/Write" />
+      <BitField name="FPIF15" description="Configurable event input x rising edge pending bit" start="15" size="1" access="Read/Write" />
+      <BitField name="FPIF20" description="configurable event input x falling edge pending bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF21" description="configurable event input x falling edge pending bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR1" description="EXTI security configuration register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC1" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC2" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC3" description="Security enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="SEC4" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC5" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC6" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC7" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC8" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC9" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC10" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC11" description="Security enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="SEC12" description="Security enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="SEC13" description="Security enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="SEC14" description="Security enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="SEC15" description="Security enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="SEC17" description="Security enable on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC18" description="Security enable on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC19" description="Security enable on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC20" description="Security enable on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC21" description="Security enable on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC22" description="Security enable on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC23" description="Security enable on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC24" description="Security enable on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC25" description="Security enable on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC26" description="Security enable on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC27" description="Security enable on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC28" description="Security enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC29" description="Security enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC30" description="Security enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC31" description="Security enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR1" description="EXTI privilege configuration register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV1" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV2" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV3" description="Privilege enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="PRIV4" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV5" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV6" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV7" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV8" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV9" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV10" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV11" description="Privilege enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="PRIV12" description="Privilege enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="PRIV13" description="Privilege enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="PRIV14" description="Privilege enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="PRIV15" description="Privilege enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="PRIV17" description="Privilege enable on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV18" description="Privilege enable on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV19" description="Privilege enable on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV20" description="Privilege enable on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV21" description="Privilege enable on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV22" description="Privilege enable on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV23" description="Privilege enable on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV24" description="Privilege enable on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV25" description="Privilege enable on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV26" description="Privilege enable on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV27" description="Privilege enable on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV28" description="Privilege enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV29" description="Privilege enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV30" description="Privilege enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV31" description="Privilege enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RTSR2" description="EXTI rising trigger selection register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT39" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="RT40" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="RT51" description="Rising trigger event configuration bit of configurable event input 51" start="19" size="1" access="Read/Write" />
+      <BitField name="RT54" description="Rising trigger event configuration bit of configurable event input 54" start="22" size="1" access="Read/Write" />
+      <BitField name="RT56" description="Rising trigger event configuration bit of configurable event input 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and Interrupt) for input line x" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and Interrupt) for input line x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR2" description="EXTI falling trigger selection register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT39" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="FT40" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="FT51" description="Falling trigger event configuration bit of configurable event input 51" start="19" size="1" access="Read/Write" />
+      <BitField name="FT54" description="Falling trigger event configuration bit of configurable event input 54" start="22" size="1" access="Read/Write" />
+      <BitField name="FT56" description="Falling trigger event configuration bit of configurable event input 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and Interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and Interrupt) for input line." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER2" description="EXTI software interrupt event register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI39" description="Software interrupt on event x" start="7" size="1" access="Read/Write" />
+      <BitField name="SWI40" description="Software interrupt on event x" start="8" size="1" access="Read/Write" />
+      <BitField name="SWI51" description="Software interrupt on event 51" start="19" size="1" access="Read/Write" />
+      <BitField name="SWI54" description="Software interrupt on event 54" start="22" size="1" access="Read/Write" />
+      <BitField name="SWI56" description="Software interrupt on event 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR2" description="EXTI rising edge pending register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF39" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="RPIF40" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="RPIF51" description="Configurable event input 51 rising edge pending bit" start="19" size="1" access="Read/Write" />
+      <BitField name="RPIF54" description="Configurable event input 54 rising edge pending bit" start="22" size="1" access="Read/Write" />
+      <BitField name="RPIF56" description="Configurable event input 56 rising edge pending bit " start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR2" description="EXTI falling edge pending register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF39" description="Configurable event input x falling edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="FPIF40" description="Configurable event input x falling edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="FPIF51" description="Configurable event input 51 falling edge pending bit" start="19" size="1" access="Read/Write" />
+      <BitField name="FPIF54" description="Configurable event input 54 falling edge pending bit" start="22" size="1" access="Read/Write" />
+      <BitField name="FPIF56" description="Configurable event input 56 falling edge pending bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR2" description="EXTI security enable register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC32" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC33" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC34" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC35" description="Security enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="SEC36" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC37" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC38" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC39" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC40" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC41" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC42" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC43" description="Security enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="SEC44" description="Security enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="SEC45" description="Security enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="SEC46" description="Security enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="SEC47" description="Security enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="SEC48" description="Security enable on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="SEC49" description="Security enable on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="SEC50" description="Security enable on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="SEC51" description="Security enable on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="SEC52" description="Security enable on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="SEC53" description="Security enable on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="SEC54" description="Security enable on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="SEC55" description="Security enable on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="SEC56" description="Security enable on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="SEC57" description="Security enable on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="SEC58" description="Security enable on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="SEC60" description="Security enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC61" description="Security enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC62" description="Security enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC63" description="Security enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR2" description="EXTI privilege enable register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV32" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV33" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV34" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV35" description="Privilege enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="PRIV36" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV37" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV38" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV39" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV40" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV41" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV42" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV43" description="Privilege enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="PRIV44" description="Privilege enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="PRIV45" description="Privilege enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="PRIV46" description="Privilege enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="PRIV47" description="Privilege enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="PRIV48" description="Privilege enable on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="PRIV49" description="Privilege enable on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="PRIV50" description="Privilege enable on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="PRIV51" description="Privilege enable on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="PRIV52" description="Privilege enable on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="PRIV53" description="Privilege enable on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="PRIV54" description="Privilege enable on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="PRIV55" description="Privilege enable on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="PRIV56" description="Privilege enable on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="PRIV57" description="Privilege enable on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="PRIV58" description="Privilege enable on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="PRIV60" description="Privilege enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV61" description="Privilege enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV62" description="Privilege enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV63" description="Privilege enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RTSR3" description="EXTI rising trigger selection register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT66" description="Rising trigger event configuration bit of configurable event input 66" start="2" size="1" access="Read/Write" />
+      <BitField name="RT68" description="Rising trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT69" description="Rising trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT70" description="Rising trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT71" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT72" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT73" description="Rising trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT74" description="Rising trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR3" description="EXTI falling trigger selection register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT66" description="Falling trigger event configuration bit of configurable event input 66" start="2" size="1" access="Read/Write" />
+      <BitField name="FT68" description="Falling trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT69" description="Falling trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT70" description="Falling trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT71" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT72" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT73" description="Falling trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT74" description="Falling trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER3" description="EXTI software interrupt event register" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI66" description="Software interrupt on event 66" start="2" size="1" access="Read/Write" />
+      <BitField name="SWI68" description="Software interrupt on event x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI69" description="Software interrupt on event x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI70" description="Software interrupt on event x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI71" description="Software interrupt on event x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI72" description="Software interrupt on event x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI73" description="Software interrupt on event x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI74" description="Software interrupt on event x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR3" description="EXTI rising edge pending register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF66" description="configurable event input 66rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="RPIF68" description="configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF69" description="configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF70" description="configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF71" description="configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF72" description="configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF73" description="configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF74" description="configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR3" description="EXTI falling edge pending register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF66" description="configurable event input 66 falling edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="FPIF68" description="configurable event input x falling edge pending bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF69" description="configurable event input x falling edge pending bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF70" description="configurable event input x falling edge pending bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF71" description="configurable event input x falling edge pending bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF72" description="configurable event input x falling edge pending bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF73" description="configurable event input x falling edge pending bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF74" description="configurable event input x falling edge pending bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR3" description="EXTI security enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC64" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC65" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC66" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC68" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC69" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC70" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC71" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC72" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC73" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC74" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC77" description="Security enable on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR3" description="EXTI privilege enable register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV64" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV65" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV66" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV68" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV69" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV70" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV71" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV72" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV73" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV74" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV77" description="Privilege enable on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR1" description="EXTI external interrupt selection register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI0" description="EXTI0 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA0 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB0 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC0 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD0 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE0 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF0 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG0 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH0 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN0 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO0 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP0 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ0 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI1" description="EXTI1 GPIO port selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA1 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB1 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC1 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD1 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE1 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF1 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG1 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH1 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN1 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO1 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP1 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ1 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI2" description="EXTI2 GPIO port selection" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA2 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB2 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC2 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD2 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE2 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF2 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG2 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH2 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN2 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO2 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP2 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ2 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI3" description="EXTI3 GPIO port selection" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA3 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB3 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC3 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD3 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE3 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF3 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG3 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH3 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN3 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO3 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP3 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ3 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR2" description="EXTI external interrupt selection register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI4" description="EXTI4 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA4 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB4 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC4 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD4 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE4 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF4 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG4 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH4 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN4 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO4 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP4 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ4 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI5" description="EXTI5 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA5 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB5 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC5 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD5 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE5 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF5 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG5 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH5 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN5 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO5 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP5 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ5 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI6" description="EXTI6 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA6 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB6 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC6 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD6 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE6 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF6 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG6 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH6 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN6 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO6 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP6 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ6 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI7" description="EXTI7 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA7 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB7 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC7 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD7 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE7 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF7 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG7 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH7 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN7 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO7 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP7 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ7 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR3" description="EXTI external interrupt selection register 3" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI8" description="EXTI8 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA8 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB8 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC8 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD8 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE8 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF8 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG8 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH8 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN8 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO8 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP8 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ8 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI9" description="EXTI9 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA9 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB9 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC9 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD9 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE9 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF9 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG9 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH9 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN9 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO9 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP9 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ9 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI10" description="EXTI10 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA10 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB10 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC10 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD10 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE10 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF10 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG10 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH10 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN10 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO10 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP10 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ10 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI11" description="EXTI11 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA11 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB11 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC11 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD11 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE11 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF11 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG11 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH11 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN11 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO11 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PO11 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ11 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR4" description="EXTI external interrupt selection register 4" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI12" description="EXTI12 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA12 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB12 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC12 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD12 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE12 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF12 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG12 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH12 pin" start="0x07" />
+        <Enum name="B_0x08" description="PO12 pin" start="0x08" />
+        <Enum name="B_0x09" description="PP12 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PQ12 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PN12 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI13" description="EXTI13 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA13 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB13 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC13 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD13 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE13 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF13 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG13 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH13 pin" start="0x07" />
+        <Enum name="B_0x08" description="PO13 pin" start="0x08" />
+        <Enum name="B_0x09" description="PP13 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PQ13 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PN13 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI14" description="EXTI14 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA14 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB14 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC14 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD14 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE14 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF14 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG14 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH14 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN14 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO14 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP14 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ14 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI15" description="EXTI15 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA15 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB15 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC15 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD15 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE15 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF15 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG15 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH15 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN15 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO15 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP15 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ15 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_LOCKR" description="EXTI lock register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global security privilege EXTI_SECCFGRx/PRIVCFGRx" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Security, privilege open can be modified." start="0x0" />
+        <Enum name="B_0x1" description="Security, privilege locked can no longer be modified." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR1" description="EXTI CPU wake-up with interrupt mask register 1" start="+0x080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM0" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM1" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM2" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM3" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="IM4" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM5" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM6" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM7" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM8" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM9" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM10" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM11" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="IM12" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="IM13" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="IM14" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="IM15" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="IM17" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM18" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM19" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM20" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM21" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM22" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM23" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM24" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM25" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM26" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM27" description="CPU wake-up with interrupt mask on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM28" description="CPU wake-up with interrupt mask on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM29" description="CPU wake-up with interrupt mask on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM30" description="CPU wake-up with interrupt mask on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM31" description="CPU wake-up with interrupt mask on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR1" description="EXTI CPU wake-up with event mask register 1" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM0" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM1" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM2" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM3" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="EM4" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM5" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM6" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM7" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM8" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM9" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM10" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM11" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="EM12" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="EM13" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="EM14" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="EM15" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="EM17" description="CPU wake-up with event on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM18" description="CPU wake-up with event on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM19" description="CPU wake-up with event on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM20" description="CPU wake-up with event on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM21" description="CPU wake-up with event on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM22" description="CPU wake-up with event on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM23" description="CPU wake-up with event on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM24" description="CPU wake-up with event on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM25" description="CPU wake-up with event on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM26" description="CPU wake-up with event on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM27" description="CPU wake-up with event on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM28" description="CPU wake-up with event on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM29" description="CPU wake-up with event on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM30" description="CPU wake-up with event on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM31" description="CPU wake-up with event on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR2" description="EXTI CPU wake-up with interrupt mask register 2" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM32" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM33" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM34" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM35" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="IM36" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM37" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM38" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM39" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM40" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM41" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM42" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM43" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="IM44" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="IM45" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="IM46" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="IM47" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="IM48" description="CPU wake-up with interrupt mask on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="IM49" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="IM50" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="IM51" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="IM52" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="IM53" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="IM54" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="IM55" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="IM56" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="IM57" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="IM58" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="IM60" description="CPU wake-up with interrupt mask on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM61" description="CPU wake-up with interrupt mask on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM62" description="CPU wake-up with interrupt mask on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM63" description="CPU wake-up with interrupt mask on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR2" description="EXTI CPU wake-up with event mask register 2" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM32" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM33" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM34" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM35" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="EM36" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM37" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM38" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM39" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM40" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM41" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM42" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM43" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="EM44" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="EM45" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="EM46" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="EM47" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="EM48" description="CPU wake-up with interrupt mask on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="EM49" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="EM50" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="EM51" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="EM52" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="EM53" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="EM54" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="EM55" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="EM56" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="EM57" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="EM58" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="EM60" description="CPU wake-up with event on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM61" description="CPU wake-up with event on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM62" description="CPU wake-up with event on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM63" description="CPU wake-up with event on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR3" description="EXTI CPU wake-up with interrupt mask register 3" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM64" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM65" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM66" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM68" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM69" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM70" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM71" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM72" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM73" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM74" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM77" description="CPU wake-up with interrupt mask on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR3" description="EXTI CPU wake-up with event mask register 3" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM64" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM65" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM66" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM68" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM69" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM70" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM71" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM72" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM73" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM74" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM77" description="CPU wake-up with event on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EXTI_S" description="Extended interrupts and event controller" start="0x56025000">
+    <Register name="EXTI_RTSR1" description="EXTI rising trigger selection register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT0" description="Rising trigger event configuration bit of configurable event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="RT1" description="Rising trigger event configuration bit of configurable event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="RT2" description="Rising trigger event configuration bit of configurable event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="RT3" description="Rising trigger event configuration bit of configurable event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="RT4" description="Rising trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="RT5" description="Rising trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="RT6" description="Rising trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="RT7" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="RT8" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="RT9" description="Rising trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="RT10" description="Rising trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="RT11" description="Rising trigger event configuration bit of configurable event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="RT12" description="Rising trigger event configuration bit of configurable event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="RT13" description="Rising trigger event configuration bit of configurable event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="RT14" description="Rising trigger event configuration bit of configurable event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="RT15" description="Rising trigger event configuration bit of configurable event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="RT20" description="Rising trigger event configuration bit of configurable event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT21" description="Rising trigger event configuration bit of configurable event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR1" description="EXTI falling trigger selection register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT0" description="Falling trigger event configuration bit of configurable event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="FT1" description="Falling trigger event configuration bit of configurable event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="FT2" description="Falling trigger event configuration bit of configurable event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="FT3" description="Falling trigger event configuration bit of configurable event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="FT4" description="Falling trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="FT5" description="Falling trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="FT6" description="Falling trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="FT7" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="FT8" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="FT9" description="Falling trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="FT10" description="Falling trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="FT11" description="Falling trigger event configuration bit of configurable event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="FT12" description="Falling trigger event configuration bit of configurable event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="FT13" description="Falling trigger event configuration bit of configurable event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="FT14" description="Falling trigger event configuration bit of configurable event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="FT15" description="Falling trigger event configuration bit of configurable event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="FT20" description="Falling trigger event configuration bit of configurable event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line." start="0x1" />
+      </BitField>
+      <BitField name="FT21" description="Falling trigger event configuration bit of configurable event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER1" description="EXTI software interrupt event register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI0" description="Software interrupt on event x" start="0" size="1" access="Read/Write" />
+      <BitField name="SWI1" description="Software interrupt on event x" start="1" size="1" access="Read/Write" />
+      <BitField name="SWI2" description="Software interrupt on event x" start="2" size="1" access="Read/Write" />
+      <BitField name="SWI3" description="Software interrupt on event x" start="3" size="1" access="Read/Write" />
+      <BitField name="SWI4" description="Software interrupt on event x" start="4" size="1" access="Read/Write" />
+      <BitField name="SWI5" description="Software interrupt on event x" start="5" size="1" access="Read/Write" />
+      <BitField name="SWI6" description="Software interrupt on event x" start="6" size="1" access="Read/Write" />
+      <BitField name="SWI7" description="Software interrupt on event x" start="7" size="1" access="Read/Write" />
+      <BitField name="SWI8" description="Software interrupt on event x" start="8" size="1" access="Read/Write" />
+      <BitField name="SWI9" description="Software interrupt on event x" start="9" size="1" access="Read/Write" />
+      <BitField name="SWI10" description="Software interrupt on event x" start="10" size="1" access="Read/Write" />
+      <BitField name="SWI11" description="Software interrupt on event x" start="11" size="1" access="Read/Write" />
+      <BitField name="SWI12" description="Software interrupt on event x" start="12" size="1" access="Read/Write" />
+      <BitField name="SWI13" description="Software interrupt on event x" start="13" size="1" access="Read/Write" />
+      <BitField name="SWI14" description="Software interrupt on event x" start="14" size="1" access="Read/Write" />
+      <BitField name="SWI15" description="Software interrupt on event x" start="15" size="1" access="Read/Write" />
+      <BitField name="SWI20" description="Software interrupt on event x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI21" description="Software interrupt on event x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR1" description="EXTI rising edge pending register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF0" description="Configurable event input x rising edge pending bit" start="0" size="1" access="Read/Write" />
+      <BitField name="RPIF1" description="Configurable event input x rising edge pending bit" start="1" size="1" access="Read/Write" />
+      <BitField name="RPIF2" description="Configurable event input x rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="RPIF3" description="Configurable event input x rising edge pending bit" start="3" size="1" access="Read/Write" />
+      <BitField name="RPIF4" description="Configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write" />
+      <BitField name="RPIF5" description="Configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write" />
+      <BitField name="RPIF6" description="Configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write" />
+      <BitField name="RPIF7" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="RPIF8" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="RPIF9" description="Configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write" />
+      <BitField name="RPIF10" description="Configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write" />
+      <BitField name="RPIF11" description="Configurable event input x rising edge pending bit" start="11" size="1" access="Read/Write" />
+      <BitField name="RPIF12" description="Configurable event input x rising edge pending bit" start="12" size="1" access="Read/Write" />
+      <BitField name="RPIF13" description="Configurable event input x rising edge pending bit" start="13" size="1" access="Read/Write" />
+      <BitField name="RPIF14" description="Configurable event input x rising edge pending bit" start="14" size="1" access="Read/Write" />
+      <BitField name="RPIF15" description="Configurable event input x rising edge pending bit" start="15" size="1" access="Read/Write" />
+      <BitField name="RPIF20" description="Configurable event input x rising edge pending bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF21" description="Configurable event input x rising edge pending bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR1" description="EXTI falling edge pending register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF0" description="Configurable event input x rising edge pending bit" start="0" size="1" access="Read/Write" />
+      <BitField name="FPIF1" description="Configurable event input x rising edge pending bit" start="1" size="1" access="Read/Write" />
+      <BitField name="FPIF2" description="Configurable event input x rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="FPIF3" description="Configurable event input x rising edge pending bit" start="3" size="1" access="Read/Write" />
+      <BitField name="FPIF4" description="Configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write" />
+      <BitField name="FPIF5" description="Configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write" />
+      <BitField name="FPIF6" description="Configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write" />
+      <BitField name="FPIF7" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="FPIF8" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="FPIF9" description="Configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write" />
+      <BitField name="FPIF10" description="Configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write" />
+      <BitField name="FPIF11" description="Configurable event input x rising edge pending bit" start="11" size="1" access="Read/Write" />
+      <BitField name="FPIF12" description="Configurable event input x rising edge pending bit" start="12" size="1" access="Read/Write" />
+      <BitField name="FPIF13" description="Configurable event input x rising edge pending bit" start="13" size="1" access="Read/Write" />
+      <BitField name="FPIF14" description="Configurable event input x rising edge pending bit" start="14" size="1" access="Read/Write" />
+      <BitField name="FPIF15" description="Configurable event input x rising edge pending bit" start="15" size="1" access="Read/Write" />
+      <BitField name="FPIF20" description="configurable event input x falling edge pending bit" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF21" description="configurable event input x falling edge pending bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR1" description="EXTI security configuration register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC1" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC2" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC3" description="Security enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="SEC4" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC5" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC6" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC7" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC8" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC9" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC10" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC11" description="Security enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="SEC12" description="Security enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="SEC13" description="Security enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="SEC14" description="Security enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="SEC15" description="Security enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="SEC17" description="Security enable on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC18" description="Security enable on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC19" description="Security enable on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC20" description="Security enable on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC21" description="Security enable on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC22" description="Security enable on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC23" description="Security enable on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC24" description="Security enable on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC25" description="Security enable on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC26" description="Security enable on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC27" description="Security enable on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC28" description="Security enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC29" description="Security enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC30" description="Security enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC31" description="Security enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR1" description="EXTI privilege configuration register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV1" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV2" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV3" description="Privilege enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="PRIV4" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV5" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV6" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV7" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV8" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV9" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV10" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV11" description="Privilege enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="PRIV12" description="Privilege enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="PRIV13" description="Privilege enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="PRIV14" description="Privilege enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="PRIV15" description="Privilege enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="PRIV17" description="Privilege enable on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV18" description="Privilege enable on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV19" description="Privilege enable on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV20" description="Privilege enable on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV21" description="Privilege enable on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV22" description="Privilege enable on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV23" description="Privilege enable on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV24" description="Privilege enable on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV25" description="Privilege enable on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV26" description="Privilege enable on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV27" description="Privilege enable on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV28" description="Privilege enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV29" description="Privilege enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV30" description="Privilege enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV31" description="Privilege enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RTSR2" description="EXTI rising trigger selection register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT39" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="RT40" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="RT51" description="Rising trigger event configuration bit of configurable event input 51" start="19" size="1" access="Read/Write" />
+      <BitField name="RT54" description="Rising trigger event configuration bit of configurable event input 54" start="22" size="1" access="Read/Write" />
+      <BitField name="RT56" description="Rising trigger event configuration bit of configurable event input 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and Interrupt) for input line x" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and Interrupt) for input line x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR2" description="EXTI falling trigger selection register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT39" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="FT40" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="FT51" description="Falling trigger event configuration bit of configurable event input 51" start="19" size="1" access="Read/Write" />
+      <BitField name="FT54" description="Falling trigger event configuration bit of configurable event input 54" start="22" size="1" access="Read/Write" />
+      <BitField name="FT56" description="Falling trigger event configuration bit of configurable event input 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and Interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and Interrupt) for input line." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER2" description="EXTI software interrupt event register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI39" description="Software interrupt on event x" start="7" size="1" access="Read/Write" />
+      <BitField name="SWI40" description="Software interrupt on event x" start="8" size="1" access="Read/Write" />
+      <BitField name="SWI51" description="Software interrupt on event 51" start="19" size="1" access="Read/Write" />
+      <BitField name="SWI54" description="Software interrupt on event 54" start="22" size="1" access="Read/Write" />
+      <BitField name="SWI56" description="Software interrupt on event 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR2" description="EXTI rising edge pending register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF39" description="Configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="RPIF40" description="Configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="RPIF51" description="Configurable event input 51 rising edge pending bit" start="19" size="1" access="Read/Write" />
+      <BitField name="RPIF54" description="Configurable event input 54 rising edge pending bit" start="22" size="1" access="Read/Write" />
+      <BitField name="RPIF56" description="Configurable event input 56 rising edge pending bit " start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR2" description="EXTI falling edge pending register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF39" description="Configurable event input x falling edge pending bit" start="7" size="1" access="Read/Write" />
+      <BitField name="FPIF40" description="Configurable event input x falling edge pending bit" start="8" size="1" access="Read/Write" />
+      <BitField name="FPIF51" description="Configurable event input 51 falling edge pending bit" start="19" size="1" access="Read/Write" />
+      <BitField name="FPIF54" description="Configurable event input 54 falling edge pending bit" start="22" size="1" access="Read/Write" />
+      <BitField name="FPIF56" description="Configurable event input 56 falling edge pending bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR2" description="EXTI security enable register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC32" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC33" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC34" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC35" description="Security enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="SEC36" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC37" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC38" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC39" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC40" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC41" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC42" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC43" description="Security enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="SEC44" description="Security enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="SEC45" description="Security enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="SEC46" description="Security enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="SEC47" description="Security enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="SEC48" description="Security enable on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="SEC49" description="Security enable on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="SEC50" description="Security enable on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="SEC51" description="Security enable on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="SEC52" description="Security enable on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="SEC53" description="Security enable on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="SEC54" description="Security enable on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="SEC55" description="Security enable on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="SEC56" description="Security enable on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="SEC57" description="Security enable on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="SEC58" description="Security enable on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="SEC60" description="Security enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC61" description="Security enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC62" description="Security enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+      <BitField name="SEC63" description="Security enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR2" description="EXTI privilege enable register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV32" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV33" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV34" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV35" description="Privilege enable on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="PRIV36" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV37" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV38" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV39" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV40" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV41" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV42" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV43" description="Privilege enable on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="PRIV44" description="Privilege enable on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="PRIV45" description="Privilege enable on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="PRIV46" description="Privilege enable on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="PRIV47" description="Privilege enable on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="PRIV48" description="Privilege enable on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="PRIV49" description="Privilege enable on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="PRIV50" description="Privilege enable on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="PRIV51" description="Privilege enable on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="PRIV52" description="Privilege enable on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="PRIV53" description="Privilege enable on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="PRIV54" description="Privilege enable on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="PRIV55" description="Privilege enable on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="PRIV56" description="Privilege enable on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="PRIV57" description="Privilege enable on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="PRIV58" description="Privilege enable on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="PRIV60" description="Privilege enable on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV61" description="Privilege enable on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV62" description="Privilege enable on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+      <BitField name="PRIV63" description="Privilege enable on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged)" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RTSR3" description="EXTI rising trigger selection register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RT66" description="Rising trigger event configuration bit of configurable event input 66" start="2" size="1" access="Read/Write" />
+      <BitField name="RT68" description="Rising trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT69" description="Rising trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT70" description="Rising trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT71" description="Rising trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT72" description="Rising trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT73" description="Rising trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="RT74" description="Rising trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Rising trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FTSR3" description="EXTI falling trigger selection register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FT66" description="Falling trigger event configuration bit of configurable event input 66" start="2" size="1" access="Read/Write" />
+      <BitField name="FT68" description="Falling trigger event configuration bit of configurable event input x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT69" description="Falling trigger event configuration bit of configurable event input x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT70" description="Falling trigger event configuration bit of configurable event input x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT71" description="Falling trigger event configuration bit of configurable event input x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT72" description="Falling trigger event configuration bit of configurable event input x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT73" description="Falling trigger event configuration bit of configurable event input x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+      <BitField name="FT74" description="Falling trigger event configuration bit of configurable event input x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling trigger disabled (for event and interrupt) for input line" start="0x0" />
+        <Enum name="B_0x1" description="Falling trigger enabled (for event and interrupt) for input line" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SWIER3" description="EXTI software interrupt event register" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWI66" description="Software interrupt on event 66" start="2" size="1" access="Read/Write" />
+      <BitField name="SWI68" description="Software interrupt on event x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI69" description="Software interrupt on event x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI70" description="Software interrupt on event x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI71" description="Software interrupt on event x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI72" description="Software interrupt on event x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI73" description="Software interrupt on event x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+      <BitField name="SWI74" description="Software interrupt on event x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 to this bit triggers a rising edge event on event x (bit auto cleared by hardware)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_RPR3" description="EXTI rising edge pending register" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPIF66" description="configurable event input 66rising edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="RPIF68" description="configurable event input x rising edge pending bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF69" description="configurable event input x rising edge pending bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF70" description="configurable event input x rising edge pending bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF71" description="configurable event input x rising edge pending bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF72" description="configurable event input x rising edge pending bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF73" description="configurable event input x rising edge pending bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="RPIF74" description="configurable event input x rising edge pending bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_FPR3" description="EXTI falling edge pending register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPIF66" description="configurable event input 66 falling edge pending bit" start="2" size="1" access="Read/Write" />
+      <BitField name="FPIF68" description="configurable event input x falling edge pending bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF69" description="configurable event input x falling edge pending bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF70" description="configurable event input x falling edge pending bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF71" description="configurable event input x falling edge pending bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF72" description="configurable event input x falling edge pending bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF73" description="configurable event input x falling edge pending bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+      <BitField name="FPIF74" description="configurable event input x falling edge pending bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_SECCFGR3" description="EXTI security enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC64" description="Security enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="SEC65" description="Security enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="SEC66" description="Security enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="SEC68" description="Security enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="SEC69" description="Security enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="SEC70" description="Security enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="SEC71" description="Security enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="SEC72" description="Security enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="SEC73" description="Security enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="SEC74" description="Security enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="SEC77" description="Security enable on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event security disabled (non-secure)" start="0x0" />
+        <Enum name="B_0x1" description="Event security enabled (secure)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_PRIVCFGR3" description="EXTI privilege enable register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV64" description="Privilege enable on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="PRIV65" description="Privilege enable on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="PRIV66" description="Privilege enable on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="PRIV68" description="Privilege enable on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="PRIV69" description="Privilege enable on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="PRIV70" description="Privilege enable on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="PRIV71" description="Privilege enable on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="PRIV72" description="Privilege enable on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="PRIV73" description="Privilege enable on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="PRIV74" description="Privilege enable on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="PRIV77" description="Privilege enable on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Event privilege disabled (unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="Event privilege enabled (privileged)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR1" description="EXTI external interrupt selection register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI0" description="EXTI0 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA0 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB0 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC0 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD0 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE0 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF0 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG0 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH0 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN0 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO0 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP0 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ0 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI1" description="EXTI1 GPIO port selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA1 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB1 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC1 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD1 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE1 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF1 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG1 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH1 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN1 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO1 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP1 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ1 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI2" description="EXTI2 GPIO port selection" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA2 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB2 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC2 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD2 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE2 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF2 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG2 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH2 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN2 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO2 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP2 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ2 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI3" description="EXTI3 GPIO port selection" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA3 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB3 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC3 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD3 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE3 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF3 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG3 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH3 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN3 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO3 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP3 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ3 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR2" description="EXTI external interrupt selection register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI4" description="EXTI4 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA4 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB4 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC4 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD4 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE4 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF4 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG4 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH4 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN4 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO4 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP4 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ4 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI5" description="EXTI5 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA5 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB5 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC5 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD5 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE5 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF5 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG5 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH5 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN5 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO5 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP5 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ5 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI6" description="EXTI6 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA6 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB6 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC6 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD6 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE6 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF6 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG6 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH6 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN6 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO6 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP6 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ6 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI7" description="EXTI7 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA7 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB7 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC7 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD7 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE7 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF7 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG7 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH7 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN7 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO7 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP7 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ7 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR3" description="EXTI external interrupt selection register 3" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI8" description="EXTI8 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA8 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB8 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC8 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD8 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE8 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF8 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG8 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH8 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN8 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO8 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP8 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ8 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI9" description="EXTI9 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA9 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB9 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC9 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD9 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE9 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF9 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG9 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH9 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN9 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO9 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP9 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ9 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI10" description="EXTI10 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA10 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB10 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC10 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD10 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE10 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF10 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG10 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH10 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN10 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO10 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP10 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ10 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI11" description="EXTI11 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA11 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB11 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC11 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD11 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE11 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF11 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG11 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH11 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN11 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO11 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PO11 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ11 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EXTICR4" description="EXTI external interrupt selection register 4" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI12" description="EXTI12 GPIO port selection." start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA12 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB12 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC12 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD12 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE12 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF12 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG12 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH12 pin" start="0x07" />
+        <Enum name="B_0x08" description="PO12 pin" start="0x08" />
+        <Enum name="B_0x09" description="PP12 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PQ12 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PN12 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI13" description="EXTI13 GPIO port selection." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA13 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB13 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC13 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD13 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE13 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF13 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG13 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH13 pin" start="0x07" />
+        <Enum name="B_0x08" description="PO13 pin" start="0x08" />
+        <Enum name="B_0x09" description="PP13 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PQ13 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PN13 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI14" description="EXTI14 GPIO port selection." start="16" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA14 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB14 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC14 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD14 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE14 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF14 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG14 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH14 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN14 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO14 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP14 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ14 pin" start="0x0B" />
+      </BitField>
+      <BitField name="EXTI15" description="EXTI15 GPIO port selection." start="24" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="PA15 pin" start="0x00" />
+        <Enum name="B_0x01" description="PB15 pin" start="0x01" />
+        <Enum name="B_0x02" description="PC15 pin" start="0x02" />
+        <Enum name="B_0x03" description="PD15 pin" start="0x03" />
+        <Enum name="B_0x04" description="PE15 pin" start="0x04" />
+        <Enum name="B_0x05" description="PF15 pin" start="0x05" />
+        <Enum name="B_0x06" description="PG15 pin" start="0x06" />
+        <Enum name="B_0x07" description="PH15 pin" start="0x07" />
+        <Enum name="B_0x08" description="PN15 pin" start="0x08" />
+        <Enum name="B_0x09" description="PO15 pin" start="0x09" />
+        <Enum name="B_0x0A" description="PP15 pin" start="0x0A" />
+        <Enum name="B_0x0B" description="PQ15 pin" start="0x0B" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_LOCKR" description="EXTI lock register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global security privilege EXTI_SECCFGRx/PRIVCFGRx" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Security, privilege open can be modified." start="0x0" />
+        <Enum name="B_0x1" description="Security, privilege locked can no longer be modified." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR1" description="EXTI CPU wake-up with interrupt mask register 1" start="+0x080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM0" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM1" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM2" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM3" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="IM4" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM5" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM6" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM7" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM8" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM9" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM10" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM11" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="IM12" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="IM13" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="IM14" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="IM15" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="IM17" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM18" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM19" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM20" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM21" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM22" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM23" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM24" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM25" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM26" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM27" description="CPU wake-up with interrupt mask on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM28" description="CPU wake-up with interrupt mask on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM29" description="CPU wake-up with interrupt mask on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM30" description="CPU wake-up with interrupt mask on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM31" description="CPU wake-up with interrupt mask on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR1" description="EXTI CPU wake-up with event mask register 1" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM0" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM1" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM2" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM3" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="EM4" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM5" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM6" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM7" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM8" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM9" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM10" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM11" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="EM12" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="EM13" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="EM14" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="EM15" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="EM17" description="CPU wake-up with event on event input x" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM18" description="CPU wake-up with event on event input x" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM19" description="CPU wake-up with event on event input x" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM20" description="CPU wake-up with event on event input x" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM21" description="CPU wake-up with event on event input x" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM22" description="CPU wake-up with event on event input x" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM23" description="CPU wake-up with event on event input x" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM24" description="CPU wake-up with event on event input x" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM25" description="CPU wake-up with event on event input x" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM26" description="CPU wake-up with event on event input x" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM27" description="CPU wake-up with event on event input x" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM28" description="CPU wake-up with event on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM29" description="CPU wake-up with event on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM30" description="CPU wake-up with event on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM31" description="CPU wake-up with event on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR2" description="EXTI CPU wake-up with interrupt mask register 2" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM32" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM33" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM34" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM35" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="IM36" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM37" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM38" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM39" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM40" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM41" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM42" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM43" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="IM44" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="IM45" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="IM46" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="IM47" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="IM48" description="CPU wake-up with interrupt mask on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="IM49" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="IM50" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="IM51" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="IM52" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="IM53" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="IM54" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="IM55" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="IM56" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="IM57" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="IM58" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="IM60" description="CPU wake-up with interrupt mask on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM61" description="CPU wake-up with interrupt mask on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM62" description="CPU wake-up with interrupt mask on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+      <BitField name="IM63" description="CPU wake-up with interrupt mask on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR2" description="EXTI CPU wake-up with event mask register 2" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM32" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM33" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM34" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM35" description="CPU wake-up with interrupt mask on event input x" start="3" size="1" access="Read/Write" />
+      <BitField name="EM36" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM37" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM38" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM39" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM40" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM41" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM42" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM43" description="CPU wake-up with interrupt mask on event input x" start="11" size="1" access="Read/Write" />
+      <BitField name="EM44" description="CPU wake-up with interrupt mask on event input x" start="12" size="1" access="Read/Write" />
+      <BitField name="EM45" description="CPU wake-up with interrupt mask on event input x" start="13" size="1" access="Read/Write" />
+      <BitField name="EM46" description="CPU wake-up with interrupt mask on event input x" start="14" size="1" access="Read/Write" />
+      <BitField name="EM47" description="CPU wake-up with interrupt mask on event input x" start="15" size="1" access="Read/Write" />
+      <BitField name="EM48" description="CPU wake-up with interrupt mask on event input x" start="16" size="1" access="Read/Write" />
+      <BitField name="EM49" description="CPU wake-up with interrupt mask on event input x" start="17" size="1" access="Read/Write" />
+      <BitField name="EM50" description="CPU wake-up with interrupt mask on event input x" start="18" size="1" access="Read/Write" />
+      <BitField name="EM51" description="CPU wake-up with interrupt mask on event input x" start="19" size="1" access="Read/Write" />
+      <BitField name="EM52" description="CPU wake-up with interrupt mask on event input x" start="20" size="1" access="Read/Write" />
+      <BitField name="EM53" description="CPU wake-up with interrupt mask on event input x" start="21" size="1" access="Read/Write" />
+      <BitField name="EM54" description="CPU wake-up with interrupt mask on event input x" start="22" size="1" access="Read/Write" />
+      <BitField name="EM55" description="CPU wake-up with interrupt mask on event input x" start="23" size="1" access="Read/Write" />
+      <BitField name="EM56" description="CPU wake-up with interrupt mask on event input x" start="24" size="1" access="Read/Write" />
+      <BitField name="EM57" description="CPU wake-up with interrupt mask on event input x" start="25" size="1" access="Read/Write" />
+      <BitField name="EM58" description="CPU wake-up with interrupt mask on event input x" start="26" size="1" access="Read/Write" />
+      <BitField name="EM60" description="CPU wake-up with event on event input x" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM61" description="CPU wake-up with event on event input x" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM62" description="CPU wake-up with event on event input x" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+      <BitField name="EM63" description="CPU wake-up with event on event input x" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_IMR3" description="EXTI CPU wake-up with interrupt mask register 3" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IM64" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="IM65" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="IM66" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="IM68" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="IM69" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="IM70" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="IM71" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="IM72" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="IM73" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="IM74" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="IM77" description="CPU wake-up with interrupt mask on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up and interrupt from input event x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up and interrupt from input event x is unmasked. CPU wake-up event and configurable event interrupt generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="EXTI_EMR3" description="EXTI CPU wake-up with event mask register 3" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EM64" description="CPU wake-up with interrupt mask on event input x" start="0" size="1" access="Read/Write" />
+      <BitField name="EM65" description="CPU wake-up with interrupt mask on event input x" start="1" size="1" access="Read/Write" />
+      <BitField name="EM66" description="CPU wake-up with interrupt mask on event input x" start="2" size="1" access="Read/Write" />
+      <BitField name="EM68" description="CPU wake-up with interrupt mask on event input x" start="4" size="1" access="Read/Write" />
+      <BitField name="EM69" description="CPU wake-up with interrupt mask on event input x" start="5" size="1" access="Read/Write" />
+      <BitField name="EM70" description="CPU wake-up with interrupt mask on event input x" start="6" size="1" access="Read/Write" />
+      <BitField name="EM71" description="CPU wake-up with interrupt mask on event input x" start="7" size="1" access="Read/Write" />
+      <BitField name="EM72" description="CPU wake-up with interrupt mask on event input x" start="8" size="1" access="Read/Write" />
+      <BitField name="EM73" description="CPU wake-up with interrupt mask on event input x" start="9" size="1" access="Read/Write" />
+      <BitField name="EM74" description="CPU wake-up with interrupt mask on event input x" start="10" size="1" access="Read/Write" />
+      <BitField name="EM77" description="CPU wake-up with event on event input 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up with event request from line x is masked." start="0x0" />
+        <Enum name="B_0x1" description="Wake-up with event request from line x is unmasked." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN1" description="FDCAN register block" start="0x4000A000">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN1_S" description="FDCAN register block" start="0x5000A000">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN2" description="FDCAN register block" start="0x4000A400">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN2_S" description="FDCAN register block" start="0x5000A400">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN3" description="FDCAN register block" start="0x4000E800">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN3_S" description="FDCAN register block" start="0x5000E800">
+    <Register name="FDCAN_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day =18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year = 4" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 2" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 3" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CREL" description="FDCAN core release register" start="+0x0000" size="4" reset_value="0x32141218" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Timestamp day = 18" start="0" size="8" access="ReadOnly" />
+      <BitField name="MON" description="Timestamp month = 12" start="8" size="8" access="ReadOnly" />
+      <BitField name="YEAR" description="Timestamp year =" start="16" size="4" access="ReadOnly" />
+      <BitField name="SUBSTEP" description="Sub-step of core release = 1" start="20" size="4" access="ReadOnly" />
+      <BitField name="STEP" description="Step of core release = 1" start="24" size="4" access="ReadOnly" />
+      <BitField name="REL" description="Core release = 1" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_CCFG" description="FDCAN Endian register" start="+0x0004" size="4" reset_value="0x87654321" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time quanta per bit time" start="0" size="5" access="Read/Write" />
+      <BitField name="BCC" description="Bypass clock calibration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock calibration unit generates time quanta clock" start="0x0" />
+        <Enum name="B_0x1" description="Clock calibration unit bypassed (default configuration)" start="0x1" />
+      </BitField>
+      <BitField name="CFL" description="Calibration field length" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration field length is 32 bits" start="0x0" />
+        <Enum name="B_0x1" description="Calibration field length is 64 bits" start="0x1" />
+      </BitField>
+      <BitField name="OCPM" description="Oscillator clock periods minimum" start="8" size="8" access="Read/Write" />
+      <BitField name="CDIV" description="Clock divider" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Divide by 1" start="0x0" />
+        <Enum name="B_0x1" description="Divide by 2" start="0x1" />
+        <Enum name="B_0x2" description="Divide by 4" start="0x2" />
+        <Enum name="B_0x3" description="Divide by 6" start="0x3" />
+        <Enum name="B_0x4" description="Divide by 8" start="0x4" />
+        <Enum name="B_0x5" description="Divide by 10" start="0x5" />
+        <Enum name="B_0x6" description="Divide by 12" start="0x6" />
+        <Enum name="B_0x7" description="Divide by 14" start="0x7" />
+        <Enum name="B_0x8" description="Divide by 16" start="0x8" />
+        <Enum name="B_0x9" description="Divide by 18" start="0x9" />
+        <Enum name="B_0xA" description="Divide by 20" start="0xA" />
+        <Enum name="B_0xB" description="Divide by 22" start="0xB" />
+        <Enum name="B_0xC" description="Divide by 24" start="0xC" />
+        <Enum name="B_0xD" description="Divide by 26" start="0xD" />
+        <Enum name="B_0xE" description="Divide by 28" start="0xE" />
+        <Enum name="B_0xF" description="Divide by 30" start="0xF" />
+      </BitField>
+      <BitField name="SWR" description="Software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_CCU_CSTAT" description="Calibration status register" start="+0x0008" size="4" reset_value="0x0203FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator clock period counter" start="0" size="18" access="ReadOnly" />
+      <BitField name="TQC" description="Time quanta counter" start="18" size="11" access="ReadOnly" />
+      <BitField name="CALS" description="Calibration state" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Not_Calibrated" start="0x0" />
+        <Enum name="B_0x1" description="Basic_Calibrated" start="0x1" />
+        <Enum name="B_0x2" description="Precision_Calibrated" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization jump width" start="0" size="4" access="Read/Write" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" access="Read/Write" />
+      <BitField name="DTSEG1" description="Data time segment before sample point" start="8" size="5" access="Read/Write" />
+      <BitField name="DBRP" description="Data bitrate prescaler" start="16" size="5" access="Read/Write" />
+      <BitField name="TDC" description="Transceiver delay compensation" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transceiver delay compensation disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transceiver delay compensation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_CWD" description="FDCAN data bit timing and prescaler register" start="+0x000C" size="4" reset_value="0x00000A33" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop back mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value, loop back mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Loop back mode is enabled (see Test modes)" start="0x1" />
+      </BitField>
+      <BitField name="TX" description="Control of transmit pin" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time" start="0x0" />
+        <Enum name="B_0x1" description="Sample point can be monitored at pin FDCANx_TX" start="0x1" />
+        <Enum name="B_0x2" description="Dominant (0) level at pin FDCANx_TX" start="0x2" />
+        <Enum name="B_0x3" description="Recessive (1) at pin FDCANx_TX" start="0x3" />
+      </BitField>
+      <BitField name="RX" description="Receive pin" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The CAN bus is dominant (FDCANx_RX = 0)" start="0x0" />
+        <Enum name="B_0x1" description="The CAN bus is recessive (FDCANx_RX = 1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCU_IR" description="FDCAN test register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration watchdog event" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No calibration watchdog event" start="0x0" />
+        <Enum name="B_0x1" description="Calibration watchdog event occurred" start="0x1" />
+      </BitField>
+      <BitField name="CSC" description="Calibration state changed" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration state unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Calibration state has changed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" access="Read/Write" />
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_CCU_IE" description="FDCAN RAM watchdog register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration watchdog event enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSCE" description="Calibration state changed enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC control register" start="+0x0018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation" start="0x0" />
+        <Enum name="B_0x1" description="Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="CCE" description="Configuration change enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The CPU has no write access to the protected configuration registers" start="0x0" />
+        <Enum name="B_0x1" description="The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared)" start="0x1" />
+      </BitField>
+      <BitField name="ASM" description="ASM restricted operation mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal CAN operation" start="0x0" />
+        <Enum name="B_0x1" description="Restricted operation mode active" start="0x1" />
+      </BitField>
+      <BitField name="CSA" description="Clock stop acknowledge" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No clock stop acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN may be set in power down by stopping APB clock and kernel clock" start="0x1" />
+      </BitField>
+      <BitField name="CSR" description="Clock stop request" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No clock stop is requested" start="0x0" />
+        <Enum name="B_0x1" description="Clock stop requested. When clock stop is requested, first INIT and then CSA is set" start="0x1" />
+      </BitField>
+      <BitField name="MON" description="Bus monitoring mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus monitoring mode is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bus monitoring mode is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAR" description="Disable automatic retransmission" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic retransmission of messages not transmitted successfully enabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic retransmission disabled" start="0x1" />
+      </BitField>
+      <BitField name="TEST" description="Test mode enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation, register TEST holds reset values" start="0x0" />
+        <Enum name="B_0x1" description="Test mode, write access to register TEST enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDOE" description="FD operation enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FD operation disabled" start="0x0" />
+        <Enum name="B_0x1" description="FD operation enabled" start="0x1" />
+      </BitField>
+      <BitField name="BRSE" description="FDCAN bitrate switching" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitrate switching for transmissions disabled" start="0x0" />
+        <Enum name="B_0x1" description="Bitrate switching for transmissions enabled" start="0x1" />
+      </BitField>
+      <BitField name="PXHD" description="Protocol exception handling disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Protocol exception handling enabled" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception handling disabled" start="0x1" />
+      </BitField>
+      <BitField name="EFBI" description="Edge filtering during bus integration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Edge filtering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Two consecutive dominant tq required to detect an edge for hard synchronization" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="NISO" description="Non ISO operation" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN FD frame format according to ISO11898-1" start="0x0" />
+        <Enum name="B_0x1" description="CAN FD frame format according to Bosch CAN FD Specification V1.0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN nominal bit timing and prescaler register" start="+0x001C" size="4" reset_value="0x06000A03" reset_mask="0xFFFFFFFF">
+      <BitField name="NTSEG2" description="Nominal time segment after sample point" start="0" size="7" access="Read/Write" />
+      <BitField name="NTSEG1" description="Nominal time segment before sample point" start="8" size="8" access="Read/Write" />
+      <BitField name="NBRP" description="Bitrate prescaler" start="16" size="9" access="Read/Write" />
+      <BitField name="NSJW" description="Nominal (re)synchronization jump width" start="25" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN timestamp counter configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="Timestamp select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp counter value always 0x0000" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter value incremented according to TCP" start="0x1" />
+        <Enum name="B_0x2" description="External timestamp counter from TIM3 value used (tim3_cnt[0:15])" start="0x2" />
+        <Enum name="B_0x3" description="Same as 00." start="0x3" />
+      </BitField>
+      <BitField name="TCP" description="Timestamp counter prescaler" start="16" size="4" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN timestamp counter value register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN timeout counter configuration register" start="+0x0028" size="4" reset_value="0xFFFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable timeout counter" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timeout counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Timeout counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOS" description="Timeout select" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Continuous operation" start="0x0" />
+        <Enum name="B_0x1" description="Timeout controlled by Tx event FIFO" start="0x1" />
+        <Enum name="B_0x2" description="Timeout controlled by Rx FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Timeout controlled by Rx FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="TOP" description="Timeout period" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN timeout counter value register" start="+0x002C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout counter" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN error counter register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEC" description="Transmit error counter" start="0" size="8" access="ReadOnly" />
+      <BitField name="REC" description="Receive error counter" start="8" size="7" access="ReadOnly" />
+      <BitField name="RP" description="Receive error passive" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The receive error counter is below the error passive level of 128" start="0x0" />
+        <Enum name="B_0x1" description="The receive error counter has reached the error passive level of 128" start="0x1" />
+      </BitField>
+      <BitField name="CEL" description="CAN error logging" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN protocol status register" start="+0x0044" size="4" reset_value="0x00000707" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last error code" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No error: No error occurred since LEC has been reset by successful reception or transmission." start="0x0" />
+        <Enum name="B_0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." start="0x1" />
+        <Enum name="B_0x2" description="Form error: A fixed format part of a received frame has the wrong format." start="0x2" />
+        <Enum name="B_0x3" description="AckError: The message transmitted by the FDCAN was not acknowledged by another node." start="0x3" />
+        <Enum name="B_0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant." start="0x4" />
+        <Enum name="B_0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)." start="0x5" />
+        <Enum name="B_0x6" description="CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data." start="0x6" />
+        <Enum name="B_0x7" description="NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register." start="0x7" />
+      </BitField>
+      <BitField name="ACT" description="Activity" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronizing: node is synchronizing on CAN communication" start="0x0" />
+        <Enum name="B_0x1" description="Idle: node is neither receiver nor transmitter" start="0x1" />
+        <Enum name="B_0x2" description="Receiver: node is operating as receiver" start="0x2" />
+        <Enum name="B_0x3" description="Transmitter: node is operating as transmitter" start="0x3" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in the Error_Passive state" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Both error counters are below the Error_Warning limit of 96" start="0x0" />
+        <Enum name="B_0x1" description="At least one of error counter has reached the Error_Warning limit of 96" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The FDCAN is not Bus_Off" start="0x0" />
+        <Enum name="B_0x1" description="The FDCAN is in Bus_Off state" start="0x1" />
+      </BitField>
+      <BitField name="DLEC" description="Data last error code" start="8" size="3" access="ReadOnly" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN message" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not ha ve its ESI flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its ESI flag set" start="0x1" />
+      </BitField>
+      <BitField name="RBRS" description="BRS flag of last received FDCAN message" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Last received FDCAN message did not have its BRS flag set" start="0x0" />
+        <Enum name="B_0x1" description="Last received FDCAN message had its BRS flag set" start="0x1" />
+      </BitField>
+      <BitField name="REDL" description="Received FDCAN message" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Since this bit was reset by the CPU, no FDCAN message has been received" start="0x0" />
+        <Enum name="B_0x1" description="Message in FDCAN format with EDL flag set has been received" start="0x1" />
+      </BitField>
+      <BitField name="PXE" description="Protocol exception event" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol exception event occurred since last read access" start="0x0" />
+        <Enum name="B_0x1" description="Protocol exception event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TDCV" description="Transmitter delay compensation value" start="16" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN transmitter delay compensation register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter delay compensation filter window length" start="0" size="7" access="Read/Write" />
+      <BitField name="TDCO" description="Transmitter delay compensation offset" start="8" size="7" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN interrupt register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New message" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 0" start="0x1" />
+      </BitField>
+      <BitField name="RF0W" description="Rx FIFO 0 watermark reached" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF0F" description="Rx FIFO 0 full" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="RF1N" description="Rx FIFO 1 new message" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No new message written to Rx FIFO 1" start="0x0" />
+        <Enum name="B_0x1" description="New message written to Rx FIFO 1" start="0x1" />
+      </BitField>
+      <BitField name="RF1W" description="Rx FIFO 1 watermark reached" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="RF1F" description="Rx FIFO 1 full" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0" start="0x1" />
+      </BitField>
+      <BitField name="HPM" description="High priority message" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No high priority message received" start="0x0" />
+        <Enum name="B_0x1" description="High priority message received" start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission completed" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission completed" start="0x0" />
+        <Enum name="B_0x1" description="Transmission completed" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="Transmission cancellation finished" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission cancellation finished" start="0x0" />
+        <Enum name="B_0x1" description="Transmission cancellation finished" start="0x1" />
+      </BitField>
+      <BitField name="TFE" description="Tx FIFO empty" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO non-empty" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty" start="0x1" />
+      </BitField>
+      <BitField name="TEFN" description="Tx event FIFO new entry" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Tx handler wrote Tx event FIFO element" start="0x1" />
+      </BitField>
+      <BitField name="TEFW" description="Tx event FIFO watermark reached" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO fill level below watermark" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO fill level reached watermark" start="0x1" />
+      </BitField>
+      <BitField name="TEFF" description="Tx event FIFO full" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx event FIFO element lost" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0" start="0x1" />
+      </BitField>
+      <BitField name="TSW" description="Timestamp wraparound" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timestamp counter wraparound" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp counter wraparound" start="0x1" />
+      </BitField>
+      <BitField name="MRAF" description="Message RAM access failure" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM access failure occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM access failure occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOO" description="Timeout occurred" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No timeout" start="0x0" />
+        <Enum name="B_0x1" description="Timeout reached" start="0x1" />
+      </BitField>
+      <BitField name="DRX" description="Message stored to dedicated Rx buffer" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx buffer updated" start="0x0" />
+        <Enum name="B_0x1" description="At least one received message stored into a Rx buffer" start="0x1" />
+      </BitField>
+      <BitField name="ELO" description="Error logging overflow" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CAN error logging counter did not overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow of CAN error logging counter occurred" start="0x1" />
+      </BitField>
+      <BitField name="EP" description="Error passive" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Passive status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Passive status changed" start="0x1" />
+      </BitField>
+      <BitField name="EW" description="Warning status" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error_Warning status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Error_Warning status changed" start="0x1" />
+      </BitField>
+      <BitField name="BO" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bus_Off status unchanged" start="0x0" />
+        <Enum name="B_0x1" description="Bus_Off status changed" start="0x1" />
+      </BitField>
+      <BitField name="WDI" description="Watchdog interrupt" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No message RAM watchdog event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Message RAM watchdog event due to missing READY" start="0x1" />
+      </BitField>
+      <BitField name="PEA" description="Protocol error in arbitration phase (nominal bit time is used)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in arbitration phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in arbitration phase detected (PSR.LEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="PED" description="Protocol error in data phase (data bit time is used)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No protocol error in data phase" start="0x0" />
+        <Enum name="B_0x1" description="Protocol error in data phase detected (PSR.DLEC different from 0,7)" start="0x1" />
+      </BitField>
+      <BitField name="ARA" description="Access to reserved address" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No access to reserved address occurred" start="0x0" />
+        <Enum name="B_0x1" description="Access to reserved address occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN interrupt enable register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 new message interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0WE" description="Rx FIFO 0 watermark reached interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0FE" description="Rx FIFO 0 full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF0LE" description="Rx FIFO 0 message lost interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1NE" description="Rx FIFO 1 new message interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1WE" description="Rx FIFO 1 watermark reached interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1FE" description="Rx FIFO 1 full interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RF1LE" description="Rx FIFO 1 message lost interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPME" description="High priority message interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCE" description="Transmission completed interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCFE" description="Transmission cancellation finished interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TFEE" description="Tx FIFO empty interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFNE" description="Tx event FIFO new entry interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFWE" description="Tx event FIFO watermark reached interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFFE" description="Tx event FIFO full interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEFLE" description="Tx event FIFO element lost interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSWE" description="Timestamp wraparound interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRAFE" description="Message RAM access failure interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOOE" description="Timeout occurred interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DRXE" description="Message stored to dedicated Rx buffer interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELOE" description="Error logging overflow interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EPE" description="Error passive interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EWE" description="Warning status interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOE" description="Bus_Off status" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDIE" description="Watchdog interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEAE" description="Protocol error in Arbitration phase enable" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDE" description="Protocol error in data phase enable" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAE" description="Access to Reserved address enable" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN interrupt line select register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 new message interrupt line" start="0" size="1" access="Read/Write" />
+      <BitField name="RF0WL" description="Rx FIFO 0 watermark reached interrupt line" start="1" size="1" access="Read/Write" />
+      <BitField name="RF0FL" description="Rx FIFO 0 full interrupt line" start="2" size="1" access="Read/Write" />
+      <BitField name="RF0LL" description="Rx FIFO 0 message lost interrupt line" start="3" size="1" access="Read/Write" />
+      <BitField name="RF1NL" description="Rx FIFO 1 new message interrupt line" start="4" size="1" access="Read/Write" />
+      <BitField name="RF1WL" description="Rx FIFO 1 watermark reached interrupt line" start="5" size="1" access="Read/Write" />
+      <BitField name="RF1FL" description="Rx FIFO 1 full interrupt line" start="6" size="1" access="Read/Write" />
+      <BitField name="RF1LL" description="Rx FIFO 1 message lost interrupt line" start="7" size="1" access="Read/Write" />
+      <BitField name="HPML" description="High priority message interrupt line" start="8" size="1" access="Read/Write" />
+      <BitField name="TCL" description="Transmission completed interrupt line" start="9" size="1" access="Read/Write" />
+      <BitField name="TCFL" description="Transmission cancellation finished interrupt line" start="10" size="1" access="Read/Write" />
+      <BitField name="TFEL" description="Tx FIFO empty interrupt line" start="11" size="1" access="Read/Write" />
+      <BitField name="TEFNL" description="Tx event FIFO new entry interrupt line" start="12" size="1" access="Read/Write" />
+      <BitField name="TEFWL" description="Tx event FIFO watermark reached interrupt line" start="13" size="1" access="Read/Write" />
+      <BitField name="TEFFL" description="Tx event FIFO full interrupt line" start="14" size="1" access="Read/Write" />
+      <BitField name="TEFLL" description="Tx event FIFO element Lost interrupt line" start="15" size="1" access="Read/Write" />
+      <BitField name="TSWL" description="Timestamp wraparound interrupt line" start="16" size="1" access="Read/Write" />
+      <BitField name="MRAFL" description="Message RAM access failure interrupt line" start="17" size="1" access="Read/Write" />
+      <BitField name="TOOL" description="Timeout occurred interrupt line" start="18" size="1" access="Read/Write" />
+      <BitField name="DRXL" description="Message stored to dedicated Rx buffer interrupt line" start="19" size="1" access="Read/Write" />
+      <BitField name="ELOL" description="Error logging overflow interrupt line" start="22" size="1" access="Read/Write" />
+      <BitField name="EPL" description="Error passive interrupt line" start="23" size="1" access="Read/Write" />
+      <BitField name="EWL" description="Warning status interrupt line" start="24" size="1" access="Read/Write" />
+      <BitField name="BOL" description="Bus_Off status" start="25" size="1" access="Read/Write" />
+      <BitField name="WDIL" description="Watchdog interrupt line" start="26" size="1" access="Read/Write" />
+      <BitField name="PEAL" description="Protocol error in arbitration phase line" start="27" size="1" access="Read/Write" />
+      <BitField name="PEDL" description="Protocol error in data phase line" start="28" size="1" access="Read/Write" />
+      <BitField name="ARAL" description="Access to reserved address line" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN interrupt line enable register" start="+0x005C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable interrupt line 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr0_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr0_it enabled" start="0x1" />
+      </BitField>
+      <BitField name="EINT1" description="Enable interrupt line 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt line fdcan_intr1_it disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt line fdcan_intr1_it enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN global filter configuration register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject remote frames extended" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 29-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 29-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="RRFS" description="Reject remote frames standard" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Filter remote frames with 11-bit standard ID" start="0x0" />
+        <Enum name="B_0x1" description="Reject all remote frames with 11-bit standard ID" start="0x1" />
+      </BitField>
+      <BitField name="ANFE" description="Accept non-matching frames extended" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+      <BitField name="ANFS" description="Accept non-matching frames standard" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Accept in Rx FIFO 0" start="0x0" />
+        <Enum name="B_0x1" description="Accept in Rx FIFO 1" start="0x1" />
+        <Enum name="B_0x2" description="Reject" start="0x2" />
+        <Enum name="B_0x3" description="Reject" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN standard ID filter configuration register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter list standard start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSS" description="List size standard" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No standard message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN extended ID filter configuration register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter list extended start address" start="2" size="14" access="Read/Write" />
+      <BitField name="LSE" description="List size extended" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No extended message ID filter" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN extended ID and mask register" start="+0x0090" size="4" reset_value="0x1FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN high priority message status register" start="+0x0094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer index" start="0" size="6" access="ReadOnly" />
+      <BitField name="MSI" description="Message storage indicator" start="6" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO selected" start="0x0" />
+        <Enum name="B_0x1" description="FIFO overrun" start="0x1" />
+        <Enum name="B_0x2" description="Message stored in FIFO 0" start="0x2" />
+        <Enum name="B_0x3" description="Message stored in FIFO 1" start="0x3" />
+      </BitField>
+      <BitField name="FIDX" description="Filter index" start="8" size="7" access="ReadOnly" />
+      <BitField name="FLST" description="Filter list" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Standard filter list" start="0x0" />
+        <Enum name="B_0x1" description="Extended filter list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN new data 1 register" start="+0x0098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data[31:0]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND1" description="New data[31:0]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND2" description="New data[31:0]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND3" description="New data[31:0]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND4" description="New data[31:0]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND5" description="New data[31:0]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND6" description="New data[31:0]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND7" description="New data[31:0]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND8" description="New data[31:0]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND9" description="New data[31:0]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND10" description="New data[31:0]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND11" description="New data[31:0]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND12" description="New data[31:0]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND13" description="New data[31:0]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND14" description="New data[31:0]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND15" description="New data[31:0]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND16" description="New data[31:0]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND17" description="New data[31:0]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND18" description="New data[31:0]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND19" description="New data[31:0]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND20" description="New data[31:0]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND21" description="New data[31:0]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND22" description="New data[31:0]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND23" description="New data[31:0]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND24" description="New data[31:0]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND25" description="New data[31:0]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND26" description="New data[31:0]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND27" description="New data[31:0]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND28" description="New data[31:0]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND29" description="New data[31:0]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND30" description="New data[31:0]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND31" description="New data[31:0]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN new data 2 register" start="+0x009C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data[63:32]" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND33" description="New data[63:32]" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND34" description="New data[63:32]" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND35" description="New data[63:32]" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND36" description="New data[63:32]" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND37" description="New data[63:32]" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND38" description="New data[63:32]" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND39" description="New data[63:32]" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND40" description="New data[63:32]" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND41" description="New data[63:32]" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND42" description="New data[63:32]" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND43" description="New data[63:32]" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND44" description="New data[63:32]" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND45" description="New data[63:32]" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND46" description="New data[63:32]" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND47" description="New data[63:32]" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND48" description="New data[63:32]" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND49" description="New data[63:32]" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND50" description="New data[63:32]" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND51" description="New data[63:32]" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND52" description="New data[63:32]" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND53" description="New data[63:32]" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND54" description="New data[63:32]" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND55" description="New data[63:32]" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND56" description="New data[63:32]" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND57" description="New data[63:32]" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND58" description="New data[63:32]" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND59" description="New data[63:32]" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND60" description="New data[63:32]" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND61" description="New data[63:32]" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND62" description="New data[63:32]" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+      <BitField name="ND63" description="New data[63:32]" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx buffer not updated" start="0x0" />
+        <Enum name="B_0x1" description="Rx buffer updated from new message" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 configuration register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F0S" description="Rx FIFO 0 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0" start="0x0" />
+      </BitField>
+      <BitField name="F0WM" description="FIFO 0 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F0OM" description="FIFO 0 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 0 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 0 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 status register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 fill level" start="0" size="7" access="Read/Write" />
+      <BitField name="F0GI" description="Rx FIFO 0 get index" start="8" size="6" access="Read/Write" />
+      <BitField name="F0PI" description="Rx FIFO 0 put index" start="16" size="6" access="Read/Write" />
+      <BitField name="F0F" description="Rx FIFO 0 full" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO 0 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 full" start="0x1" />
+      </BitField>
+      <BitField name="RF0L" description="Rx FIFO 0 message lost" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 0 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF0A" description="FDCAN Rx FIFO 0 acknowledge register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0AI" description="Rx FIFO 0 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx buffer configuration register" start="+0x00AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx buffer start address" start="2" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 configuration register" start="+0x00B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 start address" start="2" size="14" access="Read/Write" />
+      <BitField name="F1S" description="Rx FIFO 1 size" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No Rx FIFO 1" start="0x0" />
+      </BitField>
+      <BitField name="F1WM" description="Rx FIFO 1 watermark" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+      <BitField name="F1OM" description="FIFO 1 operation mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO 1 blocking mode" start="0x0" />
+        <Enum name="B_0x1" description="FIFO 1 overwrite mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 status register" start="+0x00B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 fill level" start="0" size="7" access="ReadOnly" />
+      <BitField name="F1GI" description="Rx FIFO 1 get index" start="8" size="6" access="ReadOnly" />
+      <BitField name="F1PI" description="Rx FIFO 1 put index" start="16" size="6" access="ReadOnly" />
+      <BitField name="F1F" description="Rx FIFO 1 full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx FIFO 1 not full" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 full" start="0x1" />
+      </BitField>
+      <BitField name="RF1L" description="Rx FIFO 1 message lost" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Rx FIFO 1 message lost" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0." start="0x1" />
+      </BitField>
+      <BitField name="DMS" description="Debug message status" start="30" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle state, wait for reception of debug messages" start="0x0" />
+        <Enum name="B_0x1" description="Debug message A received" start="0x1" />
+        <Enum name="B_0x2" description="Debug messages A, B received" start="0x2" />
+        <Enum name="B_0x3" description="Debug messages A, B, C received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 acknowledge register" start="+0x00B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 acknowledge index" start="0" size="6" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx buffer element size configuration register" start="+0x00BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 data field size" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="F1DS" description="Rx FIFO 0 data field size" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+      <BitField name="RBDS" description="Rx buffer data field size" start="8" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx buffer configuration register" start="+0x00C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx buffers start address" start="2" size="14" access="Read/Write" />
+      <BitField name="NDTB" description="Number of dedicated transmit buffers" start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No dedicated Tx buffers" start="0x0" />
+      </BitField>
+      <BitField name="TFQS" description="Transmit FIFO/queue size" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No Tx FIFO/queue" start="0x0" />
+      </BitField>
+      <BitField name="TFQM" description="Tx FIFO/queue mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO operation" start="0x0" />
+        <Enum name="B_0x1" description="Tx queue operation." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/queue status register" start="+0x00C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO free level" start="0" size="6" access="ReadOnly" />
+      <BitField name="TFGI" description="Tx FIFO get index." start="8" size="5" access="ReadOnly" />
+      <BitField name="TFQPI" description="Tx FIFO/queue put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="TFQF" description="Tx FIFO/queue full" start="21" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx buffer element size configuration register" start="+0x00C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx buffer data Field size:" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="8-byte data field" start="0x0" />
+        <Enum name="B_0x1" description="12-byte data field" start="0x1" />
+        <Enum name="B_0x2" description="16-byte data field" start="0x2" />
+        <Enum name="B_0x3" description="20-byte data field" start="0x3" />
+        <Enum name="B_0x4" description="24-byte data field" start="0x4" />
+        <Enum name="B_0x5" description="32-byte data field" start="0x5" />
+        <Enum name="B_0x6" description="48-byte data field" start="0x6" />
+        <Enum name="B_0x7" description="64-byte data field" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx buffer request pending register" start="+0x00CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission request pending" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission request pending" start="0x0" />
+        <Enum name="B_0x1" description="Transmission request pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx buffer add request register" start="+0x00D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No transmission request added" start="0x0" />
+        <Enum name="B_0x1" description="Transmission requested added." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx buffer cancellation request register" start="+0x00D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation request" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="No cancellation pending" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx buffer transmission occurred register" start="+0x00D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission occurred" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmission occurred" start="0x0" />
+        <Enum name="B_0x1" description="Transmission occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx buffer cancellation finished register" start="+0x00DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation finished" start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit buffer cancellation" start="0x0" />
+        <Enum name="B_0x1" description="Transmit buffer cancellation finished" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx buffer transmission interrupt enable register" start="+0x00E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmission interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx buffer cancellation finished interrupt enable register" start="+0x00E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFIE" description="Cancellation finished interrupt enable" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="Cancellation finished interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Cancellation finished interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx event FIFO configuration register" start="+0x00F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO start address" start="2" size="14" access="Read/Write" />
+      <BitField name="EFS" description="Event FIFO size." start="16" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Tx event FIFO disabled" start="0x0" />
+      </BitField>
+      <BitField name="EFWM" description="Event FIFO watermark" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Watermark interrupt disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx event FIFO status register" start="+0x00F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO fill level" start="0" size="6" access="ReadOnly" />
+      <BitField name="EFGI" description="Event FIFO get index" start="8" size="5" access="ReadOnly" />
+      <BitField name="EFPI" description="Event FIFO put index" start="16" size="5" access="ReadOnly" />
+      <BitField name="EFF" description="Event FIFO full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Tx event FIFO not full" start="0x0" />
+        <Enum name="B_0x1" description="Tx event FIFO full" start="0x1" />
+      </BitField>
+      <BitField name="TEFL" description="Tx event FIFO element lost" start="25" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx event FIFO acknowledge register" start="+0x00F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO acknowledge index" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT trigger memory configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger memory start address." start="2" size="14" access="Read/Write" />
+      <BitField name="TME" description="Trigger memory elements" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger memory" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT reference message configuration register" start="+0x0104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference identifier." start="0" size="29" access="Read/Write" />
+      <BitField name="XTD" description="Extended identifier" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="11-bit standard identifier" start="0x0" />
+        <Enum name="B_0x1" description="29-bit extended identifier" start="0x1" />
+      </BitField>
+      <BitField name="RMPS" description="Reference message payload select" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reference message has no additional payload" start="0x0" />
+        <Enum name="B_0x1" description="The following elements are taken from Tx buffer 0:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT operation configuration register" start="+0x0108" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation mode." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Event-driven CAN communication, default" start="0x0" />
+        <Enum name="B_0x1" description="TTCAN level 1" start="0x1" />
+        <Enum name="B_0x2" description="TTCAN level 2" start="0x2" />
+        <Enum name="B_0x3" description="TTCAN level 0" start="0x3" />
+      </BitField>
+      <BitField name="GEN" description="Gap enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Strictly time-triggered operation" start="0x0" />
+        <Enum name="B_0x1" description="External event-synchronized time-triggered operation" start="0x1" />
+      </BitField>
+      <BitField name="TM" description="Time master." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time master function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Potential time master" start="0x1" />
+      </BitField>
+      <BitField name="LDSDL" description="LD of synchronization deviation limit." start="5" size="3" access="Read/Write" />
+      <BitField name="IRTO" description="Initial reference trigger offset." start="8" size="7" access="Read/Write" />
+      <BitField name="EECS" description="Enable external clock synchronization" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock synchronization in FDCAN level 0, 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock synchronization in FDCAN level 0, 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog limit." start="16" size="8" access="Read/Write" />
+      <BitField name="EGTF" description="Enable global time filtering." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Global time filtering in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Global time filtering in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ECC" description="Enable clock calibration." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic clock calibration in FDCAN level 0, 2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic clock calibration in FDCAN level 0, 2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="EVTP" description="Event trigger polarity." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT matrix limits register" start="+0x010C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle count Max" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 basic cycle per matrix cycle" start="0x00" />
+        <Enum name="B_0x01" description="2 basic cycles per matrix cycle" start="0x01" />
+        <Enum name="B_0x03" description="4 basic cycles per matrix cycle" start="0x03" />
+        <Enum name="B_0x07" description="8 basic cycles per matrix cycle" start="0x07" />
+        <Enum name="B_0x0F" description="16 basic cycles per matrix cycle" start="0x0F" />
+        <Enum name="B_0x1F" description="32 basic cycles per matrix cycle" start="0x1F" />
+        <Enum name="B_0x3F" description="64 basic cycles per matrix cycle" start="0x3F" />
+      </BitField>
+      <BitField name="CSS" description="Cycle start synchronization" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No sync pulse" start="0x0" />
+        <Enum name="B_0x1" description="Sync pulse at start of basic cycle" start="0x1" />
+        <Enum name="B_0x2" description="Sync pulse at start of matrix cycle" start="0x2" />
+      </BitField>
+      <BitField name="TXEW" description="Tx enable window" start="8" size="4" access="Read/Write" />
+      <BitField name="ENTT" description="Expected number of Tx triggers" start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR configuration register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator configuration low." start="0" size="16" access="Read/Write" />
+      <BitField name="DC" description="Denominator configuration." start="16" size="14" access="Read/Write">
+        <Enum name="B_0x0000" description="Illegal value" start="0x0000" />
+      </BitField>
+      <BitField name="ELT" description="Enable local time." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Local time is stopped, default" start="0x0" />
+        <Enum name="B_0x1" description="Local time is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT operation control register" start="+0x0114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set global time." start="0" size="1" access="Read/Write" />
+      <BitField name="ECS" description="External clock synchronization." start="1" size="1" access="Read/Write" />
+      <BitField name="SWP" description="Stop watch polarity." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rising edge trigger" start="0x0" />
+        <Enum name="B_0x1" description="Falling edge trigger" start="0x1" />
+      </BitField>
+      <BitField name="SWS" description="Stop watch source." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Stop watch disabled" start="0x0" />
+        <Enum name="B_0x1" description="Actual value of cycle time is copied to FDCAN_TTCPT.SWV" start="0x1" />
+        <Enum name="B_0x2" description="Actual value of local time is copied to FDCAN_TTCPT.SWV" start="0x2" />
+        <Enum name="B_0x3" description="Actual value of global time is copied to FDCAN_TTCPT.SWV" start="0x3" />
+      </BitField>
+      <BitField name="RTIE" description="Register time mark interrupt pulse enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Register time mark interrupt output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt output enabled" start="0x1" />
+      </BitField>
+      <BitField name="TMC" description="Register time mark compare." start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No Register time mark interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="Register time mark interrupt if time mark = cycle time" start="0x1" />
+        <Enum name="B_0x2" description="Register time mark interrupt if time mark = local time" start="0x2" />
+        <Enum name="B_0x3" description="Register time mark interrupt if time mark = global time" start="0x3" />
+      </BitField>
+      <BitField name="TTIE" description="Trigger time mark interrupt pulse enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger time mark interrupt output fdcan1_tmp for more than one instance and fdcan_tmp if only one instance enabled" start="0x1" />
+      </BitField>
+      <BitField name="GCS" description="Gap control select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gap control independent from event trigger" start="0x0" />
+        <Enum name="B_0x1" description="Gap control by input event trigger pin" start="0x1" />
+      </BitField>
+      <BitField name="FGP" description="Finish gap." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No reference message requested" start="0x0" />
+        <Enum name="B_0x1" description="Application requested start of reference message" start="0x1" />
+      </BitField>
+      <BitField name="TMG" description="Time mark gap." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset by each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Next reference message started when register time mark interrupt FDCAN_TTIR.RTMI is activated" start="0x1" />
+      </BitField>
+      <BitField name="NIG" description="Next is gap." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action, reset by reception of any reference message" start="0x0" />
+        <Enum name="B_0x1" description="Transmit next reference message with Next_is_Gap = 1" start="0x1" />
+      </BitField>
+      <BitField name="ESCN" description="External synchronization control" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External synchronization disabled" start="0x0" />
+        <Enum name="B_0x1" description="External synchronization enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCKC" description="TT operation control register locked." start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTOCN enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTOCN locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTGTP" description="FDCAN TT global time preset register" start="+0x0118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TP" description="Time preset" start="0" size="16" access="Read/Write" />
+      <BitField name="CTP" description="Cycle time target phase" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT time mark register" start="+0x011C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time mark" start="0" size="16" access="Read/Write" />
+      <BitField name="TICC" description="Time mark cycle code" start="16" size="7" access="Read/Write" />
+      <BitField name="LCKM" description="TT time mark register locked" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write access to FDCAN_TTTMK enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to FDCAN_TTTMK locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT interrupt register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of basic cycle" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No basic cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Basic cycle started" start="0x1" />
+      </BitField>
+      <BitField name="SMC" description="Start of matrix cycle" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No matrix cycle started since bit has been reset" start="0x0" />
+        <Enum name="B_0x1" description="Matrix cycle started" start="0x1" />
+      </BitField>
+      <BitField name="CSM" description="Change of synchronization mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in master to slave relation or schedule synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Master to slave relation or schedule synchronization changed," start="0x1" />
+      </BitField>
+      <BitField name="SOG" description="Start of gap" start="3" size="1" access="Read/Write" />
+      <BitField name="RTMI" description="Register time mark interrupt" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached" start="0x1" />
+      </BitField>
+      <BitField name="TTMI" description="Trigger time mark event internal" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Time mark not reached" start="0x0" />
+        <Enum name="B_0x1" description="Time mark reached (level 0: cycle time FDCAN_TTOCF.RTO x 0x200)" start="0x1" />
+      </BitField>
+      <BitField name="SWE" description="Stop watch event" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No rising/falling edge at stop watch trigger pin detected" start="0x0" />
+        <Enum name="B_0x1" description="Rising/falling edge at stop watch trigger pin detected" start="0x1" />
+      </BitField>
+      <BitField name="GTW" description="Global time wrap" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No global time wrap occurred" start="0x0" />
+        <Enum name="B_0x1" description="Global time wrap from 0xFFFF to 0x0000 occurred" start="0x1" />
+      </BitField>
+      <BitField name="GTD" description="Global time discontinuity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No discontinuity of global time" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuity of global time" start="0x1" />
+      </BitField>
+      <BitField name="GTE" description="Global time error" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Synchronization deviation within limit" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation exceeded limit" start="0x1" />
+      </BitField>
+      <BitField name="TXU" description="Tx count underflow" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="Less Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="TXO" description="Tx count overflow" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Number of Tx trigger as expected" start="0x0" />
+        <Enum name="B_0x1" description="More Tx trigger than expected in one cycle" start="0x1" />
+      </BitField>
+      <BitField name="SE1" description="Scheduling error 1" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 1" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 1 occurred" start="0x1" />
+      </BitField>
+      <BitField name="SE2" description="Scheduling error 2" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No scheduling error 2" start="0x0" />
+        <Enum name="B_0x1" description="Scheduling error 2 occurred" start="0x1" />
+      </BitField>
+      <BitField name="ELC" description="Error level changed" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No change in error level" start="0x0" />
+        <Enum name="B_0x1" description="Error level changed" start="0x1" />
+      </BitField>
+      <BitField name="IWTG" description="Initialization watch trigger" start="15" size="1" access="Read/Write" />
+      <BitField name="WT" description="Watch trigger" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No missing reference message" start="0x0" />
+        <Enum name="B_0x1" description="Missing reference message (level 0: cycle time 0xFF00)" start="0x1" />
+      </BitField>
+      <BitField name="AW" description="Application watchdog" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Application watchdog not served in time" start="0x1" />
+      </BitField>
+      <BitField name="CER" description="Configuration error" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No error found in trigger list" start="0x0" />
+        <Enum name="B_0x1" description="Error found in trigger list" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT interrupt enable register" start="+0x0124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of basic cycle interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMCE" description="Start of matrix cycle interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSME" description="Change of synchronization mode interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SOGE" description="Start of gap interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTMIE" description="Register time mark interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TTMIE" description="Trigger time mark event internal interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWEE" description="Stop watch event interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTWE" description="Global time wrap interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTDE" description="Global time discontinuity interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GTEE" description="Global time error interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUE" description="Tx count underflow interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXOE" description="Tx count overflow interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE1E" description="Scheduling error 1 interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SE2E" description="Scheduling error 2 interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ELCE" description="Change error level interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IWTE" description="Initialization watch trigger interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WTE" description="Watch trigger interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CERE" description="Configuration error interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT interrupt line select register" start="+0x0128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of basic cycle interrupt line" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SMCL" description="Start of matrix cycle interrupt line" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CSML" description="Change of synchronization mode interrupt line" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SOGL" description="Start of gap interrupt line" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="RTMIL" description="Register time mark interrupt line" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TTMIL" description="Trigger time mark event internal interrupt line" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SWEL" description="Stop watch event interrupt line" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTWL" description="Global time wrap interrupt line" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTDL" description="Global time discontinuity interrupt line" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="GTEL" description="Global time error interrupt line" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXUL" description="Tx count underflow interrupt line" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="TXOL" description="Tx count overflow interrupt line" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE1L" description="Scheduling error 1 interrupt line" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="SE2L" description="Scheduling error 2 interrupt line" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="ELCL" description="Change error level interrupt line" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="IWTL" description="Initialization watch trigger interrupt line" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="WTL" description="Watch trigger interrupt line" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="AWL" description="Application watchdog interrupt line" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+      <BitField name="CERL" description="Configuration error interrupt line" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TT interrupt assigned to interrupt line 0" start="0x0" />
+        <Enum name="B_0x1" description="TT interrupt assigned to interrupt line 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT operation status register" start="+0x012C" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error level" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Severity 0 - No error" start="0x0" />
+        <Enum name="B_0x1" description="Severity 1 - Warning" start="0x1" />
+        <Enum name="B_0x2" description="Severity 2 - error" start="0x2" />
+        <Enum name="B_0x3" description="Severity 3 - Severe error" start="0x3" />
+      </BitField>
+      <BitField name="MS" description="Master state" start="2" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Master_Off, no master properties relevant" start="0x0" />
+        <Enum name="B_0x1" description="Operating as time Slave" start="0x1" />
+        <Enum name="B_0x2" description="Operating as backup time master" start="0x2" />
+        <Enum name="B_0x3" description="Operating as current time master" start="0x3" />
+      </BitField>
+      <BitField name="SYS" description="Synchronization state" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Out of Synchronization" start="0x0" />
+        <Enum name="B_0x1" description="Synchronizing to FDCAN communication" start="0x1" />
+        <Enum name="B_0x2" description="Schedule suspended by gap (In_Gap)" start="0x2" />
+        <Enum name="B_0x3" description="Synchronized to schedule (In_Schedule)" start="0x3" />
+      </BitField>
+      <BitField name="QGTP" description="Quality of global time phase" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Global time not valid" start="0x0" />
+        <Enum name="B_0x1" description="Global time in phase with time master" start="0x1" />
+      </BitField>
+      <BitField name="QCS" description="Quality of clock speed" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Local clock speed not synchronized to time master clock speed" start="0x0" />
+        <Enum name="B_0x1" description="Synchronization deviation less than or equal to SDL" start="0x1" />
+      </BitField>
+      <BitField name="RTO" description="Reference trigger offset" start="8" size="8" access="ReadOnly" />
+      <BitField name="WGTD" description="Wait for global time discontinuity" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No global time preset pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message." start="0x1" />
+      </BitField>
+      <BitField name="GFI" description="Gap finished indicator" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Reset at the end of each reference message" start="0x0" />
+        <Enum name="B_0x1" description="Gap finished by FDCAN" start="0x1" />
+      </BitField>
+      <BitField name="TMP" description="Time master priority" start="24" size="3" access="ReadOnly" />
+      <BitField name="GSI" description="Gap started indicator" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap in schedule, reset by each reference message and for all time slaves" start="0x0" />
+        <Enum name="B_0x1" description="Gap time after basic cycle has started" start="0x1" />
+      </BitField>
+      <BitField name="WFE" description="Wait for event" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No gap announced, reset by a reference message with Next_is_Gap = 0" start="0x0" />
+        <Enum name="B_0x1" description="Reference message with Next_is_Gap = 1 received" start="0x1" />
+      </BitField>
+      <BitField name="AWE" description="Application watchdog event" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Application watchdog served in time" start="0x0" />
+        <Enum name="B_0x1" description="Failed to serve application watchdog in time" start="0x1" />
+      </BitField>
+      <BitField name="WECS" description="Wait for external clock synchronization." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No external clock synchronization pending" start="0x0" />
+        <Enum name="B_0x1" description="Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle." start="0x1" />
+      </BitField>
+      <BitField name="SPL" description="Schedule phase lock" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Phase outside range" start="0x0" />
+        <Enum name="B_0x1" description="Phase inside range" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR numerator actual register" start="+0x0130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator actual value" start="0" size="18" access="ReadOnly">
+        <Enum name="B_0x0EFFF" description="illegal value" start="0x0EFFF" />
+        <Enum name="B_0x21000" description="illegal value" start="0x21000" />
+      </BitField>
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT local and global time register" start="+0x0134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local time" start="0" size="16" access="ReadOnly" />
+      <BitField name="GT" description="Global time" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT cycle time and count register" start="+0x0138" size="4" reset_value="0x003F0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle time" start="0" size="16" access="ReadOnly" />
+      <BitField name="CC" description="Cycle count" start="16" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT capture time register" start="+0x013C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCV" description="Cycle count value" start="0" size="6" access="ReadOnly" />
+      <BitField name="SWV" description="Stop watch value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT cycle sync mark register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle sync mark" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT trigger select register" start="+0x0300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_swt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_swt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_swt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_swt3" start="0x3" />
+      </BitField>
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="fdcan1_evt0" start="0x0" />
+        <Enum name="B_0x1" description="fdcan1_evt1" start="0x1" />
+        <Enum name="B_0x2" description="fdcan1_evt2" start="0x2" />
+        <Enum name="B_0x3" description="fdcan1_evt3" start="0x3" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FMC1" description="Flexible memory controller" start="0x48024000">
+    <Register name="FMC_BCR1" description="SRAM/NOR Flash chip-select control register for memory region 1" start="+0x0" size="4" reset_value="0x000030DB" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="NEx deasserted after 64 fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="NEx deasserted after 256 fmc_ker_ck clock cycles" start="0x3" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR1" description="SRAM/NOR Flash chip-select timing registers for memory region 1" start="+0x4" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR2" description="SRAM/NOR Flash chip-select control register for memory region 2" start="+0x8" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR2" description="SRAM/NOR Flash chip-select timing registers for memory region 2" start="+0xC" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR3" description="SRAM/NOR Flash chip-select control register for memory region 3" start="+0x10" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR3" description="SRAM/NOR Flash chip-select timing registers for memory region 3" start="+0x14" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR4" description="SRAM/NOR Flash chip-select control register for memory region 4" start="+0x18" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR4" description="SRAM/NOR Flash chip-select timing registers for memory region 4" start="+0x1C" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CFGR" description="FMC common configuration register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CCLKEN" description="Continuous clock enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is defined by the programmed CLKDIV value in the FMC_BCRx register (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The FMC_CLK is generated continuously during asynchronous and synchronous access." start="0x1" />
+      </BitField>
+      <BitField name="BMAP0" description="FMC memory region mapping" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default mapping (refer to Table 132)" start="0x0" />
+        <Enum name="B_0x1" description="Devices are remapped (refer to Table 133)" start="0x1" />
+      </BitField>
+      <BitField name="BMAP1" description="FMC memory region mapping" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default mapping (refer to Table 132)" start="0x0" />
+        <Enum name="B_0x1" description="Devices are remapped (refer to Table 133)" start="0x1" />
+      </BitField>
+      <BitField name="FMCEN" description="FMC controller enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC controller disabled" start="0x0" />
+        <Enum name="B_0x1" description="FMC controller enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PCR" description="NAND Flash programmable control register" start="+0x80" size="4" reset_value="0x0007FE08" reset_mask="0xFFFFFFFF">
+      <BitField name="PWAITEN" description="Wait feature enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="disabled (default)" start="0x0" />
+        <Enum name="B_0x1" description="enabled" start="0x1" />
+      </BitField>
+      <BitField name="PBKEN" description="NAND Flash memory region enable bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled." start="0x1" />
+      </BitField>
+      <BitField name="PWID" description="Data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+      </BitField>
+      <BitField name="ECCEN" description="ECC computation logic enable bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC logic is disabled and reset (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="ECC logic is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ECCALG" description="ECC algorithm" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hamming code is selected (default)." start="0x0" />
+        <Enum name="B_0x1" description="BCH code is selected." start="0x1" />
+      </BitField>
+      <BitField name="TCLR" description="CLE to RE delay." start="9" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0xF" description="16 * fmc_ker_ck cycles (default)" start="0xF" />
+      </BitField>
+      <BitField name="TAR" description="ALE to RE delay." start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0xF" description="16 * fmc_ker_ck cycles (default)" start="0xF" />
+      </BitField>
+      <BitField name="ECCSS" description="ECC sector size (used to access spare area)" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="256 bytes" start="0x0" />
+        <Enum name="B_0x1" description="512 bytes" start="0x1" />
+        <Enum name="B_0x2" description="1024 bytes" start="0x2" />
+        <Enum name="B_0x3" description="2048 bytes (default)" start="0x3" />
+        <Enum name="B_0x4" description="4096 bytes" start="0x4" />
+      </BitField>
+      <BitField name="BCHECC" description="BCH error correction capability" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit BCH (4-bit error correction and 8-bit error detection per 512 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="8-bit BCH (8-bit error correction and 16-bit error detection per 512 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="WEN" description="Write enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read access enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SR" description="FMC status register" start="+0x84" size="4" reset_value="0x00000053" reset_mask="0xFFFFFFFF">
+      <BitField name="ISOST" description="FMC isolation state with respect to the AXI interface" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="FMC is not isolated; AXI transactions are treated by the FMC and its controllers." start="0x0" />
+        <Enum name="B_0x1" description="FMC has been enabled (FMCEN = 1) and waits for the end of pending AXI transactions (which leads to error responses) before going to non-isolated state." start="0x1" />
+        <Enum name="B_0x2" description="FMC has been disabled (FMCEN = 0) and waits for the end of pending AXI transactions before going to isolation state." start="0x2" />
+        <Enum name="B_0x3" description="FMC is isolated from its AXI interface. All AXI requests lead to error responses." start="0x3" />
+      </BitField>
+      <BitField name="PEF" description="Pipe Empty Flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="NWRF" description="NAND write request flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="NAND Flash write requests are pending" start="0x0" />
+        <Enum name="B_0x1" description="No NAND Flash write requests pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PMEM" description="FMC common memory space timing register" start="+0x88" size="4" reset_value="0x0A0A0A0A" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMSET" description="Common memory setup time" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycles" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+      <BitField name="MEMWAIT" description="Common memory wait time" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0xFF" />
+      </BitField>
+      <BitField name="MEMHOLD" description="Common memory hold time" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+      <BitField name="MEMHIZ" description="Common memory data bus Hi-Z time" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PATT" description="FMC attribute memory space timing registers" start="+0x8C" size="4" reset_value="0x0A0A0A0A" reset_mask="0xFFFFFFFF">
+      <BitField name="ATTSET" description="Attribute memory setup time" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles." start="0xFF" />
+      </BitField>
+      <BitField name="ATTWAIT" description="Attribute memory wait time" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle (+ wait cycle introduced by deassertion of NWAIT)" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT)" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0xFF" />
+      </BitField>
+      <BitField name="ATTHOLD" description="Attribute memory hold time" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles." start="0xFF" />
+      </BitField>
+      <BitField name="ATTHIZ" description="Attribute memory data bus Hi-Z time" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_HPR" description="FMC Hamming parity result registers" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPR" description="Hamming parity result" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_HECCR" description="FMC Hamming code ECC result register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HECC" description="ECC result" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BWTR1" description="SRAM/NOR-Flash write timing registers for memory region 1" start="+0x104" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR2" description="SRAM/NOR-Flash write timing registers for memory region 2" start="+0x10C" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR3" description="SRAM/NOR-Flash write timing registers for memory region 3" start="+0x114" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR4" description="SRAM/NOR-Flash write timing registers for memory region 4" start="+0x11C" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCR1" description="SDRAM control registers for SDRAM device 1" start="+0x140" size="4" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="9 bits" start="0x1" />
+        <Enum name="B_0x2" description="10 bits" start="0x2" />
+        <Enum name="B_0x3" description="11 bits." start="0x3" />
+      </BitField>
+      <BitField name="NR" description="Number of row address bits" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="11 bit" start="0x0" />
+        <Enum name="B_0x1" description="12 bits" start="0x1" />
+        <Enum name="B_0x2" description="13 bits" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width." start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="NB" description="Number of banks" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Two banks" start="0x0" />
+        <Enum name="B_0x1" description="Four banks" start="0x1" />
+      </BitField>
+      <BitField name="CAS" description="CAS Latency" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 cycles" start="0x3" />
+      </BitField>
+      <BitField name="WP" description="Write protection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write accesses allowed" start="0x0" />
+        <Enum name="B_0x1" description="Write accesses ignored" start="0x1" />
+      </BitField>
+      <BitField name="SDCLK" description="SDRAM clock configuration" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SDCLK clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDCLK period = 1 * fmc_ker_ck period" start="0x1" />
+        <Enum name="B_0x2" description="SDCLK period = 2 * fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0x3" description="SDCLK period = 3 * fmc_ker_ck periods" start="0x3" />
+      </BitField>
+      <BitField name="RPIPE" description="Read pipe" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No fmc_ker_ck clock cycle delay (default value)" start="0x0" />
+        <Enum name="B_0x1" description="One fmc_ker_ck clock cycle delay" start="0x1" />
+        <Enum name="B_0x2" description="Two fmc_ker_ck clock cycle delay" start="0x2" />
+      </BitField>
+      <BitField name="SDEN" description="SDRAM device enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="SDRAM device enabled" start="0x1" />
+        <Enum name="B_0x0" description="SDRAM disabled" start="0x0" />
+      </BitField>
+      <BitField name="SDINIT" description="SDRAM device initialization" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Initialization is complete and the device is ready to be accessed" start="0x1" />
+        <Enum name="B_0x0" description="Initialization is not complete, the AXI accesses are rejected and an AXI slave error is generated." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCR2" description="SDRAM control registers for SDRAM device 2" start="+0x144" size="4" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="9 bits" start="0x1" />
+        <Enum name="B_0x2" description="10 bits" start="0x2" />
+        <Enum name="B_0x3" description="11 bits." start="0x3" />
+      </BitField>
+      <BitField name="NR" description="Number of row address bits" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="11 bit" start="0x0" />
+        <Enum name="B_0x1" description="12 bits" start="0x1" />
+        <Enum name="B_0x2" description="13 bits" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width." start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="NB" description="Number of banks" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Two banks" start="0x0" />
+        <Enum name="B_0x1" description="Four banks" start="0x1" />
+      </BitField>
+      <BitField name="CAS" description="CAS Latency" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 cycles" start="0x3" />
+      </BitField>
+      <BitField name="WP" description="Write protection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write accesses allowed" start="0x0" />
+        <Enum name="B_0x1" description="Write accesses ignored" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="SDRAM device enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="SDRAM device enabled" start="0x1" />
+        <Enum name="B_0x0" description="SDRAM disabled" start="0x0" />
+      </BitField>
+      <BitField name="SDINIT" description="SDRAM device initialization" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Initialization is complete and the device is ready to be accessed" start="0x1" />
+        <Enum name="B_0x0" description="Initialization is not complete, the AXI accesses are rejected and an AXI slave error is generated." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDTR" description="SDRAM timing register" start="+0x148" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TMRD" description="Load mode register to active " start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TXSR" description="Exit self-refresh delay" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRAS" description="Self-refresh time" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRC" description="Row cycle delay" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TWR" description="Recovery delay" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRP" description="Row precharge delay" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRCD" description="Row to column delay" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle." start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCMR" description="SDRAM command mode register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="Command mode" start="0" size="3" access="WriteOnly">
+        <Enum name="B_0x0" description="Normal mode command (NRM)" start="0x0" />
+        <Enum name="B_0x2" description="Precharge all banks command (PALL)" start="0x2" />
+        <Enum name="B_0x3" description="Refresh command (REF)" start="0x3" />
+        <Enum name="B_0x4" description="Load mode register command (LMR)" start="0x4" />
+        <Enum name="B_0x5" description="Self-refresh command (SR)" start="0x5" />
+        <Enum name="B_0x6" description="Power-down command (PD)" start="0x6" />
+      </BitField>
+      <BitField name="DS2" description="Command targeting SDRAM device 2" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Command not issued to SDRAM device 2" start="0x0" />
+        <Enum name="B_0x1" description="Command issued to SDRAM device 2" start="0x1" />
+      </BitField>
+      <BitField name="DS1" description="Command targeting SDRAM device 1" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Command not issued to SDRAM device 1" start="0x0" />
+        <Enum name="B_0x1" description="Command issued to SDRAM device 1" start="0x1" />
+      </BitField>
+      <BitField name="NRFS" description="Number of Refresh commands" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 Refresh cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 Refresh cycles" start="0x1" />
+        <Enum name="B_0xE" description="15 Refresh cycles" start="0xE" />
+        <Enum name="B_0xF" description="16 Refresh cycles" start="0xF" />
+      </BitField>
+      <BitField name="MRD" description="Mode register definition" start="9" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FMC_SDRTR" description="SDRAM refresh timer register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRE" description="Clear Refresh error flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="Refresh Error flag is cleared" start="0x1" />
+      </BitField>
+      <BitField name="RFSCNT" description="Refresh Timer Count" start="1" size="13" access="Read/Write" />
+      <BitField name="REIE" description="RES Interrupt Enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated if RE = 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDSR" description="SDRAM status register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Refresh error flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No refresh error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="A refresh error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="MODES1" description="Status Mode for SDRAM device 1" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Normal mode, devices are not in Self-refresh or power-down" start="0x0" />
+        <Enum name="B_0x1" description="Self-refresh" start="0x1" />
+        <Enum name="B_0x2" description="Power-down" start="0x2" />
+      </BitField>
+      <BitField name="MODES2" description="Status mode for SDRAM device 2" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Normal mode, devices are not in Self-refresh or power-down" start="0x0" />
+        <Enum name="B_0x1" description="Self-refresh" start="0x1" />
+        <Enum name="B_0x2" description="Power-down" start="0x2" />
+      </BitField>
+      <BitField name="CMDOK" description="Previous command status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Command not complete" start="0x0" />
+        <Enum name="B_0x1" description="Command complete in the SDRAM clock domain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_IER" description="FMC NAND interrupt enable register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IREE" description="Interrupt rising edge detection enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt rising edge detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt rising edge detection request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IHLE" description="Interrupt high-level detection enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt high-level detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt high-level detection request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFEE" description="Interrupt falling edge detection enable bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt falling edge detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt falling edge detection request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_ISR" description="FMC controller interrupt status register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IREF" description="Interrupt rising edge flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt rising edge occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt rising edge occurred" start="0x1" />
+      </BitField>
+      <BitField name="IHLF" description="Interrupt high-level flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Interrupt high-level occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt high-level occurred" start="0x1" />
+      </BitField>
+      <BitField name="IFEF" description="Interrupt falling edge flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt falling edge occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt falling edge occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_ICR" description="FMC NAND controller interrupt clear register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CIREF" description="Clear Interrupt rising edge flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear the IREF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="CIHLF" description="Clear Interrupt high-level flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clears the IHLF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="CIFEF" description="Clear Interrupt falling edge flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clears the IFEF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCR" description="FMC NAND command sequencer control register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSQSTART" description="Command Sequencer Enable" start="0" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_CSQCFGR1" description="FMC NAND command sequencer configuration register 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMD2EN" description="Command cycle 2 Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command cycle 2 not issued." start="0x0" />
+        <Enum name="B_0x1" description="Command cycle 2 (programmed CMD2[7:0]) sent by the command sequencer to the NAND Flash memory after the address cycles." start="0x1" />
+      </BitField>
+      <BitField name="DMADEN" description="Command sequencer DMA request data enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No DMA request transfer" start="0x0" />
+        <Enum name="B_0x1" description="A DMA request transfer" start="0x1" />
+      </BitField>
+      <BitField name="ACYNBR" description="Address Cycle number " start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No address cycle." start="0x0" />
+        <Enum name="B_0x1" description="1 address cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 address cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 address cycles" start="0x3" />
+        <Enum name="B_0x4" description="4 address cycles" start="0x4" />
+        <Enum name="B_0x5" description="5 address cycles" start="0x5" />
+      </BitField>
+      <BitField name="CMD1" description="Command 1 sequencer" start="8" size="8" access="Read/Write" />
+      <BitField name="CMD2" description="Command 2 sequencer" start="16" size="8" access="Read/Write" />
+      <BitField name="CMD1T" description="Command 1 Sequencer timings" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="CMD2T" description="Command 2 Sequencer timings" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCFGR2" description="FMC NAND command sequencer configuration register 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQSDTEN" description="Sequencer spare data transfer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC disabled and spare data area not accessed by the sequencer" start="0x0" />
+        <Enum name="B_0x1" description="ECC enabled and spare data area read or programmed by the sequencer after each sector transfer" start="0x1" />
+      </BitField>
+      <BitField name="RCMD2EN" description="Random Command 2 sequencer enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command 2 not issued." start="0x0" />
+        <Enum name="B_0x1" description="Command 2 (CMD2SQ[7:0]) issued by the command sequencer to NAND flash memory after the address cycle." start="0x1" />
+      </BitField>
+      <BitField name="DMASEN" description="Command sequencer DMA request decoding status enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No DMA request used for ECC status registers transfer" start="0x0" />
+        <Enum name="B_0x1" description="A DMA request used for ECC status registers transfer" start="0x1" />
+      </BitField>
+      <BitField name="RCMD1" description="Random Command 1 sequencer" start="8" size="8" access="Read/Write" />
+      <BitField name="RCMD2" description="Random Command 2 sequencer" start="16" size="8" access="Read/Write" />
+      <BitField name="RCMD1T" description="Command 1 sequencer timings" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RCMD2T" description="Command 1 sequencer timings" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCFGR3" description="FMC NAND sequencer configuration register 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SNBR" description="Number of sectors to be read/written" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="1 sector" start="0x0" />
+        <Enum name="B_0x1" description="2 sectors" start="0x1" />
+        <Enum name="B_0x3F" description="16 sectors" start="0x3F" />
+      </BitField>
+      <BitField name="AC1T" description="Address cycle 1 sequencer timings" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC2T" description="Address cycle 2 sequencer timings" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC3T" description="Address cycle 3 sequencer timings" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC3 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC3 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC4T" description="Address cycle 4sequencer timings" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC4 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC4 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC5T" description="Address cycle 5 sequencer timings" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC5 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC5 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="SDT" description="Spare data transfer sequencer timings" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Spare data transfer issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Spare data transfer issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RAC1T" description="Random Address cycle 1 sequencer timings" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Random ADDC1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Random ADDC1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RAC2T" description="Random Address cycle 2 sequencer timings" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Random ADDC2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Random ADDC2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQAR1" description="FMC NAND command sequencer address register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDC1" description="Address Cycle 1" start="0" size="8" access="Read/Write" />
+      <BitField name="ADDC2" description="Address Cycle 2" start="8" size="8" access="Read/Write" />
+      <BitField name="ADDC3" description="Address Cycle 3" start="16" size="8" access="Read/Write" />
+      <BitField name="ADDC4" description="Address Cycle 4" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQAR2" description="FMC NAND command sequencer address register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDC5" description="Address Cycle 5" start="0" size="8" access="Read/Write" />
+      <BitField name="SAO" description="Spare Area Address Offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQIER" description="FMC NAND command sequencer interrupt enable register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIE" description="Transfer Complete Interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SCIE" description="Sector Complete interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sector Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Sector Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SEIE" description="Sector Error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sector Error Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Sector Error Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SUEIE" description="Sector Uncorrectable Error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Command Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="CMDTCIE" description="Command Transfer Complete interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Command Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQISR" description="FMC NAND command sequencer interrupt status register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="Transfer Complete flag" start="0" size="1" access="Read/Write" />
+      <BitField name="SCF" description="Sector Complete flag" start="1" size="1" access="Read/Write" />
+      <BitField name="SEF" description="Sector Error flag" start="2" size="1" access="Read/Write" />
+      <BitField name="SUEF" description="Sector Uncorrectable Error flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CMDTCF" description="Command Transfer Complete flag" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQICR" description="FMC NAND command sequencer interrupt clear register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCF" description="Clear Transfer Complete flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CSCF" description="Clear Sector Complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSEF" description="Clear Sector Error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CSUEF" description="Clear Sector uncorrectable Error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CCMDTCF" description="Clear Command Transfer Complete flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_CSQEMSR" description="FMC command sequencer error mapping status register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM" description="Sector Error mapping " start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHIER" description="FMC BCH interrupt enable register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUEIE" description="Decoder Uncorrectable Errors Interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Uncorrectable Errors Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Uncorrectable Errors Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DERIE" description="Decoder Error Ready Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Error Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Error Ready Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="Decoder Error Found Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Error Found Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Error Found Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DSRIE" description="Decoder Syndrome Ready Interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Syndrome Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Syndrome Ready Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="EPBRIE" description="Decoder Parity Bits Ready Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Parity Bits Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Parity Bits Ready Interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCHISR" description="FMC BCH interrupt and status register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUEF" description="Decoder Uncorrectable Errors flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="DERF" description="Decoder Error Ready flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="Decoder Error Found flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="DSRF" description="Decoder Syndrome Ready flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="EPBRF" description="Encoder Parity Bits Ready flag" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHICR" description="FMC BCH interrupt clear register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CDUEF" description="Clear Decoder Uncorrectable Error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CDERF" description="Clear Decoder Error ready flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CDEFF" description="Clear Decoder Error Found flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CDSRF" description="Clear Decoder Syndrome Ready flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CEPBRF" description="Clear Encoder Parity Bits Ready flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR1" description="FMC BCH parity bits register 1" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR2" description="FMC BCH parity bits register 2" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR3" description="FMC BCH parity bits register 3" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR4" description="FMC BCH parity bits register 4" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR0" description="FMC BCH decoder status register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUE" description="Decoder uncorrectable error" start="0" size="1" access="ReadOnly" />
+      <BitField name="DEF" description="Decoder error found" start="1" size="1" access="ReadOnly" />
+      <BitField name="DEN" description="Decoder error number" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR1" description="FMC BCH decoder status register for memory region 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP1" description="Error bit position for error number 1" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP2" description="Error bit position for error number 2" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR2" description="FMC BCH decoder status register for memory region 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP3" description="Error bit position for error number 3" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP4" description="Error bit position for error number 4" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR3" description="FMC BCH decoder status register for memory region 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP5" description="Error bit position for error number 5" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP6" description="Error bit position for error number 6" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR4" description="FMC BCH decoder status register for memory region 4" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP7" description="Error bit position for error number 7" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP8" description="Error bit position for error number 8" start="16" size="13" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FMC1_S" description="Flexible memory controller" start="0x58024000">
+    <Register name="FMC_BCR1" description="SRAM/NOR Flash chip-select control register for memory region 1" start="+0x0" size="4" reset_value="0x000030DB" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="NEx deasserted after 64 fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="NEx deasserted after 256 fmc_ker_ck clock cycles" start="0x3" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR1" description="SRAM/NOR Flash chip-select timing registers for memory region 1" start="+0x4" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR2" description="SRAM/NOR Flash chip-select control register for memory region 2" start="+0x8" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR2" description="SRAM/NOR Flash chip-select timing registers for memory region 2" start="+0xC" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR3" description="SRAM/NOR Flash chip-select control register for memory region 3" start="+0x10" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR3" description="SRAM/NOR Flash chip-select timing registers for memory region 3" start="+0x14" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCR4" description="SRAM/NOR Flash chip-select control register for memory region 4" start="+0x18" size="4" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory region enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address/Data non-multiplexed" start="0x0" />
+        <Enum name="B_0x1" description="Address/Data multiplexed on databus (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SRAM/ FRAM (default after reset for memory region 2...4)" start="0x0" />
+        <Enum name="B_0x1" description="PSRAM (CRAM)/FRAM" start="0x1" />
+        <Enum name="B_0x2" description="NOR Flash/OneNAND Flash (default after reset for memory region 1)" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="FACCEN" description="Flash memory access enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding NOR Flash memory access is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding NOR Flash memory access is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BURSTEN" description="Burst enable bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="Burst mode enable. Read accesses are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="WAITPOL" description="Wait signal polarity bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT active low (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT active high." start="0x1" />
+      </BitField>
+      <BitField name="WAITCFG" description="Wait timing configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal active one data cycle before wait state (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal active during wait state (not used for PSRAM)." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="Write enable bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations to the memory region by the FMC disabled. An AXI slave error is reported," start="0x0" />
+        <Enum name="B_0x1" description="Write operations to the memory region by the FMC enabled (default after reset)." start="0x1" />
+      </BitField>
+      <BitField name="WAITEN" description="Wait enable bit" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="EXTMOD" description="Extended mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Values inside FMC_BWTR register not taken into account (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Values inside FMC_BWTR register taken into account" start="0x1" />
+      </BitField>
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NWAIT signal not taken in to account during asynchronous transfers (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NWAIT signal taken in to account during asynchronous transfers" start="0x1" />
+      </BitField>
+      <BitField name="CPSIZE" description="CRAM page size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No burst split when crossing page boundary. (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="128 bytes" start="0x1" />
+        <Enum name="B_0x2" description="256 bytes" start="0x2" />
+        <Enum name="B_0x3" description="512 bytes" start="0x3" />
+        <Enum name="B_0x4" description="1024 bytes" start="0x4" />
+      </BitField>
+      <BitField name="CBURSTRW" description="Write burst enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write operations are always performed in asynchronous mode" start="0x0" />
+        <Enum name="B_0x1" description="Write operations are performed in synchronous mode." start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT0" description="Chip Select (CS) counter" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="CSCOUNT1" description="Chip Select (CS) counter" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="NEx deasserted after fmc_ker_ck clock cycle" start="0x1" />
+      </BitField>
+      <BitField name="NBLSET" description="Byte lane (NBL) setup" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="NBL setup time is 0 fmc_ker_ck clock cycle." start="0x0" />
+        <Enum name="B_0x1" description="NBL setup time is 1 fmc_ker_ck clock cycle." start="0x1" />
+        <Enum name="B_0x2" description="NBL setup time is 2 fmc_ker_ck clock cycles." start="0x2" />
+        <Enum name="B_0x3" description="NBL setup time is 3 fmc_ker_ck clock cycles." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BTR4" description="SRAM/NOR Flash chip-select timing registers for memory region 4" start="+0x1C" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration =1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATLAT" description="Data latency for synchronous memory (see note below bit descriptions)" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Data latency of 2 FMC_CLK clock cycles for first burst access" start="0x0" />
+        <Enum name="B_0xF" description="Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write)" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write)" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CFGR" description="FMC common configuration register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal)" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="FMC_CLK period= 1x fmc_ker_ck period" start="0x0" />
+        <Enum name="B_0x1" description="FMC_CLK period = 2 fmc_ker_ck periods" start="0x1" />
+        <Enum name="B_0x2" description="FMC_CLK period = 3 fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0xF" description="FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="CCLKEN" description="Continuous clock enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is defined by the programmed CLKDIV value in the FMC_BCRx register (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The FMC_CLK is generated continuously during asynchronous and synchronous access." start="0x1" />
+      </BitField>
+      <BitField name="BMAP0" description="FMC memory region mapping" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default mapping (refer to Table 132)" start="0x0" />
+        <Enum name="B_0x1" description="Devices are remapped (refer to Table 133)" start="0x1" />
+      </BitField>
+      <BitField name="BMAP1" description="FMC memory region mapping" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default mapping (refer to Table 132)" start="0x0" />
+        <Enum name="B_0x1" description="Devices are remapped (refer to Table 133)" start="0x1" />
+      </BitField>
+      <BitField name="FMCEN" description="FMC controller enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC controller disabled" start="0x0" />
+        <Enum name="B_0x1" description="FMC controller enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PCR" description="NAND Flash programmable control register" start="+0x80" size="4" reset_value="0x0007FE08" reset_mask="0xFFFFFFFF">
+      <BitField name="PWAITEN" description="Wait feature enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="disabled (default)" start="0x0" />
+        <Enum name="B_0x1" description="enabled" start="0x1" />
+      </BitField>
+      <BitField name="PBKEN" description="NAND Flash memory region enable bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Corresponding memory region is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Corresponding memory region is enabled." start="0x1" />
+      </BitField>
+      <BitField name="PWID" description="Data bus width" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+      </BitField>
+      <BitField name="ECCEN" description="ECC computation logic enable bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC logic is disabled and reset (default after reset)," start="0x0" />
+        <Enum name="B_0x1" description="ECC logic is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ECCALG" description="ECC algorithm" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hamming code is selected (default)." start="0x0" />
+        <Enum name="B_0x1" description="BCH code is selected." start="0x1" />
+      </BitField>
+      <BitField name="TCLR" description="CLE to RE delay." start="9" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0xF" description="16 * fmc_ker_ck cycles (default)" start="0xF" />
+      </BitField>
+      <BitField name="TAR" description="ALE to RE delay." start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0xF" description="16 * fmc_ker_ck cycles (default)" start="0xF" />
+      </BitField>
+      <BitField name="ECCSS" description="ECC sector size (used to access spare area)" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="256 bytes" start="0x0" />
+        <Enum name="B_0x1" description="512 bytes" start="0x1" />
+        <Enum name="B_0x2" description="1024 bytes" start="0x2" />
+        <Enum name="B_0x3" description="2048 bytes (default)" start="0x3" />
+        <Enum name="B_0x4" description="4096 bytes" start="0x4" />
+      </BitField>
+      <BitField name="BCHECC" description="BCH error correction capability" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit BCH (4-bit error correction and 8-bit error detection per 512 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="8-bit BCH (8-bit error correction and 16-bit error detection per 512 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="WEN" description="Write enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read access enabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SR" description="FMC status register" start="+0x84" size="4" reset_value="0x00000053" reset_mask="0xFFFFFFFF">
+      <BitField name="ISOST" description="FMC isolation state with respect to the AXI interface" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="FMC is not isolated; AXI transactions are treated by the FMC and its controllers." start="0x0" />
+        <Enum name="B_0x1" description="FMC has been enabled (FMCEN = 1) and waits for the end of pending AXI transactions (which leads to error responses) before going to non-isolated state." start="0x1" />
+        <Enum name="B_0x2" description="FMC has been disabled (FMCEN = 0) and waits for the end of pending AXI transactions before going to isolation state." start="0x2" />
+        <Enum name="B_0x3" description="FMC is isolated from its AXI interface. All AXI requests lead to error responses." start="0x3" />
+      </BitField>
+      <BitField name="PEF" description="Pipe Empty Flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="NWRF" description="NAND write request flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="NAND Flash write requests are pending" start="0x0" />
+        <Enum name="B_0x1" description="No NAND Flash write requests pending" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PMEM" description="FMC common memory space timing register" start="+0x88" size="4" reset_value="0x0A0A0A0A" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMSET" description="Common memory setup time" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycles" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+      <BitField name="MEMWAIT" description="Common memory wait time" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0xFF" />
+      </BitField>
+      <BitField name="MEMHOLD" description="Common memory hold time" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+      <BitField name="MEMHIZ" description="Common memory data bus Hi-Z time" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_PATT" description="FMC attribute memory space timing registers" start="+0x8C" size="4" reset_value="0x0A0A0A0A" reset_mask="0xFFFFFFFF">
+      <BitField name="ATTSET" description="Attribute memory setup time" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles." start="0xFF" />
+      </BitField>
+      <BitField name="ATTWAIT" description="Attribute memory wait time" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle (+ wait cycle introduced by deassertion of NWAIT)" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT)" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)" start="0xFF" />
+      </BitField>
+      <BitField name="ATTHOLD" description="Attribute memory hold time" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles." start="0xFF" />
+      </BitField>
+      <BitField name="ATTHIZ" description="Attribute memory data bus Hi-Z time" start="24" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="1 * fmc_ker_ck cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 * fmc_ker_ck cycle" start="0x1" />
+        <Enum name="B_0xFF" description="256 * fmc_ker_ck cycles" start="0xFF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_HPR" description="FMC Hamming parity result registers" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPR" description="Hamming parity result" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_HECCR" description="FMC Hamming code ECC result register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HECC" description="ECC result" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BWTR1" description="SRAM/NOR-Flash write timing registers for memory region 1" start="+0x104" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR2" description="SRAM/NOR-Flash write timing registers for memory region 2" start="+0x10C" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR3" description="SRAM/NOR-Flash write timing registers for memory region 3" start="+0x114" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BWTR4" description="SRAM/NOR-Flash write timing registers for memory region 4" start="+0x11C" size="4" reset_value="0x000FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ADDSET phase duration = 0 * fmc_ker_ck clock cycle" start="0x0" />
+        <Enum name="B_0xF" description="ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ADDHLD" description="Address-hold phase duration." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="ADDHLD phase duration = 1 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="ADDHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0xF" description="ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="DATAST" description="Data-phase duration." start="8" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="DATAST phase duration = 1 * fmc_ker_ck clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="DATAST phase duration = 2 * fmc_ker_ck clock cycles" start="0x2" />
+        <Enum name="B_0xFF" description="DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset)" start="0xFF" />
+      </BitField>
+      <BitField name="BUSTURN" description="Bus turnaround phase duration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added" start="0x0" />
+        <Enum name="B_0xF" description="BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset)" start="0xF" />
+      </BitField>
+      <BitField name="ACCMOD" description="Access mode." start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Access mode A" start="0x0" />
+        <Enum name="B_0x1" description="Access mode B" start="0x1" />
+        <Enum name="B_0x2" description="Access mode C" start="0x2" />
+        <Enum name="B_0x3" description="Access mode D" start="0x3" />
+      </BitField>
+      <BitField name="DATAHLD" description="Data Hold phase duration " start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATAHLD phase duration = 1 * fmc_ker_ck clock cycle (default)" start="0x0" />
+        <Enum name="B_0x1" description="DATAHLD phase duration = 2 * fmc_ker_ck clock cycle" start="0x1" />
+        <Enum name="B_0x2" description="DATAHLD phase duration = 3 * fmc_ker_ck clock cycle" start="0x2" />
+        <Enum name="B_0x3" description="DATAHLD phase duration = 4 * fmc_ker_ck clock cycle" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCR1" description="SDRAM control registers for SDRAM device 1" start="+0x140" size="4" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="9 bits" start="0x1" />
+        <Enum name="B_0x2" description="10 bits" start="0x2" />
+        <Enum name="B_0x3" description="11 bits." start="0x3" />
+      </BitField>
+      <BitField name="NR" description="Number of row address bits" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="11 bit" start="0x0" />
+        <Enum name="B_0x1" description="12 bits" start="0x1" />
+        <Enum name="B_0x2" description="13 bits" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width." start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="NB" description="Number of banks" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Two banks" start="0x0" />
+        <Enum name="B_0x1" description="Four banks" start="0x1" />
+      </BitField>
+      <BitField name="CAS" description="CAS Latency" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 cycles" start="0x3" />
+      </BitField>
+      <BitField name="WP" description="Write protection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write accesses allowed" start="0x0" />
+        <Enum name="B_0x1" description="Write accesses ignored" start="0x1" />
+      </BitField>
+      <BitField name="SDCLK" description="SDRAM clock configuration" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="SDCLK clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDCLK period = 1 * fmc_ker_ck period" start="0x1" />
+        <Enum name="B_0x2" description="SDCLK period = 2 * fmc_ker_ck periods" start="0x2" />
+        <Enum name="B_0x3" description="SDCLK period = 3 * fmc_ker_ck periods" start="0x3" />
+      </BitField>
+      <BitField name="RPIPE" description="Read pipe" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No fmc_ker_ck clock cycle delay (default value)" start="0x0" />
+        <Enum name="B_0x1" description="One fmc_ker_ck clock cycle delay" start="0x1" />
+        <Enum name="B_0x2" description="Two fmc_ker_ck clock cycle delay" start="0x2" />
+      </BitField>
+      <BitField name="SDEN" description="SDRAM device enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="SDRAM device enabled" start="0x1" />
+        <Enum name="B_0x0" description="SDRAM disabled" start="0x0" />
+      </BitField>
+      <BitField name="SDINIT" description="SDRAM device initialization" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Initialization is complete and the device is ready to be accessed" start="0x1" />
+        <Enum name="B_0x0" description="Initialization is not complete, the AXI accesses are rejected and an AXI slave error is generated." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCR2" description="SDRAM control registers for SDRAM device 2" start="+0x144" size="4" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="9 bits" start="0x1" />
+        <Enum name="B_0x2" description="10 bits" start="0x2" />
+        <Enum name="B_0x3" description="11 bits." start="0x3" />
+      </BitField>
+      <BitField name="NR" description="Number of row address bits" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="11 bit" start="0x0" />
+        <Enum name="B_0x1" description="12 bits" start="0x1" />
+        <Enum name="B_0x2" description="13 bits" start="0x2" />
+      </BitField>
+      <BitField name="MWID" description="Memory data bus width." start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8 bits" start="0x0" />
+        <Enum name="B_0x1" description="16 bits" start="0x1" />
+        <Enum name="B_0x2" description="32 bits" start="0x2" />
+      </BitField>
+      <BitField name="NB" description="Number of banks" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Two banks" start="0x0" />
+        <Enum name="B_0x1" description="Four banks" start="0x1" />
+      </BitField>
+      <BitField name="CAS" description="CAS Latency" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 cycles" start="0x3" />
+      </BitField>
+      <BitField name="WP" description="Write protection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write accesses allowed" start="0x0" />
+        <Enum name="B_0x1" description="Write accesses ignored" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="SDRAM device enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="SDRAM device enabled" start="0x1" />
+        <Enum name="B_0x0" description="SDRAM disabled" start="0x0" />
+      </BitField>
+      <BitField name="SDINIT" description="SDRAM device initialization" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Initialization is complete and the device is ready to be accessed" start="0x1" />
+        <Enum name="B_0x0" description="Initialization is not complete, the AXI accesses are rejected and an AXI slave error is generated." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDTR" description="SDRAM timing register" start="+0x148" size="4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TMRD" description="Load mode register to active " start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TXSR" description="Exit self-refresh delay" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRAS" description="Self-refresh time" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRC" description="Row cycle delay" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TWR" description="Recovery delay" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRP" description="Row precharge delay" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+      <BitField name="TRCD" description="Row to column delay" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 cycle." start="0x0" />
+        <Enum name="B_0x1" description="2 cycles" start="0x1" />
+        <Enum name="B_0xF" description="16 cycles" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDCMR" description="SDRAM command mode register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="Command mode" start="0" size="3" access="WriteOnly">
+        <Enum name="B_0x0" description="Normal mode command (NRM)" start="0x0" />
+        <Enum name="B_0x2" description="Precharge all banks command (PALL)" start="0x2" />
+        <Enum name="B_0x3" description="Refresh command (REF)" start="0x3" />
+        <Enum name="B_0x4" description="Load mode register command (LMR)" start="0x4" />
+        <Enum name="B_0x5" description="Self-refresh command (SR)" start="0x5" />
+        <Enum name="B_0x6" description="Power-down command (PD)" start="0x6" />
+      </BitField>
+      <BitField name="DS2" description="Command targeting SDRAM device 2" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Command not issued to SDRAM device 2" start="0x0" />
+        <Enum name="B_0x1" description="Command issued to SDRAM device 2" start="0x1" />
+      </BitField>
+      <BitField name="DS1" description="Command targeting SDRAM device 1" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Command not issued to SDRAM device 1" start="0x0" />
+        <Enum name="B_0x1" description="Command issued to SDRAM device 1" start="0x1" />
+      </BitField>
+      <BitField name="NRFS" description="Number of Refresh commands" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 Refresh cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 Refresh cycles" start="0x1" />
+        <Enum name="B_0xE" description="15 Refresh cycles" start="0xE" />
+        <Enum name="B_0xF" description="16 Refresh cycles" start="0xF" />
+      </BitField>
+      <BitField name="MRD" description="Mode register definition" start="9" size="14" access="Read/Write" />
+    </Register>
+    <Register name="FMC_SDRTR" description="SDRAM refresh timer register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRE" description="Clear Refresh error flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="Refresh Error flag is cleared" start="0x1" />
+      </BitField>
+      <BitField name="RFSCNT" description="Refresh Timer Count" start="1" size="13" access="Read/Write" />
+      <BitField name="REIE" description="RES Interrupt Enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="An Interrupt is generated if RE = 1" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_SDSR" description="SDRAM status register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Refresh error flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No refresh error has been detected" start="0x0" />
+        <Enum name="B_0x1" description="A refresh error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="MODES1" description="Status Mode for SDRAM device 1" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Normal mode, devices are not in Self-refresh or power-down" start="0x0" />
+        <Enum name="B_0x1" description="Self-refresh" start="0x1" />
+        <Enum name="B_0x2" description="Power-down" start="0x2" />
+      </BitField>
+      <BitField name="MODES2" description="Status mode for SDRAM device 2" start="3" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Normal mode, devices are not in Self-refresh or power-down" start="0x0" />
+        <Enum name="B_0x1" description="Self-refresh" start="0x1" />
+        <Enum name="B_0x2" description="Power-down" start="0x2" />
+      </BitField>
+      <BitField name="CMDOK" description="Previous command status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Command not complete" start="0x0" />
+        <Enum name="B_0x1" description="Command complete in the SDRAM clock domain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_IER" description="FMC NAND interrupt enable register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IREE" description="Interrupt rising edge detection enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt rising edge detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt rising edge detection request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IHLE" description="Interrupt high-level detection enable bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt high-level detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt high-level detection request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFEE" description="Interrupt falling edge detection enable bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt falling edge detection request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt falling edge detection request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_ISR" description="FMC controller interrupt status register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IREF" description="Interrupt rising edge flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt rising edge occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt rising edge occurred" start="0x1" />
+      </BitField>
+      <BitField name="IHLF" description="Interrupt high-level flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Interrupt high-level occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt high-level occurred" start="0x1" />
+      </BitField>
+      <BitField name="IFEF" description="Interrupt falling edge flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt falling edge occurred" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt falling edge occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_ICR" description="FMC NAND controller interrupt clear register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CIREF" description="Clear Interrupt rising edge flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear the IREF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="CIHLF" description="Clear Interrupt high-level flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clears the IHLF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="CIFEF" description="Clear Interrupt falling edge flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clears the IFEF flag in the FMC_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCR" description="FMC NAND command sequencer control register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSQSTART" description="Command Sequencer Enable" start="0" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_CSQCFGR1" description="FMC NAND command sequencer configuration register 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMD2EN" description="Command cycle 2 Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command cycle 2 not issued." start="0x0" />
+        <Enum name="B_0x1" description="Command cycle 2 (programmed CMD2[7:0]) sent by the command sequencer to the NAND Flash memory after the address cycles." start="0x1" />
+      </BitField>
+      <BitField name="DMADEN" description="Command sequencer DMA request data enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No DMA request transfer" start="0x0" />
+        <Enum name="B_0x1" description="A DMA request transfer" start="0x1" />
+      </BitField>
+      <BitField name="ACYNBR" description="Address Cycle number " start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No address cycle." start="0x0" />
+        <Enum name="B_0x1" description="1 address cycle" start="0x1" />
+        <Enum name="B_0x2" description="2 address cycles" start="0x2" />
+        <Enum name="B_0x3" description="3 address cycles" start="0x3" />
+        <Enum name="B_0x4" description="4 address cycles" start="0x4" />
+        <Enum name="B_0x5" description="5 address cycles" start="0x5" />
+      </BitField>
+      <BitField name="CMD1" description="Command 1 sequencer" start="8" size="8" access="Read/Write" />
+      <BitField name="CMD2" description="Command 2 sequencer" start="16" size="8" access="Read/Write" />
+      <BitField name="CMD1T" description="Command 1 Sequencer timings" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="CMD2T" description="Command 2 Sequencer timings" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCFGR2" description="FMC NAND command sequencer configuration register 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQSDTEN" description="Sequencer spare data transfer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC disabled and spare data area not accessed by the sequencer" start="0x0" />
+        <Enum name="B_0x1" description="ECC enabled and spare data area read or programmed by the sequencer after each sector transfer" start="0x1" />
+      </BitField>
+      <BitField name="RCMD2EN" description="Random Command 2 sequencer enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command 2 not issued." start="0x0" />
+        <Enum name="B_0x1" description="Command 2 (CMD2SQ[7:0]) issued by the command sequencer to NAND flash memory after the address cycle." start="0x1" />
+      </BitField>
+      <BitField name="DMASEN" description="Command sequencer DMA request decoding status enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No DMA request used for ECC status registers transfer" start="0x0" />
+        <Enum name="B_0x1" description="A DMA request used for ECC status registers transfer" start="0x1" />
+      </BitField>
+      <BitField name="RCMD1" description="Random Command 1 sequencer" start="8" size="8" access="Read/Write" />
+      <BitField name="RCMD2" description="Random Command 2 sequencer" start="16" size="8" access="Read/Write" />
+      <BitField name="RCMD1T" description="Command 1 sequencer timings" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RCMD2T" description="Command 1 sequencer timings" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMD1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="CMD1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQCFGR3" description="FMC NAND sequencer configuration register 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SNBR" description="Number of sectors to be read/written" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="1 sector" start="0x0" />
+        <Enum name="B_0x1" description="2 sectors" start="0x1" />
+        <Enum name="B_0x3F" description="16 sectors" start="0x3F" />
+      </BitField>
+      <BitField name="AC1T" description="Address cycle 1 sequencer timings" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC2T" description="Address cycle 2 sequencer timings" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC3T" description="Address cycle 3 sequencer timings" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC3 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC3 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC4T" description="Address cycle 4sequencer timings" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC4 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC4 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="AC5T" description="Address cycle 5 sequencer timings" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDC5 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="ADDC5 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="SDT" description="Spare data transfer sequencer timings" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Spare data transfer issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Spare data transfer issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RAC1T" description="Random Address cycle 1 sequencer timings" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Random ADDC1 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Random ADDC1 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+      <BitField name="RAC2T" description="Random Address cycle 2 sequencer timings" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Random ADDC2 issued with the timings programmed in FMC_PMEM" start="0x0" />
+        <Enum name="B_0x1" description="Random ADDC2 issued with the timings programmed in FMC_PATT" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQAR1" description="FMC NAND command sequencer address register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDC1" description="Address Cycle 1" start="0" size="8" access="Read/Write" />
+      <BitField name="ADDC2" description="Address Cycle 2" start="8" size="8" access="Read/Write" />
+      <BitField name="ADDC3" description="Address Cycle 3" start="16" size="8" access="Read/Write" />
+      <BitField name="ADDC4" description="Address Cycle 4" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQAR2" description="FMC NAND command sequencer address register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDC5" description="Address Cycle 5" start="0" size="8" access="Read/Write" />
+      <BitField name="SAO" description="Spare Area Address Offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQIER" description="FMC NAND command sequencer interrupt enable register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIE" description="Transfer Complete Interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SCIE" description="Sector Complete interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sector Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Sector Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SEIE" description="Sector Error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sector Error Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Sector Error Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="SUEIE" description="Sector Uncorrectable Error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Command Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="CMDTCIE" description="Command Transfer Complete interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command Transfer Complete Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Command Transfer Complete Interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_CSQISR" description="FMC NAND command sequencer interrupt status register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="Transfer Complete flag" start="0" size="1" access="Read/Write" />
+      <BitField name="SCF" description="Sector Complete flag" start="1" size="1" access="Read/Write" />
+      <BitField name="SEF" description="Sector Error flag" start="2" size="1" access="Read/Write" />
+      <BitField name="SUEF" description="Sector Uncorrectable Error flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CMDTCF" description="Command Transfer Complete flag" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="FMC_CSQICR" description="FMC NAND command sequencer interrupt clear register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCF" description="Clear Transfer Complete flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CSCF" description="Clear Sector Complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSEF" description="Clear Sector Error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CSUEF" description="Clear Sector uncorrectable Error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CCMDTCF" description="Clear Command Transfer Complete flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_CSQEMSR" description="FMC command sequencer error mapping status register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM" description="Sector Error mapping " start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHIER" description="FMC BCH interrupt enable register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUEIE" description="Decoder Uncorrectable Errors Interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Uncorrectable Errors Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Uncorrectable Errors Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DERIE" description="Decoder Error Ready Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Error Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Error Ready Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="Decoder Error Found Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Error Found Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Error Found Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="DSRIE" description="Decoder Syndrome Ready Interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Syndrome Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Syndrome Ready Interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="EPBRIE" description="Decoder Parity Bits Ready Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decoder Parity Bits Ready Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Decoder Parity Bits Ready Interrupt enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMC_BCHISR" description="FMC BCH interrupt and status register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUEF" description="Decoder Uncorrectable Errors flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="DERF" description="Decoder Error Ready flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="Decoder Error Found flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="DSRF" description="Decoder Syndrome Ready flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="EPBRF" description="Encoder Parity Bits Ready flag" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHICR" description="FMC BCH interrupt clear register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CDUEF" description="Clear Decoder Uncorrectable Error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CDERF" description="Clear Decoder Error ready flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CDEFF" description="Clear Decoder Error Found flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CDSRF" description="Clear Decoder Syndrome Ready flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CEPBRF" description="Clear Encoder Parity Bits Ready flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR1" description="FMC BCH parity bits register 1" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR2" description="FMC BCH parity bits register 2" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR3" description="FMC BCH parity bits register 3" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHPBR4" description="FMC BCH parity bits register 4" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCHPB" description="BCH parity bits" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR0" description="FMC BCH decoder status register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUE" description="Decoder uncorrectable error" start="0" size="1" access="ReadOnly" />
+      <BitField name="DEF" description="Decoder error found" start="1" size="1" access="ReadOnly" />
+      <BitField name="DEN" description="Decoder error number" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR1" description="FMC BCH decoder status register for memory region 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP1" description="Error bit position for error number 1" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP2" description="Error bit position for error number 2" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR2" description="FMC BCH decoder status register for memory region 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP3" description="Error bit position for error number 3" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP4" description="Error bit position for error number 4" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR3" description="FMC BCH decoder status register for memory region 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP5" description="Error bit position for error number 5" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP6" description="Error bit position for error number 6" start="16" size="13" access="ReadOnly" />
+    </Register>
+    <Register name="FMC_BCHDSR4" description="FMC BCH decoder status register for memory region 4" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EBP7" description="Error bit position for error number 7" start="0" size="13" access="ReadOnly" />
+      <BitField name="EBP8" description="Error bit position for error number 8" start="16" size="13" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GFXMMU" description="Chrom-GRC" start="0x48030000">
+    <Register name="GFXMMU_CR" description="GFXMMU configuration register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="B0OIE" description="Buffer 0 overflow interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B1OIE" description="Buffer 1 overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B2OIE" description="Buffer 2 overflow interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B3OIE" description="Buffer 3 overflow interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AMEIE" description="AXI master error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BS" description="Block size" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-byte blocks" start="0x0" />
+        <Enum name="B_0x1" description="12-byte blocks" start="0x1" />
+      </BitField>
+      <BitField name="ATE" description="Address translation enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address translation is disable" start="0x0" />
+        <Enum name="B_0x1" description="Address translation is enable" start="0x1" />
+      </BitField>
+      <BitField name="B0PE" description="Buffer 0 packing enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B0PM" description="Buffer 0 packing mode" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B1PE" description="Buffer 1 packing enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B1PM" description="Buffer 1 packing mode" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B2PE" description="Buffer 2 packing enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B2PM" description="Buffer 2 packing mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B3PE" description="Buffer 3 packing enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B3PM" description="Buffer 3 packing mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXMMU_SR" description="GFXMMU status register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="B0OF" description="Buffer 0 overflow flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="B1OF" description="Buffer 1 overflow flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="B2OF" description="Buffer 2 overflow flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="B3OF" description="Buffer 3 overflow flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="AMEF" description="AXI master error flag" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GFXMMU_FCR" description="GFXMMU flag clear register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CB0OF" description="Clear buffer 0 overflow flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CB1OF" description="Clear buffer 1 overflow flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CB2OF" description="Clear buffer 2 overflow flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CB3OF" description="Clear buffer 3 overflow flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CAMEF" description="Clear AXI master error flag" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_DVR" description="GFXMMU default value register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DV" description="Default value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_DAR" description="GFXMMU default alpha register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Default alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B0CR" description="GFXMMU buffer 0 configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B1CR" description="GFXMMU buffer 1 configuration register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B2CR" description="GFXMMU buffer 2 configuration register" start="+0x0028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B3CR" description="GFXMMU buffer 3 configuration register" start="+0x002C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT0L" description="GFXMMU LUT entry 0 low" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT0H" description="GFXMMU LUT entry 0 high" start="+0x1004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1L" description="GFXMMU LUT entry 1 low" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1H" description="GFXMMU LUT entry 1 high" start="+0x100C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT2L" description="GFXMMU LUT entry 2 low" start="+0x1010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT2H" description="GFXMMU LUT entry 2 high" start="+0x1014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT3L" description="GFXMMU LUT entry 3 low" start="+0x1018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT3H" description="GFXMMU LUT entry 3 high" start="+0x101C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT4L" description="GFXMMU LUT entry 4 low" start="+0x1020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT4H" description="GFXMMU LUT entry 4 high" start="+0x1024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT5L" description="GFXMMU LUT entry 5 low" start="+0x1028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT5H" description="GFXMMU LUT entry 5 high" start="+0x102C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT6L" description="GFXMMU LUT entry 6 low" start="+0x1030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT6H" description="GFXMMU LUT entry 6 high" start="+0x1034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT7L" description="GFXMMU LUT entry 7 low" start="+0x1038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT7H" description="GFXMMU LUT entry 7 high" start="+0x103C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT8L" description="GFXMMU LUT entry 8 low" start="+0x1040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT8H" description="GFXMMU LUT entry 8 high" start="+0x1044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT9L" description="GFXMMU LUT entry 9 low" start="+0x1048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT9H" description="GFXMMU LUT entry 9 high" start="+0x104C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT10L" description="GFXMMU LUT entry 10 low" start="+0x1050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT10H" description="GFXMMU LUT entry 10 high" start="+0x1054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT11L" description="GFXMMU LUT entry 11 low" start="+0x1058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT11H" description="GFXMMU LUT entry 11 high" start="+0x105C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT12L" description="GFXMMU LUT entry 12 low" start="+0x1060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT12H" description="GFXMMU LUT entry 12 high" start="+0x1064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT13L" description="GFXMMU LUT entry 13 low" start="+0x1068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT13H" description="GFXMMU LUT entry 13 high" start="+0x106C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT14L" description="GFXMMU LUT entry 14 low" start="+0x1070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT14H" description="GFXMMU LUT entry 14 high" start="+0x1074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT15L" description="GFXMMU LUT entry 15 low" start="+0x1078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT15H" description="GFXMMU LUT entry 15 high" start="+0x107C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT16L" description="GFXMMU LUT entry 16 low" start="+0x1080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT16H" description="GFXMMU LUT entry 16 high" start="+0x1084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT17L" description="GFXMMU LUT entry 17 low" start="+0x1088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT17H" description="GFXMMU LUT entry 17 high" start="+0x108C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT18L" description="GFXMMU LUT entry 18 low" start="+0x1090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT18H" description="GFXMMU LUT entry 18 high" start="+0x1094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT19L" description="GFXMMU LUT entry 19 low" start="+0x1098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT19H" description="GFXMMU LUT entry 19 high" start="+0x109C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT20L" description="GFXMMU LUT entry 20 low" start="+0x10A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT20H" description="GFXMMU LUT entry 20 high" start="+0x10A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT21L" description="GFXMMU LUT entry 21 low" start="+0x10A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT21H" description="GFXMMU LUT entry 21 high" start="+0x10AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT22L" description="GFXMMU LUT entry 22 low" start="+0x10B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT22H" description="GFXMMU LUT entry 22 high" start="+0x10B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT23L" description="GFXMMU LUT entry 23 low" start="+0x10B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT23H" description="GFXMMU LUT entry 23 high" start="+0x10BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT24L" description="GFXMMU LUT entry 24 low" start="+0x10C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT24H" description="GFXMMU LUT entry 24 high" start="+0x10C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT25L" description="GFXMMU LUT entry 25 low" start="+0x10C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT25H" description="GFXMMU LUT entry 25 high" start="+0x10CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT26L" description="GFXMMU LUT entry 26 low" start="+0x10D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT26H" description="GFXMMU LUT entry 26 high" start="+0x10D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT27L" description="GFXMMU LUT entry 27 low" start="+0x10D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT27H" description="GFXMMU LUT entry 27 high" start="+0x10DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT28L" description="GFXMMU LUT entry 28 low" start="+0x10E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT28H" description="GFXMMU LUT entry 28 high" start="+0x10E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT29L" description="GFXMMU LUT entry 29 low" start="+0x10E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT29H" description="GFXMMU LUT entry 29 high" start="+0x10EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT30L" description="GFXMMU LUT entry 30 low" start="+0x10F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT30H" description="GFXMMU LUT entry 30 high" start="+0x10F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT31L" description="GFXMMU LUT entry 31 low" start="+0x10F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT31H" description="GFXMMU LUT entry 31 high" start="+0x10FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT32L" description="GFXMMU LUT entry 32 low" start="+0x1100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT32H" description="GFXMMU LUT entry 32 high" start="+0x1104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT33L" description="GFXMMU LUT entry 33 low" start="+0x1108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT33H" description="GFXMMU LUT entry 33 high" start="+0x110C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT34L" description="GFXMMU LUT entry 34 low" start="+0x1110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT34H" description="GFXMMU LUT entry 34 high" start="+0x1114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT35L" description="GFXMMU LUT entry 35 low" start="+0x1118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT35H" description="GFXMMU LUT entry 35 high" start="+0x111C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT36L" description="GFXMMU LUT entry 36 low" start="+0x1120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT36H" description="GFXMMU LUT entry 36 high" start="+0x1124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT37L" description="GFXMMU LUT entry 37 low" start="+0x1128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT37H" description="GFXMMU LUT entry 37 high" start="+0x112C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT38L" description="GFXMMU LUT entry 38 low" start="+0x1130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT38H" description="GFXMMU LUT entry 38 high" start="+0x1134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT39L" description="GFXMMU LUT entry 39 low" start="+0x1138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT39H" description="GFXMMU LUT entry 39 high" start="+0x113C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT40L" description="GFXMMU LUT entry 40 low" start="+0x1140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT40H" description="GFXMMU LUT entry 40 high" start="+0x1144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT41L" description="GFXMMU LUT entry 41 low" start="+0x1148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT41H" description="GFXMMU LUT entry 41 high" start="+0x114C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT42L" description="GFXMMU LUT entry 42 low" start="+0x1150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT42H" description="GFXMMU LUT entry 42 high" start="+0x1154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT43L" description="GFXMMU LUT entry 43 low" start="+0x1158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT43H" description="GFXMMU LUT entry 43 high" start="+0x115C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT44L" description="GFXMMU LUT entry 44 low" start="+0x1160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT44H" description="GFXMMU LUT entry 44 high" start="+0x1164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT45L" description="GFXMMU LUT entry 45 low" start="+0x1168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT45H" description="GFXMMU LUT entry 45 high" start="+0x116C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT46L" description="GFXMMU LUT entry 46 low" start="+0x1170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT46H" description="GFXMMU LUT entry 46 high" start="+0x1174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT47L" description="GFXMMU LUT entry 47 low" start="+0x1178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT47H" description="GFXMMU LUT entry 47 high" start="+0x117C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT48L" description="GFXMMU LUT entry 48 low" start="+0x1180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT48H" description="GFXMMU LUT entry 48 high" start="+0x1184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT49L" description="GFXMMU LUT entry 49 low" start="+0x1188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT49H" description="GFXMMU LUT entry 49 high" start="+0x118C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT50L" description="GFXMMU LUT entry 50 low" start="+0x1190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT50H" description="GFXMMU LUT entry 50 high" start="+0x1194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT51L" description="GFXMMU LUT entry 51 low" start="+0x1198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT51H" description="GFXMMU LUT entry 51 high" start="+0x119C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT52L" description="GFXMMU LUT entry 52 low" start="+0x11A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT52H" description="GFXMMU LUT entry 52 high" start="+0x11A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT53L" description="GFXMMU LUT entry 53 low" start="+0x11A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT53H" description="GFXMMU LUT entry 53 high" start="+0x11AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT54L" description="GFXMMU LUT entry 54 low" start="+0x11B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT54H" description="GFXMMU LUT entry 54 high" start="+0x11B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT55L" description="GFXMMU LUT entry 55 low" start="+0x11B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT55H" description="GFXMMU LUT entry 55 high" start="+0x11BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT56L" description="GFXMMU LUT entry 56 low" start="+0x11C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT56H" description="GFXMMU LUT entry 56 high" start="+0x11C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT57L" description="GFXMMU LUT entry 57 low" start="+0x11C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT57H" description="GFXMMU LUT entry 57 high" start="+0x11CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT58L" description="GFXMMU LUT entry 58 low" start="+0x11D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT58H" description="GFXMMU LUT entry 58 high" start="+0x11D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT59L" description="GFXMMU LUT entry 59 low" start="+0x11D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT59H" description="GFXMMU LUT entry 59 high" start="+0x11DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT60L" description="GFXMMU LUT entry 60 low" start="+0x11E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT60H" description="GFXMMU LUT entry 60 high" start="+0x11E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT61L" description="GFXMMU LUT entry 61 low" start="+0x11E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT61H" description="GFXMMU LUT entry 61 high" start="+0x11EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT62L" description="GFXMMU LUT entry 62 low" start="+0x11F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT62H" description="GFXMMU LUT entry 62 high" start="+0x11F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT63L" description="GFXMMU LUT entry 63 low" start="+0x11F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT63H" description="GFXMMU LUT entry 63 high" start="+0x11FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT64L" description="GFXMMU LUT entry 64 low" start="+0x1200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT64H" description="GFXMMU LUT entry 64 high" start="+0x1204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT65L" description="GFXMMU LUT entry 65 low" start="+0x1208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT65H" description="GFXMMU LUT entry 65 high" start="+0x120C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT66L" description="GFXMMU LUT entry 66 low" start="+0x1210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT66H" description="GFXMMU LUT entry 66 high" start="+0x1214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT67L" description="GFXMMU LUT entry 67 low" start="+0x1218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT67H" description="GFXMMU LUT entry 67 high" start="+0x121C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT68L" description="GFXMMU LUT entry 68 low" start="+0x1220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT68H" description="GFXMMU LUT entry 68 high" start="+0x1224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT69L" description="GFXMMU LUT entry 69 low" start="+0x1228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT69H" description="GFXMMU LUT entry 69 high" start="+0x122C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT70L" description="GFXMMU LUT entry 70 low" start="+0x1230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT70H" description="GFXMMU LUT entry 70 high" start="+0x1234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT71L" description="GFXMMU LUT entry 71 low" start="+0x1238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT71H" description="GFXMMU LUT entry 71 high" start="+0x123C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT72L" description="GFXMMU LUT entry 72 low" start="+0x1240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT72H" description="GFXMMU LUT entry 72 high" start="+0x1244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT73L" description="GFXMMU LUT entry 73 low" start="+0x1248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT73H" description="GFXMMU LUT entry 73 high" start="+0x124C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT74L" description="GFXMMU LUT entry 74 low" start="+0x1250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT74H" description="GFXMMU LUT entry 74 high" start="+0x1254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT75L" description="GFXMMU LUT entry 75 low" start="+0x1258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT75H" description="GFXMMU LUT entry 75 high" start="+0x125C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT76L" description="GFXMMU LUT entry 76 low" start="+0x1260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT76H" description="GFXMMU LUT entry 76 high" start="+0x1264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT77L" description="GFXMMU LUT entry 77 low" start="+0x1268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT77H" description="GFXMMU LUT entry 77 high" start="+0x126C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT78L" description="GFXMMU LUT entry 78 low" start="+0x1270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT78H" description="GFXMMU LUT entry 78 high" start="+0x1274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT79L" description="GFXMMU LUT entry 79 low" start="+0x1278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT79H" description="GFXMMU LUT entry 79 high" start="+0x127C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT80L" description="GFXMMU LUT entry 80 low" start="+0x1280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT80H" description="GFXMMU LUT entry 80 high" start="+0x1284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT81L" description="GFXMMU LUT entry 81 low" start="+0x1288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT81H" description="GFXMMU LUT entry 81 high" start="+0x128C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT82L" description="GFXMMU LUT entry 82 low" start="+0x1290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT82H" description="GFXMMU LUT entry 82 high" start="+0x1294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT83L" description="GFXMMU LUT entry 83 low" start="+0x1298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT83H" description="GFXMMU LUT entry 83 high" start="+0x129C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT84L" description="GFXMMU LUT entry 84 low" start="+0x12A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT84H" description="GFXMMU LUT entry 84 high" start="+0x12A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT85L" description="GFXMMU LUT entry 85 low" start="+0x12A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT85H" description="GFXMMU LUT entry 85 high" start="+0x12AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT86L" description="GFXMMU LUT entry 86 low" start="+0x12B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT86H" description="GFXMMU LUT entry 86 high" start="+0x12B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT87L" description="GFXMMU LUT entry 87 low" start="+0x12B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT87H" description="GFXMMU LUT entry 87 high" start="+0x12BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT88L" description="GFXMMU LUT entry 88 low" start="+0x12C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT88H" description="GFXMMU LUT entry 88 high" start="+0x12C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT89L" description="GFXMMU LUT entry 89 low" start="+0x12C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT89H" description="GFXMMU LUT entry 89 high" start="+0x12CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT90L" description="GFXMMU LUT entry 90 low" start="+0x12D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT90H" description="GFXMMU LUT entry 90 high" start="+0x12D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT91L" description="GFXMMU LUT entry 91 low" start="+0x12D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT91H" description="GFXMMU LUT entry 91 high" start="+0x12DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT92L" description="GFXMMU LUT entry 92 low" start="+0x12E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT92H" description="GFXMMU LUT entry 92 high" start="+0x12E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT93L" description="GFXMMU LUT entry 93 low" start="+0x12E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT93H" description="GFXMMU LUT entry 93 high" start="+0x12EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT94L" description="GFXMMU LUT entry 94 low" start="+0x12F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT94H" description="GFXMMU LUT entry 94 high" start="+0x12F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT95L" description="GFXMMU LUT entry 95 low" start="+0x12F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT95H" description="GFXMMU LUT entry 95 high" start="+0x12FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT96L" description="GFXMMU LUT entry 96 low" start="+0x1300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT96H" description="GFXMMU LUT entry 96 high" start="+0x1304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT97L" description="GFXMMU LUT entry 97 low" start="+0x1308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT97H" description="GFXMMU LUT entry 97 high" start="+0x130C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT98L" description="GFXMMU LUT entry 98 low" start="+0x1310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT98H" description="GFXMMU LUT entry 98 high" start="+0x1314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT99L" description="GFXMMU LUT entry 99 low" start="+0x1318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT99H" description="GFXMMU LUT entry 99 high" start="+0x131C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT100L" description="GFXMMU LUT entry 100 low" start="+0x1320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT100H" description="GFXMMU LUT entry 100 high" start="+0x1324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT101L" description="GFXMMU LUT entry 101 low" start="+0x1328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT101H" description="GFXMMU LUT entry 101 high" start="+0x132C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT102L" description="GFXMMU LUT entry 102 low" start="+0x1330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT102H" description="GFXMMU LUT entry 102 high" start="+0x1334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT103L" description="GFXMMU LUT entry 103 low" start="+0x1338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT103H" description="GFXMMU LUT entry 103 high" start="+0x133C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT104L" description="GFXMMU LUT entry 104 low" start="+0x1340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT104H" description="GFXMMU LUT entry 104 high" start="+0x1344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT105L" description="GFXMMU LUT entry 105 low" start="+0x1348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT105H" description="GFXMMU LUT entry 105 high" start="+0x134C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT106L" description="GFXMMU LUT entry 106 low" start="+0x1350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT106H" description="GFXMMU LUT entry 106 high" start="+0x1354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT107L" description="GFXMMU LUT entry 107 low" start="+0x1358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT107H" description="GFXMMU LUT entry 107 high" start="+0x135C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT108L" description="GFXMMU LUT entry 108 low" start="+0x1360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT108H" description="GFXMMU LUT entry 108 high" start="+0x1364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT109L" description="GFXMMU LUT entry 109 low" start="+0x1368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT109H" description="GFXMMU LUT entry 109 high" start="+0x136C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT110L" description="GFXMMU LUT entry 110 low" start="+0x1370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT110H" description="GFXMMU LUT entry 110 high" start="+0x1374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT111L" description="GFXMMU LUT entry 111 low" start="+0x1378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT111H" description="GFXMMU LUT entry 111 high" start="+0x137C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT112L" description="GFXMMU LUT entry 112 low" start="+0x1380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT112H" description="GFXMMU LUT entry 112 high" start="+0x1384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT113L" description="GFXMMU LUT entry 113 low" start="+0x1388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT113H" description="GFXMMU LUT entry 113 high" start="+0x138C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT114L" description="GFXMMU LUT entry 114 low" start="+0x1390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT114H" description="GFXMMU LUT entry 114 high" start="+0x1394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT115L" description="GFXMMU LUT entry 115 low" start="+0x1398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT115H" description="GFXMMU LUT entry 115 high" start="+0x139C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT116L" description="GFXMMU LUT entry 116 low" start="+0x13A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT116H" description="GFXMMU LUT entry 116 high" start="+0x13A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT117L" description="GFXMMU LUT entry 117 low" start="+0x13A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT117H" description="GFXMMU LUT entry 117 high" start="+0x13AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT118L" description="GFXMMU LUT entry 118 low" start="+0x13B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT118H" description="GFXMMU LUT entry 118 high" start="+0x13B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT119L" description="GFXMMU LUT entry 119 low" start="+0x13B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT119H" description="GFXMMU LUT entry 119 high" start="+0x13BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT120L" description="GFXMMU LUT entry 120 low" start="+0x13C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT120H" description="GFXMMU LUT entry 120 high" start="+0x13C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT121L" description="GFXMMU LUT entry 121 low" start="+0x13C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT121H" description="GFXMMU LUT entry 121 high" start="+0x13CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT122L" description="GFXMMU LUT entry 122 low" start="+0x13D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT122H" description="GFXMMU LUT entry 122 high" start="+0x13D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT123L" description="GFXMMU LUT entry 123 low" start="+0x13D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT123H" description="GFXMMU LUT entry 123 high" start="+0x13DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT124L" description="GFXMMU LUT entry 124 low" start="+0x13E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT124H" description="GFXMMU LUT entry 124 high" start="+0x13E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT125L" description="GFXMMU LUT entry 125 low" start="+0x13E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT125H" description="GFXMMU LUT entry 125 high" start="+0x13EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT126L" description="GFXMMU LUT entry 126 low" start="+0x13F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT126H" description="GFXMMU LUT entry 126 high" start="+0x13F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT127L" description="GFXMMU LUT entry 127 low" start="+0x13F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT127H" description="GFXMMU LUT entry 127 high" start="+0x13FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT128L" description="GFXMMU LUT entry 128 low" start="+0x1400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT128H" description="GFXMMU LUT entry 128 high" start="+0x1404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT129L" description="GFXMMU LUT entry 129 low" start="+0x1408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT129H" description="GFXMMU LUT entry 129 high" start="+0x140C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT130L" description="GFXMMU LUT entry 130 low" start="+0x1410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT130H" description="GFXMMU LUT entry 130 high" start="+0x1414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT131L" description="GFXMMU LUT entry 131 low" start="+0x1418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT131H" description="GFXMMU LUT entry 131 high" start="+0x141C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT132L" description="GFXMMU LUT entry 132 low" start="+0x1420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT132H" description="GFXMMU LUT entry 132 high" start="+0x1424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT133L" description="GFXMMU LUT entry 133 low" start="+0x1428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT133H" description="GFXMMU LUT entry 133 high" start="+0x142C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT134L" description="GFXMMU LUT entry 134 low" start="+0x1430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT134H" description="GFXMMU LUT entry 134 high" start="+0x1434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT135L" description="GFXMMU LUT entry 135 low" start="+0x1438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT135H" description="GFXMMU LUT entry 135 high" start="+0x143C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT136L" description="GFXMMU LUT entry 136 low" start="+0x1440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT136H" description="GFXMMU LUT entry 136 high" start="+0x1444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT137L" description="GFXMMU LUT entry 137 low" start="+0x1448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT137H" description="GFXMMU LUT entry 137 high" start="+0x144C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT138L" description="GFXMMU LUT entry 138 low" start="+0x1450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT138H" description="GFXMMU LUT entry 138 high" start="+0x1454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT139L" description="GFXMMU LUT entry 139 low" start="+0x1458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT139H" description="GFXMMU LUT entry 139 high" start="+0x145C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT140L" description="GFXMMU LUT entry 140 low" start="+0x1460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT140H" description="GFXMMU LUT entry 140 high" start="+0x1464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT141L" description="GFXMMU LUT entry 141 low" start="+0x1468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT141H" description="GFXMMU LUT entry 141 high" start="+0x146C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT142L" description="GFXMMU LUT entry 142 low" start="+0x1470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT142H" description="GFXMMU LUT entry 142 high" start="+0x1474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT143L" description="GFXMMU LUT entry 143 low" start="+0x1478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT143H" description="GFXMMU LUT entry 143 high" start="+0x147C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT144L" description="GFXMMU LUT entry 144 low" start="+0x1480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT144H" description="GFXMMU LUT entry 144 high" start="+0x1484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT145L" description="GFXMMU LUT entry 145 low" start="+0x1488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT145H" description="GFXMMU LUT entry 145 high" start="+0x148C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT146L" description="GFXMMU LUT entry 146 low" start="+0x1490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT146H" description="GFXMMU LUT entry 146 high" start="+0x1494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT147L" description="GFXMMU LUT entry 147 low" start="+0x1498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT147H" description="GFXMMU LUT entry 147 high" start="+0x149C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT148L" description="GFXMMU LUT entry 148 low" start="+0x14A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT148H" description="GFXMMU LUT entry 148 high" start="+0x14A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT149L" description="GFXMMU LUT entry 149 low" start="+0x14A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT149H" description="GFXMMU LUT entry 149 high" start="+0x14AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT150L" description="GFXMMU LUT entry 150 low" start="+0x14B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT150H" description="GFXMMU LUT entry 150 high" start="+0x14B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT151L" description="GFXMMU LUT entry 151 low" start="+0x14B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT151H" description="GFXMMU LUT entry 151 high" start="+0x14BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT152L" description="GFXMMU LUT entry 152 low" start="+0x14C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT152H" description="GFXMMU LUT entry 152 high" start="+0x14C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT153L" description="GFXMMU LUT entry 153 low" start="+0x14C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT153H" description="GFXMMU LUT entry 153 high" start="+0x14CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT154L" description="GFXMMU LUT entry 154 low" start="+0x14D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT154H" description="GFXMMU LUT entry 154 high" start="+0x14D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT155L" description="GFXMMU LUT entry 155 low" start="+0x14D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT155H" description="GFXMMU LUT entry 155 high" start="+0x14DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT156L" description="GFXMMU LUT entry 156 low" start="+0x14E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT156H" description="GFXMMU LUT entry 156 high" start="+0x14E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT157L" description="GFXMMU LUT entry 157 low" start="+0x14E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT157H" description="GFXMMU LUT entry 157 high" start="+0x14EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT158L" description="GFXMMU LUT entry 158 low" start="+0x14F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT158H" description="GFXMMU LUT entry 158 high" start="+0x14F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT159L" description="GFXMMU LUT entry 159 low" start="+0x14F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT159H" description="GFXMMU LUT entry 159 high" start="+0x14FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT160L" description="GFXMMU LUT entry 160 low" start="+0x1500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT160H" description="GFXMMU LUT entry 160 high" start="+0x1504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT161L" description="GFXMMU LUT entry 161 low" start="+0x1508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT161H" description="GFXMMU LUT entry 161 high" start="+0x150C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT162L" description="GFXMMU LUT entry 162 low" start="+0x1510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT162H" description="GFXMMU LUT entry 162 high" start="+0x1514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT163L" description="GFXMMU LUT entry 163 low" start="+0x1518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT163H" description="GFXMMU LUT entry 163 high" start="+0x151C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT164L" description="GFXMMU LUT entry 164 low" start="+0x1520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT164H" description="GFXMMU LUT entry 164 high" start="+0x1524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT165L" description="GFXMMU LUT entry 165 low" start="+0x1528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT165H" description="GFXMMU LUT entry 165 high" start="+0x152C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT166L" description="GFXMMU LUT entry 166 low" start="+0x1530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT166H" description="GFXMMU LUT entry 166 high" start="+0x1534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT167L" description="GFXMMU LUT entry 167 low" start="+0x1538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT167H" description="GFXMMU LUT entry 167 high" start="+0x153C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT168L" description="GFXMMU LUT entry 168 low" start="+0x1540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT168H" description="GFXMMU LUT entry 168 high" start="+0x1544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT169L" description="GFXMMU LUT entry 169 low" start="+0x1548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT169H" description="GFXMMU LUT entry 169 high" start="+0x154C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT170L" description="GFXMMU LUT entry 170 low" start="+0x1550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT170H" description="GFXMMU LUT entry 170 high" start="+0x1554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT171L" description="GFXMMU LUT entry 171 low" start="+0x1558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT171H" description="GFXMMU LUT entry 171 high" start="+0x155C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT172L" description="GFXMMU LUT entry 172 low" start="+0x1560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT172H" description="GFXMMU LUT entry 172 high" start="+0x1564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT173L" description="GFXMMU LUT entry 173 low" start="+0x1568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT173H" description="GFXMMU LUT entry 173 high" start="+0x156C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT174L" description="GFXMMU LUT entry 174 low" start="+0x1570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT174H" description="GFXMMU LUT entry 174 high" start="+0x1574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT175L" description="GFXMMU LUT entry 175 low" start="+0x1578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT175H" description="GFXMMU LUT entry 175 high" start="+0x157C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT176L" description="GFXMMU LUT entry 176 low" start="+0x1580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT176H" description="GFXMMU LUT entry 176 high" start="+0x1584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT177L" description="GFXMMU LUT entry 177 low" start="+0x1588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT177H" description="GFXMMU LUT entry 177 high" start="+0x158C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT178L" description="GFXMMU LUT entry 178 low" start="+0x1590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT178H" description="GFXMMU LUT entry 178 high" start="+0x1594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT179L" description="GFXMMU LUT entry 179 low" start="+0x1598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT179H" description="GFXMMU LUT entry 179 high" start="+0x159C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT180L" description="GFXMMU LUT entry 180 low" start="+0x15A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT180H" description="GFXMMU LUT entry 180 high" start="+0x15A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT181L" description="GFXMMU LUT entry 181 low" start="+0x15A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT181H" description="GFXMMU LUT entry 181 high" start="+0x15AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT182L" description="GFXMMU LUT entry 182 low" start="+0x15B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT182H" description="GFXMMU LUT entry 182 high" start="+0x15B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT183L" description="GFXMMU LUT entry 183 low" start="+0x15B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT183H" description="GFXMMU LUT entry 183 high" start="+0x15BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT184L" description="GFXMMU LUT entry 184 low" start="+0x15C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT184H" description="GFXMMU LUT entry 184 high" start="+0x15C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT185L" description="GFXMMU LUT entry 185 low" start="+0x15C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT185H" description="GFXMMU LUT entry 185 high" start="+0x15CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT186L" description="GFXMMU LUT entry 186 low" start="+0x15D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT186H" description="GFXMMU LUT entry 186 high" start="+0x15D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT187L" description="GFXMMU LUT entry 187 low" start="+0x15D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT187H" description="GFXMMU LUT entry 187 high" start="+0x15DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT188L" description="GFXMMU LUT entry 188 low" start="+0x15E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT188H" description="GFXMMU LUT entry 188 high" start="+0x15E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT189L" description="GFXMMU LUT entry 189 low" start="+0x15E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT189H" description="GFXMMU LUT entry 189 high" start="+0x15EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT190L" description="GFXMMU LUT entry 190 low" start="+0x15F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT190H" description="GFXMMU LUT entry 190 high" start="+0x15F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT191L" description="GFXMMU LUT entry 191 low" start="+0x15F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT191H" description="GFXMMU LUT entry 191 high" start="+0x15FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT192L" description="GFXMMU LUT entry 192 low" start="+0x1600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT192H" description="GFXMMU LUT entry 192 high" start="+0x1604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT193L" description="GFXMMU LUT entry 193 low" start="+0x1608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT193H" description="GFXMMU LUT entry 193 high" start="+0x160C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT194L" description="GFXMMU LUT entry 194 low" start="+0x1610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT194H" description="GFXMMU LUT entry 194 high" start="+0x1614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT195L" description="GFXMMU LUT entry 195 low" start="+0x1618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT195H" description="GFXMMU LUT entry 195 high" start="+0x161C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT196L" description="GFXMMU LUT entry 196 low" start="+0x1620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT196H" description="GFXMMU LUT entry 196 high" start="+0x1624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT197L" description="GFXMMU LUT entry 197 low" start="+0x1628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT197H" description="GFXMMU LUT entry 197 high" start="+0x162C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT198L" description="GFXMMU LUT entry 198 low" start="+0x1630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT198H" description="GFXMMU LUT entry 198 high" start="+0x1634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT199L" description="GFXMMU LUT entry 199 low" start="+0x1638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT199H" description="GFXMMU LUT entry 199 high" start="+0x163C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT200L" description="GFXMMU LUT entry 200 low" start="+0x1640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT200H" description="GFXMMU LUT entry 200 high" start="+0x1644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT201L" description="GFXMMU LUT entry 201 low" start="+0x1648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT201H" description="GFXMMU LUT entry 201 high" start="+0x164C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT202L" description="GFXMMU LUT entry 202 low" start="+0x1650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT202H" description="GFXMMU LUT entry 202 high" start="+0x1654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT203L" description="GFXMMU LUT entry 203 low" start="+0x1658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT203H" description="GFXMMU LUT entry 203 high" start="+0x165C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT204L" description="GFXMMU LUT entry 204 low" start="+0x1660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT204H" description="GFXMMU LUT entry 204 high" start="+0x1664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT205L" description="GFXMMU LUT entry 205 low" start="+0x1668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT205H" description="GFXMMU LUT entry 205 high" start="+0x166C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT206L" description="GFXMMU LUT entry 206 low" start="+0x1670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT206H" description="GFXMMU LUT entry 206 high" start="+0x1674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT207L" description="GFXMMU LUT entry 207 low" start="+0x1678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT207H" description="GFXMMU LUT entry 207 high" start="+0x167C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT208L" description="GFXMMU LUT entry 208 low" start="+0x1680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT208H" description="GFXMMU LUT entry 208 high" start="+0x1684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT209L" description="GFXMMU LUT entry 209 low" start="+0x1688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT209H" description="GFXMMU LUT entry 209 high" start="+0x168C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT210L" description="GFXMMU LUT entry 210 low" start="+0x1690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT210H" description="GFXMMU LUT entry 210 high" start="+0x1694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT211L" description="GFXMMU LUT entry 211 low" start="+0x1698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT211H" description="GFXMMU LUT entry 211 high" start="+0x169C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT212L" description="GFXMMU LUT entry 212 low" start="+0x16A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT212H" description="GFXMMU LUT entry 212 high" start="+0x16A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT213L" description="GFXMMU LUT entry 213 low" start="+0x16A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT213H" description="GFXMMU LUT entry 213 high" start="+0x16AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT214L" description="GFXMMU LUT entry 214 low" start="+0x16B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT214H" description="GFXMMU LUT entry 214 high" start="+0x16B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT215L" description="GFXMMU LUT entry 215 low" start="+0x16B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT215H" description="GFXMMU LUT entry 215 high" start="+0x16BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT216L" description="GFXMMU LUT entry 216 low" start="+0x16C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT216H" description="GFXMMU LUT entry 216 high" start="+0x16C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT217L" description="GFXMMU LUT entry 217 low" start="+0x16C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT217H" description="GFXMMU LUT entry 217 high" start="+0x16CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT218L" description="GFXMMU LUT entry 218 low" start="+0x16D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT218H" description="GFXMMU LUT entry 218 high" start="+0x16D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT219L" description="GFXMMU LUT entry 219 low" start="+0x16D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT219H" description="GFXMMU LUT entry 219 high" start="+0x16DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT220L" description="GFXMMU LUT entry 220 low" start="+0x16E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT220H" description="GFXMMU LUT entry 220 high" start="+0x16E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT221L" description="GFXMMU LUT entry 221 low" start="+0x16E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT221H" description="GFXMMU LUT entry 221 high" start="+0x16EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT222L" description="GFXMMU LUT entry 222 low" start="+0x16F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT222H" description="GFXMMU LUT entry 222 high" start="+0x16F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT223L" description="GFXMMU LUT entry 223 low" start="+0x16F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT223H" description="GFXMMU LUT entry 223 high" start="+0x16FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT224L" description="GFXMMU LUT entry 224 low" start="+0x1700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT224H" description="GFXMMU LUT entry 224 high" start="+0x1704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT225L" description="GFXMMU LUT entry 225 low" start="+0x1708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT225H" description="GFXMMU LUT entry 225 high" start="+0x170C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT226L" description="GFXMMU LUT entry 226 low" start="+0x1710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT226H" description="GFXMMU LUT entry 226 high" start="+0x1714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT227L" description="GFXMMU LUT entry 227 low" start="+0x1718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT227H" description="GFXMMU LUT entry 227 high" start="+0x171C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT228L" description="GFXMMU LUT entry 228 low" start="+0x1720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT228H" description="GFXMMU LUT entry 228 high" start="+0x1724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT229L" description="GFXMMU LUT entry 229 low" start="+0x1728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT229H" description="GFXMMU LUT entry 229 high" start="+0x172C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT230L" description="GFXMMU LUT entry 230 low" start="+0x1730" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT230H" description="GFXMMU LUT entry 230 high" start="+0x1734" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT231L" description="GFXMMU LUT entry 231 low" start="+0x1738" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT231H" description="GFXMMU LUT entry 231 high" start="+0x173C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT232L" description="GFXMMU LUT entry 232 low" start="+0x1740" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT232H" description="GFXMMU LUT entry 232 high" start="+0x1744" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT233L" description="GFXMMU LUT entry 233 low" start="+0x1748" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT233H" description="GFXMMU LUT entry 233 high" start="+0x174C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT234L" description="GFXMMU LUT entry 234 low" start="+0x1750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT234H" description="GFXMMU LUT entry 234 high" start="+0x1754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT235L" description="GFXMMU LUT entry 235 low" start="+0x1758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT235H" description="GFXMMU LUT entry 235 high" start="+0x175C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT236L" description="GFXMMU LUT entry 236 low" start="+0x1760" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT236H" description="GFXMMU LUT entry 236 high" start="+0x1764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT237L" description="GFXMMU LUT entry 237 low" start="+0x1768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT237H" description="GFXMMU LUT entry 237 high" start="+0x176C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT238L" description="GFXMMU LUT entry 238 low" start="+0x1770" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT238H" description="GFXMMU LUT entry 238 high" start="+0x1774" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT239L" description="GFXMMU LUT entry 239 low" start="+0x1778" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT239H" description="GFXMMU LUT entry 239 high" start="+0x177C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT240L" description="GFXMMU LUT entry 240 low" start="+0x1780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT240H" description="GFXMMU LUT entry 240 high" start="+0x1784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT241L" description="GFXMMU LUT entry 241 low" start="+0x1788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT241H" description="GFXMMU LUT entry 241 high" start="+0x178C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT242L" description="GFXMMU LUT entry 242 low" start="+0x1790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT242H" description="GFXMMU LUT entry 242 high" start="+0x1794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT243L" description="GFXMMU LUT entry 243 low" start="+0x1798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT243H" description="GFXMMU LUT entry 243 high" start="+0x179C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT244L" description="GFXMMU LUT entry 244 low" start="+0x17A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT244H" description="GFXMMU LUT entry 244 high" start="+0x17A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT245L" description="GFXMMU LUT entry 245 low" start="+0x17A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT245H" description="GFXMMU LUT entry 245 high" start="+0x17AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT246L" description="GFXMMU LUT entry 246 low" start="+0x17B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT246H" description="GFXMMU LUT entry 246 high" start="+0x17B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT247L" description="GFXMMU LUT entry 247 low" start="+0x17B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT247H" description="GFXMMU LUT entry 247 high" start="+0x17BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT248L" description="GFXMMU LUT entry 248 low" start="+0x17C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT248H" description="GFXMMU LUT entry 248 high" start="+0x17C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT249L" description="GFXMMU LUT entry 249 low" start="+0x17C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT249H" description="GFXMMU LUT entry 249 high" start="+0x17CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT250L" description="GFXMMU LUT entry 250 low" start="+0x17D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT250H" description="GFXMMU LUT entry 250 high" start="+0x17D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT251L" description="GFXMMU LUT entry 251 low" start="+0x17D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT251H" description="GFXMMU LUT entry 251 high" start="+0x17DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT252L" description="GFXMMU LUT entry 252 low" start="+0x17E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT252H" description="GFXMMU LUT entry 252 high" start="+0x17E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT253L" description="GFXMMU LUT entry 253 low" start="+0x17E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT253H" description="GFXMMU LUT entry 253 high" start="+0x17EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT254L" description="GFXMMU LUT entry 254 low" start="+0x17F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT254H" description="GFXMMU LUT entry 254 high" start="+0x17F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT255L" description="GFXMMU LUT entry 255 low" start="+0x17F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT255H" description="GFXMMU LUT entry 255 high" start="+0x17FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT256L" description="GFXMMU LUT entry 256 low" start="+0x1800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT256H" description="GFXMMU LUT entry 256 high" start="+0x1804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT257L" description="GFXMMU LUT entry 257 low" start="+0x1808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT257H" description="GFXMMU LUT entry 257 high" start="+0x180C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT258L" description="GFXMMU LUT entry 258 low" start="+0x1810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT258H" description="GFXMMU LUT entry 258 high" start="+0x1814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT259L" description="GFXMMU LUT entry 259 low" start="+0x1818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT259H" description="GFXMMU LUT entry 259 high" start="+0x181C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT260L" description="GFXMMU LUT entry 260 low" start="+0x1820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT260H" description="GFXMMU LUT entry 260 high" start="+0x1824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT261L" description="GFXMMU LUT entry 261 low" start="+0x1828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT261H" description="GFXMMU LUT entry 261 high" start="+0x182C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT262L" description="GFXMMU LUT entry 262 low" start="+0x1830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT262H" description="GFXMMU LUT entry 262 high" start="+0x1834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT263L" description="GFXMMU LUT entry 263 low" start="+0x1838" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT263H" description="GFXMMU LUT entry 263 high" start="+0x183C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT264L" description="GFXMMU LUT entry 264 low" start="+0x1840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT264H" description="GFXMMU LUT entry 264 high" start="+0x1844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT265L" description="GFXMMU LUT entry 265 low" start="+0x1848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT265H" description="GFXMMU LUT entry 265 high" start="+0x184C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT266L" description="GFXMMU LUT entry 266 low" start="+0x1850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT266H" description="GFXMMU LUT entry 266 high" start="+0x1854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT267L" description="GFXMMU LUT entry 267 low" start="+0x1858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT267H" description="GFXMMU LUT entry 267 high" start="+0x185C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT268L" description="GFXMMU LUT entry 268 low" start="+0x1860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT268H" description="GFXMMU LUT entry 268 high" start="+0x1864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT269L" description="GFXMMU LUT entry 269 low" start="+0x1868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT269H" description="GFXMMU LUT entry 269 high" start="+0x186C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT270L" description="GFXMMU LUT entry 270 low" start="+0x1870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT270H" description="GFXMMU LUT entry 270 high" start="+0x1874" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT271L" description="GFXMMU LUT entry 271 low" start="+0x1878" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT271H" description="GFXMMU LUT entry 271 high" start="+0x187C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT272L" description="GFXMMU LUT entry 272 low" start="+0x1880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT272H" description="GFXMMU LUT entry 272 high" start="+0x1884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT273L" description="GFXMMU LUT entry 273 low" start="+0x1888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT273H" description="GFXMMU LUT entry 273 high" start="+0x188C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT274L" description="GFXMMU LUT entry 274 low" start="+0x1890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT274H" description="GFXMMU LUT entry 274 high" start="+0x1894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT275L" description="GFXMMU LUT entry 275 low" start="+0x1898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT275H" description="GFXMMU LUT entry 275 high" start="+0x189C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT276L" description="GFXMMU LUT entry 276 low" start="+0x18A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT276H" description="GFXMMU LUT entry 276 high" start="+0x18A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT277L" description="GFXMMU LUT entry 277 low" start="+0x18A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT277H" description="GFXMMU LUT entry 277 high" start="+0x18AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT278L" description="GFXMMU LUT entry 278 low" start="+0x18B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT278H" description="GFXMMU LUT entry 278 high" start="+0x18B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT279L" description="GFXMMU LUT entry 279 low" start="+0x18B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT279H" description="GFXMMU LUT entry 279 high" start="+0x18BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT280L" description="GFXMMU LUT entry 280 low" start="+0x18C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT280H" description="GFXMMU LUT entry 280 high" start="+0x18C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT281L" description="GFXMMU LUT entry 281 low" start="+0x18C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT281H" description="GFXMMU LUT entry 281 high" start="+0x18CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT282L" description="GFXMMU LUT entry 282 low" start="+0x18D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT282H" description="GFXMMU LUT entry 282 high" start="+0x18D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT283L" description="GFXMMU LUT entry 283 low" start="+0x18D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT283H" description="GFXMMU LUT entry 283 high" start="+0x18DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT284L" description="GFXMMU LUT entry 284 low" start="+0x18E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT284H" description="GFXMMU LUT entry 284 high" start="+0x18E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT285L" description="GFXMMU LUT entry 285 low" start="+0x18E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT285H" description="GFXMMU LUT entry 285 high" start="+0x18EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT286L" description="GFXMMU LUT entry 286 low" start="+0x18F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT286H" description="GFXMMU LUT entry 286 high" start="+0x18F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT287L" description="GFXMMU LUT entry 287 low" start="+0x18F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT287H" description="GFXMMU LUT entry 287 high" start="+0x18FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT288L" description="GFXMMU LUT entry 288 low" start="+0x1900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT288H" description="GFXMMU LUT entry 288 high" start="+0x1904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT289L" description="GFXMMU LUT entry 289 low" start="+0x1908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT289H" description="GFXMMU LUT entry 289 high" start="+0x190C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT290L" description="GFXMMU LUT entry 290 low" start="+0x1910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT290H" description="GFXMMU LUT entry 290 high" start="+0x1914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT291L" description="GFXMMU LUT entry 291 low" start="+0x1918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT291H" description="GFXMMU LUT entry 291 high" start="+0x191C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT292L" description="GFXMMU LUT entry 292 low" start="+0x1920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT292H" description="GFXMMU LUT entry 292 high" start="+0x1924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT293L" description="GFXMMU LUT entry 293 low" start="+0x1928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT293H" description="GFXMMU LUT entry 293 high" start="+0x192C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT294L" description="GFXMMU LUT entry 294 low" start="+0x1930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT294H" description="GFXMMU LUT entry 294 high" start="+0x1934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT295L" description="GFXMMU LUT entry 295 low" start="+0x1938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT295H" description="GFXMMU LUT entry 295 high" start="+0x193C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT296L" description="GFXMMU LUT entry 296 low" start="+0x1940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT296H" description="GFXMMU LUT entry 296 high" start="+0x1944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT297L" description="GFXMMU LUT entry 297 low" start="+0x1948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT297H" description="GFXMMU LUT entry 297 high" start="+0x194C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT298L" description="GFXMMU LUT entry 298 low" start="+0x1950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT298H" description="GFXMMU LUT entry 298 high" start="+0x1954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT299L" description="GFXMMU LUT entry 299 low" start="+0x1958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT299H" description="GFXMMU LUT entry 299 high" start="+0x195C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT300L" description="GFXMMU LUT entry 300 low" start="+0x1960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT300H" description="GFXMMU LUT entry 300 high" start="+0x1964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT301L" description="GFXMMU LUT entry 301 low" start="+0x1968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT301H" description="GFXMMU LUT entry 301 high" start="+0x196C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT302L" description="GFXMMU LUT entry 302 low" start="+0x1970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT302H" description="GFXMMU LUT entry 302 high" start="+0x1974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT303L" description="GFXMMU LUT entry 303 low" start="+0x1978" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT303H" description="GFXMMU LUT entry 303 high" start="+0x197C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT304L" description="GFXMMU LUT entry 304 low" start="+0x1980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT304H" description="GFXMMU LUT entry 304 high" start="+0x1984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT305L" description="GFXMMU LUT entry 305 low" start="+0x1988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT305H" description="GFXMMU LUT entry 305 high" start="+0x198C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT306L" description="GFXMMU LUT entry 306 low" start="+0x1990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT306H" description="GFXMMU LUT entry 306 high" start="+0x1994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT307L" description="GFXMMU LUT entry 307 low" start="+0x1998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT307H" description="GFXMMU LUT entry 307 high" start="+0x199C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT308L" description="GFXMMU LUT entry 308 low" start="+0x19A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT308H" description="GFXMMU LUT entry 308 high" start="+0x19A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT309L" description="GFXMMU LUT entry 309 low" start="+0x19A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT309H" description="GFXMMU LUT entry 309 high" start="+0x19AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT310L" description="GFXMMU LUT entry 310 low" start="+0x19B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT310H" description="GFXMMU LUT entry 310 high" start="+0x19B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT311L" description="GFXMMU LUT entry 311 low" start="+0x19B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT311H" description="GFXMMU LUT entry 311 high" start="+0x19BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT312L" description="GFXMMU LUT entry 312 low" start="+0x19C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT312H" description="GFXMMU LUT entry 312 high" start="+0x19C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT313L" description="GFXMMU LUT entry 313 low" start="+0x19C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT313H" description="GFXMMU LUT entry 313 high" start="+0x19CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT314L" description="GFXMMU LUT entry 314 low" start="+0x19D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT314H" description="GFXMMU LUT entry 314 high" start="+0x19D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT315L" description="GFXMMU LUT entry 315 low" start="+0x19D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT315H" description="GFXMMU LUT entry 315 high" start="+0x19DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT316L" description="GFXMMU LUT entry 316 low" start="+0x19E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT316H" description="GFXMMU LUT entry 316 high" start="+0x19E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT317L" description="GFXMMU LUT entry 317 low" start="+0x19E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT317H" description="GFXMMU LUT entry 317 high" start="+0x19EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT318L" description="GFXMMU LUT entry 318 low" start="+0x19F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT318H" description="GFXMMU LUT entry 318 high" start="+0x19F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT319L" description="GFXMMU LUT entry 319 low" start="+0x19F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT319H" description="GFXMMU LUT entry 319 high" start="+0x19FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT320L" description="GFXMMU LUT entry 320 low" start="+0x1A00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT320H" description="GFXMMU LUT entry 320 high" start="+0x1A04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT321L" description="GFXMMU LUT entry 321 low" start="+0x1A08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT321H" description="GFXMMU LUT entry 321 high" start="+0x1A0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT322L" description="GFXMMU LUT entry 322 low" start="+0x1A10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT322H" description="GFXMMU LUT entry 322 high" start="+0x1A14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT323L" description="GFXMMU LUT entry 323 low" start="+0x1A18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT323H" description="GFXMMU LUT entry 323 high" start="+0x1A1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT324L" description="GFXMMU LUT entry 324 low" start="+0x1A20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT324H" description="GFXMMU LUT entry 324 high" start="+0x1A24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT325L" description="GFXMMU LUT entry 325 low" start="+0x1A28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT325H" description="GFXMMU LUT entry 325 high" start="+0x1A2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT326L" description="GFXMMU LUT entry 326 low" start="+0x1A30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT326H" description="GFXMMU LUT entry 326 high" start="+0x1A34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT327L" description="GFXMMU LUT entry 327 low" start="+0x1A38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT327H" description="GFXMMU LUT entry 327 high" start="+0x1A3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT328L" description="GFXMMU LUT entry 328 low" start="+0x1A40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT328H" description="GFXMMU LUT entry 328 high" start="+0x1A44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT329L" description="GFXMMU LUT entry 329 low" start="+0x1A48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT329H" description="GFXMMU LUT entry 329 high" start="+0x1A4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT330L" description="GFXMMU LUT entry 330 low" start="+0x1A50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT330H" description="GFXMMU LUT entry 330 high" start="+0x1A54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT331L" description="GFXMMU LUT entry 331 low" start="+0x1A58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT331H" description="GFXMMU LUT entry 331 high" start="+0x1A5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT332L" description="GFXMMU LUT entry 332 low" start="+0x1A60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT332H" description="GFXMMU LUT entry 332 high" start="+0x1A64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT333L" description="GFXMMU LUT entry 333 low" start="+0x1A68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT333H" description="GFXMMU LUT entry 333 high" start="+0x1A6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT334L" description="GFXMMU LUT entry 334 low" start="+0x1A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT334H" description="GFXMMU LUT entry 334 high" start="+0x1A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT335L" description="GFXMMU LUT entry 335 low" start="+0x1A78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT335H" description="GFXMMU LUT entry 335 high" start="+0x1A7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT336L" description="GFXMMU LUT entry 336 low" start="+0x1A80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT336H" description="GFXMMU LUT entry 336 high" start="+0x1A84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT337L" description="GFXMMU LUT entry 337 low" start="+0x1A88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT337H" description="GFXMMU LUT entry 337 high" start="+0x1A8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT338L" description="GFXMMU LUT entry 338 low" start="+0x1A90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT338H" description="GFXMMU LUT entry 338 high" start="+0x1A94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT339L" description="GFXMMU LUT entry 339 low" start="+0x1A98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT339H" description="GFXMMU LUT entry 339 high" start="+0x1A9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT340L" description="GFXMMU LUT entry 340 low" start="+0x1AA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT340H" description="GFXMMU LUT entry 340 high" start="+0x1AA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT341L" description="GFXMMU LUT entry 341 low" start="+0x1AA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT341H" description="GFXMMU LUT entry 341 high" start="+0x1AAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT342L" description="GFXMMU LUT entry 342 low" start="+0x1AB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT342H" description="GFXMMU LUT entry 342 high" start="+0x1AB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT343L" description="GFXMMU LUT entry 343 low" start="+0x1AB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT343H" description="GFXMMU LUT entry 343 high" start="+0x1ABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT344L" description="GFXMMU LUT entry 344 low" start="+0x1AC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT344H" description="GFXMMU LUT entry 344 high" start="+0x1AC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT345L" description="GFXMMU LUT entry 345 low" start="+0x1AC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT345H" description="GFXMMU LUT entry 345 high" start="+0x1ACC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT346L" description="GFXMMU LUT entry 346 low" start="+0x1AD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT346H" description="GFXMMU LUT entry 346 high" start="+0x1AD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT347L" description="GFXMMU LUT entry 347 low" start="+0x1AD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT347H" description="GFXMMU LUT entry 347 high" start="+0x1ADC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT348L" description="GFXMMU LUT entry 348 low" start="+0x1AE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT348H" description="GFXMMU LUT entry 348 high" start="+0x1AE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT349L" description="GFXMMU LUT entry 349 low" start="+0x1AE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT349H" description="GFXMMU LUT entry 349 high" start="+0x1AEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT350L" description="GFXMMU LUT entry 350 low" start="+0x1AF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT350H" description="GFXMMU LUT entry 350 high" start="+0x1AF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT351L" description="GFXMMU LUT entry 351 low" start="+0x1AF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT351H" description="GFXMMU LUT entry 351 high" start="+0x1AFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT352L" description="GFXMMU LUT entry 352 low" start="+0x1B00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT352H" description="GFXMMU LUT entry 352 high" start="+0x1B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT353L" description="GFXMMU LUT entry 353 low" start="+0x1B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT353H" description="GFXMMU LUT entry 353 high" start="+0x1B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT354L" description="GFXMMU LUT entry 354 low" start="+0x1B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT354H" description="GFXMMU LUT entry 354 high" start="+0x1B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT355L" description="GFXMMU LUT entry 355 low" start="+0x1B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT355H" description="GFXMMU LUT entry 355 high" start="+0x1B1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT356L" description="GFXMMU LUT entry 356 low" start="+0x1B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT356H" description="GFXMMU LUT entry 356 high" start="+0x1B24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT357L" description="GFXMMU LUT entry 357 low" start="+0x1B28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT357H" description="GFXMMU LUT entry 357 high" start="+0x1B2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT358L" description="GFXMMU LUT entry 358 low" start="+0x1B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT358H" description="GFXMMU LUT entry 358 high" start="+0x1B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT359L" description="GFXMMU LUT entry 359 low" start="+0x1B38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT359H" description="GFXMMU LUT entry 359 high" start="+0x1B3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT360L" description="GFXMMU LUT entry 360 low" start="+0x1B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT360H" description="GFXMMU LUT entry 360 high" start="+0x1B44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT361L" description="GFXMMU LUT entry 361 low" start="+0x1B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT361H" description="GFXMMU LUT entry 361 high" start="+0x1B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT362L" description="GFXMMU LUT entry 362 low" start="+0x1B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT362H" description="GFXMMU LUT entry 362 high" start="+0x1B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT363L" description="GFXMMU LUT entry 363 low" start="+0x1B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT363H" description="GFXMMU LUT entry 363 high" start="+0x1B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT364L" description="GFXMMU LUT entry 364 low" start="+0x1B60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT364H" description="GFXMMU LUT entry 364 high" start="+0x1B64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT365L" description="GFXMMU LUT entry 365 low" start="+0x1B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT365H" description="GFXMMU LUT entry 365 high" start="+0x1B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT366L" description="GFXMMU LUT entry 366 low" start="+0x1B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT366H" description="GFXMMU LUT entry 366 high" start="+0x1B74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT367L" description="GFXMMU LUT entry 367 low" start="+0x1B78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT367H" description="GFXMMU LUT entry 367 high" start="+0x1B7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT368L" description="GFXMMU LUT entry 368 low" start="+0x1B80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT368H" description="GFXMMU LUT entry 368 high" start="+0x1B84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT369L" description="GFXMMU LUT entry 369 low" start="+0x1B88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT369H" description="GFXMMU LUT entry 369 high" start="+0x1B8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT370L" description="GFXMMU LUT entry 370 low" start="+0x1B90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT370H" description="GFXMMU LUT entry 370 high" start="+0x1B94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT371L" description="GFXMMU LUT entry 371 low" start="+0x1B98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT371H" description="GFXMMU LUT entry 371 high" start="+0x1B9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT372L" description="GFXMMU LUT entry 372 low" start="+0x1BA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT372H" description="GFXMMU LUT entry 372 high" start="+0x1BA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT373L" description="GFXMMU LUT entry 373 low" start="+0x1BA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT373H" description="GFXMMU LUT entry 373 high" start="+0x1BAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT374L" description="GFXMMU LUT entry 374 low" start="+0x1BB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT374H" description="GFXMMU LUT entry 374 high" start="+0x1BB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT375L" description="GFXMMU LUT entry 375 low" start="+0x1BB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT375H" description="GFXMMU LUT entry 375 high" start="+0x1BBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT376L" description="GFXMMU LUT entry 376 low" start="+0x1BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT376H" description="GFXMMU LUT entry 376 high" start="+0x1BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT377L" description="GFXMMU LUT entry 377 low" start="+0x1BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT377H" description="GFXMMU LUT entry 377 high" start="+0x1BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT378L" description="GFXMMU LUT entry 378 low" start="+0x1BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT378H" description="GFXMMU LUT entry 378 high" start="+0x1BD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT379L" description="GFXMMU LUT entry 379 low" start="+0x1BD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT379H" description="GFXMMU LUT entry 379 high" start="+0x1BDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT380L" description="GFXMMU LUT entry 380 low" start="+0x1BE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT380H" description="GFXMMU LUT entry 380 high" start="+0x1BE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT381L" description="GFXMMU LUT entry 381 low" start="+0x1BE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT381H" description="GFXMMU LUT entry 381 high" start="+0x1BEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT382L" description="GFXMMU LUT entry 382 low" start="+0x1BF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT382H" description="GFXMMU LUT entry 382 high" start="+0x1BF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT383L" description="GFXMMU LUT entry 383 low" start="+0x1BF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT383H" description="GFXMMU LUT entry 383 high" start="+0x1BFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT384L" description="GFXMMU LUT entry 384 low" start="+0x1C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT384H" description="GFXMMU LUT entry 384 high" start="+0x1C04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT385L" description="GFXMMU LUT entry 385 low" start="+0x1C08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT385H" description="GFXMMU LUT entry 385 high" start="+0x1C0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT386L" description="GFXMMU LUT entry 386 low" start="+0x1C10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT386H" description="GFXMMU LUT entry 386 high" start="+0x1C14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT387L" description="GFXMMU LUT entry 387 low" start="+0x1C18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT387H" description="GFXMMU LUT entry 387 high" start="+0x1C1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT388L" description="GFXMMU LUT entry 388 low" start="+0x1C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT388H" description="GFXMMU LUT entry 388 high" start="+0x1C24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT389L" description="GFXMMU LUT entry 389 low" start="+0x1C28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT389H" description="GFXMMU LUT entry 389 high" start="+0x1C2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT390L" description="GFXMMU LUT entry 390 low" start="+0x1C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT390H" description="GFXMMU LUT entry 390 high" start="+0x1C34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT391L" description="GFXMMU LUT entry 391 low" start="+0x1C38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT391H" description="GFXMMU LUT entry 391 high" start="+0x1C3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT392L" description="GFXMMU LUT entry 392 low" start="+0x1C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT392H" description="GFXMMU LUT entry 392 high" start="+0x1C44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT393L" description="GFXMMU LUT entry 393 low" start="+0x1C48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT393H" description="GFXMMU LUT entry 393 high" start="+0x1C4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT394L" description="GFXMMU LUT entry 394 low" start="+0x1C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT394H" description="GFXMMU LUT entry 394 high" start="+0x1C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT395L" description="GFXMMU LUT entry 395 low" start="+0x1C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT395H" description="GFXMMU LUT entry 395 high" start="+0x1C5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT396L" description="GFXMMU LUT entry 396 low" start="+0x1C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT396H" description="GFXMMU LUT entry 396 high" start="+0x1C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT397L" description="GFXMMU LUT entry 397 low" start="+0x1C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT397H" description="GFXMMU LUT entry 397 high" start="+0x1C6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT398L" description="GFXMMU LUT entry 398 low" start="+0x1C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT398H" description="GFXMMU LUT entry 398 high" start="+0x1C74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT399L" description="GFXMMU LUT entry 399 low" start="+0x1C78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT399H" description="GFXMMU LUT entry 399 high" start="+0x1C7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT400L" description="GFXMMU LUT entry 400 low" start="+0x1C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT400H" description="GFXMMU LUT entry 400 high" start="+0x1C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT401L" description="GFXMMU LUT entry 401 low" start="+0x1C88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT401H" description="GFXMMU LUT entry 401 high" start="+0x1C8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT402L" description="GFXMMU LUT entry 402 low" start="+0x1C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT402H" description="GFXMMU LUT entry 402 high" start="+0x1C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT403L" description="GFXMMU LUT entry 403 low" start="+0x1C98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT403H" description="GFXMMU LUT entry 403 high" start="+0x1C9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT404L" description="GFXMMU LUT entry 404 low" start="+0x1CA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT404H" description="GFXMMU LUT entry 404 high" start="+0x1CA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT405L" description="GFXMMU LUT entry 405 low" start="+0x1CA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT405H" description="GFXMMU LUT entry 405 high" start="+0x1CAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT406L" description="GFXMMU LUT entry 406 low" start="+0x1CB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT406H" description="GFXMMU LUT entry 406 high" start="+0x1CB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT407L" description="GFXMMU LUT entry 407 low" start="+0x1CB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT407H" description="GFXMMU LUT entry 407 high" start="+0x1CBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT408L" description="GFXMMU LUT entry 408 low" start="+0x1CC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT408H" description="GFXMMU LUT entry 408 high" start="+0x1CC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT409L" description="GFXMMU LUT entry 409 low" start="+0x1CC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT409H" description="GFXMMU LUT entry 409 high" start="+0x1CCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT410L" description="GFXMMU LUT entry 410 low" start="+0x1CD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT410H" description="GFXMMU LUT entry 410 high" start="+0x1CD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT411L" description="GFXMMU LUT entry 411 low" start="+0x1CD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT411H" description="GFXMMU LUT entry 411 high" start="+0x1CDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT412L" description="GFXMMU LUT entry 412 low" start="+0x1CE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT412H" description="GFXMMU LUT entry 412 high" start="+0x1CE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT413L" description="GFXMMU LUT entry 413 low" start="+0x1CE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT413H" description="GFXMMU LUT entry 413 high" start="+0x1CEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT414L" description="GFXMMU LUT entry 414 low" start="+0x1CF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT414H" description="GFXMMU LUT entry 414 high" start="+0x1CF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT415L" description="GFXMMU LUT entry 415 low" start="+0x1CF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT415H" description="GFXMMU LUT entry 415 high" start="+0x1CFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT416L" description="GFXMMU LUT entry 416 low" start="+0x1D00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT416H" description="GFXMMU LUT entry 416 high" start="+0x1D04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT417L" description="GFXMMU LUT entry 417 low" start="+0x1D08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT417H" description="GFXMMU LUT entry 417 high" start="+0x1D0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT418L" description="GFXMMU LUT entry 418 low" start="+0x1D10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT418H" description="GFXMMU LUT entry 418 high" start="+0x1D14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT419L" description="GFXMMU LUT entry 419 low" start="+0x1D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT419H" description="GFXMMU LUT entry 419 high" start="+0x1D1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT420L" description="GFXMMU LUT entry 420 low" start="+0x1D20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT420H" description="GFXMMU LUT entry 420 high" start="+0x1D24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT421L" description="GFXMMU LUT entry 421 low" start="+0x1D28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT421H" description="GFXMMU LUT entry 421 high" start="+0x1D2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT422L" description="GFXMMU LUT entry 422 low" start="+0x1D30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT422H" description="GFXMMU LUT entry 422 high" start="+0x1D34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT423L" description="GFXMMU LUT entry 423 low" start="+0x1D38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT423H" description="GFXMMU LUT entry 423 high" start="+0x1D3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT424L" description="GFXMMU LUT entry 424 low" start="+0x1D40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT424H" description="GFXMMU LUT entry 424 high" start="+0x1D44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT425L" description="GFXMMU LUT entry 425 low" start="+0x1D48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT425H" description="GFXMMU LUT entry 425 high" start="+0x1D4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT426L" description="GFXMMU LUT entry 426 low" start="+0x1D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT426H" description="GFXMMU LUT entry 426 high" start="+0x1D54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT427L" description="GFXMMU LUT entry 427 low" start="+0x1D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT427H" description="GFXMMU LUT entry 427 high" start="+0x1D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT428L" description="GFXMMU LUT entry 428 low" start="+0x1D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT428H" description="GFXMMU LUT entry 428 high" start="+0x1D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT429L" description="GFXMMU LUT entry 429 low" start="+0x1D68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT429H" description="GFXMMU LUT entry 429 high" start="+0x1D6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT430L" description="GFXMMU LUT entry 430 low" start="+0x1D70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT430H" description="GFXMMU LUT entry 430 high" start="+0x1D74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT431L" description="GFXMMU LUT entry 431 low" start="+0x1D78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT431H" description="GFXMMU LUT entry 431 high" start="+0x1D7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT432L" description="GFXMMU LUT entry 432 low" start="+0x1D80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT432H" description="GFXMMU LUT entry 432 high" start="+0x1D84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT433L" description="GFXMMU LUT entry 433 low" start="+0x1D88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT433H" description="GFXMMU LUT entry 433 high" start="+0x1D8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT434L" description="GFXMMU LUT entry 434 low" start="+0x1D90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT434H" description="GFXMMU LUT entry 434 high" start="+0x1D94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT435L" description="GFXMMU LUT entry 435 low" start="+0x1D98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT435H" description="GFXMMU LUT entry 435 high" start="+0x1D9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT436L" description="GFXMMU LUT entry 436 low" start="+0x1DA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT436H" description="GFXMMU LUT entry 436 high" start="+0x1DA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT437L" description="GFXMMU LUT entry 437 low" start="+0x1DA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT437H" description="GFXMMU LUT entry 437 high" start="+0x1DAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT438L" description="GFXMMU LUT entry 438 low" start="+0x1DB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT438H" description="GFXMMU LUT entry 438 high" start="+0x1DB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT439L" description="GFXMMU LUT entry 439 low" start="+0x1DB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT439H" description="GFXMMU LUT entry 439 high" start="+0x1DBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT440L" description="GFXMMU LUT entry 440 low" start="+0x1DC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT440H" description="GFXMMU LUT entry 440 high" start="+0x1DC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT441L" description="GFXMMU LUT entry 441 low" start="+0x1DC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT441H" description="GFXMMU LUT entry 441 high" start="+0x1DCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT442L" description="GFXMMU LUT entry 442 low" start="+0x1DD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT442H" description="GFXMMU LUT entry 442 high" start="+0x1DD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT443L" description="GFXMMU LUT entry 443 low" start="+0x1DD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT443H" description="GFXMMU LUT entry 443 high" start="+0x1DDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT444L" description="GFXMMU LUT entry 444 low" start="+0x1DE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT444H" description="GFXMMU LUT entry 444 high" start="+0x1DE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT445L" description="GFXMMU LUT entry 445 low" start="+0x1DE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT445H" description="GFXMMU LUT entry 445 high" start="+0x1DEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT446L" description="GFXMMU LUT entry 446 low" start="+0x1DF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT446H" description="GFXMMU LUT entry 446 high" start="+0x1DF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT447L" description="GFXMMU LUT entry 447 low" start="+0x1DF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT447H" description="GFXMMU LUT entry 447 high" start="+0x1DFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT448L" description="GFXMMU LUT entry 448 low" start="+0x1E00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT448H" description="GFXMMU LUT entry 448 high" start="+0x1E04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT449L" description="GFXMMU LUT entry 449 low" start="+0x1E08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT449H" description="GFXMMU LUT entry 449 high" start="+0x1E0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT450L" description="GFXMMU LUT entry 450 low" start="+0x1E10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT450H" description="GFXMMU LUT entry 450 high" start="+0x1E14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT451L" description="GFXMMU LUT entry 451 low" start="+0x1E18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT451H" description="GFXMMU LUT entry 451 high" start="+0x1E1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT452L" description="GFXMMU LUT entry 452 low" start="+0x1E20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT452H" description="GFXMMU LUT entry 452 high" start="+0x1E24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT453L" description="GFXMMU LUT entry 453 low" start="+0x1E28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT453H" description="GFXMMU LUT entry 453 high" start="+0x1E2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT454L" description="GFXMMU LUT entry 454 low" start="+0x1E30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT454H" description="GFXMMU LUT entry 454 high" start="+0x1E34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT455L" description="GFXMMU LUT entry 455 low" start="+0x1E38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT455H" description="GFXMMU LUT entry 455 high" start="+0x1E3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT456L" description="GFXMMU LUT entry 456 low" start="+0x1E40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT456H" description="GFXMMU LUT entry 456 high" start="+0x1E44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT457L" description="GFXMMU LUT entry 457 low" start="+0x1E48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT457H" description="GFXMMU LUT entry 457 high" start="+0x1E4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT458L" description="GFXMMU LUT entry 458 low" start="+0x1E50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT458H" description="GFXMMU LUT entry 458 high" start="+0x1E54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT459L" description="GFXMMU LUT entry 459 low" start="+0x1E58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT459H" description="GFXMMU LUT entry 459 high" start="+0x1E5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT460L" description="GFXMMU LUT entry 460 low" start="+0x1E60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT460H" description="GFXMMU LUT entry 460 high" start="+0x1E64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT461L" description="GFXMMU LUT entry 461 low" start="+0x1E68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT461H" description="GFXMMU LUT entry 461 high" start="+0x1E6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT462L" description="GFXMMU LUT entry 462 low" start="+0x1E70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT462H" description="GFXMMU LUT entry 462 high" start="+0x1E74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT463L" description="GFXMMU LUT entry 463 low" start="+0x1E78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT463H" description="GFXMMU LUT entry 463 high" start="+0x1E7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT464L" description="GFXMMU LUT entry 464 low" start="+0x1E80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT464H" description="GFXMMU LUT entry 464 high" start="+0x1E84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT465L" description="GFXMMU LUT entry 465 low" start="+0x1E88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT465H" description="GFXMMU LUT entry 465 high" start="+0x1E8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT466L" description="GFXMMU LUT entry 466 low" start="+0x1E90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT466H" description="GFXMMU LUT entry 466 high" start="+0x1E94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT467L" description="GFXMMU LUT entry 467 low" start="+0x1E98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT467H" description="GFXMMU LUT entry 467 high" start="+0x1E9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT468L" description="GFXMMU LUT entry 468 low" start="+0x1EA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT468H" description="GFXMMU LUT entry 468 high" start="+0x1EA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT469L" description="GFXMMU LUT entry 469 low" start="+0x1EA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT469H" description="GFXMMU LUT entry 469 high" start="+0x1EAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT470L" description="GFXMMU LUT entry 470 low" start="+0x1EB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT470H" description="GFXMMU LUT entry 470 high" start="+0x1EB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT471L" description="GFXMMU LUT entry 471 low" start="+0x1EB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT471H" description="GFXMMU LUT entry 471 high" start="+0x1EBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT472L" description="GFXMMU LUT entry 472 low" start="+0x1EC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT472H" description="GFXMMU LUT entry 472 high" start="+0x1EC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT473L" description="GFXMMU LUT entry 473 low" start="+0x1EC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT473H" description="GFXMMU LUT entry 473 high" start="+0x1ECC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT474L" description="GFXMMU LUT entry 474 low" start="+0x1ED0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT474H" description="GFXMMU LUT entry 474 high" start="+0x1ED4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT475L" description="GFXMMU LUT entry 475 low" start="+0x1ED8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT475H" description="GFXMMU LUT entry 475 high" start="+0x1EDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT476L" description="GFXMMU LUT entry 476 low" start="+0x1EE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT476H" description="GFXMMU LUT entry 476 high" start="+0x1EE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT477L" description="GFXMMU LUT entry 477 low" start="+0x1EE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT477H" description="GFXMMU LUT entry 477 high" start="+0x1EEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT478L" description="GFXMMU LUT entry 478 low" start="+0x1EF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT478H" description="GFXMMU LUT entry 478 high" start="+0x1EF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT479L" description="GFXMMU LUT entry 479 low" start="+0x1EF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT479H" description="GFXMMU LUT entry 479 high" start="+0x1EFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT480L" description="GFXMMU LUT entry 480 low" start="+0x1F00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT480H" description="GFXMMU LUT entry 480 high" start="+0x1F04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT481L" description="GFXMMU LUT entry 481 low" start="+0x1F08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT481H" description="GFXMMU LUT entry 481 high" start="+0x1F0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT482L" description="GFXMMU LUT entry 482 low" start="+0x1F10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT482H" description="GFXMMU LUT entry 482 high" start="+0x1F14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT483L" description="GFXMMU LUT entry 483 low" start="+0x1F18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT483H" description="GFXMMU LUT entry 483 high" start="+0x1F1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT484L" description="GFXMMU LUT entry 484 low" start="+0x1F20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT484H" description="GFXMMU LUT entry 484 high" start="+0x1F24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT485L" description="GFXMMU LUT entry 485 low" start="+0x1F28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT485H" description="GFXMMU LUT entry 485 high" start="+0x1F2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT486L" description="GFXMMU LUT entry 486 low" start="+0x1F30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT486H" description="GFXMMU LUT entry 486 high" start="+0x1F34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT487L" description="GFXMMU LUT entry 487 low" start="+0x1F38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT487H" description="GFXMMU LUT entry 487 high" start="+0x1F3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT488L" description="GFXMMU LUT entry 488 low" start="+0x1F40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT488H" description="GFXMMU LUT entry 488 high" start="+0x1F44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT489L" description="GFXMMU LUT entry 489 low" start="+0x1F48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT489H" description="GFXMMU LUT entry 489 high" start="+0x1F4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT490L" description="GFXMMU LUT entry 490 low" start="+0x1F50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT490H" description="GFXMMU LUT entry 490 high" start="+0x1F54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT491L" description="GFXMMU LUT entry 491 low" start="+0x1F58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT491H" description="GFXMMU LUT entry 491 high" start="+0x1F5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT492L" description="GFXMMU LUT entry 492 low" start="+0x1F60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT492H" description="GFXMMU LUT entry 492 high" start="+0x1F64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT493L" description="GFXMMU LUT entry 493 low" start="+0x1F68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT493H" description="GFXMMU LUT entry 493 high" start="+0x1F6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT494L" description="GFXMMU LUT entry 494 low" start="+0x1F70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT494H" description="GFXMMU LUT entry 494 high" start="+0x1F74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT495L" description="GFXMMU LUT entry 495 low" start="+0x1F78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT495H" description="GFXMMU LUT entry 495 high" start="+0x1F7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT496L" description="GFXMMU LUT entry 496 low" start="+0x1F80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT496H" description="GFXMMU LUT entry 496 high" start="+0x1F84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT497L" description="GFXMMU LUT entry 497 low" start="+0x1F88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT497H" description="GFXMMU LUT entry 497 high" start="+0x1F8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT498L" description="GFXMMU LUT entry 498 low" start="+0x1F90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT498H" description="GFXMMU LUT entry 498 high" start="+0x1F94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT499L" description="GFXMMU LUT entry 499 low" start="+0x1F98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT499H" description="GFXMMU LUT entry 499 high" start="+0x1F9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT500L" description="GFXMMU LUT entry 500 low" start="+0x1FA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT500H" description="GFXMMU LUT entry 500 high" start="+0x1FA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT501L" description="GFXMMU LUT entry 501 low" start="+0x1FA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT501H" description="GFXMMU LUT entry 501 high" start="+0x1FAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT502L" description="GFXMMU LUT entry 502 low" start="+0x1FB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT502H" description="GFXMMU LUT entry 502 high" start="+0x1FB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT503L" description="GFXMMU LUT entry 503 low" start="+0x1FB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT503H" description="GFXMMU LUT entry 503 high" start="+0x1FBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT504L" description="GFXMMU LUT entry 504 low" start="+0x1FC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT504H" description="GFXMMU LUT entry 504 high" start="+0x1FC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT505L" description="GFXMMU LUT entry 505 low" start="+0x1FC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT505H" description="GFXMMU LUT entry 505 high" start="+0x1FCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT506L" description="GFXMMU LUT entry 506 low" start="+0x1FD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT506H" description="GFXMMU LUT entry 506 high" start="+0x1FD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT507L" description="GFXMMU LUT entry 507 low" start="+0x1FD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT507H" description="GFXMMU LUT entry 507 high" start="+0x1FDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT508L" description="GFXMMU LUT entry 508 low" start="+0x1FE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT508H" description="GFXMMU LUT entry 508 high" start="+0x1FE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT509L" description="GFXMMU LUT entry 509 low" start="+0x1FE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT509H" description="GFXMMU LUT entry 509 high" start="+0x1FEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT510L" description="GFXMMU LUT entry 510 low" start="+0x1FF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT510H" description="GFXMMU LUT entry 510 high" start="+0x1FF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT511L" description="GFXMMU LUT entry 511 low" start="+0x1FF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT511H" description="GFXMMU LUT entry 511 high" start="+0x1FFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT512L" description="GFXMMU LUT entry 512 low" start="+0x2000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT512H" description="GFXMMU LUT entry 512 high" start="+0x2004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT513L" description="GFXMMU LUT entry 513 low" start="+0x2008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT513H" description="GFXMMU LUT entry 513 high" start="+0x200C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT514L" description="GFXMMU LUT entry 514 low" start="+0x2010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT514H" description="GFXMMU LUT entry 514 high" start="+0x2014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT515L" description="GFXMMU LUT entry 515 low" start="+0x2018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT515H" description="GFXMMU LUT entry 515 high" start="+0x201C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT516L" description="GFXMMU LUT entry 516 low" start="+0x2020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT516H" description="GFXMMU LUT entry 516 high" start="+0x2024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT517L" description="GFXMMU LUT entry 517 low" start="+0x2028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT517H" description="GFXMMU LUT entry 517 high" start="+0x202C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT518L" description="GFXMMU LUT entry 518 low" start="+0x2030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT518H" description="GFXMMU LUT entry 518 high" start="+0x2034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT519L" description="GFXMMU LUT entry 519 low" start="+0x2038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT519H" description="GFXMMU LUT entry 519 high" start="+0x203C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT520L" description="GFXMMU LUT entry 520 low" start="+0x2040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT520H" description="GFXMMU LUT entry 520 high" start="+0x2044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT521L" description="GFXMMU LUT entry 521 low" start="+0x2048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT521H" description="GFXMMU LUT entry 521 high" start="+0x204C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT522L" description="GFXMMU LUT entry 522 low" start="+0x2050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT522H" description="GFXMMU LUT entry 522 high" start="+0x2054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT523L" description="GFXMMU LUT entry 523 low" start="+0x2058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT523H" description="GFXMMU LUT entry 523 high" start="+0x205C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT524L" description="GFXMMU LUT entry 524 low" start="+0x2060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT524H" description="GFXMMU LUT entry 524 high" start="+0x2064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT525L" description="GFXMMU LUT entry 525 low" start="+0x2068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT525H" description="GFXMMU LUT entry 525 high" start="+0x206C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT526L" description="GFXMMU LUT entry 526 low" start="+0x2070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT526H" description="GFXMMU LUT entry 526 high" start="+0x2074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT527L" description="GFXMMU LUT entry 527 low" start="+0x2078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT527H" description="GFXMMU LUT entry 527 high" start="+0x207C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT528L" description="GFXMMU LUT entry 528 low" start="+0x2080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT528H" description="GFXMMU LUT entry 528 high" start="+0x2084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT529L" description="GFXMMU LUT entry 529 low" start="+0x2088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT529H" description="GFXMMU LUT entry 529 high" start="+0x208C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT530L" description="GFXMMU LUT entry 530 low" start="+0x2090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT530H" description="GFXMMU LUT entry 530 high" start="+0x2094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT531L" description="GFXMMU LUT entry 531 low" start="+0x2098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT531H" description="GFXMMU LUT entry 531 high" start="+0x209C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT532L" description="GFXMMU LUT entry 532 low" start="+0x20A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT532H" description="GFXMMU LUT entry 532 high" start="+0x20A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT533L" description="GFXMMU LUT entry 533 low" start="+0x20A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT533H" description="GFXMMU LUT entry 533 high" start="+0x20AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT534L" description="GFXMMU LUT entry 534 low" start="+0x20B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT534H" description="GFXMMU LUT entry 534 high" start="+0x20B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT535L" description="GFXMMU LUT entry 535 low" start="+0x20B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT535H" description="GFXMMU LUT entry 535 high" start="+0x20BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT536L" description="GFXMMU LUT entry 536 low" start="+0x20C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT536H" description="GFXMMU LUT entry 536 high" start="+0x20C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT537L" description="GFXMMU LUT entry 537 low" start="+0x20C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT537H" description="GFXMMU LUT entry 537 high" start="+0x20CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT538L" description="GFXMMU LUT entry 538 low" start="+0x20D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT538H" description="GFXMMU LUT entry 538 high" start="+0x20D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT539L" description="GFXMMU LUT entry 539 low" start="+0x20D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT539H" description="GFXMMU LUT entry 539 high" start="+0x20DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT540L" description="GFXMMU LUT entry 540 low" start="+0x20E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT540H" description="GFXMMU LUT entry 540 high" start="+0x20E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT541L" description="GFXMMU LUT entry 541 low" start="+0x20E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT541H" description="GFXMMU LUT entry 541 high" start="+0x20EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT542L" description="GFXMMU LUT entry 542 low" start="+0x20F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT542H" description="GFXMMU LUT entry 542 high" start="+0x20F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT543L" description="GFXMMU LUT entry 543 low" start="+0x20F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT543H" description="GFXMMU LUT entry 543 high" start="+0x20FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT544L" description="GFXMMU LUT entry 544 low" start="+0x2100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT544H" description="GFXMMU LUT entry 544 high" start="+0x2104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT545L" description="GFXMMU LUT entry 545 low" start="+0x2108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT545H" description="GFXMMU LUT entry 545 high" start="+0x210C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT546L" description="GFXMMU LUT entry 546 low" start="+0x2110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT546H" description="GFXMMU LUT entry 546 high" start="+0x2114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT547L" description="GFXMMU LUT entry 547 low" start="+0x2118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT547H" description="GFXMMU LUT entry 547 high" start="+0x211C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT548L" description="GFXMMU LUT entry 548 low" start="+0x2120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT548H" description="GFXMMU LUT entry 548 high" start="+0x2124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT549L" description="GFXMMU LUT entry 549 low" start="+0x2128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT549H" description="GFXMMU LUT entry 549 high" start="+0x212C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT550L" description="GFXMMU LUT entry 550 low" start="+0x2130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT550H" description="GFXMMU LUT entry 550 high" start="+0x2134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT551L" description="GFXMMU LUT entry 551 low" start="+0x2138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT551H" description="GFXMMU LUT entry 551 high" start="+0x213C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT552L" description="GFXMMU LUT entry 552 low" start="+0x2140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT552H" description="GFXMMU LUT entry 552 high" start="+0x2144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT553L" description="GFXMMU LUT entry 553 low" start="+0x2148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT553H" description="GFXMMU LUT entry 553 high" start="+0x214C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT554L" description="GFXMMU LUT entry 554 low" start="+0x2150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT554H" description="GFXMMU LUT entry 554 high" start="+0x2154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT555L" description="GFXMMU LUT entry 555 low" start="+0x2158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT555H" description="GFXMMU LUT entry 555 high" start="+0x215C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT556L" description="GFXMMU LUT entry 556 low" start="+0x2160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT556H" description="GFXMMU LUT entry 556 high" start="+0x2164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT557L" description="GFXMMU LUT entry 557 low" start="+0x2168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT557H" description="GFXMMU LUT entry 557 high" start="+0x216C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT558L" description="GFXMMU LUT entry 558 low" start="+0x2170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT558H" description="GFXMMU LUT entry 558 high" start="+0x2174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT559L" description="GFXMMU LUT entry 559 low" start="+0x2178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT559H" description="GFXMMU LUT entry 559 high" start="+0x217C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT560L" description="GFXMMU LUT entry 560 low" start="+0x2180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT560H" description="GFXMMU LUT entry 560 high" start="+0x2184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT561L" description="GFXMMU LUT entry 561 low" start="+0x2188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT561H" description="GFXMMU LUT entry 561 high" start="+0x218C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT562L" description="GFXMMU LUT entry 562 low" start="+0x2190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT562H" description="GFXMMU LUT entry 562 high" start="+0x2194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT563L" description="GFXMMU LUT entry 563 low" start="+0x2198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT563H" description="GFXMMU LUT entry 563 high" start="+0x219C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT564L" description="GFXMMU LUT entry 564 low" start="+0x21A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT564H" description="GFXMMU LUT entry 564 high" start="+0x21A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT565L" description="GFXMMU LUT entry 565 low" start="+0x21A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT565H" description="GFXMMU LUT entry 565 high" start="+0x21AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT566L" description="GFXMMU LUT entry 566 low" start="+0x21B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT566H" description="GFXMMU LUT entry 566 high" start="+0x21B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT567L" description="GFXMMU LUT entry 567 low" start="+0x21B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT567H" description="GFXMMU LUT entry 567 high" start="+0x21BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT568L" description="GFXMMU LUT entry 568 low" start="+0x21C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT568H" description="GFXMMU LUT entry 568 high" start="+0x21C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT569L" description="GFXMMU LUT entry 569 low" start="+0x21C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT569H" description="GFXMMU LUT entry 569 high" start="+0x21CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT570L" description="GFXMMU LUT entry 570 low" start="+0x21D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT570H" description="GFXMMU LUT entry 570 high" start="+0x21D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT571L" description="GFXMMU LUT entry 571 low" start="+0x21D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT571H" description="GFXMMU LUT entry 571 high" start="+0x21DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT572L" description="GFXMMU LUT entry 572 low" start="+0x21E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT572H" description="GFXMMU LUT entry 572 high" start="+0x21E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT573L" description="GFXMMU LUT entry 573 low" start="+0x21E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT573H" description="GFXMMU LUT entry 573 high" start="+0x21EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT574L" description="GFXMMU LUT entry 574 low" start="+0x21F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT574H" description="GFXMMU LUT entry 574 high" start="+0x21F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT575L" description="GFXMMU LUT entry 575 low" start="+0x21F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT575H" description="GFXMMU LUT entry 575 high" start="+0x21FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT576L" description="GFXMMU LUT entry 576 low" start="+0x2200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT576H" description="GFXMMU LUT entry 576 high" start="+0x2204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT577L" description="GFXMMU LUT entry 577 low" start="+0x2208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT577H" description="GFXMMU LUT entry 577 high" start="+0x220C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT578L" description="GFXMMU LUT entry 578 low" start="+0x2210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT578H" description="GFXMMU LUT entry 578 high" start="+0x2214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT579L" description="GFXMMU LUT entry 579 low" start="+0x2218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT579H" description="GFXMMU LUT entry 579 high" start="+0x221C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT580L" description="GFXMMU LUT entry 580 low" start="+0x2220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT580H" description="GFXMMU LUT entry 580 high" start="+0x2224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT581L" description="GFXMMU LUT entry 581 low" start="+0x2228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT581H" description="GFXMMU LUT entry 581 high" start="+0x222C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT582L" description="GFXMMU LUT entry 582 low" start="+0x2230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT582H" description="GFXMMU LUT entry 582 high" start="+0x2234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT583L" description="GFXMMU LUT entry 583 low" start="+0x2238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT583H" description="GFXMMU LUT entry 583 high" start="+0x223C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT584L" description="GFXMMU LUT entry 584 low" start="+0x2240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT584H" description="GFXMMU LUT entry 584 high" start="+0x2244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT585L" description="GFXMMU LUT entry 585 low" start="+0x2248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT585H" description="GFXMMU LUT entry 585 high" start="+0x224C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT586L" description="GFXMMU LUT entry 586 low" start="+0x2250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT586H" description="GFXMMU LUT entry 586 high" start="+0x2254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT587L" description="GFXMMU LUT entry 587 low" start="+0x2258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT587H" description="GFXMMU LUT entry 587 high" start="+0x225C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT588L" description="GFXMMU LUT entry 588 low" start="+0x2260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT588H" description="GFXMMU LUT entry 588 high" start="+0x2264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT589L" description="GFXMMU LUT entry 589 low" start="+0x2268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT589H" description="GFXMMU LUT entry 589 high" start="+0x226C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT590L" description="GFXMMU LUT entry 590 low" start="+0x2270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT590H" description="GFXMMU LUT entry 590 high" start="+0x2274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT591L" description="GFXMMU LUT entry 591 low" start="+0x2278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT591H" description="GFXMMU LUT entry 591 high" start="+0x227C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT592L" description="GFXMMU LUT entry 592 low" start="+0x2280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT592H" description="GFXMMU LUT entry 592 high" start="+0x2284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT593L" description="GFXMMU LUT entry 593 low" start="+0x2288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT593H" description="GFXMMU LUT entry 593 high" start="+0x228C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT594L" description="GFXMMU LUT entry 594 low" start="+0x2290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT594H" description="GFXMMU LUT entry 594 high" start="+0x2294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT595L" description="GFXMMU LUT entry 595 low" start="+0x2298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT595H" description="GFXMMU LUT entry 595 high" start="+0x229C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT596L" description="GFXMMU LUT entry 596 low" start="+0x22A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT596H" description="GFXMMU LUT entry 596 high" start="+0x22A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT597L" description="GFXMMU LUT entry 597 low" start="+0x22A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT597H" description="GFXMMU LUT entry 597 high" start="+0x22AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT598L" description="GFXMMU LUT entry 598 low" start="+0x22B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT598H" description="GFXMMU LUT entry 598 high" start="+0x22B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT599L" description="GFXMMU LUT entry 599 low" start="+0x22B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT599H" description="GFXMMU LUT entry 599 high" start="+0x22BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT600L" description="GFXMMU LUT entry 600 low" start="+0x22C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT600H" description="GFXMMU LUT entry 600 high" start="+0x22C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT601L" description="GFXMMU LUT entry 601 low" start="+0x22C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT601H" description="GFXMMU LUT entry 601 high" start="+0x22CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT602L" description="GFXMMU LUT entry 602 low" start="+0x22D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT602H" description="GFXMMU LUT entry 602 high" start="+0x22D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT603L" description="GFXMMU LUT entry 603 low" start="+0x22D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT603H" description="GFXMMU LUT entry 603 high" start="+0x22DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT604L" description="GFXMMU LUT entry 604 low" start="+0x22E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT604H" description="GFXMMU LUT entry 604 high" start="+0x22E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT605L" description="GFXMMU LUT entry 605 low" start="+0x22E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT605H" description="GFXMMU LUT entry 605 high" start="+0x22EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT606L" description="GFXMMU LUT entry 606 low" start="+0x22F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT606H" description="GFXMMU LUT entry 606 high" start="+0x22F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT607L" description="GFXMMU LUT entry 607 low" start="+0x22F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT607H" description="GFXMMU LUT entry 607 high" start="+0x22FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT608L" description="GFXMMU LUT entry 608 low" start="+0x2300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT608H" description="GFXMMU LUT entry 608 high" start="+0x2304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT609L" description="GFXMMU LUT entry 609 low" start="+0x2308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT609H" description="GFXMMU LUT entry 609 high" start="+0x230C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT610L" description="GFXMMU LUT entry 610 low" start="+0x2310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT610H" description="GFXMMU LUT entry 610 high" start="+0x2314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT611L" description="GFXMMU LUT entry 611 low" start="+0x2318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT611H" description="GFXMMU LUT entry 611 high" start="+0x231C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT612L" description="GFXMMU LUT entry 612 low" start="+0x2320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT612H" description="GFXMMU LUT entry 612 high" start="+0x2324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT613L" description="GFXMMU LUT entry 613 low" start="+0x2328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT613H" description="GFXMMU LUT entry 613 high" start="+0x232C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT614L" description="GFXMMU LUT entry 614 low" start="+0x2330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT614H" description="GFXMMU LUT entry 614 high" start="+0x2334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT615L" description="GFXMMU LUT entry 615 low" start="+0x2338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT615H" description="GFXMMU LUT entry 615 high" start="+0x233C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT616L" description="GFXMMU LUT entry 616 low" start="+0x2340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT616H" description="GFXMMU LUT entry 616 high" start="+0x2344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT617L" description="GFXMMU LUT entry 617 low" start="+0x2348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT617H" description="GFXMMU LUT entry 617 high" start="+0x234C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT618L" description="GFXMMU LUT entry 618 low" start="+0x2350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT618H" description="GFXMMU LUT entry 618 high" start="+0x2354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT619L" description="GFXMMU LUT entry 619 low" start="+0x2358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT619H" description="GFXMMU LUT entry 619 high" start="+0x235C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT620L" description="GFXMMU LUT entry 620 low" start="+0x2360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT620H" description="GFXMMU LUT entry 620 high" start="+0x2364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT621L" description="GFXMMU LUT entry 621 low" start="+0x2368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT621H" description="GFXMMU LUT entry 621 high" start="+0x236C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT622L" description="GFXMMU LUT entry 622 low" start="+0x2370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT622H" description="GFXMMU LUT entry 622 high" start="+0x2374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT623L" description="GFXMMU LUT entry 623 low" start="+0x2378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT623H" description="GFXMMU LUT entry 623 high" start="+0x237C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT624L" description="GFXMMU LUT entry 624 low" start="+0x2380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT624H" description="GFXMMU LUT entry 624 high" start="+0x2384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT625L" description="GFXMMU LUT entry 625 low" start="+0x2388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT625H" description="GFXMMU LUT entry 625 high" start="+0x238C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT626L" description="GFXMMU LUT entry 626 low" start="+0x2390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT626H" description="GFXMMU LUT entry 626 high" start="+0x2394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT627L" description="GFXMMU LUT entry 627 low" start="+0x2398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT627H" description="GFXMMU LUT entry 627 high" start="+0x239C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT628L" description="GFXMMU LUT entry 628 low" start="+0x23A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT628H" description="GFXMMU LUT entry 628 high" start="+0x23A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT629L" description="GFXMMU LUT entry 629 low" start="+0x23A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT629H" description="GFXMMU LUT entry 629 high" start="+0x23AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT630L" description="GFXMMU LUT entry 630 low" start="+0x23B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT630H" description="GFXMMU LUT entry 630 high" start="+0x23B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT631L" description="GFXMMU LUT entry 631 low" start="+0x23B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT631H" description="GFXMMU LUT entry 631 high" start="+0x23BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT632L" description="GFXMMU LUT entry 632 low" start="+0x23C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT632H" description="GFXMMU LUT entry 632 high" start="+0x23C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT633L" description="GFXMMU LUT entry 633 low" start="+0x23C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT633H" description="GFXMMU LUT entry 633 high" start="+0x23CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT634L" description="GFXMMU LUT entry 634 low" start="+0x23D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT634H" description="GFXMMU LUT entry 634 high" start="+0x23D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT635L" description="GFXMMU LUT entry 635 low" start="+0x23D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT635H" description="GFXMMU LUT entry 635 high" start="+0x23DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT636L" description="GFXMMU LUT entry 636 low" start="+0x23E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT636H" description="GFXMMU LUT entry 636 high" start="+0x23E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT637L" description="GFXMMU LUT entry 637 low" start="+0x23E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT637H" description="GFXMMU LUT entry 637 high" start="+0x23EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT638L" description="GFXMMU LUT entry 638 low" start="+0x23F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT638H" description="GFXMMU LUT entry 638 high" start="+0x23F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT639L" description="GFXMMU LUT entry 639 low" start="+0x23F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT639H" description="GFXMMU LUT entry 639 high" start="+0x23FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT640L" description="GFXMMU LUT entry 640 low" start="+0x2400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT640H" description="GFXMMU LUT entry 640 high" start="+0x2404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT641L" description="GFXMMU LUT entry 641 low" start="+0x2408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT641H" description="GFXMMU LUT entry 641 high" start="+0x240C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT642L" description="GFXMMU LUT entry 642 low" start="+0x2410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT642H" description="GFXMMU LUT entry 642 high" start="+0x2414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT643L" description="GFXMMU LUT entry 643 low" start="+0x2418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT643H" description="GFXMMU LUT entry 643 high" start="+0x241C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT644L" description="GFXMMU LUT entry 644 low" start="+0x2420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT644H" description="GFXMMU LUT entry 644 high" start="+0x2424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT645L" description="GFXMMU LUT entry 645 low" start="+0x2428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT645H" description="GFXMMU LUT entry 645 high" start="+0x242C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT646L" description="GFXMMU LUT entry 646 low" start="+0x2430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT646H" description="GFXMMU LUT entry 646 high" start="+0x2434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT647L" description="GFXMMU LUT entry 647 low" start="+0x2438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT647H" description="GFXMMU LUT entry 647 high" start="+0x243C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT648L" description="GFXMMU LUT entry 648 low" start="+0x2440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT648H" description="GFXMMU LUT entry 648 high" start="+0x2444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT649L" description="GFXMMU LUT entry 649 low" start="+0x2448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT649H" description="GFXMMU LUT entry 649 high" start="+0x244C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT650L" description="GFXMMU LUT entry 650 low" start="+0x2450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT650H" description="GFXMMU LUT entry 650 high" start="+0x2454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT651L" description="GFXMMU LUT entry 651 low" start="+0x2458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT651H" description="GFXMMU LUT entry 651 high" start="+0x245C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT652L" description="GFXMMU LUT entry 652 low" start="+0x2460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT652H" description="GFXMMU LUT entry 652 high" start="+0x2464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT653L" description="GFXMMU LUT entry 653 low" start="+0x2468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT653H" description="GFXMMU LUT entry 653 high" start="+0x246C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT654L" description="GFXMMU LUT entry 654 low" start="+0x2470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT654H" description="GFXMMU LUT entry 654 high" start="+0x2474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT655L" description="GFXMMU LUT entry 655 low" start="+0x2478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT655H" description="GFXMMU LUT entry 655 high" start="+0x247C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT656L" description="GFXMMU LUT entry 656 low" start="+0x2480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT656H" description="GFXMMU LUT entry 656 high" start="+0x2484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT657L" description="GFXMMU LUT entry 657 low" start="+0x2488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT657H" description="GFXMMU LUT entry 657 high" start="+0x248C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT658L" description="GFXMMU LUT entry 658 low" start="+0x2490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT658H" description="GFXMMU LUT entry 658 high" start="+0x2494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT659L" description="GFXMMU LUT entry 659 low" start="+0x2498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT659H" description="GFXMMU LUT entry 659 high" start="+0x249C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT660L" description="GFXMMU LUT entry 660 low" start="+0x24A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT660H" description="GFXMMU LUT entry 660 high" start="+0x24A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT661L" description="GFXMMU LUT entry 661 low" start="+0x24A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT661H" description="GFXMMU LUT entry 661 high" start="+0x24AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT662L" description="GFXMMU LUT entry 662 low" start="+0x24B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT662H" description="GFXMMU LUT entry 662 high" start="+0x24B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT663L" description="GFXMMU LUT entry 663 low" start="+0x24B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT663H" description="GFXMMU LUT entry 663 high" start="+0x24BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT664L" description="GFXMMU LUT entry 664 low" start="+0x24C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT664H" description="GFXMMU LUT entry 664 high" start="+0x24C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT665L" description="GFXMMU LUT entry 665 low" start="+0x24C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT665H" description="GFXMMU LUT entry 665 high" start="+0x24CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT666L" description="GFXMMU LUT entry 666 low" start="+0x24D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT666H" description="GFXMMU LUT entry 666 high" start="+0x24D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT667L" description="GFXMMU LUT entry 667 low" start="+0x24D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT667H" description="GFXMMU LUT entry 667 high" start="+0x24DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT668L" description="GFXMMU LUT entry 668 low" start="+0x24E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT668H" description="GFXMMU LUT entry 668 high" start="+0x24E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT669L" description="GFXMMU LUT entry 669 low" start="+0x24E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT669H" description="GFXMMU LUT entry 669 high" start="+0x24EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT670L" description="GFXMMU LUT entry 670 low" start="+0x24F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT670H" description="GFXMMU LUT entry 670 high" start="+0x24F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT671L" description="GFXMMU LUT entry 671 low" start="+0x24F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT671H" description="GFXMMU LUT entry 671 high" start="+0x24FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT672L" description="GFXMMU LUT entry 672 low" start="+0x2500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT672H" description="GFXMMU LUT entry 672 high" start="+0x2504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT673L" description="GFXMMU LUT entry 673 low" start="+0x2508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT673H" description="GFXMMU LUT entry 673 high" start="+0x250C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT674L" description="GFXMMU LUT entry 674 low" start="+0x2510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT674H" description="GFXMMU LUT entry 674 high" start="+0x2514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT675L" description="GFXMMU LUT entry 675 low" start="+0x2518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT675H" description="GFXMMU LUT entry 675 high" start="+0x251C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT676L" description="GFXMMU LUT entry 676 low" start="+0x2520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT676H" description="GFXMMU LUT entry 676 high" start="+0x2524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT677L" description="GFXMMU LUT entry 677 low" start="+0x2528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT677H" description="GFXMMU LUT entry 677 high" start="+0x252C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT678L" description="GFXMMU LUT entry 678 low" start="+0x2530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT678H" description="GFXMMU LUT entry 678 high" start="+0x2534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT679L" description="GFXMMU LUT entry 679 low" start="+0x2538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT679H" description="GFXMMU LUT entry 679 high" start="+0x253C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT680L" description="GFXMMU LUT entry 680 low" start="+0x2540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT680H" description="GFXMMU LUT entry 680 high" start="+0x2544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT681L" description="GFXMMU LUT entry 681 low" start="+0x2548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT681H" description="GFXMMU LUT entry 681 high" start="+0x254C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT682L" description="GFXMMU LUT entry 682 low" start="+0x2550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT682H" description="GFXMMU LUT entry 682 high" start="+0x2554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT683L" description="GFXMMU LUT entry 683 low" start="+0x2558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT683H" description="GFXMMU LUT entry 683 high" start="+0x255C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT684L" description="GFXMMU LUT entry 684 low" start="+0x2560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT684H" description="GFXMMU LUT entry 684 high" start="+0x2564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT685L" description="GFXMMU LUT entry 685 low" start="+0x2568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT685H" description="GFXMMU LUT entry 685 high" start="+0x256C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT686L" description="GFXMMU LUT entry 686 low" start="+0x2570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT686H" description="GFXMMU LUT entry 686 high" start="+0x2574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT687L" description="GFXMMU LUT entry 687 low" start="+0x2578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT687H" description="GFXMMU LUT entry 687 high" start="+0x257C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT688L" description="GFXMMU LUT entry 688 low" start="+0x2580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT688H" description="GFXMMU LUT entry 688 high" start="+0x2584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT689L" description="GFXMMU LUT entry 689 low" start="+0x2588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT689H" description="GFXMMU LUT entry 689 high" start="+0x258C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT690L" description="GFXMMU LUT entry 690 low" start="+0x2590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT690H" description="GFXMMU LUT entry 690 high" start="+0x2594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT691L" description="GFXMMU LUT entry 691 low" start="+0x2598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT691H" description="GFXMMU LUT entry 691 high" start="+0x259C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT692L" description="GFXMMU LUT entry 692 low" start="+0x25A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT692H" description="GFXMMU LUT entry 692 high" start="+0x25A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT693L" description="GFXMMU LUT entry 693 low" start="+0x25A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT693H" description="GFXMMU LUT entry 693 high" start="+0x25AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT694L" description="GFXMMU LUT entry 694 low" start="+0x25B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT694H" description="GFXMMU LUT entry 694 high" start="+0x25B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT695L" description="GFXMMU LUT entry 695 low" start="+0x25B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT695H" description="GFXMMU LUT entry 695 high" start="+0x25BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT696L" description="GFXMMU LUT entry 696 low" start="+0x25C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT696H" description="GFXMMU LUT entry 696 high" start="+0x25C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT697L" description="GFXMMU LUT entry 697 low" start="+0x25C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT697H" description="GFXMMU LUT entry 697 high" start="+0x25CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT698L" description="GFXMMU LUT entry 698 low" start="+0x25D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT698H" description="GFXMMU LUT entry 698 high" start="+0x25D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT699L" description="GFXMMU LUT entry 699 low" start="+0x25D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT699H" description="GFXMMU LUT entry 699 high" start="+0x25DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT700L" description="GFXMMU LUT entry 700 low" start="+0x25E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT700H" description="GFXMMU LUT entry 700 high" start="+0x25E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT701L" description="GFXMMU LUT entry 701 low" start="+0x25E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT701H" description="GFXMMU LUT entry 701 high" start="+0x25EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT702L" description="GFXMMU LUT entry 702 low" start="+0x25F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT702H" description="GFXMMU LUT entry 702 high" start="+0x25F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT703L" description="GFXMMU LUT entry 703 low" start="+0x25F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT703H" description="GFXMMU LUT entry 703 high" start="+0x25FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT704L" description="GFXMMU LUT entry 704 low" start="+0x2600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT704H" description="GFXMMU LUT entry 704 high" start="+0x2604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT705L" description="GFXMMU LUT entry 705 low" start="+0x2608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT705H" description="GFXMMU LUT entry 705 high" start="+0x260C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT706L" description="GFXMMU LUT entry 706 low" start="+0x2610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT706H" description="GFXMMU LUT entry 706 high" start="+0x2614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT707L" description="GFXMMU LUT entry 707 low" start="+0x2618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT707H" description="GFXMMU LUT entry 707 high" start="+0x261C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT708L" description="GFXMMU LUT entry 708 low" start="+0x2620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT708H" description="GFXMMU LUT entry 708 high" start="+0x2624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT709L" description="GFXMMU LUT entry 709 low" start="+0x2628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT709H" description="GFXMMU LUT entry 709 high" start="+0x262C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT710L" description="GFXMMU LUT entry 710 low" start="+0x2630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT710H" description="GFXMMU LUT entry 710 high" start="+0x2634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT711L" description="GFXMMU LUT entry 711 low" start="+0x2638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT711H" description="GFXMMU LUT entry 711 high" start="+0x263C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT712L" description="GFXMMU LUT entry 712 low" start="+0x2640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT712H" description="GFXMMU LUT entry 712 high" start="+0x2644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT713L" description="GFXMMU LUT entry 713 low" start="+0x2648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT713H" description="GFXMMU LUT entry 713 high" start="+0x264C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT714L" description="GFXMMU LUT entry 714 low" start="+0x2650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT714H" description="GFXMMU LUT entry 714 high" start="+0x2654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT715L" description="GFXMMU LUT entry 715 low" start="+0x2658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT715H" description="GFXMMU LUT entry 715 high" start="+0x265C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT716L" description="GFXMMU LUT entry 716 low" start="+0x2660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT716H" description="GFXMMU LUT entry 716 high" start="+0x2664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT717L" description="GFXMMU LUT entry 717 low" start="+0x2668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT717H" description="GFXMMU LUT entry 717 high" start="+0x266C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT718L" description="GFXMMU LUT entry 718 low" start="+0x2670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT718H" description="GFXMMU LUT entry 718 high" start="+0x2674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT719L" description="GFXMMU LUT entry 719 low" start="+0x2678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT719H" description="GFXMMU LUT entry 719 high" start="+0x267C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT720L" description="GFXMMU LUT entry 720 low" start="+0x2680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT720H" description="GFXMMU LUT entry 720 high" start="+0x2684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT721L" description="GFXMMU LUT entry 721 low" start="+0x2688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT721H" description="GFXMMU LUT entry 721 high" start="+0x268C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT722L" description="GFXMMU LUT entry 722 low" start="+0x2690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT722H" description="GFXMMU LUT entry 722 high" start="+0x2694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT723L" description="GFXMMU LUT entry 723 low" start="+0x2698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT723H" description="GFXMMU LUT entry 723 high" start="+0x269C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT724L" description="GFXMMU LUT entry 724 low" start="+0x26A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT724H" description="GFXMMU LUT entry 724 high" start="+0x26A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT725L" description="GFXMMU LUT entry 725 low" start="+0x26A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT725H" description="GFXMMU LUT entry 725 high" start="+0x26AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT726L" description="GFXMMU LUT entry 726 low" start="+0x26B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT726H" description="GFXMMU LUT entry 726 high" start="+0x26B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT727L" description="GFXMMU LUT entry 727 low" start="+0x26B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT727H" description="GFXMMU LUT entry 727 high" start="+0x26BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT728L" description="GFXMMU LUT entry 728 low" start="+0x26C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT728H" description="GFXMMU LUT entry 728 high" start="+0x26C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT729L" description="GFXMMU LUT entry 729 low" start="+0x26C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT729H" description="GFXMMU LUT entry 729 high" start="+0x26CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT730L" description="GFXMMU LUT entry 730 low" start="+0x26D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT730H" description="GFXMMU LUT entry 730 high" start="+0x26D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT731L" description="GFXMMU LUT entry 731 low" start="+0x26D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT731H" description="GFXMMU LUT entry 731 high" start="+0x26DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT732L" description="GFXMMU LUT entry 732 low" start="+0x26E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT732H" description="GFXMMU LUT entry 732 high" start="+0x26E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT733L" description="GFXMMU LUT entry 733 low" start="+0x26E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT733H" description="GFXMMU LUT entry 733 high" start="+0x26EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT734L" description="GFXMMU LUT entry 734 low" start="+0x26F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT734H" description="GFXMMU LUT entry 734 high" start="+0x26F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT735L" description="GFXMMU LUT entry 735 low" start="+0x26F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT735H" description="GFXMMU LUT entry 735 high" start="+0x26FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT736L" description="GFXMMU LUT entry 736 low" start="+0x2700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT736H" description="GFXMMU LUT entry 736 high" start="+0x2704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT737L" description="GFXMMU LUT entry 737 low" start="+0x2708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT737H" description="GFXMMU LUT entry 737 high" start="+0x270C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT738L" description="GFXMMU LUT entry 738 low" start="+0x2710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT738H" description="GFXMMU LUT entry 738 high" start="+0x2714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT739L" description="GFXMMU LUT entry 739 low" start="+0x2718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT739H" description="GFXMMU LUT entry 739 high" start="+0x271C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT740L" description="GFXMMU LUT entry 740 low" start="+0x2720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT740H" description="GFXMMU LUT entry 740 high" start="+0x2724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT741L" description="GFXMMU LUT entry 741 low" start="+0x2728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT741H" description="GFXMMU LUT entry 741 high" start="+0x272C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT742L" description="GFXMMU LUT entry 742 low" start="+0x2730" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT742H" description="GFXMMU LUT entry 742 high" start="+0x2734" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT743L" description="GFXMMU LUT entry 743 low" start="+0x2738" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT743H" description="GFXMMU LUT entry 743 high" start="+0x273C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT744L" description="GFXMMU LUT entry 744 low" start="+0x2740" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT744H" description="GFXMMU LUT entry 744 high" start="+0x2744" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT745L" description="GFXMMU LUT entry 745 low" start="+0x2748" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT745H" description="GFXMMU LUT entry 745 high" start="+0x274C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT746L" description="GFXMMU LUT entry 746 low" start="+0x2750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT746H" description="GFXMMU LUT entry 746 high" start="+0x2754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT747L" description="GFXMMU LUT entry 747 low" start="+0x2758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT747H" description="GFXMMU LUT entry 747 high" start="+0x275C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT748L" description="GFXMMU LUT entry 748 low" start="+0x2760" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT748H" description="GFXMMU LUT entry 748 high" start="+0x2764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT749L" description="GFXMMU LUT entry 749 low" start="+0x2768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT749H" description="GFXMMU LUT entry 749 high" start="+0x276C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT750L" description="GFXMMU LUT entry 750 low" start="+0x2770" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT750H" description="GFXMMU LUT entry 750 high" start="+0x2774" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT751L" description="GFXMMU LUT entry 751 low" start="+0x2778" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT751H" description="GFXMMU LUT entry 751 high" start="+0x277C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT752L" description="GFXMMU LUT entry 752 low" start="+0x2780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT752H" description="GFXMMU LUT entry 752 high" start="+0x2784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT753L" description="GFXMMU LUT entry 753 low" start="+0x2788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT753H" description="GFXMMU LUT entry 753 high" start="+0x278C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT754L" description="GFXMMU LUT entry 754 low" start="+0x2790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT754H" description="GFXMMU LUT entry 754 high" start="+0x2794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT755L" description="GFXMMU LUT entry 755 low" start="+0x2798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT755H" description="GFXMMU LUT entry 755 high" start="+0x279C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT756L" description="GFXMMU LUT entry 756 low" start="+0x27A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT756H" description="GFXMMU LUT entry 756 high" start="+0x27A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT757L" description="GFXMMU LUT entry 757 low" start="+0x27A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT757H" description="GFXMMU LUT entry 757 high" start="+0x27AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT758L" description="GFXMMU LUT entry 758 low" start="+0x27B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT758H" description="GFXMMU LUT entry 758 high" start="+0x27B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT759L" description="GFXMMU LUT entry 759 low" start="+0x27B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT759H" description="GFXMMU LUT entry 759 high" start="+0x27BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT760L" description="GFXMMU LUT entry 760 low" start="+0x27C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT760H" description="GFXMMU LUT entry 760 high" start="+0x27C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT761L" description="GFXMMU LUT entry 761 low" start="+0x27C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT761H" description="GFXMMU LUT entry 761 high" start="+0x27CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT762L" description="GFXMMU LUT entry 762 low" start="+0x27D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT762H" description="GFXMMU LUT entry 762 high" start="+0x27D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT763L" description="GFXMMU LUT entry 763 low" start="+0x27D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT763H" description="GFXMMU LUT entry 763 high" start="+0x27DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT764L" description="GFXMMU LUT entry 764 low" start="+0x27E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT764H" description="GFXMMU LUT entry 764 high" start="+0x27E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT765L" description="GFXMMU LUT entry 765 low" start="+0x27E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT765H" description="GFXMMU LUT entry 765 high" start="+0x27EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT766L" description="GFXMMU LUT entry 766 low" start="+0x27F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT766H" description="GFXMMU LUT entry 766 high" start="+0x27F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT767L" description="GFXMMU LUT entry 767 low" start="+0x27F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT767H" description="GFXMMU LUT entry 767 high" start="+0x27FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT768L" description="GFXMMU LUT entry 768 low" start="+0x2800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT768H" description="GFXMMU LUT entry 768 high" start="+0x2804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT769L" description="GFXMMU LUT entry 769 low" start="+0x2808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT769H" description="GFXMMU LUT entry 769 high" start="+0x280C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT770L" description="GFXMMU LUT entry 770 low" start="+0x2810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT770H" description="GFXMMU LUT entry 770 high" start="+0x2814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT771L" description="GFXMMU LUT entry 771 low" start="+0x2818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT771H" description="GFXMMU LUT entry 771 high" start="+0x281C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT772L" description="GFXMMU LUT entry 772 low" start="+0x2820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT772H" description="GFXMMU LUT entry 772 high" start="+0x2824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT773L" description="GFXMMU LUT entry 773 low" start="+0x2828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT773H" description="GFXMMU LUT entry 773 high" start="+0x282C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT774L" description="GFXMMU LUT entry 774 low" start="+0x2830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT774H" description="GFXMMU LUT entry 774 high" start="+0x2834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT775L" description="GFXMMU LUT entry 775 low" start="+0x2838" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT775H" description="GFXMMU LUT entry 775 high" start="+0x283C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT776L" description="GFXMMU LUT entry 776 low" start="+0x2840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT776H" description="GFXMMU LUT entry 776 high" start="+0x2844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT777L" description="GFXMMU LUT entry 777 low" start="+0x2848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT777H" description="GFXMMU LUT entry 777 high" start="+0x284C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT778L" description="GFXMMU LUT entry 778 low" start="+0x2850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT778H" description="GFXMMU LUT entry 778 high" start="+0x2854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT779L" description="GFXMMU LUT entry 779 low" start="+0x2858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT779H" description="GFXMMU LUT entry 779 high" start="+0x285C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT780L" description="GFXMMU LUT entry 780 low" start="+0x2860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT780H" description="GFXMMU LUT entry 780 high" start="+0x2864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT781L" description="GFXMMU LUT entry 781 low" start="+0x2868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT781H" description="GFXMMU LUT entry 781 high" start="+0x286C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT782L" description="GFXMMU LUT entry 782 low" start="+0x2870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT782H" description="GFXMMU LUT entry 782 high" start="+0x2874" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT783L" description="GFXMMU LUT entry 783 low" start="+0x2878" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT783H" description="GFXMMU LUT entry 783 high" start="+0x287C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT784L" description="GFXMMU LUT entry 784 low" start="+0x2880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT784H" description="GFXMMU LUT entry 784 high" start="+0x2884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT785L" description="GFXMMU LUT entry 785 low" start="+0x2888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT785H" description="GFXMMU LUT entry 785 high" start="+0x288C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT786L" description="GFXMMU LUT entry 786 low" start="+0x2890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT786H" description="GFXMMU LUT entry 786 high" start="+0x2894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT787L" description="GFXMMU LUT entry 787 low" start="+0x2898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT787H" description="GFXMMU LUT entry 787 high" start="+0x289C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT788L" description="GFXMMU LUT entry 788 low" start="+0x28A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT788H" description="GFXMMU LUT entry 788 high" start="+0x28A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT789L" description="GFXMMU LUT entry 789 low" start="+0x28A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT789H" description="GFXMMU LUT entry 789 high" start="+0x28AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT790L" description="GFXMMU LUT entry 790 low" start="+0x28B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT790H" description="GFXMMU LUT entry 790 high" start="+0x28B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT791L" description="GFXMMU LUT entry 791 low" start="+0x28B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT791H" description="GFXMMU LUT entry 791 high" start="+0x28BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT792L" description="GFXMMU LUT entry 792 low" start="+0x28C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT792H" description="GFXMMU LUT entry 792 high" start="+0x28C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT793L" description="GFXMMU LUT entry 793 low" start="+0x28C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT793H" description="GFXMMU LUT entry 793 high" start="+0x28CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT794L" description="GFXMMU LUT entry 794 low" start="+0x28D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT794H" description="GFXMMU LUT entry 794 high" start="+0x28D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT795L" description="GFXMMU LUT entry 795 low" start="+0x28D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT795H" description="GFXMMU LUT entry 795 high" start="+0x28DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT796L" description="GFXMMU LUT entry 796 low" start="+0x28E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT796H" description="GFXMMU LUT entry 796 high" start="+0x28E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT797L" description="GFXMMU LUT entry 797 low" start="+0x28E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT797H" description="GFXMMU LUT entry 797 high" start="+0x28EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT798L" description="GFXMMU LUT entry 798 low" start="+0x28F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT798H" description="GFXMMU LUT entry 798 high" start="+0x28F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT799L" description="GFXMMU LUT entry 799 low" start="+0x28F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT799H" description="GFXMMU LUT entry 799 high" start="+0x28FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT800L" description="GFXMMU LUT entry 800 low" start="+0x2900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT800H" description="GFXMMU LUT entry 800 high" start="+0x2904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT801L" description="GFXMMU LUT entry 801 low" start="+0x2908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT801H" description="GFXMMU LUT entry 801 high" start="+0x290C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT802L" description="GFXMMU LUT entry 802 low" start="+0x2910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT802H" description="GFXMMU LUT entry 802 high" start="+0x2914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT803L" description="GFXMMU LUT entry 803 low" start="+0x2918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT803H" description="GFXMMU LUT entry 803 high" start="+0x291C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT804L" description="GFXMMU LUT entry 804 low" start="+0x2920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT804H" description="GFXMMU LUT entry 804 high" start="+0x2924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT805L" description="GFXMMU LUT entry 805 low" start="+0x2928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT805H" description="GFXMMU LUT entry 805 high" start="+0x292C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT806L" description="GFXMMU LUT entry 806 low" start="+0x2930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT806H" description="GFXMMU LUT entry 806 high" start="+0x2934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT807L" description="GFXMMU LUT entry 807 low" start="+0x2938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT807H" description="GFXMMU LUT entry 807 high" start="+0x293C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT808L" description="GFXMMU LUT entry 808 low" start="+0x2940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT808H" description="GFXMMU LUT entry 808 high" start="+0x2944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT809L" description="GFXMMU LUT entry 809 low" start="+0x2948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT809H" description="GFXMMU LUT entry 809 high" start="+0x294C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT810L" description="GFXMMU LUT entry 810 low" start="+0x2950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT810H" description="GFXMMU LUT entry 810 high" start="+0x2954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT811L" description="GFXMMU LUT entry 811 low" start="+0x2958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT811H" description="GFXMMU LUT entry 811 high" start="+0x295C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT812L" description="GFXMMU LUT entry 812 low" start="+0x2960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT812H" description="GFXMMU LUT entry 812 high" start="+0x2964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT813L" description="GFXMMU LUT entry 813 low" start="+0x2968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT813H" description="GFXMMU LUT entry 813 high" start="+0x296C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT814L" description="GFXMMU LUT entry 814 low" start="+0x2970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT814H" description="GFXMMU LUT entry 814 high" start="+0x2974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT815L" description="GFXMMU LUT entry 815 low" start="+0x2978" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT815H" description="GFXMMU LUT entry 815 high" start="+0x297C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT816L" description="GFXMMU LUT entry 816 low" start="+0x2980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT816H" description="GFXMMU LUT entry 816 high" start="+0x2984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT817L" description="GFXMMU LUT entry 817 low" start="+0x2988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT817H" description="GFXMMU LUT entry 817 high" start="+0x298C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT818L" description="GFXMMU LUT entry 818 low" start="+0x2990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT818H" description="GFXMMU LUT entry 818 high" start="+0x2994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT819L" description="GFXMMU LUT entry 819 low" start="+0x2998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT819H" description="GFXMMU LUT entry 819 high" start="+0x299C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT820L" description="GFXMMU LUT entry 820 low" start="+0x29A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT820H" description="GFXMMU LUT entry 820 high" start="+0x29A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT821L" description="GFXMMU LUT entry 821 low" start="+0x29A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT821H" description="GFXMMU LUT entry 821 high" start="+0x29AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT822L" description="GFXMMU LUT entry 822 low" start="+0x29B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT822H" description="GFXMMU LUT entry 822 high" start="+0x29B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT823L" description="GFXMMU LUT entry 823 low" start="+0x29B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT823H" description="GFXMMU LUT entry 823 high" start="+0x29BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT824L" description="GFXMMU LUT entry 824 low" start="+0x29C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT824H" description="GFXMMU LUT entry 824 high" start="+0x29C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT825L" description="GFXMMU LUT entry 825 low" start="+0x29C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT825H" description="GFXMMU LUT entry 825 high" start="+0x29CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT826L" description="GFXMMU LUT entry 826 low" start="+0x29D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT826H" description="GFXMMU LUT entry 826 high" start="+0x29D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT827L" description="GFXMMU LUT entry 827 low" start="+0x29D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT827H" description="GFXMMU LUT entry 827 high" start="+0x29DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT828L" description="GFXMMU LUT entry 828 low" start="+0x29E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT828H" description="GFXMMU LUT entry 828 high" start="+0x29E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT829L" description="GFXMMU LUT entry 829 low" start="+0x29E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT829H" description="GFXMMU LUT entry 829 high" start="+0x29EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT830L" description="GFXMMU LUT entry 830 low" start="+0x29F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT830H" description="GFXMMU LUT entry 830 high" start="+0x29F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT831L" description="GFXMMU LUT entry 831 low" start="+0x29F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT831H" description="GFXMMU LUT entry 831 high" start="+0x29FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT832L" description="GFXMMU LUT entry 832 low" start="+0x2A00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT832H" description="GFXMMU LUT entry 832 high" start="+0x2A04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT833L" description="GFXMMU LUT entry 833 low" start="+0x2A08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT833H" description="GFXMMU LUT entry 833 high" start="+0x2A0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT834L" description="GFXMMU LUT entry 834 low" start="+0x2A10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT834H" description="GFXMMU LUT entry 834 high" start="+0x2A14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT835L" description="GFXMMU LUT entry 835 low" start="+0x2A18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT835H" description="GFXMMU LUT entry 835 high" start="+0x2A1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT836L" description="GFXMMU LUT entry 836 low" start="+0x2A20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT836H" description="GFXMMU LUT entry 836 high" start="+0x2A24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT837L" description="GFXMMU LUT entry 837 low" start="+0x2A28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT837H" description="GFXMMU LUT entry 837 high" start="+0x2A2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT838L" description="GFXMMU LUT entry 838 low" start="+0x2A30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT838H" description="GFXMMU LUT entry 838 high" start="+0x2A34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT839L" description="GFXMMU LUT entry 839 low" start="+0x2A38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT839H" description="GFXMMU LUT entry 839 high" start="+0x2A3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT840L" description="GFXMMU LUT entry 840 low" start="+0x2A40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT840H" description="GFXMMU LUT entry 840 high" start="+0x2A44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT841L" description="GFXMMU LUT entry 841 low" start="+0x2A48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT841H" description="GFXMMU LUT entry 841 high" start="+0x2A4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT842L" description="GFXMMU LUT entry 842 low" start="+0x2A50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT842H" description="GFXMMU LUT entry 842 high" start="+0x2A54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT843L" description="GFXMMU LUT entry 843 low" start="+0x2A58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT843H" description="GFXMMU LUT entry 843 high" start="+0x2A5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT844L" description="GFXMMU LUT entry 844 low" start="+0x2A60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT844H" description="GFXMMU LUT entry 844 high" start="+0x2A64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT845L" description="GFXMMU LUT entry 845 low" start="+0x2A68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT845H" description="GFXMMU LUT entry 845 high" start="+0x2A6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT846L" description="GFXMMU LUT entry 846 low" start="+0x2A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT846H" description="GFXMMU LUT entry 846 high" start="+0x2A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT847L" description="GFXMMU LUT entry 847 low" start="+0x2A78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT847H" description="GFXMMU LUT entry 847 high" start="+0x2A7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT848L" description="GFXMMU LUT entry 848 low" start="+0x2A80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT848H" description="GFXMMU LUT entry 848 high" start="+0x2A84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT849L" description="GFXMMU LUT entry 849 low" start="+0x2A88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT849H" description="GFXMMU LUT entry 849 high" start="+0x2A8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT850L" description="GFXMMU LUT entry 850 low" start="+0x2A90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT850H" description="GFXMMU LUT entry 850 high" start="+0x2A94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT851L" description="GFXMMU LUT entry 851 low" start="+0x2A98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT851H" description="GFXMMU LUT entry 851 high" start="+0x2A9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT852L" description="GFXMMU LUT entry 852 low" start="+0x2AA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT852H" description="GFXMMU LUT entry 852 high" start="+0x2AA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT853L" description="GFXMMU LUT entry 853 low" start="+0x2AA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT853H" description="GFXMMU LUT entry 853 high" start="+0x2AAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT854L" description="GFXMMU LUT entry 854 low" start="+0x2AB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT854H" description="GFXMMU LUT entry 854 high" start="+0x2AB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT855L" description="GFXMMU LUT entry 855 low" start="+0x2AB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT855H" description="GFXMMU LUT entry 855 high" start="+0x2ABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT856L" description="GFXMMU LUT entry 856 low" start="+0x2AC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT856H" description="GFXMMU LUT entry 856 high" start="+0x2AC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT857L" description="GFXMMU LUT entry 857 low" start="+0x2AC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT857H" description="GFXMMU LUT entry 857 high" start="+0x2ACC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT858L" description="GFXMMU LUT entry 858 low" start="+0x2AD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT858H" description="GFXMMU LUT entry 858 high" start="+0x2AD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT859L" description="GFXMMU LUT entry 859 low" start="+0x2AD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT859H" description="GFXMMU LUT entry 859 high" start="+0x2ADC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT860L" description="GFXMMU LUT entry 860 low" start="+0x2AE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT860H" description="GFXMMU LUT entry 860 high" start="+0x2AE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT861L" description="GFXMMU LUT entry 861 low" start="+0x2AE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT861H" description="GFXMMU LUT entry 861 high" start="+0x2AEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT862L" description="GFXMMU LUT entry 862 low" start="+0x2AF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT862H" description="GFXMMU LUT entry 862 high" start="+0x2AF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT863L" description="GFXMMU LUT entry 863 low" start="+0x2AF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT863H" description="GFXMMU LUT entry 863 high" start="+0x2AFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT864L" description="GFXMMU LUT entry 864 low" start="+0x2B00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT864H" description="GFXMMU LUT entry 864 high" start="+0x2B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT865L" description="GFXMMU LUT entry 865 low" start="+0x2B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT865H" description="GFXMMU LUT entry 865 high" start="+0x2B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT866L" description="GFXMMU LUT entry 866 low" start="+0x2B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT866H" description="GFXMMU LUT entry 866 high" start="+0x2B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT867L" description="GFXMMU LUT entry 867 low" start="+0x2B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT867H" description="GFXMMU LUT entry 867 high" start="+0x2B1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT868L" description="GFXMMU LUT entry 868 low" start="+0x2B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT868H" description="GFXMMU LUT entry 868 high" start="+0x2B24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT869L" description="GFXMMU LUT entry 869 low" start="+0x2B28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT869H" description="GFXMMU LUT entry 869 high" start="+0x2B2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT870L" description="GFXMMU LUT entry 870 low" start="+0x2B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT870H" description="GFXMMU LUT entry 870 high" start="+0x2B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT871L" description="GFXMMU LUT entry 871 low" start="+0x2B38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT871H" description="GFXMMU LUT entry 871 high" start="+0x2B3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT872L" description="GFXMMU LUT entry 872 low" start="+0x2B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT872H" description="GFXMMU LUT entry 872 high" start="+0x2B44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT873L" description="GFXMMU LUT entry 873 low" start="+0x2B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT873H" description="GFXMMU LUT entry 873 high" start="+0x2B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT874L" description="GFXMMU LUT entry 874 low" start="+0x2B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT874H" description="GFXMMU LUT entry 874 high" start="+0x2B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT875L" description="GFXMMU LUT entry 875 low" start="+0x2B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT875H" description="GFXMMU LUT entry 875 high" start="+0x2B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT876L" description="GFXMMU LUT entry 876 low" start="+0x2B60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT876H" description="GFXMMU LUT entry 876 high" start="+0x2B64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT877L" description="GFXMMU LUT entry 877 low" start="+0x2B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT877H" description="GFXMMU LUT entry 877 high" start="+0x2B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT878L" description="GFXMMU LUT entry 878 low" start="+0x2B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT878H" description="GFXMMU LUT entry 878 high" start="+0x2B74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT879L" description="GFXMMU LUT entry 879 low" start="+0x2B78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT879H" description="GFXMMU LUT entry 879 high" start="+0x2B7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT880L" description="GFXMMU LUT entry 880 low" start="+0x2B80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT880H" description="GFXMMU LUT entry 880 high" start="+0x2B84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT881L" description="GFXMMU LUT entry 881 low" start="+0x2B88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT881H" description="GFXMMU LUT entry 881 high" start="+0x2B8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT882L" description="GFXMMU LUT entry 882 low" start="+0x2B90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT882H" description="GFXMMU LUT entry 882 high" start="+0x2B94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT883L" description="GFXMMU LUT entry 883 low" start="+0x2B98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT883H" description="GFXMMU LUT entry 883 high" start="+0x2B9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT884L" description="GFXMMU LUT entry 884 low" start="+0x2BA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT884H" description="GFXMMU LUT entry 884 high" start="+0x2BA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT885L" description="GFXMMU LUT entry 885 low" start="+0x2BA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT885H" description="GFXMMU LUT entry 885 high" start="+0x2BAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT886L" description="GFXMMU LUT entry 886 low" start="+0x2BB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT886H" description="GFXMMU LUT entry 886 high" start="+0x2BB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT887L" description="GFXMMU LUT entry 887 low" start="+0x2BB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT887H" description="GFXMMU LUT entry 887 high" start="+0x2BBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT888L" description="GFXMMU LUT entry 888 low" start="+0x2BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT888H" description="GFXMMU LUT entry 888 high" start="+0x2BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT889L" description="GFXMMU LUT entry 889 low" start="+0x2BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT889H" description="GFXMMU LUT entry 889 high" start="+0x2BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT890L" description="GFXMMU LUT entry 890 low" start="+0x2BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT890H" description="GFXMMU LUT entry 890 high" start="+0x2BD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT891L" description="GFXMMU LUT entry 891 low" start="+0x2BD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT891H" description="GFXMMU LUT entry 891 high" start="+0x2BDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT892L" description="GFXMMU LUT entry 892 low" start="+0x2BE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT892H" description="GFXMMU LUT entry 892 high" start="+0x2BE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT893L" description="GFXMMU LUT entry 893 low" start="+0x2BE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT893H" description="GFXMMU LUT entry 893 high" start="+0x2BEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT894L" description="GFXMMU LUT entry 894 low" start="+0x2BF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT894H" description="GFXMMU LUT entry 894 high" start="+0x2BF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT895L" description="GFXMMU LUT entry 895 low" start="+0x2BF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT895H" description="GFXMMU LUT entry 895 high" start="+0x2BFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT896L" description="GFXMMU LUT entry 896 low" start="+0x2C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT896H" description="GFXMMU LUT entry 896 high" start="+0x2C04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT897L" description="GFXMMU LUT entry 897 low" start="+0x2C08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT897H" description="GFXMMU LUT entry 897 high" start="+0x2C0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT898L" description="GFXMMU LUT entry 898 low" start="+0x2C10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT898H" description="GFXMMU LUT entry 898 high" start="+0x2C14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT899L" description="GFXMMU LUT entry 899 low" start="+0x2C18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT899H" description="GFXMMU LUT entry 899 high" start="+0x2C1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT900L" description="GFXMMU LUT entry 900 low" start="+0x2C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT900H" description="GFXMMU LUT entry 900 high" start="+0x2C24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT901L" description="GFXMMU LUT entry 901 low" start="+0x2C28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT901H" description="GFXMMU LUT entry 901 high" start="+0x2C2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT902L" description="GFXMMU LUT entry 902 low" start="+0x2C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT902H" description="GFXMMU LUT entry 902 high" start="+0x2C34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT903L" description="GFXMMU LUT entry 903 low" start="+0x2C38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT903H" description="GFXMMU LUT entry 903 high" start="+0x2C3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT904L" description="GFXMMU LUT entry 904 low" start="+0x2C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT904H" description="GFXMMU LUT entry 904 high" start="+0x2C44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT905L" description="GFXMMU LUT entry 905 low" start="+0x2C48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT905H" description="GFXMMU LUT entry 905 high" start="+0x2C4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT906L" description="GFXMMU LUT entry 906 low" start="+0x2C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT906H" description="GFXMMU LUT entry 906 high" start="+0x2C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT907L" description="GFXMMU LUT entry 907 low" start="+0x2C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT907H" description="GFXMMU LUT entry 907 high" start="+0x2C5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT908L" description="GFXMMU LUT entry 908 low" start="+0x2C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT908H" description="GFXMMU LUT entry 908 high" start="+0x2C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT909L" description="GFXMMU LUT entry 909 low" start="+0x2C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT909H" description="GFXMMU LUT entry 909 high" start="+0x2C6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT910L" description="GFXMMU LUT entry 910 low" start="+0x2C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT910H" description="GFXMMU LUT entry 910 high" start="+0x2C74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT911L" description="GFXMMU LUT entry 911 low" start="+0x2C78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT911H" description="GFXMMU LUT entry 911 high" start="+0x2C7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT912L" description="GFXMMU LUT entry 912 low" start="+0x2C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT912H" description="GFXMMU LUT entry 912 high" start="+0x2C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT913L" description="GFXMMU LUT entry 913 low" start="+0x2C88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT913H" description="GFXMMU LUT entry 913 high" start="+0x2C8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT914L" description="GFXMMU LUT entry 914 low" start="+0x2C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT914H" description="GFXMMU LUT entry 914 high" start="+0x2C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT915L" description="GFXMMU LUT entry 915 low" start="+0x2C98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT915H" description="GFXMMU LUT entry 915 high" start="+0x2C9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT916L" description="GFXMMU LUT entry 916 low" start="+0x2CA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT916H" description="GFXMMU LUT entry 916 high" start="+0x2CA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT917L" description="GFXMMU LUT entry 917 low" start="+0x2CA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT917H" description="GFXMMU LUT entry 917 high" start="+0x2CAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT918L" description="GFXMMU LUT entry 918 low" start="+0x2CB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT918H" description="GFXMMU LUT entry 918 high" start="+0x2CB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT919L" description="GFXMMU LUT entry 919 low" start="+0x2CB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT919H" description="GFXMMU LUT entry 919 high" start="+0x2CBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT920L" description="GFXMMU LUT entry 920 low" start="+0x2CC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT920H" description="GFXMMU LUT entry 920 high" start="+0x2CC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT921L" description="GFXMMU LUT entry 921 low" start="+0x2CC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT921H" description="GFXMMU LUT entry 921 high" start="+0x2CCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT922L" description="GFXMMU LUT entry 922 low" start="+0x2CD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT922H" description="GFXMMU LUT entry 922 high" start="+0x2CD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT923L" description="GFXMMU LUT entry 923 low" start="+0x2CD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT923H" description="GFXMMU LUT entry 923 high" start="+0x2CDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT924L" description="GFXMMU LUT entry 924 low" start="+0x2CE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT924H" description="GFXMMU LUT entry 924 high" start="+0x2CE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT925L" description="GFXMMU LUT entry 925 low" start="+0x2CE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT925H" description="GFXMMU LUT entry 925 high" start="+0x2CEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT926L" description="GFXMMU LUT entry 926 low" start="+0x2CF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT926H" description="GFXMMU LUT entry 926 high" start="+0x2CF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT927L" description="GFXMMU LUT entry 927 low" start="+0x2CF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT927H" description="GFXMMU LUT entry 927 high" start="+0x2CFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT928L" description="GFXMMU LUT entry 928 low" start="+0x2D00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT928H" description="GFXMMU LUT entry 928 high" start="+0x2D04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT929L" description="GFXMMU LUT entry 929 low" start="+0x2D08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT929H" description="GFXMMU LUT entry 929 high" start="+0x2D0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT930L" description="GFXMMU LUT entry 930 low" start="+0x2D10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT930H" description="GFXMMU LUT entry 930 high" start="+0x2D14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT931L" description="GFXMMU LUT entry 931 low" start="+0x2D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT931H" description="GFXMMU LUT entry 931 high" start="+0x2D1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT932L" description="GFXMMU LUT entry 932 low" start="+0x2D20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT932H" description="GFXMMU LUT entry 932 high" start="+0x2D24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT933L" description="GFXMMU LUT entry 933 low" start="+0x2D28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT933H" description="GFXMMU LUT entry 933 high" start="+0x2D2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT934L" description="GFXMMU LUT entry 934 low" start="+0x2D30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT934H" description="GFXMMU LUT entry 934 high" start="+0x2D34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT935L" description="GFXMMU LUT entry 935 low" start="+0x2D38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT935H" description="GFXMMU LUT entry 935 high" start="+0x2D3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT936L" description="GFXMMU LUT entry 936 low" start="+0x2D40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT936H" description="GFXMMU LUT entry 936 high" start="+0x2D44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT937L" description="GFXMMU LUT entry 937 low" start="+0x2D48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT937H" description="GFXMMU LUT entry 937 high" start="+0x2D4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT938L" description="GFXMMU LUT entry 938 low" start="+0x2D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT938H" description="GFXMMU LUT entry 938 high" start="+0x2D54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT939L" description="GFXMMU LUT entry 939 low" start="+0x2D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT939H" description="GFXMMU LUT entry 939 high" start="+0x2D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT940L" description="GFXMMU LUT entry 940 low" start="+0x2D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT940H" description="GFXMMU LUT entry 940 high" start="+0x2D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT941L" description="GFXMMU LUT entry 941 low" start="+0x2D68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT941H" description="GFXMMU LUT entry 941 high" start="+0x2D6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT942L" description="GFXMMU LUT entry 942 low" start="+0x2D70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT942H" description="GFXMMU LUT entry 942 high" start="+0x2D74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT943L" description="GFXMMU LUT entry 943 low" start="+0x2D78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT943H" description="GFXMMU LUT entry 943 high" start="+0x2D7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT944L" description="GFXMMU LUT entry 944 low" start="+0x2D80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT944H" description="GFXMMU LUT entry 944 high" start="+0x2D84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT945L" description="GFXMMU LUT entry 945 low" start="+0x2D88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT945H" description="GFXMMU LUT entry 945 high" start="+0x2D8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT946L" description="GFXMMU LUT entry 946 low" start="+0x2D90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT946H" description="GFXMMU LUT entry 946 high" start="+0x2D94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT947L" description="GFXMMU LUT entry 947 low" start="+0x2D98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT947H" description="GFXMMU LUT entry 947 high" start="+0x2D9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT948L" description="GFXMMU LUT entry 948 low" start="+0x2DA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT948H" description="GFXMMU LUT entry 948 high" start="+0x2DA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT949L" description="GFXMMU LUT entry 949 low" start="+0x2DA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT949H" description="GFXMMU LUT entry 949 high" start="+0x2DAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT950L" description="GFXMMU LUT entry 950 low" start="+0x2DB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT950H" description="GFXMMU LUT entry 950 high" start="+0x2DB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT951L" description="GFXMMU LUT entry 951 low" start="+0x2DB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT951H" description="GFXMMU LUT entry 951 high" start="+0x2DBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT952L" description="GFXMMU LUT entry 952 low" start="+0x2DC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT952H" description="GFXMMU LUT entry 952 high" start="+0x2DC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT953L" description="GFXMMU LUT entry 953 low" start="+0x2DC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT953H" description="GFXMMU LUT entry 953 high" start="+0x2DCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT954L" description="GFXMMU LUT entry 954 low" start="+0x2DD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT954H" description="GFXMMU LUT entry 954 high" start="+0x2DD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT955L" description="GFXMMU LUT entry 955 low" start="+0x2DD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT955H" description="GFXMMU LUT entry 955 high" start="+0x2DDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT956L" description="GFXMMU LUT entry 956 low" start="+0x2DE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT956H" description="GFXMMU LUT entry 956 high" start="+0x2DE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT957L" description="GFXMMU LUT entry 957 low" start="+0x2DE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT957H" description="GFXMMU LUT entry 957 high" start="+0x2DEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT958L" description="GFXMMU LUT entry 958 low" start="+0x2DF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT958H" description="GFXMMU LUT entry 958 high" start="+0x2DF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT959L" description="GFXMMU LUT entry 959 low" start="+0x2DF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT959H" description="GFXMMU LUT entry 959 high" start="+0x2DFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT960L" description="GFXMMU LUT entry 960 low" start="+0x2E00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT960H" description="GFXMMU LUT entry 960 high" start="+0x2E04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT961L" description="GFXMMU LUT entry 961 low" start="+0x2E08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT961H" description="GFXMMU LUT entry 961 high" start="+0x2E0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT962L" description="GFXMMU LUT entry 962 low" start="+0x2E10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT962H" description="GFXMMU LUT entry 962 high" start="+0x2E14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT963L" description="GFXMMU LUT entry 963 low" start="+0x2E18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT963H" description="GFXMMU LUT entry 963 high" start="+0x2E1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT964L" description="GFXMMU LUT entry 964 low" start="+0x2E20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT964H" description="GFXMMU LUT entry 964 high" start="+0x2E24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT965L" description="GFXMMU LUT entry 965 low" start="+0x2E28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT965H" description="GFXMMU LUT entry 965 high" start="+0x2E2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT966L" description="GFXMMU LUT entry 966 low" start="+0x2E30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT966H" description="GFXMMU LUT entry 966 high" start="+0x2E34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT967L" description="GFXMMU LUT entry 967 low" start="+0x2E38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT967H" description="GFXMMU LUT entry 967 high" start="+0x2E3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT968L" description="GFXMMU LUT entry 968 low" start="+0x2E40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT968H" description="GFXMMU LUT entry 968 high" start="+0x2E44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT969L" description="GFXMMU LUT entry 969 low" start="+0x2E48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT969H" description="GFXMMU LUT entry 969 high" start="+0x2E4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT970L" description="GFXMMU LUT entry 970 low" start="+0x2E50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT970H" description="GFXMMU LUT entry 970 high" start="+0x2E54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT971L" description="GFXMMU LUT entry 971 low" start="+0x2E58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT971H" description="GFXMMU LUT entry 971 high" start="+0x2E5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT972L" description="GFXMMU LUT entry 972 low" start="+0x2E60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT972H" description="GFXMMU LUT entry 972 high" start="+0x2E64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT973L" description="GFXMMU LUT entry 973 low" start="+0x2E68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT973H" description="GFXMMU LUT entry 973 high" start="+0x2E6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT974L" description="GFXMMU LUT entry 974 low" start="+0x2E70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT974H" description="GFXMMU LUT entry 974 high" start="+0x2E74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT975L" description="GFXMMU LUT entry 975 low" start="+0x2E78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT975H" description="GFXMMU LUT entry 975 high" start="+0x2E7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT976L" description="GFXMMU LUT entry 976 low" start="+0x2E80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT976H" description="GFXMMU LUT entry 976 high" start="+0x2E84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT977L" description="GFXMMU LUT entry 977 low" start="+0x2E88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT977H" description="GFXMMU LUT entry 977 high" start="+0x2E8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT978L" description="GFXMMU LUT entry 978 low" start="+0x2E90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT978H" description="GFXMMU LUT entry 978 high" start="+0x2E94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT979L" description="GFXMMU LUT entry 979 low" start="+0x2E98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT979H" description="GFXMMU LUT entry 979 high" start="+0x2E9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT980L" description="GFXMMU LUT entry 980 low" start="+0x2EA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT980H" description="GFXMMU LUT entry 980 high" start="+0x2EA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT981L" description="GFXMMU LUT entry 981 low" start="+0x2EA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT981H" description="GFXMMU LUT entry 981 high" start="+0x2EAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT982L" description="GFXMMU LUT entry 982 low" start="+0x2EB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT982H" description="GFXMMU LUT entry 982 high" start="+0x2EB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT983L" description="GFXMMU LUT entry 983 low" start="+0x2EB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT983H" description="GFXMMU LUT entry 983 high" start="+0x2EBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT984L" description="GFXMMU LUT entry 984 low" start="+0x2EC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT984H" description="GFXMMU LUT entry 984 high" start="+0x2EC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT985L" description="GFXMMU LUT entry 985 low" start="+0x2EC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT985H" description="GFXMMU LUT entry 985 high" start="+0x2ECC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT986L" description="GFXMMU LUT entry 986 low" start="+0x2ED0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT986H" description="GFXMMU LUT entry 986 high" start="+0x2ED4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT987L" description="GFXMMU LUT entry 987 low" start="+0x2ED8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT987H" description="GFXMMU LUT entry 987 high" start="+0x2EDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT988L" description="GFXMMU LUT entry 988 low" start="+0x2EE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT988H" description="GFXMMU LUT entry 988 high" start="+0x2EE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT989L" description="GFXMMU LUT entry 989 low" start="+0x2EE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT989H" description="GFXMMU LUT entry 989 high" start="+0x2EEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT990L" description="GFXMMU LUT entry 990 low" start="+0x2EF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT990H" description="GFXMMU LUT entry 990 high" start="+0x2EF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT991L" description="GFXMMU LUT entry 991 low" start="+0x2EF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT991H" description="GFXMMU LUT entry 991 high" start="+0x2EFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT992L" description="GFXMMU LUT entry 992 low" start="+0x2F00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT992H" description="GFXMMU LUT entry 992 high" start="+0x2F04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT993L" description="GFXMMU LUT entry 993 low" start="+0x2F08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT993H" description="GFXMMU LUT entry 993 high" start="+0x2F0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT994L" description="GFXMMU LUT entry 994 low" start="+0x2F10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT994H" description="GFXMMU LUT entry 994 high" start="+0x2F14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT995L" description="GFXMMU LUT entry 995 low" start="+0x2F18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT995H" description="GFXMMU LUT entry 995 high" start="+0x2F1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT996L" description="GFXMMU LUT entry 996 low" start="+0x2F20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT996H" description="GFXMMU LUT entry 996 high" start="+0x2F24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT997L" description="GFXMMU LUT entry 997 low" start="+0x2F28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT997H" description="GFXMMU LUT entry 997 high" start="+0x2F2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT998L" description="GFXMMU LUT entry 998 low" start="+0x2F30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT998H" description="GFXMMU LUT entry 998 high" start="+0x2F34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT999L" description="GFXMMU LUT entry 999 low" start="+0x2F38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT999H" description="GFXMMU LUT entry 999 high" start="+0x2F3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1000L" description="GFXMMU LUT entry 1000 low" start="+0x2F40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1000H" description="GFXMMU LUT entry 1000 high" start="+0x2F44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1001L" description="GFXMMU LUT entry 1001 low" start="+0x2F48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1001H" description="GFXMMU LUT entry 1001 high" start="+0x2F4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1002L" description="GFXMMU LUT entry 1002 low" start="+0x2F50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1002H" description="GFXMMU LUT entry 1002 high" start="+0x2F54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1003L" description="GFXMMU LUT entry 1003 low" start="+0x2F58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1003H" description="GFXMMU LUT entry 1003 high" start="+0x2F5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1004L" description="GFXMMU LUT entry 1004 low" start="+0x2F60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1004H" description="GFXMMU LUT entry 1004 high" start="+0x2F64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1005L" description="GFXMMU LUT entry 1005 low" start="+0x2F68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1005H" description="GFXMMU LUT entry 1005 high" start="+0x2F6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1006L" description="GFXMMU LUT entry 1006 low" start="+0x2F70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1006H" description="GFXMMU LUT entry 1006 high" start="+0x2F74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1007L" description="GFXMMU LUT entry 1007 low" start="+0x2F78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1007H" description="GFXMMU LUT entry 1007 high" start="+0x2F7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1008L" description="GFXMMU LUT entry 1008 low" start="+0x2F80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1008H" description="GFXMMU LUT entry 1008 high" start="+0x2F84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1009L" description="GFXMMU LUT entry 1009 low" start="+0x2F88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1009H" description="GFXMMU LUT entry 1009 high" start="+0x2F8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1010L" description="GFXMMU LUT entry 1010 low" start="+0x2F90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1010H" description="GFXMMU LUT entry 1010 high" start="+0x2F94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1011L" description="GFXMMU LUT entry 1011 low" start="+0x2F98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1011H" description="GFXMMU LUT entry 1011 high" start="+0x2F9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1012L" description="GFXMMU LUT entry 1012 low" start="+0x2FA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1012H" description="GFXMMU LUT entry 1012 high" start="+0x2FA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1013L" description="GFXMMU LUT entry 1013 low" start="+0x2FA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1013H" description="GFXMMU LUT entry 1013 high" start="+0x2FAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1014L" description="GFXMMU LUT entry 1014 low" start="+0x2FB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1014H" description="GFXMMU LUT entry 1014 high" start="+0x2FB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1015L" description="GFXMMU LUT entry 1015 low" start="+0x2FB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1015H" description="GFXMMU LUT entry 1015 high" start="+0x2FBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1016L" description="GFXMMU LUT entry 1016 low" start="+0x2FC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1016H" description="GFXMMU LUT entry 1016 high" start="+0x2FC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1017L" description="GFXMMU LUT entry 1017 low" start="+0x2FC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1017H" description="GFXMMU LUT entry 1017 high" start="+0x2FCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1018L" description="GFXMMU LUT entry 1018 low" start="+0x2FD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1018H" description="GFXMMU LUT entry 1018 high" start="+0x2FD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1019L" description="GFXMMU LUT entry 1019 low" start="+0x2FD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1019H" description="GFXMMU LUT entry 1019 high" start="+0x2FDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1020L" description="GFXMMU LUT entry 1020 low" start="+0x2FE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1020H" description="GFXMMU LUT entry 1020 high" start="+0x2FE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1021L" description="GFXMMU LUT entry 1021 low" start="+0x2FE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1021H" description="GFXMMU LUT entry 1021 high" start="+0x2FEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1022L" description="GFXMMU LUT entry 1022 low" start="+0x2FF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1022H" description="GFXMMU LUT entry 1022 high" start="+0x2FF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1023L" description="GFXMMU LUT entry 1023 low" start="+0x2FF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1023H" description="GFXMMU LUT entry 1023 high" start="+0x2FFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GFXMMU_S" description="Chrom-GRC" start="0x58030000">
+    <Register name="GFXMMU_CR" description="GFXMMU configuration register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="B0OIE" description="Buffer 0 overflow interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B1OIE" description="Buffer 1 overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B2OIE" description="Buffer 2 overflow interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="B3OIE" description="Buffer 3 overflow interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AMEIE" description="AXI master error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BS" description="Block size" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-byte blocks" start="0x0" />
+        <Enum name="B_0x1" description="12-byte blocks" start="0x1" />
+      </BitField>
+      <BitField name="ATE" description="Address translation enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address translation is disable" start="0x0" />
+        <Enum name="B_0x1" description="Address translation is enable" start="0x1" />
+      </BitField>
+      <BitField name="B0PE" description="Buffer 0 packing enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B0PM" description="Buffer 0 packing mode" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B1PE" description="Buffer 1 packing enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B1PM" description="Buffer 1 packing mode" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B2PE" description="Buffer 2 packing enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B2PM" description="Buffer 2 packing mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+      <BitField name="B3PE" description="Buffer 3 packing enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Packing is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Packing is enable" start="0x1" />
+      </BitField>
+      <BitField name="B3PM" description="Buffer 3 packing mode" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB is removed" start="0x0" />
+        <Enum name="B_0x1" description="LSB is removed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXMMU_SR" description="GFXMMU status register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="B0OF" description="Buffer 0 overflow flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="B1OF" description="Buffer 1 overflow flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="B2OF" description="Buffer 2 overflow flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="B3OF" description="Buffer 3 overflow flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="AMEF" description="AXI master error flag" start="4" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GFXMMU_FCR" description="GFXMMU flag clear register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CB0OF" description="Clear buffer 0 overflow flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CB1OF" description="Clear buffer 1 overflow flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CB2OF" description="Clear buffer 2 overflow flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CB3OF" description="Clear buffer 3 overflow flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CAMEF" description="Clear AXI master error flag" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_DVR" description="GFXMMU default value register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DV" description="Default value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_DAR" description="GFXMMU default alpha register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Default alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B0CR" description="GFXMMU buffer 0 configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B1CR" description="GFXMMU buffer 1 configuration register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B2CR" description="GFXMMU buffer 2 configuration register" start="+0x0028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_B3CR" description="GFXMMU buffer 3 configuration register" start="+0x002C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PBO" description="Physical buffer offset" start="4" size="19" access="Read/Write" />
+      <BitField name="PBBA" description="Physical buffer base address" start="23" size="9" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT0L" description="GFXMMU LUT entry 0 low" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT0H" description="GFXMMU LUT entry 0 high" start="+0x1004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1L" description="GFXMMU LUT entry 1 low" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1H" description="GFXMMU LUT entry 1 high" start="+0x100C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT2L" description="GFXMMU LUT entry 2 low" start="+0x1010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT2H" description="GFXMMU LUT entry 2 high" start="+0x1014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT3L" description="GFXMMU LUT entry 3 low" start="+0x1018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT3H" description="GFXMMU LUT entry 3 high" start="+0x101C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT4L" description="GFXMMU LUT entry 4 low" start="+0x1020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT4H" description="GFXMMU LUT entry 4 high" start="+0x1024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT5L" description="GFXMMU LUT entry 5 low" start="+0x1028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT5H" description="GFXMMU LUT entry 5 high" start="+0x102C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT6L" description="GFXMMU LUT entry 6 low" start="+0x1030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT6H" description="GFXMMU LUT entry 6 high" start="+0x1034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT7L" description="GFXMMU LUT entry 7 low" start="+0x1038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT7H" description="GFXMMU LUT entry 7 high" start="+0x103C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT8L" description="GFXMMU LUT entry 8 low" start="+0x1040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT8H" description="GFXMMU LUT entry 8 high" start="+0x1044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT9L" description="GFXMMU LUT entry 9 low" start="+0x1048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT9H" description="GFXMMU LUT entry 9 high" start="+0x104C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT10L" description="GFXMMU LUT entry 10 low" start="+0x1050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT10H" description="GFXMMU LUT entry 10 high" start="+0x1054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT11L" description="GFXMMU LUT entry 11 low" start="+0x1058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT11H" description="GFXMMU LUT entry 11 high" start="+0x105C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT12L" description="GFXMMU LUT entry 12 low" start="+0x1060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT12H" description="GFXMMU LUT entry 12 high" start="+0x1064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT13L" description="GFXMMU LUT entry 13 low" start="+0x1068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT13H" description="GFXMMU LUT entry 13 high" start="+0x106C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT14L" description="GFXMMU LUT entry 14 low" start="+0x1070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT14H" description="GFXMMU LUT entry 14 high" start="+0x1074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT15L" description="GFXMMU LUT entry 15 low" start="+0x1078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT15H" description="GFXMMU LUT entry 15 high" start="+0x107C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT16L" description="GFXMMU LUT entry 16 low" start="+0x1080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT16H" description="GFXMMU LUT entry 16 high" start="+0x1084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT17L" description="GFXMMU LUT entry 17 low" start="+0x1088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT17H" description="GFXMMU LUT entry 17 high" start="+0x108C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT18L" description="GFXMMU LUT entry 18 low" start="+0x1090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT18H" description="GFXMMU LUT entry 18 high" start="+0x1094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT19L" description="GFXMMU LUT entry 19 low" start="+0x1098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT19H" description="GFXMMU LUT entry 19 high" start="+0x109C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT20L" description="GFXMMU LUT entry 20 low" start="+0x10A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT20H" description="GFXMMU LUT entry 20 high" start="+0x10A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT21L" description="GFXMMU LUT entry 21 low" start="+0x10A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT21H" description="GFXMMU LUT entry 21 high" start="+0x10AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT22L" description="GFXMMU LUT entry 22 low" start="+0x10B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT22H" description="GFXMMU LUT entry 22 high" start="+0x10B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT23L" description="GFXMMU LUT entry 23 low" start="+0x10B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT23H" description="GFXMMU LUT entry 23 high" start="+0x10BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT24L" description="GFXMMU LUT entry 24 low" start="+0x10C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT24H" description="GFXMMU LUT entry 24 high" start="+0x10C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT25L" description="GFXMMU LUT entry 25 low" start="+0x10C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT25H" description="GFXMMU LUT entry 25 high" start="+0x10CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT26L" description="GFXMMU LUT entry 26 low" start="+0x10D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT26H" description="GFXMMU LUT entry 26 high" start="+0x10D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT27L" description="GFXMMU LUT entry 27 low" start="+0x10D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT27H" description="GFXMMU LUT entry 27 high" start="+0x10DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT28L" description="GFXMMU LUT entry 28 low" start="+0x10E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT28H" description="GFXMMU LUT entry 28 high" start="+0x10E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT29L" description="GFXMMU LUT entry 29 low" start="+0x10E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT29H" description="GFXMMU LUT entry 29 high" start="+0x10EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT30L" description="GFXMMU LUT entry 30 low" start="+0x10F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT30H" description="GFXMMU LUT entry 30 high" start="+0x10F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT31L" description="GFXMMU LUT entry 31 low" start="+0x10F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT31H" description="GFXMMU LUT entry 31 high" start="+0x10FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT32L" description="GFXMMU LUT entry 32 low" start="+0x1100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT32H" description="GFXMMU LUT entry 32 high" start="+0x1104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT33L" description="GFXMMU LUT entry 33 low" start="+0x1108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT33H" description="GFXMMU LUT entry 33 high" start="+0x110C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT34L" description="GFXMMU LUT entry 34 low" start="+0x1110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT34H" description="GFXMMU LUT entry 34 high" start="+0x1114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT35L" description="GFXMMU LUT entry 35 low" start="+0x1118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT35H" description="GFXMMU LUT entry 35 high" start="+0x111C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT36L" description="GFXMMU LUT entry 36 low" start="+0x1120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT36H" description="GFXMMU LUT entry 36 high" start="+0x1124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT37L" description="GFXMMU LUT entry 37 low" start="+0x1128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT37H" description="GFXMMU LUT entry 37 high" start="+0x112C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT38L" description="GFXMMU LUT entry 38 low" start="+0x1130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT38H" description="GFXMMU LUT entry 38 high" start="+0x1134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT39L" description="GFXMMU LUT entry 39 low" start="+0x1138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT39H" description="GFXMMU LUT entry 39 high" start="+0x113C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT40L" description="GFXMMU LUT entry 40 low" start="+0x1140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT40H" description="GFXMMU LUT entry 40 high" start="+0x1144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT41L" description="GFXMMU LUT entry 41 low" start="+0x1148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT41H" description="GFXMMU LUT entry 41 high" start="+0x114C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT42L" description="GFXMMU LUT entry 42 low" start="+0x1150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT42H" description="GFXMMU LUT entry 42 high" start="+0x1154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT43L" description="GFXMMU LUT entry 43 low" start="+0x1158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT43H" description="GFXMMU LUT entry 43 high" start="+0x115C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT44L" description="GFXMMU LUT entry 44 low" start="+0x1160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT44H" description="GFXMMU LUT entry 44 high" start="+0x1164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT45L" description="GFXMMU LUT entry 45 low" start="+0x1168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT45H" description="GFXMMU LUT entry 45 high" start="+0x116C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT46L" description="GFXMMU LUT entry 46 low" start="+0x1170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT46H" description="GFXMMU LUT entry 46 high" start="+0x1174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT47L" description="GFXMMU LUT entry 47 low" start="+0x1178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT47H" description="GFXMMU LUT entry 47 high" start="+0x117C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT48L" description="GFXMMU LUT entry 48 low" start="+0x1180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT48H" description="GFXMMU LUT entry 48 high" start="+0x1184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT49L" description="GFXMMU LUT entry 49 low" start="+0x1188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT49H" description="GFXMMU LUT entry 49 high" start="+0x118C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT50L" description="GFXMMU LUT entry 50 low" start="+0x1190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT50H" description="GFXMMU LUT entry 50 high" start="+0x1194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT51L" description="GFXMMU LUT entry 51 low" start="+0x1198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT51H" description="GFXMMU LUT entry 51 high" start="+0x119C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT52L" description="GFXMMU LUT entry 52 low" start="+0x11A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT52H" description="GFXMMU LUT entry 52 high" start="+0x11A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT53L" description="GFXMMU LUT entry 53 low" start="+0x11A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT53H" description="GFXMMU LUT entry 53 high" start="+0x11AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT54L" description="GFXMMU LUT entry 54 low" start="+0x11B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT54H" description="GFXMMU LUT entry 54 high" start="+0x11B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT55L" description="GFXMMU LUT entry 55 low" start="+0x11B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT55H" description="GFXMMU LUT entry 55 high" start="+0x11BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT56L" description="GFXMMU LUT entry 56 low" start="+0x11C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT56H" description="GFXMMU LUT entry 56 high" start="+0x11C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT57L" description="GFXMMU LUT entry 57 low" start="+0x11C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT57H" description="GFXMMU LUT entry 57 high" start="+0x11CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT58L" description="GFXMMU LUT entry 58 low" start="+0x11D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT58H" description="GFXMMU LUT entry 58 high" start="+0x11D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT59L" description="GFXMMU LUT entry 59 low" start="+0x11D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT59H" description="GFXMMU LUT entry 59 high" start="+0x11DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT60L" description="GFXMMU LUT entry 60 low" start="+0x11E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT60H" description="GFXMMU LUT entry 60 high" start="+0x11E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT61L" description="GFXMMU LUT entry 61 low" start="+0x11E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT61H" description="GFXMMU LUT entry 61 high" start="+0x11EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT62L" description="GFXMMU LUT entry 62 low" start="+0x11F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT62H" description="GFXMMU LUT entry 62 high" start="+0x11F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT63L" description="GFXMMU LUT entry 63 low" start="+0x11F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT63H" description="GFXMMU LUT entry 63 high" start="+0x11FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT64L" description="GFXMMU LUT entry 64 low" start="+0x1200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT64H" description="GFXMMU LUT entry 64 high" start="+0x1204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT65L" description="GFXMMU LUT entry 65 low" start="+0x1208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT65H" description="GFXMMU LUT entry 65 high" start="+0x120C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT66L" description="GFXMMU LUT entry 66 low" start="+0x1210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT66H" description="GFXMMU LUT entry 66 high" start="+0x1214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT67L" description="GFXMMU LUT entry 67 low" start="+0x1218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT67H" description="GFXMMU LUT entry 67 high" start="+0x121C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT68L" description="GFXMMU LUT entry 68 low" start="+0x1220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT68H" description="GFXMMU LUT entry 68 high" start="+0x1224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT69L" description="GFXMMU LUT entry 69 low" start="+0x1228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT69H" description="GFXMMU LUT entry 69 high" start="+0x122C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT70L" description="GFXMMU LUT entry 70 low" start="+0x1230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT70H" description="GFXMMU LUT entry 70 high" start="+0x1234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT71L" description="GFXMMU LUT entry 71 low" start="+0x1238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT71H" description="GFXMMU LUT entry 71 high" start="+0x123C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT72L" description="GFXMMU LUT entry 72 low" start="+0x1240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT72H" description="GFXMMU LUT entry 72 high" start="+0x1244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT73L" description="GFXMMU LUT entry 73 low" start="+0x1248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT73H" description="GFXMMU LUT entry 73 high" start="+0x124C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT74L" description="GFXMMU LUT entry 74 low" start="+0x1250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT74H" description="GFXMMU LUT entry 74 high" start="+0x1254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT75L" description="GFXMMU LUT entry 75 low" start="+0x1258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT75H" description="GFXMMU LUT entry 75 high" start="+0x125C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT76L" description="GFXMMU LUT entry 76 low" start="+0x1260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT76H" description="GFXMMU LUT entry 76 high" start="+0x1264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT77L" description="GFXMMU LUT entry 77 low" start="+0x1268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT77H" description="GFXMMU LUT entry 77 high" start="+0x126C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT78L" description="GFXMMU LUT entry 78 low" start="+0x1270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT78H" description="GFXMMU LUT entry 78 high" start="+0x1274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT79L" description="GFXMMU LUT entry 79 low" start="+0x1278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT79H" description="GFXMMU LUT entry 79 high" start="+0x127C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT80L" description="GFXMMU LUT entry 80 low" start="+0x1280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT80H" description="GFXMMU LUT entry 80 high" start="+0x1284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT81L" description="GFXMMU LUT entry 81 low" start="+0x1288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT81H" description="GFXMMU LUT entry 81 high" start="+0x128C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT82L" description="GFXMMU LUT entry 82 low" start="+0x1290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT82H" description="GFXMMU LUT entry 82 high" start="+0x1294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT83L" description="GFXMMU LUT entry 83 low" start="+0x1298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT83H" description="GFXMMU LUT entry 83 high" start="+0x129C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT84L" description="GFXMMU LUT entry 84 low" start="+0x12A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT84H" description="GFXMMU LUT entry 84 high" start="+0x12A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT85L" description="GFXMMU LUT entry 85 low" start="+0x12A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT85H" description="GFXMMU LUT entry 85 high" start="+0x12AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT86L" description="GFXMMU LUT entry 86 low" start="+0x12B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT86H" description="GFXMMU LUT entry 86 high" start="+0x12B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT87L" description="GFXMMU LUT entry 87 low" start="+0x12B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT87H" description="GFXMMU LUT entry 87 high" start="+0x12BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT88L" description="GFXMMU LUT entry 88 low" start="+0x12C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT88H" description="GFXMMU LUT entry 88 high" start="+0x12C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT89L" description="GFXMMU LUT entry 89 low" start="+0x12C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT89H" description="GFXMMU LUT entry 89 high" start="+0x12CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT90L" description="GFXMMU LUT entry 90 low" start="+0x12D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT90H" description="GFXMMU LUT entry 90 high" start="+0x12D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT91L" description="GFXMMU LUT entry 91 low" start="+0x12D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT91H" description="GFXMMU LUT entry 91 high" start="+0x12DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT92L" description="GFXMMU LUT entry 92 low" start="+0x12E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT92H" description="GFXMMU LUT entry 92 high" start="+0x12E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT93L" description="GFXMMU LUT entry 93 low" start="+0x12E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT93H" description="GFXMMU LUT entry 93 high" start="+0x12EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT94L" description="GFXMMU LUT entry 94 low" start="+0x12F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT94H" description="GFXMMU LUT entry 94 high" start="+0x12F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT95L" description="GFXMMU LUT entry 95 low" start="+0x12F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT95H" description="GFXMMU LUT entry 95 high" start="+0x12FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT96L" description="GFXMMU LUT entry 96 low" start="+0x1300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT96H" description="GFXMMU LUT entry 96 high" start="+0x1304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT97L" description="GFXMMU LUT entry 97 low" start="+0x1308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT97H" description="GFXMMU LUT entry 97 high" start="+0x130C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT98L" description="GFXMMU LUT entry 98 low" start="+0x1310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT98H" description="GFXMMU LUT entry 98 high" start="+0x1314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT99L" description="GFXMMU LUT entry 99 low" start="+0x1318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT99H" description="GFXMMU LUT entry 99 high" start="+0x131C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT100L" description="GFXMMU LUT entry 100 low" start="+0x1320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT100H" description="GFXMMU LUT entry 100 high" start="+0x1324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT101L" description="GFXMMU LUT entry 101 low" start="+0x1328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT101H" description="GFXMMU LUT entry 101 high" start="+0x132C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT102L" description="GFXMMU LUT entry 102 low" start="+0x1330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT102H" description="GFXMMU LUT entry 102 high" start="+0x1334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT103L" description="GFXMMU LUT entry 103 low" start="+0x1338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT103H" description="GFXMMU LUT entry 103 high" start="+0x133C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT104L" description="GFXMMU LUT entry 104 low" start="+0x1340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT104H" description="GFXMMU LUT entry 104 high" start="+0x1344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT105L" description="GFXMMU LUT entry 105 low" start="+0x1348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT105H" description="GFXMMU LUT entry 105 high" start="+0x134C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT106L" description="GFXMMU LUT entry 106 low" start="+0x1350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT106H" description="GFXMMU LUT entry 106 high" start="+0x1354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT107L" description="GFXMMU LUT entry 107 low" start="+0x1358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT107H" description="GFXMMU LUT entry 107 high" start="+0x135C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT108L" description="GFXMMU LUT entry 108 low" start="+0x1360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT108H" description="GFXMMU LUT entry 108 high" start="+0x1364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT109L" description="GFXMMU LUT entry 109 low" start="+0x1368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT109H" description="GFXMMU LUT entry 109 high" start="+0x136C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT110L" description="GFXMMU LUT entry 110 low" start="+0x1370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT110H" description="GFXMMU LUT entry 110 high" start="+0x1374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT111L" description="GFXMMU LUT entry 111 low" start="+0x1378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT111H" description="GFXMMU LUT entry 111 high" start="+0x137C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT112L" description="GFXMMU LUT entry 112 low" start="+0x1380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT112H" description="GFXMMU LUT entry 112 high" start="+0x1384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT113L" description="GFXMMU LUT entry 113 low" start="+0x1388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT113H" description="GFXMMU LUT entry 113 high" start="+0x138C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT114L" description="GFXMMU LUT entry 114 low" start="+0x1390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT114H" description="GFXMMU LUT entry 114 high" start="+0x1394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT115L" description="GFXMMU LUT entry 115 low" start="+0x1398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT115H" description="GFXMMU LUT entry 115 high" start="+0x139C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT116L" description="GFXMMU LUT entry 116 low" start="+0x13A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT116H" description="GFXMMU LUT entry 116 high" start="+0x13A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT117L" description="GFXMMU LUT entry 117 low" start="+0x13A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT117H" description="GFXMMU LUT entry 117 high" start="+0x13AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT118L" description="GFXMMU LUT entry 118 low" start="+0x13B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT118H" description="GFXMMU LUT entry 118 high" start="+0x13B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT119L" description="GFXMMU LUT entry 119 low" start="+0x13B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT119H" description="GFXMMU LUT entry 119 high" start="+0x13BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT120L" description="GFXMMU LUT entry 120 low" start="+0x13C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT120H" description="GFXMMU LUT entry 120 high" start="+0x13C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT121L" description="GFXMMU LUT entry 121 low" start="+0x13C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT121H" description="GFXMMU LUT entry 121 high" start="+0x13CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT122L" description="GFXMMU LUT entry 122 low" start="+0x13D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT122H" description="GFXMMU LUT entry 122 high" start="+0x13D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT123L" description="GFXMMU LUT entry 123 low" start="+0x13D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT123H" description="GFXMMU LUT entry 123 high" start="+0x13DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT124L" description="GFXMMU LUT entry 124 low" start="+0x13E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT124H" description="GFXMMU LUT entry 124 high" start="+0x13E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT125L" description="GFXMMU LUT entry 125 low" start="+0x13E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT125H" description="GFXMMU LUT entry 125 high" start="+0x13EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT126L" description="GFXMMU LUT entry 126 low" start="+0x13F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT126H" description="GFXMMU LUT entry 126 high" start="+0x13F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT127L" description="GFXMMU LUT entry 127 low" start="+0x13F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT127H" description="GFXMMU LUT entry 127 high" start="+0x13FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT128L" description="GFXMMU LUT entry 128 low" start="+0x1400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT128H" description="GFXMMU LUT entry 128 high" start="+0x1404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT129L" description="GFXMMU LUT entry 129 low" start="+0x1408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT129H" description="GFXMMU LUT entry 129 high" start="+0x140C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT130L" description="GFXMMU LUT entry 130 low" start="+0x1410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT130H" description="GFXMMU LUT entry 130 high" start="+0x1414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT131L" description="GFXMMU LUT entry 131 low" start="+0x1418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT131H" description="GFXMMU LUT entry 131 high" start="+0x141C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT132L" description="GFXMMU LUT entry 132 low" start="+0x1420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT132H" description="GFXMMU LUT entry 132 high" start="+0x1424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT133L" description="GFXMMU LUT entry 133 low" start="+0x1428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT133H" description="GFXMMU LUT entry 133 high" start="+0x142C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT134L" description="GFXMMU LUT entry 134 low" start="+0x1430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT134H" description="GFXMMU LUT entry 134 high" start="+0x1434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT135L" description="GFXMMU LUT entry 135 low" start="+0x1438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT135H" description="GFXMMU LUT entry 135 high" start="+0x143C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT136L" description="GFXMMU LUT entry 136 low" start="+0x1440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT136H" description="GFXMMU LUT entry 136 high" start="+0x1444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT137L" description="GFXMMU LUT entry 137 low" start="+0x1448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT137H" description="GFXMMU LUT entry 137 high" start="+0x144C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT138L" description="GFXMMU LUT entry 138 low" start="+0x1450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT138H" description="GFXMMU LUT entry 138 high" start="+0x1454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT139L" description="GFXMMU LUT entry 139 low" start="+0x1458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT139H" description="GFXMMU LUT entry 139 high" start="+0x145C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT140L" description="GFXMMU LUT entry 140 low" start="+0x1460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT140H" description="GFXMMU LUT entry 140 high" start="+0x1464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT141L" description="GFXMMU LUT entry 141 low" start="+0x1468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT141H" description="GFXMMU LUT entry 141 high" start="+0x146C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT142L" description="GFXMMU LUT entry 142 low" start="+0x1470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT142H" description="GFXMMU LUT entry 142 high" start="+0x1474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT143L" description="GFXMMU LUT entry 143 low" start="+0x1478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT143H" description="GFXMMU LUT entry 143 high" start="+0x147C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT144L" description="GFXMMU LUT entry 144 low" start="+0x1480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT144H" description="GFXMMU LUT entry 144 high" start="+0x1484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT145L" description="GFXMMU LUT entry 145 low" start="+0x1488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT145H" description="GFXMMU LUT entry 145 high" start="+0x148C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT146L" description="GFXMMU LUT entry 146 low" start="+0x1490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT146H" description="GFXMMU LUT entry 146 high" start="+0x1494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT147L" description="GFXMMU LUT entry 147 low" start="+0x1498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT147H" description="GFXMMU LUT entry 147 high" start="+0x149C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT148L" description="GFXMMU LUT entry 148 low" start="+0x14A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT148H" description="GFXMMU LUT entry 148 high" start="+0x14A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT149L" description="GFXMMU LUT entry 149 low" start="+0x14A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT149H" description="GFXMMU LUT entry 149 high" start="+0x14AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT150L" description="GFXMMU LUT entry 150 low" start="+0x14B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT150H" description="GFXMMU LUT entry 150 high" start="+0x14B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT151L" description="GFXMMU LUT entry 151 low" start="+0x14B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT151H" description="GFXMMU LUT entry 151 high" start="+0x14BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT152L" description="GFXMMU LUT entry 152 low" start="+0x14C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT152H" description="GFXMMU LUT entry 152 high" start="+0x14C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT153L" description="GFXMMU LUT entry 153 low" start="+0x14C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT153H" description="GFXMMU LUT entry 153 high" start="+0x14CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT154L" description="GFXMMU LUT entry 154 low" start="+0x14D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT154H" description="GFXMMU LUT entry 154 high" start="+0x14D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT155L" description="GFXMMU LUT entry 155 low" start="+0x14D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT155H" description="GFXMMU LUT entry 155 high" start="+0x14DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT156L" description="GFXMMU LUT entry 156 low" start="+0x14E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT156H" description="GFXMMU LUT entry 156 high" start="+0x14E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT157L" description="GFXMMU LUT entry 157 low" start="+0x14E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT157H" description="GFXMMU LUT entry 157 high" start="+0x14EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT158L" description="GFXMMU LUT entry 158 low" start="+0x14F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT158H" description="GFXMMU LUT entry 158 high" start="+0x14F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT159L" description="GFXMMU LUT entry 159 low" start="+0x14F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT159H" description="GFXMMU LUT entry 159 high" start="+0x14FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT160L" description="GFXMMU LUT entry 160 low" start="+0x1500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT160H" description="GFXMMU LUT entry 160 high" start="+0x1504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT161L" description="GFXMMU LUT entry 161 low" start="+0x1508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT161H" description="GFXMMU LUT entry 161 high" start="+0x150C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT162L" description="GFXMMU LUT entry 162 low" start="+0x1510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT162H" description="GFXMMU LUT entry 162 high" start="+0x1514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT163L" description="GFXMMU LUT entry 163 low" start="+0x1518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT163H" description="GFXMMU LUT entry 163 high" start="+0x151C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT164L" description="GFXMMU LUT entry 164 low" start="+0x1520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT164H" description="GFXMMU LUT entry 164 high" start="+0x1524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT165L" description="GFXMMU LUT entry 165 low" start="+0x1528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT165H" description="GFXMMU LUT entry 165 high" start="+0x152C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT166L" description="GFXMMU LUT entry 166 low" start="+0x1530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT166H" description="GFXMMU LUT entry 166 high" start="+0x1534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT167L" description="GFXMMU LUT entry 167 low" start="+0x1538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT167H" description="GFXMMU LUT entry 167 high" start="+0x153C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT168L" description="GFXMMU LUT entry 168 low" start="+0x1540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT168H" description="GFXMMU LUT entry 168 high" start="+0x1544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT169L" description="GFXMMU LUT entry 169 low" start="+0x1548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT169H" description="GFXMMU LUT entry 169 high" start="+0x154C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT170L" description="GFXMMU LUT entry 170 low" start="+0x1550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT170H" description="GFXMMU LUT entry 170 high" start="+0x1554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT171L" description="GFXMMU LUT entry 171 low" start="+0x1558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT171H" description="GFXMMU LUT entry 171 high" start="+0x155C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT172L" description="GFXMMU LUT entry 172 low" start="+0x1560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT172H" description="GFXMMU LUT entry 172 high" start="+0x1564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT173L" description="GFXMMU LUT entry 173 low" start="+0x1568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT173H" description="GFXMMU LUT entry 173 high" start="+0x156C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT174L" description="GFXMMU LUT entry 174 low" start="+0x1570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT174H" description="GFXMMU LUT entry 174 high" start="+0x1574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT175L" description="GFXMMU LUT entry 175 low" start="+0x1578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT175H" description="GFXMMU LUT entry 175 high" start="+0x157C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT176L" description="GFXMMU LUT entry 176 low" start="+0x1580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT176H" description="GFXMMU LUT entry 176 high" start="+0x1584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT177L" description="GFXMMU LUT entry 177 low" start="+0x1588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT177H" description="GFXMMU LUT entry 177 high" start="+0x158C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT178L" description="GFXMMU LUT entry 178 low" start="+0x1590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT178H" description="GFXMMU LUT entry 178 high" start="+0x1594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT179L" description="GFXMMU LUT entry 179 low" start="+0x1598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT179H" description="GFXMMU LUT entry 179 high" start="+0x159C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT180L" description="GFXMMU LUT entry 180 low" start="+0x15A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT180H" description="GFXMMU LUT entry 180 high" start="+0x15A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT181L" description="GFXMMU LUT entry 181 low" start="+0x15A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT181H" description="GFXMMU LUT entry 181 high" start="+0x15AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT182L" description="GFXMMU LUT entry 182 low" start="+0x15B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT182H" description="GFXMMU LUT entry 182 high" start="+0x15B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT183L" description="GFXMMU LUT entry 183 low" start="+0x15B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT183H" description="GFXMMU LUT entry 183 high" start="+0x15BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT184L" description="GFXMMU LUT entry 184 low" start="+0x15C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT184H" description="GFXMMU LUT entry 184 high" start="+0x15C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT185L" description="GFXMMU LUT entry 185 low" start="+0x15C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT185H" description="GFXMMU LUT entry 185 high" start="+0x15CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT186L" description="GFXMMU LUT entry 186 low" start="+0x15D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT186H" description="GFXMMU LUT entry 186 high" start="+0x15D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT187L" description="GFXMMU LUT entry 187 low" start="+0x15D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT187H" description="GFXMMU LUT entry 187 high" start="+0x15DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT188L" description="GFXMMU LUT entry 188 low" start="+0x15E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT188H" description="GFXMMU LUT entry 188 high" start="+0x15E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT189L" description="GFXMMU LUT entry 189 low" start="+0x15E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT189H" description="GFXMMU LUT entry 189 high" start="+0x15EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT190L" description="GFXMMU LUT entry 190 low" start="+0x15F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT190H" description="GFXMMU LUT entry 190 high" start="+0x15F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT191L" description="GFXMMU LUT entry 191 low" start="+0x15F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT191H" description="GFXMMU LUT entry 191 high" start="+0x15FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT192L" description="GFXMMU LUT entry 192 low" start="+0x1600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT192H" description="GFXMMU LUT entry 192 high" start="+0x1604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT193L" description="GFXMMU LUT entry 193 low" start="+0x1608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT193H" description="GFXMMU LUT entry 193 high" start="+0x160C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT194L" description="GFXMMU LUT entry 194 low" start="+0x1610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT194H" description="GFXMMU LUT entry 194 high" start="+0x1614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT195L" description="GFXMMU LUT entry 195 low" start="+0x1618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT195H" description="GFXMMU LUT entry 195 high" start="+0x161C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT196L" description="GFXMMU LUT entry 196 low" start="+0x1620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT196H" description="GFXMMU LUT entry 196 high" start="+0x1624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT197L" description="GFXMMU LUT entry 197 low" start="+0x1628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT197H" description="GFXMMU LUT entry 197 high" start="+0x162C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT198L" description="GFXMMU LUT entry 198 low" start="+0x1630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT198H" description="GFXMMU LUT entry 198 high" start="+0x1634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT199L" description="GFXMMU LUT entry 199 low" start="+0x1638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT199H" description="GFXMMU LUT entry 199 high" start="+0x163C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT200L" description="GFXMMU LUT entry 200 low" start="+0x1640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT200H" description="GFXMMU LUT entry 200 high" start="+0x1644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT201L" description="GFXMMU LUT entry 201 low" start="+0x1648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT201H" description="GFXMMU LUT entry 201 high" start="+0x164C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT202L" description="GFXMMU LUT entry 202 low" start="+0x1650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT202H" description="GFXMMU LUT entry 202 high" start="+0x1654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT203L" description="GFXMMU LUT entry 203 low" start="+0x1658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT203H" description="GFXMMU LUT entry 203 high" start="+0x165C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT204L" description="GFXMMU LUT entry 204 low" start="+0x1660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT204H" description="GFXMMU LUT entry 204 high" start="+0x1664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT205L" description="GFXMMU LUT entry 205 low" start="+0x1668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT205H" description="GFXMMU LUT entry 205 high" start="+0x166C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT206L" description="GFXMMU LUT entry 206 low" start="+0x1670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT206H" description="GFXMMU LUT entry 206 high" start="+0x1674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT207L" description="GFXMMU LUT entry 207 low" start="+0x1678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT207H" description="GFXMMU LUT entry 207 high" start="+0x167C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT208L" description="GFXMMU LUT entry 208 low" start="+0x1680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT208H" description="GFXMMU LUT entry 208 high" start="+0x1684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT209L" description="GFXMMU LUT entry 209 low" start="+0x1688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT209H" description="GFXMMU LUT entry 209 high" start="+0x168C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT210L" description="GFXMMU LUT entry 210 low" start="+0x1690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT210H" description="GFXMMU LUT entry 210 high" start="+0x1694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT211L" description="GFXMMU LUT entry 211 low" start="+0x1698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT211H" description="GFXMMU LUT entry 211 high" start="+0x169C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT212L" description="GFXMMU LUT entry 212 low" start="+0x16A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT212H" description="GFXMMU LUT entry 212 high" start="+0x16A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT213L" description="GFXMMU LUT entry 213 low" start="+0x16A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT213H" description="GFXMMU LUT entry 213 high" start="+0x16AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT214L" description="GFXMMU LUT entry 214 low" start="+0x16B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT214H" description="GFXMMU LUT entry 214 high" start="+0x16B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT215L" description="GFXMMU LUT entry 215 low" start="+0x16B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT215H" description="GFXMMU LUT entry 215 high" start="+0x16BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT216L" description="GFXMMU LUT entry 216 low" start="+0x16C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT216H" description="GFXMMU LUT entry 216 high" start="+0x16C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT217L" description="GFXMMU LUT entry 217 low" start="+0x16C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT217H" description="GFXMMU LUT entry 217 high" start="+0x16CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT218L" description="GFXMMU LUT entry 218 low" start="+0x16D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT218H" description="GFXMMU LUT entry 218 high" start="+0x16D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT219L" description="GFXMMU LUT entry 219 low" start="+0x16D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT219H" description="GFXMMU LUT entry 219 high" start="+0x16DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT220L" description="GFXMMU LUT entry 220 low" start="+0x16E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT220H" description="GFXMMU LUT entry 220 high" start="+0x16E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT221L" description="GFXMMU LUT entry 221 low" start="+0x16E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT221H" description="GFXMMU LUT entry 221 high" start="+0x16EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT222L" description="GFXMMU LUT entry 222 low" start="+0x16F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT222H" description="GFXMMU LUT entry 222 high" start="+0x16F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT223L" description="GFXMMU LUT entry 223 low" start="+0x16F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT223H" description="GFXMMU LUT entry 223 high" start="+0x16FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT224L" description="GFXMMU LUT entry 224 low" start="+0x1700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT224H" description="GFXMMU LUT entry 224 high" start="+0x1704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT225L" description="GFXMMU LUT entry 225 low" start="+0x1708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT225H" description="GFXMMU LUT entry 225 high" start="+0x170C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT226L" description="GFXMMU LUT entry 226 low" start="+0x1710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT226H" description="GFXMMU LUT entry 226 high" start="+0x1714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT227L" description="GFXMMU LUT entry 227 low" start="+0x1718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT227H" description="GFXMMU LUT entry 227 high" start="+0x171C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT228L" description="GFXMMU LUT entry 228 low" start="+0x1720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT228H" description="GFXMMU LUT entry 228 high" start="+0x1724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT229L" description="GFXMMU LUT entry 229 low" start="+0x1728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT229H" description="GFXMMU LUT entry 229 high" start="+0x172C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT230L" description="GFXMMU LUT entry 230 low" start="+0x1730" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT230H" description="GFXMMU LUT entry 230 high" start="+0x1734" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT231L" description="GFXMMU LUT entry 231 low" start="+0x1738" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT231H" description="GFXMMU LUT entry 231 high" start="+0x173C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT232L" description="GFXMMU LUT entry 232 low" start="+0x1740" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT232H" description="GFXMMU LUT entry 232 high" start="+0x1744" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT233L" description="GFXMMU LUT entry 233 low" start="+0x1748" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT233H" description="GFXMMU LUT entry 233 high" start="+0x174C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT234L" description="GFXMMU LUT entry 234 low" start="+0x1750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT234H" description="GFXMMU LUT entry 234 high" start="+0x1754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT235L" description="GFXMMU LUT entry 235 low" start="+0x1758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT235H" description="GFXMMU LUT entry 235 high" start="+0x175C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT236L" description="GFXMMU LUT entry 236 low" start="+0x1760" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT236H" description="GFXMMU LUT entry 236 high" start="+0x1764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT237L" description="GFXMMU LUT entry 237 low" start="+0x1768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT237H" description="GFXMMU LUT entry 237 high" start="+0x176C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT238L" description="GFXMMU LUT entry 238 low" start="+0x1770" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT238H" description="GFXMMU LUT entry 238 high" start="+0x1774" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT239L" description="GFXMMU LUT entry 239 low" start="+0x1778" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT239H" description="GFXMMU LUT entry 239 high" start="+0x177C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT240L" description="GFXMMU LUT entry 240 low" start="+0x1780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT240H" description="GFXMMU LUT entry 240 high" start="+0x1784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT241L" description="GFXMMU LUT entry 241 low" start="+0x1788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT241H" description="GFXMMU LUT entry 241 high" start="+0x178C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT242L" description="GFXMMU LUT entry 242 low" start="+0x1790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT242H" description="GFXMMU LUT entry 242 high" start="+0x1794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT243L" description="GFXMMU LUT entry 243 low" start="+0x1798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT243H" description="GFXMMU LUT entry 243 high" start="+0x179C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT244L" description="GFXMMU LUT entry 244 low" start="+0x17A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT244H" description="GFXMMU LUT entry 244 high" start="+0x17A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT245L" description="GFXMMU LUT entry 245 low" start="+0x17A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT245H" description="GFXMMU LUT entry 245 high" start="+0x17AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT246L" description="GFXMMU LUT entry 246 low" start="+0x17B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT246H" description="GFXMMU LUT entry 246 high" start="+0x17B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT247L" description="GFXMMU LUT entry 247 low" start="+0x17B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT247H" description="GFXMMU LUT entry 247 high" start="+0x17BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT248L" description="GFXMMU LUT entry 248 low" start="+0x17C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT248H" description="GFXMMU LUT entry 248 high" start="+0x17C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT249L" description="GFXMMU LUT entry 249 low" start="+0x17C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT249H" description="GFXMMU LUT entry 249 high" start="+0x17CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT250L" description="GFXMMU LUT entry 250 low" start="+0x17D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT250H" description="GFXMMU LUT entry 250 high" start="+0x17D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT251L" description="GFXMMU LUT entry 251 low" start="+0x17D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT251H" description="GFXMMU LUT entry 251 high" start="+0x17DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT252L" description="GFXMMU LUT entry 252 low" start="+0x17E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT252H" description="GFXMMU LUT entry 252 high" start="+0x17E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT253L" description="GFXMMU LUT entry 253 low" start="+0x17E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT253H" description="GFXMMU LUT entry 253 high" start="+0x17EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT254L" description="GFXMMU LUT entry 254 low" start="+0x17F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT254H" description="GFXMMU LUT entry 254 high" start="+0x17F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT255L" description="GFXMMU LUT entry 255 low" start="+0x17F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT255H" description="GFXMMU LUT entry 255 high" start="+0x17FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT256L" description="GFXMMU LUT entry 256 low" start="+0x1800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT256H" description="GFXMMU LUT entry 256 high" start="+0x1804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT257L" description="GFXMMU LUT entry 257 low" start="+0x1808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT257H" description="GFXMMU LUT entry 257 high" start="+0x180C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT258L" description="GFXMMU LUT entry 258 low" start="+0x1810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT258H" description="GFXMMU LUT entry 258 high" start="+0x1814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT259L" description="GFXMMU LUT entry 259 low" start="+0x1818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT259H" description="GFXMMU LUT entry 259 high" start="+0x181C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT260L" description="GFXMMU LUT entry 260 low" start="+0x1820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT260H" description="GFXMMU LUT entry 260 high" start="+0x1824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT261L" description="GFXMMU LUT entry 261 low" start="+0x1828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT261H" description="GFXMMU LUT entry 261 high" start="+0x182C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT262L" description="GFXMMU LUT entry 262 low" start="+0x1830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT262H" description="GFXMMU LUT entry 262 high" start="+0x1834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT263L" description="GFXMMU LUT entry 263 low" start="+0x1838" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT263H" description="GFXMMU LUT entry 263 high" start="+0x183C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT264L" description="GFXMMU LUT entry 264 low" start="+0x1840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT264H" description="GFXMMU LUT entry 264 high" start="+0x1844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT265L" description="GFXMMU LUT entry 265 low" start="+0x1848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT265H" description="GFXMMU LUT entry 265 high" start="+0x184C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT266L" description="GFXMMU LUT entry 266 low" start="+0x1850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT266H" description="GFXMMU LUT entry 266 high" start="+0x1854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT267L" description="GFXMMU LUT entry 267 low" start="+0x1858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT267H" description="GFXMMU LUT entry 267 high" start="+0x185C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT268L" description="GFXMMU LUT entry 268 low" start="+0x1860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT268H" description="GFXMMU LUT entry 268 high" start="+0x1864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT269L" description="GFXMMU LUT entry 269 low" start="+0x1868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT269H" description="GFXMMU LUT entry 269 high" start="+0x186C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT270L" description="GFXMMU LUT entry 270 low" start="+0x1870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT270H" description="GFXMMU LUT entry 270 high" start="+0x1874" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT271L" description="GFXMMU LUT entry 271 low" start="+0x1878" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT271H" description="GFXMMU LUT entry 271 high" start="+0x187C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT272L" description="GFXMMU LUT entry 272 low" start="+0x1880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT272H" description="GFXMMU LUT entry 272 high" start="+0x1884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT273L" description="GFXMMU LUT entry 273 low" start="+0x1888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT273H" description="GFXMMU LUT entry 273 high" start="+0x188C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT274L" description="GFXMMU LUT entry 274 low" start="+0x1890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT274H" description="GFXMMU LUT entry 274 high" start="+0x1894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT275L" description="GFXMMU LUT entry 275 low" start="+0x1898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT275H" description="GFXMMU LUT entry 275 high" start="+0x189C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT276L" description="GFXMMU LUT entry 276 low" start="+0x18A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT276H" description="GFXMMU LUT entry 276 high" start="+0x18A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT277L" description="GFXMMU LUT entry 277 low" start="+0x18A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT277H" description="GFXMMU LUT entry 277 high" start="+0x18AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT278L" description="GFXMMU LUT entry 278 low" start="+0x18B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT278H" description="GFXMMU LUT entry 278 high" start="+0x18B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT279L" description="GFXMMU LUT entry 279 low" start="+0x18B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT279H" description="GFXMMU LUT entry 279 high" start="+0x18BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT280L" description="GFXMMU LUT entry 280 low" start="+0x18C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT280H" description="GFXMMU LUT entry 280 high" start="+0x18C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT281L" description="GFXMMU LUT entry 281 low" start="+0x18C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT281H" description="GFXMMU LUT entry 281 high" start="+0x18CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT282L" description="GFXMMU LUT entry 282 low" start="+0x18D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT282H" description="GFXMMU LUT entry 282 high" start="+0x18D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT283L" description="GFXMMU LUT entry 283 low" start="+0x18D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT283H" description="GFXMMU LUT entry 283 high" start="+0x18DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT284L" description="GFXMMU LUT entry 284 low" start="+0x18E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT284H" description="GFXMMU LUT entry 284 high" start="+0x18E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT285L" description="GFXMMU LUT entry 285 low" start="+0x18E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT285H" description="GFXMMU LUT entry 285 high" start="+0x18EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT286L" description="GFXMMU LUT entry 286 low" start="+0x18F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT286H" description="GFXMMU LUT entry 286 high" start="+0x18F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT287L" description="GFXMMU LUT entry 287 low" start="+0x18F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT287H" description="GFXMMU LUT entry 287 high" start="+0x18FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT288L" description="GFXMMU LUT entry 288 low" start="+0x1900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT288H" description="GFXMMU LUT entry 288 high" start="+0x1904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT289L" description="GFXMMU LUT entry 289 low" start="+0x1908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT289H" description="GFXMMU LUT entry 289 high" start="+0x190C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT290L" description="GFXMMU LUT entry 290 low" start="+0x1910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT290H" description="GFXMMU LUT entry 290 high" start="+0x1914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT291L" description="GFXMMU LUT entry 291 low" start="+0x1918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT291H" description="GFXMMU LUT entry 291 high" start="+0x191C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT292L" description="GFXMMU LUT entry 292 low" start="+0x1920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT292H" description="GFXMMU LUT entry 292 high" start="+0x1924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT293L" description="GFXMMU LUT entry 293 low" start="+0x1928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT293H" description="GFXMMU LUT entry 293 high" start="+0x192C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT294L" description="GFXMMU LUT entry 294 low" start="+0x1930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT294H" description="GFXMMU LUT entry 294 high" start="+0x1934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT295L" description="GFXMMU LUT entry 295 low" start="+0x1938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT295H" description="GFXMMU LUT entry 295 high" start="+0x193C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT296L" description="GFXMMU LUT entry 296 low" start="+0x1940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT296H" description="GFXMMU LUT entry 296 high" start="+0x1944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT297L" description="GFXMMU LUT entry 297 low" start="+0x1948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT297H" description="GFXMMU LUT entry 297 high" start="+0x194C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT298L" description="GFXMMU LUT entry 298 low" start="+0x1950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT298H" description="GFXMMU LUT entry 298 high" start="+0x1954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT299L" description="GFXMMU LUT entry 299 low" start="+0x1958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT299H" description="GFXMMU LUT entry 299 high" start="+0x195C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT300L" description="GFXMMU LUT entry 300 low" start="+0x1960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT300H" description="GFXMMU LUT entry 300 high" start="+0x1964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT301L" description="GFXMMU LUT entry 301 low" start="+0x1968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT301H" description="GFXMMU LUT entry 301 high" start="+0x196C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT302L" description="GFXMMU LUT entry 302 low" start="+0x1970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT302H" description="GFXMMU LUT entry 302 high" start="+0x1974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT303L" description="GFXMMU LUT entry 303 low" start="+0x1978" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT303H" description="GFXMMU LUT entry 303 high" start="+0x197C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT304L" description="GFXMMU LUT entry 304 low" start="+0x1980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT304H" description="GFXMMU LUT entry 304 high" start="+0x1984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT305L" description="GFXMMU LUT entry 305 low" start="+0x1988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT305H" description="GFXMMU LUT entry 305 high" start="+0x198C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT306L" description="GFXMMU LUT entry 306 low" start="+0x1990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT306H" description="GFXMMU LUT entry 306 high" start="+0x1994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT307L" description="GFXMMU LUT entry 307 low" start="+0x1998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT307H" description="GFXMMU LUT entry 307 high" start="+0x199C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT308L" description="GFXMMU LUT entry 308 low" start="+0x19A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT308H" description="GFXMMU LUT entry 308 high" start="+0x19A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT309L" description="GFXMMU LUT entry 309 low" start="+0x19A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT309H" description="GFXMMU LUT entry 309 high" start="+0x19AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT310L" description="GFXMMU LUT entry 310 low" start="+0x19B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT310H" description="GFXMMU LUT entry 310 high" start="+0x19B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT311L" description="GFXMMU LUT entry 311 low" start="+0x19B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT311H" description="GFXMMU LUT entry 311 high" start="+0x19BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT312L" description="GFXMMU LUT entry 312 low" start="+0x19C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT312H" description="GFXMMU LUT entry 312 high" start="+0x19C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT313L" description="GFXMMU LUT entry 313 low" start="+0x19C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT313H" description="GFXMMU LUT entry 313 high" start="+0x19CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT314L" description="GFXMMU LUT entry 314 low" start="+0x19D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT314H" description="GFXMMU LUT entry 314 high" start="+0x19D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT315L" description="GFXMMU LUT entry 315 low" start="+0x19D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT315H" description="GFXMMU LUT entry 315 high" start="+0x19DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT316L" description="GFXMMU LUT entry 316 low" start="+0x19E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT316H" description="GFXMMU LUT entry 316 high" start="+0x19E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT317L" description="GFXMMU LUT entry 317 low" start="+0x19E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT317H" description="GFXMMU LUT entry 317 high" start="+0x19EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT318L" description="GFXMMU LUT entry 318 low" start="+0x19F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT318H" description="GFXMMU LUT entry 318 high" start="+0x19F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT319L" description="GFXMMU LUT entry 319 low" start="+0x19F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT319H" description="GFXMMU LUT entry 319 high" start="+0x19FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT320L" description="GFXMMU LUT entry 320 low" start="+0x1A00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT320H" description="GFXMMU LUT entry 320 high" start="+0x1A04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT321L" description="GFXMMU LUT entry 321 low" start="+0x1A08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT321H" description="GFXMMU LUT entry 321 high" start="+0x1A0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT322L" description="GFXMMU LUT entry 322 low" start="+0x1A10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT322H" description="GFXMMU LUT entry 322 high" start="+0x1A14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT323L" description="GFXMMU LUT entry 323 low" start="+0x1A18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT323H" description="GFXMMU LUT entry 323 high" start="+0x1A1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT324L" description="GFXMMU LUT entry 324 low" start="+0x1A20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT324H" description="GFXMMU LUT entry 324 high" start="+0x1A24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT325L" description="GFXMMU LUT entry 325 low" start="+0x1A28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT325H" description="GFXMMU LUT entry 325 high" start="+0x1A2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT326L" description="GFXMMU LUT entry 326 low" start="+0x1A30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT326H" description="GFXMMU LUT entry 326 high" start="+0x1A34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT327L" description="GFXMMU LUT entry 327 low" start="+0x1A38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT327H" description="GFXMMU LUT entry 327 high" start="+0x1A3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT328L" description="GFXMMU LUT entry 328 low" start="+0x1A40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT328H" description="GFXMMU LUT entry 328 high" start="+0x1A44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT329L" description="GFXMMU LUT entry 329 low" start="+0x1A48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT329H" description="GFXMMU LUT entry 329 high" start="+0x1A4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT330L" description="GFXMMU LUT entry 330 low" start="+0x1A50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT330H" description="GFXMMU LUT entry 330 high" start="+0x1A54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT331L" description="GFXMMU LUT entry 331 low" start="+0x1A58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT331H" description="GFXMMU LUT entry 331 high" start="+0x1A5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT332L" description="GFXMMU LUT entry 332 low" start="+0x1A60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT332H" description="GFXMMU LUT entry 332 high" start="+0x1A64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT333L" description="GFXMMU LUT entry 333 low" start="+0x1A68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT333H" description="GFXMMU LUT entry 333 high" start="+0x1A6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT334L" description="GFXMMU LUT entry 334 low" start="+0x1A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT334H" description="GFXMMU LUT entry 334 high" start="+0x1A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT335L" description="GFXMMU LUT entry 335 low" start="+0x1A78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT335H" description="GFXMMU LUT entry 335 high" start="+0x1A7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT336L" description="GFXMMU LUT entry 336 low" start="+0x1A80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT336H" description="GFXMMU LUT entry 336 high" start="+0x1A84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT337L" description="GFXMMU LUT entry 337 low" start="+0x1A88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT337H" description="GFXMMU LUT entry 337 high" start="+0x1A8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT338L" description="GFXMMU LUT entry 338 low" start="+0x1A90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT338H" description="GFXMMU LUT entry 338 high" start="+0x1A94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT339L" description="GFXMMU LUT entry 339 low" start="+0x1A98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT339H" description="GFXMMU LUT entry 339 high" start="+0x1A9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT340L" description="GFXMMU LUT entry 340 low" start="+0x1AA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT340H" description="GFXMMU LUT entry 340 high" start="+0x1AA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT341L" description="GFXMMU LUT entry 341 low" start="+0x1AA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT341H" description="GFXMMU LUT entry 341 high" start="+0x1AAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT342L" description="GFXMMU LUT entry 342 low" start="+0x1AB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT342H" description="GFXMMU LUT entry 342 high" start="+0x1AB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT343L" description="GFXMMU LUT entry 343 low" start="+0x1AB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT343H" description="GFXMMU LUT entry 343 high" start="+0x1ABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT344L" description="GFXMMU LUT entry 344 low" start="+0x1AC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT344H" description="GFXMMU LUT entry 344 high" start="+0x1AC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT345L" description="GFXMMU LUT entry 345 low" start="+0x1AC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT345H" description="GFXMMU LUT entry 345 high" start="+0x1ACC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT346L" description="GFXMMU LUT entry 346 low" start="+0x1AD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT346H" description="GFXMMU LUT entry 346 high" start="+0x1AD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT347L" description="GFXMMU LUT entry 347 low" start="+0x1AD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT347H" description="GFXMMU LUT entry 347 high" start="+0x1ADC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT348L" description="GFXMMU LUT entry 348 low" start="+0x1AE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT348H" description="GFXMMU LUT entry 348 high" start="+0x1AE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT349L" description="GFXMMU LUT entry 349 low" start="+0x1AE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT349H" description="GFXMMU LUT entry 349 high" start="+0x1AEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT350L" description="GFXMMU LUT entry 350 low" start="+0x1AF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT350H" description="GFXMMU LUT entry 350 high" start="+0x1AF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT351L" description="GFXMMU LUT entry 351 low" start="+0x1AF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT351H" description="GFXMMU LUT entry 351 high" start="+0x1AFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT352L" description="GFXMMU LUT entry 352 low" start="+0x1B00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT352H" description="GFXMMU LUT entry 352 high" start="+0x1B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT353L" description="GFXMMU LUT entry 353 low" start="+0x1B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT353H" description="GFXMMU LUT entry 353 high" start="+0x1B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT354L" description="GFXMMU LUT entry 354 low" start="+0x1B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT354H" description="GFXMMU LUT entry 354 high" start="+0x1B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT355L" description="GFXMMU LUT entry 355 low" start="+0x1B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT355H" description="GFXMMU LUT entry 355 high" start="+0x1B1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT356L" description="GFXMMU LUT entry 356 low" start="+0x1B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT356H" description="GFXMMU LUT entry 356 high" start="+0x1B24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT357L" description="GFXMMU LUT entry 357 low" start="+0x1B28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT357H" description="GFXMMU LUT entry 357 high" start="+0x1B2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT358L" description="GFXMMU LUT entry 358 low" start="+0x1B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT358H" description="GFXMMU LUT entry 358 high" start="+0x1B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT359L" description="GFXMMU LUT entry 359 low" start="+0x1B38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT359H" description="GFXMMU LUT entry 359 high" start="+0x1B3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT360L" description="GFXMMU LUT entry 360 low" start="+0x1B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT360H" description="GFXMMU LUT entry 360 high" start="+0x1B44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT361L" description="GFXMMU LUT entry 361 low" start="+0x1B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT361H" description="GFXMMU LUT entry 361 high" start="+0x1B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT362L" description="GFXMMU LUT entry 362 low" start="+0x1B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT362H" description="GFXMMU LUT entry 362 high" start="+0x1B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT363L" description="GFXMMU LUT entry 363 low" start="+0x1B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT363H" description="GFXMMU LUT entry 363 high" start="+0x1B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT364L" description="GFXMMU LUT entry 364 low" start="+0x1B60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT364H" description="GFXMMU LUT entry 364 high" start="+0x1B64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT365L" description="GFXMMU LUT entry 365 low" start="+0x1B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT365H" description="GFXMMU LUT entry 365 high" start="+0x1B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT366L" description="GFXMMU LUT entry 366 low" start="+0x1B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT366H" description="GFXMMU LUT entry 366 high" start="+0x1B74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT367L" description="GFXMMU LUT entry 367 low" start="+0x1B78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT367H" description="GFXMMU LUT entry 367 high" start="+0x1B7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT368L" description="GFXMMU LUT entry 368 low" start="+0x1B80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT368H" description="GFXMMU LUT entry 368 high" start="+0x1B84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT369L" description="GFXMMU LUT entry 369 low" start="+0x1B88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT369H" description="GFXMMU LUT entry 369 high" start="+0x1B8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT370L" description="GFXMMU LUT entry 370 low" start="+0x1B90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT370H" description="GFXMMU LUT entry 370 high" start="+0x1B94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT371L" description="GFXMMU LUT entry 371 low" start="+0x1B98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT371H" description="GFXMMU LUT entry 371 high" start="+0x1B9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT372L" description="GFXMMU LUT entry 372 low" start="+0x1BA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT372H" description="GFXMMU LUT entry 372 high" start="+0x1BA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT373L" description="GFXMMU LUT entry 373 low" start="+0x1BA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT373H" description="GFXMMU LUT entry 373 high" start="+0x1BAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT374L" description="GFXMMU LUT entry 374 low" start="+0x1BB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT374H" description="GFXMMU LUT entry 374 high" start="+0x1BB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT375L" description="GFXMMU LUT entry 375 low" start="+0x1BB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT375H" description="GFXMMU LUT entry 375 high" start="+0x1BBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT376L" description="GFXMMU LUT entry 376 low" start="+0x1BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT376H" description="GFXMMU LUT entry 376 high" start="+0x1BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT377L" description="GFXMMU LUT entry 377 low" start="+0x1BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT377H" description="GFXMMU LUT entry 377 high" start="+0x1BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT378L" description="GFXMMU LUT entry 378 low" start="+0x1BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT378H" description="GFXMMU LUT entry 378 high" start="+0x1BD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT379L" description="GFXMMU LUT entry 379 low" start="+0x1BD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT379H" description="GFXMMU LUT entry 379 high" start="+0x1BDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT380L" description="GFXMMU LUT entry 380 low" start="+0x1BE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT380H" description="GFXMMU LUT entry 380 high" start="+0x1BE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT381L" description="GFXMMU LUT entry 381 low" start="+0x1BE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT381H" description="GFXMMU LUT entry 381 high" start="+0x1BEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT382L" description="GFXMMU LUT entry 382 low" start="+0x1BF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT382H" description="GFXMMU LUT entry 382 high" start="+0x1BF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT383L" description="GFXMMU LUT entry 383 low" start="+0x1BF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT383H" description="GFXMMU LUT entry 383 high" start="+0x1BFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT384L" description="GFXMMU LUT entry 384 low" start="+0x1C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT384H" description="GFXMMU LUT entry 384 high" start="+0x1C04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT385L" description="GFXMMU LUT entry 385 low" start="+0x1C08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT385H" description="GFXMMU LUT entry 385 high" start="+0x1C0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT386L" description="GFXMMU LUT entry 386 low" start="+0x1C10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT386H" description="GFXMMU LUT entry 386 high" start="+0x1C14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT387L" description="GFXMMU LUT entry 387 low" start="+0x1C18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT387H" description="GFXMMU LUT entry 387 high" start="+0x1C1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT388L" description="GFXMMU LUT entry 388 low" start="+0x1C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT388H" description="GFXMMU LUT entry 388 high" start="+0x1C24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT389L" description="GFXMMU LUT entry 389 low" start="+0x1C28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT389H" description="GFXMMU LUT entry 389 high" start="+0x1C2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT390L" description="GFXMMU LUT entry 390 low" start="+0x1C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT390H" description="GFXMMU LUT entry 390 high" start="+0x1C34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT391L" description="GFXMMU LUT entry 391 low" start="+0x1C38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT391H" description="GFXMMU LUT entry 391 high" start="+0x1C3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT392L" description="GFXMMU LUT entry 392 low" start="+0x1C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT392H" description="GFXMMU LUT entry 392 high" start="+0x1C44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT393L" description="GFXMMU LUT entry 393 low" start="+0x1C48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT393H" description="GFXMMU LUT entry 393 high" start="+0x1C4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT394L" description="GFXMMU LUT entry 394 low" start="+0x1C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT394H" description="GFXMMU LUT entry 394 high" start="+0x1C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT395L" description="GFXMMU LUT entry 395 low" start="+0x1C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT395H" description="GFXMMU LUT entry 395 high" start="+0x1C5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT396L" description="GFXMMU LUT entry 396 low" start="+0x1C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT396H" description="GFXMMU LUT entry 396 high" start="+0x1C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT397L" description="GFXMMU LUT entry 397 low" start="+0x1C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT397H" description="GFXMMU LUT entry 397 high" start="+0x1C6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT398L" description="GFXMMU LUT entry 398 low" start="+0x1C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT398H" description="GFXMMU LUT entry 398 high" start="+0x1C74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT399L" description="GFXMMU LUT entry 399 low" start="+0x1C78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT399H" description="GFXMMU LUT entry 399 high" start="+0x1C7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT400L" description="GFXMMU LUT entry 400 low" start="+0x1C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT400H" description="GFXMMU LUT entry 400 high" start="+0x1C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT401L" description="GFXMMU LUT entry 401 low" start="+0x1C88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT401H" description="GFXMMU LUT entry 401 high" start="+0x1C8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT402L" description="GFXMMU LUT entry 402 low" start="+0x1C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT402H" description="GFXMMU LUT entry 402 high" start="+0x1C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT403L" description="GFXMMU LUT entry 403 low" start="+0x1C98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT403H" description="GFXMMU LUT entry 403 high" start="+0x1C9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT404L" description="GFXMMU LUT entry 404 low" start="+0x1CA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT404H" description="GFXMMU LUT entry 404 high" start="+0x1CA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT405L" description="GFXMMU LUT entry 405 low" start="+0x1CA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT405H" description="GFXMMU LUT entry 405 high" start="+0x1CAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT406L" description="GFXMMU LUT entry 406 low" start="+0x1CB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT406H" description="GFXMMU LUT entry 406 high" start="+0x1CB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT407L" description="GFXMMU LUT entry 407 low" start="+0x1CB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT407H" description="GFXMMU LUT entry 407 high" start="+0x1CBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT408L" description="GFXMMU LUT entry 408 low" start="+0x1CC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT408H" description="GFXMMU LUT entry 408 high" start="+0x1CC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT409L" description="GFXMMU LUT entry 409 low" start="+0x1CC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT409H" description="GFXMMU LUT entry 409 high" start="+0x1CCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT410L" description="GFXMMU LUT entry 410 low" start="+0x1CD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT410H" description="GFXMMU LUT entry 410 high" start="+0x1CD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT411L" description="GFXMMU LUT entry 411 low" start="+0x1CD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT411H" description="GFXMMU LUT entry 411 high" start="+0x1CDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT412L" description="GFXMMU LUT entry 412 low" start="+0x1CE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT412H" description="GFXMMU LUT entry 412 high" start="+0x1CE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT413L" description="GFXMMU LUT entry 413 low" start="+0x1CE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT413H" description="GFXMMU LUT entry 413 high" start="+0x1CEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT414L" description="GFXMMU LUT entry 414 low" start="+0x1CF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT414H" description="GFXMMU LUT entry 414 high" start="+0x1CF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT415L" description="GFXMMU LUT entry 415 low" start="+0x1CF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT415H" description="GFXMMU LUT entry 415 high" start="+0x1CFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT416L" description="GFXMMU LUT entry 416 low" start="+0x1D00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT416H" description="GFXMMU LUT entry 416 high" start="+0x1D04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT417L" description="GFXMMU LUT entry 417 low" start="+0x1D08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT417H" description="GFXMMU LUT entry 417 high" start="+0x1D0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT418L" description="GFXMMU LUT entry 418 low" start="+0x1D10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT418H" description="GFXMMU LUT entry 418 high" start="+0x1D14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT419L" description="GFXMMU LUT entry 419 low" start="+0x1D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT419H" description="GFXMMU LUT entry 419 high" start="+0x1D1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT420L" description="GFXMMU LUT entry 420 low" start="+0x1D20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT420H" description="GFXMMU LUT entry 420 high" start="+0x1D24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT421L" description="GFXMMU LUT entry 421 low" start="+0x1D28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT421H" description="GFXMMU LUT entry 421 high" start="+0x1D2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT422L" description="GFXMMU LUT entry 422 low" start="+0x1D30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT422H" description="GFXMMU LUT entry 422 high" start="+0x1D34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT423L" description="GFXMMU LUT entry 423 low" start="+0x1D38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT423H" description="GFXMMU LUT entry 423 high" start="+0x1D3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT424L" description="GFXMMU LUT entry 424 low" start="+0x1D40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT424H" description="GFXMMU LUT entry 424 high" start="+0x1D44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT425L" description="GFXMMU LUT entry 425 low" start="+0x1D48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT425H" description="GFXMMU LUT entry 425 high" start="+0x1D4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT426L" description="GFXMMU LUT entry 426 low" start="+0x1D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT426H" description="GFXMMU LUT entry 426 high" start="+0x1D54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT427L" description="GFXMMU LUT entry 427 low" start="+0x1D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT427H" description="GFXMMU LUT entry 427 high" start="+0x1D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT428L" description="GFXMMU LUT entry 428 low" start="+0x1D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT428H" description="GFXMMU LUT entry 428 high" start="+0x1D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT429L" description="GFXMMU LUT entry 429 low" start="+0x1D68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT429H" description="GFXMMU LUT entry 429 high" start="+0x1D6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT430L" description="GFXMMU LUT entry 430 low" start="+0x1D70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT430H" description="GFXMMU LUT entry 430 high" start="+0x1D74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT431L" description="GFXMMU LUT entry 431 low" start="+0x1D78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT431H" description="GFXMMU LUT entry 431 high" start="+0x1D7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT432L" description="GFXMMU LUT entry 432 low" start="+0x1D80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT432H" description="GFXMMU LUT entry 432 high" start="+0x1D84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT433L" description="GFXMMU LUT entry 433 low" start="+0x1D88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT433H" description="GFXMMU LUT entry 433 high" start="+0x1D8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT434L" description="GFXMMU LUT entry 434 low" start="+0x1D90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT434H" description="GFXMMU LUT entry 434 high" start="+0x1D94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT435L" description="GFXMMU LUT entry 435 low" start="+0x1D98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT435H" description="GFXMMU LUT entry 435 high" start="+0x1D9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT436L" description="GFXMMU LUT entry 436 low" start="+0x1DA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT436H" description="GFXMMU LUT entry 436 high" start="+0x1DA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT437L" description="GFXMMU LUT entry 437 low" start="+0x1DA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT437H" description="GFXMMU LUT entry 437 high" start="+0x1DAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT438L" description="GFXMMU LUT entry 438 low" start="+0x1DB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT438H" description="GFXMMU LUT entry 438 high" start="+0x1DB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT439L" description="GFXMMU LUT entry 439 low" start="+0x1DB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT439H" description="GFXMMU LUT entry 439 high" start="+0x1DBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT440L" description="GFXMMU LUT entry 440 low" start="+0x1DC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT440H" description="GFXMMU LUT entry 440 high" start="+0x1DC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT441L" description="GFXMMU LUT entry 441 low" start="+0x1DC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT441H" description="GFXMMU LUT entry 441 high" start="+0x1DCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT442L" description="GFXMMU LUT entry 442 low" start="+0x1DD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT442H" description="GFXMMU LUT entry 442 high" start="+0x1DD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT443L" description="GFXMMU LUT entry 443 low" start="+0x1DD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT443H" description="GFXMMU LUT entry 443 high" start="+0x1DDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT444L" description="GFXMMU LUT entry 444 low" start="+0x1DE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT444H" description="GFXMMU LUT entry 444 high" start="+0x1DE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT445L" description="GFXMMU LUT entry 445 low" start="+0x1DE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT445H" description="GFXMMU LUT entry 445 high" start="+0x1DEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT446L" description="GFXMMU LUT entry 446 low" start="+0x1DF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT446H" description="GFXMMU LUT entry 446 high" start="+0x1DF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT447L" description="GFXMMU LUT entry 447 low" start="+0x1DF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT447H" description="GFXMMU LUT entry 447 high" start="+0x1DFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT448L" description="GFXMMU LUT entry 448 low" start="+0x1E00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT448H" description="GFXMMU LUT entry 448 high" start="+0x1E04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT449L" description="GFXMMU LUT entry 449 low" start="+0x1E08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT449H" description="GFXMMU LUT entry 449 high" start="+0x1E0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT450L" description="GFXMMU LUT entry 450 low" start="+0x1E10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT450H" description="GFXMMU LUT entry 450 high" start="+0x1E14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT451L" description="GFXMMU LUT entry 451 low" start="+0x1E18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT451H" description="GFXMMU LUT entry 451 high" start="+0x1E1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT452L" description="GFXMMU LUT entry 452 low" start="+0x1E20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT452H" description="GFXMMU LUT entry 452 high" start="+0x1E24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT453L" description="GFXMMU LUT entry 453 low" start="+0x1E28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT453H" description="GFXMMU LUT entry 453 high" start="+0x1E2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT454L" description="GFXMMU LUT entry 454 low" start="+0x1E30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT454H" description="GFXMMU LUT entry 454 high" start="+0x1E34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT455L" description="GFXMMU LUT entry 455 low" start="+0x1E38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT455H" description="GFXMMU LUT entry 455 high" start="+0x1E3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT456L" description="GFXMMU LUT entry 456 low" start="+0x1E40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT456H" description="GFXMMU LUT entry 456 high" start="+0x1E44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT457L" description="GFXMMU LUT entry 457 low" start="+0x1E48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT457H" description="GFXMMU LUT entry 457 high" start="+0x1E4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT458L" description="GFXMMU LUT entry 458 low" start="+0x1E50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT458H" description="GFXMMU LUT entry 458 high" start="+0x1E54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT459L" description="GFXMMU LUT entry 459 low" start="+0x1E58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT459H" description="GFXMMU LUT entry 459 high" start="+0x1E5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT460L" description="GFXMMU LUT entry 460 low" start="+0x1E60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT460H" description="GFXMMU LUT entry 460 high" start="+0x1E64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT461L" description="GFXMMU LUT entry 461 low" start="+0x1E68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT461H" description="GFXMMU LUT entry 461 high" start="+0x1E6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT462L" description="GFXMMU LUT entry 462 low" start="+0x1E70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT462H" description="GFXMMU LUT entry 462 high" start="+0x1E74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT463L" description="GFXMMU LUT entry 463 low" start="+0x1E78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT463H" description="GFXMMU LUT entry 463 high" start="+0x1E7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT464L" description="GFXMMU LUT entry 464 low" start="+0x1E80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT464H" description="GFXMMU LUT entry 464 high" start="+0x1E84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT465L" description="GFXMMU LUT entry 465 low" start="+0x1E88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT465H" description="GFXMMU LUT entry 465 high" start="+0x1E8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT466L" description="GFXMMU LUT entry 466 low" start="+0x1E90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT466H" description="GFXMMU LUT entry 466 high" start="+0x1E94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT467L" description="GFXMMU LUT entry 467 low" start="+0x1E98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT467H" description="GFXMMU LUT entry 467 high" start="+0x1E9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT468L" description="GFXMMU LUT entry 468 low" start="+0x1EA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT468H" description="GFXMMU LUT entry 468 high" start="+0x1EA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT469L" description="GFXMMU LUT entry 469 low" start="+0x1EA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT469H" description="GFXMMU LUT entry 469 high" start="+0x1EAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT470L" description="GFXMMU LUT entry 470 low" start="+0x1EB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT470H" description="GFXMMU LUT entry 470 high" start="+0x1EB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT471L" description="GFXMMU LUT entry 471 low" start="+0x1EB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT471H" description="GFXMMU LUT entry 471 high" start="+0x1EBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT472L" description="GFXMMU LUT entry 472 low" start="+0x1EC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT472H" description="GFXMMU LUT entry 472 high" start="+0x1EC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT473L" description="GFXMMU LUT entry 473 low" start="+0x1EC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT473H" description="GFXMMU LUT entry 473 high" start="+0x1ECC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT474L" description="GFXMMU LUT entry 474 low" start="+0x1ED0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT474H" description="GFXMMU LUT entry 474 high" start="+0x1ED4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT475L" description="GFXMMU LUT entry 475 low" start="+0x1ED8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT475H" description="GFXMMU LUT entry 475 high" start="+0x1EDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT476L" description="GFXMMU LUT entry 476 low" start="+0x1EE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT476H" description="GFXMMU LUT entry 476 high" start="+0x1EE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT477L" description="GFXMMU LUT entry 477 low" start="+0x1EE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT477H" description="GFXMMU LUT entry 477 high" start="+0x1EEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT478L" description="GFXMMU LUT entry 478 low" start="+0x1EF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT478H" description="GFXMMU LUT entry 478 high" start="+0x1EF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT479L" description="GFXMMU LUT entry 479 low" start="+0x1EF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT479H" description="GFXMMU LUT entry 479 high" start="+0x1EFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT480L" description="GFXMMU LUT entry 480 low" start="+0x1F00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT480H" description="GFXMMU LUT entry 480 high" start="+0x1F04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT481L" description="GFXMMU LUT entry 481 low" start="+0x1F08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT481H" description="GFXMMU LUT entry 481 high" start="+0x1F0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT482L" description="GFXMMU LUT entry 482 low" start="+0x1F10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT482H" description="GFXMMU LUT entry 482 high" start="+0x1F14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT483L" description="GFXMMU LUT entry 483 low" start="+0x1F18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT483H" description="GFXMMU LUT entry 483 high" start="+0x1F1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT484L" description="GFXMMU LUT entry 484 low" start="+0x1F20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT484H" description="GFXMMU LUT entry 484 high" start="+0x1F24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT485L" description="GFXMMU LUT entry 485 low" start="+0x1F28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT485H" description="GFXMMU LUT entry 485 high" start="+0x1F2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT486L" description="GFXMMU LUT entry 486 low" start="+0x1F30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT486H" description="GFXMMU LUT entry 486 high" start="+0x1F34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT487L" description="GFXMMU LUT entry 487 low" start="+0x1F38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT487H" description="GFXMMU LUT entry 487 high" start="+0x1F3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT488L" description="GFXMMU LUT entry 488 low" start="+0x1F40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT488H" description="GFXMMU LUT entry 488 high" start="+0x1F44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT489L" description="GFXMMU LUT entry 489 low" start="+0x1F48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT489H" description="GFXMMU LUT entry 489 high" start="+0x1F4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT490L" description="GFXMMU LUT entry 490 low" start="+0x1F50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT490H" description="GFXMMU LUT entry 490 high" start="+0x1F54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT491L" description="GFXMMU LUT entry 491 low" start="+0x1F58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT491H" description="GFXMMU LUT entry 491 high" start="+0x1F5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT492L" description="GFXMMU LUT entry 492 low" start="+0x1F60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT492H" description="GFXMMU LUT entry 492 high" start="+0x1F64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT493L" description="GFXMMU LUT entry 493 low" start="+0x1F68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT493H" description="GFXMMU LUT entry 493 high" start="+0x1F6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT494L" description="GFXMMU LUT entry 494 low" start="+0x1F70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT494H" description="GFXMMU LUT entry 494 high" start="+0x1F74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT495L" description="GFXMMU LUT entry 495 low" start="+0x1F78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT495H" description="GFXMMU LUT entry 495 high" start="+0x1F7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT496L" description="GFXMMU LUT entry 496 low" start="+0x1F80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT496H" description="GFXMMU LUT entry 496 high" start="+0x1F84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT497L" description="GFXMMU LUT entry 497 low" start="+0x1F88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT497H" description="GFXMMU LUT entry 497 high" start="+0x1F8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT498L" description="GFXMMU LUT entry 498 low" start="+0x1F90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT498H" description="GFXMMU LUT entry 498 high" start="+0x1F94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT499L" description="GFXMMU LUT entry 499 low" start="+0x1F98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT499H" description="GFXMMU LUT entry 499 high" start="+0x1F9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT500L" description="GFXMMU LUT entry 500 low" start="+0x1FA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT500H" description="GFXMMU LUT entry 500 high" start="+0x1FA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT501L" description="GFXMMU LUT entry 501 low" start="+0x1FA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT501H" description="GFXMMU LUT entry 501 high" start="+0x1FAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT502L" description="GFXMMU LUT entry 502 low" start="+0x1FB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT502H" description="GFXMMU LUT entry 502 high" start="+0x1FB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT503L" description="GFXMMU LUT entry 503 low" start="+0x1FB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT503H" description="GFXMMU LUT entry 503 high" start="+0x1FBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT504L" description="GFXMMU LUT entry 504 low" start="+0x1FC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT504H" description="GFXMMU LUT entry 504 high" start="+0x1FC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT505L" description="GFXMMU LUT entry 505 low" start="+0x1FC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT505H" description="GFXMMU LUT entry 505 high" start="+0x1FCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT506L" description="GFXMMU LUT entry 506 low" start="+0x1FD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT506H" description="GFXMMU LUT entry 506 high" start="+0x1FD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT507L" description="GFXMMU LUT entry 507 low" start="+0x1FD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT507H" description="GFXMMU LUT entry 507 high" start="+0x1FDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT508L" description="GFXMMU LUT entry 508 low" start="+0x1FE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT508H" description="GFXMMU LUT entry 508 high" start="+0x1FE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT509L" description="GFXMMU LUT entry 509 low" start="+0x1FE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT509H" description="GFXMMU LUT entry 509 high" start="+0x1FEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT510L" description="GFXMMU LUT entry 510 low" start="+0x1FF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT510H" description="GFXMMU LUT entry 510 high" start="+0x1FF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT511L" description="GFXMMU LUT entry 511 low" start="+0x1FF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT511H" description="GFXMMU LUT entry 511 high" start="+0x1FFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT512L" description="GFXMMU LUT entry 512 low" start="+0x2000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT512H" description="GFXMMU LUT entry 512 high" start="+0x2004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT513L" description="GFXMMU LUT entry 513 low" start="+0x2008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT513H" description="GFXMMU LUT entry 513 high" start="+0x200C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT514L" description="GFXMMU LUT entry 514 low" start="+0x2010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT514H" description="GFXMMU LUT entry 514 high" start="+0x2014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT515L" description="GFXMMU LUT entry 515 low" start="+0x2018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT515H" description="GFXMMU LUT entry 515 high" start="+0x201C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT516L" description="GFXMMU LUT entry 516 low" start="+0x2020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT516H" description="GFXMMU LUT entry 516 high" start="+0x2024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT517L" description="GFXMMU LUT entry 517 low" start="+0x2028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT517H" description="GFXMMU LUT entry 517 high" start="+0x202C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT518L" description="GFXMMU LUT entry 518 low" start="+0x2030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT518H" description="GFXMMU LUT entry 518 high" start="+0x2034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT519L" description="GFXMMU LUT entry 519 low" start="+0x2038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT519H" description="GFXMMU LUT entry 519 high" start="+0x203C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT520L" description="GFXMMU LUT entry 520 low" start="+0x2040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT520H" description="GFXMMU LUT entry 520 high" start="+0x2044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT521L" description="GFXMMU LUT entry 521 low" start="+0x2048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT521H" description="GFXMMU LUT entry 521 high" start="+0x204C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT522L" description="GFXMMU LUT entry 522 low" start="+0x2050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT522H" description="GFXMMU LUT entry 522 high" start="+0x2054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT523L" description="GFXMMU LUT entry 523 low" start="+0x2058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT523H" description="GFXMMU LUT entry 523 high" start="+0x205C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT524L" description="GFXMMU LUT entry 524 low" start="+0x2060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT524H" description="GFXMMU LUT entry 524 high" start="+0x2064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT525L" description="GFXMMU LUT entry 525 low" start="+0x2068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT525H" description="GFXMMU LUT entry 525 high" start="+0x206C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT526L" description="GFXMMU LUT entry 526 low" start="+0x2070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT526H" description="GFXMMU LUT entry 526 high" start="+0x2074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT527L" description="GFXMMU LUT entry 527 low" start="+0x2078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT527H" description="GFXMMU LUT entry 527 high" start="+0x207C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT528L" description="GFXMMU LUT entry 528 low" start="+0x2080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT528H" description="GFXMMU LUT entry 528 high" start="+0x2084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT529L" description="GFXMMU LUT entry 529 low" start="+0x2088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT529H" description="GFXMMU LUT entry 529 high" start="+0x208C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT530L" description="GFXMMU LUT entry 530 low" start="+0x2090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT530H" description="GFXMMU LUT entry 530 high" start="+0x2094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT531L" description="GFXMMU LUT entry 531 low" start="+0x2098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT531H" description="GFXMMU LUT entry 531 high" start="+0x209C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT532L" description="GFXMMU LUT entry 532 low" start="+0x20A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT532H" description="GFXMMU LUT entry 532 high" start="+0x20A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT533L" description="GFXMMU LUT entry 533 low" start="+0x20A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT533H" description="GFXMMU LUT entry 533 high" start="+0x20AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT534L" description="GFXMMU LUT entry 534 low" start="+0x20B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT534H" description="GFXMMU LUT entry 534 high" start="+0x20B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT535L" description="GFXMMU LUT entry 535 low" start="+0x20B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT535H" description="GFXMMU LUT entry 535 high" start="+0x20BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT536L" description="GFXMMU LUT entry 536 low" start="+0x20C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT536H" description="GFXMMU LUT entry 536 high" start="+0x20C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT537L" description="GFXMMU LUT entry 537 low" start="+0x20C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT537H" description="GFXMMU LUT entry 537 high" start="+0x20CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT538L" description="GFXMMU LUT entry 538 low" start="+0x20D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT538H" description="GFXMMU LUT entry 538 high" start="+0x20D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT539L" description="GFXMMU LUT entry 539 low" start="+0x20D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT539H" description="GFXMMU LUT entry 539 high" start="+0x20DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT540L" description="GFXMMU LUT entry 540 low" start="+0x20E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT540H" description="GFXMMU LUT entry 540 high" start="+0x20E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT541L" description="GFXMMU LUT entry 541 low" start="+0x20E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT541H" description="GFXMMU LUT entry 541 high" start="+0x20EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT542L" description="GFXMMU LUT entry 542 low" start="+0x20F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT542H" description="GFXMMU LUT entry 542 high" start="+0x20F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT543L" description="GFXMMU LUT entry 543 low" start="+0x20F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT543H" description="GFXMMU LUT entry 543 high" start="+0x20FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT544L" description="GFXMMU LUT entry 544 low" start="+0x2100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT544H" description="GFXMMU LUT entry 544 high" start="+0x2104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT545L" description="GFXMMU LUT entry 545 low" start="+0x2108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT545H" description="GFXMMU LUT entry 545 high" start="+0x210C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT546L" description="GFXMMU LUT entry 546 low" start="+0x2110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT546H" description="GFXMMU LUT entry 546 high" start="+0x2114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT547L" description="GFXMMU LUT entry 547 low" start="+0x2118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT547H" description="GFXMMU LUT entry 547 high" start="+0x211C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT548L" description="GFXMMU LUT entry 548 low" start="+0x2120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT548H" description="GFXMMU LUT entry 548 high" start="+0x2124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT549L" description="GFXMMU LUT entry 549 low" start="+0x2128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT549H" description="GFXMMU LUT entry 549 high" start="+0x212C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT550L" description="GFXMMU LUT entry 550 low" start="+0x2130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT550H" description="GFXMMU LUT entry 550 high" start="+0x2134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT551L" description="GFXMMU LUT entry 551 low" start="+0x2138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT551H" description="GFXMMU LUT entry 551 high" start="+0x213C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT552L" description="GFXMMU LUT entry 552 low" start="+0x2140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT552H" description="GFXMMU LUT entry 552 high" start="+0x2144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT553L" description="GFXMMU LUT entry 553 low" start="+0x2148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT553H" description="GFXMMU LUT entry 553 high" start="+0x214C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT554L" description="GFXMMU LUT entry 554 low" start="+0x2150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT554H" description="GFXMMU LUT entry 554 high" start="+0x2154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT555L" description="GFXMMU LUT entry 555 low" start="+0x2158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT555H" description="GFXMMU LUT entry 555 high" start="+0x215C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT556L" description="GFXMMU LUT entry 556 low" start="+0x2160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT556H" description="GFXMMU LUT entry 556 high" start="+0x2164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT557L" description="GFXMMU LUT entry 557 low" start="+0x2168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT557H" description="GFXMMU LUT entry 557 high" start="+0x216C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT558L" description="GFXMMU LUT entry 558 low" start="+0x2170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT558H" description="GFXMMU LUT entry 558 high" start="+0x2174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT559L" description="GFXMMU LUT entry 559 low" start="+0x2178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT559H" description="GFXMMU LUT entry 559 high" start="+0x217C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT560L" description="GFXMMU LUT entry 560 low" start="+0x2180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT560H" description="GFXMMU LUT entry 560 high" start="+0x2184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT561L" description="GFXMMU LUT entry 561 low" start="+0x2188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT561H" description="GFXMMU LUT entry 561 high" start="+0x218C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT562L" description="GFXMMU LUT entry 562 low" start="+0x2190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT562H" description="GFXMMU LUT entry 562 high" start="+0x2194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT563L" description="GFXMMU LUT entry 563 low" start="+0x2198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT563H" description="GFXMMU LUT entry 563 high" start="+0x219C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT564L" description="GFXMMU LUT entry 564 low" start="+0x21A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT564H" description="GFXMMU LUT entry 564 high" start="+0x21A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT565L" description="GFXMMU LUT entry 565 low" start="+0x21A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT565H" description="GFXMMU LUT entry 565 high" start="+0x21AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT566L" description="GFXMMU LUT entry 566 low" start="+0x21B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT566H" description="GFXMMU LUT entry 566 high" start="+0x21B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT567L" description="GFXMMU LUT entry 567 low" start="+0x21B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT567H" description="GFXMMU LUT entry 567 high" start="+0x21BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT568L" description="GFXMMU LUT entry 568 low" start="+0x21C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT568H" description="GFXMMU LUT entry 568 high" start="+0x21C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT569L" description="GFXMMU LUT entry 569 low" start="+0x21C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT569H" description="GFXMMU LUT entry 569 high" start="+0x21CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT570L" description="GFXMMU LUT entry 570 low" start="+0x21D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT570H" description="GFXMMU LUT entry 570 high" start="+0x21D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT571L" description="GFXMMU LUT entry 571 low" start="+0x21D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT571H" description="GFXMMU LUT entry 571 high" start="+0x21DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT572L" description="GFXMMU LUT entry 572 low" start="+0x21E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT572H" description="GFXMMU LUT entry 572 high" start="+0x21E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT573L" description="GFXMMU LUT entry 573 low" start="+0x21E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT573H" description="GFXMMU LUT entry 573 high" start="+0x21EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT574L" description="GFXMMU LUT entry 574 low" start="+0x21F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT574H" description="GFXMMU LUT entry 574 high" start="+0x21F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT575L" description="GFXMMU LUT entry 575 low" start="+0x21F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT575H" description="GFXMMU LUT entry 575 high" start="+0x21FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT576L" description="GFXMMU LUT entry 576 low" start="+0x2200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT576H" description="GFXMMU LUT entry 576 high" start="+0x2204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT577L" description="GFXMMU LUT entry 577 low" start="+0x2208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT577H" description="GFXMMU LUT entry 577 high" start="+0x220C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT578L" description="GFXMMU LUT entry 578 low" start="+0x2210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT578H" description="GFXMMU LUT entry 578 high" start="+0x2214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT579L" description="GFXMMU LUT entry 579 low" start="+0x2218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT579H" description="GFXMMU LUT entry 579 high" start="+0x221C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT580L" description="GFXMMU LUT entry 580 low" start="+0x2220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT580H" description="GFXMMU LUT entry 580 high" start="+0x2224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT581L" description="GFXMMU LUT entry 581 low" start="+0x2228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT581H" description="GFXMMU LUT entry 581 high" start="+0x222C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT582L" description="GFXMMU LUT entry 582 low" start="+0x2230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT582H" description="GFXMMU LUT entry 582 high" start="+0x2234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT583L" description="GFXMMU LUT entry 583 low" start="+0x2238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT583H" description="GFXMMU LUT entry 583 high" start="+0x223C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT584L" description="GFXMMU LUT entry 584 low" start="+0x2240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT584H" description="GFXMMU LUT entry 584 high" start="+0x2244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT585L" description="GFXMMU LUT entry 585 low" start="+0x2248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT585H" description="GFXMMU LUT entry 585 high" start="+0x224C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT586L" description="GFXMMU LUT entry 586 low" start="+0x2250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT586H" description="GFXMMU LUT entry 586 high" start="+0x2254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT587L" description="GFXMMU LUT entry 587 low" start="+0x2258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT587H" description="GFXMMU LUT entry 587 high" start="+0x225C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT588L" description="GFXMMU LUT entry 588 low" start="+0x2260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT588H" description="GFXMMU LUT entry 588 high" start="+0x2264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT589L" description="GFXMMU LUT entry 589 low" start="+0x2268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT589H" description="GFXMMU LUT entry 589 high" start="+0x226C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT590L" description="GFXMMU LUT entry 590 low" start="+0x2270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT590H" description="GFXMMU LUT entry 590 high" start="+0x2274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT591L" description="GFXMMU LUT entry 591 low" start="+0x2278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT591H" description="GFXMMU LUT entry 591 high" start="+0x227C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT592L" description="GFXMMU LUT entry 592 low" start="+0x2280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT592H" description="GFXMMU LUT entry 592 high" start="+0x2284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT593L" description="GFXMMU LUT entry 593 low" start="+0x2288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT593H" description="GFXMMU LUT entry 593 high" start="+0x228C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT594L" description="GFXMMU LUT entry 594 low" start="+0x2290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT594H" description="GFXMMU LUT entry 594 high" start="+0x2294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT595L" description="GFXMMU LUT entry 595 low" start="+0x2298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT595H" description="GFXMMU LUT entry 595 high" start="+0x229C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT596L" description="GFXMMU LUT entry 596 low" start="+0x22A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT596H" description="GFXMMU LUT entry 596 high" start="+0x22A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT597L" description="GFXMMU LUT entry 597 low" start="+0x22A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT597H" description="GFXMMU LUT entry 597 high" start="+0x22AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT598L" description="GFXMMU LUT entry 598 low" start="+0x22B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT598H" description="GFXMMU LUT entry 598 high" start="+0x22B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT599L" description="GFXMMU LUT entry 599 low" start="+0x22B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT599H" description="GFXMMU LUT entry 599 high" start="+0x22BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT600L" description="GFXMMU LUT entry 600 low" start="+0x22C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT600H" description="GFXMMU LUT entry 600 high" start="+0x22C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT601L" description="GFXMMU LUT entry 601 low" start="+0x22C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT601H" description="GFXMMU LUT entry 601 high" start="+0x22CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT602L" description="GFXMMU LUT entry 602 low" start="+0x22D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT602H" description="GFXMMU LUT entry 602 high" start="+0x22D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT603L" description="GFXMMU LUT entry 603 low" start="+0x22D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT603H" description="GFXMMU LUT entry 603 high" start="+0x22DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT604L" description="GFXMMU LUT entry 604 low" start="+0x22E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT604H" description="GFXMMU LUT entry 604 high" start="+0x22E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT605L" description="GFXMMU LUT entry 605 low" start="+0x22E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT605H" description="GFXMMU LUT entry 605 high" start="+0x22EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT606L" description="GFXMMU LUT entry 606 low" start="+0x22F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT606H" description="GFXMMU LUT entry 606 high" start="+0x22F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT607L" description="GFXMMU LUT entry 607 low" start="+0x22F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT607H" description="GFXMMU LUT entry 607 high" start="+0x22FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT608L" description="GFXMMU LUT entry 608 low" start="+0x2300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT608H" description="GFXMMU LUT entry 608 high" start="+0x2304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT609L" description="GFXMMU LUT entry 609 low" start="+0x2308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT609H" description="GFXMMU LUT entry 609 high" start="+0x230C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT610L" description="GFXMMU LUT entry 610 low" start="+0x2310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT610H" description="GFXMMU LUT entry 610 high" start="+0x2314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT611L" description="GFXMMU LUT entry 611 low" start="+0x2318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT611H" description="GFXMMU LUT entry 611 high" start="+0x231C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT612L" description="GFXMMU LUT entry 612 low" start="+0x2320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT612H" description="GFXMMU LUT entry 612 high" start="+0x2324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT613L" description="GFXMMU LUT entry 613 low" start="+0x2328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT613H" description="GFXMMU LUT entry 613 high" start="+0x232C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT614L" description="GFXMMU LUT entry 614 low" start="+0x2330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT614H" description="GFXMMU LUT entry 614 high" start="+0x2334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT615L" description="GFXMMU LUT entry 615 low" start="+0x2338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT615H" description="GFXMMU LUT entry 615 high" start="+0x233C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT616L" description="GFXMMU LUT entry 616 low" start="+0x2340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT616H" description="GFXMMU LUT entry 616 high" start="+0x2344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT617L" description="GFXMMU LUT entry 617 low" start="+0x2348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT617H" description="GFXMMU LUT entry 617 high" start="+0x234C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT618L" description="GFXMMU LUT entry 618 low" start="+0x2350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT618H" description="GFXMMU LUT entry 618 high" start="+0x2354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT619L" description="GFXMMU LUT entry 619 low" start="+0x2358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT619H" description="GFXMMU LUT entry 619 high" start="+0x235C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT620L" description="GFXMMU LUT entry 620 low" start="+0x2360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT620H" description="GFXMMU LUT entry 620 high" start="+0x2364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT621L" description="GFXMMU LUT entry 621 low" start="+0x2368" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT621H" description="GFXMMU LUT entry 621 high" start="+0x236C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT622L" description="GFXMMU LUT entry 622 low" start="+0x2370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT622H" description="GFXMMU LUT entry 622 high" start="+0x2374" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT623L" description="GFXMMU LUT entry 623 low" start="+0x2378" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT623H" description="GFXMMU LUT entry 623 high" start="+0x237C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT624L" description="GFXMMU LUT entry 624 low" start="+0x2380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT624H" description="GFXMMU LUT entry 624 high" start="+0x2384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT625L" description="GFXMMU LUT entry 625 low" start="+0x2388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT625H" description="GFXMMU LUT entry 625 high" start="+0x238C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT626L" description="GFXMMU LUT entry 626 low" start="+0x2390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT626H" description="GFXMMU LUT entry 626 high" start="+0x2394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT627L" description="GFXMMU LUT entry 627 low" start="+0x2398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT627H" description="GFXMMU LUT entry 627 high" start="+0x239C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT628L" description="GFXMMU LUT entry 628 low" start="+0x23A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT628H" description="GFXMMU LUT entry 628 high" start="+0x23A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT629L" description="GFXMMU LUT entry 629 low" start="+0x23A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT629H" description="GFXMMU LUT entry 629 high" start="+0x23AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT630L" description="GFXMMU LUT entry 630 low" start="+0x23B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT630H" description="GFXMMU LUT entry 630 high" start="+0x23B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT631L" description="GFXMMU LUT entry 631 low" start="+0x23B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT631H" description="GFXMMU LUT entry 631 high" start="+0x23BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT632L" description="GFXMMU LUT entry 632 low" start="+0x23C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT632H" description="GFXMMU LUT entry 632 high" start="+0x23C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT633L" description="GFXMMU LUT entry 633 low" start="+0x23C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT633H" description="GFXMMU LUT entry 633 high" start="+0x23CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT634L" description="GFXMMU LUT entry 634 low" start="+0x23D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT634H" description="GFXMMU LUT entry 634 high" start="+0x23D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT635L" description="GFXMMU LUT entry 635 low" start="+0x23D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT635H" description="GFXMMU LUT entry 635 high" start="+0x23DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT636L" description="GFXMMU LUT entry 636 low" start="+0x23E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT636H" description="GFXMMU LUT entry 636 high" start="+0x23E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT637L" description="GFXMMU LUT entry 637 low" start="+0x23E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT637H" description="GFXMMU LUT entry 637 high" start="+0x23EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT638L" description="GFXMMU LUT entry 638 low" start="+0x23F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT638H" description="GFXMMU LUT entry 638 high" start="+0x23F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT639L" description="GFXMMU LUT entry 639 low" start="+0x23F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT639H" description="GFXMMU LUT entry 639 high" start="+0x23FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT640L" description="GFXMMU LUT entry 640 low" start="+0x2400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT640H" description="GFXMMU LUT entry 640 high" start="+0x2404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT641L" description="GFXMMU LUT entry 641 low" start="+0x2408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT641H" description="GFXMMU LUT entry 641 high" start="+0x240C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT642L" description="GFXMMU LUT entry 642 low" start="+0x2410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT642H" description="GFXMMU LUT entry 642 high" start="+0x2414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT643L" description="GFXMMU LUT entry 643 low" start="+0x2418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT643H" description="GFXMMU LUT entry 643 high" start="+0x241C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT644L" description="GFXMMU LUT entry 644 low" start="+0x2420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT644H" description="GFXMMU LUT entry 644 high" start="+0x2424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT645L" description="GFXMMU LUT entry 645 low" start="+0x2428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT645H" description="GFXMMU LUT entry 645 high" start="+0x242C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT646L" description="GFXMMU LUT entry 646 low" start="+0x2430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT646H" description="GFXMMU LUT entry 646 high" start="+0x2434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT647L" description="GFXMMU LUT entry 647 low" start="+0x2438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT647H" description="GFXMMU LUT entry 647 high" start="+0x243C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT648L" description="GFXMMU LUT entry 648 low" start="+0x2440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT648H" description="GFXMMU LUT entry 648 high" start="+0x2444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT649L" description="GFXMMU LUT entry 649 low" start="+0x2448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT649H" description="GFXMMU LUT entry 649 high" start="+0x244C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT650L" description="GFXMMU LUT entry 650 low" start="+0x2450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT650H" description="GFXMMU LUT entry 650 high" start="+0x2454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT651L" description="GFXMMU LUT entry 651 low" start="+0x2458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT651H" description="GFXMMU LUT entry 651 high" start="+0x245C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT652L" description="GFXMMU LUT entry 652 low" start="+0x2460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT652H" description="GFXMMU LUT entry 652 high" start="+0x2464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT653L" description="GFXMMU LUT entry 653 low" start="+0x2468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT653H" description="GFXMMU LUT entry 653 high" start="+0x246C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT654L" description="GFXMMU LUT entry 654 low" start="+0x2470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT654H" description="GFXMMU LUT entry 654 high" start="+0x2474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT655L" description="GFXMMU LUT entry 655 low" start="+0x2478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT655H" description="GFXMMU LUT entry 655 high" start="+0x247C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT656L" description="GFXMMU LUT entry 656 low" start="+0x2480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT656H" description="GFXMMU LUT entry 656 high" start="+0x2484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT657L" description="GFXMMU LUT entry 657 low" start="+0x2488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT657H" description="GFXMMU LUT entry 657 high" start="+0x248C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT658L" description="GFXMMU LUT entry 658 low" start="+0x2490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT658H" description="GFXMMU LUT entry 658 high" start="+0x2494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT659L" description="GFXMMU LUT entry 659 low" start="+0x2498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT659H" description="GFXMMU LUT entry 659 high" start="+0x249C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT660L" description="GFXMMU LUT entry 660 low" start="+0x24A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT660H" description="GFXMMU LUT entry 660 high" start="+0x24A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT661L" description="GFXMMU LUT entry 661 low" start="+0x24A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT661H" description="GFXMMU LUT entry 661 high" start="+0x24AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT662L" description="GFXMMU LUT entry 662 low" start="+0x24B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT662H" description="GFXMMU LUT entry 662 high" start="+0x24B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT663L" description="GFXMMU LUT entry 663 low" start="+0x24B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT663H" description="GFXMMU LUT entry 663 high" start="+0x24BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT664L" description="GFXMMU LUT entry 664 low" start="+0x24C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT664H" description="GFXMMU LUT entry 664 high" start="+0x24C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT665L" description="GFXMMU LUT entry 665 low" start="+0x24C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT665H" description="GFXMMU LUT entry 665 high" start="+0x24CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT666L" description="GFXMMU LUT entry 666 low" start="+0x24D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT666H" description="GFXMMU LUT entry 666 high" start="+0x24D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT667L" description="GFXMMU LUT entry 667 low" start="+0x24D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT667H" description="GFXMMU LUT entry 667 high" start="+0x24DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT668L" description="GFXMMU LUT entry 668 low" start="+0x24E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT668H" description="GFXMMU LUT entry 668 high" start="+0x24E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT669L" description="GFXMMU LUT entry 669 low" start="+0x24E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT669H" description="GFXMMU LUT entry 669 high" start="+0x24EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT670L" description="GFXMMU LUT entry 670 low" start="+0x24F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT670H" description="GFXMMU LUT entry 670 high" start="+0x24F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT671L" description="GFXMMU LUT entry 671 low" start="+0x24F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT671H" description="GFXMMU LUT entry 671 high" start="+0x24FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT672L" description="GFXMMU LUT entry 672 low" start="+0x2500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT672H" description="GFXMMU LUT entry 672 high" start="+0x2504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT673L" description="GFXMMU LUT entry 673 low" start="+0x2508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT673H" description="GFXMMU LUT entry 673 high" start="+0x250C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT674L" description="GFXMMU LUT entry 674 low" start="+0x2510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT674H" description="GFXMMU LUT entry 674 high" start="+0x2514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT675L" description="GFXMMU LUT entry 675 low" start="+0x2518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT675H" description="GFXMMU LUT entry 675 high" start="+0x251C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT676L" description="GFXMMU LUT entry 676 low" start="+0x2520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT676H" description="GFXMMU LUT entry 676 high" start="+0x2524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT677L" description="GFXMMU LUT entry 677 low" start="+0x2528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT677H" description="GFXMMU LUT entry 677 high" start="+0x252C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT678L" description="GFXMMU LUT entry 678 low" start="+0x2530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT678H" description="GFXMMU LUT entry 678 high" start="+0x2534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT679L" description="GFXMMU LUT entry 679 low" start="+0x2538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT679H" description="GFXMMU LUT entry 679 high" start="+0x253C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT680L" description="GFXMMU LUT entry 680 low" start="+0x2540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT680H" description="GFXMMU LUT entry 680 high" start="+0x2544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT681L" description="GFXMMU LUT entry 681 low" start="+0x2548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT681H" description="GFXMMU LUT entry 681 high" start="+0x254C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT682L" description="GFXMMU LUT entry 682 low" start="+0x2550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT682H" description="GFXMMU LUT entry 682 high" start="+0x2554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT683L" description="GFXMMU LUT entry 683 low" start="+0x2558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT683H" description="GFXMMU LUT entry 683 high" start="+0x255C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT684L" description="GFXMMU LUT entry 684 low" start="+0x2560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT684H" description="GFXMMU LUT entry 684 high" start="+0x2564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT685L" description="GFXMMU LUT entry 685 low" start="+0x2568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT685H" description="GFXMMU LUT entry 685 high" start="+0x256C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT686L" description="GFXMMU LUT entry 686 low" start="+0x2570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT686H" description="GFXMMU LUT entry 686 high" start="+0x2574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT687L" description="GFXMMU LUT entry 687 low" start="+0x2578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT687H" description="GFXMMU LUT entry 687 high" start="+0x257C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT688L" description="GFXMMU LUT entry 688 low" start="+0x2580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT688H" description="GFXMMU LUT entry 688 high" start="+0x2584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT689L" description="GFXMMU LUT entry 689 low" start="+0x2588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT689H" description="GFXMMU LUT entry 689 high" start="+0x258C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT690L" description="GFXMMU LUT entry 690 low" start="+0x2590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT690H" description="GFXMMU LUT entry 690 high" start="+0x2594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT691L" description="GFXMMU LUT entry 691 low" start="+0x2598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT691H" description="GFXMMU LUT entry 691 high" start="+0x259C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT692L" description="GFXMMU LUT entry 692 low" start="+0x25A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT692H" description="GFXMMU LUT entry 692 high" start="+0x25A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT693L" description="GFXMMU LUT entry 693 low" start="+0x25A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT693H" description="GFXMMU LUT entry 693 high" start="+0x25AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT694L" description="GFXMMU LUT entry 694 low" start="+0x25B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT694H" description="GFXMMU LUT entry 694 high" start="+0x25B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT695L" description="GFXMMU LUT entry 695 low" start="+0x25B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT695H" description="GFXMMU LUT entry 695 high" start="+0x25BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT696L" description="GFXMMU LUT entry 696 low" start="+0x25C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT696H" description="GFXMMU LUT entry 696 high" start="+0x25C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT697L" description="GFXMMU LUT entry 697 low" start="+0x25C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT697H" description="GFXMMU LUT entry 697 high" start="+0x25CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT698L" description="GFXMMU LUT entry 698 low" start="+0x25D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT698H" description="GFXMMU LUT entry 698 high" start="+0x25D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT699L" description="GFXMMU LUT entry 699 low" start="+0x25D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT699H" description="GFXMMU LUT entry 699 high" start="+0x25DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT700L" description="GFXMMU LUT entry 700 low" start="+0x25E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT700H" description="GFXMMU LUT entry 700 high" start="+0x25E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT701L" description="GFXMMU LUT entry 701 low" start="+0x25E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT701H" description="GFXMMU LUT entry 701 high" start="+0x25EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT702L" description="GFXMMU LUT entry 702 low" start="+0x25F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT702H" description="GFXMMU LUT entry 702 high" start="+0x25F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT703L" description="GFXMMU LUT entry 703 low" start="+0x25F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT703H" description="GFXMMU LUT entry 703 high" start="+0x25FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT704L" description="GFXMMU LUT entry 704 low" start="+0x2600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT704H" description="GFXMMU LUT entry 704 high" start="+0x2604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT705L" description="GFXMMU LUT entry 705 low" start="+0x2608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT705H" description="GFXMMU LUT entry 705 high" start="+0x260C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT706L" description="GFXMMU LUT entry 706 low" start="+0x2610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT706H" description="GFXMMU LUT entry 706 high" start="+0x2614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT707L" description="GFXMMU LUT entry 707 low" start="+0x2618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT707H" description="GFXMMU LUT entry 707 high" start="+0x261C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT708L" description="GFXMMU LUT entry 708 low" start="+0x2620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT708H" description="GFXMMU LUT entry 708 high" start="+0x2624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT709L" description="GFXMMU LUT entry 709 low" start="+0x2628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT709H" description="GFXMMU LUT entry 709 high" start="+0x262C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT710L" description="GFXMMU LUT entry 710 low" start="+0x2630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT710H" description="GFXMMU LUT entry 710 high" start="+0x2634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT711L" description="GFXMMU LUT entry 711 low" start="+0x2638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT711H" description="GFXMMU LUT entry 711 high" start="+0x263C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT712L" description="GFXMMU LUT entry 712 low" start="+0x2640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT712H" description="GFXMMU LUT entry 712 high" start="+0x2644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT713L" description="GFXMMU LUT entry 713 low" start="+0x2648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT713H" description="GFXMMU LUT entry 713 high" start="+0x264C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT714L" description="GFXMMU LUT entry 714 low" start="+0x2650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT714H" description="GFXMMU LUT entry 714 high" start="+0x2654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT715L" description="GFXMMU LUT entry 715 low" start="+0x2658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT715H" description="GFXMMU LUT entry 715 high" start="+0x265C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT716L" description="GFXMMU LUT entry 716 low" start="+0x2660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT716H" description="GFXMMU LUT entry 716 high" start="+0x2664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT717L" description="GFXMMU LUT entry 717 low" start="+0x2668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT717H" description="GFXMMU LUT entry 717 high" start="+0x266C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT718L" description="GFXMMU LUT entry 718 low" start="+0x2670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT718H" description="GFXMMU LUT entry 718 high" start="+0x2674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT719L" description="GFXMMU LUT entry 719 low" start="+0x2678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT719H" description="GFXMMU LUT entry 719 high" start="+0x267C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT720L" description="GFXMMU LUT entry 720 low" start="+0x2680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT720H" description="GFXMMU LUT entry 720 high" start="+0x2684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT721L" description="GFXMMU LUT entry 721 low" start="+0x2688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT721H" description="GFXMMU LUT entry 721 high" start="+0x268C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT722L" description="GFXMMU LUT entry 722 low" start="+0x2690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT722H" description="GFXMMU LUT entry 722 high" start="+0x2694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT723L" description="GFXMMU LUT entry 723 low" start="+0x2698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT723H" description="GFXMMU LUT entry 723 high" start="+0x269C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT724L" description="GFXMMU LUT entry 724 low" start="+0x26A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT724H" description="GFXMMU LUT entry 724 high" start="+0x26A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT725L" description="GFXMMU LUT entry 725 low" start="+0x26A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT725H" description="GFXMMU LUT entry 725 high" start="+0x26AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT726L" description="GFXMMU LUT entry 726 low" start="+0x26B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT726H" description="GFXMMU LUT entry 726 high" start="+0x26B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT727L" description="GFXMMU LUT entry 727 low" start="+0x26B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT727H" description="GFXMMU LUT entry 727 high" start="+0x26BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT728L" description="GFXMMU LUT entry 728 low" start="+0x26C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT728H" description="GFXMMU LUT entry 728 high" start="+0x26C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT729L" description="GFXMMU LUT entry 729 low" start="+0x26C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT729H" description="GFXMMU LUT entry 729 high" start="+0x26CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT730L" description="GFXMMU LUT entry 730 low" start="+0x26D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT730H" description="GFXMMU LUT entry 730 high" start="+0x26D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT731L" description="GFXMMU LUT entry 731 low" start="+0x26D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT731H" description="GFXMMU LUT entry 731 high" start="+0x26DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT732L" description="GFXMMU LUT entry 732 low" start="+0x26E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT732H" description="GFXMMU LUT entry 732 high" start="+0x26E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT733L" description="GFXMMU LUT entry 733 low" start="+0x26E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT733H" description="GFXMMU LUT entry 733 high" start="+0x26EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT734L" description="GFXMMU LUT entry 734 low" start="+0x26F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT734H" description="GFXMMU LUT entry 734 high" start="+0x26F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT735L" description="GFXMMU LUT entry 735 low" start="+0x26F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT735H" description="GFXMMU LUT entry 735 high" start="+0x26FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT736L" description="GFXMMU LUT entry 736 low" start="+0x2700" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT736H" description="GFXMMU LUT entry 736 high" start="+0x2704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT737L" description="GFXMMU LUT entry 737 low" start="+0x2708" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT737H" description="GFXMMU LUT entry 737 high" start="+0x270C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT738L" description="GFXMMU LUT entry 738 low" start="+0x2710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT738H" description="GFXMMU LUT entry 738 high" start="+0x2714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT739L" description="GFXMMU LUT entry 739 low" start="+0x2718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT739H" description="GFXMMU LUT entry 739 high" start="+0x271C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT740L" description="GFXMMU LUT entry 740 low" start="+0x2720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT740H" description="GFXMMU LUT entry 740 high" start="+0x2724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT741L" description="GFXMMU LUT entry 741 low" start="+0x2728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT741H" description="GFXMMU LUT entry 741 high" start="+0x272C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT742L" description="GFXMMU LUT entry 742 low" start="+0x2730" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT742H" description="GFXMMU LUT entry 742 high" start="+0x2734" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT743L" description="GFXMMU LUT entry 743 low" start="+0x2738" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT743H" description="GFXMMU LUT entry 743 high" start="+0x273C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT744L" description="GFXMMU LUT entry 744 low" start="+0x2740" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT744H" description="GFXMMU LUT entry 744 high" start="+0x2744" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT745L" description="GFXMMU LUT entry 745 low" start="+0x2748" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT745H" description="GFXMMU LUT entry 745 high" start="+0x274C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT746L" description="GFXMMU LUT entry 746 low" start="+0x2750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT746H" description="GFXMMU LUT entry 746 high" start="+0x2754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT747L" description="GFXMMU LUT entry 747 low" start="+0x2758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT747H" description="GFXMMU LUT entry 747 high" start="+0x275C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT748L" description="GFXMMU LUT entry 748 low" start="+0x2760" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT748H" description="GFXMMU LUT entry 748 high" start="+0x2764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT749L" description="GFXMMU LUT entry 749 low" start="+0x2768" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT749H" description="GFXMMU LUT entry 749 high" start="+0x276C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT750L" description="GFXMMU LUT entry 750 low" start="+0x2770" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT750H" description="GFXMMU LUT entry 750 high" start="+0x2774" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT751L" description="GFXMMU LUT entry 751 low" start="+0x2778" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT751H" description="GFXMMU LUT entry 751 high" start="+0x277C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT752L" description="GFXMMU LUT entry 752 low" start="+0x2780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT752H" description="GFXMMU LUT entry 752 high" start="+0x2784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT753L" description="GFXMMU LUT entry 753 low" start="+0x2788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT753H" description="GFXMMU LUT entry 753 high" start="+0x278C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT754L" description="GFXMMU LUT entry 754 low" start="+0x2790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT754H" description="GFXMMU LUT entry 754 high" start="+0x2794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT755L" description="GFXMMU LUT entry 755 low" start="+0x2798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT755H" description="GFXMMU LUT entry 755 high" start="+0x279C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT756L" description="GFXMMU LUT entry 756 low" start="+0x27A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT756H" description="GFXMMU LUT entry 756 high" start="+0x27A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT757L" description="GFXMMU LUT entry 757 low" start="+0x27A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT757H" description="GFXMMU LUT entry 757 high" start="+0x27AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT758L" description="GFXMMU LUT entry 758 low" start="+0x27B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT758H" description="GFXMMU LUT entry 758 high" start="+0x27B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT759L" description="GFXMMU LUT entry 759 low" start="+0x27B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT759H" description="GFXMMU LUT entry 759 high" start="+0x27BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT760L" description="GFXMMU LUT entry 760 low" start="+0x27C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT760H" description="GFXMMU LUT entry 760 high" start="+0x27C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT761L" description="GFXMMU LUT entry 761 low" start="+0x27C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT761H" description="GFXMMU LUT entry 761 high" start="+0x27CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT762L" description="GFXMMU LUT entry 762 low" start="+0x27D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT762H" description="GFXMMU LUT entry 762 high" start="+0x27D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT763L" description="GFXMMU LUT entry 763 low" start="+0x27D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT763H" description="GFXMMU LUT entry 763 high" start="+0x27DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT764L" description="GFXMMU LUT entry 764 low" start="+0x27E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT764H" description="GFXMMU LUT entry 764 high" start="+0x27E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT765L" description="GFXMMU LUT entry 765 low" start="+0x27E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT765H" description="GFXMMU LUT entry 765 high" start="+0x27EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT766L" description="GFXMMU LUT entry 766 low" start="+0x27F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT766H" description="GFXMMU LUT entry 766 high" start="+0x27F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT767L" description="GFXMMU LUT entry 767 low" start="+0x27F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT767H" description="GFXMMU LUT entry 767 high" start="+0x27FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT768L" description="GFXMMU LUT entry 768 low" start="+0x2800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT768H" description="GFXMMU LUT entry 768 high" start="+0x2804" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT769L" description="GFXMMU LUT entry 769 low" start="+0x2808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT769H" description="GFXMMU LUT entry 769 high" start="+0x280C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT770L" description="GFXMMU LUT entry 770 low" start="+0x2810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT770H" description="GFXMMU LUT entry 770 high" start="+0x2814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT771L" description="GFXMMU LUT entry 771 low" start="+0x2818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT771H" description="GFXMMU LUT entry 771 high" start="+0x281C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT772L" description="GFXMMU LUT entry 772 low" start="+0x2820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT772H" description="GFXMMU LUT entry 772 high" start="+0x2824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT773L" description="GFXMMU LUT entry 773 low" start="+0x2828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT773H" description="GFXMMU LUT entry 773 high" start="+0x282C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT774L" description="GFXMMU LUT entry 774 low" start="+0x2830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT774H" description="GFXMMU LUT entry 774 high" start="+0x2834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT775L" description="GFXMMU LUT entry 775 low" start="+0x2838" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT775H" description="GFXMMU LUT entry 775 high" start="+0x283C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT776L" description="GFXMMU LUT entry 776 low" start="+0x2840" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT776H" description="GFXMMU LUT entry 776 high" start="+0x2844" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT777L" description="GFXMMU LUT entry 777 low" start="+0x2848" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT777H" description="GFXMMU LUT entry 777 high" start="+0x284C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT778L" description="GFXMMU LUT entry 778 low" start="+0x2850" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT778H" description="GFXMMU LUT entry 778 high" start="+0x2854" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT779L" description="GFXMMU LUT entry 779 low" start="+0x2858" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT779H" description="GFXMMU LUT entry 779 high" start="+0x285C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT780L" description="GFXMMU LUT entry 780 low" start="+0x2860" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT780H" description="GFXMMU LUT entry 780 high" start="+0x2864" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT781L" description="GFXMMU LUT entry 781 low" start="+0x2868" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT781H" description="GFXMMU LUT entry 781 high" start="+0x286C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT782L" description="GFXMMU LUT entry 782 low" start="+0x2870" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT782H" description="GFXMMU LUT entry 782 high" start="+0x2874" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT783L" description="GFXMMU LUT entry 783 low" start="+0x2878" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT783H" description="GFXMMU LUT entry 783 high" start="+0x287C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT784L" description="GFXMMU LUT entry 784 low" start="+0x2880" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT784H" description="GFXMMU LUT entry 784 high" start="+0x2884" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT785L" description="GFXMMU LUT entry 785 low" start="+0x2888" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT785H" description="GFXMMU LUT entry 785 high" start="+0x288C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT786L" description="GFXMMU LUT entry 786 low" start="+0x2890" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT786H" description="GFXMMU LUT entry 786 high" start="+0x2894" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT787L" description="GFXMMU LUT entry 787 low" start="+0x2898" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT787H" description="GFXMMU LUT entry 787 high" start="+0x289C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT788L" description="GFXMMU LUT entry 788 low" start="+0x28A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT788H" description="GFXMMU LUT entry 788 high" start="+0x28A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT789L" description="GFXMMU LUT entry 789 low" start="+0x28A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT789H" description="GFXMMU LUT entry 789 high" start="+0x28AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT790L" description="GFXMMU LUT entry 790 low" start="+0x28B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT790H" description="GFXMMU LUT entry 790 high" start="+0x28B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT791L" description="GFXMMU LUT entry 791 low" start="+0x28B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT791H" description="GFXMMU LUT entry 791 high" start="+0x28BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT792L" description="GFXMMU LUT entry 792 low" start="+0x28C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT792H" description="GFXMMU LUT entry 792 high" start="+0x28C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT793L" description="GFXMMU LUT entry 793 low" start="+0x28C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT793H" description="GFXMMU LUT entry 793 high" start="+0x28CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT794L" description="GFXMMU LUT entry 794 low" start="+0x28D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT794H" description="GFXMMU LUT entry 794 high" start="+0x28D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT795L" description="GFXMMU LUT entry 795 low" start="+0x28D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT795H" description="GFXMMU LUT entry 795 high" start="+0x28DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT796L" description="GFXMMU LUT entry 796 low" start="+0x28E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT796H" description="GFXMMU LUT entry 796 high" start="+0x28E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT797L" description="GFXMMU LUT entry 797 low" start="+0x28E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT797H" description="GFXMMU LUT entry 797 high" start="+0x28EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT798L" description="GFXMMU LUT entry 798 low" start="+0x28F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT798H" description="GFXMMU LUT entry 798 high" start="+0x28F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT799L" description="GFXMMU LUT entry 799 low" start="+0x28F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT799H" description="GFXMMU LUT entry 799 high" start="+0x28FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT800L" description="GFXMMU LUT entry 800 low" start="+0x2900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT800H" description="GFXMMU LUT entry 800 high" start="+0x2904" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT801L" description="GFXMMU LUT entry 801 low" start="+0x2908" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT801H" description="GFXMMU LUT entry 801 high" start="+0x290C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT802L" description="GFXMMU LUT entry 802 low" start="+0x2910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT802H" description="GFXMMU LUT entry 802 high" start="+0x2914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT803L" description="GFXMMU LUT entry 803 low" start="+0x2918" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT803H" description="GFXMMU LUT entry 803 high" start="+0x291C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT804L" description="GFXMMU LUT entry 804 low" start="+0x2920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT804H" description="GFXMMU LUT entry 804 high" start="+0x2924" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT805L" description="GFXMMU LUT entry 805 low" start="+0x2928" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT805H" description="GFXMMU LUT entry 805 high" start="+0x292C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT806L" description="GFXMMU LUT entry 806 low" start="+0x2930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT806H" description="GFXMMU LUT entry 806 high" start="+0x2934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT807L" description="GFXMMU LUT entry 807 low" start="+0x2938" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT807H" description="GFXMMU LUT entry 807 high" start="+0x293C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT808L" description="GFXMMU LUT entry 808 low" start="+0x2940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT808H" description="GFXMMU LUT entry 808 high" start="+0x2944" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT809L" description="GFXMMU LUT entry 809 low" start="+0x2948" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT809H" description="GFXMMU LUT entry 809 high" start="+0x294C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT810L" description="GFXMMU LUT entry 810 low" start="+0x2950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT810H" description="GFXMMU LUT entry 810 high" start="+0x2954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT811L" description="GFXMMU LUT entry 811 low" start="+0x2958" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT811H" description="GFXMMU LUT entry 811 high" start="+0x295C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT812L" description="GFXMMU LUT entry 812 low" start="+0x2960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT812H" description="GFXMMU LUT entry 812 high" start="+0x2964" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT813L" description="GFXMMU LUT entry 813 low" start="+0x2968" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT813H" description="GFXMMU LUT entry 813 high" start="+0x296C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT814L" description="GFXMMU LUT entry 814 low" start="+0x2970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT814H" description="GFXMMU LUT entry 814 high" start="+0x2974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT815L" description="GFXMMU LUT entry 815 low" start="+0x2978" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT815H" description="GFXMMU LUT entry 815 high" start="+0x297C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT816L" description="GFXMMU LUT entry 816 low" start="+0x2980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT816H" description="GFXMMU LUT entry 816 high" start="+0x2984" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT817L" description="GFXMMU LUT entry 817 low" start="+0x2988" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT817H" description="GFXMMU LUT entry 817 high" start="+0x298C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT818L" description="GFXMMU LUT entry 818 low" start="+0x2990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT818H" description="GFXMMU LUT entry 818 high" start="+0x2994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT819L" description="GFXMMU LUT entry 819 low" start="+0x2998" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT819H" description="GFXMMU LUT entry 819 high" start="+0x299C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT820L" description="GFXMMU LUT entry 820 low" start="+0x29A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT820H" description="GFXMMU LUT entry 820 high" start="+0x29A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT821L" description="GFXMMU LUT entry 821 low" start="+0x29A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT821H" description="GFXMMU LUT entry 821 high" start="+0x29AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT822L" description="GFXMMU LUT entry 822 low" start="+0x29B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT822H" description="GFXMMU LUT entry 822 high" start="+0x29B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT823L" description="GFXMMU LUT entry 823 low" start="+0x29B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT823H" description="GFXMMU LUT entry 823 high" start="+0x29BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT824L" description="GFXMMU LUT entry 824 low" start="+0x29C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT824H" description="GFXMMU LUT entry 824 high" start="+0x29C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT825L" description="GFXMMU LUT entry 825 low" start="+0x29C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT825H" description="GFXMMU LUT entry 825 high" start="+0x29CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT826L" description="GFXMMU LUT entry 826 low" start="+0x29D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT826H" description="GFXMMU LUT entry 826 high" start="+0x29D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT827L" description="GFXMMU LUT entry 827 low" start="+0x29D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT827H" description="GFXMMU LUT entry 827 high" start="+0x29DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT828L" description="GFXMMU LUT entry 828 low" start="+0x29E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT828H" description="GFXMMU LUT entry 828 high" start="+0x29E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT829L" description="GFXMMU LUT entry 829 low" start="+0x29E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT829H" description="GFXMMU LUT entry 829 high" start="+0x29EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT830L" description="GFXMMU LUT entry 830 low" start="+0x29F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT830H" description="GFXMMU LUT entry 830 high" start="+0x29F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT831L" description="GFXMMU LUT entry 831 low" start="+0x29F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT831H" description="GFXMMU LUT entry 831 high" start="+0x29FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT832L" description="GFXMMU LUT entry 832 low" start="+0x2A00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT832H" description="GFXMMU LUT entry 832 high" start="+0x2A04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT833L" description="GFXMMU LUT entry 833 low" start="+0x2A08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT833H" description="GFXMMU LUT entry 833 high" start="+0x2A0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT834L" description="GFXMMU LUT entry 834 low" start="+0x2A10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT834H" description="GFXMMU LUT entry 834 high" start="+0x2A14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT835L" description="GFXMMU LUT entry 835 low" start="+0x2A18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT835H" description="GFXMMU LUT entry 835 high" start="+0x2A1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT836L" description="GFXMMU LUT entry 836 low" start="+0x2A20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT836H" description="GFXMMU LUT entry 836 high" start="+0x2A24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT837L" description="GFXMMU LUT entry 837 low" start="+0x2A28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT837H" description="GFXMMU LUT entry 837 high" start="+0x2A2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT838L" description="GFXMMU LUT entry 838 low" start="+0x2A30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT838H" description="GFXMMU LUT entry 838 high" start="+0x2A34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT839L" description="GFXMMU LUT entry 839 low" start="+0x2A38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT839H" description="GFXMMU LUT entry 839 high" start="+0x2A3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT840L" description="GFXMMU LUT entry 840 low" start="+0x2A40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT840H" description="GFXMMU LUT entry 840 high" start="+0x2A44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT841L" description="GFXMMU LUT entry 841 low" start="+0x2A48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT841H" description="GFXMMU LUT entry 841 high" start="+0x2A4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT842L" description="GFXMMU LUT entry 842 low" start="+0x2A50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT842H" description="GFXMMU LUT entry 842 high" start="+0x2A54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT843L" description="GFXMMU LUT entry 843 low" start="+0x2A58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT843H" description="GFXMMU LUT entry 843 high" start="+0x2A5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT844L" description="GFXMMU LUT entry 844 low" start="+0x2A60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT844H" description="GFXMMU LUT entry 844 high" start="+0x2A64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT845L" description="GFXMMU LUT entry 845 low" start="+0x2A68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT845H" description="GFXMMU LUT entry 845 high" start="+0x2A6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT846L" description="GFXMMU LUT entry 846 low" start="+0x2A70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT846H" description="GFXMMU LUT entry 846 high" start="+0x2A74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT847L" description="GFXMMU LUT entry 847 low" start="+0x2A78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT847H" description="GFXMMU LUT entry 847 high" start="+0x2A7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT848L" description="GFXMMU LUT entry 848 low" start="+0x2A80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT848H" description="GFXMMU LUT entry 848 high" start="+0x2A84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT849L" description="GFXMMU LUT entry 849 low" start="+0x2A88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT849H" description="GFXMMU LUT entry 849 high" start="+0x2A8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT850L" description="GFXMMU LUT entry 850 low" start="+0x2A90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT850H" description="GFXMMU LUT entry 850 high" start="+0x2A94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT851L" description="GFXMMU LUT entry 851 low" start="+0x2A98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT851H" description="GFXMMU LUT entry 851 high" start="+0x2A9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT852L" description="GFXMMU LUT entry 852 low" start="+0x2AA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT852H" description="GFXMMU LUT entry 852 high" start="+0x2AA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT853L" description="GFXMMU LUT entry 853 low" start="+0x2AA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT853H" description="GFXMMU LUT entry 853 high" start="+0x2AAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT854L" description="GFXMMU LUT entry 854 low" start="+0x2AB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT854H" description="GFXMMU LUT entry 854 high" start="+0x2AB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT855L" description="GFXMMU LUT entry 855 low" start="+0x2AB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT855H" description="GFXMMU LUT entry 855 high" start="+0x2ABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT856L" description="GFXMMU LUT entry 856 low" start="+0x2AC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT856H" description="GFXMMU LUT entry 856 high" start="+0x2AC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT857L" description="GFXMMU LUT entry 857 low" start="+0x2AC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT857H" description="GFXMMU LUT entry 857 high" start="+0x2ACC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT858L" description="GFXMMU LUT entry 858 low" start="+0x2AD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT858H" description="GFXMMU LUT entry 858 high" start="+0x2AD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT859L" description="GFXMMU LUT entry 859 low" start="+0x2AD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT859H" description="GFXMMU LUT entry 859 high" start="+0x2ADC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT860L" description="GFXMMU LUT entry 860 low" start="+0x2AE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT860H" description="GFXMMU LUT entry 860 high" start="+0x2AE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT861L" description="GFXMMU LUT entry 861 low" start="+0x2AE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT861H" description="GFXMMU LUT entry 861 high" start="+0x2AEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT862L" description="GFXMMU LUT entry 862 low" start="+0x2AF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT862H" description="GFXMMU LUT entry 862 high" start="+0x2AF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT863L" description="GFXMMU LUT entry 863 low" start="+0x2AF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT863H" description="GFXMMU LUT entry 863 high" start="+0x2AFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT864L" description="GFXMMU LUT entry 864 low" start="+0x2B00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT864H" description="GFXMMU LUT entry 864 high" start="+0x2B04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT865L" description="GFXMMU LUT entry 865 low" start="+0x2B08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT865H" description="GFXMMU LUT entry 865 high" start="+0x2B0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT866L" description="GFXMMU LUT entry 866 low" start="+0x2B10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT866H" description="GFXMMU LUT entry 866 high" start="+0x2B14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT867L" description="GFXMMU LUT entry 867 low" start="+0x2B18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT867H" description="GFXMMU LUT entry 867 high" start="+0x2B1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT868L" description="GFXMMU LUT entry 868 low" start="+0x2B20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT868H" description="GFXMMU LUT entry 868 high" start="+0x2B24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT869L" description="GFXMMU LUT entry 869 low" start="+0x2B28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT869H" description="GFXMMU LUT entry 869 high" start="+0x2B2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT870L" description="GFXMMU LUT entry 870 low" start="+0x2B30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT870H" description="GFXMMU LUT entry 870 high" start="+0x2B34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT871L" description="GFXMMU LUT entry 871 low" start="+0x2B38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT871H" description="GFXMMU LUT entry 871 high" start="+0x2B3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT872L" description="GFXMMU LUT entry 872 low" start="+0x2B40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT872H" description="GFXMMU LUT entry 872 high" start="+0x2B44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT873L" description="GFXMMU LUT entry 873 low" start="+0x2B48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT873H" description="GFXMMU LUT entry 873 high" start="+0x2B4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT874L" description="GFXMMU LUT entry 874 low" start="+0x2B50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT874H" description="GFXMMU LUT entry 874 high" start="+0x2B54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT875L" description="GFXMMU LUT entry 875 low" start="+0x2B58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT875H" description="GFXMMU LUT entry 875 high" start="+0x2B5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT876L" description="GFXMMU LUT entry 876 low" start="+0x2B60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT876H" description="GFXMMU LUT entry 876 high" start="+0x2B64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT877L" description="GFXMMU LUT entry 877 low" start="+0x2B68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT877H" description="GFXMMU LUT entry 877 high" start="+0x2B6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT878L" description="GFXMMU LUT entry 878 low" start="+0x2B70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT878H" description="GFXMMU LUT entry 878 high" start="+0x2B74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT879L" description="GFXMMU LUT entry 879 low" start="+0x2B78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT879H" description="GFXMMU LUT entry 879 high" start="+0x2B7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT880L" description="GFXMMU LUT entry 880 low" start="+0x2B80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT880H" description="GFXMMU LUT entry 880 high" start="+0x2B84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT881L" description="GFXMMU LUT entry 881 low" start="+0x2B88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT881H" description="GFXMMU LUT entry 881 high" start="+0x2B8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT882L" description="GFXMMU LUT entry 882 low" start="+0x2B90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT882H" description="GFXMMU LUT entry 882 high" start="+0x2B94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT883L" description="GFXMMU LUT entry 883 low" start="+0x2B98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT883H" description="GFXMMU LUT entry 883 high" start="+0x2B9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT884L" description="GFXMMU LUT entry 884 low" start="+0x2BA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT884H" description="GFXMMU LUT entry 884 high" start="+0x2BA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT885L" description="GFXMMU LUT entry 885 low" start="+0x2BA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT885H" description="GFXMMU LUT entry 885 high" start="+0x2BAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT886L" description="GFXMMU LUT entry 886 low" start="+0x2BB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT886H" description="GFXMMU LUT entry 886 high" start="+0x2BB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT887L" description="GFXMMU LUT entry 887 low" start="+0x2BB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT887H" description="GFXMMU LUT entry 887 high" start="+0x2BBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT888L" description="GFXMMU LUT entry 888 low" start="+0x2BC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT888H" description="GFXMMU LUT entry 888 high" start="+0x2BC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT889L" description="GFXMMU LUT entry 889 low" start="+0x2BC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT889H" description="GFXMMU LUT entry 889 high" start="+0x2BCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT890L" description="GFXMMU LUT entry 890 low" start="+0x2BD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT890H" description="GFXMMU LUT entry 890 high" start="+0x2BD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT891L" description="GFXMMU LUT entry 891 low" start="+0x2BD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT891H" description="GFXMMU LUT entry 891 high" start="+0x2BDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT892L" description="GFXMMU LUT entry 892 low" start="+0x2BE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT892H" description="GFXMMU LUT entry 892 high" start="+0x2BE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT893L" description="GFXMMU LUT entry 893 low" start="+0x2BE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT893H" description="GFXMMU LUT entry 893 high" start="+0x2BEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT894L" description="GFXMMU LUT entry 894 low" start="+0x2BF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT894H" description="GFXMMU LUT entry 894 high" start="+0x2BF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT895L" description="GFXMMU LUT entry 895 low" start="+0x2BF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT895H" description="GFXMMU LUT entry 895 high" start="+0x2BFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT896L" description="GFXMMU LUT entry 896 low" start="+0x2C00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT896H" description="GFXMMU LUT entry 896 high" start="+0x2C04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT897L" description="GFXMMU LUT entry 897 low" start="+0x2C08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT897H" description="GFXMMU LUT entry 897 high" start="+0x2C0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT898L" description="GFXMMU LUT entry 898 low" start="+0x2C10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT898H" description="GFXMMU LUT entry 898 high" start="+0x2C14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT899L" description="GFXMMU LUT entry 899 low" start="+0x2C18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT899H" description="GFXMMU LUT entry 899 high" start="+0x2C1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT900L" description="GFXMMU LUT entry 900 low" start="+0x2C20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT900H" description="GFXMMU LUT entry 900 high" start="+0x2C24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT901L" description="GFXMMU LUT entry 901 low" start="+0x2C28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT901H" description="GFXMMU LUT entry 901 high" start="+0x2C2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT902L" description="GFXMMU LUT entry 902 low" start="+0x2C30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT902H" description="GFXMMU LUT entry 902 high" start="+0x2C34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT903L" description="GFXMMU LUT entry 903 low" start="+0x2C38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT903H" description="GFXMMU LUT entry 903 high" start="+0x2C3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT904L" description="GFXMMU LUT entry 904 low" start="+0x2C40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT904H" description="GFXMMU LUT entry 904 high" start="+0x2C44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT905L" description="GFXMMU LUT entry 905 low" start="+0x2C48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT905H" description="GFXMMU LUT entry 905 high" start="+0x2C4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT906L" description="GFXMMU LUT entry 906 low" start="+0x2C50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT906H" description="GFXMMU LUT entry 906 high" start="+0x2C54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT907L" description="GFXMMU LUT entry 907 low" start="+0x2C58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT907H" description="GFXMMU LUT entry 907 high" start="+0x2C5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT908L" description="GFXMMU LUT entry 908 low" start="+0x2C60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT908H" description="GFXMMU LUT entry 908 high" start="+0x2C64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT909L" description="GFXMMU LUT entry 909 low" start="+0x2C68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT909H" description="GFXMMU LUT entry 909 high" start="+0x2C6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT910L" description="GFXMMU LUT entry 910 low" start="+0x2C70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT910H" description="GFXMMU LUT entry 910 high" start="+0x2C74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT911L" description="GFXMMU LUT entry 911 low" start="+0x2C78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT911H" description="GFXMMU LUT entry 911 high" start="+0x2C7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT912L" description="GFXMMU LUT entry 912 low" start="+0x2C80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT912H" description="GFXMMU LUT entry 912 high" start="+0x2C84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT913L" description="GFXMMU LUT entry 913 low" start="+0x2C88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT913H" description="GFXMMU LUT entry 913 high" start="+0x2C8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT914L" description="GFXMMU LUT entry 914 low" start="+0x2C90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT914H" description="GFXMMU LUT entry 914 high" start="+0x2C94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT915L" description="GFXMMU LUT entry 915 low" start="+0x2C98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT915H" description="GFXMMU LUT entry 915 high" start="+0x2C9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT916L" description="GFXMMU LUT entry 916 low" start="+0x2CA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT916H" description="GFXMMU LUT entry 916 high" start="+0x2CA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT917L" description="GFXMMU LUT entry 917 low" start="+0x2CA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT917H" description="GFXMMU LUT entry 917 high" start="+0x2CAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT918L" description="GFXMMU LUT entry 918 low" start="+0x2CB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT918H" description="GFXMMU LUT entry 918 high" start="+0x2CB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT919L" description="GFXMMU LUT entry 919 low" start="+0x2CB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT919H" description="GFXMMU LUT entry 919 high" start="+0x2CBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT920L" description="GFXMMU LUT entry 920 low" start="+0x2CC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT920H" description="GFXMMU LUT entry 920 high" start="+0x2CC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT921L" description="GFXMMU LUT entry 921 low" start="+0x2CC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT921H" description="GFXMMU LUT entry 921 high" start="+0x2CCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT922L" description="GFXMMU LUT entry 922 low" start="+0x2CD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT922H" description="GFXMMU LUT entry 922 high" start="+0x2CD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT923L" description="GFXMMU LUT entry 923 low" start="+0x2CD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT923H" description="GFXMMU LUT entry 923 high" start="+0x2CDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT924L" description="GFXMMU LUT entry 924 low" start="+0x2CE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT924H" description="GFXMMU LUT entry 924 high" start="+0x2CE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT925L" description="GFXMMU LUT entry 925 low" start="+0x2CE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT925H" description="GFXMMU LUT entry 925 high" start="+0x2CEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT926L" description="GFXMMU LUT entry 926 low" start="+0x2CF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT926H" description="GFXMMU LUT entry 926 high" start="+0x2CF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT927L" description="GFXMMU LUT entry 927 low" start="+0x2CF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT927H" description="GFXMMU LUT entry 927 high" start="+0x2CFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT928L" description="GFXMMU LUT entry 928 low" start="+0x2D00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT928H" description="GFXMMU LUT entry 928 high" start="+0x2D04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT929L" description="GFXMMU LUT entry 929 low" start="+0x2D08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT929H" description="GFXMMU LUT entry 929 high" start="+0x2D0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT930L" description="GFXMMU LUT entry 930 low" start="+0x2D10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT930H" description="GFXMMU LUT entry 930 high" start="+0x2D14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT931L" description="GFXMMU LUT entry 931 low" start="+0x2D18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT931H" description="GFXMMU LUT entry 931 high" start="+0x2D1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT932L" description="GFXMMU LUT entry 932 low" start="+0x2D20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT932H" description="GFXMMU LUT entry 932 high" start="+0x2D24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT933L" description="GFXMMU LUT entry 933 low" start="+0x2D28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT933H" description="GFXMMU LUT entry 933 high" start="+0x2D2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT934L" description="GFXMMU LUT entry 934 low" start="+0x2D30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT934H" description="GFXMMU LUT entry 934 high" start="+0x2D34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT935L" description="GFXMMU LUT entry 935 low" start="+0x2D38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT935H" description="GFXMMU LUT entry 935 high" start="+0x2D3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT936L" description="GFXMMU LUT entry 936 low" start="+0x2D40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT936H" description="GFXMMU LUT entry 936 high" start="+0x2D44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT937L" description="GFXMMU LUT entry 937 low" start="+0x2D48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT937H" description="GFXMMU LUT entry 937 high" start="+0x2D4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT938L" description="GFXMMU LUT entry 938 low" start="+0x2D50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT938H" description="GFXMMU LUT entry 938 high" start="+0x2D54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT939L" description="GFXMMU LUT entry 939 low" start="+0x2D58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT939H" description="GFXMMU LUT entry 939 high" start="+0x2D5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT940L" description="GFXMMU LUT entry 940 low" start="+0x2D60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT940H" description="GFXMMU LUT entry 940 high" start="+0x2D64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT941L" description="GFXMMU LUT entry 941 low" start="+0x2D68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT941H" description="GFXMMU LUT entry 941 high" start="+0x2D6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT942L" description="GFXMMU LUT entry 942 low" start="+0x2D70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT942H" description="GFXMMU LUT entry 942 high" start="+0x2D74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT943L" description="GFXMMU LUT entry 943 low" start="+0x2D78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT943H" description="GFXMMU LUT entry 943 high" start="+0x2D7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT944L" description="GFXMMU LUT entry 944 low" start="+0x2D80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT944H" description="GFXMMU LUT entry 944 high" start="+0x2D84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT945L" description="GFXMMU LUT entry 945 low" start="+0x2D88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT945H" description="GFXMMU LUT entry 945 high" start="+0x2D8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT946L" description="GFXMMU LUT entry 946 low" start="+0x2D90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT946H" description="GFXMMU LUT entry 946 high" start="+0x2D94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT947L" description="GFXMMU LUT entry 947 low" start="+0x2D98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT947H" description="GFXMMU LUT entry 947 high" start="+0x2D9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT948L" description="GFXMMU LUT entry 948 low" start="+0x2DA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT948H" description="GFXMMU LUT entry 948 high" start="+0x2DA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT949L" description="GFXMMU LUT entry 949 low" start="+0x2DA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT949H" description="GFXMMU LUT entry 949 high" start="+0x2DAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT950L" description="GFXMMU LUT entry 950 low" start="+0x2DB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT950H" description="GFXMMU LUT entry 950 high" start="+0x2DB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT951L" description="GFXMMU LUT entry 951 low" start="+0x2DB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT951H" description="GFXMMU LUT entry 951 high" start="+0x2DBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT952L" description="GFXMMU LUT entry 952 low" start="+0x2DC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT952H" description="GFXMMU LUT entry 952 high" start="+0x2DC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT953L" description="GFXMMU LUT entry 953 low" start="+0x2DC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT953H" description="GFXMMU LUT entry 953 high" start="+0x2DCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT954L" description="GFXMMU LUT entry 954 low" start="+0x2DD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT954H" description="GFXMMU LUT entry 954 high" start="+0x2DD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT955L" description="GFXMMU LUT entry 955 low" start="+0x2DD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT955H" description="GFXMMU LUT entry 955 high" start="+0x2DDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT956L" description="GFXMMU LUT entry 956 low" start="+0x2DE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT956H" description="GFXMMU LUT entry 956 high" start="+0x2DE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT957L" description="GFXMMU LUT entry 957 low" start="+0x2DE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT957H" description="GFXMMU LUT entry 957 high" start="+0x2DEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT958L" description="GFXMMU LUT entry 958 low" start="+0x2DF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT958H" description="GFXMMU LUT entry 958 high" start="+0x2DF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT959L" description="GFXMMU LUT entry 959 low" start="+0x2DF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT959H" description="GFXMMU LUT entry 959 high" start="+0x2DFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT960L" description="GFXMMU LUT entry 960 low" start="+0x2E00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT960H" description="GFXMMU LUT entry 960 high" start="+0x2E04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT961L" description="GFXMMU LUT entry 961 low" start="+0x2E08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT961H" description="GFXMMU LUT entry 961 high" start="+0x2E0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT962L" description="GFXMMU LUT entry 962 low" start="+0x2E10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT962H" description="GFXMMU LUT entry 962 high" start="+0x2E14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT963L" description="GFXMMU LUT entry 963 low" start="+0x2E18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT963H" description="GFXMMU LUT entry 963 high" start="+0x2E1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT964L" description="GFXMMU LUT entry 964 low" start="+0x2E20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT964H" description="GFXMMU LUT entry 964 high" start="+0x2E24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT965L" description="GFXMMU LUT entry 965 low" start="+0x2E28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT965H" description="GFXMMU LUT entry 965 high" start="+0x2E2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT966L" description="GFXMMU LUT entry 966 low" start="+0x2E30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT966H" description="GFXMMU LUT entry 966 high" start="+0x2E34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT967L" description="GFXMMU LUT entry 967 low" start="+0x2E38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT967H" description="GFXMMU LUT entry 967 high" start="+0x2E3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT968L" description="GFXMMU LUT entry 968 low" start="+0x2E40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT968H" description="GFXMMU LUT entry 968 high" start="+0x2E44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT969L" description="GFXMMU LUT entry 969 low" start="+0x2E48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT969H" description="GFXMMU LUT entry 969 high" start="+0x2E4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT970L" description="GFXMMU LUT entry 970 low" start="+0x2E50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT970H" description="GFXMMU LUT entry 970 high" start="+0x2E54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT971L" description="GFXMMU LUT entry 971 low" start="+0x2E58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT971H" description="GFXMMU LUT entry 971 high" start="+0x2E5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT972L" description="GFXMMU LUT entry 972 low" start="+0x2E60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT972H" description="GFXMMU LUT entry 972 high" start="+0x2E64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT973L" description="GFXMMU LUT entry 973 low" start="+0x2E68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT973H" description="GFXMMU LUT entry 973 high" start="+0x2E6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT974L" description="GFXMMU LUT entry 974 low" start="+0x2E70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT974H" description="GFXMMU LUT entry 974 high" start="+0x2E74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT975L" description="GFXMMU LUT entry 975 low" start="+0x2E78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT975H" description="GFXMMU LUT entry 975 high" start="+0x2E7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT976L" description="GFXMMU LUT entry 976 low" start="+0x2E80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT976H" description="GFXMMU LUT entry 976 high" start="+0x2E84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT977L" description="GFXMMU LUT entry 977 low" start="+0x2E88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT977H" description="GFXMMU LUT entry 977 high" start="+0x2E8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT978L" description="GFXMMU LUT entry 978 low" start="+0x2E90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT978H" description="GFXMMU LUT entry 978 high" start="+0x2E94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT979L" description="GFXMMU LUT entry 979 low" start="+0x2E98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT979H" description="GFXMMU LUT entry 979 high" start="+0x2E9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT980L" description="GFXMMU LUT entry 980 low" start="+0x2EA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT980H" description="GFXMMU LUT entry 980 high" start="+0x2EA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT981L" description="GFXMMU LUT entry 981 low" start="+0x2EA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT981H" description="GFXMMU LUT entry 981 high" start="+0x2EAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT982L" description="GFXMMU LUT entry 982 low" start="+0x2EB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT982H" description="GFXMMU LUT entry 982 high" start="+0x2EB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT983L" description="GFXMMU LUT entry 983 low" start="+0x2EB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT983H" description="GFXMMU LUT entry 983 high" start="+0x2EBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT984L" description="GFXMMU LUT entry 984 low" start="+0x2EC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT984H" description="GFXMMU LUT entry 984 high" start="+0x2EC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT985L" description="GFXMMU LUT entry 985 low" start="+0x2EC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT985H" description="GFXMMU LUT entry 985 high" start="+0x2ECC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT986L" description="GFXMMU LUT entry 986 low" start="+0x2ED0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT986H" description="GFXMMU LUT entry 986 high" start="+0x2ED4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT987L" description="GFXMMU LUT entry 987 low" start="+0x2ED8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT987H" description="GFXMMU LUT entry 987 high" start="+0x2EDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT988L" description="GFXMMU LUT entry 988 low" start="+0x2EE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT988H" description="GFXMMU LUT entry 988 high" start="+0x2EE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT989L" description="GFXMMU LUT entry 989 low" start="+0x2EE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT989H" description="GFXMMU LUT entry 989 high" start="+0x2EEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT990L" description="GFXMMU LUT entry 990 low" start="+0x2EF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT990H" description="GFXMMU LUT entry 990 high" start="+0x2EF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT991L" description="GFXMMU LUT entry 991 low" start="+0x2EF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT991H" description="GFXMMU LUT entry 991 high" start="+0x2EFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT992L" description="GFXMMU LUT entry 992 low" start="+0x2F00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT992H" description="GFXMMU LUT entry 992 high" start="+0x2F04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT993L" description="GFXMMU LUT entry 993 low" start="+0x2F08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT993H" description="GFXMMU LUT entry 993 high" start="+0x2F0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT994L" description="GFXMMU LUT entry 994 low" start="+0x2F10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT994H" description="GFXMMU LUT entry 994 high" start="+0x2F14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT995L" description="GFXMMU LUT entry 995 low" start="+0x2F18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT995H" description="GFXMMU LUT entry 995 high" start="+0x2F1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT996L" description="GFXMMU LUT entry 996 low" start="+0x2F20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT996H" description="GFXMMU LUT entry 996 high" start="+0x2F24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT997L" description="GFXMMU LUT entry 997 low" start="+0x2F28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT997H" description="GFXMMU LUT entry 997 high" start="+0x2F2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT998L" description="GFXMMU LUT entry 998 low" start="+0x2F30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT998H" description="GFXMMU LUT entry 998 high" start="+0x2F34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT999L" description="GFXMMU LUT entry 999 low" start="+0x2F38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT999H" description="GFXMMU LUT entry 999 high" start="+0x2F3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1000L" description="GFXMMU LUT entry 1000 low" start="+0x2F40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1000H" description="GFXMMU LUT entry 1000 high" start="+0x2F44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1001L" description="GFXMMU LUT entry 1001 low" start="+0x2F48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1001H" description="GFXMMU LUT entry 1001 high" start="+0x2F4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1002L" description="GFXMMU LUT entry 1002 low" start="+0x2F50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1002H" description="GFXMMU LUT entry 1002 high" start="+0x2F54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1003L" description="GFXMMU LUT entry 1003 low" start="+0x2F58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1003H" description="GFXMMU LUT entry 1003 high" start="+0x2F5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1004L" description="GFXMMU LUT entry 1004 low" start="+0x2F60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1004H" description="GFXMMU LUT entry 1004 high" start="+0x2F64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1005L" description="GFXMMU LUT entry 1005 low" start="+0x2F68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1005H" description="GFXMMU LUT entry 1005 high" start="+0x2F6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1006L" description="GFXMMU LUT entry 1006 low" start="+0x2F70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1006H" description="GFXMMU LUT entry 1006 high" start="+0x2F74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1007L" description="GFXMMU LUT entry 1007 low" start="+0x2F78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1007H" description="GFXMMU LUT entry 1007 high" start="+0x2F7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1008L" description="GFXMMU LUT entry 1008 low" start="+0x2F80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1008H" description="GFXMMU LUT entry 1008 high" start="+0x2F84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1009L" description="GFXMMU LUT entry 1009 low" start="+0x2F88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1009H" description="GFXMMU LUT entry 1009 high" start="+0x2F8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1010L" description="GFXMMU LUT entry 1010 low" start="+0x2F90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1010H" description="GFXMMU LUT entry 1010 high" start="+0x2F94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1011L" description="GFXMMU LUT entry 1011 low" start="+0x2F98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1011H" description="GFXMMU LUT entry 1011 high" start="+0x2F9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1012L" description="GFXMMU LUT entry 1012 low" start="+0x2FA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1012H" description="GFXMMU LUT entry 1012 high" start="+0x2FA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1013L" description="GFXMMU LUT entry 1013 low" start="+0x2FA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1013H" description="GFXMMU LUT entry 1013 high" start="+0x2FAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1014L" description="GFXMMU LUT entry 1014 low" start="+0x2FB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1014H" description="GFXMMU LUT entry 1014 high" start="+0x2FB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1015L" description="GFXMMU LUT entry 1015 low" start="+0x2FB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1015H" description="GFXMMU LUT entry 1015 high" start="+0x2FBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1016L" description="GFXMMU LUT entry 1016 low" start="+0x2FC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1016H" description="GFXMMU LUT entry 1016 high" start="+0x2FC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1017L" description="GFXMMU LUT entry 1017 low" start="+0x2FC8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1017H" description="GFXMMU LUT entry 1017 high" start="+0x2FCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1018L" description="GFXMMU LUT entry 1018 low" start="+0x2FD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1018H" description="GFXMMU LUT entry 1018 high" start="+0x2FD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1019L" description="GFXMMU LUT entry 1019 low" start="+0x2FD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1019H" description="GFXMMU LUT entry 1019 high" start="+0x2FDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1020L" description="GFXMMU LUT entry 1020 low" start="+0x2FE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1020H" description="GFXMMU LUT entry 1020 high" start="+0x2FE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1021L" description="GFXMMU LUT entry 1021 low" start="+0x2FE8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1021H" description="GFXMMU LUT entry 1021 high" start="+0x2FEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1022L" description="GFXMMU LUT entry 1022 low" start="+0x2FF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1022H" description="GFXMMU LUT entry 1022 high" start="+0x2FF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1023L" description="GFXMMU LUT entry 1023 low" start="+0x2FF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Line is disabled (no MMU evaluation is performed)" start="0x0" />
+        <Enum name="B_0x1" description="Line is enabled (MMU evaluation is performed)" start="0x1" />
+      </BitField>
+      <BitField name="FVB" description="First valid block" start="8" size="8" access="Read/Write" />
+      <BitField name="LVB" description="Last valid block" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="GFXMMU_LUT1023H" description="GFXMMU LUT entry 1023 high" start="+0x2FFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset" start="0" size="18" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GFXTIM" description="Graphic timer" start="0x48004000">
+    <Register name="GFXTIM_CR" description="GFXTIM configuration register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TES" description="tearing source" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TE input pad selected" start="0x0" />
+        <Enum name="B_0x1" description="gfxtim_ite selected" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC input selected by SYNCS[1:0]" start="0x2" />
+        <Enum name="B_0x3" description="VSYNC input selected by SYNCS[1:0]" start="0x3" />
+      </BitField>
+      <BitField name="TEPOL" description="tearing--effect polarity" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tearing effect active on rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tearing effect active on falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SYNCS" description="synchronization source" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="gfxtim_hsync[0] and gfxtim_vsync[0] selected" start="0x0" />
+        <Enum name="B_0x1" description="gfxtim_hsync[1] and gfxtim_vsync[1] selected" start="0x1" />
+        <Enum name="B_0x2" description="gfxtim_hsync[2] and gfxtim_vsync[2] selected" start="0x2" />
+        <Enum name="B_0x3" description="gfxtim_hsync[3] and gfxtim_vsync[3] selected" start="0x3" />
+      </BitField>
+      <BitField name="FCCOE" description="frame-clock calibration output enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="frame-clock output disabled" start="0x0" />
+        <Enum name="B_0x1" description="frame-clock output enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCCOE" description="line-clock calibration output enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line-clock output disabled" start="0x0" />
+        <Enum name="B_0x1" description="line-clock output enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_CGCR" description="GFXTIM clock generator configuration register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCS" description="line clock source" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter underflow" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="LCCCS" description="line clock counter clock source" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="system clock selected" start="0x1" />
+      </BitField>
+      <BitField name="LCCFR" description="line clock counter force reload" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="line clock counter reload forced" start="0x1" />
+      </BitField>
+      <BitField name="LCCHRS" description="line clock counter hardware reload source" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no hardware reload" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCS" description="frame clock source" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter underflow" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCCCS" description="frame clock counter clock source" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="frame clock counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="line clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCCFR" description="frame clock counter force reload" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter reload forced" start="0x1" />
+      </BitField>
+      <BitField name="FCCHRS" description="frame- -clock counter hardware reload source" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no hardware reload" start="0x0" />
+        <Enum name="B_0x1" description="line- -clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TCR" description="GFXTIM timers configuration register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCEN" description="absolute frame counter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FAFCR" description="force absolute frame counter reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter reset forced" start="0x1" />
+      </BitField>
+      <BitField name="ALCEN" description="absolute line counter enable" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FALCR" description="force absolute line counter reset" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter reset forced" start="0x1" />
+      </BitField>
+      <BitField name="RFC1EN" description="relative frame counter 1 enable" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1CM" description="relative frame counter 1 continuous mode" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 1 is one shot." start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 is in continuous mode." start="0x1" />
+      </BitField>
+      <BitField name="FRFC1R" description="force relative frame counter 1 reload" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 reload forced" start="0x1" />
+      </BitField>
+      <BitField name="RFC2EN" description="relative frame counter 2 enable" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2CM" description="relative frame counter 2 continuous mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 2 is one shot." start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 is in continuous mode." start="0x1" />
+      </BitField>
+      <BitField name="FRFC2R" description="force relative frame counter 2 reload" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 reload forced" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TDR" description="GFXTIM timers disable register" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCDIS" description="absolute frame counter disable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCDIS" description="absolute line counter disable" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1DIS" description="relative frame counter 1 disable" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 disabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2DIS" description="relative frame counter 2 disable" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_EVCR" description="GFXTIM events control register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EV1EN" description="event 1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 1 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 1 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV2EN" description="event 2 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 2 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 2 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV3EN" description="event 3 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 3 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 3 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV4EN" description="event 4 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 4 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 4 generation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_EVSR" description="GFXTIM events selection register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LES1" description="line-event selection 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES1" description="frame-event selection 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES2" description="line-event selection 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES2" description="frame-event selection 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES3" description="line-event selection 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES3" description="frame-event selection 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES4" description="line-event selection 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES4" description="frame-event selection 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_WDGTCR" description="GFXTIM watchdog timer configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDGEN" description="watchdog enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGDIS" description="watchdog disable" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog disabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGS" description="watchdog status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="graphic watchdog disabled" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGHRC" description="watchdog hardware reload configuration" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog hardware reload disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog reloaded a rising edge of gfxtim_wrld" start="0x1" />
+        <Enum name="B_0x2" description="watchdog reloaded a falling edge of gfxtim_wrld" start="0x2" />
+      </BitField>
+      <BitField name="WDGCS" description="watchdog clock source" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="line clock" start="0x0" />
+        <Enum name="B_0x1" description="frame clock" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+        <Enum name="B_0x8" description="event 1" start="0x8" />
+        <Enum name="B_0x9" description="event 2" start="0x9" />
+        <Enum name="B_0xA" description="event 3" start="0xA" />
+        <Enum name="B_0xB" description="event 4" start="0xB" />
+      </BitField>
+      <BitField name="FWDGR" description="force watchdog reload" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog reload forced" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_ISR" description="GFXTIM interrupt status register" start="+0x0030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCOF" description="absolute frame counter overflow flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overflow occurred on the absolute frame counter." start="0x0" />
+        <Enum name="B_0x1" description="a overflow on the absolute frame counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCOF" description="absolute line counter overflow flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overflow occurred on the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a overflow on the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="TEF" description="tearing-effect flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no tearing effect occurred." start="0x0" />
+        <Enum name="B_0x1" description="a tearing effect occurred." start="0x1" />
+      </BitField>
+      <BitField name="AFCC1F" description="absolute frame counter compare 1 flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 1 of the absolute frame counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 1 of the absolute frame counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCC1F" description="absolute line counter compare 1 flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 1 of the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 1 of the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCC2F" description="absolute line counter compare 2 flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 2 of the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 2 of the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="RFC1RF" description="relative frame counter 1 reload flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reload occurred on relative frame counter 1." start="0x0" />
+        <Enum name="B_0x1" description="a reload on relative frame counter 1 occurred." start="0x1" />
+      </BitField>
+      <BitField name="RFC2RF" description="relative frame counter 2 reload flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reload occurred on relative frame counter 2." start="0x0" />
+        <Enum name="B_0x1" description="a reload on relative frame counter 2 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV1F" description="event 1 flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No complex event 1 occurred." start="0x0" />
+        <Enum name="B_0x1" description="Complex event 1 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV2F" description="event 2 flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 2 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 2 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV3F" description="event 3 flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 3 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 3 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV4F" description="event 4 flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 4 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 4 occurred." start="0x1" />
+      </BitField>
+      <BitField name="WDGAF" description="watchdog alarm flag" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no graphic watchdog alarm occurred." start="0x0" />
+        <Enum name="B_0x1" description="a graphic watchdog alarm occurred." start="0x1" />
+      </BitField>
+      <BitField name="WDGPF" description="watchdog pre-alarm flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no graphic watchdog pre-alarm occurred." start="0x0" />
+        <Enum name="B_0x1" description="a graphic watchdog pre-alarm occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_ICR" description="GFXTIM interrupt clear register" start="+0x0034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAFCOF" description="clear absolute frame counter overflow flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="AFCOF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCOF" description="clear absolute line counter overflow flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCOF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTEF" description="clear tearing-effect flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="TEF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CAFCC1F" description="clear absolute frame counter compare 1 flag" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="AFCC1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCC1F" description="clear absolute line counter compare 1 flag" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCC1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCC2F" description="clear absolute line counter compare 2 flag" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCC2F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CRFC1RF" description="clear relative frame counter 1 reload flag" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="RFC1RF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CRFC2RF" description="clear relative frame counter 2 reload flag" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="RFC2RF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV1F" description="clear event 1 flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV2F" description="clear event 2 flag" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV2F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV3F" description="clear event 3 flag" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV3F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV4F" description="clear event 4 flag" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV4F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CWDGAF" description="clear watchdog alarm flag" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="WDGAF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CWDGPF" description="clear watchdog pre-alarm flag" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="WDGPF cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_IER" description="GFXTIM interrupt enable register" start="+0x0038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCOIE" description="absolute frame counter overflow interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute frame counter overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCOIE" description="absolute line counter overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEIE" description="tearing-effect interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tearing-effect interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="tearing-effect interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFCC1IE" description="absolute frame counter compare 1 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute frame counter compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCC1IE" description="absolute line counter compare 1 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCC2IE" description="absolute line counter compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1RIE" description="relative frame counter 1 reload interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 1 reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2RIE" description="relative frame counter 2 reload interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 2 reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV1IE" description="event 1 interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV2IE" description="event 2 interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV3IE" description="event 3 interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV4IE" description="event 4 interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGAIE" description="watchdog alarm interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog alarm interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog alarm interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGPIE" description="watchdog pre-alarm interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog pre-alarm interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog pre-alarm interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TSR" description="GFXTIM timers status register" start="+0x003C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCS" description="absolute frame counter status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="absolute frame counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCS" description="absolute line counter status" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="absolute line counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1S" description="relative frame counter 1 status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="relative frame counter 1 disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2S" description="relative frame counter 2 status" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="relative frame counter 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_LCCRR" description="GFXTIM line clock counter reload register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_FCCRR" description="GFXTIM frame clock counter reload register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ATR" description="GFXTIM absolute time register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="ReadOnly" />
+      <BitField name="FRAME" description="fame number" start="12" size="20" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_AFCR" description="GFXTIM absolute frame counter register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCR" description="GFXTIM absolute line counter register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_AFCC1R" description="GFXTIM absolute frame counter compare 1 register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCC1R" description="GFXTIM absolute line counter compare 1 register" start="+0x0070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCC2R" description="GFXTIM absolute line counter compare 2 register" start="+0x0074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_RFC1R" description="GFXTIM relative frame counter 1 register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_RFC1RR" description="GFXTIM relative frame counter 1 reload register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_RFC2R" description="GFXTIM relative frame counter 2 register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_RFC2RR" description="GFXTIM relative frame counter 2 reload register" start="+0x008C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_WDGCR" description="GFXTIM watchdog counter register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VALUE" description="value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_WDGRR" description="GFXTIM watchdog reload register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_WDGPAR" description="GFXTIM watchdog pre-alarm register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PREALARM" description="pre-alarm value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GFXTIM_S" description="Graphic timer" start="0x58004000">
+    <Register name="GFXTIM_CR" description="GFXTIM configuration register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TES" description="tearing source" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TE input pad selected" start="0x0" />
+        <Enum name="B_0x1" description="gfxtim_ite selected" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC input selected by SYNCS[1:0]" start="0x2" />
+        <Enum name="B_0x3" description="VSYNC input selected by SYNCS[1:0]" start="0x3" />
+      </BitField>
+      <BitField name="TEPOL" description="tearing--effect polarity" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tearing effect active on rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tearing effect active on falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SYNCS" description="synchronization source" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="gfxtim_hsync[0] and gfxtim_vsync[0] selected" start="0x0" />
+        <Enum name="B_0x1" description="gfxtim_hsync[1] and gfxtim_vsync[1] selected" start="0x1" />
+        <Enum name="B_0x2" description="gfxtim_hsync[2] and gfxtim_vsync[2] selected" start="0x2" />
+        <Enum name="B_0x3" description="gfxtim_hsync[3] and gfxtim_vsync[3] selected" start="0x3" />
+      </BitField>
+      <BitField name="FCCOE" description="frame-clock calibration output enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="frame-clock output disabled" start="0x0" />
+        <Enum name="B_0x1" description="frame-clock output enabled" start="0x1" />
+      </BitField>
+      <BitField name="LCCOE" description="line-clock calibration output enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line-clock output disabled" start="0x0" />
+        <Enum name="B_0x1" description="line-clock output enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_CGCR" description="GFXTIM clock generator configuration register" start="+0x0004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCS" description="line clock source" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter underflow" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="LCCCS" description="line clock counter clock source" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="system clock selected" start="0x1" />
+      </BitField>
+      <BitField name="LCCFR" description="line clock counter force reload" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="line clock counter reload forced" start="0x1" />
+      </BitField>
+      <BitField name="LCCHRS" description="line clock counter hardware reload source" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no hardware reload" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCS" description="frame clock source" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="line clock counter underflow" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCCCS" description="frame clock counter clock source" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="frame clock counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="line clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+      <BitField name="FCCFR" description="frame clock counter force reload" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="frame clock counter reload forced" start="0x1" />
+      </BitField>
+      <BitField name="FCCHRS" description="frame- -clock counter hardware reload source" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no hardware reload" start="0x0" />
+        <Enum name="B_0x1" description="line- -clock counter underflow" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TCR" description="GFXTIM timers configuration register" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCEN" description="absolute frame counter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FAFCR" description="force absolute frame counter reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter reset forced" start="0x1" />
+      </BitField>
+      <BitField name="ALCEN" description="absolute line counter enable" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FALCR" description="force absolute line counter reset" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter reset forced" start="0x1" />
+      </BitField>
+      <BitField name="RFC1EN" description="relative frame counter 1 enable" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1CM" description="relative frame counter 1 continuous mode" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 1 is one shot." start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 is in continuous mode." start="0x1" />
+      </BitField>
+      <BitField name="FRFC1R" description="force relative frame counter 1 reload" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 reload forced" start="0x1" />
+      </BitField>
+      <BitField name="RFC2EN" description="relative frame counter 2 enable" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2CM" description="relative frame counter 2 continuous mode" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 2 is one shot." start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 is in continuous mode." start="0x1" />
+      </BitField>
+      <BitField name="FRFC2R" description="force relative frame counter 2 reload" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 reload forced" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TDR" description="GFXTIM timers disable register" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCDIS" description="absolute frame counter disable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCDIS" description="absolute line counter disable" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter disabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1DIS" description="relative frame counter 1 disable" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 disabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2DIS" description="relative frame counter 2 disable" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_EVCR" description="GFXTIM events control register" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EV1EN" description="event 1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 1 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 1 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV2EN" description="event 2 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 2 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 2 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV3EN" description="event 3 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 3 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 3 generation enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV4EN" description="event 4 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 4 generation disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 4 generation enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_EVSR" description="GFXTIM events selection register" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LES1" description="line-event selection 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES1" description="frame-event selection 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES2" description="line-event selection 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES2" description="frame-event selection 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES3" description="line-event selection 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES3" description="frame-event selection 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+      <BitField name="LES4" description="line-event selection 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no line event" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="tearing effect" start="0x2" />
+        <Enum name="B_0x4" description="absolute line counter 1 compare" start="0x4" />
+        <Enum name="B_0x5" description="absolute line counter 2 compare" start="0x5" />
+      </BitField>
+      <BitField name="FES4" description="frame-event selection 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no frame event" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow" start="0x1" />
+        <Enum name="B_0x2" description="absolute frame counter compare" start="0x2" />
+        <Enum name="B_0x4" description="relative frame counter 1 reload" start="0x4" />
+        <Enum name="B_0x5" description="relative frame counter 2 reload" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_WDGTCR" description="GFXTIM watchdog timer configuration register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDGEN" description="watchdog enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGDIS" description="watchdog disable" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog disabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGS" description="watchdog status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="graphic watchdog disabled" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGHRC" description="watchdog hardware reload configuration" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog hardware reload disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog reloaded a rising edge of gfxtim_wrld" start="0x1" />
+        <Enum name="B_0x2" description="watchdog reloaded a falling edge of gfxtim_wrld" start="0x2" />
+      </BitField>
+      <BitField name="WDGCS" description="watchdog clock source" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="line clock" start="0x0" />
+        <Enum name="B_0x1" description="frame clock" start="0x1" />
+        <Enum name="B_0x2" description="HSYNC rising edge" start="0x2" />
+        <Enum name="B_0x3" description="HSYNC falling edge" start="0x3" />
+        <Enum name="B_0x4" description="VSYNC rising edge" start="0x4" />
+        <Enum name="B_0x5" description="VSYNC falling edge" start="0x5" />
+        <Enum name="B_0x6" description="TE rising edge" start="0x6" />
+        <Enum name="B_0x7" description="TE falling edge" start="0x7" />
+        <Enum name="B_0x8" description="event 1" start="0x8" />
+        <Enum name="B_0x9" description="event 2" start="0x9" />
+        <Enum name="B_0xA" description="event 3" start="0xA" />
+        <Enum name="B_0xB" description="event 4" start="0xB" />
+      </BitField>
+      <BitField name="FWDGR" description="force watchdog reload" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="graphic watchdog reload forced" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_ISR" description="GFXTIM interrupt status register" start="+0x0030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCOF" description="absolute frame counter overflow flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overflow occurred on the absolute frame counter." start="0x0" />
+        <Enum name="B_0x1" description="a overflow on the absolute frame counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCOF" description="absolute line counter overflow flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overflow occurred on the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a overflow on the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="TEF" description="tearing-effect flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no tearing effect occurred." start="0x0" />
+        <Enum name="B_0x1" description="a tearing effect occurred." start="0x1" />
+      </BitField>
+      <BitField name="AFCC1F" description="absolute frame counter compare 1 flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 1 of the absolute frame counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 1 of the absolute frame counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCC1F" description="absolute line counter compare 1 flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 1 of the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 1 of the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="ALCC2F" description="absolute line counter compare 2 flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no match occurred on compare 2 of the absolute line counter." start="0x0" />
+        <Enum name="B_0x1" description="a match on compare 2 of the absolute line counter occurred." start="0x1" />
+      </BitField>
+      <BitField name="RFC1RF" description="relative frame counter 1 reload flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reload occurred on relative frame counter 1." start="0x0" />
+        <Enum name="B_0x1" description="a reload on relative frame counter 1 occurred." start="0x1" />
+      </BitField>
+      <BitField name="RFC2RF" description="relative frame counter 2 reload flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reload occurred on relative frame counter 2." start="0x0" />
+        <Enum name="B_0x1" description="a reload on relative frame counter 2 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV1F" description="event 1 flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No complex event 1 occurred." start="0x0" />
+        <Enum name="B_0x1" description="Complex event 1 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV2F" description="event 2 flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 2 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 2 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV3F" description="event 3 flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 3 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 3 occurred." start="0x1" />
+      </BitField>
+      <BitField name="EV4F" description="event 4 flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no complex event 4 occurred." start="0x0" />
+        <Enum name="B_0x1" description="a complex event 4 occurred." start="0x1" />
+      </BitField>
+      <BitField name="WDGAF" description="watchdog alarm flag" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no graphic watchdog alarm occurred." start="0x0" />
+        <Enum name="B_0x1" description="a graphic watchdog alarm occurred." start="0x1" />
+      </BitField>
+      <BitField name="WDGPF" description="watchdog pre-alarm flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no graphic watchdog pre-alarm occurred." start="0x0" />
+        <Enum name="B_0x1" description="a graphic watchdog pre-alarm occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_ICR" description="GFXTIM interrupt clear register" start="+0x0034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAFCOF" description="clear absolute frame counter overflow flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="AFCOF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCOF" description="clear absolute line counter overflow flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCOF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTEF" description="clear tearing-effect flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="TEF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CAFCC1F" description="clear absolute frame counter compare 1 flag" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="AFCC1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCC1F" description="clear absolute line counter compare 1 flag" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCC1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CALCC2F" description="clear absolute line counter compare 2 flag" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="ALCC2F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CRFC1RF" description="clear relative frame counter 1 reload flag" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="RFC1RF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CRFC2RF" description="clear relative frame counter 2 reload flag" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="RFC2RF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV1F" description="clear event 1 flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV1F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV2F" description="clear event 2 flag" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV2F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV3F" description="clear event 3 flag" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV3F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CEV4F" description="clear event 4 flag" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="EV4F cleared" start="0x1" />
+      </BitField>
+      <BitField name="CWDGAF" description="clear watchdog alarm flag" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="WDGAF cleared" start="0x1" />
+      </BitField>
+      <BitField name="CWDGPF" description="clear watchdog pre-alarm flag" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="WDGPF cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_IER" description="GFXTIM interrupt enable register" start="+0x0038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCOIE" description="absolute frame counter overflow interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute frame counter overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCOIE" description="absolute line counter overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TEIE" description="tearing-effect interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tearing-effect interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="tearing-effect interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFCC1IE" description="absolute frame counter compare 1 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute frame counter compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCC1IE" description="absolute line counter compare 1 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCC2IE" description="absolute line counter compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="absolute line counter compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1RIE" description="relative frame counter 1 reload interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 1 reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2RIE" description="relative frame counter 2 reload interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="relative frame counter 2 reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV1IE" description="event 1 interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV2IE" description="event 2 interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV3IE" description="event 3 interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EV4IE" description="event 4 interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="event 4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="event 4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGAIE" description="watchdog alarm interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog alarm interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog alarm interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WDGPIE" description="watchdog pre-alarm interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="watchdog pre-alarm interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="watchdog pre-alarm interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_TSR" description="GFXTIM timers status register" start="+0x003C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCS" description="absolute frame counter status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="absolute frame counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute frame counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALCS" description="absolute line counter status" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="absolute line counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="absolute line counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC1S" description="relative frame counter 1 status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="relative frame counter 1 disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 1 enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFC2S" description="relative frame counter 2 status" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="relative frame counter 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="relative frame counter 2 enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GFXTIM_LCCRR" description="GFXTIM line clock counter reload register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="22" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_FCCRR" description="GFXTIM frame clock counter reload register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ATR" description="GFXTIM absolute time register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="ReadOnly" />
+      <BitField name="FRAME" description="fame number" start="12" size="20" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_AFCR" description="GFXTIM absolute frame counter register" start="+0x0054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCR" description="GFXTIM absolute line counter register" start="+0x0058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_AFCC1R" description="GFXTIM absolute frame counter compare 1 register" start="+0x0060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCC1R" description="GFXTIM absolute line counter compare 1 register" start="+0x0070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_ALCC2R" description="GFXTIM absolute line counter compare 2 register" start="+0x0074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE" description="line number" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_RFC1R" description="GFXTIM relative frame counter 1 register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_RFC1RR" description="GFXTIM relative frame counter 1 reload register" start="+0x0084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_RFC2R" description="GFXTIM relative frame counter 2 register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame number" start="0" size="12" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_RFC2RR" description="GFXTIM relative frame counter 2 reload register" start="+0x008C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRAME" description="frame reload value" start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_WDGCR" description="GFXTIM watchdog counter register" start="+0x00A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VALUE" description="value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GFXTIM_WDGRR" description="GFXTIM watchdog reload register" start="+0x00A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GFXTIM_WDGPAR" description="GFXTIM watchdog pre-alarm register" start="+0x00A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PREALARM" description="pre-alarm value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPDMA" description="General purpose direct memory access controller" start="0x40021000">
+    <Register name="GPDMA_SECCFGR" description="GPDMA secure configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="secure state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="secure state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="secure state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="secure state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="secure state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="secure state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="secure state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="secure state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="secure state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="secure state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="secure state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="secure state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="secure state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="secure state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="secure state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="secure state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_PRIVCFGR" description="GPDMA privileged configuration register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_RCFGLOCKR" description="GPDMA configuration lock register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK0" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK1" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK2" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK3" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK4" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK5" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK6" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK7" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK8" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK9" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK10" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK11" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK12" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK13" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK14" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK15" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_MISR" description="GPDMA non-secure masked interrupt status register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_SMISR" description="GPDMA secure masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of the secure channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of the secure channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of the secure channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of the secure channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of the secure channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of the secure channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of the secure channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of the secure channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of the secure channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of the secure channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of the secure channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of the secure channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of the secure channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of the secure channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of the secure channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of the secure channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0LBAR" description="GPDMA channel 0 linked-list base address register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0FCR" description="GPDMA channel 0 flag clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0SR" description="GPDMA channel 0 status register" start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C0CR" description="GPDMA channel 0 control register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0TR1" description="GPDMA channel 0 transfer register 1" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0TR2" description="GPDMA channel 0 transfer register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0BR1" description="GPDMA channel 0 block register 1" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0SAR" description="GPDMA channel 0 source address register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0DAR" description="GPDMA channel 0 destination address register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0LLR" description="GPDMA channel 0 linked-list address register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1LBAR" description="GPDMA channel 1 linked-list base address register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1FCR" description="GPDMA channel 1 flag clear register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1SR" description="GPDMA channel 1 status register" start="+0xE0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C1CR" description="GPDMA channel 1 control register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1TR1" description="GPDMA channel 1 transfer register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1TR2" description="GPDMA channel 1 transfer register 2" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1BR1" description="GPDMA channel 1 block register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1SAR" description="GPDMA channel 1 source address register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1DAR" description="GPDMA channel 1 destination address register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1LLR" description="GPDMA channel 1 linked-list address register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2LBAR" description="GPDMA channel 2 linked-list base address register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2FCR" description="GPDMA channel 2 flag clear register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2SR" description="GPDMA channel 2 status register" start="+0x160" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C2CR" description="GPDMA channel 2 control register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2TR1" description="GPDMA channel 2 transfer register 1" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2TR2" description="GPDMA channel 2 transfer register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2BR1" description="GPDMA channel 2 block register 1" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2SAR" description="GPDMA channel 2 source address register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2DAR" description="GPDMA channel 2 destination address register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2LLR" description="GPDMA channel 2 linked-list address register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3LBAR" description="GPDMA channel 3 linked-list base address register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3FCR" description="GPDMA channel 3 flag clear register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3SR" description="GPDMA channel 3 status register" start="+0x1E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C3CR" description="GPDMA channel 3 control register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3TR1" description="GPDMA channel 3 transfer register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3TR2" description="GPDMA channel 3 transfer register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3BR1" description="GPDMA channel 3 block register 1" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3SAR" description="GPDMA channel 3 source address register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3DAR" description="GPDMA channel 3 destination address register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3LLR" description="GPDMA channel 3 linked-list address register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4LBAR" description="GPDMA channel 4 linked-list base address register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4FCR" description="GPDMA channel 4 flag clear register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4SR" description="GPDMA channel 4 status register" start="+0x260" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C4CR" description="GPDMA channel 4 control register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4TR1" description="GPDMA channel 4 transfer register 1" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4TR2" description="GPDMA channel 4 transfer register 2" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4BR1" description="GPDMA channel 4 block register 1" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4SAR" description="GPDMA channel 4 source address register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4DAR" description="GPDMA channel 4 destination address register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4LLR" description="GPDMA channel 4 linked-list address register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5LBAR" description="GPDMA channel 5 linked-list base address register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5FCR" description="GPDMA channel 5 flag clear register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5SR" description="GPDMA channel 5 status register" start="+0x2E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C5CR" description="GPDMA channel 5 control register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5TR1" description="GPDMA channel 5 transfer register 1" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5TR2" description="GPDMA channel 5 transfer register 2" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5BR1" description="GPDMA channel 5 block register 1" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5SAR" description="GPDMA channel 5 source address register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5DAR" description="GPDMA channel 5 destination address register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5LLR" description="GPDMA channel 5 linked-list address register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6LBAR" description="GPDMA channel 6 linked-list base address register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6FCR" description="GPDMA channel 6 flag clear register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6SR" description="GPDMA channel 6 status register" start="+0x360" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C6CR" description="GPDMA channel 6 control register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6TR1" description="GPDMA channel 6 transfer register 1" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6TR2" description="GPDMA channel 6 transfer register 2" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6BR1" description="GPDMA channel 6 block register 1" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6SAR" description="GPDMA channel 6 source address register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6DAR" description="GPDMA channel 6 destination address register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6LLR" description="GPDMA channel 6 linked-list address register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7LBAR" description="GPDMA channel 7 linked-list base address register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7FCR" description="GPDMA channel 7 flag clear register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7SR" description="GPDMA channel 7 status register" start="+0x3E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C7CR" description="GPDMA channel 7 control register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7TR1" description="GPDMA channel 7 transfer register 1" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7TR2" description="GPDMA channel 7 transfer register 2" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7BR1" description="GPDMA channel 7 block register 1" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7SAR" description="GPDMA channel 7 source address register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7DAR" description="GPDMA channel 7 destination address register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7LLR" description="GPDMA channel 7 linked-list address register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8LBAR" description="GPDMA channel 8 linked-list base address register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8FCR" description="GPDMA channel 8 flag clear register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8SR" description="GPDMA channel 8 status register" start="+0x460" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C8CR" description="GPDMA channel 8 control register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8TR1" description="GPDMA channel 8 transfer register 1" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8TR2" description="GPDMA channel 8 transfer register 2" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8BR1" description="GPDMA channel 8 block register 1" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8SAR" description="GPDMA channel 8 source address register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8DAR" description="GPDMA channel 8 destination address register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8LLR" description="GPDMA channel 8 linked-list address register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9LBAR" description="GPDMA channel 9 linked-list base address register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9FCR" description="GPDMA channel 9 flag clear register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9SR" description="GPDMA channel 9 status register" start="+0x4E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C9CR" description="GPDMA channel 9 control register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9TR1" description="GPDMA channel 9 transfer register 1" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9TR2" description="GPDMA channel 9 transfer register 2" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9BR1" description="GPDMA channel 9 block register 1" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9SAR" description="GPDMA channel 9 source address register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9DAR" description="GPDMA channel 9 destination address register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9LLR" description="GPDMA channel 9 linked-list address register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10LBAR" description="GPDMA channel 10 linked-list base address register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10FCR" description="GPDMA channel 10 flag clear register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10SR" description="GPDMA channel 10 status register" start="+0x560" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C10CR" description="GPDMA channel 10 control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10TR1" description="GPDMA channel 10 transfer register 1" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10TR2" description="GPDMA channel 10 transfer register 2" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10BR1" description="GPDMA channel 10 block register 1" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10SAR" description="GPDMA channel 10 source address register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10DAR" description="GPDMA channel 10 destination address register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10LLR" description="GPDMA channel 10 linked-list address register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11LBAR" description="GPDMA channel 11 linked-list base address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11FCR" description="GPDMA channel 11 flag clear register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11SR" description="GPDMA channel 11 status register" start="+0x5E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C11CR" description="GPDMA channel 11 control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11TR1" description="GPDMA channel 11 transfer register 1" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11TR2" description="GPDMA channel 11 transfer register 2" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11BR1" description="GPDMA channel 11 block register 1" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11SAR" description="GPDMA channel 11 source address register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11DAR" description="GPDMA channel 11 destination address register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11LLR" description="GPDMA channel 11 linked-list address register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12LBAR" description="GPDMA channel 12 linked-list base address register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12FCR" description="GPDMA channel 12 flag clear register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12SR" description="GPDMA channel 12 status register" start="+0x660" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C12CR" description="GPDMA channel 12 control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12TR1" description="GPDMA channel 12 transfer register 1" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12TR2" description="GPDMA channel 12 transfer register 2" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12BR1" description="GPDMA channel 12 alternate block register 1" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12SAR" description="GPDMA channel 12 source address register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12DAR" description="GPDMA channel 12 destination address register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12TR3" description="GPDMA channel 12 transfer register 3" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12BR2" description="GPDMA channel 12 block register 2" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12LLR" description="GPDMA channel 12 alternate linked-list address register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13LBAR" description="GPDMA channel 13 linked-list base address register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13FCR" description="GPDMA channel 13 flag clear register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13SR" description="GPDMA channel 13 status register" start="+0x6E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C13CR" description="GPDMA channel 13 control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13TR1" description="GPDMA channel 13 transfer register 1" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13TR2" description="GPDMA channel 13 transfer register 2" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13BR1" description="GPDMA channel 13 alternate block register 1" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13SAR" description="GPDMA channel 13 source address register" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13DAR" description="GPDMA channel 13 destination address register" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13TR3" description="GPDMA channel 13 transfer register 3" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13BR2" description="GPDMA channel 13 block register 2" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13LLR" description="GPDMA channel 13 alternate linked-list address register" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14LBAR" description="GPDMA channel 14 linked-list base address register" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14FCR" description="GPDMA channel 14 flag clear register" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14SR" description="GPDMA channel 14 status register" start="+0x760" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C14CR" description="GPDMA channel 14 control register" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14TR1" description="GPDMA channel 14 transfer register 1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14TR2" description="GPDMA channel 14 transfer register 2" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14BR1" description="GPDMA channel 14 alternate block register 1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14SAR" description="GPDMA channel 14 source address register" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14DAR" description="GPDMA channel 14 destination address register" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14TR3" description="GPDMA channel 14 transfer register 3" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14BR2" description="GPDMA channel 14 block register 2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14LLR" description="GPDMA channel 14 alternate linked-list address register" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15LBAR" description="GPDMA channel 15 linked-list base address register" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15FCR" description="GPDMA channel 15 flag clear register" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15SR" description="GPDMA channel 15 status register" start="+0x7E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C15CR" description="GPDMA channel 15 control register" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15TR1" description="GPDMA channel 15 transfer register 1" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15TR2" description="GPDMA channel 15 transfer register 2" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15BR1" description="GPDMA channel 15 alternate block register 1" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15SAR" description="GPDMA channel 15 source address register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15DAR" description="GPDMA channel 15 destination address register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15TR3" description="GPDMA channel 15 transfer register 3" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15BR2" description="GPDMA channel 15 block register 2" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15LLR" description="GPDMA channel 15 alternate linked-list address register" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPDMA_S" description="General purpose direct memory access controller" start="0x50021000">
+    <Register name="GPDMA_SECCFGR" description="GPDMA secure configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="secure state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="secure state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="secure state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="secure state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="secure state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="secure state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="secure state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="secure state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="secure state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="secure state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="secure state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="secure state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="secure state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="secure state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="secure state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="secure state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_PRIVCFGR" description="GPDMA privileged configuration register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_RCFGLOCKR" description="GPDMA configuration lock register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK0" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK1" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK2" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK3" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK4" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK5" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK6" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK7" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK8" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK9" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK10" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK11" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK12" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK13" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK14" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK15" description="lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_MISR" description="GPDMA non-secure masked interrupt status register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_SMISR" description="GPDMA secure masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of the secure channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of the secure channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of the secure channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of the secure channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of the secure channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of the secure channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of the secure channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of the secure channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of the secure channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of the secure channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of the secure channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of the secure channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of the secure channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of the secure channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of the secure channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of the secure channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0LBAR" description="GPDMA channel 0 linked-list base address register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0FCR" description="GPDMA channel 0 flag clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0SR" description="GPDMA channel 0 status register" start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C0CR" description="GPDMA channel 0 control register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0TR1" description="GPDMA channel 0 transfer register 1" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0TR2" description="GPDMA channel 0 transfer register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C0BR1" description="GPDMA channel 0 block register 1" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0SAR" description="GPDMA channel 0 source address register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0DAR" description="GPDMA channel 0 destination address register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C0LLR" description="GPDMA channel 0 linked-list address register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1LBAR" description="GPDMA channel 1 linked-list base address register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1FCR" description="GPDMA channel 1 flag clear register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1SR" description="GPDMA channel 1 status register" start="+0xE0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C1CR" description="GPDMA channel 1 control register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1TR1" description="GPDMA channel 1 transfer register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1TR2" description="GPDMA channel 1 transfer register 2" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C1BR1" description="GPDMA channel 1 block register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1SAR" description="GPDMA channel 1 source address register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1DAR" description="GPDMA channel 1 destination address register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C1LLR" description="GPDMA channel 1 linked-list address register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2LBAR" description="GPDMA channel 2 linked-list base address register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2FCR" description="GPDMA channel 2 flag clear register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2SR" description="GPDMA channel 2 status register" start="+0x160" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C2CR" description="GPDMA channel 2 control register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2TR1" description="GPDMA channel 2 transfer register 1" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2TR2" description="GPDMA channel 2 transfer register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C2BR1" description="GPDMA channel 2 block register 1" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2SAR" description="GPDMA channel 2 source address register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2DAR" description="GPDMA channel 2 destination address register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C2LLR" description="GPDMA channel 2 linked-list address register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3LBAR" description="GPDMA channel 3 linked-list base address register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3FCR" description="GPDMA channel 3 flag clear register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3SR" description="GPDMA channel 3 status register" start="+0x1E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C3CR" description="GPDMA channel 3 control register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3TR1" description="GPDMA channel 3 transfer register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3TR2" description="GPDMA channel 3 transfer register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C3BR1" description="GPDMA channel 3 block register 1" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3SAR" description="GPDMA channel 3 source address register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3DAR" description="GPDMA channel 3 destination address register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C3LLR" description="GPDMA channel 3 linked-list address register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4LBAR" description="GPDMA channel 4 linked-list base address register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4FCR" description="GPDMA channel 4 flag clear register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4SR" description="GPDMA channel 4 status register" start="+0x260" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C4CR" description="GPDMA channel 4 control register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4TR1" description="GPDMA channel 4 transfer register 1" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4TR2" description="GPDMA channel 4 transfer register 2" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C4BR1" description="GPDMA channel 4 block register 1" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4SAR" description="GPDMA channel 4 source address register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4DAR" description="GPDMA channel 4 destination address register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C4LLR" description="GPDMA channel 4 linked-list address register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5LBAR" description="GPDMA channel 5 linked-list base address register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5FCR" description="GPDMA channel 5 flag clear register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5SR" description="GPDMA channel 5 status register" start="+0x2E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C5CR" description="GPDMA channel 5 control register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5TR1" description="GPDMA channel 5 transfer register 1" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5TR2" description="GPDMA channel 5 transfer register 2" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C5BR1" description="GPDMA channel 5 block register 1" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5SAR" description="GPDMA channel 5 source address register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5DAR" description="GPDMA channel 5 destination address register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C5LLR" description="GPDMA channel 5 linked-list address register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6LBAR" description="GPDMA channel 6 linked-list base address register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6FCR" description="GPDMA channel 6 flag clear register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6SR" description="GPDMA channel 6 status register" start="+0x360" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C6CR" description="GPDMA channel 6 control register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6TR1" description="GPDMA channel 6 transfer register 1" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6TR2" description="GPDMA channel 6 transfer register 2" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C6BR1" description="GPDMA channel 6 block register 1" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6SAR" description="GPDMA channel 6 source address register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6DAR" description="GPDMA channel 6 destination address register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C6LLR" description="GPDMA channel 6 linked-list address register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7LBAR" description="GPDMA channel 7 linked-list base address register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7FCR" description="GPDMA channel 7 flag clear register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7SR" description="GPDMA channel 7 status register" start="+0x3E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C7CR" description="GPDMA channel 7 control register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7TR1" description="GPDMA channel 7 transfer register 1" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7TR2" description="GPDMA channel 7 transfer register 2" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C7BR1" description="GPDMA channel 7 block register 1" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7SAR" description="GPDMA channel 7 source address register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7DAR" description="GPDMA channel 7 destination address register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C7LLR" description="GPDMA channel 7 linked-list address register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8LBAR" description="GPDMA channel 8 linked-list base address register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8FCR" description="GPDMA channel 8 flag clear register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8SR" description="GPDMA channel 8 status register" start="+0x460" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C8CR" description="GPDMA channel 8 control register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8TR1" description="GPDMA channel 8 transfer register 1" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8TR2" description="GPDMA channel 8 transfer register 2" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C8BR1" description="GPDMA channel 8 block register 1" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8SAR" description="GPDMA channel 8 source address register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8DAR" description="GPDMA channel 8 destination address register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C8LLR" description="GPDMA channel 8 linked-list address register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9LBAR" description="GPDMA channel 9 linked-list base address register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9FCR" description="GPDMA channel 9 flag clear register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9SR" description="GPDMA channel 9 status register" start="+0x4E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C9CR" description="GPDMA channel 9 control register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9TR1" description="GPDMA channel 9 transfer register 1" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9TR2" description="GPDMA channel 9 transfer register 2" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C9BR1" description="GPDMA channel 9 block register 1" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9SAR" description="GPDMA channel 9 source address register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9DAR" description="GPDMA channel 9 destination address register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C9LLR" description="GPDMA channel 9 linked-list address register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10LBAR" description="GPDMA channel 10 linked-list base address register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10FCR" description="GPDMA channel 10 flag clear register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10SR" description="GPDMA channel 10 status register" start="+0x560" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C10CR" description="GPDMA channel 10 control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10TR1" description="GPDMA channel 10 transfer register 1" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10TR2" description="GPDMA channel 10 transfer register 2" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C10BR1" description="GPDMA channel 10 block register 1" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10SAR" description="GPDMA channel 10 source address register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10DAR" description="GPDMA channel 10 destination address register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C10LLR" description="GPDMA channel 10 linked-list address register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11LBAR" description="GPDMA channel 11 linked-list base address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11FCR" description="GPDMA channel 11 flag clear register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11SR" description="GPDMA channel 11 status register" start="+0x5E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C11CR" description="GPDMA channel 11 control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11TR1" description="GPDMA channel 11 transfer register 1" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11TR2" description="GPDMA channel 11 transfer register 2" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C11BR1" description="GPDMA channel 11 block register 1" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11SAR" description="GPDMA channel 11 source address register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11DAR" description="GPDMA channel 11 destination address register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C11LLR" description="GPDMA channel 11 linked-list address register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12LBAR" description="GPDMA channel 12 linked-list base address register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12FCR" description="GPDMA channel 12 flag clear register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12SR" description="GPDMA channel 12 status register" start="+0x660" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C12CR" description="GPDMA channel 12 control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12TR1" description="GPDMA channel 12 transfer register 1" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12TR2" description="GPDMA channel 12 transfer register 2" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12BR1" description="GPDMA channel 12 alternate block register 1" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C12SAR" description="GPDMA channel 12 source address register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12DAR" description="GPDMA channel 12 destination address register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12TR3" description="GPDMA channel 12 transfer register 3" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12BR2" description="GPDMA channel 12 block register 2" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C12LLR" description="GPDMA channel 12 alternate linked-list address register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13LBAR" description="GPDMA channel 13 linked-list base address register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13FCR" description="GPDMA channel 13 flag clear register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13SR" description="GPDMA channel 13 status register" start="+0x6E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C13CR" description="GPDMA channel 13 control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13TR1" description="GPDMA channel 13 transfer register 1" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13TR2" description="GPDMA channel 13 transfer register 2" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13BR1" description="GPDMA channel 13 alternate block register 1" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C13SAR" description="GPDMA channel 13 source address register" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13DAR" description="GPDMA channel 13 destination address register" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13TR3" description="GPDMA channel 13 transfer register 3" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13BR2" description="GPDMA channel 13 block register 2" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C13LLR" description="GPDMA channel 13 alternate linked-list address register" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14LBAR" description="GPDMA channel 14 linked-list base address register" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14FCR" description="GPDMA channel 14 flag clear register" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14SR" description="GPDMA channel 14 status register" start="+0x760" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C14CR" description="GPDMA channel 14 control register" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14TR1" description="GPDMA channel 14 transfer register 1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14TR2" description="GPDMA channel 14 transfer register 2" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14BR1" description="GPDMA channel 14 alternate block register 1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C14SAR" description="GPDMA channel 14 source address register" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14DAR" description="GPDMA channel 14 destination address register" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14TR3" description="GPDMA channel 14 transfer register 3" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14BR2" description="GPDMA channel 14 block register 2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C14LLR" description="GPDMA channel 14 alternate linked-list address register" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15LBAR" description="GPDMA channel 15 linked-list base address register" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of GPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15FCR" description="GPDMA channel 15 flag clear register" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15SR" description="GPDMA channel 15 status register" start="+0x7E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="a half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="GPDMA_C15CR" description="GPDMA channel 15 control register" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and" start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x GPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15TR1" description="GPDMA channel 15 transfer register 1" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the GPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="user setting error reported and no transfer issued" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no halfword-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AHB) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the GPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15TR2" description="GPDMA channel 15 transfer register 2" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="GPDMA hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 19.3.3)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. The GPDMA is programmed with GPDMA_CxTR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The GPDMA block transfer can be early completed by the peripheral itself (see Section 19.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00; channel x (x =12 to 15), at 2D/repeated block level. The first burst read of a 2D/repeated block transfer is conditioned by one hit trigger." start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer" start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x (x = 0 to 11), same as 00, channel x (x =12 to 15), at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0). The complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer The LLI data transfer is a block transfer or a 2D/repeated block transfer for channel x (x =12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15BR1" description="GPDMA channel 15 alternate block register 1" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPDMA_C15SAR" description="GPDMA channel 15 source address register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15DAR" description="GPDMA channel 15 destination address register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15TR3" description="GPDMA channel 15 transfer register 3" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15BR2" description="GPDMA channel 15 block register 2" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="GPDMA_C15LLR" description="GPDMA channel 15 alternate linked-list address register" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update GPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update GPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update GPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update GPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update GPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update GPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update GPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update GPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no GPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOA" description="General-purpose I/Os" start="0x46020000">
+    <Register name="GPIOA_MODER" description="GPIO port A mode register" start="+0x00" size="4" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_OTYPER" description="GPIO port A output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_OSPEEDR" description="GPIO port A output speed register" start="+0x08" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PUPDR" description="GPIO port A pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x64000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_IDR" description="GPIO port A input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_ODR" description="GPIO port A output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_BSRR" description="GPIO port A bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_LCKR" description="GPIO port A configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_AFRL" description="GPIO port A alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_AFRH" description="GPIO port A alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_BRR" description="GPIO port A bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_SECCFGR" description="GPIO port A secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PRIVCFGR" description="GPIO port A privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_RCFGLOCKR" description="GPIO port A resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_DELAYRL" description="GPIO port A delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_DELAYRH" description="GPIO port A delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_PIOCFGRL" description="GPIO port A PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PIOCFGRH" description="GPIO port A PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_HWCFGR10" description="GPIO port A hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_HWCFGR9" description="GPIO port A hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_HWCFGR8" description="GPIO port A hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xC00CCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR7" description="GPIO port A hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCEECCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR6" description="GPIO port A hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR5" description="GPIO port A hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x64000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR4" description="GPIO port A hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR3" description="GPIO port A hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR2" description="GPIO port A hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR1" description="GPIO port A hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR0" description="GPIO port A hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_VERR" description="GPIO port A version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_IPIDR" description="GPIO port A identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_SIDR" description="GPIO port A size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOA_S" description="General-purpose I/Os" start="0x56020000">
+    <Register name="GPIOA_MODER" description="GPIO port A mode register" start="+0x00" size="4" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_OTYPER" description="GPIO port A output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_OSPEEDR" description="GPIO port A output speed register" start="+0x08" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PUPDR" description="GPIO port A pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x64000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_IDR" description="GPIO port A input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_ODR" description="GPIO port A output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_BSRR" description="GPIO port A bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_LCKR" description="GPIO port A configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_AFRL" description="GPIO port A alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_AFRH" description="GPIO port A alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_BRR" description="GPIO port A bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_SECCFGR" description="GPIO port A secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PRIVCFGR" description="GPIO port A privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_RCFGLOCKR" description="GPIO port A resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_DELAYRL" description="GPIO port A delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_DELAYRH" description="GPIO port A delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_PIOCFGRL" description="GPIO port A PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_PIOCFGRH" description="GPIO port A PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOA_HWCFGR10" description="GPIO port A hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_HWCFGR9" description="GPIO port A hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOA_HWCFGR8" description="GPIO port A hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xC00CCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR7" description="GPIO port A hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCEECCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR6" description="GPIO port A hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR5" description="GPIO port A hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x64000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR4" description="GPIO port A hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR3" description="GPIO port A hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR2" description="GPIO port A hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR1" description="GPIO port A hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_HWCFGR0" description="GPIO port A hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_VERR" description="GPIO port A version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_IPIDR" description="GPIO port A identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOA_SIDR" description="GPIO port A size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOB" description="General-purpose I/Os" start="0x46020400">
+    <Register name="GPIOB_MODER" description="GPIO port B mode register" start="+0x00" size="4" reset_value="0xFFFFFAFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_OTYPER" description="GPIO port B output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_OSPEEDR" description="GPIO port B output speed register" start="+0x08" size="4" reset_value="0x00000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PUPDR" description="GPIO port B pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_IDR" description="GPIO port B input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_ODR" description="GPIO port B output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_BSRR" description="GPIO port B bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_LCKR" description="GPIO port B configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_AFRL" description="GPIO port B alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_AFRH" description="GPIO port B alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_BRR" description="GPIO port B bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_SECCFGR" description="GPIO port B secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PRIVCFGR" description="GPIO port B privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_RCFGLOCKR" description="GPIO port B resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_DELAYRL" description="GPIO port B delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_DELAYRH" description="GPIO port B delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_PIOCFGRL" description="GPIO port B PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PIOCFGRH" description="GPIO port B PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_HWCFGR10" description="GPIO port B hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_HWCFGR9" description="GPIO port B hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_HWCFGR8" description="GPIO port B hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR7" description="GPIO port B hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCECCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR6" description="GPIO port B hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFEBF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR5" description="GPIO port B hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR4" description="GPIO port B hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x000000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR3" description="GPIO port B hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR2" description="GPIO port B hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR1" description="GPIO port B hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR0" description="GPIO port B hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_VERR" description="GPIO port B version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_IPIDR" description="GPIO port B identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_SIDR" description="GPIO port B size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOB_S" description="General-purpose I/Os" start="0x56020400">
+    <Register name="GPIOB_MODER" description="GPIO port B mode register" start="+0x00" size="4" reset_value="0xFFFFFAFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_OTYPER" description="GPIO port B output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_OSPEEDR" description="GPIO port B output speed register" start="+0x08" size="4" reset_value="0x00000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PUPDR" description="GPIO port B pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_IDR" description="GPIO port B input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_ODR" description="GPIO port B output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_BSRR" description="GPIO port B bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_LCKR" description="GPIO port B configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_AFRL" description="GPIO port B alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_AFRH" description="GPIO port B alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_BRR" description="GPIO port B bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_SECCFGR" description="GPIO port B secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PRIVCFGR" description="GPIO port B privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_RCFGLOCKR" description="GPIO port B resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_DELAYRL" description="GPIO port B delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_DELAYRH" description="GPIO port B delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_PIOCFGRL" description="GPIO port B PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_PIOCFGRH" description="GPIO port B PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOB_HWCFGR10" description="GPIO port B hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_HWCFGR9" description="GPIO port B hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOB_HWCFGR8" description="GPIO port B hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR7" description="GPIO port B hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCECCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR6" description="GPIO port B hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFEBF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR5" description="GPIO port B hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR4" description="GPIO port B hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x000000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR3" description="GPIO port B hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR2" description="GPIO port B hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR1" description="GPIO port B hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_HWCFGR0" description="GPIO port B hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_VERR" description="GPIO port B version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_IPIDR" description="GPIO port B identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOB_SIDR" description="GPIO port B size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOC" description="General-purpose I/Os" start="0x46020800">
+    <Register name="GPIOC_MODER" description="GPIO port C mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_OTYPER" description="GPIO port C output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_OSPEEDR" description="GPIO port C output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PUPDR" description="GPIO port C pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_IDR" description="GPIO port C input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_ODR" description="GPIO port C output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_BSRR" description="GPIO port C bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_LCKR" description="GPIO port C configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_AFRL" description="GPIO port C alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_AFRH" description="GPIO port C alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_BRR" description="GPIO port C bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_SECCFGR" description="GPIO port C secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PRIVCFGR" description="GPIO port C privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_RCFGLOCKR" description="GPIO port C resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_DELAYRL" description="GPIO port C delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_DELAYRH" description="GPIO port C delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_PIOCFGRL" description="GPIO port C PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PIOCFGRH" description="GPIO port C PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_HWCFGR10" description="GPIO port C hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_HWCFGR9" description="GPIO port C hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_HWCFGR8" description="GPIO port C hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR7" description="GPIO port C hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR6" description="GPIO port C hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR5" description="GPIO port C hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR4" description="GPIO port C hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR3" description="GPIO port C hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR2" description="GPIO port C hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR1" description="GPIO port C hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR0" description="GPIO port C hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_VERR" description="GPIO port C version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_IPIDR" description="GPIO port C identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_SIDR" description="GPIO port C size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOC_S" description="General-purpose I/Os" start="0x56020800">
+    <Register name="GPIOC_MODER" description="GPIO port C mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_OTYPER" description="GPIO port C output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_OSPEEDR" description="GPIO port C output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PUPDR" description="GPIO port C pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_IDR" description="GPIO port C input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_ODR" description="GPIO port C output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_BSRR" description="GPIO port C bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_LCKR" description="GPIO port C configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_AFRL" description="GPIO port C alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_AFRH" description="GPIO port C alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_BRR" description="GPIO port C bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_SECCFGR" description="GPIO port C secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PRIVCFGR" description="GPIO port C privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_RCFGLOCKR" description="GPIO port C resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_DELAYRL" description="GPIO port C delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_DELAYRH" description="GPIO port C delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_PIOCFGRL" description="GPIO port C PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_PIOCFGRH" description="GPIO port C PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOC_HWCFGR10" description="GPIO port C hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_HWCFGR9" description="GPIO port C hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOC_HWCFGR8" description="GPIO port C hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR7" description="GPIO port C hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR6" description="GPIO port C hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR5" description="GPIO port C hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR4" description="GPIO port C hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR3" description="GPIO port C hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR2" description="GPIO port C hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR1" description="GPIO port C hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_HWCFGR0" description="GPIO port C hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_VERR" description="GPIO port C version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_IPIDR" description="GPIO port C identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOC_SIDR" description="GPIO port C size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOD" description="General-purpose I/Os" start="0x46020C00">
+    <Register name="GPIOD_MODER" description="GPIO port D mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_OTYPER" description="GPIO port D output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_OSPEEDR" description="GPIO port D output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PUPDR" description="GPIO port D pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_IDR" description="GPIO port D input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_ODR" description="GPIO port D output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_BSRR" description="GPIO port D bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_LCKR" description="GPIO port D configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_AFRL" description="GPIO port D alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_AFRH" description="GPIO port D alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_BRR" description="GPIO port D bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_SECCFGR" description="GPIO port D secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PRIVCFGR" description="GPIO port D privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_RCFGLOCKR" description="GPIO port D resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_DELAYRL" description="GPIO port D delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_DELAYRH" description="GPIO port D delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_PIOCFGRL" description="GPIO port D PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PIOCFGRH" description="GPIO port D PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_HWCFGR10" description="GPIO port D hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_HWCFGR9" description="GPIO port D hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_HWCFGR8" description="GPIO port D hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xCBCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR7" description="GPIO port D hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCACC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR6" description="GPIO port D hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR5" description="GPIO port D hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR4" description="GPIO port D hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR3" description="GPIO port D hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR2" description="GPIO port D hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR1" description="GPIO port D hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR0" description="GPIO port D hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_VERR" description="GPIO port D version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_IPIDR" description="GPIO port D identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_SIDR" description="GPIO port D size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOD_S" description="General-purpose I/Os" start="0x56020C00">
+    <Register name="GPIOD_MODER" description="GPIO port D mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_OTYPER" description="GPIO port D output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_OSPEEDR" description="GPIO port D output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PUPDR" description="GPIO port D pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_IDR" description="GPIO port D input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_ODR" description="GPIO port D output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_BSRR" description="GPIO port D bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_LCKR" description="GPIO port D configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_AFRL" description="GPIO port D alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_AFRH" description="GPIO port D alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_BRR" description="GPIO port D bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_SECCFGR" description="GPIO port D secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PRIVCFGR" description="GPIO port D privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_RCFGLOCKR" description="GPIO port D resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_DELAYRL" description="GPIO port D delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_DELAYRH" description="GPIO port D delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_PIOCFGRL" description="GPIO port D PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_PIOCFGRH" description="GPIO port D PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOD_HWCFGR10" description="GPIO port D hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_HWCFGR9" description="GPIO port D hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOD_HWCFGR8" description="GPIO port D hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xCBCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR7" description="GPIO port D hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCACC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR6" description="GPIO port D hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR5" description="GPIO port D hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR4" description="GPIO port D hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR3" description="GPIO port D hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR2" description="GPIO port D hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR1" description="GPIO port D hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_HWCFGR0" description="GPIO port D hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_VERR" description="GPIO port D version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_IPIDR" description="GPIO port D identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOD_SIDR" description="GPIO port D size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOE" description="General-purpose I/Os" start="0x46021000">
+    <Register name="GPIOE_MODER" description="GPIO port E mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_OTYPER" description="GPIO port E output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_OSPEEDR" description="GPIO port E output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PUPDR" description="GPIO port E pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_IDR" description="GPIO port E input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_ODR" description="GPIO port E output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_BSRR" description="GPIO port E bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_LCKR" description="GPIO port E configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_AFRL" description="GPIO port E alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_AFRH" description="GPIO port E alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_BRR" description="GPIO port E bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_SECCFGR" description="GPIO port E secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PRIVCFGR" description="GPIO port E privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_RCFGLOCKR" description="GPIO port E resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_DELAYRL" description="GPIO port E delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_DELAYRH" description="GPIO port E delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_PIOCFGRL" description="GPIO port E PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PIOCFGRH" description="GPIO port E PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_HWCFGR10" description="GPIO port E hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_HWCFGR9" description="GPIO port E hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_HWCFGR8" description="GPIO port E hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR7" description="GPIO port E hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR6" description="GPIO port E hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR5" description="GPIO port E hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR4" description="GPIO port E hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR3" description="GPIO port E hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR2" description="GPIO port E hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR1" description="GPIO port E hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR0" description="GPIO port E hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_VERR" description="GPIO port E version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_IPIDR" description="GPIO port E identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_SIDR" description="GPIO port E size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOE_S" description="General-purpose I/Os" start="0x56021000">
+    <Register name="GPIOE_MODER" description="GPIO port E mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_OTYPER" description="GPIO port E output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_OSPEEDR" description="GPIO port E output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PUPDR" description="GPIO port E pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_IDR" description="GPIO port E input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_ODR" description="GPIO port E output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_BSRR" description="GPIO port E bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_LCKR" description="GPIO port E configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_AFRL" description="GPIO port E alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_AFRH" description="GPIO port E alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_BRR" description="GPIO port E bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_SECCFGR" description="GPIO port E secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PRIVCFGR" description="GPIO port E privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_RCFGLOCKR" description="GPIO port E resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_DELAYRL" description="GPIO port E delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_DELAYRH" description="GPIO port E delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_PIOCFGRL" description="GPIO port E PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_PIOCFGRH" description="GPIO port E PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOE_HWCFGR10" description="GPIO port E hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_HWCFGR9" description="GPIO port E hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOE_HWCFGR8" description="GPIO port E hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR7" description="GPIO port E hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR6" description="GPIO port E hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR5" description="GPIO port E hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR4" description="GPIO port E hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR3" description="GPIO port E hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR2" description="GPIO port E hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR1" description="GPIO port E hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_HWCFGR0" description="GPIO port E hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_VERR" description="GPIO port E version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_IPIDR" description="GPIO port E identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOE_SIDR" description="GPIO port E size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOF" description="General-purpose I/Os" start="0x46021400">
+    <Register name="GPIOF_MODER" description="GPIO port F mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_OTYPER" description="GPIO port F output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_OSPEEDR" description="GPIO port F output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PUPDR" description="GPIO port F pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_IDR" description="GPIO port F input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_ODR" description="GPIO port F output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_BSRR" description="GPIO port F bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_LCKR" description="GPIO port F configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_AFRL" description="GPIO port F alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_AFRH" description="GPIO port F alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_BRR" description="GPIO port F bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_SECCFGR" description="GPIO port F secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PRIVCFGR" description="GPIO port F privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_RCFGLOCKR" description="GPIO port F resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_DELAYRL" description="GPIO port F delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_DELAYRH" description="GPIO port F delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_PIOCFGRL" description="GPIO port F PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PIOCFGRH" description="GPIO port F PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_HWCFGR10" description="GPIO port F hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_HWCFGR9" description="GPIO port F hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_HWCFGR8" description="GPIO port F hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xBBBBBBCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR7" description="GPIO port F hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR6" description="GPIO port F hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR5" description="GPIO port F hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR4" description="GPIO port F hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR3" description="GPIO port F hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR2" description="GPIO port F hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR1" description="GPIO port F hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR0" description="GPIO port F hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_VERR" description="GPIO port F version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_IPIDR" description="GPIO port F identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_SIDR" description="GPIO port F size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOF_S" description="General-purpose I/Os" start="0x56021400">
+    <Register name="GPIOF_MODER" description="GPIO port F mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_OTYPER" description="GPIO port F output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_OSPEEDR" description="GPIO port F output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PUPDR" description="GPIO port F pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_IDR" description="GPIO port F input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_ODR" description="GPIO port F output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_BSRR" description="GPIO port F bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_LCKR" description="GPIO port F configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_AFRL" description="GPIO port F alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_AFRH" description="GPIO port F alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_BRR" description="GPIO port F bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_SECCFGR" description="GPIO port F secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PRIVCFGR" description="GPIO port F privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_RCFGLOCKR" description="GPIO port F resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_DELAYRL" description="GPIO port F delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_DELAYRH" description="GPIO port F delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_PIOCFGRL" description="GPIO port F PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_PIOCFGRH" description="GPIO port F PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOF_HWCFGR10" description="GPIO port F hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_HWCFGR9" description="GPIO port F hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOF_HWCFGR8" description="GPIO port F hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xBBBBBBCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR7" description="GPIO port F hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR6" description="GPIO port F hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR5" description="GPIO port F hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR4" description="GPIO port F hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR3" description="GPIO port F hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR2" description="GPIO port F hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR1" description="GPIO port F hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_HWCFGR0" description="GPIO port F hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_VERR" description="GPIO port F version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_IPIDR" description="GPIO port F identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOF_SIDR" description="GPIO port F size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOG" description="General-purpose I/Os" start="0x46021800">
+    <Register name="GPIOG_MODER" description="GPIO port G mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_OTYPER" description="GPIO port G output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_OSPEEDR" description="GPIO port G output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PUPDR" description="GPIO port G pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_IDR" description="GPIO port G input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_ODR" description="GPIO port G output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_BSRR" description="GPIO port G bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_LCKR" description="GPIO port G configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_AFRL" description="GPIO port G alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_AFRH" description="GPIO port G alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_BRR" description="GPIO port G bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_SECCFGR" description="GPIO port G secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PRIVCFGR" description="GPIO port G privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_RCFGLOCKR" description="GPIO port G resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_DELAYRL" description="GPIO port G delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_DELAYRH" description="GPIO port G delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_PIOCFGRL" description="GPIO port G PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PIOCFGRH" description="GPIO port G PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_HWCFGR10" description="GPIO port G hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_HWCFGR9" description="GPIO port G hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_HWCFGR8" description="GPIO port G hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xBBBBBBBB" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR7" description="GPIO port G hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR6" description="GPIO port G hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR5" description="GPIO port G hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR4" description="GPIO port G hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR3" description="GPIO port G hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR2" description="GPIO port G hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR1" description="GPIO port G hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR0" description="GPIO port G hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_VERR" description="GPIO port G version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_IPIDR" description="GPIO port G identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_SIDR" description="GPIO port G size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOG_S" description="General-purpose I/Os" start="0x56021800">
+    <Register name="GPIOG_MODER" description="GPIO port G mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_OTYPER" description="GPIO port G output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_OSPEEDR" description="GPIO port G output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PUPDR" description="GPIO port G pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_IDR" description="GPIO port G input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_ODR" description="GPIO port G output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_BSRR" description="GPIO port G bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_LCKR" description="GPIO port G configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_AFRL" description="GPIO port G alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_AFRH" description="GPIO port G alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_BRR" description="GPIO port G bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_SECCFGR" description="GPIO port G secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PRIVCFGR" description="GPIO port G privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_RCFGLOCKR" description="GPIO port G resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_DELAYRL" description="GPIO port G delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_DELAYRH" description="GPIO port G delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_PIOCFGRL" description="GPIO port G PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_PIOCFGRH" description="GPIO port G PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOG_HWCFGR10" description="GPIO port G hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_HWCFGR9" description="GPIO port G hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOG_HWCFGR8" description="GPIO port G hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xBBBBBBBB" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR7" description="GPIO port G hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xCCCCCCCC" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR6" description="GPIO port G hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR5" description="GPIO port G hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR4" description="GPIO port G hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR3" description="GPIO port G hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR2" description="GPIO port G hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR1" description="GPIO port G hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_HWCFGR0" description="GPIO port G hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_VERR" description="GPIO port G version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_IPIDR" description="GPIO port G identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOG_SIDR" description="GPIO port G size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOH" description="General-purpose I/Os" start="0x46021C00">
+    <Register name="GPIOH_MODER" description="GPIO port H mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_OTYPER" description="GPIO port H output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_OSPEEDR" description="GPIO port H output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PUPDR" description="GPIO port H pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_IDR" description="GPIO port H input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_ODR" description="GPIO port H output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_BSRR" description="GPIO port H bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_LCKR" description="GPIO port H configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_AFRL" description="GPIO port H alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_AFRH" description="GPIO port H alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_BRR" description="GPIO port H bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_SECCFGR" description="GPIO port H secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PRIVCFGR" description="GPIO port H privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_RCFGLOCKR" description="GPIO port H resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_DELAYRL" description="GPIO port H delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_DELAYRH" description="GPIO port H delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_PIOCFGRL" description="GPIO port H PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PIOCFGRH" description="GPIO port H PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_HWCFGR10" description="GPIO port H hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_HWCFGR9" description="GPIO port H hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_HWCFGR8" description="GPIO port H hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFF2" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR7" description="GPIO port H hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x2E5FEEFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR6" description="GPIO port H hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR5" description="GPIO port H hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR4" description="GPIO port H hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR3" description="GPIO port H hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR2" description="GPIO port H hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR1" description="GPIO port H hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR0" description="GPIO port H hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_VERR" description="GPIO port H version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_IPIDR" description="GPIO port H identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_SIDR" description="GPIO port H size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOH_S" description="General-purpose I/Os" start="0x56021C00">
+    <Register name="GPIOH_MODER" description="GPIO port H mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_OTYPER" description="GPIO port H output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_OSPEEDR" description="GPIO port H output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PUPDR" description="GPIO port H pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_IDR" description="GPIO port H input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_ODR" description="GPIO port H output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_BSRR" description="GPIO port H bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_LCKR" description="GPIO port H configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_AFRL" description="GPIO port H alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_AFRH" description="GPIO port H alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_BRR" description="GPIO port H bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_SECCFGR" description="GPIO port H secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PRIVCFGR" description="GPIO port H privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_RCFGLOCKR" description="GPIO port H resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_DELAYRL" description="GPIO port H delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_DELAYRH" description="GPIO port H delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_PIOCFGRL" description="GPIO port H PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_PIOCFGRH" description="GPIO port H PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOH_HWCFGR10" description="GPIO port H hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_HWCFGR9" description="GPIO port H hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOH_HWCFGR8" description="GPIO port H hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFF2" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR7" description="GPIO port H hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x2E5FEEFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR6" description="GPIO port H hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR5" description="GPIO port H hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR4" description="GPIO port H hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR3" description="GPIO port H hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR2" description="GPIO port H hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR1" description="GPIO port H hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_HWCFGR0" description="GPIO port H hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_VERR" description="GPIO port H version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_IPIDR" description="GPIO port H identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOH_SIDR" description="GPIO port H size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPION" description="General-purpose I/Os" start="0x46023400">
+    <Register name="GPION_MODER" description="GPIO port N mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPION_OTYPER" description="GPIO port N output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_OSPEEDR" description="GPIO port N output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PUPDR" description="GPIO port N pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPION_IDR" description="GPIO port N input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_ODR" description="GPIO port N output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPION_BSRR" description="GPIO port N bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_LCKR" description="GPIO port N configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_AFRL" description="GPIO port N alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPION_AFRH" description="GPIO port N alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_BRR" description="GPIO port N bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_SECCFGR" description="GPIO port N secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PRIVCFGR" description="GPIO port N privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_RCFGLOCKR" description="GPIO port N resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_DELAYRL" description="GPIO port N delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPION_DELAYRH" description="GPIO port N delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_PIOCFGRL" description="GPIO port N PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PIOCFGRH" description="GPIO port N PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_HWCFGR10" description="GPIO port N hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_HWCFGR9" description="GPIO port N hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x00001FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_HWCFGR8" description="GPIO port N hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFF99999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR7" description="GPIO port N hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR6" description="GPIO port N hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR5" description="GPIO port N hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR4" description="GPIO port N hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR3" description="GPIO port N hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR2" description="GPIO port N hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR1" description="GPIO port N hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR0" description="GPIO port N hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_VERR" description="GPIO port N version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_IPIDR" description="GPIO port N identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_SIDR" description="GPIO port N size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPION_S" description="General-purpose I/Os" start="0x56023400">
+    <Register name="GPION_MODER" description="GPIO port N mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPION_OTYPER" description="GPIO port N output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_OSPEEDR" description="GPIO port N output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PUPDR" description="GPIO port N pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPION_IDR" description="GPIO port N input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_ODR" description="GPIO port N output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPION_BSRR" description="GPIO port N bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_LCKR" description="GPIO port N configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_AFRL" description="GPIO port N alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPION_AFRH" description="GPIO port N alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_BRR" description="GPIO port N bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_SECCFGR" description="GPIO port N secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PRIVCFGR" description="GPIO port N privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_RCFGLOCKR" description="GPIO port N resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_DELAYRL" description="GPIO port N delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPION_DELAYRH" description="GPIO port N delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_PIOCFGRL" description="GPIO port N PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_PIOCFGRH" description="GPIO port N PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPION_HWCFGR10" description="GPIO port N hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_HWCFGR9" description="GPIO port N hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x00001FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPION_HWCFGR8" description="GPIO port N hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFF99999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR7" description="GPIO port N hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR6" description="GPIO port N hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR5" description="GPIO port N hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR4" description="GPIO port N hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR3" description="GPIO port N hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR2" description="GPIO port N hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR1" description="GPIO port N hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_HWCFGR0" description="GPIO port N hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_VERR" description="GPIO port N version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_IPIDR" description="GPIO port N identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPION_SIDR" description="GPIO port N size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOO" description="General-purpose I/Os" start="0x46023800">
+    <Register name="GPIOO_MODER" description="GPIO port O mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_OTYPER" description="GPIO port O output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_OSPEEDR" description="GPIO port O output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PUPDR" description="GPIO port O pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_IDR" description="GPIO port O input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_ODR" description="GPIO port O output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_BSRR" description="GPIO port O bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_LCKR" description="GPIO port O configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_AFRL" description="GPIO port O alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_AFRH" description="GPIO port O alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_BRR" description="GPIO port O bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_SECCFGR" description="GPIO port O secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PRIVCFGR" description="GPIO port O privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_RCFGLOCKR" description="GPIO port O resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_DELAYRL" description="GPIO port O delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_DELAYRH" description="GPIO port O delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_PIOCFGRL" description="GPIO port O PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PIOCFGRH" description="GPIO port O PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_HWCFGR10" description="GPIO port O hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_HWCFGR9" description="GPIO port O hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000003F" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_HWCFGR8" description="GPIO port O hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR7" description="GPIO port O hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xFF999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR6" description="GPIO port O hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR5" description="GPIO port O hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR4" description="GPIO port O hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR3" description="GPIO port O hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR2" description="GPIO port O hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR1" description="GPIO port O hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR0" description="GPIO port O hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_VERR" description="GPIO port O version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_IPIDR" description="GPIO port O identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_SIDR" description="GPIO port O size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOO_S" description="General-purpose I/Os" start="0x56023800">
+    <Register name="GPIOO_MODER" description="GPIO port O mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_OTYPER" description="GPIO port O output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_OSPEEDR" description="GPIO port O output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PUPDR" description="GPIO port O pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_IDR" description="GPIO port O input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_ODR" description="GPIO port O output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_BSRR" description="GPIO port O bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_LCKR" description="GPIO port O configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_AFRL" description="GPIO port O alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_AFRH" description="GPIO port O alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_BRR" description="GPIO port O bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_SECCFGR" description="GPIO port O secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PRIVCFGR" description="GPIO port O privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_RCFGLOCKR" description="GPIO port O resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_DELAYRL" description="GPIO port O delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_DELAYRH" description="GPIO port O delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_PIOCFGRL" description="GPIO port O PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_PIOCFGRH" description="GPIO port O PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOO_HWCFGR10" description="GPIO port O hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_HWCFGR9" description="GPIO port O hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000003F" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOO_HWCFGR8" description="GPIO port O hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR7" description="GPIO port O hardware configuration register 7" start="+0x3D4" size="4" reset_value="0xFF999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR6" description="GPIO port O hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR5" description="GPIO port O hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR4" description="GPIO port O hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR3" description="GPIO port O hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR2" description="GPIO port O hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR1" description="GPIO port O hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_HWCFGR0" description="GPIO port O hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_VERR" description="GPIO port O version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_IPIDR" description="GPIO port O identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOO_SIDR" description="GPIO port O size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOP" description="General-purpose I/Os" start="0x46023C00">
+    <Register name="GPIOP_MODER" description="GPIO port P mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_OTYPER" description="GPIO port P output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_OSPEEDR" description="GPIO port P output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PUPDR" description="GPIO port P pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_IDR" description="GPIO port P input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_ODR" description="GPIO port P output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_BSRR" description="GPIO port P bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_LCKR" description="GPIO port P configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_AFRL" description="GPIO port P alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_AFRH" description="GPIO port P alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_BRR" description="GPIO port P bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_SECCFGR" description="GPIO port P secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PRIVCFGR" description="GPIO port P privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_RCFGLOCKR" description="GPIO port P resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_DELAYRL" description="GPIO port P delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_DELAYRH" description="GPIO port P delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_PIOCFGRL" description="GPIO port P PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PIOCFGRH" description="GPIO port P PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_HWCFGR10" description="GPIO port P hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_HWCFGR9" description="GPIO port P hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_HWCFGR8" description="GPIO port P hardware configuration register 8" start="+0x3D0" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR7" description="GPIO port P hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR6" description="GPIO port P hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR5" description="GPIO port P hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR4" description="GPIO port P hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR3" description="GPIO port P hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR2" description="GPIO port P hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR1" description="GPIO port P hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR0" description="GPIO port P hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_VERR" description="GPIO port P version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_IPIDR" description="GPIO port P identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_SIDR" description="GPIO port P size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOP_S" description="General-purpose I/Os" start="0x56023C00">
+    <Register name="GPIOP_MODER" description="GPIO port P mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_OTYPER" description="GPIO port P output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_OSPEEDR" description="GPIO port P output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PUPDR" description="GPIO port P pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_IDR" description="GPIO port P input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_ODR" description="GPIO port P output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_BSRR" description="GPIO port P bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_LCKR" description="GPIO port P configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_AFRL" description="GPIO port P alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_AFRH" description="GPIO port P alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_BRR" description="GPIO port P bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_SECCFGR" description="GPIO port P secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PRIVCFGR" description="GPIO port P privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_RCFGLOCKR" description="GPIO port P resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_DELAYRL" description="GPIO port P delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_DELAYRH" description="GPIO port P delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_PIOCFGRL" description="GPIO port P PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_PIOCFGRH" description="GPIO port P PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOP_HWCFGR10" description="GPIO port P hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_HWCFGR9" description="GPIO port P hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOP_HWCFGR8" description="GPIO port P hardware configuration register 8" start="+0x3D0" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR7" description="GPIO port P hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x99999999" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR6" description="GPIO port P hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR5" description="GPIO port P hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR4" description="GPIO port P hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR3" description="GPIO port P hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR2" description="GPIO port P hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR1" description="GPIO port P hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_HWCFGR0" description="GPIO port P hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_VERR" description="GPIO port P version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_IPIDR" description="GPIO port P identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOP_SIDR" description="GPIO port P size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOQ" description="General-purpose I/Os" start="0x46024000">
+    <Register name="GPIOQ_MODER" description="GPIO port Q mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_OTYPER" description="GPIO port Q output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_OSPEEDR" description="GPIO port Q output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PUPDR" description="GPIO port Q pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_IDR" description="GPIO port Q input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_ODR" description="GPIO port Q output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_BSRR" description="GPIO port Q bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_LCKR" description="GPIO port Q configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_AFRL" description="GPIO port Q alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_AFRH" description="GPIO port Q alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_BRR" description="GPIO port Q bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_SECCFGR" description="GPIO port Q secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PRIVCFGR" description="GPIO port Q privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_RCFGLOCKR" description="GPIO port Q resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_DELAYRL" description="GPIO port Q delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_DELAYRH" description="GPIO port Q delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_PIOCFGRL" description="GPIO port Q PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PIOCFGRH" description="GPIO port Q PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR10" description="GPIO port Q hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_HWCFGR9" description="GPIO port Q hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_HWCFGR8" description="GPIO port Q hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR7" description="GPIO port Q hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x22222222" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR6" description="GPIO port Q hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR5" description="GPIO port Q hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR4" description="GPIO port Q hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR3" description="GPIO port Q hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR2" description="GPIO port Q hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR1" description="GPIO port Q hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR0" description="GPIO port Q hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_VERR" description="GPIO port Q version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_IPIDR" description="GPIO port Q identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_SIDR" description="GPIO port Q size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOQ_S" description="General-purpose I/Os" start="0x56024000">
+    <Register name="GPIOQ_MODER" description="GPIO port Q mode register" start="+0x00" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+      <BitField name="MODE15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="General-purpose input mode" start="0x0" />
+        <Enum name="B_0x1" description="General-purpose output mode" start="0x1" />
+        <Enum name="B_0x2" description="Alternate function mode (refer to device datasheet for available options)" start="0x2" />
+        <Enum name="B_0x3" description="Analog mode (reset state)" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_OTYPER" description="GPIO port Q output type register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT1" description="Port x configuration I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT2" description="Port x configuration I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT3" description="Port x configuration I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT4" description="Port x configuration I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT5" description="Port x configuration I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT6" description="Port x configuration I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT7" description="Port x configuration I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT8" description="Port x configuration I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT9" description="Port x configuration I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT10" description="Port x configuration I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT11" description="Port x configuration I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT12" description="Port x configuration I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT13" description="Port x configuration I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT14" description="Port x configuration I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+      <BitField name="OT15" description="Port x configuration I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
+        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_OSPEEDR" description="GPIO port Q output speed register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+      <BitField name="OSPEED15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Low speed" start="0x0" />
+        <Enum name="B_0x1" description="Medium speed" start="0x1" />
+        <Enum name="B_0x2" description="High speed" start="0x2" />
+        <Enum name="B_0x3" description="Very high speed" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PUPDR" description="GPIO port Q pull-up/pull-down register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="Port x configuration I/O pin y" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD1" description="Port x configuration I/O pin y" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD2" description="Port x configuration I/O pin y" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD3" description="Port x configuration I/O pin y" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD4" description="Port x configuration I/O pin y" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD5" description="Port x configuration I/O pin y" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD6" description="Port x configuration I/O pin y" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD7" description="Port x configuration I/O pin y" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD8" description="Port x configuration I/O pin y" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD9" description="Port x configuration I/O pin y" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD10" description="Port x configuration I/O pin y" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD11" description="Port x configuration I/O pin y" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD12" description="Port x configuration I/O pin y" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD13" description="Port x configuration I/O pin y" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD14" description="Port x configuration I/O pin y" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="PUPD15" description="Port x configuration I/O pin y" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_IDR" description="GPIO port Q input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="ID0" description="Port x input data I/O pin y" start="0" size="1" access="ReadOnly" />
+      <BitField name="ID1" description="Port x input data I/O pin y" start="1" size="1" access="ReadOnly" />
+      <BitField name="ID2" description="Port x input data I/O pin y" start="2" size="1" access="ReadOnly" />
+      <BitField name="ID3" description="Port x input data I/O pin y" start="3" size="1" access="ReadOnly" />
+      <BitField name="ID4" description="Port x input data I/O pin y" start="4" size="1" access="ReadOnly" />
+      <BitField name="ID5" description="Port x input data I/O pin y" start="5" size="1" access="ReadOnly" />
+      <BitField name="ID6" description="Port x input data I/O pin y" start="6" size="1" access="ReadOnly" />
+      <BitField name="ID7" description="Port x input data I/O pin y" start="7" size="1" access="ReadOnly" />
+      <BitField name="ID8" description="Port x input data I/O pin y" start="8" size="1" access="ReadOnly" />
+      <BitField name="ID9" description="Port x input data I/O pin y" start="9" size="1" access="ReadOnly" />
+      <BitField name="ID10" description="Port x input data I/O pin y" start="10" size="1" access="ReadOnly" />
+      <BitField name="ID11" description="Port x input data I/O pin y" start="11" size="1" access="ReadOnly" />
+      <BitField name="ID12" description="Port x input data I/O pin y" start="12" size="1" access="ReadOnly" />
+      <BitField name="ID13" description="Port x input data I/O pin y" start="13" size="1" access="ReadOnly" />
+      <BitField name="ID14" description="Port x input data I/O pin y" start="14" size="1" access="ReadOnly" />
+      <BitField name="ID15" description="Port x input data I/O pin y" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_ODR" description="GPIO port Q output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port x output data I/O pin y" start="0" size="1" access="Read/Write" />
+      <BitField name="OD1" description="Port x output data I/O pin y" start="1" size="1" access="Read/Write" />
+      <BitField name="OD2" description="Port x output data I/O pin y" start="2" size="1" access="Read/Write" />
+      <BitField name="OD3" description="Port x output data I/O pin y" start="3" size="1" access="Read/Write" />
+      <BitField name="OD4" description="Port x output data I/O pin y" start="4" size="1" access="Read/Write" />
+      <BitField name="OD5" description="Port x output data I/O pin y" start="5" size="1" access="Read/Write" />
+      <BitField name="OD6" description="Port x output data I/O pin y" start="6" size="1" access="Read/Write" />
+      <BitField name="OD7" description="Port x output data I/O pin y" start="7" size="1" access="Read/Write" />
+      <BitField name="OD8" description="Port x output data I/O pin y" start="8" size="1" access="Read/Write" />
+      <BitField name="OD9" description="Port x output data I/O pin y" start="9" size="1" access="Read/Write" />
+      <BitField name="OD10" description="Port x output data I/O pin y" start="10" size="1" access="Read/Write" />
+      <BitField name="OD11" description="Port x output data I/O pin y" start="11" size="1" access="Read/Write" />
+      <BitField name="OD12" description="Port x output data I/O pin y" start="12" size="1" access="Read/Write" />
+      <BitField name="OD13" description="Port x output data I/O pin y" start="13" size="1" access="Read/Write" />
+      <BitField name="OD14" description="Port x output data I/O pin y" start="14" size="1" access="Read/Write" />
+      <BitField name="OD15" description="Port x output data I/O pin y" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_BSRR" description="GPIO port Q bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set I/O pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS1" description="Port x set I/O pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS2" description="Port x set I/O pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS3" description="Port x set I/O pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS4" description="Port x set I/O pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS5" description="Port x set I/O pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS6" description="Port x set I/O pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS7" description="Port x set I/O pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS8" description="Port x set I/O pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS9" description="Port x set I/O pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS10" description="Port x set I/O pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS11" description="Port x set I/O pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS12" description="Port x set I/O pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS13" description="Port x set I/O pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS14" description="Port x set I/O pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BS15" description="Port x set I/O pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Sets the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR0" description="Port x reset I/O pin y" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset I/O pin y" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset I/O pin y" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset I/O pin y" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset I/O pin y" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset I/O pin y" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset I/O pin y" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset I/O pin y" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset I/O pin y" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset I/O pin y" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset I/O pin y" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset I/O pin y" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset I/O pin y" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset I/O pin y" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset I/O pin y" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset I/O pin y" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODy bit" start="0x0" />
+        <Enum name="B_0x1" description="Resets the corresponding ODy bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_LCKR" description="GPIO port Q configuration lock register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock I/O pin y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK1" description="Port x lock I/O pin y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK2" description="Port x lock I/O pin y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK3" description="Port x lock I/O pin y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK4" description="Port x lock I/O pin y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK5" description="Port x lock I/O pin y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK6" description="Port x lock I/O pin y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK7" description="Port x lock I/O pin y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK8" description="Port x lock I/O pin y" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK9" description="Port x lock I/O pin y" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK10" description="Port x lock I/O pin y" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK11" description="Port x lock I/O pin y" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK12" description="Port x lock I/O pin y" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK13" description="Port x lock I/O pin y" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK14" description="Port x lock I/O pin y" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCK15" description="Port x lock I/O pin y" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
+      </BitField>
+      <BitField name="LCKK" description="Lock key" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
+        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_AFRL" description="GPIO port Q alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL1" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL2" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL3" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL4" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL5" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL6" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+      <BitField name="AFSEL7" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="AF0" start="0x0" />
+        <Enum name="B_0x1" description="AF1" start="0x1" />
+        <Enum name="B_0x2" description="AF2" start="0x2" />
+        <Enum name="B_0x3" description="AF3" start="0x3" />
+        <Enum name="B_0x4" description="AF4" start="0x4" />
+        <Enum name="B_0x5" description="AF5" start="0x5" />
+        <Enum name="B_0x6" description="AF6" start="0x6" />
+        <Enum name="B_0x7" description="AF7" start="0x7" />
+        <Enum name="B_0x8" description="AF8" start="0x8" />
+        <Enum name="B_0x9" description="AF9" start="0x9" />
+        <Enum name="B_0xA" description="AF10" start="0xA" />
+        <Enum name="B_0xB" description="AF11" start="0xB" />
+        <Enum name="B_0xC" description="AF12" start="0xC" />
+        <Enum name="B_0xD" description="AF13" start="0xD" />
+        <Enum name="B_0xE" description="AF14" start="0xE" />
+        <Enum name="B_0xF" description="AF15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_AFRH" description="GPIO port Q alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="Alternate function selection for port x I/O pin y" start="0" size="4" access="Read/Write" />
+      <BitField name="AFSEL9" description="Alternate function selection for port x I/O pin y" start="4" size="4" access="Read/Write" />
+      <BitField name="AFSEL10" description="Alternate function selection for port x I/O pin y" start="8" size="4" access="Read/Write" />
+      <BitField name="AFSEL11" description="Alternate function selection for port x I/O pin y" start="12" size="4" access="Read/Write" />
+      <BitField name="AFSEL12" description="Alternate function selection for port x I/O pin y" start="16" size="4" access="Read/Write" />
+      <BitField name="AFSEL13" description="Alternate function selection for port x I/O pin y" start="20" size="4" access="Read/Write" />
+      <BitField name="AFSEL14" description="Alternate function selection for port x I/O pin y" start="24" size="4" access="Read/Write" />
+      <BitField name="AFSEL15" description="Alternate function selection for port x I/O pin y" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_BRR" description="GPIO port Q bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BR0" description="Port x reset IO pin y" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR1" description="Port x reset IO pin y" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR2" description="Port x reset IO pin y" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR3" description="Port x reset IO pin y" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR4" description="Port x reset IO pin y" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR5" description="Port x reset IO pin y" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR6" description="Port x reset IO pin y" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR7" description="Port x reset IO pin y" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR8" description="Port x reset IO pin y" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR9" description="Port x reset IO pin y" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR10" description="Port x reset IO pin y" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR11" description="Port x reset IO pin y" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR12" description="Port x reset IO pin y" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR13" description="Port x reset IO pin y" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR14" description="Port x reset IO pin y" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+      <BitField name="BR15" description="Port x reset IO pin y" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
+        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_SECCFGR" description="GPIO port Q secure configuration register" start="+0x30" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="I/O pin y of Port x security configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="I/O pin y of Port x security configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="I/O pin y of Port x security configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I/O pin y of Port x security configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="I/O pin y of Port x security configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="I/O pin y of Port x security configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="I/O pin y of Port x security configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="I/O pin y of Port x security configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="I/O pin y of Port x security configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="I/O pin y of Port x security configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="I/O pin y of Port x security configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="I/O pin y of Port x security configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="I/O pin y of Port x security configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="I/O pin y of Port x security configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="I/O pin y of Port x security configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="I/O pin y of Port x security configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is non-secure. Secure access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is secure (see Table 70 for all corresponding secure bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PRIVCFGR" description="GPIO port Q privileged configuration register" start="+0x34" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="I/O pin y of Port x privilege configuration" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="I/O pin y of Port x privilege configuration" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="I/O pin y of Port x privilege configuration" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I/O pin y of Port x privilege configuration" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="I/O pin y of Port x privilege configuration" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="I/O pin y of Port x privilege configuration" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="I/O pin y of Port x privilege configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="I/O pin y of Port x privilege configuration" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="I/O pin y of Port x privilege configuration" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="I/O pin y of Port x privilege configuration" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="I/O pin y of Port x privilege configuration" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="I/O pin y of Port x privilege configuration" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="I/O pin y of Port x privilege configuration" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="I/O pin y of Port x privilege configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="I/O pin y of Port x privilege configuration" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="I/O pin y of Port x privilege configuration" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The I/O pin y is unprivileged. Privileged access is also possible." start="0x0" />
+        <Enum name="B_0x1" description="The I/O pin y is privileged only (see Table 70 for all corresponding protected bits)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_RCFGLOCKR" description="GPIO port Q resource configuration lock register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="I/O pin y of port x resource lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="I/O pin y of port x resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="I/O pin y of port x resource lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="I/O pin y of port x resource lock" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="I/O pin y of port x resource lock" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="I/O pin y of port x resource lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="I/O pin y of port x resource lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="I/O pin y of port x resource lock" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="I/O pin y of port x resource lock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="I/O pin y of port x resource lock" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="I/O pin y of port x resource lock" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="I/O pin y of port x resource lock" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="I/O pin y of port x resource lock" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="I/O pin y of port x resource lock" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="I/O pin y of port x resource lock" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="I/O pin y of port x resource lock" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_DELAYRL" description="GPIO port Q delay low register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY0" description="Port x IO pin y delay setup" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY1" description="Port x IO pin y delay setup" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY2" description="Port x IO pin y delay setup" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY3" description="Port x IO pin y delay setup" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY4" description="Port x IO pin y delay setup" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY5" description="Port x IO pin y delay setup" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY6" description="Port x IO pin y delay setup" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+      <BitField name="DELAY7" description="Port x IO pin y delay setup" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay 0.3 ns" start="0x1" />
+        <Enum name="B_0x2" description="Delay 0.5 ns" start="0x2" />
+        <Enum name="B_0x3" description="Delay 0.75 ns" start="0x3" />
+        <Enum name="B_0x4" description="Delay 1.0 ns" start="0x4" />
+        <Enum name="B_0x5" description="Delay 1.25 ns" start="0x5" />
+        <Enum name="B_0x6" description="Delay 1.5 ns" start="0x6" />
+        <Enum name="B_0x7" description="Delay 1.75 ns" start="0x7" />
+        <Enum name="B_0x8" description="Delay 2.0 ns" start="0x8" />
+        <Enum name="B_0x9" description="Delay 2.25 ns" start="0x9" />
+        <Enum name="B_0xA" description="Delay 2.5 ns" start="0xA" />
+        <Enum name="B_0xB" description="Delay 2.75 ns" start="0xB" />
+        <Enum name="B_0xC" description="Delay 3.0 ns" start="0xC" />
+        <Enum name="B_0xD" description="Delay 3.25 ns" start="0xD" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_DELAYRH" description="GPIO port Q delay high register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DELAY8" description="Port x I/O pin y delay setup" start="0" size="4" access="Read/Write" />
+      <BitField name="DELAY9" description="Port x I/O pin y delay setup" start="4" size="4" access="Read/Write" />
+      <BitField name="DELAY10" description="Port x I/O pin y delay setup" start="8" size="4" access="Read/Write" />
+      <BitField name="DELAY11" description="Port x I/O pin y delay setup" start="12" size="4" access="Read/Write" />
+      <BitField name="DELAY12" description="Port x I/O pin y delay setup" start="16" size="4" access="Read/Write" />
+      <BitField name="DELAY13" description="Port x I/O pin y delay setup" start="20" size="4" access="Read/Write" />
+      <BitField name="DELAY14" description="Port x I/O pin y delay setup" start="24" size="4" access="Read/Write" />
+      <BitField name="DELAY15" description="Port x I/O pin y delay setup" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_PIOCFGRL" description="GPIO port Q PIO control low register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG0" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG1" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG2" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG3" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG4" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG5" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG6" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+      <BitField name="PIOCFG7" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Input and output data are not synchronized or retimed on clock edges." start="0x0" />
+        <Enum name="B_0x1" description="Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_PIOCFGRH" description="GPIO port Q PIO control high register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PIOCFG8" description="Port x I/O pin y configuration" start="0" size="4" access="Read/Write" />
+      <BitField name="PIOCFG9" description="Port x I/O pin y configuration" start="4" size="4" access="Read/Write" />
+      <BitField name="PIOCFG10" description="Port x I/O pin y configuration" start="8" size="4" access="Read/Write" />
+      <BitField name="PIOCFG11" description="Port x I/O pin y configuration" start="12" size="4" access="Read/Write" />
+      <BitField name="PIOCFG12" description="Port x I/O pin y configuration" start="16" size="4" access="Read/Write" />
+      <BitField name="PIOCFG13" description="Port x I/O pin y configuration" start="20" size="4" access="Read/Write" />
+      <BitField name="PIOCFG14" description="Port x I/O pin y configuration" start="24" size="4" access="Read/Write" />
+      <BitField name="PIOCFG15" description="Port x I/O pin y configuration" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR10" description="GPIO port Q hardware configuration register 10" start="+0x3C8" size="4" reset_value="0x00011140" reset_mask="0xFFFFFFFF">
+      <BitField name="AHB_IOP" description="Bus interface selection" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="AHB" start="0x0" />
+        <Enum name="B_0x1" description="IOP" start="0x1" />
+      </BitField>
+      <BitField name="AFSIZE_CFG" description="Number of AF available for each I/O (accepted value: 1 to 4)" start="4" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="One AF/IO" start="0x1" />
+      </BitField>
+      <BitField name="SPEED_CFG" description="Number of speed lines for each I/O" start="8" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="One line" start="0x0" />
+        <Enum name="B_0x1" description="Two lines" start="0x1" />
+      </BitField>
+      <BitField name="LOCK_CFG" description="Lock mechanism activation" start="12" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="SEC_CFG" description="Security activation" start="16" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+      <BitField name="OR_CFG" description="Option register configuration" start="20" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-active" start="0x0" />
+        <Enum name="B_0x1" description="Active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_HWCFGR9" description="GPIO port Q hardware configuration register 9" start="+0x3CC" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_IO" description="Presence granularity, each bit indicate the I/O presence" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="I/O not present" start="0x0" />
+        <Enum name="B_0x1" description="I/O present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="GPIOQ_HWCFGR8" description="GPIO port Q hardware configuration register 8" start="+0x3D0" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO8" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO9" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO10" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO11" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO12" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO13" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO14" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO15" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR7" description="GPIO port Q hardware configuration register 7" start="+0x3D4" size="4" reset_value="0x22222222" reset_mask="0xFFFFFFFF">
+      <BitField name="FAST_AF_IO0" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="0" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO1" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="4" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO2" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="8" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO3" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="12" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO4" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="16" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO5" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="20" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO6" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="24" size="4" access="ReadOnly" />
+      <BitField name="FAST_AF_IO7" description="Indicate which is the fastest AF for I/Oy (0 to F)" start="28" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR6" description="GPIO port Q hardware configuration register 6" start="+0x3D8" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODER_RES" description="MODER register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR5" description="GPIO port Q hardware configuration register 5" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPDR_RES" description="Pull-up/pull-down register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR4" description="GPIO port Q hardware configuration register 4" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED_RES" description="OSPEED register reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR3" description="GPIO port Q hardware configuration register 3" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ODR_RES" description="Output data register reset value" start="0" size="16" access="ReadOnly" />
+      <BitField name="OTYPER_RES" description="Output type register reset value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR2" description="GPIO port Q hardware configuration register 2" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRL_RES" description="AF register low reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR1" description="GPIO port Q hardware configuration register 1" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFRH_RES" description="AF register high reset value" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_HWCFGR0" description="GPIO port Q hardware configuration register 0" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OR_RES" description="Option register reset value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_VERR" description="GPIO port Q version register" start="+0x3F4" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="MINREV" description="GPIO minor revision" start="0" size="4" access="ReadOnly" />
+      <BitField name="MAJREV" description="GPIO major revision" start="4" size="4" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_IPIDR" description="GPIO port Q identification register" start="+0x3F8" size="4" reset_value="0x000F0004" reset_mask="0xFFFFFFFF">
+      <BitField name="IPID" description="GPIO identifier" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="GPIOQ_SIDR" description="GPIO port Q size identification register" start="+0x3FC" size="4" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="SID" description="Size of the memory region allocated to GPIO registers" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HASH" description="HASH register bank (full SHA-2/SHA-3)" start="0x44020400">
+    <Register name="HASH_CR" description="HASH control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialize message digest calculation" start="2" size="1" access="Read/Write" />
+      <BitField name="DMAE" description="DMA enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA transfers disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA transfers enabled. A DMA request is sent as soon as the hash core is ready to receive data." start="0x1" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="32-bit data. The data written into HASH_DIN are directly used by the HASH processing, without reordering." start="0x0" />
+        <Enum name="B_0x1" description="16-bit data or half-word. The data written into HASH_DIN are considered as two half-words, and are swapped before being used by the HASH processing." start="0x1" />
+        <Enum name="B_0x2" description="8-bit data or bytes. The data written into HASH_DIN are considered as four bytes, and are swapped before being used by the HASH processing." start="0x2" />
+        <Enum name="B_0x3" description="bit data or bit string. The data written into HASH_DIN are considered as 32 bits (1st bit of the string at position 0), and are swapped before being used by the HASH processing (1st bit of the string at position 31)." start="0x3" />
+      </BitField>
+      <BitField name="MODE" description="Mode selection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hash mode selected" start="0x0" />
+        <Enum name="B_0x1" description="HMAC mode selected. LKEY bit must be set if the key being used is longer than the algorithm block size." start="0x1" />
+      </BitField>
+      <BitField name="NBW" description="Number of words already pushed" start="8" size="4" access="ReadOnly" />
+      <BitField name="DINNE" description="DIN not empty" start="12" size="1" access="ReadOnly" />
+      <BitField name="MDMAT" description="Multiple DMA transfers " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCAL is automatically set at the end of a DMA transfer." start="0x0" />
+        <Enum name="B_0x1" description="DCAL is not automatically set at the end of a DMA transfer." start="0x1" />
+      </BitField>
+      <BitField name="LKEY" description="Long key selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HMAC key is shorter or equal to the block size (short key). The actual key value written in HASH_DIN is used during the HMAC computation." start="0x0" />
+        <Enum name="B_0x1" description="HMAC key is longer than the block size (long key). The hash of the key is used instead of the real key during the HMAC computation." start="0x1" />
+      </BitField>
+      <BitField name="ALGO" description="Algorithm selection" start="17" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="SHA-1" start="0x0" />
+        <Enum name="B_0x2" description="SHA2-224" start="0x2" />
+        <Enum name="B_0x3" description="SHA2-256" start="0x3" />
+        <Enum name="B_0xC" description="SHA2-384" start="0xC" />
+        <Enum name="B_0xD" description="SHA2-512/224" start="0xD" />
+        <Enum name="B_0xE" description="SHA2-512/256" start="0xE" />
+        <Enum name="B_0xF" description="SHA2-512" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="HASH_DIN" description="HASH data input register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAIN" description="Data input" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="HASH_STR" description="HASH start register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NBLW" description="Number of valid bits in the last word" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="All the 32 bits of the last data written are valid message bits, that is M[31:0]" start="0x00" />
+        <Enum name="B_0x01" description="Only one bit of the last data written (after swapping) is valid, that is M[0]" start="0x01" />
+        <Enum name="B_0x02" description="Only two bits of the last data written (after swapping) are valid, that is M[1:0]" start="0x02" />
+        <Enum name="B_0x03" description="Only three bits of the last data written (after swapping) are valid that is M[2:0]" start="0x03" />
+        <Enum name="B_0x1F" description="Only 31 bits of the last data written (after swapping) are valid that is M[30:0]" start="0x1F" />
+      </BitField>
+      <BitField name="DCAL" description="Digest calculation" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="HASH_HRA0" description="HASH aliased digest register 0" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H0" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA1" description="HASH aliased digest register 1" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H1" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA2" description="HASH aliased digest register 2" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H2" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA3" description="HASH aliased digest register 3" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H3" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA4" description="HASH aliased digest register 4" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H4" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_IMR" description="HASH interrupt enable register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DINIE" description="Data input interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data input interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data input interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCIE" description="Digest calculation completion interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Digest calculation completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digest calculation completion interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HASH_SR" description="HASH status register" start="+0x24" size="4" reset_value="0x00110001" reset_mask="0xFFFFFFFF">
+      <BitField name="DINIS" description="Data input interrupt status" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Less than 16 locations are free in the input buffer" start="0x0" />
+        <Enum name="B_0x1" description="A new block can be entered into the input buffer. An interrupt is generated if the DINIE bit is set in the HASH_IMR register." start="0x1" />
+      </BitField>
+      <BitField name="DCIS" description="Digest calculation completion interrupt status" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No digest available in the HASH_HRx registers (zeros are returned)" start="0x0" />
+        <Enum name="B_0x1" description="Digest calculation complete, a digest is available in the HASH_HRx registers. An interrupt is generated if the DCIE bit is set in the HASH_IMR register." start="0x1" />
+      </BitField>
+      <BitField name="DMAS" description="DMA Status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DMA interface is disabled (DMAE = 0) and no transfer is ongoing" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface is enabled (DMAE = 1) or a transfer is ongoing" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy bit" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No block is currently being processed" start="0x0" />
+        <Enum name="B_0x1" description="The hash core is processing a block of data" start="0x1" />
+      </BitField>
+      <BitField name="NBWP" description="Number of words already pushed" start="9" size="5" access="ReadOnly" />
+      <BitField name="DINNE" description="DIN not empty" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data are present in the data input buffer" start="0x0" />
+        <Enum name="B_0x1" description="The input buffer contains at least one word of data" start="0x1" />
+      </BitField>
+      <BitField name="NBWE" description="Number of words expected" start="16" size="5" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_CSR0" description="HASH context swap register 0" start="+0xF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS0" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR1" description="HASH context swap register 1" start="+0xFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS1" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR2" description="HASH context swap register 2" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS2" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR3" description="HASH context swap register 3" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS3" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR4" description="HASH context swap register 4" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS4" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR5" description="HASH context swap register 5" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS5" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR6" description="HASH context swap register 6" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS6" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR7" description="HASH context swap register 7" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS7" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR8" description="HASH context swap register 8" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS8" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR9" description="HASH context swap register 9" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS9" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR10" description="HASH context swap register 10" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS10" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR11" description="HASH context swap register 11" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS11" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR12" description="HASH context swap register 12" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS12" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR13" description="HASH context swap register 13" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS13" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR14" description="HASH context swap register 14" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS14" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR15" description="HASH context swap register 15" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS15" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR16" description="HASH context swap register 16" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS16" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR17" description="HASH context swap register 17" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS17" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR18" description="HASH context swap register 18" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS18" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR19" description="HASH context swap register 19" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS19" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR20" description="HASH context swap register 20" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS20" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR21" description="HASH context swap register 21" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS21" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR22" description="HASH context swap register 22" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS22" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR23" description="HASH context swap register 23" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS23" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR24" description="HASH context swap register 24" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS24" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR25" description="HASH context swap register 25" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS25" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR26" description="HASH context swap register 26" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS26" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR27" description="HASH context swap register 27" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS27" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR28" description="HASH context swap register 28" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS28" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR29" description="HASH context swap register 29" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS29" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR30" description="HASH context swap register 30" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS30" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR31" description="HASH context swap register 31" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS31" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR32" description="HASH context swap register 32" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS32" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR33" description="HASH context swap register 33" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS33" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR34" description="HASH context swap register 34" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS34" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR35" description="HASH context swap register 35" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS35" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR36" description="HASH context swap register 36" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS36" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR37" description="HASH context swap register 37" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS37" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR38" description="HASH context swap register 38" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS38" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR39" description="HASH context swap register 39" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS39" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR40" description="HASH context swap register 40" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS40" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR41" description="HASH context swap register 41" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS41" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR42" description="HASH context swap register 42" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS42" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR43" description="HASH context swap register 43" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS43" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR44" description="HASH context swap register 44" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS44" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR45" description="HASH context swap register 45" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS45" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR46" description="HASH context swap register 46" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS46" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR47" description="HASH context swap register 47" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS47" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR48" description="HASH context swap register 48" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS48" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR49" description="HASH context swap register 49" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS49" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR50" description="HASH context swap register 50" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS50" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR51" description="HASH context swap register 51" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS51" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR52" description="HASH context swap register 52" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS52" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR53" description="HASH context swap register 53" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS53" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR54" description="HASH context swap register 54" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS54" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR55" description="HASH context swap register 55" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS55" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR56" description="HASH context swap register 56" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS56" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR57" description="HASH context swap register 57" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS57" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR58" description="HASH context swap register 58" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS58" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR59" description="HASH context swap register 59" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS59" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR60" description="HASH context swap register 60" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS60" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR61" description="HASH context swap register 61" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS61" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR62" description="HASH context swap register 62" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS62" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR63" description="HASH context swap register 63" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS63" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR64" description="HASH context swap register 64" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS64" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR65" description="HASH context swap register 65" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS65" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR66" description="HASH context swap register 66" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS66" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR67" description="HASH context swap register 67" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS67" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR68" description="HASH context swap register 68" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS68" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR69" description="HASH context swap register 69" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS69" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR70" description="HASH context swap register 70" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS70" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR71" description="HASH context swap register 71" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS71" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR72" description="HASH context swap register 72" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS72" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR73" description="HASH context swap register 73" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS73" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR74" description="HASH context swap register 74" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS74" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR75" description="HASH context swap register 75" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS75" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR76" description="HASH context swap register 76" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS76" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR77" description="HASH context swap register 77" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS77" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR78" description="HASH context swap register 78" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS78" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR79" description="HASH context swap register 79" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS79" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR80" description="HASH context swap register 80" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS80" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR81" description="HASH context swap register 81" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS81" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR82" description="HASH context swap register 82" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS82" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR83" description="HASH context swap register 83" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS83" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR84" description="HASH context swap register 84" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS84" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR85" description="HASH context swap register 85" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS85" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR86" description="HASH context swap register 86" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS86" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR87" description="HASH context swap register 87" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS87" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR88" description="HASH context swap register 88" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS88" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR89" description="HASH context swap register 89" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS89" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR90" description="HASH context swap register 90" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS90" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR91" description="HASH context swap register 91" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS91" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR92" description="HASH context swap register 92" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS92" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR93" description="HASH context swap register 93" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS93" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR94" description="HASH context swap register 94" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS94" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR95" description="HASH context swap register 95" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS95" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR96" description="HASH context swap register 96" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS96" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR97" description="HASH context swap register 97" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS97" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR98" description="HASH context swap register 98" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS98" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR99" description="HASH context swap register 99" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS99" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR100" description="HASH context swap register 100" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS100" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR101" description="HASH context swap register 101" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS101" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR102" description="HASH context swap register 102" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS102" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_HR0" description="HASH digest register 0" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H0" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR1" description="HASH digest register 1" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H1" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR2" description="HASH digest register 2" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H2" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR3" description="HASH digest register 3" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H3" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR4" description="HASH digest register 4" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H4" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR5" description="HASH supplementary digest register 5" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H5" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR6" description="HASH supplementary digest register 6" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H6" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR7" description="HASH supplementary digest register 7" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H7" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR8" description="HASH supplementary digest register 8" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H8" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR9" description="HASH supplementary digest register 9" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H9" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR10" description="HASH supplementary digest register 10" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H10" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR11" description="HASH supplementary digest register 11" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H11" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR12" description="HASH supplementary digest register 12" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H12" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR13" description="HASH supplementary digest register 13" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H13" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR14" description="HASH supplementary digest register 14" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H14" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR15" description="HASH supplementary digest register 15" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H15" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HASH_S" description="HASH register bank (full SHA-2/SHA-3)" start="0x54020400">
+    <Register name="HASH_CR" description="HASH control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialize message digest calculation" start="2" size="1" access="Read/Write" />
+      <BitField name="DMAE" description="DMA enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA transfers disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA transfers enabled. A DMA request is sent as soon as the hash core is ready to receive data." start="0x1" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="32-bit data. The data written into HASH_DIN are directly used by the HASH processing, without reordering." start="0x0" />
+        <Enum name="B_0x1" description="16-bit data or half-word. The data written into HASH_DIN are considered as two half-words, and are swapped before being used by the HASH processing." start="0x1" />
+        <Enum name="B_0x2" description="8-bit data or bytes. The data written into HASH_DIN are considered as four bytes, and are swapped before being used by the HASH processing." start="0x2" />
+        <Enum name="B_0x3" description="bit data or bit string. The data written into HASH_DIN are considered as 32 bits (1st bit of the string at position 0), and are swapped before being used by the HASH processing (1st bit of the string at position 31)." start="0x3" />
+      </BitField>
+      <BitField name="MODE" description="Mode selection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hash mode selected" start="0x0" />
+        <Enum name="B_0x1" description="HMAC mode selected. LKEY bit must be set if the key being used is longer than the algorithm block size." start="0x1" />
+      </BitField>
+      <BitField name="NBW" description="Number of words already pushed" start="8" size="4" access="ReadOnly" />
+      <BitField name="DINNE" description="DIN not empty" start="12" size="1" access="ReadOnly" />
+      <BitField name="MDMAT" description="Multiple DMA transfers " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCAL is automatically set at the end of a DMA transfer." start="0x0" />
+        <Enum name="B_0x1" description="DCAL is not automatically set at the end of a DMA transfer." start="0x1" />
+      </BitField>
+      <BitField name="LKEY" description="Long key selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HMAC key is shorter or equal to the block size (short key). The actual key value written in HASH_DIN is used during the HMAC computation." start="0x0" />
+        <Enum name="B_0x1" description="HMAC key is longer than the block size (long key). The hash of the key is used instead of the real key during the HMAC computation." start="0x1" />
+      </BitField>
+      <BitField name="ALGO" description="Algorithm selection" start="17" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="SHA-1" start="0x0" />
+        <Enum name="B_0x2" description="SHA2-224" start="0x2" />
+        <Enum name="B_0x3" description="SHA2-256" start="0x3" />
+        <Enum name="B_0xC" description="SHA2-384" start="0xC" />
+        <Enum name="B_0xD" description="SHA2-512/224" start="0xD" />
+        <Enum name="B_0xE" description="SHA2-512/256" start="0xE" />
+        <Enum name="B_0xF" description="SHA2-512" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="HASH_DIN" description="HASH data input register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAIN" description="Data input" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="HASH_STR" description="HASH start register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NBLW" description="Number of valid bits in the last word" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="All the 32 bits of the last data written are valid message bits, that is M[31:0]" start="0x00" />
+        <Enum name="B_0x01" description="Only one bit of the last data written (after swapping) is valid, that is M[0]" start="0x01" />
+        <Enum name="B_0x02" description="Only two bits of the last data written (after swapping) are valid, that is M[1:0]" start="0x02" />
+        <Enum name="B_0x03" description="Only three bits of the last data written (after swapping) are valid that is M[2:0]" start="0x03" />
+        <Enum name="B_0x1F" description="Only 31 bits of the last data written (after swapping) are valid that is M[30:0]" start="0x1F" />
+      </BitField>
+      <BitField name="DCAL" description="Digest calculation" start="8" size="1" access="Read/Write" />
+    </Register>
+    <Register name="HASH_HRA0" description="HASH aliased digest register 0" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H0" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA1" description="HASH aliased digest register 1" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H1" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA2" description="HASH aliased digest register 2" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H2" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA3" description="HASH aliased digest register 3" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H3" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HRA4" description="HASH aliased digest register 4" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H4" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_IMR" description="HASH interrupt enable register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DINIE" description="Data input interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data input interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data input interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCIE" description="Digest calculation completion interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Digest calculation completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digest calculation completion interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HASH_SR" description="HASH status register" start="+0x24" size="4" reset_value="0x00110001" reset_mask="0xFFFFFFFF">
+      <BitField name="DINIS" description="Data input interrupt status" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Less than 16 locations are free in the input buffer" start="0x0" />
+        <Enum name="B_0x1" description="A new block can be entered into the input buffer. An interrupt is generated if the DINIE bit is set in the HASH_IMR register." start="0x1" />
+      </BitField>
+      <BitField name="DCIS" description="Digest calculation completion interrupt status" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No digest available in the HASH_HRx registers (zeros are returned)" start="0x0" />
+        <Enum name="B_0x1" description="Digest calculation complete, a digest is available in the HASH_HRx registers. An interrupt is generated if the DCIE bit is set in the HASH_IMR register." start="0x1" />
+      </BitField>
+      <BitField name="DMAS" description="DMA Status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DMA interface is disabled (DMAE = 0) and no transfer is ongoing" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface is enabled (DMAE = 1) or a transfer is ongoing" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy bit" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No block is currently being processed" start="0x0" />
+        <Enum name="B_0x1" description="The hash core is processing a block of data" start="0x1" />
+      </BitField>
+      <BitField name="NBWP" description="Number of words already pushed" start="9" size="5" access="ReadOnly" />
+      <BitField name="DINNE" description="DIN not empty" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No data are present in the data input buffer" start="0x0" />
+        <Enum name="B_0x1" description="The input buffer contains at least one word of data" start="0x1" />
+      </BitField>
+      <BitField name="NBWE" description="Number of words expected" start="16" size="5" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_CSR0" description="HASH context swap register 0" start="+0xF8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS0" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR1" description="HASH context swap register 1" start="+0xFC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS1" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR2" description="HASH context swap register 2" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS2" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR3" description="HASH context swap register 3" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS3" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR4" description="HASH context swap register 4" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS4" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR5" description="HASH context swap register 5" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS5" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR6" description="HASH context swap register 6" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS6" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR7" description="HASH context swap register 7" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS7" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR8" description="HASH context swap register 8" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS8" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR9" description="HASH context swap register 9" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS9" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR10" description="HASH context swap register 10" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS10" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR11" description="HASH context swap register 11" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS11" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR12" description="HASH context swap register 12" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS12" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR13" description="HASH context swap register 13" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS13" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR14" description="HASH context swap register 14" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS14" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR15" description="HASH context swap register 15" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS15" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR16" description="HASH context swap register 16" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS16" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR17" description="HASH context swap register 17" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS17" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR18" description="HASH context swap register 18" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS18" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR19" description="HASH context swap register 19" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS19" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR20" description="HASH context swap register 20" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS20" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR21" description="HASH context swap register 21" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS21" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR22" description="HASH context swap register 22" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS22" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR23" description="HASH context swap register 23" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS23" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR24" description="HASH context swap register 24" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS24" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR25" description="HASH context swap register 25" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS25" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR26" description="HASH context swap register 26" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS26" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR27" description="HASH context swap register 27" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS27" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR28" description="HASH context swap register 28" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS28" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR29" description="HASH context swap register 29" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS29" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR30" description="HASH context swap register 30" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS30" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR31" description="HASH context swap register 31" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS31" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR32" description="HASH context swap register 32" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS32" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR33" description="HASH context swap register 33" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS33" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR34" description="HASH context swap register 34" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS34" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR35" description="HASH context swap register 35" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS35" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR36" description="HASH context swap register 36" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS36" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR37" description="HASH context swap register 37" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS37" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR38" description="HASH context swap register 38" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS38" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR39" description="HASH context swap register 39" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS39" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR40" description="HASH context swap register 40" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS40" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR41" description="HASH context swap register 41" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS41" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR42" description="HASH context swap register 42" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS42" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR43" description="HASH context swap register 43" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS43" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR44" description="HASH context swap register 44" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS44" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR45" description="HASH context swap register 45" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS45" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR46" description="HASH context swap register 46" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS46" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR47" description="HASH context swap register 47" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS47" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR48" description="HASH context swap register 48" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS48" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR49" description="HASH context swap register 49" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS49" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR50" description="HASH context swap register 50" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS50" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR51" description="HASH context swap register 51" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS51" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR52" description="HASH context swap register 52" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS52" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR53" description="HASH context swap register 53" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS53" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR54" description="HASH context swap register 54" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS54" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR55" description="HASH context swap register 55" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS55" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR56" description="HASH context swap register 56" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS56" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR57" description="HASH context swap register 57" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS57" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR58" description="HASH context swap register 58" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS58" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR59" description="HASH context swap register 59" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS59" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR60" description="HASH context swap register 60" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS60" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR61" description="HASH context swap register 61" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS61" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR62" description="HASH context swap register 62" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS62" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR63" description="HASH context swap register 63" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS63" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR64" description="HASH context swap register 64" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS64" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR65" description="HASH context swap register 65" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS65" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR66" description="HASH context swap register 66" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS66" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR67" description="HASH context swap register 67" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS67" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR68" description="HASH context swap register 68" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS68" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR69" description="HASH context swap register 69" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS69" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR70" description="HASH context swap register 70" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS70" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR71" description="HASH context swap register 71" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS71" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR72" description="HASH context swap register 72" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS72" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR73" description="HASH context swap register 73" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS73" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR74" description="HASH context swap register 74" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS74" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR75" description="HASH context swap register 75" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS75" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR76" description="HASH context swap register 76" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS76" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR77" description="HASH context swap register 77" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS77" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR78" description="HASH context swap register 78" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS78" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR79" description="HASH context swap register 79" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS79" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR80" description="HASH context swap register 80" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS80" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR81" description="HASH context swap register 81" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS81" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR82" description="HASH context swap register 82" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS82" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR83" description="HASH context swap register 83" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS83" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR84" description="HASH context swap register 84" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS84" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR85" description="HASH context swap register 85" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS85" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR86" description="HASH context swap register 86" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS86" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR87" description="HASH context swap register 87" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS87" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR88" description="HASH context swap register 88" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS88" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR89" description="HASH context swap register 89" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS89" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR90" description="HASH context swap register 90" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS90" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR91" description="HASH context swap register 91" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS91" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR92" description="HASH context swap register 92" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS92" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR93" description="HASH context swap register 93" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS93" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR94" description="HASH context swap register 94" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS94" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR95" description="HASH context swap register 95" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS95" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR96" description="HASH context swap register 96" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS96" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR97" description="HASH context swap register 97" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS97" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR98" description="HASH context swap register 98" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS98" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR99" description="HASH context swap register 99" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS99" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR100" description="HASH context swap register 100" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS100" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR101" description="HASH context swap register 101" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS101" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_CSR102" description="HASH context swap register 102" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CS102" description="Context swap x" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HASH_HR0" description="HASH digest register 0" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H0" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR1" description="HASH digest register 1" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H1" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR2" description="HASH digest register 2" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H2" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR3" description="HASH digest register 3" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H3" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR4" description="HASH digest register 4" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H4" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR5" description="HASH supplementary digest register 5" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H5" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR6" description="HASH supplementary digest register 6" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H6" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR7" description="HASH supplementary digest register 7" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H7" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR8" description="HASH supplementary digest register 8" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H8" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR9" description="HASH supplementary digest register 9" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H9" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR10" description="HASH supplementary digest register 10" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H10" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR11" description="HASH supplementary digest register 11" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H11" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR12" description="HASH supplementary digest register 12" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H12" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR13" description="HASH supplementary digest register 13" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H13" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR14" description="HASH supplementary digest register 14" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H14" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="HASH_HR15" description="HASH supplementary digest register 15" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="H15" description="Hash data x" start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HDP" description="Hardware debug port" start="0x46000800">
+    <Register name="HDP_CTRL" description="HDP control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable HDP, valid if enabled in BSEC" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="HDP_MUX" description="HDP multiplexer control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MUX0" description="Select the HDPy output among the 16 available signals" start="0" size="4" access="Read/Write" />
+      <BitField name="MUX1" description="Select the HDPy output among the 16 available signals" start="4" size="4" access="Read/Write" />
+      <BitField name="MUX2" description="Select the HDPy output among the 16 available signals" start="8" size="4" access="Read/Write" />
+      <BitField name="MUX3" description="Select the HDPy output among the 16 available signals" start="12" size="4" access="Read/Write" />
+      <BitField name="MUX4" description="Select the HDPy output among the 16 available signals" start="16" size="4" access="Read/Write" />
+      <BitField name="MUX5" description="Select the HDPy output among the 16 available signals" start="20" size="4" access="Read/Write" />
+      <BitField name="MUX6" description="Select the HDPy output among the 16 available signals" start="24" size="4" access="Read/Write" />
+      <BitField name="MUX7" description="Select the HDPy output among the 16 available signals" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="HDP_VAL" description="HDP read back value register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPVAL" description="Value of the HDP signals" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="HDP_GPOSET" description="HDP general-purpose output set register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOSET" description="When a bit is written to 1, the corresponding HDP GPO is set" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="HDP_GPOCLR" description="HDP general purpose output clear register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOCLR" description="When a bit is written to 1, the corresponding HDP GPO is cleared." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="HDP_GPOVAL" description="HDP general purpose output value register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOVAL" description="When written, define the value of the HDP GPO." start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HDP_S" description="Hardware debug port" start="0x56000800">
+    <Register name="HDP_CTRL" description="HDP control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable HDP, valid if enabled in BSEC" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="HDP_MUX" description="HDP multiplexer control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MUX0" description="Select the HDPy output among the 16 available signals" start="0" size="4" access="Read/Write" />
+      <BitField name="MUX1" description="Select the HDPy output among the 16 available signals" start="4" size="4" access="Read/Write" />
+      <BitField name="MUX2" description="Select the HDPy output among the 16 available signals" start="8" size="4" access="Read/Write" />
+      <BitField name="MUX3" description="Select the HDPy output among the 16 available signals" start="12" size="4" access="Read/Write" />
+      <BitField name="MUX4" description="Select the HDPy output among the 16 available signals" start="16" size="4" access="Read/Write" />
+      <BitField name="MUX5" description="Select the HDPy output among the 16 available signals" start="20" size="4" access="Read/Write" />
+      <BitField name="MUX6" description="Select the HDPy output among the 16 available signals" start="24" size="4" access="Read/Write" />
+      <BitField name="MUX7" description="Select the HDPy output among the 16 available signals" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="HDP_VAL" description="HDP read back value register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPVAL" description="Value of the HDP signals" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="HDP_GPOSET" description="HDP general-purpose output set register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOSET" description="When a bit is written to 1, the corresponding HDP GPO is set" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="HDP_GPOCLR" description="HDP general purpose output clear register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOCLR" description="When a bit is written to 1, the corresponding HDP GPO is cleared." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="HDP_GPOVAL" description="HDP general purpose output value register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPGPOVAL" description="When written, define the value of the HDP GPO." start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HPDMA" description="High-performance direct memory access controller" start="0x48020000">
+    <Register name="HPDMA_SECCFGR" description="HPDMA secure configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="secure state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="secure state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="secure state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="secure state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="secure state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="secure state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="secure state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="secure state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="secure state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="secure state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="secure state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="secure state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="secure state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="secure state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="secure state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="secure state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_PRIVCFGR" description="HPDMA privileged configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_RCFGLOCKR" description="HPDMA configuration lock register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK0" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK1" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK2" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK3" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK4" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK5" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK6" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK7" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK8" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK9" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK10" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK11" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK12" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK13" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK14" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK15" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_MISR" description="HPDMA non-secure masked interrupt status register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_SMISR" description="HPDMA secure masked interrupt status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of the secure channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of the secure channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of the secure channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of the secure channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of the secure channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of the secure channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of the secure channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of the secure channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of the secure channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of the secure channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of the secure channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of the secure channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of the secure channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of the secure channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of the secure channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of the secure channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0LBAR" description="HPDMA channel 0 linked-list base address register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0CIDCFGR" description="HPDMA channel 0 CID register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0SEMCR" description="HPDMA channel 0 semaphore control register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0FCR" description="HPDMA channel 0 flag clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0SR" description="HPDMA channel 0 status register" start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C0CR" description="HPDMA channel 0 control register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0TR1" description="HPDMA channel 0 transfer register 1" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0TR2" description="HPDMA channel 0 transfer register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0BR1" description="HPDMA channel 0 block register 1" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0SAR" description="HPDMA channel 0 source address register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0DAR" description="HPDMA channel 0 destination address register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0LLR" description="HPDMA channel 0 linked-list address register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1LBAR" description="HPDMA channel 1 linked-list base address register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1CIDCFGR" description="HPDMA channel 1 CID register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1SEMCR" description="HPDMA channel 1 semaphore control register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1FCR" description="HPDMA channel 1 flag clear register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1SR" description="HPDMA channel 1 status register" start="+0xE0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C1CR" description="HPDMA channel 1 control register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1TR1" description="HPDMA channel 1 transfer register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1TR2" description="HPDMA channel 1 transfer register 2" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1BR1" description="HPDMA channel 1 block register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1SAR" description="HPDMA channel 1 source address register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1DAR" description="HPDMA channel 1 destination address register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1LLR" description="HPDMA channel 1 linked-list address register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2LBAR" description="HPDMA channel 2 linked-list base address register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2CIDCFGR" description="HPDMA channel 2 CID register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2SEMCR" description="HPDMA channel 2 semaphore control register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2FCR" description="HPDMA channel 2 flag clear register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2SR" description="HPDMA channel 2 status register" start="+0x160" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C2CR" description="HPDMA channel 2 control register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2TR1" description="HPDMA channel 2 transfer register 1" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2TR2" description="HPDMA channel 2 transfer register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2BR1" description="HPDMA channel 2 block register 1" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2SAR" description="HPDMA channel 2 source address register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2DAR" description="HPDMA channel 2 destination address register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2LLR" description="HPDMA channel 2 linked-list address register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3LBAR" description="HPDMA channel 3 linked-list base address register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3CIDCFGR" description="HPDMA channel 3 CID register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3SEMCR" description="HPDMA channel 3 semaphore control register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3FCR" description="HPDMA channel 3 flag clear register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3SR" description="HPDMA channel 3 status register" start="+0x1E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C3CR" description="HPDMA channel 3 control register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3TR1" description="HPDMA channel 3 transfer register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3TR2" description="HPDMA channel 3 transfer register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3BR1" description="HPDMA channel 3 block register 1" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3SAR" description="HPDMA channel 3 source address register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3DAR" description="HPDMA channel 3 destination address register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3LLR" description="HPDMA channel 3 linked-list address register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4LBAR" description="HPDMA channel 4 linked-list base address register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4CIDCFGR" description="HPDMA channel 4 CID register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4SEMCR" description="HPDMA channel 4 semaphore control register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4FCR" description="HPDMA channel 4 flag clear register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4SR" description="HPDMA channel 4 status register" start="+0x260" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C4CR" description="HPDMA channel 4 control register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4TR1" description="HPDMA channel 4 transfer register 1" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4TR2" description="HPDMA channel 4 transfer register 2" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4BR1" description="HPDMA channel 4 block register 1" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4SAR" description="HPDMA channel 4 source address register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4DAR" description="HPDMA channel 4 destination address register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4LLR" description="HPDMA channel 4 linked-list address register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5LBAR" description="HPDMA channel 5 linked-list base address register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5CIDCFGR" description="HPDMA channel 5 CID register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5SEMCR" description="HPDMA channel 5 semaphore control register" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5FCR" description="HPDMA channel 5 flag clear register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5SR" description="HPDMA channel 5 status register" start="+0x2E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C5CR" description="HPDMA channel 5 control register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5TR1" description="HPDMA channel 5 transfer register 1" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5TR2" description="HPDMA channel 5 transfer register 2" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5BR1" description="HPDMA channel 5 block register 1" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5SAR" description="HPDMA channel 5 source address register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5DAR" description="HPDMA channel 5 destination address register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5LLR" description="HPDMA channel 5 linked-list address register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6LBAR" description="HPDMA channel 6 linked-list base address register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6CIDCFGR" description="HPDMA channel 6 CID register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6SEMCR" description="HPDMA channel 6 semaphore control register" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6FCR" description="HPDMA channel 6 flag clear register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6SR" description="HPDMA channel 6 status register" start="+0x360" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C6CR" description="HPDMA channel 6 control register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6TR1" description="HPDMA channel 6 transfer register 1" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6TR2" description="HPDMA channel 6 transfer register 2" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6BR1" description="HPDMA channel 6 block register 1" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6SAR" description="HPDMA channel 6 source address register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6DAR" description="HPDMA channel 6 destination address register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6LLR" description="HPDMA channel 6 linked-list address register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7LBAR" description="HPDMA channel 7 linked-list base address register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7CIDCFGR" description="HPDMA channel 7 CID register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7SEMCR" description="HPDMA channel 7 semaphore control register" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7FCR" description="HPDMA channel 7 flag clear register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7SR" description="HPDMA channel 7 status register" start="+0x3E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C7CR" description="HPDMA channel 7 control register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7TR1" description="HPDMA channel 7 transfer register 1" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7TR2" description="HPDMA channel 7 transfer register 2" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7BR1" description="HPDMA channel 7 block register 1" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7SAR" description="HPDMA channel 7 source address register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7DAR" description="HPDMA channel 7 destination address register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7LLR" description="HPDMA channel 7 linked-list address register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8LBAR" description="HPDMA channel 8 linked-list base address register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8CIDCFGR" description="HPDMA channel 8 CID register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8SEMCR" description="HPDMA channel 8 semaphore control register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8FCR" description="HPDMA channel 8 flag clear register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8SR" description="HPDMA channel 8 status register" start="+0x460" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C8CR" description="HPDMA channel 8 control register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8TR1" description="HPDMA channel 8 transfer register 1" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8TR2" description="HPDMA channel 8 transfer register 2" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8BR1" description="HPDMA channel 8 block register 1" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8SAR" description="HPDMA channel 8 source address register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8DAR" description="HPDMA channel 8 destination address register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8LLR" description="HPDMA channel 8 linked-list address register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9LBAR" description="HPDMA channel 9 linked-list base address register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9CIDCFGR" description="HPDMA channel 9 CID register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9SEMCR" description="HPDMA channel 9 semaphore control register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9FCR" description="HPDMA channel 9 flag clear register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9SR" description="HPDMA channel 9 status register" start="+0x4E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C9CR" description="HPDMA channel 9 control register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9TR1" description="HPDMA channel 9 transfer register 1" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9TR2" description="HPDMA channel 9 transfer register 2" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9BR1" description="HPDMA channel 9 block register 1" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9SAR" description="HPDMA channel 9 source address register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9DAR" description="HPDMA channel 9 destination address register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9LLR" description="HPDMA channel 9 linked-list address register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10LBAR" description="HPDMA channel 10 linked-list base address register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10CIDCFGR" description="HPDMA channel 10 CID register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10SEMCR" description="HPDMA channel 10 semaphore control register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10FCR" description="HPDMA channel 10 flag clear register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10SR" description="HPDMA channel 10 status register" start="+0x560" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C10CR" description="HPDMA channel 10 control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10TR1" description="HPDMA channel 10 transfer register 1" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10TR2" description="HPDMA channel 10 transfer register 2" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10BR1" description="HPDMA channel 10 block register 1" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10SAR" description="HPDMA channel 10 source address register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10DAR" description="HPDMA channel 10 destination address register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10LLR" description="HPDMA channel 10 linked-list address register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11LBAR" description="HPDMA channel 11 linked-list base address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11CIDCFGR" description="HPDMA channel 11 CID register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11SEMCR" description="HPDMA channel 11 semaphore control register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11FCR" description="HPDMA channel 11 flag clear register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11SR" description="HPDMA channel 11 status register" start="+0x5E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C11CR" description="HPDMA channel 11 control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11TR1" description="HPDMA channel 11 transfer register 1" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11TR2" description="HPDMA channel 11 transfer register 2" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11BR1" description="HPDMA channel 11 block register 1" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11SAR" description="HPDMA channel 11 source address register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11DAR" description="HPDMA channel 11 destination address register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11LLR" description="HPDMA channel 11 linked-list address register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12LBAR" description="HPDMA channel 12 linked-list base address register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12CIDCFGR" description="HPDMA channel 12 CID register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SEMCR" description="HPDMA channel 12 semaphore control register" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12FCR" description="HPDMA channel 12 flag clear register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SR" description="HPDMA channel 12 status register" start="+0x660" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C12CR" description="HPDMA channel 12 control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12TR1" description="HPDMA channel 12 transfer register 1" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12TR2" description="HPDMA channel 12 transfer register 2" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12BR1" description="HPDMA channel 12 alternate block register 1" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SAR" description="HPDMA channel 12 source address register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12DAR" description="HPDMA channel 12 destination address register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12TR3" description="HPDMA channel 12 transfer register 3" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12BR2" description="HPDMA channel 12 block register 2" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12LLR" description="HPDMA channel 12 alternate linked-list address register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13LBAR" description="HPDMA channel 13 linked-list base address register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13CIDCFGR" description="HPDMA channel 13 CID register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SEMCR" description="HPDMA channel 13 semaphore control register" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13FCR" description="HPDMA channel 13 flag clear register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SR" description="HPDMA channel 13 status register" start="+0x6E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C13CR" description="HPDMA channel 13 control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13TR1" description="HPDMA channel 13 transfer register 1" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13TR2" description="HPDMA channel 13 transfer register 2" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13BR1" description="HPDMA channel 13 alternate block register 1" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SAR" description="HPDMA channel 13 source address register" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13DAR" description="HPDMA channel 13 destination address register" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13TR3" description="HPDMA channel 13 transfer register 3" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13BR2" description="HPDMA channel 13 block register 2" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13LLR" description="HPDMA channel 13 alternate linked-list address register" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14LBAR" description="HPDMA channel 14 linked-list base address register" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14CIDCFGR" description="HPDMA channel 14 CID register" start="+0x754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SEMCR" description="HPDMA channel 14 semaphore control register" start="+0x758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14FCR" description="HPDMA channel 14 flag clear register" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SR" description="HPDMA channel 14 status register" start="+0x760" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C14CR" description="HPDMA channel 14 control register" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14TR1" description="HPDMA channel 14 transfer register 1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14TR2" description="HPDMA channel 14 transfer register 2" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14BR1" description="HPDMA channel 14 alternate block register 1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SAR" description="HPDMA channel 14 source address register" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14DAR" description="HPDMA channel 14 destination address register" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14TR3" description="HPDMA channel 14 transfer register 3" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14BR2" description="HPDMA channel 14 block register 2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14LLR" description="HPDMA channel 14 alternate linked-list address register" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15LBAR" description="HPDMA channel 15 linked-list base address register" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15CIDCFGR" description="HPDMA channel 15 CID register" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SEMCR" description="HPDMA channel 15 semaphore control register" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15FCR" description="HPDMA channel 15 flag clear register" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SR" description="HPDMA channel 15 status register" start="+0x7E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C15CR" description="HPDMA channel 15 control register" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15TR1" description="HPDMA channel 15 transfer register 1" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15TR2" description="HPDMA channel 15 transfer register 2" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15BR1" description="HPDMA channel 15 alternate block register 1" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SAR" description="HPDMA channel 15 source address register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15DAR" description="HPDMA channel 15 destination address register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15TR3" description="HPDMA channel 15 transfer register 3" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15BR2" description="HPDMA channel 15 block register 2" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15LLR" description="HPDMA channel 15 alternate linked-list address register" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HPDMA_S" description="High-performance direct memory access controller" start="0x58020000">
+    <Register name="HPDMA_SECCFGR" description="HPDMA secure configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="secure state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="secure state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="secure state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="secure state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="secure state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="secure state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="secure state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="secure state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="secure state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="secure state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="secure state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="secure state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="secure state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="secure state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="secure state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="secure state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="non-secure" start="0x0" />
+        <Enum name="B_0x1" description="secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_PRIVCFGR" description="HPDMA privileged configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged state of channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged state of channel x" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged state of channel x" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged state of channel x" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged state of channel x" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged state of channel x" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged state of channel x" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged state of channel x" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged state of channel x" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged state of channel x" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged state of channel x" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged state of channel x" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged state of channel x" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged state of channel x" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged state of channel x" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged state of channel x" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="unprivileged" start="0x0" />
+        <Enum name="B_0x1" description="privileged" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_RCFGLOCKR" description="HPDMA configuration lock register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK0" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK1" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK2" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK3" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK4" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK5" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK6" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK7" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK8" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK9" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK10" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK11" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK12" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK13" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK14" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+      <BitField name="LOCK15" description="lock the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx, and HPDMA_CxCIDCFGR until a global HPDMA reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="secure privilege and CID configuration of the channel x is writable." start="0x0" />
+        <Enum name="B_0x1" description="secure privilege and CID configuration of the channel x is not writable." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_MISR" description="HPDMA non-secure masked interrupt status register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_SMISR" description="HPDMA secure masked interrupt status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIS0" description="masked interrupt status of the secure channel x" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS1" description="masked interrupt status of the secure channel x" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS2" description="masked interrupt status of the secure channel x" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS3" description="masked interrupt status of the secure channel x" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS4" description="masked interrupt status of the secure channel x" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS5" description="masked interrupt status of the secure channel x" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS6" description="masked interrupt status of the secure channel x" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS7" description="masked interrupt status of the secure channel x" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS8" description="masked interrupt status of the secure channel x" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS9" description="masked interrupt status of the secure channel x" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS10" description="masked interrupt status of the secure channel x" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS11" description="masked interrupt status of the secure channel x" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS12" description="masked interrupt status of the secure channel x" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS13" description="masked interrupt status of the secure channel x" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS14" description="masked interrupt status of the secure channel x" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+      <BitField name="MIS15" description="masked interrupt status of the secure channel x" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no interrupt occurred on the secure channel x" start="0x0" />
+        <Enum name="B_0x1" description="an interrupt occurred on the secure channel x" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0LBAR" description="HPDMA channel 0 linked-list base address register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0CIDCFGR" description="HPDMA channel 0 CID register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0SEMCR" description="HPDMA channel 0 semaphore control register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0FCR" description="HPDMA channel 0 flag clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0SR" description="HPDMA channel 0 status register" start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C0CR" description="HPDMA channel 0 control register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0TR1" description="HPDMA channel 0 transfer register 1" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0TR2" description="HPDMA channel 0 transfer register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C0BR1" description="HPDMA channel 0 block register 1" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0SAR" description="HPDMA channel 0 source address register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0DAR" description="HPDMA channel 0 destination address register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C0LLR" description="HPDMA channel 0 linked-list address register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1LBAR" description="HPDMA channel 1 linked-list base address register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1CIDCFGR" description="HPDMA channel 1 CID register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1SEMCR" description="HPDMA channel 1 semaphore control register" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1FCR" description="HPDMA channel 1 flag clear register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1SR" description="HPDMA channel 1 status register" start="+0xE0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C1CR" description="HPDMA channel 1 control register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1TR1" description="HPDMA channel 1 transfer register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1TR2" description="HPDMA channel 1 transfer register 2" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C1BR1" description="HPDMA channel 1 block register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1SAR" description="HPDMA channel 1 source address register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1DAR" description="HPDMA channel 1 destination address register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C1LLR" description="HPDMA channel 1 linked-list address register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2LBAR" description="HPDMA channel 2 linked-list base address register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2CIDCFGR" description="HPDMA channel 2 CID register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2SEMCR" description="HPDMA channel 2 semaphore control register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2FCR" description="HPDMA channel 2 flag clear register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2SR" description="HPDMA channel 2 status register" start="+0x160" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C2CR" description="HPDMA channel 2 control register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2TR1" description="HPDMA channel 2 transfer register 1" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2TR2" description="HPDMA channel 2 transfer register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C2BR1" description="HPDMA channel 2 block register 1" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2SAR" description="HPDMA channel 2 source address register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2DAR" description="HPDMA channel 2 destination address register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C2LLR" description="HPDMA channel 2 linked-list address register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3LBAR" description="HPDMA channel 3 linked-list base address register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3CIDCFGR" description="HPDMA channel 3 CID register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3SEMCR" description="HPDMA channel 3 semaphore control register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3FCR" description="HPDMA channel 3 flag clear register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3SR" description="HPDMA channel 3 status register" start="+0x1E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C3CR" description="HPDMA channel 3 control register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3TR1" description="HPDMA channel 3 transfer register 1" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3TR2" description="HPDMA channel 3 transfer register 2" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C3BR1" description="HPDMA channel 3 block register 1" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3SAR" description="HPDMA channel 3 source address register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3DAR" description="HPDMA channel 3 destination address register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C3LLR" description="HPDMA channel 3 linked-list address register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4LBAR" description="HPDMA channel 4 linked-list base address register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4CIDCFGR" description="HPDMA channel 4 CID register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4SEMCR" description="HPDMA channel 4 semaphore control register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4FCR" description="HPDMA channel 4 flag clear register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4SR" description="HPDMA channel 4 status register" start="+0x260" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C4CR" description="HPDMA channel 4 control register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4TR1" description="HPDMA channel 4 transfer register 1" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4TR2" description="HPDMA channel 4 transfer register 2" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C4BR1" description="HPDMA channel 4 block register 1" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4SAR" description="HPDMA channel 4 source address register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4DAR" description="HPDMA channel 4 destination address register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C4LLR" description="HPDMA channel 4 linked-list address register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5LBAR" description="HPDMA channel 5 linked-list base address register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5CIDCFGR" description="HPDMA channel 5 CID register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5SEMCR" description="HPDMA channel 5 semaphore control register" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5FCR" description="HPDMA channel 5 flag clear register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5SR" description="HPDMA channel 5 status register" start="+0x2E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C5CR" description="HPDMA channel 5 control register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5TR1" description="HPDMA channel 5 transfer register 1" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5TR2" description="HPDMA channel 5 transfer register 2" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C5BR1" description="HPDMA channel 5 block register 1" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5SAR" description="HPDMA channel 5 source address register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5DAR" description="HPDMA channel 5 destination address register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C5LLR" description="HPDMA channel 5 linked-list address register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6LBAR" description="HPDMA channel 6 linked-list base address register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6CIDCFGR" description="HPDMA channel 6 CID register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6SEMCR" description="HPDMA channel 6 semaphore control register" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6FCR" description="HPDMA channel 6 flag clear register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6SR" description="HPDMA channel 6 status register" start="+0x360" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C6CR" description="HPDMA channel 6 control register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6TR1" description="HPDMA channel 6 transfer register 1" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6TR2" description="HPDMA channel 6 transfer register 2" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C6BR1" description="HPDMA channel 6 block register 1" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6SAR" description="HPDMA channel 6 source address register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6DAR" description="HPDMA channel 6 destination address register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C6LLR" description="HPDMA channel 6 linked-list address register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7LBAR" description="HPDMA channel 7 linked-list base address register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7CIDCFGR" description="HPDMA channel 7 CID register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7SEMCR" description="HPDMA channel 7 semaphore control register" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7FCR" description="HPDMA channel 7 flag clear register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7SR" description="HPDMA channel 7 status register" start="+0x3E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C7CR" description="HPDMA channel 7 control register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7TR1" description="HPDMA channel 7 transfer register 1" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7TR2" description="HPDMA channel 7 transfer register 2" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C7BR1" description="HPDMA channel 7 block register 1" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7SAR" description="HPDMA channel 7 source address register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7DAR" description="HPDMA channel 7 destination address register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C7LLR" description="HPDMA channel 7 linked-list address register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8LBAR" description="HPDMA channel 8 linked-list base address register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8CIDCFGR" description="HPDMA channel 8 CID register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8SEMCR" description="HPDMA channel 8 semaphore control register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8FCR" description="HPDMA channel 8 flag clear register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8SR" description="HPDMA channel 8 status register" start="+0x460" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C8CR" description="HPDMA channel 8 control register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8TR1" description="HPDMA channel 8 transfer register 1" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8TR2" description="HPDMA channel 8 transfer register 2" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C8BR1" description="HPDMA channel 8 block register 1" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8SAR" description="HPDMA channel 8 source address register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8DAR" description="HPDMA channel 8 destination address register" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C8LLR" description="HPDMA channel 8 linked-list address register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9LBAR" description="HPDMA channel 9 linked-list base address register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9CIDCFGR" description="HPDMA channel 9 CID register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9SEMCR" description="HPDMA channel 9 semaphore control register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9FCR" description="HPDMA channel 9 flag clear register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9SR" description="HPDMA channel 9 status register" start="+0x4E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C9CR" description="HPDMA channel 9 control register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9TR1" description="HPDMA channel 9 transfer register 1" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9TR2" description="HPDMA channel 9 transfer register 2" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C9BR1" description="HPDMA channel 9 block register 1" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9SAR" description="HPDMA channel 9 source address register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9DAR" description="HPDMA channel 9 destination address register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C9LLR" description="HPDMA channel 9 linked-list address register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10LBAR" description="HPDMA channel 10 linked-list base address register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10CIDCFGR" description="HPDMA channel 10 CID register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10SEMCR" description="HPDMA channel 10 semaphore control register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10FCR" description="HPDMA channel 10 flag clear register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10SR" description="HPDMA channel 10 status register" start="+0x560" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C10CR" description="HPDMA channel 10 control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10TR1" description="HPDMA channel 10 transfer register 1" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10TR2" description="HPDMA channel 10 transfer register 2" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C10BR1" description="HPDMA channel 10 block register 1" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10SAR" description="HPDMA channel 10 source address register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10DAR" description="HPDMA channel 10 destination address register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C10LLR" description="HPDMA channel 10 linked-list address register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11LBAR" description="HPDMA channel 11 linked-list base address register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11CIDCFGR" description="HPDMA channel 11 CID register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11SEMCR" description="HPDMA channel 11 semaphore control register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11FCR" description="HPDMA channel 11 flag clear register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11SR" description="HPDMA channel 11 status register" start="+0x5E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C11CR" description="HPDMA channel 11 control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11TR1" description="HPDMA channel 11 transfer register 1" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11TR2" description="HPDMA channel 11 transfer register 2" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C11BR1" description="HPDMA channel 11 block register 1" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11SAR" description="HPDMA channel 11 source address register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11DAR" description="HPDMA channel 11 destination address register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C11LLR" description="HPDMA channel 11 linked-list address register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12LBAR" description="HPDMA channel 12 linked-list base address register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12CIDCFGR" description="HPDMA channel 12 CID register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SEMCR" description="HPDMA channel 12 semaphore control register" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12FCR" description="HPDMA channel 12 flag clear register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SR" description="HPDMA channel 12 status register" start="+0x660" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C12CR" description="HPDMA channel 12 control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12TR1" description="HPDMA channel 12 transfer register 1" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12TR2" description="HPDMA channel 12 transfer register 2" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12BR1" description="HPDMA channel 12 alternate block register 1" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C12SAR" description="HPDMA channel 12 source address register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12DAR" description="HPDMA channel 12 destination address register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12TR3" description="HPDMA channel 12 transfer register 3" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12BR2" description="HPDMA channel 12 block register 2" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C12LLR" description="HPDMA channel 12 alternate linked-list address register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13LBAR" description="HPDMA channel 13 linked-list base address register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13CIDCFGR" description="HPDMA channel 13 CID register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SEMCR" description="HPDMA channel 13 semaphore control register" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13FCR" description="HPDMA channel 13 flag clear register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SR" description="HPDMA channel 13 status register" start="+0x6E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C13CR" description="HPDMA channel 13 control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13TR1" description="HPDMA channel 13 transfer register 1" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13TR2" description="HPDMA channel 13 transfer register 2" start="+0x714" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13BR1" description="HPDMA channel 13 alternate block register 1" start="+0x718" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C13SAR" description="HPDMA channel 13 source address register" start="+0x71C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13DAR" description="HPDMA channel 13 destination address register" start="+0x720" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13TR3" description="HPDMA channel 13 transfer register 3" start="+0x724" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13BR2" description="HPDMA channel 13 block register 2" start="+0x728" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C13LLR" description="HPDMA channel 13 alternate linked-list address register" start="+0x74C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14LBAR" description="HPDMA channel 14 linked-list base address register" start="+0x750" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14CIDCFGR" description="HPDMA channel 14 CID register" start="+0x754" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SEMCR" description="HPDMA channel 14 semaphore control register" start="+0x758" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14FCR" description="HPDMA channel 14 flag clear register" start="+0x75C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SR" description="HPDMA channel 14 status register" start="+0x760" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C14CR" description="HPDMA channel 14 control register" start="+0x764" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14TR1" description="HPDMA channel 14 transfer register 1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14TR2" description="HPDMA channel 14 transfer register 2" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14BR1" description="HPDMA channel 14 alternate block register 1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C14SAR" description="HPDMA channel 14 source address register" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14DAR" description="HPDMA channel 14 destination address register" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14TR3" description="HPDMA channel 14 transfer register 3" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14BR2" description="HPDMA channel 14 block register 2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C14LLR" description="HPDMA channel 14 alternate linked-list address register" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15LBAR" description="HPDMA channel 15 linked-list base address register" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBA" description="linked-list base address of HPDMA channel x" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15CIDCFGR" description="HPDMA channel 15 CID register" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEN" description="CID filtering enable of the channel x" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID filtering disabled for when accessing a channel x register/field" start="0x0" />
+        <Enum name="B_0x1" description="CID filtering enabled for when accessing a channel x register/field" start="0x1" />
+      </BitField>
+      <BitField name="SEM_EN" description="semaphore mode enable (for the CID allocation policy to the channel x)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0]." start="0x0" />
+        <Enum name="B_0x1" description="semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX." start="0x1" />
+      </BitField>
+      <BitField name="SCID" description="allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 allocated to the channel x" start="0x0" />
+        <Enum name="B_0x1" description="CID1 allocated to the channel x" start="0x1" />
+        <Enum name="B_0x2" description="CID2 allocated to the channel x" start="0x2" />
+        <Enum name="B_0x3" description="CID3 allocated to the channel x" start="0x3" />
+        <Enum name="B_0x4" description="CID4 allocated to the channel x" start="0x4" />
+        <Enum name="B_0x5" description="CID5 allocated to the channel x" start="0x5" />
+        <Enum name="B_0x6" description="CID6 allocated to the channel x" start="0x6" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID0" description="white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID0 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID0 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID1" description="white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID1 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID1 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID2" description="white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID2 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID2 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID3" description="white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID3 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID3 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID4" description="white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID4 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID4 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID5" description="white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID5 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID5 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_WLIST_CID6" description="white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CID6 black-listed in the semaphore-based CID allocation pool" start="0x0" />
+        <Enum name="B_0x1" description="CID6 white-listed in the semaphore-based CID allocation pool" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SEMCR" description="HPDMA channel 15 semaphore control register" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEM_MUTEX" description="mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0_WRITE" description="release the control of the channel x (in semaphore mode) to any white-listed CID" start="0x0" />
+        <Enum name="B_0x1_WRITE" description="take the control of the channel x (in semaphore mode), from one of the white-listed CID pool" start="0x1" />
+      </BitField>
+      <BitField name="SEM_CCID" description="current CID allocated to the channel x (in semaphore mode)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="CID0 is the last white-listed CID that took the control of the channel x." start="0x0" />
+        <Enum name="B_0x1" description="CID1 is the last white-listed CID that took the control of the channel x." start="0x1" />
+        <Enum name="B_0x2" description="CID2 is the last white-listed CID that took the control of the channel x." start="0x2" />
+        <Enum name="B_0x3" description="CID3 is the last white-listed CID that took the control of the channel x." start="0x3" />
+        <Enum name="B_0x4" description="CID4 is the last white-listed CID that took the control of the channel x." start="0x4" />
+        <Enum name="B_0x5" description="CID5 is the last white-listed CID that took the control of the channel x." start="0x5" />
+        <Enum name="B_0x6" description="CID6 is the last white-listed CID that took the control of the channel x." start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15FCR" description="HPDMA channel 15 flag clear register" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCF" description="transfer complete flag clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TCF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding HTF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding DTEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding ULEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag clear" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding USEF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag clear" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding SUSPF flag cleared" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag clear" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="corresponding TOF flag cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SR" description="HPDMA channel 15 status register" start="+0x7E0" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="IDLEF" description="idle flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="channel not in idle state" start="0x0" />
+        <Enum name="B_0x1" description="channel in idle state" start="0x1" />
+      </BitField>
+      <BitField name="TCF" description="transfer complete flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer complete event" start="0x0" />
+        <Enum name="B_0x1" description="a transfer complete event occurred" start="0x1" />
+      </BitField>
+      <BitField name="HTF" description="half transfer flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no half transfer event" start="0x0" />
+        <Enum name="B_0x1" description="an half transfer event occurred" start="0x1" />
+      </BitField>
+      <BitField name="DTEF" description="data transfer error flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no data transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred on a data transfer" start="0x1" />
+      </BitField>
+      <BitField name="ULEF" description="update link transfer error flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no update link transfer error event" start="0x0" />
+        <Enum name="B_0x1" description="a master bus error event occurred while updating a linked-list register from memory" start="0x1" />
+      </BitField>
+      <BitField name="USEF" description="user setting error flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no user setting error event" start="0x0" />
+        <Enum name="B_0x1" description="a user setting error event occurred" start="0x1" />
+      </BitField>
+      <BitField name="SUSPF" description="completed suspension flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no completed suspension event" start="0x0" />
+        <Enum name="B_0x1" description="a completed suspension event occurred" start="0x1" />
+      </BitField>
+      <BitField name="TOF" description="trigger overrun flag" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no trigger overrun event" start="0x0" />
+        <Enum name="B_0x1" description="a trigger overrun event occurred" start="0x1" />
+      </BitField>
+      <BitField name="FIFOL" description="monitored FIFO level" start="16" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="HPDMA_C15CR" description="HPDMA channel 15 control register" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: ignored, read: channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="write: enable channel, read: channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="reset" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no channel reset" start="0x0" />
+        <Enum name="B_0x1" description="channel reset" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspend" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="write: resume channel, read: channel not suspended" start="0x0" />
+        <Enum name="B_0x1" description="write: suspend channel, read: channel suspended." start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="transfer complete interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HTIE" description="half transfer complete interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTEIE" description="data transfer error interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ULEIE" description="update link transfer error interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="USEIE" description="user setting error interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SUSPIE" description="completed suspension interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="trigger overrun interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSM" description="Link step mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="channel executed for the full linked-list and completed at the end of the last LLI (HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0 if present." start="0x0" />
+        <Enum name="B_0x1" description="channel executed once for the current LLI" start="0x1" />
+      </BitField>
+      <BitField name="LAP" description="linked-list allocated port" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="PRIO" description="priority level of the channel x HPDMA transfer versus others" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="low priority, low weight" start="0x0" />
+        <Enum name="B_0x1" description="low priority, mid weight" start="0x1" />
+        <Enum name="B_0x2" description="low priority, high weight" start="0x2" />
+        <Enum name="B_0x3" description="high priority" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15TR1" description="HPDMA channel 15 transfer register 1" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDW_LOG2" description="binary logarithm of the source data width of a burst in bytes" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If SAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="SINC" description="source incrementing burst" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="SBL_1" description="source burst length minus 1, between 0 and 63" start="4" size="6" access="Read/Write" />
+      <BitField name="PAM" description="padding/alignment mode" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0_PAM_1" description="source data is transferred as right aligned, padded with 0s up to the destination data width" start="0x0" />
+        <Enum name="B_0x1_PAM_1" description="source data is transferred as right aligned, sign extended up to the destination data width" start="0x1" />
+        <Enum name="B_0x2_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x2" />
+        <Enum name="B_0x3_PAM_1" description="successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer" start="0x3" />
+      </BitField>
+      <BitField name="SBX" description="source byte exchange within the unaligned half-word of each source word " start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within the unaligned half-word of each source word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive bytes within the unaligned half-word of each source word are exchanged." start="0x1" />
+      </BitField>
+      <BitField name="SAP" description="source allocated port" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="SSEC" description="security attribute of the HPDMA transfer from the source" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+      <BitField name="DDW_LOG2" description="binary logarithm of the destination data width of a burst, in bytes" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="byte" start="0x0" />
+        <Enum name="B_0x1" description="half-word (2 bytes)" start="0x1" />
+        <Enum name="B_0x2" description="word (4 bytes)" start="0x2" />
+        <Enum name="B_0x3" description="If DAP = 0 (AXI), double-word (8 bytes)" start="0x3" />
+      </BitField>
+      <BitField name="DINC" description="destination incrementing burst" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="fixed burst" start="0x0" />
+        <Enum name="B_0x1" description="contiguously incremented burst" start="0x1" />
+      </BitField>
+      <BitField name="DBL_1" description="destination burst length minus 1, between 0 and 63" start="20" size="6" access="Read/Write" />
+      <BitField name="DBX" description="destination byte exchange" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no byte-based exchange within half-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) bytes are exchanged in each destination half-word." start="0x1" />
+      </BitField>
+      <BitField name="DHX" description="destination half-word exchange" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no half-word-based exchanged within word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) half-words are exchanged in each destination word." start="0x1" />
+      </BitField>
+      <BitField name="DWX" description="destination word exchange" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no word-based exchanged within double-word" start="0x0" />
+        <Enum name="B_0x1" description="the two consecutive (post PAM) words are exchanged in each destination double-word." start="0x1" />
+      </BitField>
+      <BitField name="DAP" description="destination allocated port" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="port 0 (AXI) allocated" start="0x0" />
+        <Enum name="B_0x1" description="port 1 (AHB) allocated" start="0x1" />
+      </BitField>
+      <BitField name="DSEC" description="security attribute of the HPDMA transfer to the destination" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA transfer non-secure" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA transfer secure" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15TR2" description="HPDMA channel 15 transfer register 2" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REQSEL" description="hardware request selection" start="0" size="8" access="Read/Write" />
+      <BitField name="SWREQ" description="software request" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no software request. The selected hardware request REQSEL[7:0] is taken into account." start="0x0" />
+        <Enum name="B_0x1" description="software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored." start="0x1" />
+      </BitField>
+      <BitField name="DREQ" description="destination hardware request" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port)" start="0x0" />
+        <Enum name="B_0x1" description="selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port)" start="0x1" />
+      </BitField>
+      <BitField name="BREQ" description="Block hardware request" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4)." start="0x1" />
+      </BitField>
+      <BitField name="PFREQ" description="Hardware request in peripheral flow control mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion." start="0x0" />
+        <Enum name="B_0x1" description="the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details)." start="0x1" />
+      </BitField>
+      <BitField name="TRIGM" description="trigger mode" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0)." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the" start="0x1" />
+        <Enum name="B_0x2" description="at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned." start="0x2" />
+        <Enum name="B_0x3" description="at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger." start="0x3" />
+      </BitField>
+      <BitField name="TRIGSEL" description="trigger event input selection" start="16" size="7" access="Read/Write" />
+      <BitField name="TRIGPOL" description="trigger event polarity" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no trigger (masked trigger event)" start="0x0" />
+        <Enum name="B_0x1" description="trigger on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="trigger on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="same as 00" start="0x3" />
+      </BitField>
+      <BitField name="TCEM" description="transfer complete event mode" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block." start="0x0" />
+        <Enum name="B_0x1" description="channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block." start="0x1" />
+        <Enum name="B_0x2" description="at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer." start="0x2" />
+        <Enum name="B_0x3" description="at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15BR1" description="HPDMA channel 15 alternate block register 1" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data bytes to transfer from the source" start="0" size="16" access="Read/Write" />
+      <BitField name="BRC" description="Block repeat counter" start="16" size="11" access="Read/Write" />
+      <BitField name="SDEC" description="source address decrement" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="DDEC" description="destination address decrement" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+      <BitField name="BRSDEC" description="Block repeat source address decrement" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by adding the programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current source address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value (current source address)" start="0x1" />
+      </BitField>
+      <BitField name="BRDDEC" description="Block repeat destination address decrement" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by adding the programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current destination address)" start="0x0" />
+        <Enum name="B_0x1" description="at the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value (current destination address)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="HPDMA_C15SAR" description="HPDMA channel 15 source address register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA" description="source address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15DAR" description="HPDMA channel 15 destination address register" start="+0x820" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="destination address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15TR3" description="HPDMA channel 15 transfer register 3" start="+0x824" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAO" description="source address offset increment" start="0" size="13" access="Read/Write" />
+      <BitField name="DAO" description="destination address offset increment" start="16" size="13" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15BR2" description="HPDMA channel 15 block register 2" start="+0x828" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRSAO" description="Block repeated source address offset" start="0" size="16" access="Read/Write" />
+      <BitField name="BRDAO" description="Block repeated destination address offset" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="HPDMA_C15LLR" description="HPDMA channel 15 alternate linked-list address register" start="+0x84C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LA" description="pointer (16-bit low-significant address) to the next linked-list data structure" start="2" size="14" access="Read/Write" />
+      <BitField name="ULL" description="Update HPDMA_CxLLR register from memory" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxLLR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxLLR update" start="0x1" />
+      </BitField>
+      <BitField name="UB2" description="Update HPDMA_CxBR2 from memory" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT3" description="Update HPDMA_CxTR3 from memory" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR3 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR3 update" start="0x1" />
+      </BitField>
+      <BitField name="UDA" description="Update HPDMA_CxDAR register from memory" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxDAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxDAR update" start="0x1" />
+      </BitField>
+      <BitField name="USA" description="update HPDMA_CxSAR from memory" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxSAR update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxSAR update" start="0x1" />
+      </BitField>
+      <BitField name="UB1" description="Update HPDMA_CxBR1 from memory" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxBR1 update" start="0x1" />
+      </BitField>
+      <BitField name="UT2" description="Update HPDMA_CxTR2 from memory" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR2 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR2 update" start="0x1" />
+      </BitField>
+      <BitField name="UT1" description="Update HPDMA_CxTR1 from memory" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no HPDMA_CxTR1 update" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA_CxTR1 update" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IAC" description="Illegal access controller" start="0x44025000">
+    <Register name="IAC_IER0" description="IAC interrupt enable register 0" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE0" description="illegal access interrupt enable for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 0 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 0 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE1" description="illegal access interrupt enable for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 1 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 1 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE2" description="illegal access interrupt enable for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 2 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 2 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE3" description="illegal access interrupt enable for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 3 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 3 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE4" description="illegal access interrupt enable for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 4 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 4 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE5" description="illegal access interrupt enable for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 5 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 5 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE6" description="illegal access interrupt enable for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 6 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 6 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE7" description="illegal access interrupt enable for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 7 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 7 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE8" description="illegal access interrupt enable for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 8 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 8 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE9" description="illegal access interrupt enable for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 9 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 9 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE10" description="illegal access interrupt enable for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 10 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 10 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE11" description="illegal access interrupt enable for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 11 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 11 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE12" description="illegal access interrupt enable for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 12 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 12 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE13" description="illegal access interrupt enable for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 13 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 13 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE14" description="illegal access interrupt enable for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 14 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 14 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE15" description="illegal access interrupt enable for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 15 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 15 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE16" description="illegal access interrupt enable for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 16 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 16 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE17" description="illegal access interrupt enable for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 17 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 17 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE18" description="illegal access interrupt enable for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 18 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 18 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE19" description="illegal access interrupt enable for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 19 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 19 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE20" description="illegal access interrupt enable for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 20 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 20 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE21" description="illegal access interrupt enable for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 21 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 21 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE22" description="illegal access interrupt enable for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 22 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 22 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE23" description="illegal access interrupt enable for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 23 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 23 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE24" description="illegal access interrupt enable for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 24 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 24 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE25" description="illegal access interrupt enable for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 25 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 25 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE26" description="illegal access interrupt enable for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 26 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 26 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE27" description="illegal access interrupt enable for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 27 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 27 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE28" description="illegal access interrupt enable for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 28 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 28 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE29" description="illegal access interrupt enable for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 29 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 29 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE30" description="illegal access interrupt enable for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 30 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 30 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE31" description="illegal access interrupt enable for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 31 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 31 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER1" description="IAC interrupt enable register 1" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE32" description="illegal access interrupt enable for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 32 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 32 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE33" description="illegal access interrupt enable for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 33 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 33 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE34" description="illegal access interrupt enable for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 34 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 34 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE35" description="illegal access interrupt enable for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 35 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 35 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE36" description="illegal access interrupt enable for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 36 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 36 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE37" description="illegal access interrupt enable for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 37 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 37 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE38" description="illegal access interrupt enable for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 38 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 38 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE39" description="illegal access interrupt enable for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 39 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 39 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE40" description="illegal access interrupt enable for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 40 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 40 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE41" description="illegal access interrupt enable for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 41 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 41 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE42" description="illegal access interrupt enable for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 42 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 42 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE43" description="illegal access interrupt enable for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 43 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 43 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE44" description="illegal access interrupt enable for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 44 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 44 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE45" description="illegal access interrupt enable for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 45 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 45 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE46" description="illegal access interrupt enable for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 46 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 46 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE47" description="illegal access interrupt enable for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 47 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 47 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE48" description="illegal access interrupt enable for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 48 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 48 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE49" description="illegal access interrupt enable for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 49 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 49 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE50" description="illegal access interrupt enable for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 50 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 50 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE51" description="illegal access interrupt enable for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 51 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 51 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE52" description="illegal access interrupt enable for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 52 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 52 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE53" description="illegal access interrupt enable for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 53 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 53 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE54" description="illegal access interrupt enable for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 54 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 54 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE55" description="illegal access interrupt enable for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 55 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 55 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE56" description="illegal access interrupt enable for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 56 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 56 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE57" description="illegal access interrupt enable for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 57 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 57 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE58" description="illegal access interrupt enable for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 58 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 58 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE59" description="illegal access interrupt enable for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 59 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 59 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE60" description="illegal access interrupt enable for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 60 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 60 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE61" description="illegal access interrupt enable for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 61 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 61 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE62" description="illegal access interrupt enable for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 62 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 62 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE63" description="illegal access interrupt enable for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 63 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 63 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER2" description="IAC interrupt enable register 2" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE64" description="illegal access interrupt enable for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 64 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 64 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE65" description="illegal access interrupt enable for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 65 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 65 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE66" description="illegal access interrupt enable for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 66 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 66 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE67" description="illegal access interrupt enable for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 67 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 67 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE68" description="illegal access interrupt enable for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 68 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 68 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE69" description="illegal access interrupt enable for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 69 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 69 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE70" description="illegal access interrupt enable for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 70 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 70 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE71" description="illegal access interrupt enable for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 71 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 71 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE72" description="illegal access interrupt enable for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 72 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 72 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE73" description="illegal access interrupt enable for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 73 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 73 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE74" description="illegal access interrupt enable for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 74 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 74 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE75" description="illegal access interrupt enable for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 75 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 75 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE76" description="illegal access interrupt enable for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 76 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 76 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE77" description="illegal access interrupt enable for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 77 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 77 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE78" description="illegal access interrupt enable for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 78 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 78 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE79" description="illegal access interrupt enable for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 79 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 79 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE80" description="illegal access interrupt enable for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 80 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 80 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE81" description="illegal access interrupt enable for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 81 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 81 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE82" description="illegal access interrupt enable for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 82 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 82 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE83" description="illegal access interrupt enable for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 83 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 83 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE84" description="illegal access interrupt enable for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 84 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 84 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE85" description="illegal access interrupt enable for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 85 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 85 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE86" description="illegal access interrupt enable for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 86 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 86 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE87" description="illegal access interrupt enable for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 87 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 87 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE88" description="illegal access interrupt enable for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 88 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 88 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE89" description="illegal access interrupt enable for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 89 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 89 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE90" description="illegal access interrupt enable for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 90 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 90 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE91" description="illegal access interrupt enable for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 91 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 91 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE92" description="illegal access interrupt enable for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 92 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 92 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE93" description="illegal access interrupt enable for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 93 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 93 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE94" description="illegal access interrupt enable for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 94 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 94 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE95" description="illegal access interrupt enable for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 95 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 95 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER3" description="IAC interrupt enable register 3" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE96" description="illegal access interrupt enable for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 96 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 96 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE97" description="illegal access interrupt enable for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 97 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 97 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE98" description="illegal access interrupt enable for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 98 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 98 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE99" description="illegal access interrupt enable for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 99 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 99 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE100" description="illegal access interrupt enable for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 100 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 100 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE101" description="illegal access interrupt enable for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 101 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 101 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE102" description="illegal access interrupt enable for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 102 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 102 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE103" description="illegal access interrupt enable for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 103 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 103 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE104" description="illegal access interrupt enable for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 104 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 104 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE105" description="illegal access interrupt enable for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 105 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 105 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE106" description="illegal access interrupt enable for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 106 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 106 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE107" description="illegal access interrupt enable for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 107 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 107 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE108" description="illegal access interrupt enable for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 108 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 108 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE109" description="illegal access interrupt enable for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 109 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 109 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE110" description="illegal access interrupt enable for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 110 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 110 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE111" description="illegal access interrupt enable for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 111 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 111 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE112" description="illegal access interrupt enable for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 112 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 112 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE113" description="illegal access interrupt enable for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 113 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 113 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE114" description="illegal access interrupt enable for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 114 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 114 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE115" description="illegal access interrupt enable for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 115 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 115 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE116" description="illegal access interrupt enable for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 116 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 116 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE117" description="illegal access interrupt enable for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 117 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 117 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE118" description="illegal access interrupt enable for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 118 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 118 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE119" description="illegal access interrupt enable for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 119 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 119 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE120" description="illegal access interrupt enable for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 120 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 120 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE121" description="illegal access interrupt enable for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 121 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 121 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE122" description="illegal access interrupt enable for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 122 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 122 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE123" description="illegal access interrupt enable for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 123 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 123 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE124" description="illegal access interrupt enable for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 124 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 124 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE125" description="illegal access interrupt enable for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 125 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 125 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE126" description="illegal access interrupt enable for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 126 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 126 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE127" description="illegal access interrupt enable for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 127 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 127 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER4" description="IAC interrupt enable register 4" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE128" description="illegal access interrupt enable for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 128 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 128 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE129" description="illegal access interrupt enable for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 129 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 129 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE130" description="illegal access interrupt enable for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 130 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 130 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE131" description="illegal access interrupt enable for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 131 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 131 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE132" description="illegal access interrupt enable for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 132 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 132 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE133" description="illegal access interrupt enable for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 133 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 133 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE134" description="illegal access interrupt enable for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 134 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 134 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE135" description="illegal access interrupt enable for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 135 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 135 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE136" description="illegal access interrupt enable for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 136 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 136 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE137" description="illegal access interrupt enable for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 137 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 137 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE138" description="illegal access interrupt enable for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 138 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 138 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE139" description="illegal access interrupt enable for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 139 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 139 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE140" description="illegal access interrupt enable for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 140 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 140 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE141" description="illegal access interrupt enable for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 141 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 141 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE142" description="illegal access interrupt enable for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 142 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 142 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE143" description="illegal access interrupt enable for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 143 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 143 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE144" description="illegal access interrupt enable for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 144 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 144 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE145" description="illegal access interrupt enable for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 145 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 145 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE146" description="illegal access interrupt enable for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 146 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 146 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE147" description="illegal access interrupt enable for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 147 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 147 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE148" description="illegal access interrupt enable for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 148 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 148 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE149" description="illegal access interrupt enable for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 149 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 149 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE150" description="illegal access interrupt enable for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 150 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 150 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE151" description="illegal access interrupt enable for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 151 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 151 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE152" description="illegal access interrupt enable for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 152 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 152 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE153" description="illegal access interrupt enable for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 153 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 153 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE154" description="illegal access interrupt enable for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 154 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 154 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE155" description="illegal access interrupt enable for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 155 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 155 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE156" description="illegal access interrupt enable for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 156 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 156 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE157" description="illegal access interrupt enable for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 157 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 157 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE158" description="illegal access interrupt enable for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 158 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 158 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE159" description="illegal access interrupt enable for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 159 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 159 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER5" description="IAC interrupt enable register 5" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE160" description="illegal access interrupt enable for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 160 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 160 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE161" description="illegal access interrupt enable for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 161 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 161 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE162" description="illegal access interrupt enable for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 162 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 162 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE163" description="illegal access interrupt enable for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 163 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 163 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE164" description="illegal access interrupt enable for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 164 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 164 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE165" description="illegal access interrupt enable for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 165 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 165 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE166" description="illegal access interrupt enable for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 166 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 166 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE167" description="illegal access interrupt enable for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 167 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 167 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE168" description="illegal access interrupt enable for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 168 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 168 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE169" description="illegal access interrupt enable for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 169 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 169 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE170" description="illegal access interrupt enable for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 170 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 170 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE171" description="illegal access interrupt enable for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 171 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 171 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE172" description="illegal access interrupt enable for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 172 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 172 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE173" description="illegal access interrupt enable for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 173 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 173 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE174" description="illegal access interrupt enable for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 174 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 174 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE175" description="illegal access interrupt enable for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 175 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 175 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE176" description="illegal access interrupt enable for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 176 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 176 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE177" description="illegal access interrupt enable for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 177 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 177 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE178" description="illegal access interrupt enable for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 178 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 178 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE179" description="illegal access interrupt enable for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 179 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 179 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE180" description="illegal access interrupt enable for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 180 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 180 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE181" description="illegal access interrupt enable for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 181 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 181 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE182" description="illegal access interrupt enable for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 182 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 182 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE183" description="illegal access interrupt enable for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 183 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 183 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE184" description="illegal access interrupt enable for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 184 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 184 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE185" description="illegal access interrupt enable for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 185 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 185 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE186" description="illegal access interrupt enable for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 186 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 186 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE187" description="illegal access interrupt enable for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 187 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 187 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE188" description="illegal access interrupt enable for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 188 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 188 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE189" description="illegal access interrupt enable for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 189 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 189 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE190" description="illegal access interrupt enable for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 190 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 190 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE191" description="illegal access interrupt enable for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 191 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 191 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR0" description="IAC interrupt status register 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF0" description="illegal access interrupt enable for peripheral 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 0 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 0 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF1" description="illegal access interrupt enable for peripheral 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 1 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 1 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF2" description="illegal access interrupt enable for peripheral 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 2 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 2 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF3" description="illegal access interrupt enable for peripheral 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 3 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 3 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF4" description="illegal access interrupt enable for peripheral 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 4 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 4 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF5" description="illegal access interrupt enable for peripheral 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 5 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 5 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF6" description="illegal access interrupt enable for peripheral 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 6 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 6 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF7" description="illegal access interrupt enable for peripheral 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 7 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 7 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF8" description="illegal access interrupt enable for peripheral 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 8 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 8 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF9" description="illegal access interrupt enable for peripheral 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 9 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 9 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF10" description="illegal access interrupt enable for peripheral 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 10 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 10 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF11" description="illegal access interrupt enable for peripheral 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 11 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 11 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF12" description="illegal access interrupt enable for peripheral 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 12 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 12 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF13" description="illegal access interrupt enable for peripheral 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 13 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 13 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF14" description="illegal access interrupt enable for peripheral 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 14 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 14 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF15" description="illegal access interrupt enable for peripheral 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 15 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 15 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF16" description="illegal access interrupt enable for peripheral 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 16 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 16 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF17" description="illegal access interrupt enable for peripheral 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 17 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 17 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF18" description="illegal access interrupt enable for peripheral 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 18 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 18 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF19" description="illegal access interrupt enable for peripheral 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 19 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 19 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF20" description="illegal access interrupt enable for peripheral 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 20 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 20 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF21" description="illegal access interrupt enable for peripheral 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 21 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 21 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF22" description="illegal access interrupt enable for peripheral 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 22 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 22 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF23" description="illegal access interrupt enable for peripheral 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 23 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 23 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF24" description="illegal access interrupt enable for peripheral 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 24 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 24 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF25" description="illegal access interrupt enable for peripheral 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 25 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 25 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF26" description="illegal access interrupt enable for peripheral 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 26 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 26 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF27" description="illegal access interrupt enable for peripheral 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 27 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 27 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF28" description="illegal access interrupt enable for peripheral 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 28 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 28 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF29" description="illegal access interrupt enable for peripheral 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 29 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 29 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF30" description="illegal access interrupt enable for peripheral 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 30 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 30 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF31" description="illegal access interrupt enable for peripheral 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 31 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 31 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR1" description="IAC interrupt status register 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF32" description="illegal access interrupt enable for peripheral 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 32 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 32 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF33" description="illegal access interrupt enable for peripheral 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 33 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 33 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF34" description="illegal access interrupt enable for peripheral 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 34 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 34 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF35" description="illegal access interrupt enable for peripheral 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 35 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 35 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF36" description="illegal access interrupt enable for peripheral 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 36 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 36 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF37" description="illegal access interrupt enable for peripheral 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 37 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 37 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF38" description="illegal access interrupt enable for peripheral 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 38 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 38 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF39" description="illegal access interrupt enable for peripheral 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 39 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 39 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF40" description="illegal access interrupt enable for peripheral 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 40 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 40 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF41" description="illegal access interrupt enable for peripheral 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 41 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 41 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF42" description="illegal access interrupt enable for peripheral 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 42 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 42 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF43" description="illegal access interrupt enable for peripheral 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 43 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 43 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF44" description="illegal access interrupt enable for peripheral 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 44 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 44 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF45" description="illegal access interrupt enable for peripheral 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 45 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 45 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF46" description="illegal access interrupt enable for peripheral 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 46 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 46 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF47" description="illegal access interrupt enable for peripheral 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 47 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 47 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF48" description="illegal access interrupt enable for peripheral 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 48 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 48 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF49" description="illegal access interrupt enable for peripheral 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 49 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 49 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF50" description="illegal access interrupt enable for peripheral 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 50 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 50 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF51" description="illegal access interrupt enable for peripheral 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 51 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 51 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF52" description="illegal access interrupt enable for peripheral 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 52 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 52 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF53" description="illegal access interrupt enable for peripheral 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 53 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 53 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF54" description="illegal access interrupt enable for peripheral 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 54 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 54 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF55" description="illegal access interrupt enable for peripheral 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 55 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 55 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF56" description="illegal access interrupt enable for peripheral 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 56 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 56 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF57" description="illegal access interrupt enable for peripheral 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 57 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 57 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF58" description="illegal access interrupt enable for peripheral 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 58 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 58 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF59" description="illegal access interrupt enable for peripheral 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 59 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 59 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF60" description="illegal access interrupt enable for peripheral 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 60 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 60 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF61" description="illegal access interrupt enable for peripheral 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 61 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 61 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF62" description="illegal access interrupt enable for peripheral 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 62 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 62 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF63" description="illegal access interrupt enable for peripheral 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 63 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 63 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR2" description="IAC interrupt status register 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF64" description="illegal access interrupt enable for peripheral 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 64 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 64 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF65" description="illegal access interrupt enable for peripheral 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 65 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 65 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF66" description="illegal access interrupt enable for peripheral 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 66 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 66 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF67" description="illegal access interrupt enable for peripheral 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 67 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 67 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF68" description="illegal access interrupt enable for peripheral 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 68 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 68 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF69" description="illegal access interrupt enable for peripheral 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 69 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 69 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF70" description="illegal access interrupt enable for peripheral 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 70 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 70 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF71" description="illegal access interrupt enable for peripheral 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 71 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 71 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF72" description="illegal access interrupt enable for peripheral 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 72 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 72 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF73" description="illegal access interrupt enable for peripheral 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 73 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 73 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF74" description="illegal access interrupt enable for peripheral 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 74 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 74 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF75" description="illegal access interrupt enable for peripheral 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 75 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 75 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF76" description="illegal access interrupt enable for peripheral 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 76 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 76 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF77" description="illegal access interrupt enable for peripheral 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 77 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 77 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF78" description="illegal access interrupt enable for peripheral 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 78 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 78 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF79" description="illegal access interrupt enable for peripheral 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 79 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 79 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF80" description="illegal access interrupt enable for peripheral 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 80 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 80 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF81" description="illegal access interrupt enable for peripheral 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 81 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 81 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF82" description="illegal access interrupt enable for peripheral 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 82 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 82 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF83" description="illegal access interrupt enable for peripheral 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 83 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 83 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF84" description="illegal access interrupt enable for peripheral 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 84 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 84 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF85" description="illegal access interrupt enable for peripheral 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 85 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 85 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF86" description="illegal access interrupt enable for peripheral 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 86 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 86 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF87" description="illegal access interrupt enable for peripheral 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 87 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 87 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF88" description="illegal access interrupt enable for peripheral 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 88 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 88 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF89" description="illegal access interrupt enable for peripheral 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 89 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 89 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF90" description="illegal access interrupt enable for peripheral 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 90 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 90 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF91" description="illegal access interrupt enable for peripheral 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 91 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 91 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF92" description="illegal access interrupt enable for peripheral 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 92 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 92 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF93" description="illegal access interrupt enable for peripheral 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 93 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 93 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF94" description="illegal access interrupt enable for peripheral 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 94 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 94 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF95" description="illegal access interrupt enable for peripheral 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 95 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 95 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR3" description="IAC interrupt status register 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF96" description="illegal access interrupt enable for peripheral 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 96 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 96 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF97" description="illegal access interrupt enable for peripheral 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 97 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 97 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF98" description="illegal access interrupt enable for peripheral 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 98 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 98 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF99" description="illegal access interrupt enable for peripheral 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 99 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 99 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF100" description="illegal access interrupt enable for peripheral 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 100 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 100 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF101" description="illegal access interrupt enable for peripheral 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 101 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 101 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF102" description="illegal access interrupt enable for peripheral 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 102 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 102 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF103" description="illegal access interrupt enable for peripheral 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 103 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 103 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF104" description="illegal access interrupt enable for peripheral 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 104 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 104 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF105" description="illegal access interrupt enable for peripheral 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 105 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 105 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF106" description="illegal access interrupt enable for peripheral 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 106 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 106 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF107" description="illegal access interrupt enable for peripheral 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 107 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 107 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF108" description="illegal access interrupt enable for peripheral 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 108 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 108 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF109" description="illegal access interrupt enable for peripheral 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 109 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 109 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF110" description="illegal access interrupt enable for peripheral 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 110 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 110 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF111" description="illegal access interrupt enable for peripheral 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 111 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 111 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF112" description="illegal access interrupt enable for peripheral 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 112 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 112 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF113" description="illegal access interrupt enable for peripheral 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 113 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 113 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF114" description="illegal access interrupt enable for peripheral 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 114 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 114 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF115" description="illegal access interrupt enable for peripheral 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 115 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 115 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF116" description="illegal access interrupt enable for peripheral 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 116 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 116 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF117" description="illegal access interrupt enable for peripheral 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 117 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 117 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF118" description="illegal access interrupt enable for peripheral 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 118 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 118 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF119" description="illegal access interrupt enable for peripheral 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 119 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 119 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF120" description="illegal access interrupt enable for peripheral 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 120 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 120 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF121" description="illegal access interrupt enable for peripheral 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 121 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 121 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF122" description="illegal access interrupt enable for peripheral 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 122 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 122 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF123" description="illegal access interrupt enable for peripheral 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 123 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 123 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF124" description="illegal access interrupt enable for peripheral 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 124 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 124 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF125" description="illegal access interrupt enable for peripheral 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 125 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 125 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF126" description="illegal access interrupt enable for peripheral 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 126 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 126 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF127" description="illegal access interrupt enable for peripheral 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 127 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 127 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR4" description="IAC interrupt status register 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF128" description="illegal access interrupt enable for peripheral 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 128 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 128 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF129" description="illegal access interrupt enable for peripheral 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 129 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 129 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF130" description="illegal access interrupt enable for peripheral 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 130 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 130 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF131" description="illegal access interrupt enable for peripheral 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 131 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 131 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF132" description="illegal access interrupt enable for peripheral 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 132 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 132 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF133" description="illegal access interrupt enable for peripheral 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 133 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 133 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF134" description="illegal access interrupt enable for peripheral 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 134 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 134 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF135" description="illegal access interrupt enable for peripheral 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 135 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 135 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF136" description="illegal access interrupt enable for peripheral 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 136 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 136 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF137" description="illegal access interrupt enable for peripheral 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 137 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 137 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF138" description="illegal access interrupt enable for peripheral 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 138 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 138 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF139" description="illegal access interrupt enable for peripheral 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 139 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 139 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF140" description="illegal access interrupt enable for peripheral 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 140 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 140 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF141" description="illegal access interrupt enable for peripheral 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 141 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 141 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF142" description="illegal access interrupt enable for peripheral 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 142 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 142 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF143" description="illegal access interrupt enable for peripheral 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 143 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 143 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF144" description="illegal access interrupt enable for peripheral 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 144 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 144 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF145" description="illegal access interrupt enable for peripheral 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 145 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 145 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF146" description="illegal access interrupt enable for peripheral 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 146 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 146 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF147" description="illegal access interrupt enable for peripheral 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 147 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 147 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF148" description="illegal access interrupt enable for peripheral 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 148 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 148 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF149" description="illegal access interrupt enable for peripheral 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 149 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 149 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF150" description="illegal access interrupt enable for peripheral 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 150 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 150 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF151" description="illegal access interrupt enable for peripheral 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 151 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 151 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF152" description="illegal access interrupt enable for peripheral 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 152 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 152 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF153" description="illegal access interrupt enable for peripheral 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 153 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 153 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF154" description="illegal access interrupt enable for peripheral 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 154 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 154 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF155" description="illegal access interrupt enable for peripheral 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 155 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 155 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF156" description="illegal access interrupt enable for peripheral 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 156 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 156 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF157" description="illegal access interrupt enable for peripheral 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 157 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 157 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF158" description="illegal access interrupt enable for peripheral 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 158 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 158 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF159" description="illegal access interrupt enable for peripheral 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 159 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 159 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR5" description="IAC interrupt status register 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF160" description="illegal access interrupt enable for peripheral 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 160 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 160 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF161" description="illegal access interrupt enable for peripheral 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 161 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 161 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF162" description="illegal access interrupt enable for peripheral 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 162 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 162 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF163" description="illegal access interrupt enable for peripheral 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 163 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 163 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF164" description="illegal access interrupt enable for peripheral 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 164 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 164 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF165" description="illegal access interrupt enable for peripheral 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 165 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 165 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF166" description="illegal access interrupt enable for peripheral 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 166 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 166 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF167" description="illegal access interrupt enable for peripheral 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 167 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 167 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF168" description="illegal access interrupt enable for peripheral 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 168 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 168 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF169" description="illegal access interrupt enable for peripheral 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 169 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 169 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF170" description="illegal access interrupt enable for peripheral 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 170 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 170 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF171" description="illegal access interrupt enable for peripheral 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 171 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 171 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF172" description="illegal access interrupt enable for peripheral 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 172 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 172 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF173" description="illegal access interrupt enable for peripheral 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 173 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 173 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF174" description="illegal access interrupt enable for peripheral 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 174 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 174 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF175" description="illegal access interrupt enable for peripheral 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 175 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 175 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF176" description="illegal access interrupt enable for peripheral 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 176 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 176 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF177" description="illegal access interrupt enable for peripheral 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 177 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 177 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF178" description="illegal access interrupt enable for peripheral 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 178 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 178 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF179" description="illegal access interrupt enable for peripheral 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 179 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 179 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF180" description="illegal access interrupt enable for peripheral 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 180 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 180 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF181" description="illegal access interrupt enable for peripheral 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 181 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 181 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF182" description="illegal access interrupt enable for peripheral 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 182 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 182 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF183" description="illegal access interrupt enable for peripheral 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 183 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 183 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF184" description="illegal access interrupt enable for peripheral 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 184 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 184 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF185" description="illegal access interrupt enable for peripheral 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 185 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 185 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF186" description="illegal access interrupt enable for peripheral 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 186 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 186 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF187" description="illegal access interrupt enable for peripheral 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 187 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 187 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF188" description="illegal access interrupt enable for peripheral 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 188 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 188 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF189" description="illegal access interrupt enable for peripheral 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 189 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 189 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF190" description="illegal access interrupt enable for peripheral 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 190 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 190 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF191" description="illegal access interrupt enable for peripheral 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 191 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 191 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR0" description="IAC interrupt clear register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF0" description="illegal access flag clear for peripheral 0" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 0 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 0 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF1" description="illegal access flag clear for peripheral 1" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 1 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 1 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF2" description="illegal access flag clear for peripheral 2" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 2 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 2 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF3" description="illegal access flag clear for peripheral 3" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 3 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 3 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF4" description="illegal access flag clear for peripheral 4" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 4 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 4 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF5" description="illegal access flag clear for peripheral 5" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 5 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 5 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF6" description="illegal access flag clear for peripheral 6" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 6 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 6 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF7" description="illegal access flag clear for peripheral 7" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 7 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 7 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF8" description="illegal access flag clear for peripheral 8" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 8 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 8 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF9" description="illegal access flag clear for peripheral 9" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 9 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 9 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF10" description="illegal access flag clear for peripheral 10" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 10 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 10 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF11" description="illegal access flag clear for peripheral 11" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 11 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 11 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF12" description="illegal access flag clear for peripheral 12" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 12 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 12 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF13" description="illegal access flag clear for peripheral 13" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 13 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 13 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF14" description="illegal access flag clear for peripheral 14" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 14 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 14 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF15" description="illegal access flag clear for peripheral 15" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 15 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 15 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF16" description="illegal access flag clear for peripheral 16" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 16 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 16 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF17" description="illegal access flag clear for peripheral 17" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 17 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 17 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF18" description="illegal access flag clear for peripheral 18" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 18 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 18 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF19" description="illegal access flag clear for peripheral 19" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 19 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 19 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF20" description="illegal access flag clear for peripheral 20" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 20 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 20 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF21" description="illegal access flag clear for peripheral 21" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 21 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 21 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF22" description="illegal access flag clear for peripheral 22" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 22 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 22 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF23" description="illegal access flag clear for peripheral 23" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 23 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 23 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF24" description="illegal access flag clear for peripheral 24" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 24 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 24 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF25" description="illegal access flag clear for peripheral 25" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 25 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 25 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF26" description="illegal access flag clear for peripheral 26" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 26 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 26 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF27" description="illegal access flag clear for peripheral 27" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 27 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 27 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF28" description="illegal access flag clear for peripheral 28" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 28 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 28 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF29" description="illegal access flag clear for peripheral 29" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 29 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 29 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF30" description="illegal access flag clear for peripheral 30" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 30 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 30 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF31" description="illegal access flag clear for peripheral 31" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 31 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 31 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR1" description="IAC interrupt clear register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF32" description="illegal access flag clear for peripheral 32" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 32 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 32 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF33" description="illegal access flag clear for peripheral 33" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 33 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 33 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF34" description="illegal access flag clear for peripheral 34" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 34 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 34 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF35" description="illegal access flag clear for peripheral 35" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 35 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 35 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF36" description="illegal access flag clear for peripheral 36" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 36 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 36 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF37" description="illegal access flag clear for peripheral 37" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 37 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 37 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF38" description="illegal access flag clear for peripheral 38" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 38 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 38 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF39" description="illegal access flag clear for peripheral 39" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 39 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 39 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF40" description="illegal access flag clear for peripheral 40" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 40 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 40 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF41" description="illegal access flag clear for peripheral 41" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 41 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 41 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF42" description="illegal access flag clear for peripheral 42" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 42 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 42 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF43" description="illegal access flag clear for peripheral 43" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 43 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 43 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF44" description="illegal access flag clear for peripheral 44" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 44 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 44 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF45" description="illegal access flag clear for peripheral 45" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 45 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 45 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF46" description="illegal access flag clear for peripheral 46" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 46 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 46 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF47" description="illegal access flag clear for peripheral 47" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 47 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 47 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF48" description="illegal access flag clear for peripheral 48" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 48 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 48 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF49" description="illegal access flag clear for peripheral 49" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 49 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 49 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF50" description="illegal access flag clear for peripheral 50" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 50 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 50 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF51" description="illegal access flag clear for peripheral 51" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 51 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 51 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF52" description="illegal access flag clear for peripheral 52" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 52 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 52 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF53" description="illegal access flag clear for peripheral 53" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 53 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 53 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF54" description="illegal access flag clear for peripheral 54" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 54 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 54 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF55" description="illegal access flag clear for peripheral 55" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 55 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 55 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF56" description="illegal access flag clear for peripheral 56" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 56 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 56 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF57" description="illegal access flag clear for peripheral 57" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 57 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 57 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF58" description="illegal access flag clear for peripheral 58" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 58 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 58 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF59" description="illegal access flag clear for peripheral 59" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 59 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 59 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF60" description="illegal access flag clear for peripheral 60" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 60 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 60 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF61" description="illegal access flag clear for peripheral 61" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 61 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 61 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF62" description="illegal access flag clear for peripheral 62" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 62 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 62 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF63" description="illegal access flag clear for peripheral 63" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 63 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 63 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR2" description="IAC interrupt clear register 2" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF64" description="illegal access flag clear for peripheral 64" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 64 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 64 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF65" description="illegal access flag clear for peripheral 65" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 65 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 65 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF66" description="illegal access flag clear for peripheral 66" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 66 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 66 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF67" description="illegal access flag clear for peripheral 67" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 67 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 67 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF68" description="illegal access flag clear for peripheral 68" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 68 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 68 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF69" description="illegal access flag clear for peripheral 69" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 69 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 69 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF70" description="illegal access flag clear for peripheral 70" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 70 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 70 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF71" description="illegal access flag clear for peripheral 71" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 71 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 71 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF72" description="illegal access flag clear for peripheral 72" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 72 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 72 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF73" description="illegal access flag clear for peripheral 73" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 73 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 73 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF74" description="illegal access flag clear for peripheral 74" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 74 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 74 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF75" description="illegal access flag clear for peripheral 75" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 75 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 75 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF76" description="illegal access flag clear for peripheral 76" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 76 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 76 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF77" description="illegal access flag clear for peripheral 77" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 77 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 77 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF78" description="illegal access flag clear for peripheral 78" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 78 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 78 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF79" description="illegal access flag clear for peripheral 79" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 79 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 79 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF80" description="illegal access flag clear for peripheral 80" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 80 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 80 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF81" description="illegal access flag clear for peripheral 81" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 81 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 81 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF82" description="illegal access flag clear for peripheral 82" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 82 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 82 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF83" description="illegal access flag clear for peripheral 83" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 83 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 83 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF84" description="illegal access flag clear for peripheral 84" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 84 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 84 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF85" description="illegal access flag clear for peripheral 85" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 85 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 85 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF86" description="illegal access flag clear for peripheral 86" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 86 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 86 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF87" description="illegal access flag clear for peripheral 87" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 87 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 87 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF88" description="illegal access flag clear for peripheral 88" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 88 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 88 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF89" description="illegal access flag clear for peripheral 89" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 89 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 89 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF90" description="illegal access flag clear for peripheral 90" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 90 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 90 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF91" description="illegal access flag clear for peripheral 91" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 91 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 91 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF92" description="illegal access flag clear for peripheral 92" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 92 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 92 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF93" description="illegal access flag clear for peripheral 93" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 93 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 93 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF94" description="illegal access flag clear for peripheral 94" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 94 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 94 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF95" description="illegal access flag clear for peripheral 95" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 95 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 95 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR3" description="IAC interrupt clear register 3" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF96" description="illegal access flag clear for peripheral 96" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 96 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 96 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF97" description="illegal access flag clear for peripheral 97" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 97 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 97 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF98" description="illegal access flag clear for peripheral 98" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 98 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 98 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF99" description="illegal access flag clear for peripheral 99" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 99 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 99 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF100" description="illegal access flag clear for peripheral 100" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 100 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 100 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF101" description="illegal access flag clear for peripheral 101" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 101 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 101 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF102" description="illegal access flag clear for peripheral 102" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 102 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 102 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF103" description="illegal access flag clear for peripheral 103" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 103 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 103 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF104" description="illegal access flag clear for peripheral 104" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 104 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 104 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF105" description="illegal access flag clear for peripheral 105" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 105 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 105 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF106" description="illegal access flag clear for peripheral 106" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 106 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 106 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF107" description="illegal access flag clear for peripheral 107" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 107 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 107 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF108" description="illegal access flag clear for peripheral 108" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 108 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 108 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF109" description="illegal access flag clear for peripheral 109" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 109 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 109 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF110" description="illegal access flag clear for peripheral 110" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 110 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 110 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF111" description="illegal access flag clear for peripheral 111" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 111 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 111 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF112" description="illegal access flag clear for peripheral 112" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 112 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 112 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF113" description="illegal access flag clear for peripheral 113" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 113 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 113 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF114" description="illegal access flag clear for peripheral 114" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 114 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 114 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF115" description="illegal access flag clear for peripheral 115" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 115 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 115 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF116" description="illegal access flag clear for peripheral 116" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 116 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 116 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF117" description="illegal access flag clear for peripheral 117" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 117 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 117 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF118" description="illegal access flag clear for peripheral 118" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 118 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 118 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF119" description="illegal access flag clear for peripheral 119" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 119 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 119 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF120" description="illegal access flag clear for peripheral 120" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 120 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 120 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF121" description="illegal access flag clear for peripheral 121" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 121 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 121 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF122" description="illegal access flag clear for peripheral 122" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 122 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 122 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF123" description="illegal access flag clear for peripheral 123" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 123 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 123 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF124" description="illegal access flag clear for peripheral 124" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 124 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 124 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF125" description="illegal access flag clear for peripheral 125" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 125 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 125 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF126" description="illegal access flag clear for peripheral 126" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 126 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 126 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF127" description="illegal access flag clear for peripheral 127" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 127 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 127 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR4" description="IAC interrupt clear register 4" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF128" description="illegal access flag clear for peripheral 128" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 128 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 128 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF129" description="illegal access flag clear for peripheral 129" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 129 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 129 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF130" description="illegal access flag clear for peripheral 130" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 130 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 130 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF131" description="illegal access flag clear for peripheral 131" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 131 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 131 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF132" description="illegal access flag clear for peripheral 132" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 132 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 132 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF133" description="illegal access flag clear for peripheral 133" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 133 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 133 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF134" description="illegal access flag clear for peripheral 134" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 134 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 134 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF135" description="illegal access flag clear for peripheral 135" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 135 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 135 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF136" description="illegal access flag clear for peripheral 136" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 136 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 136 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF137" description="illegal access flag clear for peripheral 137" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 137 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 137 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF138" description="illegal access flag clear for peripheral 138" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 138 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 138 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF139" description="illegal access flag clear for peripheral 139" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 139 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 139 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF140" description="illegal access flag clear for peripheral 140" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 140 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 140 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF141" description="illegal access flag clear for peripheral 141" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 141 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 141 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF142" description="illegal access flag clear for peripheral 142" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 142 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 142 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF143" description="illegal access flag clear for peripheral 143" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 143 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 143 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF144" description="illegal access flag clear for peripheral 144" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 144 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 144 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF145" description="illegal access flag clear for peripheral 145" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 145 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 145 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF146" description="illegal access flag clear for peripheral 146" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 146 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 146 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF147" description="illegal access flag clear for peripheral 147" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 147 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 147 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF148" description="illegal access flag clear for peripheral 148" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 148 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 148 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF149" description="illegal access flag clear for peripheral 149" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 149 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 149 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF150" description="illegal access flag clear for peripheral 150" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 150 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 150 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF151" description="illegal access flag clear for peripheral 151" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 151 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 151 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF152" description="illegal access flag clear for peripheral 152" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 152 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 152 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF153" description="illegal access flag clear for peripheral 153" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 153 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 153 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF154" description="illegal access flag clear for peripheral 154" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 154 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 154 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF155" description="illegal access flag clear for peripheral 155" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 155 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 155 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF156" description="illegal access flag clear for peripheral 156" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 156 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 156 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF157" description="illegal access flag clear for peripheral 157" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 157 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 157 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF158" description="illegal access flag clear for peripheral 158" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 158 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 158 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF159" description="illegal access flag clear for peripheral 159" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 159 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 159 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR5" description="IAC interrupt clear register 5" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF160" description="illegal access flag clear for peripheral 160" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 160 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 160 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF161" description="illegal access flag clear for peripheral 161" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 161 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 161 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF162" description="illegal access flag clear for peripheral 162" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 162 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 162 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF163" description="illegal access flag clear for peripheral 163" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 163 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 163 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF164" description="illegal access flag clear for peripheral 164" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 164 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 164 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF165" description="illegal access flag clear for peripheral 165" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 165 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 165 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF166" description="illegal access flag clear for peripheral 166" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 166 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 166 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF167" description="illegal access flag clear for peripheral 167" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 167 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 167 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF168" description="illegal access flag clear for peripheral 168" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 168 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 168 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF169" description="illegal access flag clear for peripheral 169" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 169 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 169 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF170" description="illegal access flag clear for peripheral 170" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 170 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 170 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF171" description="illegal access flag clear for peripheral 171" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 171 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 171 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF172" description="illegal access flag clear for peripheral 172" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 172 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 172 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF173" description="illegal access flag clear for peripheral 173" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 173 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 173 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF174" description="illegal access flag clear for peripheral 174" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 174 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 174 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF175" description="illegal access flag clear for peripheral 175" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 175 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 175 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF176" description="illegal access flag clear for peripheral 176" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 176 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 176 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF177" description="illegal access flag clear for peripheral 177" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 177 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 177 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF178" description="illegal access flag clear for peripheral 178" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 178 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 178 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF179" description="illegal access flag clear for peripheral 179" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 179 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 179 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF180" description="illegal access flag clear for peripheral 180" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 180 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 180 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF181" description="illegal access flag clear for peripheral 181" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 181 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 181 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF182" description="illegal access flag clear for peripheral 182" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 182 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 182 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF183" description="illegal access flag clear for peripheral 183" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 183 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 183 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF184" description="illegal access flag clear for peripheral 184" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 184 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 184 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF185" description="illegal access flag clear for peripheral 185" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 185 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 185 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF186" description="illegal access flag clear for peripheral 186" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 186 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 186 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF187" description="illegal access flag clear for peripheral 187" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 187 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 187 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF188" description="illegal access flag clear for peripheral 188" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 188 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 188 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF189" description="illegal access flag clear for peripheral 189" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 189 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 189 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF190" description="illegal access flag clear for peripheral 190" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 190 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 190 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF191" description="illegal access flag clear for peripheral 191" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 191 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 191 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR0" description="IAC ILAC input status register 0" start="+0x36C" size="4" reset_value="0xFFFFFF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN0" description="illegal access input 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 0 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 0 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN1" description="illegal access input 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 1 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 1 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN2" description="illegal access input 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 2 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 2 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN3" description="illegal access input 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 3 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 3 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN4" description="illegal access input 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 4 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 4 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN5" description="illegal access input 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 5 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 5 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN6" description="illegal access input 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 6 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 6 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN7" description="illegal access input 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 7 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 7 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN8" description="illegal access input 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 8 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 8 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN9" description="illegal access input 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 9 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 9 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN10" description="illegal access input 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 10 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 10 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN11" description="illegal access input 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 11 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 11 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN12" description="illegal access input 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 12 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 12 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN13" description="illegal access input 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 13 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 13 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN14" description="illegal access input 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 14 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 14 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN15" description="illegal access input 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 15 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 15 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN16" description="illegal access input 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 16 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 16 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN17" description="illegal access input 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 17 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 17 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN18" description="illegal access input 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 18 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 18 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN19" description="illegal access input 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 19 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 19 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN20" description="illegal access input 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 20 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 20 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN21" description="illegal access input 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 21 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 21 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN22" description="illegal access input 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 22 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 22 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN23" description="illegal access input 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 23 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 23 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN24" description="illegal access input 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 24 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 24 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN25" description="illegal access input 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 25 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 25 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN26" description="illegal access input 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 26 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 26 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN27" description="illegal access input 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 27 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 27 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN28" description="illegal access input 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 28 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 28 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN29" description="illegal access input 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 29 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 29 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN30" description="illegal access input 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 30 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 30 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN31" description="illegal access input 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 31 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 31 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR1" description="IAC ILAC input status register 1" start="+0x370" size="4" reset_value="0x77FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN32" description="illegal access input 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 32 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 32 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN33" description="illegal access input 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 33 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 33 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN34" description="illegal access input 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 34 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 34 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN35" description="illegal access input 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 35 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 35 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN36" description="illegal access input 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 36 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 36 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN37" description="illegal access input 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 37 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 37 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN38" description="illegal access input 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 38 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 38 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN39" description="illegal access input 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 39 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 39 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN40" description="illegal access input 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 40 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 40 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN41" description="illegal access input 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 41 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 41 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN42" description="illegal access input 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 42 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 42 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN43" description="illegal access input 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 43 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 43 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN44" description="illegal access input 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 44 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 44 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN45" description="illegal access input 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 45 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 45 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN46" description="illegal access input 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 46 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 46 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN47" description="illegal access input 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 47 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 47 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN48" description="illegal access input 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 48 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 48 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN49" description="illegal access input 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 49 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 49 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN50" description="illegal access input 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 50 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 50 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN51" description="illegal access input 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 51 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 51 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN52" description="illegal access input 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 52 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 52 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN53" description="illegal access input 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 53 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 53 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN54" description="illegal access input 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 54 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 54 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN55" description="illegal access input 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 55 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 55 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN56" description="illegal access input 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 56 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 56 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN57" description="illegal access input 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 57 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 57 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN58" description="illegal access input 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 58 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 58 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN59" description="illegal access input 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 59 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 59 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN60" description="illegal access input 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 60 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 60 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN61" description="illegal access input 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 61 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 61 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN62" description="illegal access input 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 62 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 62 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN63" description="illegal access input 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 63 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 63 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR2" description="IAC ILAC input status register 2" start="+0x374" size="4" reset_value="0x77DFF03B" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN64" description="illegal access input 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 64 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 64 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN65" description="illegal access input 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 65 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 65 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN66" description="illegal access input 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 66 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 66 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN67" description="illegal access input 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 67 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 67 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN68" description="illegal access input 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 68 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 68 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN69" description="illegal access input 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 69 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 69 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN70" description="illegal access input 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 70 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 70 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN71" description="illegal access input 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 71 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 71 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN72" description="illegal access input 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 72 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 72 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN73" description="illegal access input 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 73 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 73 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN74" description="illegal access input 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 74 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 74 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN75" description="illegal access input 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 75 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 75 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN76" description="illegal access input 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 76 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 76 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN77" description="illegal access input 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 77 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 77 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN78" description="illegal access input 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 78 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 78 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN79" description="illegal access input 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 79 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 79 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN80" description="illegal access input 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 80 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 80 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN81" description="illegal access input 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 81 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 81 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN82" description="illegal access input 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 82 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 82 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN83" description="illegal access input 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 83 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 83 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN84" description="illegal access input 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 84 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 84 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN85" description="illegal access input 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 85 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 85 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN86" description="illegal access input 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 86 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 86 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN87" description="illegal access input 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 87 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 87 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN88" description="illegal access input 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 88 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 88 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN89" description="illegal access input 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 89 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 89 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN90" description="illegal access input 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 90 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 90 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN91" description="illegal access input 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 91 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 91 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN92" description="illegal access input 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 92 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 92 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN93" description="illegal access input 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 93 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 93 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN94" description="illegal access input 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 94 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 94 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN95" description="illegal access input 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 95 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 95 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR3" description="IAC ILAC input status register 3" start="+0x378" size="4" reset_value="0x000005FF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN96" description="illegal access input 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 96 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 96 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN97" description="illegal access input 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 97 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 97 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN98" description="illegal access input 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 98 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 98 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN99" description="illegal access input 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 99 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 99 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN100" description="illegal access input 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 100 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 100 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN101" description="illegal access input 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 101 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 101 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN102" description="illegal access input 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 102 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 102 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN103" description="illegal access input 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 103 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 103 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN104" description="illegal access input 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 104 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 104 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN105" description="illegal access input 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 105 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 105 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN106" description="illegal access input 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 106 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 106 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN107" description="illegal access input 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 107 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 107 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN108" description="illegal access input 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 108 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 108 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN109" description="illegal access input 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 109 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 109 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN110" description="illegal access input 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 110 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 110 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN111" description="illegal access input 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 111 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 111 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN112" description="illegal access input 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 112 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 112 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN113" description="illegal access input 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 113 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 113 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN114" description="illegal access input 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 114 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 114 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN115" description="illegal access input 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 115 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 115 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN116" description="illegal access input 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 116 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 116 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN117" description="illegal access input 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 117 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 117 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN118" description="illegal access input 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 118 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 118 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN119" description="illegal access input 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 119 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 119 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN120" description="illegal access input 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 120 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 120 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN121" description="illegal access input 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 121 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 121 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN122" description="illegal access input 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 122 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 122 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN123" description="illegal access input 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 123 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 123 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN124" description="illegal access input 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 124 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 124 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN125" description="illegal access input 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 125 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 125 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN126" description="illegal access input 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 126 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 126 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN127" description="illegal access input 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 127 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 127 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR4" description="IAC ILAC input status register 4" start="+0x37C" size="4" reset_value="0x7BEFFFEF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN128" description="illegal access input 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 128 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 128 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN129" description="illegal access input 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 129 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 129 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN130" description="illegal access input 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 130 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 130 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN131" description="illegal access input 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 131 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 131 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN132" description="illegal access input 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 132 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 132 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN133" description="illegal access input 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 133 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 133 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN134" description="illegal access input 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 134 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 134 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN135" description="illegal access input 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 135 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 135 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN136" description="illegal access input 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 136 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 136 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN137" description="illegal access input 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 137 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 137 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN138" description="illegal access input 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 138 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 138 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN139" description="illegal access input 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 139 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 139 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN140" description="illegal access input 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 140 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 140 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN141" description="illegal access input 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 141 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 141 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN142" description="illegal access input 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 142 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 142 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN143" description="illegal access input 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 143 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 143 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN144" description="illegal access input 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 144 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 144 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN145" description="illegal access input 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 145 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 145 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN146" description="illegal access input 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 146 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 146 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN147" description="illegal access input 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 147 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 147 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN148" description="illegal access input 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 148 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 148 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN149" description="illegal access input 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 149 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 149 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN150" description="illegal access input 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 150 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 150 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN151" description="illegal access input 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 151 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 151 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN152" description="illegal access input 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 152 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 152 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN153" description="illegal access input 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 153 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 153 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN154" description="illegal access input 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 154 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 154 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN155" description="illegal access input 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 155 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 155 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN156" description="illegal access input 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 156 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 156 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN157" description="illegal access input 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 157 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 157 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN158" description="illegal access input 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 158 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 158 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN159" description="illegal access input 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 159 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 159 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR5" description="IAC ILAC input status register 5" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN128" description="illegal access input 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 128 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 128 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN129" description="illegal access input 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 129 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 129 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN130" description="illegal access input 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 130 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 130 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN131" description="illegal access input 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 131 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 131 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN132" description="illegal access input 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 132 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 132 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN133" description="illegal access input 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 133 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 133 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN134" description="illegal access input 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 134 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 134 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN135" description="illegal access input 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 135 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 135 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN136" description="illegal access input 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 136 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 136 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN137" description="illegal access input 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 137 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 137 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN138" description="illegal access input 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 138 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 138 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN139" description="illegal access input 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 139 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 139 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN140" description="illegal access input 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 140 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 140 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN141" description="illegal access input 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 141 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 141 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN142" description="illegal access input 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 142 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 142 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN143" description="illegal access input 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 143 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 143 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN144" description="illegal access input 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 144 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 144 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN145" description="illegal access input 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 145 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 145 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN146" description="illegal access input 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 146 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 146 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN147" description="illegal access input 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 147 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 147 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN148" description="illegal access input 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 148 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 148 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN149" description="illegal access input 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 149 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 149 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN150" description="illegal access input 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 150 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 150 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN151" description="illegal access input 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 151 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 151 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN152" description="illegal access input 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 152 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 152 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN153" description="illegal access input 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 153 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 153 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN154" description="illegal access input 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 154 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 154 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN155" description="illegal access input 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 155 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 155 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN156" description="illegal access input 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 156 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 156 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN157" description="illegal access input 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 157 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 157 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN158" description="illegal access input 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 158 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 158 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN159" description="illegal access input 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 159 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 159 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IAC_S" description="Illegal access controller" start="0x54025000">
+    <Register name="IAC_IER0" description="IAC interrupt enable register 0" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE0" description="illegal access interrupt enable for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 0 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 0 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE1" description="illegal access interrupt enable for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 1 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 1 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE2" description="illegal access interrupt enable for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 2 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 2 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE3" description="illegal access interrupt enable for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 3 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 3 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE4" description="illegal access interrupt enable for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 4 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 4 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE5" description="illegal access interrupt enable for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 5 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 5 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE6" description="illegal access interrupt enable for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 6 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 6 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE7" description="illegal access interrupt enable for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 7 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 7 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE8" description="illegal access interrupt enable for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 8 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 8 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE9" description="illegal access interrupt enable for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 9 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 9 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE10" description="illegal access interrupt enable for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 10 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 10 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE11" description="illegal access interrupt enable for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 11 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 11 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE12" description="illegal access interrupt enable for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 12 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 12 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE13" description="illegal access interrupt enable for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 13 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 13 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE14" description="illegal access interrupt enable for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 14 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 14 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE15" description="illegal access interrupt enable for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 15 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 15 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE16" description="illegal access interrupt enable for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 16 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 16 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE17" description="illegal access interrupt enable for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 17 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 17 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE18" description="illegal access interrupt enable for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 18 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 18 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE19" description="illegal access interrupt enable for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 19 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 19 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE20" description="illegal access interrupt enable for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 20 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 20 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE21" description="illegal access interrupt enable for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 21 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 21 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE22" description="illegal access interrupt enable for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 22 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 22 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE23" description="illegal access interrupt enable for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 23 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 23 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE24" description="illegal access interrupt enable for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 24 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 24 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE25" description="illegal access interrupt enable for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 25 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 25 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE26" description="illegal access interrupt enable for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 26 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 26 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE27" description="illegal access interrupt enable for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 27 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 27 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE28" description="illegal access interrupt enable for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 28 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 28 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE29" description="illegal access interrupt enable for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 29 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 29 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE30" description="illegal access interrupt enable for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 30 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 30 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE31" description="illegal access interrupt enable for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 31 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 31 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER1" description="IAC interrupt enable register 1" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE32" description="illegal access interrupt enable for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 32 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 32 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE33" description="illegal access interrupt enable for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 33 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 33 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE34" description="illegal access interrupt enable for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 34 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 34 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE35" description="illegal access interrupt enable for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 35 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 35 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE36" description="illegal access interrupt enable for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 36 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 36 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE37" description="illegal access interrupt enable for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 37 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 37 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE38" description="illegal access interrupt enable for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 38 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 38 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE39" description="illegal access interrupt enable for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 39 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 39 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE40" description="illegal access interrupt enable for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 40 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 40 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE41" description="illegal access interrupt enable for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 41 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 41 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE42" description="illegal access interrupt enable for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 42 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 42 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE43" description="illegal access interrupt enable for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 43 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 43 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE44" description="illegal access interrupt enable for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 44 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 44 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE45" description="illegal access interrupt enable for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 45 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 45 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE46" description="illegal access interrupt enable for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 46 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 46 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE47" description="illegal access interrupt enable for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 47 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 47 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE48" description="illegal access interrupt enable for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 48 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 48 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE49" description="illegal access interrupt enable for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 49 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 49 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE50" description="illegal access interrupt enable for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 50 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 50 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE51" description="illegal access interrupt enable for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 51 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 51 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE52" description="illegal access interrupt enable for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 52 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 52 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE53" description="illegal access interrupt enable for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 53 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 53 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE54" description="illegal access interrupt enable for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 54 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 54 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE55" description="illegal access interrupt enable for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 55 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 55 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE56" description="illegal access interrupt enable for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 56 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 56 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE57" description="illegal access interrupt enable for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 57 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 57 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE58" description="illegal access interrupt enable for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 58 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 58 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE59" description="illegal access interrupt enable for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 59 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 59 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE60" description="illegal access interrupt enable for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 60 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 60 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE61" description="illegal access interrupt enable for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 61 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 61 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE62" description="illegal access interrupt enable for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 62 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 62 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE63" description="illegal access interrupt enable for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 63 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 63 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER2" description="IAC interrupt enable register 2" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE64" description="illegal access interrupt enable for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 64 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 64 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE65" description="illegal access interrupt enable for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 65 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 65 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE66" description="illegal access interrupt enable for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 66 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 66 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE67" description="illegal access interrupt enable for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 67 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 67 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE68" description="illegal access interrupt enable for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 68 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 68 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE69" description="illegal access interrupt enable for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 69 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 69 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE70" description="illegal access interrupt enable for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 70 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 70 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE71" description="illegal access interrupt enable for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 71 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 71 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE72" description="illegal access interrupt enable for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 72 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 72 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE73" description="illegal access interrupt enable for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 73 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 73 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE74" description="illegal access interrupt enable for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 74 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 74 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE75" description="illegal access interrupt enable for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 75 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 75 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE76" description="illegal access interrupt enable for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 76 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 76 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE77" description="illegal access interrupt enable for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 77 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 77 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE78" description="illegal access interrupt enable for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 78 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 78 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE79" description="illegal access interrupt enable for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 79 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 79 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE80" description="illegal access interrupt enable for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 80 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 80 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE81" description="illegal access interrupt enable for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 81 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 81 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE82" description="illegal access interrupt enable for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 82 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 82 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE83" description="illegal access interrupt enable for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 83 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 83 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE84" description="illegal access interrupt enable for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 84 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 84 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE85" description="illegal access interrupt enable for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 85 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 85 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE86" description="illegal access interrupt enable for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 86 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 86 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE87" description="illegal access interrupt enable for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 87 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 87 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE88" description="illegal access interrupt enable for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 88 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 88 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE89" description="illegal access interrupt enable for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 89 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 89 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE90" description="illegal access interrupt enable for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 90 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 90 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE91" description="illegal access interrupt enable for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 91 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 91 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE92" description="illegal access interrupt enable for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 92 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 92 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE93" description="illegal access interrupt enable for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 93 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 93 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE94" description="illegal access interrupt enable for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 94 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 94 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE95" description="illegal access interrupt enable for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 95 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 95 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER3" description="IAC interrupt enable register 3" start="+0xC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE96" description="illegal access interrupt enable for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 96 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 96 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE97" description="illegal access interrupt enable for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 97 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 97 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE98" description="illegal access interrupt enable for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 98 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 98 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE99" description="illegal access interrupt enable for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 99 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 99 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE100" description="illegal access interrupt enable for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 100 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 100 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE101" description="illegal access interrupt enable for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 101 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 101 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE102" description="illegal access interrupt enable for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 102 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 102 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE103" description="illegal access interrupt enable for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 103 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 103 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE104" description="illegal access interrupt enable for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 104 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 104 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE105" description="illegal access interrupt enable for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 105 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 105 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE106" description="illegal access interrupt enable for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 106 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 106 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE107" description="illegal access interrupt enable for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 107 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 107 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE108" description="illegal access interrupt enable for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 108 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 108 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE109" description="illegal access interrupt enable for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 109 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 109 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE110" description="illegal access interrupt enable for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 110 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 110 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE111" description="illegal access interrupt enable for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 111 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 111 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE112" description="illegal access interrupt enable for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 112 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 112 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE113" description="illegal access interrupt enable for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 113 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 113 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE114" description="illegal access interrupt enable for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 114 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 114 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE115" description="illegal access interrupt enable for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 115 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 115 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE116" description="illegal access interrupt enable for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 116 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 116 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE117" description="illegal access interrupt enable for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 117 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 117 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE118" description="illegal access interrupt enable for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 118 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 118 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE119" description="illegal access interrupt enable for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 119 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 119 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE120" description="illegal access interrupt enable for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 120 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 120 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE121" description="illegal access interrupt enable for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 121 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 121 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE122" description="illegal access interrupt enable for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 122 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 122 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE123" description="illegal access interrupt enable for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 123 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 123 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE124" description="illegal access interrupt enable for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 124 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 124 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE125" description="illegal access interrupt enable for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 125 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 125 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE126" description="illegal access interrupt enable for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 126 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 126 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE127" description="illegal access interrupt enable for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 127 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 127 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER4" description="IAC interrupt enable register 4" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE128" description="illegal access interrupt enable for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 128 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 128 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE129" description="illegal access interrupt enable for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 129 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 129 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE130" description="illegal access interrupt enable for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 130 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 130 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE131" description="illegal access interrupt enable for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 131 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 131 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE132" description="illegal access interrupt enable for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 132 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 132 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE133" description="illegal access interrupt enable for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 133 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 133 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE134" description="illegal access interrupt enable for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 134 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 134 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE135" description="illegal access interrupt enable for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 135 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 135 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE136" description="illegal access interrupt enable for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 136 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 136 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE137" description="illegal access interrupt enable for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 137 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 137 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE138" description="illegal access interrupt enable for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 138 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 138 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE139" description="illegal access interrupt enable for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 139 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 139 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE140" description="illegal access interrupt enable for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 140 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 140 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE141" description="illegal access interrupt enable for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 141 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 141 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE142" description="illegal access interrupt enable for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 142 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 142 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE143" description="illegal access interrupt enable for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 143 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 143 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE144" description="illegal access interrupt enable for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 144 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 144 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE145" description="illegal access interrupt enable for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 145 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 145 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE146" description="illegal access interrupt enable for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 146 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 146 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE147" description="illegal access interrupt enable for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 147 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 147 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE148" description="illegal access interrupt enable for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 148 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 148 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE149" description="illegal access interrupt enable for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 149 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 149 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE150" description="illegal access interrupt enable for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 150 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 150 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE151" description="illegal access interrupt enable for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 151 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 151 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE152" description="illegal access interrupt enable for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 152 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 152 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE153" description="illegal access interrupt enable for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 153 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 153 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE154" description="illegal access interrupt enable for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 154 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 154 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE155" description="illegal access interrupt enable for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 155 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 155 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE156" description="illegal access interrupt enable for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 156 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 156 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE157" description="illegal access interrupt enable for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 157 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 157 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE158" description="illegal access interrupt enable for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 158 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 158 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE159" description="illegal access interrupt enable for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 159 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 159 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IER5" description="IAC interrupt enable register 5" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAIE160" description="illegal access interrupt enable for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 160 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 160 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE161" description="illegal access interrupt enable for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 161 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 161 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE162" description="illegal access interrupt enable for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 162 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 162 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE163" description="illegal access interrupt enable for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 163 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 163 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE164" description="illegal access interrupt enable for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 164 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 164 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE165" description="illegal access interrupt enable for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 165 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 165 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE166" description="illegal access interrupt enable for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 166 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 166 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE167" description="illegal access interrupt enable for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 167 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 167 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE168" description="illegal access interrupt enable for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 168 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 168 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE169" description="illegal access interrupt enable for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 169 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 169 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE170" description="illegal access interrupt enable for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 170 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 170 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE171" description="illegal access interrupt enable for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 171 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 171 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE172" description="illegal access interrupt enable for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 172 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 172 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE173" description="illegal access interrupt enable for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 173 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 173 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE174" description="illegal access interrupt enable for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 174 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 174 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE175" description="illegal access interrupt enable for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 175 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 175 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE176" description="illegal access interrupt enable for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 176 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 176 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE177" description="illegal access interrupt enable for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 177 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 177 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE178" description="illegal access interrupt enable for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 178 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 178 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE179" description="illegal access interrupt enable for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 179 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 179 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE180" description="illegal access interrupt enable for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 180 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 180 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE181" description="illegal access interrupt enable for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 181 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 181 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE182" description="illegal access interrupt enable for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 182 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 182 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE183" description="illegal access interrupt enable for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 183 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 183 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE184" description="illegal access interrupt enable for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 184 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 184 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE185" description="illegal access interrupt enable for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 185 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 185 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE186" description="illegal access interrupt enable for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 186 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 186 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE187" description="illegal access interrupt enable for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 187 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 187 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE188" description="illegal access interrupt enable for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 188 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 188 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE189" description="illegal access interrupt enable for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 189 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 189 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE190" description="illegal access interrupt enable for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 190 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 190 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+      <BitField name="IAIE191" description="illegal access interrupt enable for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Illegal access event from peripheral 191 does not generate interrupt (masked)." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access event from peripheral 191 can generate interrupts (unmasked)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR0" description="IAC interrupt status register 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF0" description="illegal access interrupt enable for peripheral 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 0 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 0 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF1" description="illegal access interrupt enable for peripheral 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 1 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 1 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF2" description="illegal access interrupt enable for peripheral 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 2 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 2 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF3" description="illegal access interrupt enable for peripheral 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 3 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 3 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF4" description="illegal access interrupt enable for peripheral 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 4 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 4 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF5" description="illegal access interrupt enable for peripheral 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 5 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 5 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF6" description="illegal access interrupt enable for peripheral 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 6 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 6 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF7" description="illegal access interrupt enable for peripheral 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 7 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 7 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF8" description="illegal access interrupt enable for peripheral 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 8 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 8 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF9" description="illegal access interrupt enable for peripheral 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 9 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 9 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF10" description="illegal access interrupt enable for peripheral 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 10 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 10 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF11" description="illegal access interrupt enable for peripheral 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 11 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 11 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF12" description="illegal access interrupt enable for peripheral 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 12 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 12 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF13" description="illegal access interrupt enable for peripheral 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 13 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 13 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF14" description="illegal access interrupt enable for peripheral 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 14 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 14 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF15" description="illegal access interrupt enable for peripheral 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 15 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 15 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF16" description="illegal access interrupt enable for peripheral 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 16 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 16 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF17" description="illegal access interrupt enable for peripheral 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 17 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 17 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF18" description="illegal access interrupt enable for peripheral 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 18 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 18 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF19" description="illegal access interrupt enable for peripheral 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 19 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 19 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF20" description="illegal access interrupt enable for peripheral 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 20 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 20 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF21" description="illegal access interrupt enable for peripheral 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 21 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 21 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF22" description="illegal access interrupt enable for peripheral 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 22 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 22 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF23" description="illegal access interrupt enable for peripheral 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 23 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 23 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF24" description="illegal access interrupt enable for peripheral 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 24 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 24 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF25" description="illegal access interrupt enable for peripheral 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 25 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 25 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF26" description="illegal access interrupt enable for peripheral 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 26 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 26 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF27" description="illegal access interrupt enable for peripheral 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 27 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 27 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF28" description="illegal access interrupt enable for peripheral 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 28 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 28 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF29" description="illegal access interrupt enable for peripheral 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 29 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 29 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF30" description="illegal access interrupt enable for peripheral 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 30 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 30 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF31" description="illegal access interrupt enable for peripheral 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 31 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 31 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR1" description="IAC interrupt status register 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF32" description="illegal access interrupt enable for peripheral 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 32 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 32 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF33" description="illegal access interrupt enable for peripheral 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 33 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 33 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF34" description="illegal access interrupt enable for peripheral 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 34 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 34 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF35" description="illegal access interrupt enable for peripheral 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 35 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 35 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF36" description="illegal access interrupt enable for peripheral 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 36 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 36 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF37" description="illegal access interrupt enable for peripheral 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 37 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 37 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF38" description="illegal access interrupt enable for peripheral 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 38 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 38 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF39" description="illegal access interrupt enable for peripheral 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 39 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 39 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF40" description="illegal access interrupt enable for peripheral 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 40 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 40 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF41" description="illegal access interrupt enable for peripheral 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 41 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 41 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF42" description="illegal access interrupt enable for peripheral 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 42 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 42 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF43" description="illegal access interrupt enable for peripheral 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 43 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 43 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF44" description="illegal access interrupt enable for peripheral 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 44 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 44 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF45" description="illegal access interrupt enable for peripheral 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 45 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 45 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF46" description="illegal access interrupt enable for peripheral 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 46 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 46 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF47" description="illegal access interrupt enable for peripheral 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 47 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 47 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF48" description="illegal access interrupt enable for peripheral 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 48 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 48 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF49" description="illegal access interrupt enable for peripheral 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 49 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 49 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF50" description="illegal access interrupt enable for peripheral 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 50 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 50 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF51" description="illegal access interrupt enable for peripheral 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 51 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 51 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF52" description="illegal access interrupt enable for peripheral 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 52 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 52 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF53" description="illegal access interrupt enable for peripheral 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 53 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 53 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF54" description="illegal access interrupt enable for peripheral 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 54 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 54 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF55" description="illegal access interrupt enable for peripheral 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 55 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 55 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF56" description="illegal access interrupt enable for peripheral 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 56 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 56 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF57" description="illegal access interrupt enable for peripheral 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 57 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 57 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF58" description="illegal access interrupt enable for peripheral 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 58 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 58 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF59" description="illegal access interrupt enable for peripheral 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 59 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 59 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF60" description="illegal access interrupt enable for peripheral 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 60 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 60 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF61" description="illegal access interrupt enable for peripheral 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 61 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 61 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF62" description="illegal access interrupt enable for peripheral 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 62 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 62 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF63" description="illegal access interrupt enable for peripheral 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 63 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 63 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR2" description="IAC interrupt status register 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF64" description="illegal access interrupt enable for peripheral 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 64 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 64 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF65" description="illegal access interrupt enable for peripheral 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 65 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 65 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF66" description="illegal access interrupt enable for peripheral 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 66 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 66 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF67" description="illegal access interrupt enable for peripheral 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 67 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 67 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF68" description="illegal access interrupt enable for peripheral 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 68 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 68 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF69" description="illegal access interrupt enable for peripheral 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 69 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 69 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF70" description="illegal access interrupt enable for peripheral 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 70 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 70 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF71" description="illegal access interrupt enable for peripheral 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 71 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 71 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF72" description="illegal access interrupt enable for peripheral 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 72 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 72 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF73" description="illegal access interrupt enable for peripheral 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 73 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 73 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF74" description="illegal access interrupt enable for peripheral 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 74 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 74 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF75" description="illegal access interrupt enable for peripheral 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 75 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 75 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF76" description="illegal access interrupt enable for peripheral 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 76 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 76 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF77" description="illegal access interrupt enable for peripheral 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 77 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 77 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF78" description="illegal access interrupt enable for peripheral 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 78 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 78 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF79" description="illegal access interrupt enable for peripheral 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 79 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 79 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF80" description="illegal access interrupt enable for peripheral 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 80 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 80 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF81" description="illegal access interrupt enable for peripheral 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 81 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 81 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF82" description="illegal access interrupt enable for peripheral 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 82 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 82 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF83" description="illegal access interrupt enable for peripheral 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 83 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 83 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF84" description="illegal access interrupt enable for peripheral 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 84 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 84 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF85" description="illegal access interrupt enable for peripheral 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 85 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 85 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF86" description="illegal access interrupt enable for peripheral 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 86 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 86 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF87" description="illegal access interrupt enable for peripheral 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 87 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 87 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF88" description="illegal access interrupt enable for peripheral 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 88 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 88 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF89" description="illegal access interrupt enable for peripheral 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 89 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 89 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF90" description="illegal access interrupt enable for peripheral 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 90 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 90 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF91" description="illegal access interrupt enable for peripheral 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 91 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 91 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF92" description="illegal access interrupt enable for peripheral 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 92 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 92 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF93" description="illegal access interrupt enable for peripheral 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 93 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 93 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF94" description="illegal access interrupt enable for peripheral 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 94 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 94 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF95" description="illegal access interrupt enable for peripheral 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 95 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 95 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR3" description="IAC interrupt status register 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF96" description="illegal access interrupt enable for peripheral 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 96 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 96 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF97" description="illegal access interrupt enable for peripheral 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 97 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 97 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF98" description="illegal access interrupt enable for peripheral 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 98 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 98 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF99" description="illegal access interrupt enable for peripheral 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 99 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 99 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF100" description="illegal access interrupt enable for peripheral 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 100 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 100 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF101" description="illegal access interrupt enable for peripheral 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 101 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 101 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF102" description="illegal access interrupt enable for peripheral 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 102 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 102 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF103" description="illegal access interrupt enable for peripheral 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 103 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 103 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF104" description="illegal access interrupt enable for peripheral 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 104 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 104 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF105" description="illegal access interrupt enable for peripheral 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 105 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 105 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF106" description="illegal access interrupt enable for peripheral 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 106 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 106 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF107" description="illegal access interrupt enable for peripheral 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 107 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 107 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF108" description="illegal access interrupt enable for peripheral 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 108 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 108 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF109" description="illegal access interrupt enable for peripheral 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 109 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 109 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF110" description="illegal access interrupt enable for peripheral 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 110 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 110 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF111" description="illegal access interrupt enable for peripheral 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 111 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 111 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF112" description="illegal access interrupt enable for peripheral 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 112 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 112 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF113" description="illegal access interrupt enable for peripheral 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 113 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 113 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF114" description="illegal access interrupt enable for peripheral 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 114 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 114 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF115" description="illegal access interrupt enable for peripheral 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 115 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 115 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF116" description="illegal access interrupt enable for peripheral 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 116 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 116 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF117" description="illegal access interrupt enable for peripheral 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 117 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 117 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF118" description="illegal access interrupt enable for peripheral 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 118 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 118 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF119" description="illegal access interrupt enable for peripheral 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 119 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 119 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF120" description="illegal access interrupt enable for peripheral 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 120 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 120 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF121" description="illegal access interrupt enable for peripheral 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 121 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 121 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF122" description="illegal access interrupt enable for peripheral 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 122 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 122 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF123" description="illegal access interrupt enable for peripheral 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 123 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 123 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF124" description="illegal access interrupt enable for peripheral 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 124 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 124 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF125" description="illegal access interrupt enable for peripheral 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 125 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 125 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF126" description="illegal access interrupt enable for peripheral 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 126 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 126 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF127" description="illegal access interrupt enable for peripheral 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 127 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 127 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR4" description="IAC interrupt status register 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF128" description="illegal access interrupt enable for peripheral 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 128 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 128 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF129" description="illegal access interrupt enable for peripheral 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 129 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 129 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF130" description="illegal access interrupt enable for peripheral 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 130 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 130 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF131" description="illegal access interrupt enable for peripheral 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 131 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 131 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF132" description="illegal access interrupt enable for peripheral 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 132 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 132 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF133" description="illegal access interrupt enable for peripheral 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 133 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 133 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF134" description="illegal access interrupt enable for peripheral 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 134 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 134 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF135" description="illegal access interrupt enable for peripheral 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 135 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 135 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF136" description="illegal access interrupt enable for peripheral 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 136 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 136 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF137" description="illegal access interrupt enable for peripheral 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 137 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 137 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF138" description="illegal access interrupt enable for peripheral 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 138 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 138 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF139" description="illegal access interrupt enable for peripheral 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 139 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 139 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF140" description="illegal access interrupt enable for peripheral 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 140 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 140 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF141" description="illegal access interrupt enable for peripheral 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 141 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 141 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF142" description="illegal access interrupt enable for peripheral 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 142 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 142 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF143" description="illegal access interrupt enable for peripheral 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 143 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 143 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF144" description="illegal access interrupt enable for peripheral 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 144 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 144 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF145" description="illegal access interrupt enable for peripheral 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 145 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 145 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF146" description="illegal access interrupt enable for peripheral 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 146 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 146 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF147" description="illegal access interrupt enable for peripheral 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 147 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 147 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF148" description="illegal access interrupt enable for peripheral 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 148 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 148 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF149" description="illegal access interrupt enable for peripheral 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 149 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 149 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF150" description="illegal access interrupt enable for peripheral 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 150 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 150 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF151" description="illegal access interrupt enable for peripheral 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 151 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 151 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF152" description="illegal access interrupt enable for peripheral 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 152 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 152 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF153" description="illegal access interrupt enable for peripheral 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 153 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 153 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF154" description="illegal access interrupt enable for peripheral 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 154 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 154 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF155" description="illegal access interrupt enable for peripheral 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 155 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 155 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF156" description="illegal access interrupt enable for peripheral 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 156 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 156 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF157" description="illegal access interrupt enable for peripheral 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 157 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 157 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF158" description="illegal access interrupt enable for peripheral 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 158 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 158 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF159" description="illegal access interrupt enable for peripheral 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 159 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 159 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ISR5" description="IAC interrupt status register 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF160" description="illegal access interrupt enable for peripheral 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 160 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 160 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF161" description="illegal access interrupt enable for peripheral 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 161 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 161 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF162" description="illegal access interrupt enable for peripheral 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 162 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 162 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF163" description="illegal access interrupt enable for peripheral 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 163 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 163 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF164" description="illegal access interrupt enable for peripheral 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 164 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 164 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF165" description="illegal access interrupt enable for peripheral 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 165 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 165 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF166" description="illegal access interrupt enable for peripheral 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 166 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 166 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF167" description="illegal access interrupt enable for peripheral 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 167 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 167 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF168" description="illegal access interrupt enable for peripheral 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 168 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 168 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF169" description="illegal access interrupt enable for peripheral 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 169 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 169 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF170" description="illegal access interrupt enable for peripheral 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 170 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 170 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF171" description="illegal access interrupt enable for peripheral 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 171 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 171 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF172" description="illegal access interrupt enable for peripheral 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 172 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 172 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF173" description="illegal access interrupt enable for peripheral 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 173 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 173 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF174" description="illegal access interrupt enable for peripheral 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 174 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 174 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF175" description="illegal access interrupt enable for peripheral 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 175 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 175 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF176" description="illegal access interrupt enable for peripheral 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 176 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 176 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF177" description="illegal access interrupt enable for peripheral 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 177 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 177 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF178" description="illegal access interrupt enable for peripheral 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 178 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 178 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF179" description="illegal access interrupt enable for peripheral 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 179 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 179 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF180" description="illegal access interrupt enable for peripheral 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 180 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 180 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF181" description="illegal access interrupt enable for peripheral 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 181 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 181 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF182" description="illegal access interrupt enable for peripheral 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 182 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 182 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF183" description="illegal access interrupt enable for peripheral 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 183 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 183 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF184" description="illegal access interrupt enable for peripheral 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 184 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 184 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF185" description="illegal access interrupt enable for peripheral 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 185 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 185 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF186" description="illegal access interrupt enable for peripheral 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 186 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 186 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF187" description="illegal access interrupt enable for peripheral 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 187 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 187 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF188" description="illegal access interrupt enable for peripheral 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 188 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 188 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF189" description="illegal access interrupt enable for peripheral 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 189 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 189 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF190" description="illegal access interrupt enable for peripheral 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 190 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 190 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+      <BitField name="IAF191" description="illegal access interrupt enable for peripheral 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No illegal access event detected for peripheral 191 (since reset or the last time this bit was cleared)." start="0x0" />
+        <Enum name="B_0x1" description="At least one illegal access event has been detected for peripheral 191 (since the last time this bit was cleared)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR0" description="IAC interrupt clear register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF0" description="illegal access flag clear for peripheral 0" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 0 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 0 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF1" description="illegal access flag clear for peripheral 1" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 1 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 1 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF2" description="illegal access flag clear for peripheral 2" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 2 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 2 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF3" description="illegal access flag clear for peripheral 3" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 3 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 3 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF4" description="illegal access flag clear for peripheral 4" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 4 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 4 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF5" description="illegal access flag clear for peripheral 5" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 5 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 5 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF6" description="illegal access flag clear for peripheral 6" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 6 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 6 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF7" description="illegal access flag clear for peripheral 7" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 7 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 7 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF8" description="illegal access flag clear for peripheral 8" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 8 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 8 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF9" description="illegal access flag clear for peripheral 9" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 9 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 9 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF10" description="illegal access flag clear for peripheral 10" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 10 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 10 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF11" description="illegal access flag clear for peripheral 11" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 11 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 11 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF12" description="illegal access flag clear for peripheral 12" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 12 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 12 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF13" description="illegal access flag clear for peripheral 13" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 13 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 13 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF14" description="illegal access flag clear for peripheral 14" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 14 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 14 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF15" description="illegal access flag clear for peripheral 15" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 15 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 15 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF16" description="illegal access flag clear for peripheral 16" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 16 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 16 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF17" description="illegal access flag clear for peripheral 17" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 17 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 17 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF18" description="illegal access flag clear for peripheral 18" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 18 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 18 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF19" description="illegal access flag clear for peripheral 19" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 19 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 19 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF20" description="illegal access flag clear for peripheral 20" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 20 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 20 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF21" description="illegal access flag clear for peripheral 21" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 21 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 21 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF22" description="illegal access flag clear for peripheral 22" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 22 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 22 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF23" description="illegal access flag clear for peripheral 23" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 23 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 23 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF24" description="illegal access flag clear for peripheral 24" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 24 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 24 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF25" description="illegal access flag clear for peripheral 25" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 25 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 25 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF26" description="illegal access flag clear for peripheral 26" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 26 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 26 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF27" description="illegal access flag clear for peripheral 27" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 27 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 27 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF28" description="illegal access flag clear for peripheral 28" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 28 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 28 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF29" description="illegal access flag clear for peripheral 29" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 29 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 29 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF30" description="illegal access flag clear for peripheral 30" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 30 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 30 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF31" description="illegal access flag clear for peripheral 31" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 31 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 31 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR1" description="IAC interrupt clear register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF32" description="illegal access flag clear for peripheral 32" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 32 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 32 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF33" description="illegal access flag clear for peripheral 33" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 33 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 33 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF34" description="illegal access flag clear for peripheral 34" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 34 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 34 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF35" description="illegal access flag clear for peripheral 35" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 35 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 35 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF36" description="illegal access flag clear for peripheral 36" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 36 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 36 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF37" description="illegal access flag clear for peripheral 37" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 37 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 37 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF38" description="illegal access flag clear for peripheral 38" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 38 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 38 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF39" description="illegal access flag clear for peripheral 39" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 39 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 39 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF40" description="illegal access flag clear for peripheral 40" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 40 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 40 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF41" description="illegal access flag clear for peripheral 41" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 41 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 41 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF42" description="illegal access flag clear for peripheral 42" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 42 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 42 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF43" description="illegal access flag clear for peripheral 43" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 43 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 43 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF44" description="illegal access flag clear for peripheral 44" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 44 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 44 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF45" description="illegal access flag clear for peripheral 45" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 45 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 45 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF46" description="illegal access flag clear for peripheral 46" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 46 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 46 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF47" description="illegal access flag clear for peripheral 47" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 47 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 47 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF48" description="illegal access flag clear for peripheral 48" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 48 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 48 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF49" description="illegal access flag clear for peripheral 49" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 49 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 49 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF50" description="illegal access flag clear for peripheral 50" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 50 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 50 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF51" description="illegal access flag clear for peripheral 51" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 51 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 51 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF52" description="illegal access flag clear for peripheral 52" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 52 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 52 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF53" description="illegal access flag clear for peripheral 53" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 53 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 53 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF54" description="illegal access flag clear for peripheral 54" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 54 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 54 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF55" description="illegal access flag clear for peripheral 55" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 55 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 55 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF56" description="illegal access flag clear for peripheral 56" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 56 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 56 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF57" description="illegal access flag clear for peripheral 57" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 57 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 57 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF58" description="illegal access flag clear for peripheral 58" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 58 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 58 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF59" description="illegal access flag clear for peripheral 59" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 59 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 59 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF60" description="illegal access flag clear for peripheral 60" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 60 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 60 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF61" description="illegal access flag clear for peripheral 61" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 61 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 61 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF62" description="illegal access flag clear for peripheral 62" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 62 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 62 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF63" description="illegal access flag clear for peripheral 63" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 63 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 63 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR2" description="IAC interrupt clear register 2" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF64" description="illegal access flag clear for peripheral 64" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 64 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 64 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF65" description="illegal access flag clear for peripheral 65" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 65 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 65 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF66" description="illegal access flag clear for peripheral 66" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 66 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 66 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF67" description="illegal access flag clear for peripheral 67" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 67 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 67 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF68" description="illegal access flag clear for peripheral 68" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 68 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 68 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF69" description="illegal access flag clear for peripheral 69" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 69 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 69 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF70" description="illegal access flag clear for peripheral 70" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 70 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 70 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF71" description="illegal access flag clear for peripheral 71" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 71 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 71 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF72" description="illegal access flag clear for peripheral 72" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 72 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 72 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF73" description="illegal access flag clear for peripheral 73" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 73 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 73 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF74" description="illegal access flag clear for peripheral 74" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 74 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 74 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF75" description="illegal access flag clear for peripheral 75" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 75 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 75 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF76" description="illegal access flag clear for peripheral 76" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 76 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 76 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF77" description="illegal access flag clear for peripheral 77" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 77 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 77 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF78" description="illegal access flag clear for peripheral 78" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 78 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 78 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF79" description="illegal access flag clear for peripheral 79" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 79 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 79 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF80" description="illegal access flag clear for peripheral 80" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 80 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 80 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF81" description="illegal access flag clear for peripheral 81" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 81 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 81 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF82" description="illegal access flag clear for peripheral 82" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 82 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 82 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF83" description="illegal access flag clear for peripheral 83" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 83 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 83 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF84" description="illegal access flag clear for peripheral 84" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 84 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 84 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF85" description="illegal access flag clear for peripheral 85" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 85 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 85 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF86" description="illegal access flag clear for peripheral 86" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 86 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 86 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF87" description="illegal access flag clear for peripheral 87" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 87 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 87 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF88" description="illegal access flag clear for peripheral 88" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 88 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 88 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF89" description="illegal access flag clear for peripheral 89" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 89 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 89 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF90" description="illegal access flag clear for peripheral 90" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 90 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 90 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF91" description="illegal access flag clear for peripheral 91" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 91 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 91 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF92" description="illegal access flag clear for peripheral 92" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 92 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 92 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF93" description="illegal access flag clear for peripheral 93" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 93 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 93 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF94" description="illegal access flag clear for peripheral 94" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 94 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 94 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF95" description="illegal access flag clear for peripheral 95" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 95 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 95 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR3" description="IAC interrupt clear register 3" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF96" description="illegal access flag clear for peripheral 96" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 96 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 96 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF97" description="illegal access flag clear for peripheral 97" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 97 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 97 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF98" description="illegal access flag clear for peripheral 98" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 98 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 98 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF99" description="illegal access flag clear for peripheral 99" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 99 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 99 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF100" description="illegal access flag clear for peripheral 100" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 100 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 100 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF101" description="illegal access flag clear for peripheral 101" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 101 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 101 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF102" description="illegal access flag clear for peripheral 102" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 102 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 102 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF103" description="illegal access flag clear for peripheral 103" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 103 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 103 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF104" description="illegal access flag clear for peripheral 104" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 104 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 104 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF105" description="illegal access flag clear for peripheral 105" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 105 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 105 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF106" description="illegal access flag clear for peripheral 106" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 106 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 106 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF107" description="illegal access flag clear for peripheral 107" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 107 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 107 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF108" description="illegal access flag clear for peripheral 108" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 108 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 108 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF109" description="illegal access flag clear for peripheral 109" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 109 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 109 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF110" description="illegal access flag clear for peripheral 110" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 110 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 110 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF111" description="illegal access flag clear for peripheral 111" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 111 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 111 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF112" description="illegal access flag clear for peripheral 112" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 112 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 112 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF113" description="illegal access flag clear for peripheral 113" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 113 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 113 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF114" description="illegal access flag clear for peripheral 114" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 114 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 114 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF115" description="illegal access flag clear for peripheral 115" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 115 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 115 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF116" description="illegal access flag clear for peripheral 116" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 116 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 116 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF117" description="illegal access flag clear for peripheral 117" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 117 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 117 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF118" description="illegal access flag clear for peripheral 118" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 118 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 118 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF119" description="illegal access flag clear for peripheral 119" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 119 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 119 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF120" description="illegal access flag clear for peripheral 120" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 120 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 120 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF121" description="illegal access flag clear for peripheral 121" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 121 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 121 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF122" description="illegal access flag clear for peripheral 122" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 122 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 122 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF123" description="illegal access flag clear for peripheral 123" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 123 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 123 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF124" description="illegal access flag clear for peripheral 124" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 124 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 124 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF125" description="illegal access flag clear for peripheral 125" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 125 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 125 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF126" description="illegal access flag clear for peripheral 126" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 126 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 126 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF127" description="illegal access flag clear for peripheral 127" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 127 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 127 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR4" description="IAC interrupt clear register 4" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF128" description="illegal access flag clear for peripheral 128" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 128 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 128 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF129" description="illegal access flag clear for peripheral 129" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 129 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 129 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF130" description="illegal access flag clear for peripheral 130" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 130 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 130 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF131" description="illegal access flag clear for peripheral 131" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 131 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 131 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF132" description="illegal access flag clear for peripheral 132" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 132 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 132 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF133" description="illegal access flag clear for peripheral 133" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 133 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 133 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF134" description="illegal access flag clear for peripheral 134" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 134 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 134 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF135" description="illegal access flag clear for peripheral 135" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 135 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 135 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF136" description="illegal access flag clear for peripheral 136" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 136 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 136 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF137" description="illegal access flag clear for peripheral 137" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 137 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 137 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF138" description="illegal access flag clear for peripheral 138" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 138 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 138 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF139" description="illegal access flag clear for peripheral 139" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 139 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 139 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF140" description="illegal access flag clear for peripheral 140" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 140 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 140 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF141" description="illegal access flag clear for peripheral 141" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 141 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 141 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF142" description="illegal access flag clear for peripheral 142" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 142 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 142 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF143" description="illegal access flag clear for peripheral 143" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 143 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 143 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF144" description="illegal access flag clear for peripheral 144" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 144 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 144 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF145" description="illegal access flag clear for peripheral 145" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 145 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 145 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF146" description="illegal access flag clear for peripheral 146" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 146 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 146 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF147" description="illegal access flag clear for peripheral 147" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 147 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 147 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF148" description="illegal access flag clear for peripheral 148" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 148 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 148 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF149" description="illegal access flag clear for peripheral 149" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 149 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 149 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF150" description="illegal access flag clear for peripheral 150" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 150 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 150 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF151" description="illegal access flag clear for peripheral 151" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 151 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 151 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF152" description="illegal access flag clear for peripheral 152" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 152 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 152 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF153" description="illegal access flag clear for peripheral 153" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 153 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 153 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF154" description="illegal access flag clear for peripheral 154" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 154 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 154 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF155" description="illegal access flag clear for peripheral 155" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 155 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 155 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF156" description="illegal access flag clear for peripheral 156" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 156 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 156 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF157" description="illegal access flag clear for peripheral 157" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 157 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 157 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF158" description="illegal access flag clear for peripheral 158" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 158 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 158 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF159" description="illegal access flag clear for peripheral 159" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 159 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 159 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_ICR5" description="IAC interrupt clear register 5" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAF160" description="illegal access flag clear for peripheral 160" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 160 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 160 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF161" description="illegal access flag clear for peripheral 161" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 161 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 161 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF162" description="illegal access flag clear for peripheral 162" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 162 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 162 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF163" description="illegal access flag clear for peripheral 163" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 163 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 163 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF164" description="illegal access flag clear for peripheral 164" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 164 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 164 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF165" description="illegal access flag clear for peripheral 165" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 165 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 165 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF166" description="illegal access flag clear for peripheral 166" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 166 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 166 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF167" description="illegal access flag clear for peripheral 167" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 167 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 167 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF168" description="illegal access flag clear for peripheral 168" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 168 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 168 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF169" description="illegal access flag clear for peripheral 169" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 169 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 169 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF170" description="illegal access flag clear for peripheral 170" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 170 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 170 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF171" description="illegal access flag clear for peripheral 171" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 171 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 171 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF172" description="illegal access flag clear for peripheral 172" start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 172 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 172 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF173" description="illegal access flag clear for peripheral 173" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 173 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 173 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF174" description="illegal access flag clear for peripheral 174" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 174 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 174 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF175" description="illegal access flag clear for peripheral 175" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 175 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 175 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF176" description="illegal access flag clear for peripheral 176" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 176 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 176 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF177" description="illegal access flag clear for peripheral 177" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 177 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 177 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF178" description="illegal access flag clear for peripheral 178" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 178 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 178 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF179" description="illegal access flag clear for peripheral 179" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 179 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 179 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF180" description="illegal access flag clear for peripheral 180" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 180 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 180 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF181" description="illegal access flag clear for peripheral 181" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 181 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 181 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF182" description="illegal access flag clear for peripheral 182" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 182 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 182 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF183" description="illegal access flag clear for peripheral 183" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 183 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 183 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF184" description="illegal access flag clear for peripheral 184" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 184 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 184 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF185" description="illegal access flag clear for peripheral 185" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 185 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 185 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF186" description="illegal access flag clear for peripheral 186" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 186 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 186 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF187" description="illegal access flag clear for peripheral 187" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 187 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 187 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF188" description="illegal access flag clear for peripheral 188" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 188 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 188 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF189" description="illegal access flag clear for peripheral 189" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 189 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 189 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF190" description="illegal access flag clear for peripheral 190" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 190 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 190 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+      <BitField name="IAF191" description="illegal access flag clear for peripheral 191" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IAF 191 flag status not affected" start="0x0" />
+        <Enum name="B_0x1" description="IAF 191 flag status cleared in IAC_ISRx" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR0" description="IAC ILAC input status register 0" start="+0x36C" size="4" reset_value="0xFFFFFF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN0" description="illegal access input 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 0 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 0 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN1" description="illegal access input 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 1 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 1 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN2" description="illegal access input 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 2 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 2 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN3" description="illegal access input 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 3 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 3 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN4" description="illegal access input 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 4 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 4 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN5" description="illegal access input 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 5 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 5 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN6" description="illegal access input 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 6 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 6 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN7" description="illegal access input 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 7 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 7 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN8" description="illegal access input 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 8 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 8 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN9" description="illegal access input 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 9 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 9 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN10" description="illegal access input 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 10 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 10 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN11" description="illegal access input 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 11 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 11 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN12" description="illegal access input 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 12 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 12 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN13" description="illegal access input 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 13 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 13 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN14" description="illegal access input 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 14 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 14 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN15" description="illegal access input 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 15 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 15 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN16" description="illegal access input 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 16 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 16 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN17" description="illegal access input 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 17 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 17 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN18" description="illegal access input 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 18 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 18 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN19" description="illegal access input 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 19 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 19 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN20" description="illegal access input 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 20 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 20 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN21" description="illegal access input 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 21 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 21 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN22" description="illegal access input 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 22 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 22 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN23" description="illegal access input 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 23 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 23 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN24" description="illegal access input 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 24 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 24 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN25" description="illegal access input 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 25 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 25 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN26" description="illegal access input 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 26 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 26 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN27" description="illegal access input 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 27 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 27 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN28" description="illegal access input 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 28 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 28 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN29" description="illegal access input 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 29 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 29 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN30" description="illegal access input 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 30 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 30 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN31" description="illegal access input 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 31 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 31 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR1" description="IAC ILAC input status register 1" start="+0x370" size="4" reset_value="0x77FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN32" description="illegal access input 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 32 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 32 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN33" description="illegal access input 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 33 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 33 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN34" description="illegal access input 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 34 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 34 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN35" description="illegal access input 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 35 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 35 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN36" description="illegal access input 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 36 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 36 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN37" description="illegal access input 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 37 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 37 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN38" description="illegal access input 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 38 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 38 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN39" description="illegal access input 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 39 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 39 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN40" description="illegal access input 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 40 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 40 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN41" description="illegal access input 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 41 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 41 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN42" description="illegal access input 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 42 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 42 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN43" description="illegal access input 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 43 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 43 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN44" description="illegal access input 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 44 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 44 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN45" description="illegal access input 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 45 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 45 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN46" description="illegal access input 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 46 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 46 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN47" description="illegal access input 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 47 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 47 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN48" description="illegal access input 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 48 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 48 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN49" description="illegal access input 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 49 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 49 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN50" description="illegal access input 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 50 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 50 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN51" description="illegal access input 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 51 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 51 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN52" description="illegal access input 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 52 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 52 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN53" description="illegal access input 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 53 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 53 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN54" description="illegal access input 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 54 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 54 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN55" description="illegal access input 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 55 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 55 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN56" description="illegal access input 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 56 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 56 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN57" description="illegal access input 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 57 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 57 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN58" description="illegal access input 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 58 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 58 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN59" description="illegal access input 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 59 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 59 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN60" description="illegal access input 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 60 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 60 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN61" description="illegal access input 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 61 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 61 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN62" description="illegal access input 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 62 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 62 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN63" description="illegal access input 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 63 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 63 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR2" description="IAC ILAC input status register 2" start="+0x374" size="4" reset_value="0x77DFF03B" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN64" description="illegal access input 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 64 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 64 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN65" description="illegal access input 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 65 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 65 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN66" description="illegal access input 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 66 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 66 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN67" description="illegal access input 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 67 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 67 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN68" description="illegal access input 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 68 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 68 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN69" description="illegal access input 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 69 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 69 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN70" description="illegal access input 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 70 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 70 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN71" description="illegal access input 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 71 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 71 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN72" description="illegal access input 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 72 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 72 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN73" description="illegal access input 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 73 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 73 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN74" description="illegal access input 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 74 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 74 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN75" description="illegal access input 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 75 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 75 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN76" description="illegal access input 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 76 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 76 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN77" description="illegal access input 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 77 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 77 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN78" description="illegal access input 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 78 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 78 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN79" description="illegal access input 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 79 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 79 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN80" description="illegal access input 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 80 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 80 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN81" description="illegal access input 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 81 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 81 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN82" description="illegal access input 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 82 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 82 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN83" description="illegal access input 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 83 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 83 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN84" description="illegal access input 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 84 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 84 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN85" description="illegal access input 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 85 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 85 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN86" description="illegal access input 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 86 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 86 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN87" description="illegal access input 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 87 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 87 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN88" description="illegal access input 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 88 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 88 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN89" description="illegal access input 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 89 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 89 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN90" description="illegal access input 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 90 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 90 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN91" description="illegal access input 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 91 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 91 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN92" description="illegal access input 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 92 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 92 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN93" description="illegal access input 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 93 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 93 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN94" description="illegal access input 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 94 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 94 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN95" description="illegal access input 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 95 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 95 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR3" description="IAC ILAC input status register 3" start="+0x378" size="4" reset_value="0x000005FF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN96" description="illegal access input 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 96 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 96 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN97" description="illegal access input 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 97 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 97 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN98" description="illegal access input 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 98 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 98 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN99" description="illegal access input 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 99 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 99 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN100" description="illegal access input 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 100 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 100 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN101" description="illegal access input 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 101 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 101 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN102" description="illegal access input 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 102 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 102 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN103" description="illegal access input 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 103 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 103 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN104" description="illegal access input 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 104 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 104 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN105" description="illegal access input 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 105 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 105 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN106" description="illegal access input 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 106 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 106 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN107" description="illegal access input 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 107 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 107 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN108" description="illegal access input 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 108 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 108 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN109" description="illegal access input 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 109 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 109 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN110" description="illegal access input 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 110 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 110 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN111" description="illegal access input 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 111 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 111 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN112" description="illegal access input 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 112 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 112 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN113" description="illegal access input 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 113 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 113 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN114" description="illegal access input 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 114 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 114 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN115" description="illegal access input 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 115 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 115 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN116" description="illegal access input 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 116 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 116 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN117" description="illegal access input 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 117 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 117 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN118" description="illegal access input 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 118 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 118 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN119" description="illegal access input 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 119 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 119 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN120" description="illegal access input 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 120 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 120 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN121" description="illegal access input 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 121 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 121 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN122" description="illegal access input 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 122 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 122 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN123" description="illegal access input 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 123 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 123 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN124" description="illegal access input 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 124 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 124 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN125" description="illegal access input 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 125 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 125 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN126" description="illegal access input 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 126 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 126 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN127" description="illegal access input 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 127 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 127 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR4" description="IAC ILAC input status register 4" start="+0x37C" size="4" reset_value="0x7BEFFFEF" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN128" description="illegal access input 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 128 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 128 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN129" description="illegal access input 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 129 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 129 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN130" description="illegal access input 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 130 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 130 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN131" description="illegal access input 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 131 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 131 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN132" description="illegal access input 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 132 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 132 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN133" description="illegal access input 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 133 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 133 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN134" description="illegal access input 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 134 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 134 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN135" description="illegal access input 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 135 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 135 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN136" description="illegal access input 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 136 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 136 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN137" description="illegal access input 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 137 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 137 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN138" description="illegal access input 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 138 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 138 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN139" description="illegal access input 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 139 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 139 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN140" description="illegal access input 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 140 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 140 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN141" description="illegal access input 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 141 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 141 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN142" description="illegal access input 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 142 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 142 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN143" description="illegal access input 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 143 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 143 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN144" description="illegal access input 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 144 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 144 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN145" description="illegal access input 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 145 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 145 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN146" description="illegal access input 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 146 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 146 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN147" description="illegal access input 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 147 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 147 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN148" description="illegal access input 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 148 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 148 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN149" description="illegal access input 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 149 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 149 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN150" description="illegal access input 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 150 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 150 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN151" description="illegal access input 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 151 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 151 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN152" description="illegal access input 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 152 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 152 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN153" description="illegal access input 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 153 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 153 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN154" description="illegal access input 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 154 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 154 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN155" description="illegal access input 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 155 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 155 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN156" description="illegal access input 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 156 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 156 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN157" description="illegal access input 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 157 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 157 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN158" description="illegal access input 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 158 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 158 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN159" description="illegal access input 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 159 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 159 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IAC_IISR5" description="IAC ILAC input status register 5" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ILACIN128" description="illegal access input 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 128 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 128 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN129" description="illegal access input 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 129 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 129 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN130" description="illegal access input 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 130 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 130 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN131" description="illegal access input 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 131 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 131 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN132" description="illegal access input 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 132 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 132 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN133" description="illegal access input 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 133 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 133 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN134" description="illegal access input 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 134 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 134 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN135" description="illegal access input 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 135 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 135 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN136" description="illegal access input 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 136 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 136 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN137" description="illegal access input 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 137 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 137 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN138" description="illegal access input 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 138 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 138 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN139" description="illegal access input 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 139 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 139 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN140" description="illegal access input 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 140 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 140 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN141" description="illegal access input 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 141 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 141 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN142" description="illegal access input 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 142 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 142 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN143" description="illegal access input 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 143 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 143 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN144" description="illegal access input 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 144 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 144 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN145" description="illegal access input 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 145 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 145 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN146" description="illegal access input 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 146 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 146 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN147" description="illegal access input 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 147 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 147 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN148" description="illegal access input 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 148 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 148 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN149" description="illegal access input 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 149 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 149 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN150" description="illegal access input 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 150 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 150 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN151" description="illegal access input 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 151 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 151 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN152" description="illegal access input 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 152 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 152 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN153" description="illegal access input 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 153 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 153 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN154" description="illegal access input 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 154 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 154 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN155" description="illegal access input 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 155 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 155 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN156" description="illegal access input 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 156 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 156 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN157" description="illegal access input 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 157 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 157 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN158" description="illegal access input 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 158 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 158 to IAC present" start="0x1" />
+      </BitField>
+      <BitField name="ILACIN159" description="illegal access input 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ILAC input 159 to IAC not present" start="0x0" />
+        <Enum name="B_0x1" description="ILAC input 159 to IAC present" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ICACHE" description="Texture cache" start="0x48035000">
+    <Register name="ICACHE_CR" description="ICACHE control register" start="+0x000" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache disabled" start="0x0" />
+        <Enum name="B_0x1" description="cache enabled" start="0x1" />
+      </BitField>
+      <BitField name="CACHEINV" description="cache invalidation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="invalidate entire cache (all cache lines valid bit = 0)" start="0x1" />
+      </BitField>
+      <BitField name="WAYSEL" description="cache associativity mode selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="direct mapped cache (1-way cache)" start="0x0" />
+        <Enum name="B_0x1" description="n-way set associative cache (reset value)" start="0x1" />
+      </BitField>
+      <BitField name="HITMEN" description="hit monitor enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="MISSMEN" description="miss monitor enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="HITMRST" description="hit monitor reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="MISSMRST" description="miss monitor reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache miss monitor" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_SR" description="ICACHE status register" start="+0x004" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSYF" description="busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHEINV operation" start="0x0" />
+        <Enum name="B_0x1" description="cache executing a full invalidate CACHEINV operation" start="0x1" />
+      </BitField>
+      <BitField name="BSYENDF" description="busy end flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy" start="0x0" />
+        <Enum name="B_0x1" description="full invalidate CACHEINV operation finished" start="0x1" />
+      </BitField>
+      <BitField name="ERRF" description="cache error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no error" start="0x0" />
+        <Enum name="B_0x1" description="an error occurred during the operation (cacheable write)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_IER" description="ICACHE interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSYENDIE" description="interrupt enable on busy end" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on busy end" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on busy end" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="interrupt enable on cache error" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on error" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on error" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_FCR" description="ICACHE flag clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CBSYENDF" description="clear busy end flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears BSYENDF flag in ICACHE_SR." start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="clear cache error flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears ERRF flag in ICACHE_SR" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_HMONR" description="ICACHE hit monitor register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HITMON" description="cache hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ICACHE_MMONR" description="ICACHE miss monitor register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MISSMON" description="cache miss monitor counter" start="0" size="16" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ICACHE_S" description="Texture cache" start="0x58035000">
+    <Register name="ICACHE_CR" description="ICACHE control register" start="+0x000" size="4" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache disabled" start="0x0" />
+        <Enum name="B_0x1" description="cache enabled" start="0x1" />
+      </BitField>
+      <BitField name="CACHEINV" description="cache invalidation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="invalidate entire cache (all cache lines valid bit = 0)" start="0x1" />
+      </BitField>
+      <BitField name="WAYSEL" description="cache associativity mode selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="direct mapped cache (1-way cache)" start="0x0" />
+        <Enum name="B_0x1" description="n-way set associative cache (reset value)" start="0x1" />
+      </BitField>
+      <BitField name="HITMEN" description="hit monitor enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache hit monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache hit monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="MISSMEN" description="miss monitor enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="cache miss monitor switched off. Stopping the monitor does not reset it." start="0x0" />
+        <Enum name="B_0x1" description="cache miss monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="HITMRST" description="hit monitor reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache hit monitor" start="0x1" />
+      </BitField>
+      <BitField name="MISSMRST" description="miss monitor reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="reset cache miss monitor" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_SR" description="ICACHE status register" start="+0x004" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BUSYF" description="busy flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache not busy on a CACHEINV operation" start="0x0" />
+        <Enum name="B_0x1" description="cache executing a full invalidate CACHEINV operation" start="0x1" />
+      </BitField>
+      <BitField name="BSYENDF" description="busy end flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="cache busy" start="0x0" />
+        <Enum name="B_0x1" description="full invalidate CACHEINV operation finished" start="0x1" />
+      </BitField>
+      <BitField name="ERRF" description="cache error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no error" start="0x0" />
+        <Enum name="B_0x1" description="an error occurred during the operation (cacheable write)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_IER" description="ICACHE interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSYENDIE" description="interrupt enable on busy end" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on busy end" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on busy end" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="interrupt enable on cache error" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled on error" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled on error" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_FCR" description="ICACHE flag clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CBSYENDF" description="clear busy end flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears BSYENDF flag in ICACHE_SR." start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="clear cache error flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears ERRF flag in ICACHE_SR" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ICACHE_HMONR" description="ICACHE hit monitor register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HITMON" description="cache hit monitor counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ICACHE_MMONR" description="ICACHE miss monitor register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MISSMON" description="cache miss monitor counter" start="0" size="16" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IWDG" description="Independent watchdog" start="0x46004800">
+    <Register name="IWDG_KR" description="IWDG key register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Key value (write only, read 0x0000)" start="0" size="16" access="WriteOnly" />
+    </Register>
+    <Register name="IWDG_PR" description="IWDG prescaler register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="Prescaler divider " start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="divider / 4" start="0x0" />
+        <Enum name="B_0x1" description="divider / 8" start="0x1" />
+        <Enum name="B_0x2" description="divider / 16" start="0x2" />
+        <Enum name="B_0x3" description="divider / 32" start="0x3" />
+        <Enum name="B_0x4" description="divider / 64" start="0x4" />
+        <Enum name="B_0x5" description="divider / 128" start="0x5" />
+        <Enum name="B_0x6" description="divider / 256" start="0x6" />
+        <Enum name="B_0x7" description="divider / 512" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="IWDG_RLR" description="IWDG reload register" start="+0x08" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="RL" description="Watchdog counter reload value " start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="IWDG_SR" description="IWDG status register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVU" description="Watchdog prescaler value update" start="0" size="1" access="ReadOnly" />
+      <BitField name="RVU" description="Watchdog counter reload value update" start="1" size="1" access="ReadOnly" />
+      <BitField name="WVU" description="Watchdog counter window value update" start="2" size="1" access="ReadOnly" />
+      <BitField name="EWU" description="Watchdog interrupt comparator value update " start="3" size="1" access="ReadOnly" />
+      <BitField name="ONF" description="Watchdog enable status bit" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The IWDG is not activated" start="0x0" />
+        <Enum name="B_0x1" description="The IWDG is activated and needs to be refreshed regularly by the application" start="0x1" />
+      </BitField>
+      <BitField name="EWIF" description="Watchdog early interrupt flag" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="IWDG_WINR" description="IWDG window register" start="+0x10" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WIN" description="Watchdog counter window value " start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="IWDG_EWCR" description="IWDG early wake-up interrupt register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIT" description="Watchdog counter window value " start="0" size="12" access="Read/Write" />
+      <BitField name="EWIE" description="Watchdog early interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The early interrupt interface is disabled." start="0x0" />
+        <Enum name="B_0x1" description="The early interrupt interface is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IWDG_ICR" description="IWDG interrupt clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIC" description="Watchdog early interrupt acknowledge " start="15" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IWDG_S" description="Independent watchdog" start="0x56004800">
+    <Register name="IWDG_KR" description="IWDG key register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Key value (write only, read 0x0000)" start="0" size="16" access="WriteOnly" />
+    </Register>
+    <Register name="IWDG_PR" description="IWDG prescaler register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="Prescaler divider " start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="divider / 4" start="0x0" />
+        <Enum name="B_0x1" description="divider / 8" start="0x1" />
+        <Enum name="B_0x2" description="divider / 16" start="0x2" />
+        <Enum name="B_0x3" description="divider / 32" start="0x3" />
+        <Enum name="B_0x4" description="divider / 64" start="0x4" />
+        <Enum name="B_0x5" description="divider / 128" start="0x5" />
+        <Enum name="B_0x6" description="divider / 256" start="0x6" />
+        <Enum name="B_0x7" description="divider / 512" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="IWDG_RLR" description="IWDG reload register" start="+0x08" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="RL" description="Watchdog counter reload value " start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="IWDG_SR" description="IWDG status register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVU" description="Watchdog prescaler value update" start="0" size="1" access="ReadOnly" />
+      <BitField name="RVU" description="Watchdog counter reload value update" start="1" size="1" access="ReadOnly" />
+      <BitField name="WVU" description="Watchdog counter window value update" start="2" size="1" access="ReadOnly" />
+      <BitField name="EWU" description="Watchdog interrupt comparator value update " start="3" size="1" access="ReadOnly" />
+      <BitField name="ONF" description="Watchdog enable status bit" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The IWDG is not activated" start="0x0" />
+        <Enum name="B_0x1" description="The IWDG is activated and needs to be refreshed regularly by the application" start="0x1" />
+      </BitField>
+      <BitField name="EWIF" description="Watchdog early interrupt flag" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="IWDG_WINR" description="IWDG window register" start="+0x10" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WIN" description="Watchdog counter window value " start="0" size="12" access="Read/Write" />
+    </Register>
+    <Register name="IWDG_EWCR" description="IWDG early wake-up interrupt register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIT" description="Watchdog counter window value " start="0" size="12" access="Read/Write" />
+      <BitField name="EWIE" description="Watchdog early interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The early interrupt interface is disabled." start="0x0" />
+        <Enum name="B_0x1" description="The early interrupt interface is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="IWDG_ICR" description="IWDG interrupt clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIC" description="Watchdog early interrupt acknowledge " start="15" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1" description="Inter-integrated circuit" start="0x40005400">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1_S" description="Inter-integrated circuit" start="0x50005400">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C2" description="Inter-integrated circuit" start="0x40005800">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C2_S" description="Inter-integrated circuit" start="0x50005800">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C3" description="Inter-integrated circuit" start="0x40005C00">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C3_S" description="Inter-integrated circuit" start="0x50005C00">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C4" description="Inter-integrated circuit" start="0x46001C00">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C4_S" description="Inter-integrated circuit" start="0x56001C00">
+    <Register name="I2C_CR1" description="I2C control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
+        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
+      </BitField>
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer Complete interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="Error interrupts enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
+        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
+      </BitField>
+      <BitField name="DNF" description="Digital noise filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tless thansub&gt;I2CCLKless than/sub&gt;" start="0x1" />
+        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tless thansub&gt;I2CCLKless than/sub&gt;" start="0xF" />
+      </BitField>
+      <BitField name="ANFOFF" description="Analog noise filter OFF" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
+      </BitField>
+      <BitField name="SBC" description="Slave byte control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
+      </BitField>
+      <BitField name="NOSTRETCH" description="Clock stretching disable " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
+        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
+      </BitField>
+      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBHEN" description="SMBus host address enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="SMBDEN" description="SMBus device default address enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
+      </BitField>
+      <BitField name="ALERTEN" description="SMBus alert enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK)." start="0x0" />
+        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
+      </BitField>
+      <BitField name="PECEN" description="PEC enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMP" description="Fast-mode Plus 20 mA drive enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="20 mA I/O drive disabled" start="0x0" />
+        <Enum name="B_0x1" description="20 mA I/O drive enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADDRACLR" description="Address match flag (ADDR) automatic clear" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADDR flag is set by hardware and cleared by software by setting ADDRCF bit." start="0x0" />
+        <Enum name="B_0x1" description="ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+      <BitField name="STOPFACLR" description="STOP detection flag (STOPF) automatic clear" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="STOPF flag is set by hardware and cleared by software by setting STOPCF bit." start="0x0" />
+        <Enum name="B_0x1" description="STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_CR2" description="I2C control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD" description="Slave address (master mode)" start="0" size="10" access="Read/Write" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
+        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
+      </BitField>
+      <BitField name="ADD10" description="10-bit addressing mode (master mode)" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
+        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
+      </BitField>
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
+        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
+      </BitField>
+      <BitField name="START" description="Start generation" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Start generation." start="0x0" />
+        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="Stop generation (master mode)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
+        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="NACK generation (slave mode)" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
+        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
+      </BitField>
+      <BitField name="NBYTES" description="Number of bytes" start="16" size="8" access="Read/Write" />
+      <BitField name="RELOAD" description="NBYTES reload mode" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
+        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
+      </BitField>
+      <BitField name="AUTOEND" description="Automatic end mode (master mode)" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
+        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
+      </BitField>
+      <BitField name="PECBYTE" description="Packet error checking byte" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
+        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR1" description="I2C own address 1 register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface own slave address" start="0" size="10" access="Read/Write" />
+      <BitField name="OA1MODE" description="Own address 1 10-bit mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
+      </BitField>
+      <BitField name="OA1EN" description="Own address 1 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_OAR2" description="I2C own address 2 register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address" start="1" size="7" access="Read/Write" />
+      <BitField name="OA2MSK" description="Own address 2 masks" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No mask" start="0x0" />
+        <Enum name="B_0x1" description="OA2[1] is masked and don't care. Only OA2[7:2] are compared." start="0x1" />
+        <Enum name="B_0x2" description="OA2[2:1] are masked and don't care. Only OA2[7:3] are compared." start="0x2" />
+        <Enum name="B_0x3" description="OA2[3:1] are masked and don't care. Only OA2[7:4] are compared." start="0x3" />
+        <Enum name="B_0x4" description="OA2[4:1] are masked and don't care. Only OA2[7:5] are compared." start="0x4" />
+        <Enum name="B_0x5" description="OA2[5:1] are masked and don't care. Only OA2[7:6] are compared." start="0x5" />
+        <Enum name="B_0x6" description="OA2[6:1] are masked and don't care. Only OA2[7] is compared." start="0x6" />
+        <Enum name="B_0x7" description="OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
+      </BitField>
+      <BitField name="OA2EN" description="Own address 2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
+        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_TIMINGR" description="I2C timing register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode)" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH" description="SCL high period (master mode)" start="8" size="8" access="Read/Write" />
+      <BitField name="SDADEL" description="Data hold time" start="16" size="4" access="Read/Write" />
+      <BitField name="SCLDEL" description="Data setup time" start="20" size="4" access="Read/Write" />
+      <BitField name="PRESC" description="Timing prescaler" start="28" size="4" access="Read/Write" />
+    </Register>
+    <Register name="I2C_TIMEOUTR" description="I2C timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A" start="0" size="12" access="Read/Write" />
+      <BitField name="TIDLE" description="Idle clock timeout detection " start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
+        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
+      </BitField>
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tless thansub&gt;TIMEOUTless than/sub&gt; (TIDLE=0) or high for more than tless thansub&gt;IDLE less than/sub&gt;(TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+      <BitField name="TIMEOUTB" description="Bus timeout B" start="16" size="12" access="Read/Write" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tless thansub&gt;LOW:EXT less than/sub&gt;is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I2C_ISR" description="I2C interrupt and status register" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) " start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) " start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers)" start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode)" start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag " start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode)" start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload" start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error " start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost " start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode)" start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception" start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tless thansub&gt;LOWless than/sub&gt; detection flag" start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert " start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy" start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
+        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
+      </BitField>
+      <BitField name="ADDCODE" description="Address match code (Slave mode) " start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_ICR" description="I2C interrupt clear register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear " start="3" size="1" access="WriteOnly" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="STOPCF" description="STOP detection flag clear " start="5" size="1" access="WriteOnly" />
+      <BitField name="BERRCF" description="Bus error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="ARLOCF" description="Arbitration lost flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="PECCF" description="PEC Error flag clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="ALERTCF" description="Alert flag clear" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="I2C_PECR" description="I2C PEC register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_RXDR" description="I2C receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I2C_TXDR" description="I2C transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data" start="0" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I3C1" description="Improved inter-integrated circuit" start="0x40006000">
+    <Register name="I3C_CR" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target)" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer" start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="RNW" description="Read / non-write message (when I3C acts as controller)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="write message" start="0x0" />
+        <Enum name="B_0x1" description="read message" start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="7-bit I3C dynamic / Iless thansup&gt;2less than/sup&gt;C static target address (when I3C acts as controller)" start="17" size="7" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (whatever I3C acts as controller/target)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="SCL clock is forced to stop until a next control word is executed" start="0x0" />
+        <Enum name="B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="header message" start="0x1" />
+        <Enum name="B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="private message (refer to Figure 801)" start="0x2" />
+        <Enum name="B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="direct message (second part of an I3C SDR direct CCC command) (refer to Figure 794)" start="0x3" />
+        <Enum name="B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="legacy Iless thansup&gt;2less than/sup&gt;C message (refer to Figure 803)" start="0x4" />
+        <Enum name="B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET" description="hot-join request (W) (refer to Figure 805)" start="0x8" />
+        <Enum name="B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET" description="controller-role request (W) (refer to Figure 806)" start="0x9" />
+        <Enum name="B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET" description="IBI (in-band interrupt) request (R) (refer to Figure 804)" start="0xA" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when the I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="this message from controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CR_alternate" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer." start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="CCC" description="8-bit CCC code (when I3C acts as controller)" start="16" size="8" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (when I3C acts as controller)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="broadcast/direct CCC command (refer to Table 621, Figure 794, Figure 795, Figure 796)" start="0x6" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="the message from the controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CFGR" description="I3C configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="I3C enable (whatever I3C acts as controller/target)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C is disabled" start="0x0" />
+        <Enum name="B_0x1" description="I3C is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRINIT" description="Initial controller/target role" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="target role" start="0x0" />
+        <Enum name="B_0x1" description="controller role" start="0x1" />
+      </BitField>
+      <BitField name="NOARBH" description="No arbitrable header after a start (when I3C acts as a controller)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup&gt;2less than/sup&gt;C message or an I3C SDR private read/write message (default)." start="0x0" />
+        <Enum name="B_0x1" description="No arbitrable header" start="0x1" />
+      </BitField>
+      <BitField name="RSTPTRN" description="HDR reset pattern enable (when I3C acts as a controller)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="standard stop emitted at the end of a frame" start="0x0" />
+        <Enum name="B_0x1" description="HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command" start="0x1" />
+      </BitField>
+      <BitField name="EXITPTRN" description="HDR exit pattern enable (when I3C acts as a controller)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). This is used to send the header, to test ownership of the bus when there is a suspicion of a problem after controller-role hand-off (new controller did not assert its controller-role by accessing the previous one in less than the delay defined by the activity state)." start="0x0" />
+        <Enum name="B_0x1" description="HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). This is used on a controller error detection and escalation handling, in case of a not responding target to a private message or a direct read CCC." start="0x1" />
+      </BitField>
+      <BitField name="HKSDAEN" description="High-keeper enable on SDA line (when I3C acts as a controller)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="High-keeper is disabled" start="0x0" />
+        <Enum name="B_0x1" description="High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up." start="0x1" />
+      </BitField>
+      <BitField name="HJACK" description="Hot-join request acknowledge (when I3C acts as a controller)" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request is not acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request is acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="RX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for RX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXFLUSH" description="RX-FIFO flush (whatever I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXTHRES" description="RX-FIFO threshold (whatever I3C acts as controller/target)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word/4-bytes threshold" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="TX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for TX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXFLUSH" description="TX-FIFO flush (whatever I3C acts as controller/target)" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXTHRES" description="TX-FIFO threshold (whatever I3C acts as controller/target)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word / 4-byte threshold" start="0x1" />
+      </BitField>
+      <BitField name="SDMAEN" description="S-FIFO DMA request enable (when I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for reading status register I3C_SR" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for reading status register I3C_SR" start="0x1" />
+      </BitField>
+      <BitField name="SFLUSH" description="S-FIFO flush (when I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush S-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="SMODE" description="S-FIFO enable / status receive mode (when I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="S-FIFO is disabled" start="0x0" />
+        <Enum name="B_0x1" description="S-FIFO is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TMODE" description="Transmit mode (when I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer." start="0x0" />
+        <Enum name="B_0x1" description="C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. Refer to Section 64.10.2 for more details." start="0x1" />
+      </BitField>
+      <BitField name="CDMAEN" description="C-FIFO DMA request enable (when I3C acts as controller)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for C-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CFLUSH" description="C-FIFO flush (when I3C acts as controller)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TSFSET" description="Frame transfer set (software trigger) (when I3C acts as controller)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RDR" description="I3C receive data byte register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data on I3C bus." start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_RDWR" description="I3C receive data word register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data (earliest byte on I3C bus)." start="0" size="8" access="ReadOnly" />
+      <BitField name="RDB1" description="8-bit received data (next byte after RDB0 on I3C bus)." start="8" size="8" access="ReadOnly" />
+      <BitField name="RDB2" description="8-bit received data (next byte after RDB1 on I3C bus)." start="16" size="8" access="ReadOnly" />
+      <BitField name="RDB3" description="8-bit received data (latest byte on I3C bus)." start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_TDR" description="I3C transmit data byte register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit data to transmit on I3C bus." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_TDWR" description="I3C transmit data word register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit transmit data (earliest byte on I3C bus)" start="0" size="8" access="WriteOnly" />
+      <BitField name="TDB1" description="8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." start="8" size="8" access="WriteOnly" />
+      <BitField name="TDB2" description="8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." start="16" size="8" access="WriteOnly" />
+      <BitField name="TDB3" description="8-bit transmit data (latest byte on I3C bus)." start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_IBIDR" description="I3C IBI payload data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIDB0" description="8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte)." start="0" size="8" access="Read/Write" />
+      <BitField name="IBIDB1" description="8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." start="8" size="8" access="Read/Write" />
+      <BitField name="IBIDB2" description="8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." start="16" size="8" access="Read/Write" />
+      <BitField name="IBIDB3" description="8-bit IBI payload data (latest byte on I3C bus)." start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TGTTDR" description="I3C target transmit configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TGTTDCNT" description="Transmit data counter, in bytes (when I3C is configured as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="PRELOAD" description="Preload of the TX-FIFO (when I3C is configured as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no TX-FIFO preload" start="0x0" />
+        <Enum name="B_0x1" description="TX-FIFO preload" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_SR" description="I3C status register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XDCNT" description="Data counter " start="0" size="16" access="ReadOnly" />
+      <BitField name="ABT" description="A private read message is ended prematurely by the target (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no early completion from the target" start="0x0" />
+        <Enum name="B_0x1" description="early completion from the target" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Message direction" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write" start="0x0" />
+        <Enum name="B_0x1" description="read" start="0x1" />
+      </BitField>
+      <BitField name="MID" description="Message identifier/counter of a given frame (when the I3C acts as controller)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_SER" description="I3C status error register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CODERR" description="Protocol error code/type" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="CE0 error (transaction after sending CCC):" start="0x0" />
+        <Enum name="B_0x1" description="CE1 error (monitoring error):" start="0x1" />
+        <Enum name="B_0x2" description="CE2 error (no response to broadcast address):" start="0x2" />
+        <Enum name="B_0x3" description="CE3 error (failed controller-role hand-off):" start="0x3" />
+        <Enum name="B_0x8" description="TE0 error (invalid broadcast address 0b111_1110 + W):" start="0x8" />
+        <Enum name="B_0x9" description="TE1 error (CCC code):" start="0x9" />
+        <Enum name="B_0xA" description="TE2 error (write data):" start="0xA" />
+        <Enum name="B_0xB" description="TE3 error (assigned address during dynamic address arbitration):" start="0xB" />
+        <Enum name="B_0xC" description="TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration):" start="0xC" />
+        <Enum name="B_0xD" description="TE5 error (transaction after detecting CCC):" start="0xD" />
+        <Enum name="B_0xE" description="TE6 error (monitoring error):" start="0xE" />
+      </BitField>
+      <BitField name="PERR" description="Protocol error" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="SCL stall error (when the I3C acts as target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB)" start="0x1" />
+      </BitField>
+      <BitField name="DOVR" description="RX-FIFO overrun or TX-FIFO underrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected either:" start="0x1" />
+      </BitField>
+      <BitField name="COVR" description="C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected either:" start="0x1" />
+      </BitField>
+      <BitField name="ANACK" description="Address not acknowledged (when the I3C is configured as controller)" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that the static/dynamic address was not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DNACK" description="Data not acknowledged (when the I3C acts as controller)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that a data byte is not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DERR" description="Data error (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RMR" description="I3C received message register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIRDCNT" description="IBI received payload data count (when the I3C is configured as controller)" start="0" size="3" access="ReadOnly" />
+      <BitField name="RCODE" description="Received CCC code (when the I3C is configured as target)" start="8" size="8" access="ReadOnly" />
+      <BitField name="RADD" description="Received target address (when the I3C is configured as controller)" start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_EVR" description="I3C event register" start="+0x050" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEF" description="C-FIFO empty flag (whatever the I3C acts as controller)" start="0" size="1" access="ReadOnly" />
+      <BitField name="TXFEF" description="TX-FIFO empty flag (whatever the I3C acts as controller/target)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFNFF" description="C-FIFO not full flag (when the I3C acts as controller)" start="2" size="1" access="ReadOnly" />
+      <BitField name="SFNEF" description="S-FIFO not empty flag (when the I3C acts as controller)" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXFNFF" description="TX-FIFO not full flag (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXFNEF" description="RX-FIFO not empty flag (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXLASTF" description="Last written data byte/word flag (whatever the I3C acts as controller/target)" start="6" size="1" access="ReadOnly" />
+      <BitField name="RXLASTF" description="Last read data byte/word flag (when the I3C acts as controller)" start="7" size="1" access="ReadOnly" />
+      <BitField name="FCF" description="Frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly" />
+      <BitField name="RXTGTENDF" description="Target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="ReadOnly" />
+      <BitField name="ERRF" description="Flag (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly" />
+      <BitField name="IBIF" description="IBI flag (when the I3C acts as controller)" start="15" size="1" access="ReadOnly" />
+      <BitField name="IBIENDF" description="IBI end flag (when the I3C acts as target)" start="16" size="1" access="ReadOnly" />
+      <BitField name="CRF" description="Controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="ReadOnly" />
+      <BitField name="CRUPDF" description="Controller-role update flag (when the I3C acts as target)" start="18" size="1" access="ReadOnly" />
+      <BitField name="HJF" description="Hot-join flag (when the I3C acts as controller)" start="19" size="1" access="ReadOnly" />
+      <BitField name="WKPF" description="Wake-up/missed start flag (when the I3C acts as target)" start="21" size="1" access="ReadOnly" />
+      <BitField name="GETF" description="Get flag (when the I3C acts as target)" start="22" size="1" access="ReadOnly" />
+      <BitField name="STAF" description="Get status flag (when the I3C acts as target)" start="23" size="1" access="ReadOnly" />
+      <BitField name="DAUPDF" description="Dynamic address update flag (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+      <BitField name="MWLUPDF" description="Maximum write length update flag (when the I3C acts as target)" start="25" size="1" access="ReadOnly" />
+      <BitField name="MRLUPDF" description="Maximum read length update flag (when the I3C acts as target)" start="26" size="1" access="ReadOnly" />
+      <BitField name="RSTF" description="Reset pattern flag (when the I3C acts as target)" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASUPDF" description="Activity state update flag (when the I3C acts as target)" start="28" size="1" access="ReadOnly" />
+      <BitField name="INTUPDF" description="Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" start="29" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="DEFTGTS flag (when the I3C acts as target)" start="30" size="1" access="ReadOnly" />
+      <BitField name="GRPF" description="Group addressing flag (when the I3C acts as target)" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_IER" description="I3C interrupt enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFNFIE" description="C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFNEIE" description="S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FCIE" description="frame complete interrupt enable (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXTGTENDIE" description="target-initiated read end interrupt enable (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="error interrupt enable (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIIE" description="IBI request interrupt enable (when the I3C acts as controller)" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIENDIE" description="IBI end interrupt enable (when the I3C acts as target)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRIE" description="Controller-role request interrupt enable (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRUPDIE" description="Controller-role update interrupt enable (when the I3C acts as target)" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJIE" description="Hot-join interrupt enable (when the I3C acts as controller)" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WKPIE" description="Wake-up interrupt enable (when the I3C acts as target)" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GETIE" description="GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="STAIE" description="format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAUPDIE" description="ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MWLUPDIE" description="SETMWL CCC interrupt enable (when the I3C acts as target)" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRLUPDIE" description="SETMRL CCC interrupt enable (when the I3C acts as target)" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RSTIE" description="reset pattern interrupt enable (when the I3C acts as target)" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ASUPDIE" description="ENTASx CCC interrupt enable (when the I3C acts as target)" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="INTUPDIE" description="ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="DEFTGTS CCC interrupt enable (when the I3C acts as target)" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GRPIE" description="DEFGRPA CCC interrupt enable (when the I3C acts as target)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CEVR" description="I3C clear event register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFCF" description="Clear frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear FCF" start="0x1" />
+      </BitField>
+      <BitField name="CRXTGTENDF" description="Clear target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RXTGTENDF" start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="Clear error flag (whatever the I3C acts as controller/target)" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ERRF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIF" description="Clear IBI request flag (when the I3C acts as controller)" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIENDF" description="Clear IBI end flag (when the I3C acts as target)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIENDF" start="0x1" />
+      </BitField>
+      <BitField name="CCRF" description="Clear controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRF" start="0x1" />
+      </BitField>
+      <BitField name="CCRUPDF" description="Clear controller-role update flag (when the I3C acts as target)" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CHJF" description="Clear hot-join flag (when the I3C acts as controller)" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear HJF" start="0x1" />
+      </BitField>
+      <BitField name="CWKPF" description="Clear wake-up flag (when the I3C acts as target)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear WKPF" start="0x1" />
+      </BitField>
+      <BitField name="CGETF" description="Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GETF" start="0x1" />
+      </BitField>
+      <BitField name="CSTAF" description="Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear STAF" start="0x1" />
+      </BitField>
+      <BitField name="CDAUPDF" description="Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DAUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMWLUPDF" description="Clear SETMWL CCC flag (when the I3C acts as target)" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MWLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMRLUPDF" description="Clear SETMRL CCC flag (when the I3C acts as target)" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MRLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CRSTF" description="Clear reset pattern flag (when the I3C acts as target)" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RSTF" start="0x1" />
+      </BitField>
+      <BitField name="CASUPDF" description="Clear ENTASx CCC flag (when the I3C acts as target)" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ASUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CINTUPDF" description="Clear ENEC/DISEC CCC flag (when the I3C acts as target)" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CINTUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CDEFF" description="Clear DEFTGTS CCC flag (when the I3C acts as target)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DEFF" start="0x1" />
+      </BitField>
+      <BitField name="CGRPF" description="Clear DEFGRPA CCC flag (when the I3C acts as target)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GRPF" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR0" description="I3C own device characteristics register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAVAL" description="Dynamic address is valid (when the I3C acts as target)" start="0" size="1" access="Read/Write" />
+      <BitField name="DA" description="7-bit dynamic address" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIEN" description="IBI request enable (when the I3C acts as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IBI request disabled" start="0x0" />
+        <Enum name="B_0x1" description="IBI request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CREN" description="Controller-role request enable (when the I3C acts as target)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="controller-role request disabled" start="0x0" />
+        <Enum name="B_0x1" description="controller-role request enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJEN" description="Hot-join request enable (when the I3C acts as target)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request disabled" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request enabled" start="0x1" />
+      </BitField>
+      <BitField name="AS" description="Activity state (when the I3C acts as target)" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="activity state 0" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3" start="0x3" />
+      </BitField>
+      <BitField name="RSTACT" description="Reset action/level on received reset pattern (when the I3C acts as target)" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset action" start="0x0" />
+        <Enum name="B_0x1" description="first level of reset: the application software must either:" start="0x1" />
+        <Enum name="B_0x2" description="second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 21.3: RCC functional description - Reset) has the same impact as a pin reset (NRST = 0):" start="0x2" />
+        <Enum name="B_0x3" description="no reset action" start="0x3" />
+      </BitField>
+      <BitField name="RSTVAL" description="Reset action is valid (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_DEVR1" description="I3C device 1 characteristics register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR2" description="I3C device 2 characteristics register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR3" description="I3C device 3 characteristics register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR4" description="I3C device 4 characteristics register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXRLR" description="I3C maximum read length register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRL" description="Maximum data read length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="IBIP" description="IBI payload data maximum size, in bytes (when I3C acts as target)" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="null payload data size (only allowed when BCR2 = 0 in the IC3_BCR register)" start="0x0" />
+        <Enum name="B_0x1" description="1 byte (mandatory data byte MDB[7:0]" start="0x1" />
+        <Enum name="B_0x2" description="2 bytes (including first MDB[7:0])" start="0x2" />
+        <Enum name="B_0x3" description="3 bytes (including first MDB[7:0])" start="0x3" />
+        <Enum name="B_0x4" description="4 bytes (including first MDB[7:0])" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXWLR" description="I3C maximum write length register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MWL" description="Maximum data write length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR0" description="I3C timing register 0" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL_PP" description="SCL low duration in I3C push-pull phases, in number of kernel clocks cycles:" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH_I3C" description="SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles:" start="8" size="8" access="Read/Write" />
+      <BitField name="SCLL_OD" description="SCL low duration in open-drain phases, used for legacy Iless thansup&gt;2less than/sup&gt;C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles:" start="16" size="8" access="Read/Write" />
+      <BitField name="SCLH_I2C" description="SCL high duration, used for legacy Iless thansup&gt;2less than/sup&gt;C messages, in number of kernel clocks cycles:" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR1" description="I3C timing register 1" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVAL" description="Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. " start="0" size="8" access="Read/Write" />
+      <BitField name="ASNCR" description="Activity state of the new controller (when I3C acts as active controller)" start="8" size="2" access="Read/Write" />
+      <BitField name="FREE" description="Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" start="16" size="7" access="Read/Write" />
+      <BitField name="SDA_HD" description="SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub&gt;HD_PPless than/sub&gt;):" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR2" description="I3C timing register 2" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STALLT" description="Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup&gt;2less than/sup&gt;C read)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLD" description="Controller clock stall enable on PAR phase of Data" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLC" description="Controller clock stall enable on PAR phase of CCC" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLA" description="Controller clock stall enable on ACK phase" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="Controller clock stall time, in number of kernel clock cycles" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_BCR" description="I3C bus characteristics register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCR0" description="max data speed limitation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no limitation" start="0x0" />
+        <Enum name="B_0x1" description="limitation, as described by I3C_GETMXDSR." start="0x1" />
+      </BitField>
+      <BitField name="BCR2" description="in-band interrupt (IBI) payload" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the accepted IBI" start="0x0" />
+        <Enum name="B_0x1" description="at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes)" start="0x1" />
+      </BitField>
+      <BitField name="BCR6" description="Controller capable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C target (no controller capable)" start="0x0" />
+        <Enum name="B_0x1" description="I3C controller capable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DCR" description="I3C device characteristics register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCR" description="device characteristics ID" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="generic device (for v1.0 devices)" start="0x00" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETCAPR" description="I3C get capability register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPPEND" description="IBI MDB support for pending read notification" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification" start="0x0" />
+        <Enum name="B_0x1" description="this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CRCAPR" description="I3C controller-role capability register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPDHOFF" description="delayed controller-role hand-off" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not needs additional time to process a controller-role hand-off" start="0x0" />
+        <Enum name="B_0x1" description="this I3C needs additional time to process a controller-role hand-off" start="0x1" />
+      </BitField>
+      <BitField name="CAPGRP" description="group management support (when acting as controller)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not support group address capabilities" start="0x0" />
+        <Enum name="B_0x1" description="this I3C supports group address capabilities (when becoming controller)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETMXDSR" description="I3C get capability register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFAS" description="Controller hand-off activity state " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="activity state 0 is the initial activity state of this I3C before and when becoming controller" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1 is the initial activity state of this I3C when becoming controller" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2 is the initial activity state of this I3C when becoming controller" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3 is the initial activity state of this I3C when becoming controller" start="0x3" />
+      </BitField>
+      <BitField name="FMT" description="GETMXDS CCC format" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="format 1 (2 bytes with MaxWr with no defining byte, MaxRd)" start="0x0" />
+        <Enum name="B_0x1" description="format 2: (5 bytes w.ith MaxWr with no defining byte, MaxRd, MaxRdTurn)" start="0x1" />
+        <Enum name="B_0x2" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn)" start="0x2" />
+        <Enum name="B_0x3" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn)" start="0x3" />
+      </BitField>
+      <BitField name="RDTURN" description="programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" start="16" size="8" access="Read/Write" />
+      <BitField name="TSCO" description="clock-to-data turnaround time (tless thansub&gt;SCOless than/sub&gt;)" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;SCOless than/sub&gt; less than or equal to 12 ns" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;SCOless than/sub&gt; &gt; 12 ns (refer to the datasheet for more details)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_EPIDR" description="I3C extended provisioned ID register" start="+0xD4" size="4" reset_value="0x02080000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIPIID" description="4-bit MIPI Instance ID" start="12" size="4" access="Read/Write" />
+      <BitField name="IDTSEL" description="provisioned ID type selector" start="16" size="1" access="ReadOnly" />
+      <BitField name="MIPIMID" description="15-bit MIPI manufacturer ID" start="17" size="15" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I3C1_S" description="Improved inter-integrated circuit" start="0x50006000">
+    <Register name="I3C_CR" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target)" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer" start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="RNW" description="Read / non-write message (when I3C acts as controller)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="write message" start="0x0" />
+        <Enum name="B_0x1" description="read message" start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="7-bit I3C dynamic / Iless thansup&gt;2less than/sup&gt;C static target address (when I3C acts as controller)" start="17" size="7" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (whatever I3C acts as controller/target)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="SCL clock is forced to stop until a next control word is executed" start="0x0" />
+        <Enum name="B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="header message" start="0x1" />
+        <Enum name="B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="private message (refer to Figure 801)" start="0x2" />
+        <Enum name="B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="direct message (second part of an I3C SDR direct CCC command) (refer to Figure 794)" start="0x3" />
+        <Enum name="B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="legacy Iless thansup&gt;2less than/sup&gt;C message (refer to Figure 803)" start="0x4" />
+        <Enum name="B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET" description="hot-join request (W) (refer to Figure 805)" start="0x8" />
+        <Enum name="B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET" description="controller-role request (W) (refer to Figure 806)" start="0x9" />
+        <Enum name="B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET" description="IBI (in-band interrupt) request (R) (refer to Figure 804)" start="0xA" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when the I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="this message from controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CR_alternate" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer." start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="CCC" description="8-bit CCC code (when I3C acts as controller)" start="16" size="8" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (when I3C acts as controller)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="broadcast/direct CCC command (refer to Table 621, Figure 794, Figure 795, Figure 796)" start="0x6" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="the message from the controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CFGR" description="I3C configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="I3C enable (whatever I3C acts as controller/target)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C is disabled" start="0x0" />
+        <Enum name="B_0x1" description="I3C is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRINIT" description="Initial controller/target role" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="target role" start="0x0" />
+        <Enum name="B_0x1" description="controller role" start="0x1" />
+      </BitField>
+      <BitField name="NOARBH" description="No arbitrable header after a start (when I3C acts as a controller)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup&gt;2less than/sup&gt;C message or an I3C SDR private read/write message (default)." start="0x0" />
+        <Enum name="B_0x1" description="No arbitrable header" start="0x1" />
+      </BitField>
+      <BitField name="RSTPTRN" description="HDR reset pattern enable (when I3C acts as a controller)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="standard stop emitted at the end of a frame" start="0x0" />
+        <Enum name="B_0x1" description="HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command" start="0x1" />
+      </BitField>
+      <BitField name="EXITPTRN" description="HDR exit pattern enable (when I3C acts as a controller)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). This is used to send the header, to test ownership of the bus when there is a suspicion of a problem after controller-role hand-off (new controller did not assert its controller-role by accessing the previous one in less than the delay defined by the activity state)." start="0x0" />
+        <Enum name="B_0x1" description="HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). This is used on a controller error detection and escalation handling, in case of a not responding target to a private message or a direct read CCC." start="0x1" />
+      </BitField>
+      <BitField name="HKSDAEN" description="High-keeper enable on SDA line (when I3C acts as a controller)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="High-keeper is disabled" start="0x0" />
+        <Enum name="B_0x1" description="High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up." start="0x1" />
+      </BitField>
+      <BitField name="HJACK" description="Hot-join request acknowledge (when I3C acts as a controller)" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request is not acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request is acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="RX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for RX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXFLUSH" description="RX-FIFO flush (whatever I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXTHRES" description="RX-FIFO threshold (whatever I3C acts as controller/target)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word/4-bytes threshold" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="TX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for TX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXFLUSH" description="TX-FIFO flush (whatever I3C acts as controller/target)" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXTHRES" description="TX-FIFO threshold (whatever I3C acts as controller/target)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word / 4-byte threshold" start="0x1" />
+      </BitField>
+      <BitField name="SDMAEN" description="S-FIFO DMA request enable (when I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for reading status register I3C_SR" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for reading status register I3C_SR" start="0x1" />
+      </BitField>
+      <BitField name="SFLUSH" description="S-FIFO flush (when I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush S-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="SMODE" description="S-FIFO enable / status receive mode (when I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="S-FIFO is disabled" start="0x0" />
+        <Enum name="B_0x1" description="S-FIFO is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TMODE" description="Transmit mode (when I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer." start="0x0" />
+        <Enum name="B_0x1" description="C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. Refer to Section 64.10.2 for more details." start="0x1" />
+      </BitField>
+      <BitField name="CDMAEN" description="C-FIFO DMA request enable (when I3C acts as controller)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for C-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CFLUSH" description="C-FIFO flush (when I3C acts as controller)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TSFSET" description="Frame transfer set (software trigger) (when I3C acts as controller)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RDR" description="I3C receive data byte register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data on I3C bus." start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_RDWR" description="I3C receive data word register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data (earliest byte on I3C bus)." start="0" size="8" access="ReadOnly" />
+      <BitField name="RDB1" description="8-bit received data (next byte after RDB0 on I3C bus)." start="8" size="8" access="ReadOnly" />
+      <BitField name="RDB2" description="8-bit received data (next byte after RDB1 on I3C bus)." start="16" size="8" access="ReadOnly" />
+      <BitField name="RDB3" description="8-bit received data (latest byte on I3C bus)." start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_TDR" description="I3C transmit data byte register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit data to transmit on I3C bus." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_TDWR" description="I3C transmit data word register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit transmit data (earliest byte on I3C bus)" start="0" size="8" access="WriteOnly" />
+      <BitField name="TDB1" description="8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." start="8" size="8" access="WriteOnly" />
+      <BitField name="TDB2" description="8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." start="16" size="8" access="WriteOnly" />
+      <BitField name="TDB3" description="8-bit transmit data (latest byte on I3C bus)." start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_IBIDR" description="I3C IBI payload data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIDB0" description="8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte)." start="0" size="8" access="Read/Write" />
+      <BitField name="IBIDB1" description="8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." start="8" size="8" access="Read/Write" />
+      <BitField name="IBIDB2" description="8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." start="16" size="8" access="Read/Write" />
+      <BitField name="IBIDB3" description="8-bit IBI payload data (latest byte on I3C bus)." start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TGTTDR" description="I3C target transmit configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TGTTDCNT" description="Transmit data counter, in bytes (when I3C is configured as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="PRELOAD" description="Preload of the TX-FIFO (when I3C is configured as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no TX-FIFO preload" start="0x0" />
+        <Enum name="B_0x1" description="TX-FIFO preload" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_SR" description="I3C status register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XDCNT" description="Data counter " start="0" size="16" access="ReadOnly" />
+      <BitField name="ABT" description="A private read message is ended prematurely by the target (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no early completion from the target" start="0x0" />
+        <Enum name="B_0x1" description="early completion from the target" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Message direction" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write" start="0x0" />
+        <Enum name="B_0x1" description="read" start="0x1" />
+      </BitField>
+      <BitField name="MID" description="Message identifier/counter of a given frame (when the I3C acts as controller)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_SER" description="I3C status error register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CODERR" description="Protocol error code/type" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="CE0 error (transaction after sending CCC):" start="0x0" />
+        <Enum name="B_0x1" description="CE1 error (monitoring error):" start="0x1" />
+        <Enum name="B_0x2" description="CE2 error (no response to broadcast address):" start="0x2" />
+        <Enum name="B_0x3" description="CE3 error (failed controller-role hand-off):" start="0x3" />
+        <Enum name="B_0x8" description="TE0 error (invalid broadcast address 0b111_1110 + W):" start="0x8" />
+        <Enum name="B_0x9" description="TE1 error (CCC code):" start="0x9" />
+        <Enum name="B_0xA" description="TE2 error (write data):" start="0xA" />
+        <Enum name="B_0xB" description="TE3 error (assigned address during dynamic address arbitration):" start="0xB" />
+        <Enum name="B_0xC" description="TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration):" start="0xC" />
+        <Enum name="B_0xD" description="TE5 error (transaction after detecting CCC):" start="0xD" />
+        <Enum name="B_0xE" description="TE6 error (monitoring error):" start="0xE" />
+      </BitField>
+      <BitField name="PERR" description="Protocol error" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="SCL stall error (when the I3C acts as target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB)" start="0x1" />
+      </BitField>
+      <BitField name="DOVR" description="RX-FIFO overrun or TX-FIFO underrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected either:" start="0x1" />
+      </BitField>
+      <BitField name="COVR" description="C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected either:" start="0x1" />
+      </BitField>
+      <BitField name="ANACK" description="Address not acknowledged (when the I3C is configured as controller)" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that the static/dynamic address was not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DNACK" description="Data not acknowledged (when the I3C acts as controller)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that a data byte is not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DERR" description="Data error (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RMR" description="I3C received message register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIRDCNT" description="IBI received payload data count (when the I3C is configured as controller)" start="0" size="3" access="ReadOnly" />
+      <BitField name="RCODE" description="Received CCC code (when the I3C is configured as target)" start="8" size="8" access="ReadOnly" />
+      <BitField name="RADD" description="Received target address (when the I3C is configured as controller)" start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_EVR" description="I3C event register" start="+0x050" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEF" description="C-FIFO empty flag (whatever the I3C acts as controller)" start="0" size="1" access="ReadOnly" />
+      <BitField name="TXFEF" description="TX-FIFO empty flag (whatever the I3C acts as controller/target)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFNFF" description="C-FIFO not full flag (when the I3C acts as controller)" start="2" size="1" access="ReadOnly" />
+      <BitField name="SFNEF" description="S-FIFO not empty flag (when the I3C acts as controller)" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXFNFF" description="TX-FIFO not full flag (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXFNEF" description="RX-FIFO not empty flag (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXLASTF" description="Last written data byte/word flag (whatever the I3C acts as controller/target)" start="6" size="1" access="ReadOnly" />
+      <BitField name="RXLASTF" description="Last read data byte/word flag (when the I3C acts as controller)" start="7" size="1" access="ReadOnly" />
+      <BitField name="FCF" description="Frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly" />
+      <BitField name="RXTGTENDF" description="Target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="ReadOnly" />
+      <BitField name="ERRF" description="Flag (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly" />
+      <BitField name="IBIF" description="IBI flag (when the I3C acts as controller)" start="15" size="1" access="ReadOnly" />
+      <BitField name="IBIENDF" description="IBI end flag (when the I3C acts as target)" start="16" size="1" access="ReadOnly" />
+      <BitField name="CRF" description="Controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="ReadOnly" />
+      <BitField name="CRUPDF" description="Controller-role update flag (when the I3C acts as target)" start="18" size="1" access="ReadOnly" />
+      <BitField name="HJF" description="Hot-join flag (when the I3C acts as controller)" start="19" size="1" access="ReadOnly" />
+      <BitField name="WKPF" description="Wake-up/missed start flag (when the I3C acts as target)" start="21" size="1" access="ReadOnly" />
+      <BitField name="GETF" description="Get flag (when the I3C acts as target)" start="22" size="1" access="ReadOnly" />
+      <BitField name="STAF" description="Get status flag (when the I3C acts as target)" start="23" size="1" access="ReadOnly" />
+      <BitField name="DAUPDF" description="Dynamic address update flag (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+      <BitField name="MWLUPDF" description="Maximum write length update flag (when the I3C acts as target)" start="25" size="1" access="ReadOnly" />
+      <BitField name="MRLUPDF" description="Maximum read length update flag (when the I3C acts as target)" start="26" size="1" access="ReadOnly" />
+      <BitField name="RSTF" description="Reset pattern flag (when the I3C acts as target)" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASUPDF" description="Activity state update flag (when the I3C acts as target)" start="28" size="1" access="ReadOnly" />
+      <BitField name="INTUPDF" description="Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" start="29" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="DEFTGTS flag (when the I3C acts as target)" start="30" size="1" access="ReadOnly" />
+      <BitField name="GRPF" description="Group addressing flag (when the I3C acts as target)" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_IER" description="I3C interrupt enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFNFIE" description="C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFNEIE" description="S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FCIE" description="frame complete interrupt enable (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXTGTENDIE" description="target-initiated read end interrupt enable (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="error interrupt enable (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIIE" description="IBI request interrupt enable (when the I3C acts as controller)" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIENDIE" description="IBI end interrupt enable (when the I3C acts as target)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRIE" description="Controller-role request interrupt enable (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRUPDIE" description="Controller-role update interrupt enable (when the I3C acts as target)" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJIE" description="Hot-join interrupt enable (when the I3C acts as controller)" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WKPIE" description="Wake-up interrupt enable (when the I3C acts as target)" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GETIE" description="GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="STAIE" description="format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAUPDIE" description="ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MWLUPDIE" description="SETMWL CCC interrupt enable (when the I3C acts as target)" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRLUPDIE" description="SETMRL CCC interrupt enable (when the I3C acts as target)" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RSTIE" description="reset pattern interrupt enable (when the I3C acts as target)" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ASUPDIE" description="ENTASx CCC interrupt enable (when the I3C acts as target)" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="INTUPDIE" description="ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="DEFTGTS CCC interrupt enable (when the I3C acts as target)" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GRPIE" description="DEFGRPA CCC interrupt enable (when the I3C acts as target)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CEVR" description="I3C clear event register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFCF" description="Clear frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear FCF" start="0x1" />
+      </BitField>
+      <BitField name="CRXTGTENDF" description="Clear target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RXTGTENDF" start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="Clear error flag (whatever the I3C acts as controller/target)" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ERRF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIF" description="Clear IBI request flag (when the I3C acts as controller)" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIENDF" description="Clear IBI end flag (when the I3C acts as target)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIENDF" start="0x1" />
+      </BitField>
+      <BitField name="CCRF" description="Clear controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRF" start="0x1" />
+      </BitField>
+      <BitField name="CCRUPDF" description="Clear controller-role update flag (when the I3C acts as target)" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CHJF" description="Clear hot-join flag (when the I3C acts as controller)" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear HJF" start="0x1" />
+      </BitField>
+      <BitField name="CWKPF" description="Clear wake-up flag (when the I3C acts as target)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear WKPF" start="0x1" />
+      </BitField>
+      <BitField name="CGETF" description="Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GETF" start="0x1" />
+      </BitField>
+      <BitField name="CSTAF" description="Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear STAF" start="0x1" />
+      </BitField>
+      <BitField name="CDAUPDF" description="Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DAUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMWLUPDF" description="Clear SETMWL CCC flag (when the I3C acts as target)" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MWLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMRLUPDF" description="Clear SETMRL CCC flag (when the I3C acts as target)" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MRLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CRSTF" description="Clear reset pattern flag (when the I3C acts as target)" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RSTF" start="0x1" />
+      </BitField>
+      <BitField name="CASUPDF" description="Clear ENTASx CCC flag (when the I3C acts as target)" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ASUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CINTUPDF" description="Clear ENEC/DISEC CCC flag (when the I3C acts as target)" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CINTUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CDEFF" description="Clear DEFTGTS CCC flag (when the I3C acts as target)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DEFF" start="0x1" />
+      </BitField>
+      <BitField name="CGRPF" description="Clear DEFGRPA CCC flag (when the I3C acts as target)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GRPF" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR0" description="I3C own device characteristics register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAVAL" description="Dynamic address is valid (when the I3C acts as target)" start="0" size="1" access="Read/Write" />
+      <BitField name="DA" description="7-bit dynamic address" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIEN" description="IBI request enable (when the I3C acts as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IBI request disabled" start="0x0" />
+        <Enum name="B_0x1" description="IBI request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CREN" description="Controller-role request enable (when the I3C acts as target)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="controller-role request disabled" start="0x0" />
+        <Enum name="B_0x1" description="controller-role request enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJEN" description="Hot-join request enable (when the I3C acts as target)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request disabled" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request enabled" start="0x1" />
+      </BitField>
+      <BitField name="AS" description="Activity state (when the I3C acts as target)" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="activity state 0" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3" start="0x3" />
+      </BitField>
+      <BitField name="RSTACT" description="Reset action/level on received reset pattern (when the I3C acts as target)" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset action" start="0x0" />
+        <Enum name="B_0x1" description="first level of reset: the application software must either:" start="0x1" />
+        <Enum name="B_0x2" description="second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 21.3: RCC functional description - Reset) has the same impact as a pin reset (NRST = 0):" start="0x2" />
+        <Enum name="B_0x3" description="no reset action" start="0x3" />
+      </BitField>
+      <BitField name="RSTVAL" description="Reset action is valid (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_DEVR1" description="I3C device 1 characteristics register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR2" description="I3C device 2 characteristics register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR3" description="I3C device 3 characteristics register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR4" description="I3C device 4 characteristics register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXRLR" description="I3C maximum read length register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRL" description="Maximum data read length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="IBIP" description="IBI payload data maximum size, in bytes (when I3C acts as target)" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="null payload data size (only allowed when BCR2 = 0 in the IC3_BCR register)" start="0x0" />
+        <Enum name="B_0x1" description="1 byte (mandatory data byte MDB[7:0]" start="0x1" />
+        <Enum name="B_0x2" description="2 bytes (including first MDB[7:0])" start="0x2" />
+        <Enum name="B_0x3" description="3 bytes (including first MDB[7:0])" start="0x3" />
+        <Enum name="B_0x4" description="4 bytes (including first MDB[7:0])" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXWLR" description="I3C maximum write length register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MWL" description="Maximum data write length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR0" description="I3C timing register 0" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL_PP" description="SCL low duration in I3C push-pull phases, in number of kernel clocks cycles:" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH_I3C" description="SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles:" start="8" size="8" access="Read/Write" />
+      <BitField name="SCLL_OD" description="SCL low duration in open-drain phases, used for legacy Iless thansup&gt;2less than/sup&gt;C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles:" start="16" size="8" access="Read/Write" />
+      <BitField name="SCLH_I2C" description="SCL high duration, used for legacy Iless thansup&gt;2less than/sup&gt;C messages, in number of kernel clocks cycles:" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR1" description="I3C timing register 1" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVAL" description="Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. " start="0" size="8" access="Read/Write" />
+      <BitField name="ASNCR" description="Activity state of the new controller (when I3C acts as active controller)" start="8" size="2" access="Read/Write" />
+      <BitField name="FREE" description="Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" start="16" size="7" access="Read/Write" />
+      <BitField name="SDA_HD" description="SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub&gt;HD_PPless than/sub&gt;):" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR2" description="I3C timing register 2" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STALLT" description="Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup&gt;2less than/sup&gt;C read)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLD" description="Controller clock stall enable on PAR phase of Data" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLC" description="Controller clock stall enable on PAR phase of CCC" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLA" description="Controller clock stall enable on ACK phase" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="Controller clock stall time, in number of kernel clock cycles" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_BCR" description="I3C bus characteristics register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCR0" description="max data speed limitation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no limitation" start="0x0" />
+        <Enum name="B_0x1" description="limitation, as described by I3C_GETMXDSR." start="0x1" />
+      </BitField>
+      <BitField name="BCR2" description="in-band interrupt (IBI) payload" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the accepted IBI" start="0x0" />
+        <Enum name="B_0x1" description="at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes)" start="0x1" />
+      </BitField>
+      <BitField name="BCR6" description="Controller capable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C target (no controller capable)" start="0x0" />
+        <Enum name="B_0x1" description="I3C controller capable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DCR" description="I3C device characteristics register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCR" description="device characteristics ID" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="generic device (for v1.0 devices)" start="0x00" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETCAPR" description="I3C get capability register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPPEND" description="IBI MDB support for pending read notification" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification" start="0x0" />
+        <Enum name="B_0x1" description="this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CRCAPR" description="I3C controller-role capability register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPDHOFF" description="delayed controller-role hand-off" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not needs additional time to process a controller-role hand-off" start="0x0" />
+        <Enum name="B_0x1" description="this I3C needs additional time to process a controller-role hand-off" start="0x1" />
+      </BitField>
+      <BitField name="CAPGRP" description="group management support (when acting as controller)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not support group address capabilities" start="0x0" />
+        <Enum name="B_0x1" description="this I3C supports group address capabilities (when becoming controller)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETMXDSR" description="I3C get capability register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFAS" description="Controller hand-off activity state " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="activity state 0 is the initial activity state of this I3C before and when becoming controller" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1 is the initial activity state of this I3C when becoming controller" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2 is the initial activity state of this I3C when becoming controller" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3 is the initial activity state of this I3C when becoming controller" start="0x3" />
+      </BitField>
+      <BitField name="FMT" description="GETMXDS CCC format" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="format 1 (2 bytes with MaxWr with no defining byte, MaxRd)" start="0x0" />
+        <Enum name="B_0x1" description="format 2: (5 bytes w.ith MaxWr with no defining byte, MaxRd, MaxRdTurn)" start="0x1" />
+        <Enum name="B_0x2" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn)" start="0x2" />
+        <Enum name="B_0x3" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn)" start="0x3" />
+      </BitField>
+      <BitField name="RDTURN" description="programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" start="16" size="8" access="Read/Write" />
+      <BitField name="TSCO" description="clock-to-data turnaround time (tless thansub&gt;SCOless than/sub&gt;)" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;SCOless than/sub&gt; less than or equal to 12 ns" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;SCOless than/sub&gt; &gt; 12 ns (refer to the datasheet for more details)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_EPIDR" description="I3C extended provisioned ID register" start="+0xD4" size="4" reset_value="0x02080000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIPIID" description="4-bit MIPI Instance ID" start="12" size="4" access="Read/Write" />
+      <BitField name="IDTSEL" description="provisioned ID type selector" start="16" size="1" access="ReadOnly" />
+      <BitField name="MIPIMID" description="15-bit MIPI manufacturer ID" start="17" size="15" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I3C2" description="Improved inter-integrated circuit" start="0x40006400">
+    <Register name="I3C_CR" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target)" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer" start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="RNW" description="Read / non-write message (when I3C acts as controller)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="write message" start="0x0" />
+        <Enum name="B_0x1" description="read message" start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="7-bit I3C dynamic / Iless thansup&gt;2less than/sup&gt;C static target address (when I3C acts as controller)" start="17" size="7" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (whatever I3C acts as controller/target)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="SCL clock is forced to stop until a next control word is executed" start="0x0" />
+        <Enum name="B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="header message" start="0x1" />
+        <Enum name="B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="private message (refer to Figure 801)" start="0x2" />
+        <Enum name="B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="direct message (second part of an I3C SDR direct CCC command) (refer to Figure 794)" start="0x3" />
+        <Enum name="B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="legacy Iless thansup&gt;2less than/sup&gt;C message (refer to Figure 803)" start="0x4" />
+        <Enum name="B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET" description="hot-join request (W) (refer to Figure 805)" start="0x8" />
+        <Enum name="B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET" description="controller-role request (W) (refer to Figure 806)" start="0x9" />
+        <Enum name="B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET" description="IBI (in-band interrupt) request (R) (refer to Figure 804)" start="0xA" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when the I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="this message from controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CR_alternate" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer." start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="CCC" description="8-bit CCC code (when I3C acts as controller)" start="16" size="8" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (when I3C acts as controller)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="broadcast/direct CCC command (refer to Table 621, Figure 794, Figure 795, Figure 796)" start="0x6" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="the message from the controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CFGR" description="I3C configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="I3C enable (whatever I3C acts as controller/target)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C is disabled" start="0x0" />
+        <Enum name="B_0x1" description="I3C is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRINIT" description="Initial controller/target role" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="target role" start="0x0" />
+        <Enum name="B_0x1" description="controller role" start="0x1" />
+      </BitField>
+      <BitField name="NOARBH" description="No arbitrable header after a start (when I3C acts as a controller)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup&gt;2less than/sup&gt;C message or an I3C SDR private read/write message (default)." start="0x0" />
+        <Enum name="B_0x1" description="No arbitrable header" start="0x1" />
+      </BitField>
+      <BitField name="RSTPTRN" description="HDR reset pattern enable (when I3C acts as a controller)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="standard stop emitted at the end of a frame" start="0x0" />
+        <Enum name="B_0x1" description="HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command" start="0x1" />
+      </BitField>
+      <BitField name="EXITPTRN" description="HDR exit pattern enable (when I3C acts as a controller)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). This is used to send the header, to test ownership of the bus when there is a suspicion of a problem after controller-role hand-off (new controller did not assert its controller-role by accessing the previous one in less than the delay defined by the activity state)." start="0x0" />
+        <Enum name="B_0x1" description="HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). This is used on a controller error detection and escalation handling, in case of a not responding target to a private message or a direct read CCC." start="0x1" />
+      </BitField>
+      <BitField name="HKSDAEN" description="High-keeper enable on SDA line (when I3C acts as a controller)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="High-keeper is disabled" start="0x0" />
+        <Enum name="B_0x1" description="High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up." start="0x1" />
+      </BitField>
+      <BitField name="HJACK" description="Hot-join request acknowledge (when I3C acts as a controller)" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request is not acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request is acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="RX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for RX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXFLUSH" description="RX-FIFO flush (whatever I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXTHRES" description="RX-FIFO threshold (whatever I3C acts as controller/target)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word/4-bytes threshold" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="TX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for TX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXFLUSH" description="TX-FIFO flush (whatever I3C acts as controller/target)" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXTHRES" description="TX-FIFO threshold (whatever I3C acts as controller/target)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word / 4-byte threshold" start="0x1" />
+      </BitField>
+      <BitField name="SDMAEN" description="S-FIFO DMA request enable (when I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for reading status register I3C_SR" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for reading status register I3C_SR" start="0x1" />
+      </BitField>
+      <BitField name="SFLUSH" description="S-FIFO flush (when I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush S-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="SMODE" description="S-FIFO enable / status receive mode (when I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="S-FIFO is disabled" start="0x0" />
+        <Enum name="B_0x1" description="S-FIFO is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TMODE" description="Transmit mode (when I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer." start="0x0" />
+        <Enum name="B_0x1" description="C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. Refer to Section 64.10.2 for more details." start="0x1" />
+      </BitField>
+      <BitField name="CDMAEN" description="C-FIFO DMA request enable (when I3C acts as controller)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for C-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CFLUSH" description="C-FIFO flush (when I3C acts as controller)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TSFSET" description="Frame transfer set (software trigger) (when I3C acts as controller)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RDR" description="I3C receive data byte register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data on I3C bus." start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_RDWR" description="I3C receive data word register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data (earliest byte on I3C bus)." start="0" size="8" access="ReadOnly" />
+      <BitField name="RDB1" description="8-bit received data (next byte after RDB0 on I3C bus)." start="8" size="8" access="ReadOnly" />
+      <BitField name="RDB2" description="8-bit received data (next byte after RDB1 on I3C bus)." start="16" size="8" access="ReadOnly" />
+      <BitField name="RDB3" description="8-bit received data (latest byte on I3C bus)." start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_TDR" description="I3C transmit data byte register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit data to transmit on I3C bus." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_TDWR" description="I3C transmit data word register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit transmit data (earliest byte on I3C bus)" start="0" size="8" access="WriteOnly" />
+      <BitField name="TDB1" description="8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." start="8" size="8" access="WriteOnly" />
+      <BitField name="TDB2" description="8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." start="16" size="8" access="WriteOnly" />
+      <BitField name="TDB3" description="8-bit transmit data (latest byte on I3C bus)." start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_IBIDR" description="I3C IBI payload data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIDB0" description="8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte)." start="0" size="8" access="Read/Write" />
+      <BitField name="IBIDB1" description="8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." start="8" size="8" access="Read/Write" />
+      <BitField name="IBIDB2" description="8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." start="16" size="8" access="Read/Write" />
+      <BitField name="IBIDB3" description="8-bit IBI payload data (latest byte on I3C bus)." start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TGTTDR" description="I3C target transmit configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TGTTDCNT" description="Transmit data counter, in bytes (when I3C is configured as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="PRELOAD" description="Preload of the TX-FIFO (when I3C is configured as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no TX-FIFO preload" start="0x0" />
+        <Enum name="B_0x1" description="TX-FIFO preload" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_SR" description="I3C status register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XDCNT" description="Data counter " start="0" size="16" access="ReadOnly" />
+      <BitField name="ABT" description="A private read message is ended prematurely by the target (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no early completion from the target" start="0x0" />
+        <Enum name="B_0x1" description="early completion from the target" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Message direction" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write" start="0x0" />
+        <Enum name="B_0x1" description="read" start="0x1" />
+      </BitField>
+      <BitField name="MID" description="Message identifier/counter of a given frame (when the I3C acts as controller)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_SER" description="I3C status error register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CODERR" description="Protocol error code/type" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="CE0 error (transaction after sending CCC):" start="0x0" />
+        <Enum name="B_0x1" description="CE1 error (monitoring error):" start="0x1" />
+        <Enum name="B_0x2" description="CE2 error (no response to broadcast address):" start="0x2" />
+        <Enum name="B_0x3" description="CE3 error (failed controller-role hand-off):" start="0x3" />
+        <Enum name="B_0x8" description="TE0 error (invalid broadcast address 0b111_1110 + W):" start="0x8" />
+        <Enum name="B_0x9" description="TE1 error (CCC code):" start="0x9" />
+        <Enum name="B_0xA" description="TE2 error (write data):" start="0xA" />
+        <Enum name="B_0xB" description="TE3 error (assigned address during dynamic address arbitration):" start="0xB" />
+        <Enum name="B_0xC" description="TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration):" start="0xC" />
+        <Enum name="B_0xD" description="TE5 error (transaction after detecting CCC):" start="0xD" />
+        <Enum name="B_0xE" description="TE6 error (monitoring error):" start="0xE" />
+      </BitField>
+      <BitField name="PERR" description="Protocol error" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="SCL stall error (when the I3C acts as target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB)" start="0x1" />
+      </BitField>
+      <BitField name="DOVR" description="RX-FIFO overrun or TX-FIFO underrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected either:" start="0x1" />
+      </BitField>
+      <BitField name="COVR" description="C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected either:" start="0x1" />
+      </BitField>
+      <BitField name="ANACK" description="Address not acknowledged (when the I3C is configured as controller)" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that the static/dynamic address was not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DNACK" description="Data not acknowledged (when the I3C acts as controller)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that a data byte is not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DERR" description="Data error (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RMR" description="I3C received message register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIRDCNT" description="IBI received payload data count (when the I3C is configured as controller)" start="0" size="3" access="ReadOnly" />
+      <BitField name="RCODE" description="Received CCC code (when the I3C is configured as target)" start="8" size="8" access="ReadOnly" />
+      <BitField name="RADD" description="Received target address (when the I3C is configured as controller)" start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_EVR" description="I3C event register" start="+0x050" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEF" description="C-FIFO empty flag (whatever the I3C acts as controller)" start="0" size="1" access="ReadOnly" />
+      <BitField name="TXFEF" description="TX-FIFO empty flag (whatever the I3C acts as controller/target)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFNFF" description="C-FIFO not full flag (when the I3C acts as controller)" start="2" size="1" access="ReadOnly" />
+      <BitField name="SFNEF" description="S-FIFO not empty flag (when the I3C acts as controller)" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXFNFF" description="TX-FIFO not full flag (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXFNEF" description="RX-FIFO not empty flag (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXLASTF" description="Last written data byte/word flag (whatever the I3C acts as controller/target)" start="6" size="1" access="ReadOnly" />
+      <BitField name="RXLASTF" description="Last read data byte/word flag (when the I3C acts as controller)" start="7" size="1" access="ReadOnly" />
+      <BitField name="FCF" description="Frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly" />
+      <BitField name="RXTGTENDF" description="Target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="ReadOnly" />
+      <BitField name="ERRF" description="Flag (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly" />
+      <BitField name="IBIF" description="IBI flag (when the I3C acts as controller)" start="15" size="1" access="ReadOnly" />
+      <BitField name="IBIENDF" description="IBI end flag (when the I3C acts as target)" start="16" size="1" access="ReadOnly" />
+      <BitField name="CRF" description="Controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="ReadOnly" />
+      <BitField name="CRUPDF" description="Controller-role update flag (when the I3C acts as target)" start="18" size="1" access="ReadOnly" />
+      <BitField name="HJF" description="Hot-join flag (when the I3C acts as controller)" start="19" size="1" access="ReadOnly" />
+      <BitField name="WKPF" description="Wake-up/missed start flag (when the I3C acts as target)" start="21" size="1" access="ReadOnly" />
+      <BitField name="GETF" description="Get flag (when the I3C acts as target)" start="22" size="1" access="ReadOnly" />
+      <BitField name="STAF" description="Get status flag (when the I3C acts as target)" start="23" size="1" access="ReadOnly" />
+      <BitField name="DAUPDF" description="Dynamic address update flag (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+      <BitField name="MWLUPDF" description="Maximum write length update flag (when the I3C acts as target)" start="25" size="1" access="ReadOnly" />
+      <BitField name="MRLUPDF" description="Maximum read length update flag (when the I3C acts as target)" start="26" size="1" access="ReadOnly" />
+      <BitField name="RSTF" description="Reset pattern flag (when the I3C acts as target)" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASUPDF" description="Activity state update flag (when the I3C acts as target)" start="28" size="1" access="ReadOnly" />
+      <BitField name="INTUPDF" description="Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" start="29" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="DEFTGTS flag (when the I3C acts as target)" start="30" size="1" access="ReadOnly" />
+      <BitField name="GRPF" description="Group addressing flag (when the I3C acts as target)" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_IER" description="I3C interrupt enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFNFIE" description="C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFNEIE" description="S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FCIE" description="frame complete interrupt enable (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXTGTENDIE" description="target-initiated read end interrupt enable (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="error interrupt enable (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIIE" description="IBI request interrupt enable (when the I3C acts as controller)" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIENDIE" description="IBI end interrupt enable (when the I3C acts as target)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRIE" description="Controller-role request interrupt enable (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRUPDIE" description="Controller-role update interrupt enable (when the I3C acts as target)" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJIE" description="Hot-join interrupt enable (when the I3C acts as controller)" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WKPIE" description="Wake-up interrupt enable (when the I3C acts as target)" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GETIE" description="GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="STAIE" description="format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAUPDIE" description="ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MWLUPDIE" description="SETMWL CCC interrupt enable (when the I3C acts as target)" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRLUPDIE" description="SETMRL CCC interrupt enable (when the I3C acts as target)" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RSTIE" description="reset pattern interrupt enable (when the I3C acts as target)" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ASUPDIE" description="ENTASx CCC interrupt enable (when the I3C acts as target)" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="INTUPDIE" description="ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="DEFTGTS CCC interrupt enable (when the I3C acts as target)" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GRPIE" description="DEFGRPA CCC interrupt enable (when the I3C acts as target)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CEVR" description="I3C clear event register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFCF" description="Clear frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear FCF" start="0x1" />
+      </BitField>
+      <BitField name="CRXTGTENDF" description="Clear target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RXTGTENDF" start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="Clear error flag (whatever the I3C acts as controller/target)" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ERRF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIF" description="Clear IBI request flag (when the I3C acts as controller)" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIENDF" description="Clear IBI end flag (when the I3C acts as target)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIENDF" start="0x1" />
+      </BitField>
+      <BitField name="CCRF" description="Clear controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRF" start="0x1" />
+      </BitField>
+      <BitField name="CCRUPDF" description="Clear controller-role update flag (when the I3C acts as target)" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CHJF" description="Clear hot-join flag (when the I3C acts as controller)" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear HJF" start="0x1" />
+      </BitField>
+      <BitField name="CWKPF" description="Clear wake-up flag (when the I3C acts as target)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear WKPF" start="0x1" />
+      </BitField>
+      <BitField name="CGETF" description="Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GETF" start="0x1" />
+      </BitField>
+      <BitField name="CSTAF" description="Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear STAF" start="0x1" />
+      </BitField>
+      <BitField name="CDAUPDF" description="Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DAUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMWLUPDF" description="Clear SETMWL CCC flag (when the I3C acts as target)" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MWLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMRLUPDF" description="Clear SETMRL CCC flag (when the I3C acts as target)" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MRLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CRSTF" description="Clear reset pattern flag (when the I3C acts as target)" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RSTF" start="0x1" />
+      </BitField>
+      <BitField name="CASUPDF" description="Clear ENTASx CCC flag (when the I3C acts as target)" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ASUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CINTUPDF" description="Clear ENEC/DISEC CCC flag (when the I3C acts as target)" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CINTUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CDEFF" description="Clear DEFTGTS CCC flag (when the I3C acts as target)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DEFF" start="0x1" />
+      </BitField>
+      <BitField name="CGRPF" description="Clear DEFGRPA CCC flag (when the I3C acts as target)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GRPF" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR0" description="I3C own device characteristics register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAVAL" description="Dynamic address is valid (when the I3C acts as target)" start="0" size="1" access="Read/Write" />
+      <BitField name="DA" description="7-bit dynamic address" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIEN" description="IBI request enable (when the I3C acts as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IBI request disabled" start="0x0" />
+        <Enum name="B_0x1" description="IBI request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CREN" description="Controller-role request enable (when the I3C acts as target)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="controller-role request disabled" start="0x0" />
+        <Enum name="B_0x1" description="controller-role request enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJEN" description="Hot-join request enable (when the I3C acts as target)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request disabled" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request enabled" start="0x1" />
+      </BitField>
+      <BitField name="AS" description="Activity state (when the I3C acts as target)" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="activity state 0" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3" start="0x3" />
+      </BitField>
+      <BitField name="RSTACT" description="Reset action/level on received reset pattern (when the I3C acts as target)" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset action" start="0x0" />
+        <Enum name="B_0x1" description="first level of reset: the application software must either:" start="0x1" />
+        <Enum name="B_0x2" description="second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 21.3: RCC functional description - Reset) has the same impact as a pin reset (NRST = 0):" start="0x2" />
+        <Enum name="B_0x3" description="no reset action" start="0x3" />
+      </BitField>
+      <BitField name="RSTVAL" description="Reset action is valid (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_DEVR1" description="I3C device 1 characteristics register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR2" description="I3C device 2 characteristics register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR3" description="I3C device 3 characteristics register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR4" description="I3C device 4 characteristics register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXRLR" description="I3C maximum read length register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRL" description="Maximum data read length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="IBIP" description="IBI payload data maximum size, in bytes (when I3C acts as target)" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="null payload data size (only allowed when BCR2 = 0 in the IC3_BCR register)" start="0x0" />
+        <Enum name="B_0x1" description="1 byte (mandatory data byte MDB[7:0]" start="0x1" />
+        <Enum name="B_0x2" description="2 bytes (including first MDB[7:0])" start="0x2" />
+        <Enum name="B_0x3" description="3 bytes (including first MDB[7:0])" start="0x3" />
+        <Enum name="B_0x4" description="4 bytes (including first MDB[7:0])" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXWLR" description="I3C maximum write length register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MWL" description="Maximum data write length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR0" description="I3C timing register 0" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL_PP" description="SCL low duration in I3C push-pull phases, in number of kernel clocks cycles:" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH_I3C" description="SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles:" start="8" size="8" access="Read/Write" />
+      <BitField name="SCLL_OD" description="SCL low duration in open-drain phases, used for legacy Iless thansup&gt;2less than/sup&gt;C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles:" start="16" size="8" access="Read/Write" />
+      <BitField name="SCLH_I2C" description="SCL high duration, used for legacy Iless thansup&gt;2less than/sup&gt;C messages, in number of kernel clocks cycles:" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR1" description="I3C timing register 1" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVAL" description="Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. " start="0" size="8" access="Read/Write" />
+      <BitField name="ASNCR" description="Activity state of the new controller (when I3C acts as active controller)" start="8" size="2" access="Read/Write" />
+      <BitField name="FREE" description="Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" start="16" size="7" access="Read/Write" />
+      <BitField name="SDA_HD" description="SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub&gt;HD_PPless than/sub&gt;):" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR2" description="I3C timing register 2" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STALLT" description="Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup&gt;2less than/sup&gt;C read)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLD" description="Controller clock stall enable on PAR phase of Data" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLC" description="Controller clock stall enable on PAR phase of CCC" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLA" description="Controller clock stall enable on ACK phase" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="Controller clock stall time, in number of kernel clock cycles" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_BCR" description="I3C bus characteristics register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCR0" description="max data speed limitation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no limitation" start="0x0" />
+        <Enum name="B_0x1" description="limitation, as described by I3C_GETMXDSR." start="0x1" />
+      </BitField>
+      <BitField name="BCR2" description="in-band interrupt (IBI) payload" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the accepted IBI" start="0x0" />
+        <Enum name="B_0x1" description="at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes)" start="0x1" />
+      </BitField>
+      <BitField name="BCR6" description="Controller capable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C target (no controller capable)" start="0x0" />
+        <Enum name="B_0x1" description="I3C controller capable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DCR" description="I3C device characteristics register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCR" description="device characteristics ID" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="generic device (for v1.0 devices)" start="0x00" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETCAPR" description="I3C get capability register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPPEND" description="IBI MDB support for pending read notification" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification" start="0x0" />
+        <Enum name="B_0x1" description="this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CRCAPR" description="I3C controller-role capability register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPDHOFF" description="delayed controller-role hand-off" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not needs additional time to process a controller-role hand-off" start="0x0" />
+        <Enum name="B_0x1" description="this I3C needs additional time to process a controller-role hand-off" start="0x1" />
+      </BitField>
+      <BitField name="CAPGRP" description="group management support (when acting as controller)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not support group address capabilities" start="0x0" />
+        <Enum name="B_0x1" description="this I3C supports group address capabilities (when becoming controller)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETMXDSR" description="I3C get capability register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFAS" description="Controller hand-off activity state " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="activity state 0 is the initial activity state of this I3C before and when becoming controller" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1 is the initial activity state of this I3C when becoming controller" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2 is the initial activity state of this I3C when becoming controller" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3 is the initial activity state of this I3C when becoming controller" start="0x3" />
+      </BitField>
+      <BitField name="FMT" description="GETMXDS CCC format" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="format 1 (2 bytes with MaxWr with no defining byte, MaxRd)" start="0x0" />
+        <Enum name="B_0x1" description="format 2: (5 bytes w.ith MaxWr with no defining byte, MaxRd, MaxRdTurn)" start="0x1" />
+        <Enum name="B_0x2" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn)" start="0x2" />
+        <Enum name="B_0x3" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn)" start="0x3" />
+      </BitField>
+      <BitField name="RDTURN" description="programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" start="16" size="8" access="Read/Write" />
+      <BitField name="TSCO" description="clock-to-data turnaround time (tless thansub&gt;SCOless than/sub&gt;)" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;SCOless than/sub&gt; less than or equal to 12 ns" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;SCOless than/sub&gt; &gt; 12 ns (refer to the datasheet for more details)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_EPIDR" description="I3C extended provisioned ID register" start="+0xD4" size="4" reset_value="0x02080000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIPIID" description="4-bit MIPI Instance ID" start="12" size="4" access="Read/Write" />
+      <BitField name="IDTSEL" description="provisioned ID type selector" start="16" size="1" access="ReadOnly" />
+      <BitField name="MIPIMID" description="15-bit MIPI manufacturer ID" start="17" size="15" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I3C2_S" description="Improved inter-integrated circuit" start="0x50006400">
+    <Register name="I3C_CR" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target)" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer" start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="RNW" description="Read / non-write message (when I3C acts as controller)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="write message" start="0x0" />
+        <Enum name="B_0x1" description="read message" start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="7-bit I3C dynamic / Iless thansup&gt;2less than/sup&gt;C static target address (when I3C acts as controller)" start="17" size="7" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (whatever I3C acts as controller/target)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="SCL clock is forced to stop until a next control word is executed" start="0x0" />
+        <Enum name="B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="header message" start="0x1" />
+        <Enum name="B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="private message (refer to Figure 801)" start="0x2" />
+        <Enum name="B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="direct message (second part of an I3C SDR direct CCC command) (refer to Figure 794)" start="0x3" />
+        <Enum name="B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="legacy Iless thansup&gt;2less than/sup&gt;C message (refer to Figure 803)" start="0x4" />
+        <Enum name="B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET" description="hot-join request (W) (refer to Figure 805)" start="0x8" />
+        <Enum name="B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET" description="controller-role request (W) (refer to Figure 806)" start="0x9" />
+        <Enum name="B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET" description="IBI (in-band interrupt) request (R) (refer to Figure 804)" start="0xA" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when the I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="this message from controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CR_alternate" description="I3C message control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCNT" description="Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes" start="0" size="16" access="WriteOnly">
+        <Enum name="B_0x0000" description="no data to transfer." start="0x0000" />
+        <Enum name="B_0x0001" description="1 byte" start="0x0001" />
+        <Enum name="B_0x0002" description="2 bytes" start="0x0002" />
+        <Enum name="B_0xFFFF" description="64 Kbytes - 1 byte" start="0xFFFF" />
+      </BitField>
+      <BitField name="CCC" description="8-bit CCC code (when I3C acts as controller)" start="16" size="8" access="WriteOnly" />
+      <BitField name="MTYPE" description="Message type (when I3C acts as controller)" start="27" size="4" access="WriteOnly">
+        <Enum name="B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER" description="broadcast/direct CCC command (refer to Table 621, Figure 794, Figure 795, Figure 796)" start="0x6" />
+      </BitField>
+      <BitField name="MEND" description="Message end type / last message of a frame (when I3C acts as controller)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="this message from controller is followed by a repeated start (Sr), before another message must be emitted" start="0x0" />
+        <Enum name="B_0x1" description="the message from the controller ends with a stop (P), being the last message of a frame" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CFGR" description="I3C configuration register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="I3C enable (whatever I3C acts as controller/target)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C is disabled" start="0x0" />
+        <Enum name="B_0x1" description="I3C is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRINIT" description="Initial controller/target role" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="target role" start="0x0" />
+        <Enum name="B_0x1" description="controller role" start="0x1" />
+      </BitField>
+      <BitField name="NOARBH" description="No arbitrable header after a start (when I3C acts as a controller)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup&gt;2less than/sup&gt;C message or an I3C SDR private read/write message (default)." start="0x0" />
+        <Enum name="B_0x1" description="No arbitrable header" start="0x1" />
+      </BitField>
+      <BitField name="RSTPTRN" description="HDR reset pattern enable (when I3C acts as a controller)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="standard stop emitted at the end of a frame" start="0x0" />
+        <Enum name="B_0x1" description="HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command" start="0x1" />
+      </BitField>
+      <BitField name="EXITPTRN" description="HDR exit pattern enable (when I3C acts as a controller)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). This is used to send the header, to test ownership of the bus when there is a suspicion of a problem after controller-role hand-off (new controller did not assert its controller-role by accessing the previous one in less than the delay defined by the activity state)." start="0x0" />
+        <Enum name="B_0x1" description="HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). This is used on a controller error detection and escalation handling, in case of a not responding target to a private message or a direct read CCC." start="0x1" />
+      </BitField>
+      <BitField name="HKSDAEN" description="High-keeper enable on SDA line (when I3C acts as a controller)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="High-keeper is disabled" start="0x0" />
+        <Enum name="B_0x1" description="High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up." start="0x1" />
+      </BitField>
+      <BitField name="HJACK" description="Hot-join request acknowledge (when I3C acts as a controller)" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request is not acknowledged" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request is acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="RX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for RX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXFLUSH" description="RX-FIFO flush (whatever I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush RX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="RXTHRES" description="RX-FIFO threshold (whatever I3C acts as controller/target)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word/4-bytes threshold" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="TX-FIFO DMA request enable (whatever I3C acts as controller/target)" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for TX-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXFLUSH" description="TX-FIFO flush (whatever I3C acts as controller/target)" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush TX-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TXTHRES" description="TX-FIFO threshold (whatever I3C acts as controller/target)" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1-byte threshold" start="0x0" />
+        <Enum name="B_0x1" description="1-word / 4-byte threshold" start="0x1" />
+      </BitField>
+      <BitField name="SDMAEN" description="S-FIFO DMA request enable (when I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for reading status register I3C_SR" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for reading status register I3C_SR" start="0x1" />
+      </BitField>
+      <BitField name="SFLUSH" description="S-FIFO flush (when I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush S-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="SMODE" description="S-FIFO enable / status receive mode (when I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="S-FIFO is disabled" start="0x0" />
+        <Enum name="B_0x1" description="S-FIFO is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TMODE" description="Transmit mode (when I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer." start="0x0" />
+        <Enum name="B_0x1" description="C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. Refer to Section 64.10.2 for more details." start="0x1" />
+      </BitField>
+      <BitField name="CDMAEN" description="C-FIFO DMA request enable (when I3C acts as controller)" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA mode is disabled for C-FIFO" start="0x0" />
+        <Enum name="B_0x1" description="DMA mode is enabled for C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CFLUSH" description="C-FIFO flush (when I3C acts as controller)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="flush C-FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TSFSET" description="Frame transfer set (software trigger) (when I3C acts as controller)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RDR" description="I3C receive data byte register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data on I3C bus." start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_RDWR" description="I3C receive data word register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDB0" description="8-bit received data (earliest byte on I3C bus)." start="0" size="8" access="ReadOnly" />
+      <BitField name="RDB1" description="8-bit received data (next byte after RDB0 on I3C bus)." start="8" size="8" access="ReadOnly" />
+      <BitField name="RDB2" description="8-bit received data (next byte after RDB1 on I3C bus)." start="16" size="8" access="ReadOnly" />
+      <BitField name="RDB3" description="8-bit received data (latest byte on I3C bus)." start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_TDR" description="I3C transmit data byte register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit data to transmit on I3C bus." start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_TDWR" description="I3C transmit data word register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDB0" description="8-bit transmit data (earliest byte on I3C bus)" start="0" size="8" access="WriteOnly" />
+      <BitField name="TDB1" description="8-bit transmit data (next byte after TDB0[7:0] on I3C bus)." start="8" size="8" access="WriteOnly" />
+      <BitField name="TDB2" description="8-bit transmit data (next byte after TDB1[7:0] on I3C bus)." start="16" size="8" access="WriteOnly" />
+      <BitField name="TDB3" description="8-bit transmit data (latest byte on I3C bus)." start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="I3C_IBIDR" description="I3C IBI payload data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIDB0" description="8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte)." start="0" size="8" access="Read/Write" />
+      <BitField name="IBIDB1" description="8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0])." start="8" size="8" access="Read/Write" />
+      <BitField name="IBIDB2" description="8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0])." start="16" size="8" access="Read/Write" />
+      <BitField name="IBIDB3" description="8-bit IBI payload data (latest byte on I3C bus)." start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TGTTDR" description="I3C target transmit configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TGTTDCNT" description="Transmit data counter, in bytes (when I3C is configured as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="PRELOAD" description="Preload of the TX-FIFO (when I3C is configured as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no TX-FIFO preload" start="0x0" />
+        <Enum name="B_0x1" description="TX-FIFO preload" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_SR" description="I3C status register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XDCNT" description="Data counter " start="0" size="16" access="ReadOnly" />
+      <BitField name="ABT" description="A private read message is ended prematurely by the target (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no early completion from the target" start="0x0" />
+        <Enum name="B_0x1" description="early completion from the target" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Message direction" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write" start="0x0" />
+        <Enum name="B_0x1" description="read" start="0x1" />
+      </BitField>
+      <BitField name="MID" description="Message identifier/counter of a given frame (when the I3C acts as controller)" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_SER" description="I3C status error register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CODERR" description="Protocol error code/type" start="0" size="4" access="ReadOnly">
+        <Enum name="B_0x0" description="CE0 error (transaction after sending CCC):" start="0x0" />
+        <Enum name="B_0x1" description="CE1 error (monitoring error):" start="0x1" />
+        <Enum name="B_0x2" description="CE2 error (no response to broadcast address):" start="0x2" />
+        <Enum name="B_0x3" description="CE3 error (failed controller-role hand-off):" start="0x3" />
+        <Enum name="B_0x8" description="TE0 error (invalid broadcast address 0b111_1110 + W):" start="0x8" />
+        <Enum name="B_0x9" description="TE1 error (CCC code):" start="0x9" />
+        <Enum name="B_0xA" description="TE2 error (write data):" start="0xA" />
+        <Enum name="B_0xB" description="TE3 error (assigned address during dynamic address arbitration):" start="0xB" />
+        <Enum name="B_0xC" description="TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration):" start="0xC" />
+        <Enum name="B_0xD" description="TE5 error (transaction after detecting CCC):" start="0xD" />
+        <Enum name="B_0xE" description="TE6 error (monitoring error):" start="0xE" />
+      </BitField>
+      <BitField name="PERR" description="Protocol error" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0]" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="SCL stall error (when the I3C acts as target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB)" start="0x1" />
+      </BitField>
+      <BitField name="DOVR" description="RX-FIFO overrun or TX-FIFO underrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="whatever controller or target, hardware detected either:" start="0x1" />
+      </BitField>
+      <BitField name="COVR" description="C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected either:" start="0x1" />
+      </BitField>
+      <BitField name="ANACK" description="Address not acknowledged (when the I3C is configured as controller)" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that the static/dynamic address was not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DNACK" description="Data not acknowledged (when the I3C acts as controller)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected that a data byte is not acknowledged by a target, either during:" start="0x1" />
+      </BitField>
+      <BitField name="DERR" description="Data error (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no detected error" start="0x0" />
+        <Enum name="B_0x1" description="controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_RMR" description="I3C received message register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IBIRDCNT" description="IBI received payload data count (when the I3C is configured as controller)" start="0" size="3" access="ReadOnly" />
+      <BitField name="RCODE" description="Received CCC code (when the I3C is configured as target)" start="8" size="8" access="ReadOnly" />
+      <BitField name="RADD" description="Received target address (when the I3C is configured as controller)" start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_EVR" description="I3C event register" start="+0x050" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="CFEF" description="C-FIFO empty flag (whatever the I3C acts as controller)" start="0" size="1" access="ReadOnly" />
+      <BitField name="TXFEF" description="TX-FIFO empty flag (whatever the I3C acts as controller/target)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFNFF" description="C-FIFO not full flag (when the I3C acts as controller)" start="2" size="1" access="ReadOnly" />
+      <BitField name="SFNEF" description="S-FIFO not empty flag (when the I3C acts as controller)" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXFNFF" description="TX-FIFO not full flag (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXFNEF" description="RX-FIFO not empty flag (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly" />
+      <BitField name="TXLASTF" description="Last written data byte/word flag (whatever the I3C acts as controller/target)" start="6" size="1" access="ReadOnly" />
+      <BitField name="RXLASTF" description="Last read data byte/word flag (when the I3C acts as controller)" start="7" size="1" access="ReadOnly" />
+      <BitField name="FCF" description="Frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly" />
+      <BitField name="RXTGTENDF" description="Target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="ReadOnly" />
+      <BitField name="ERRF" description="Flag (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly" />
+      <BitField name="IBIF" description="IBI flag (when the I3C acts as controller)" start="15" size="1" access="ReadOnly" />
+      <BitField name="IBIENDF" description="IBI end flag (when the I3C acts as target)" start="16" size="1" access="ReadOnly" />
+      <BitField name="CRF" description="Controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="ReadOnly" />
+      <BitField name="CRUPDF" description="Controller-role update flag (when the I3C acts as target)" start="18" size="1" access="ReadOnly" />
+      <BitField name="HJF" description="Hot-join flag (when the I3C acts as controller)" start="19" size="1" access="ReadOnly" />
+      <BitField name="WKPF" description="Wake-up/missed start flag (when the I3C acts as target)" start="21" size="1" access="ReadOnly" />
+      <BitField name="GETF" description="Get flag (when the I3C acts as target)" start="22" size="1" access="ReadOnly" />
+      <BitField name="STAF" description="Get status flag (when the I3C acts as target)" start="23" size="1" access="ReadOnly" />
+      <BitField name="DAUPDF" description="Dynamic address update flag (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+      <BitField name="MWLUPDF" description="Maximum write length update flag (when the I3C acts as target)" start="25" size="1" access="ReadOnly" />
+      <BitField name="MRLUPDF" description="Maximum read length update flag (when the I3C acts as target)" start="26" size="1" access="ReadOnly" />
+      <BitField name="RSTF" description="Reset pattern flag (when the I3C acts as target)" start="27" size="1" access="ReadOnly" />
+      <BitField name="ASUPDF" description="Activity state update flag (when the I3C acts as target)" start="28" size="1" access="ReadOnly" />
+      <BitField name="INTUPDF" description="Interrupt/controller-role/hot-join update flag (when the I3C acts as target)" start="29" size="1" access="ReadOnly" />
+      <BitField name="DEFF" description="DEFTGTS flag (when the I3C acts as target)" start="30" size="1" access="ReadOnly" />
+      <BitField name="GRPF" description="Group addressing flag (when the I3C acts as target)" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_IER" description="I3C interrupt enable register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFNFIE" description="C-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFNEIE" description="S-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target)" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target)" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FCIE" description="frame complete interrupt enable (whatever the I3C acts as controller/target)" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXTGTENDIE" description="target-initiated read end interrupt enable (when the I3C acts as controller)" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ERRIE" description="error interrupt enable (whatever the I3C acts as controller/target)" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIIE" description="IBI request interrupt enable (when the I3C acts as controller)" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IBIENDIE" description="IBI end interrupt enable (when the I3C acts as target)" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRIE" description="Controller-role request interrupt enable (when the I3C acts as controller)" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRUPDIE" description="Controller-role update interrupt enable (when the I3C acts as target)" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJIE" description="Hot-join interrupt enable (when the I3C acts as controller)" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="WKPIE" description="Wake-up interrupt enable (when the I3C acts as target)" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GETIE" description="GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="STAIE" description="format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target)" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DAUPDIE" description="ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MWLUPDIE" description="SETMWL CCC interrupt enable (when the I3C acts as target)" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MRLUPDIE" description="SETMRL CCC interrupt enable (when the I3C acts as target)" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RSTIE" description="reset pattern interrupt enable (when the I3C acts as target)" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ASUPDIE" description="ENTASx CCC interrupt enable (when the I3C acts as target)" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="INTUPDIE" description="ENEC/DISEC CCC interrupt enable (when the I3C acts as target)" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEFIE" description="DEFTGTS CCC interrupt enable (when the I3C acts as target)" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="GRPIE" description="DEFGRPA CCC interrupt enable (when the I3C acts as target)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CEVR" description="I3C clear event register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFCF" description="Clear frame complete flag (whatever the I3C acts as controller/target)" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear FCF" start="0x1" />
+      </BitField>
+      <BitField name="CRXTGTENDF" description="Clear target-initiated read end flag (when the I3C acts as controller)" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RXTGTENDF" start="0x1" />
+      </BitField>
+      <BitField name="CERRF" description="Clear error flag (whatever the I3C acts as controller/target)" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ERRF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIF" description="Clear IBI request flag (when the I3C acts as controller)" start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIF" start="0x1" />
+      </BitField>
+      <BitField name="CIBIENDF" description="Clear IBI end flag (when the I3C acts as target)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear IBIENDF" start="0x1" />
+      </BitField>
+      <BitField name="CCRF" description="Clear controller-role request flag (when the I3C acts as controller)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRF" start="0x1" />
+      </BitField>
+      <BitField name="CCRUPDF" description="Clear controller-role update flag (when the I3C acts as target)" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CRUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CHJF" description="Clear hot-join flag (when the I3C acts as controller)" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear HJF" start="0x1" />
+      </BitField>
+      <BitField name="CWKPF" description="Clear wake-up flag (when the I3C acts as target)" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear WKPF" start="0x1" />
+      </BitField>
+      <BitField name="CGETF" description="Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target)" start="22" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GETF" start="0x1" />
+      </BitField>
+      <BitField name="CSTAF" description="Clear format 1 GETSTATUS CCC flag (when the I3C acts as target)" start="23" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear STAF" start="0x1" />
+      </BitField>
+      <BitField name="CDAUPDF" description="Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target)" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DAUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMWLUPDF" description="Clear SETMWL CCC flag (when the I3C acts as target)" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MWLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CMRLUPDF" description="Clear SETMRL CCC flag (when the I3C acts as target)" start="26" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear MRLUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CRSTF" description="Clear reset pattern flag (when the I3C acts as target)" start="27" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear RSTF" start="0x1" />
+      </BitField>
+      <BitField name="CASUPDF" description="Clear ENTASx CCC flag (when the I3C acts as target)" start="28" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear ASUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CINTUPDF" description="Clear ENEC/DISEC CCC flag (when the I3C acts as target)" start="29" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear CINTUPDF" start="0x1" />
+      </BitField>
+      <BitField name="CDEFF" description="Clear DEFTGTS CCC flag (when the I3C acts as target)" start="30" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear DEFF" start="0x1" />
+      </BitField>
+      <BitField name="CGRPF" description="Clear DEFGRPA CCC flag (when the I3C acts as target)" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clear GRPF" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR0" description="I3C own device characteristics register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAVAL" description="Dynamic address is valid (when the I3C acts as target)" start="0" size="1" access="Read/Write" />
+      <BitField name="DA" description="7-bit dynamic address" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIEN" description="IBI request enable (when the I3C acts as target)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IBI request disabled" start="0x0" />
+        <Enum name="B_0x1" description="IBI request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CREN" description="Controller-role request enable (when the I3C acts as target)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="controller-role request disabled" start="0x0" />
+        <Enum name="B_0x1" description="controller-role request enabled" start="0x1" />
+      </BitField>
+      <BitField name="HJEN" description="Hot-join request enable (when the I3C acts as target)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="hot-join request disabled" start="0x0" />
+        <Enum name="B_0x1" description="hot-join request enabled" start="0x1" />
+      </BitField>
+      <BitField name="AS" description="Activity state (when the I3C acts as target)" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="activity state 0" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3" start="0x3" />
+      </BitField>
+      <BitField name="RSTACT" description="Reset action/level on received reset pattern (when the I3C acts as target)" start="22" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset action" start="0x0" />
+        <Enum name="B_0x1" description="first level of reset: the application software must either:" start="0x1" />
+        <Enum name="B_0x2" description="second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 21.3: RCC functional description - Reset) has the same impact as a pin reset (NRST = 0):" start="0x2" />
+        <Enum name="B_0x3" description="no reset action" start="0x3" />
+      </BitField>
+      <BitField name="RSTVAL" description="Reset action is valid (when the I3C acts as target)" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="I3C_DEVR1" description="I3C device 1 characteristics register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR2" description="I3C device 2 characteristics register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR3" description="I3C device 3 characteristics register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DEVR4" description="I3C device 4 characteristics register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DA" description="Assigned I3C dynamic address to target x (when the I3C acts as controller)" start="1" size="7" access="Read/Write" />
+      <BitField name="IBIACK" description="IBI request acknowledge (when the I3C acts as controller)" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="an IBI request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="CRACK" description="Controller-role request acknowledge (when the I3C acts as controller)" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="a controller-role request from target x must be NACK-ed" start="0x0" />
+        <Enum name="B_0x1" description="a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed" start="0x1" />
+      </BitField>
+      <BitField name="IBIDEN" description="IBI data enable (when the I3C acts as controller)" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the acknowledged IBI from target x" start="0x0" />
+        <Enum name="B_0x1" description="the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x" start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted" start="0x0" />
+        <Enum name="B_0x1" description="I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x" start="0x1" />
+      </BitField>
+      <BitField name="DIS" description="DA[6:0] write disabled (when the I3C acts as controller)" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed" start="0x0" />
+        <Enum name="B_0x1" description="write to DA[7:0] and to IBIDEN is disabled/locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXRLR" description="I3C maximum read length register" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRL" description="Maximum data read length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+      <BitField name="IBIP" description="IBI payload data maximum size, in bytes (when I3C acts as target)" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="null payload data size (only allowed when BCR2 = 0 in the IC3_BCR register)" start="0x0" />
+        <Enum name="B_0x1" description="1 byte (mandatory data byte MDB[7:0]" start="0x1" />
+        <Enum name="B_0x2" description="2 bytes (including first MDB[7:0])" start="0x2" />
+        <Enum name="B_0x3" description="3 bytes (including first MDB[7:0])" start="0x3" />
+        <Enum name="B_0x4" description="4 bytes (including first MDB[7:0])" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="I3C_MAXWLR" description="I3C maximum write length register" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MWL" description="Maximum data write length (when I3C acts as target)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR0" description="I3C timing register 0" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL_PP" description="SCL low duration in I3C push-pull phases, in number of kernel clocks cycles:" start="0" size="8" access="Read/Write" />
+      <BitField name="SCLH_I3C" description="SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles:" start="8" size="8" access="Read/Write" />
+      <BitField name="SCLL_OD" description="SCL low duration in open-drain phases, used for legacy Iless thansup&gt;2less than/sup&gt;C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles:" start="16" size="8" access="Read/Write" />
+      <BitField name="SCLH_I2C" description="SCL high duration, used for legacy Iless thansup&gt;2less than/sup&gt;C messages, in number of kernel clocks cycles:" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR1" description="I3C timing register 1" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVAL" description="Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. " start="0" size="8" access="Read/Write" />
+      <BitField name="ASNCR" description="Activity state of the new controller (when I3C acts as active controller)" start="8" size="2" access="Read/Write" />
+      <BitField name="FREE" description="Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller)" start="16" size="7" access="Read/Write" />
+      <BitField name="SDA_HD" description="SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub&gt;HD_PPless than/sub&gt;):" start="28" size="1" access="Read/Write" />
+    </Register>
+    <Register name="I3C_TIMINGR2" description="I3C timing register 2" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STALLT" description="Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup&gt;2less than/sup&gt;C read)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLD" description="Controller clock stall enable on PAR phase of Data" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLC" description="Controller clock stall enable on PAR phase of CCC" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALLA" description="Controller clock stall enable on ACK phase" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no stall" start="0x0" />
+        <Enum name="B_0x1" description="stall enabled" start="0x1" />
+      </BitField>
+      <BitField name="STALL" description="Controller clock stall time, in number of kernel clock cycles" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="I3C_BCR" description="I3C bus characteristics register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCR0" description="max data speed limitation" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no limitation" start="0x0" />
+        <Enum name="B_0x1" description="limitation, as described by I3C_GETMXDSR." start="0x1" />
+      </BitField>
+      <BitField name="BCR2" description="in-band interrupt (IBI) payload" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no data byte follows the accepted IBI" start="0x0" />
+        <Enum name="B_0x1" description="at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes)" start="0x1" />
+      </BitField>
+      <BitField name="BCR6" description="Controller capable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C target (no controller capable)" start="0x0" />
+        <Enum name="B_0x1" description="I3C controller capable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_DCR" description="I3C device characteristics register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCR" description="device characteristics ID" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="generic device (for v1.0 devices)" start="0x00" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETCAPR" description="I3C get capability register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPPEND" description="IBI MDB support for pending read notification" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification" start="0x0" />
+        <Enum name="B_0x1" description="this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_CRCAPR" description="I3C controller-role capability register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAPDHOFF" description="delayed controller-role hand-off" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not needs additional time to process a controller-role hand-off" start="0x0" />
+        <Enum name="B_0x1" description="this I3C needs additional time to process a controller-role hand-off" start="0x1" />
+      </BitField>
+      <BitField name="CAPGRP" description="group management support (when acting as controller)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="this I3C does not support group address capabilities" start="0x0" />
+        <Enum name="B_0x1" description="this I3C supports group address capabilities (when becoming controller)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_GETMXDSR" description="I3C get capability register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HOFFAS" description="Controller hand-off activity state " start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="activity state 0 is the initial activity state of this I3C before and when becoming controller" start="0x0" />
+        <Enum name="B_0x1" description="activity state 1 is the initial activity state of this I3C when becoming controller" start="0x1" />
+        <Enum name="B_0x2" description="activity state 2 is the initial activity state of this I3C when becoming controller" start="0x2" />
+        <Enum name="B_0x3" description="activity state 3 is the initial activity state of this I3C when becoming controller" start="0x3" />
+      </BitField>
+      <BitField name="FMT" description="GETMXDS CCC format" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="format 1 (2 bytes with MaxWr with no defining byte, MaxRd)" start="0x0" />
+        <Enum name="B_0x1" description="format 2: (5 bytes w.ith MaxWr with no defining byte, MaxRd, MaxRdTurn)" start="0x1" />
+        <Enum name="B_0x2" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn)" start="0x2" />
+        <Enum name="B_0x3" description="format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn)" start="0x3" />
+      </BitField>
+      <BitField name="RDTURN" description="programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)" start="16" size="8" access="Read/Write" />
+      <BitField name="TSCO" description="clock-to-data turnaround time (tless thansub&gt;SCOless than/sub&gt;)" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;SCOless than/sub&gt; less than or equal to 12 ns" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;SCOless than/sub&gt; &gt; 12 ns (refer to the datasheet for more details)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="I3C_EPIDR" description="I3C extended provisioned ID register" start="+0xD4" size="4" reset_value="0x02080000" reset_mask="0xFFFFFFFF">
+      <BitField name="MIPIID" description="4-bit MIPI Instance ID" start="12" size="4" access="Read/Write" />
+      <BitField name="IDTSEL" description="provisioned ID type selector" start="16" size="1" access="ReadOnly" />
+      <BitField name="MIPIMID" description="15-bit MIPI manufacturer ID" start="17" size="15" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="JPEG" description="JPEG codec" start="0x48023000">
+    <Register name="JPEG_CONFR0" description="JPEG codec control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="START" description="Start" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Stop/abort" start="0x0" />
+        <Enum name="B_0x1" description="Start" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_CONFR1" description="JPEG codec configuration register 1" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NF" description="Number of color components" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Grayscale (1 color component)" start="0x0" />
+        <Enum name="B_0x1" description="- (2 color components)" start="0x1" />
+        <Enum name="B_0x2" description="YUV or RGB (3 color components)" start="0x2" />
+        <Enum name="B_0x3" description="CMYK (4 color components)" start="0x3" />
+      </BitField>
+      <BitField name="DE" description="Codec operation as coder or decoder" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Code" start="0x0" />
+        <Enum name="B_0x1" description="Decode" start="0x1" />
+      </BitField>
+      <BitField name="COLSPACE" description="Color space" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Grayscale (1 quantization table)" start="0x0" />
+        <Enum name="B_0x1" description="YUV (2 quantization tables)" start="0x1" />
+        <Enum name="B_0x2" description="RGB (3 quantization tables)" start="0x2" />
+        <Enum name="B_0x3" description="CMYK (4 quantization tables)" start="0x3" />
+      </BitField>
+      <BitField name="NS" description="Number of components for scan" start="6" size="2" access="Read/Write" />
+      <BitField name="HDR" description="Header processing" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="YSIZE" description="Y Size" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR2" description="JPEG codec configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NMCU" description="Number of MCUs" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR3" description="JPEG codec configuration register 3" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSIZE" description="X size" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR4" description="JPEG codec configuration register 4" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR5" description="JPEG codec configuration register 5" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR6" description="JPEG codec configuration register 6" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR7" description="JPEG codec configuration register 7" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CR" description="JPEG control register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JCEN" description="JPEG core enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (internal registers are reset)." start="0x0" />
+        <Enum name="B_0x1" description="Enabled (internal registers are accessible)." start="0x1" />
+      </BitField>
+      <BitField name="IFTIE" description="Input FIFO threshold interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFNFIE" description="Input FIFO not full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="OFTIE" description="Output FIFO threshold interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="OFNEIE" description="Output FIFO not empty interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPDIE" description="Header parsing done interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMAEN" description="Input DMA enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="ODMAEN" description="Output DMA enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFF" description="Input FIFO flush" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is flushed" start="0x1" />
+      </BitField>
+      <BitField name="OFF" description="Output FIFO flush" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is flushed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_SR" description="JPEG status register" start="+0x034" size="4" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
+      <BitField name="IFTF" description="Input FIFO threshold flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="At or above threshold" start="0x0" />
+        <Enum name="B_0x1" description="Below threshold." start="0x1" />
+      </BitField>
+      <BitField name="IFNFF" description="Input FIFO not full flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Full" start="0x0" />
+        <Enum name="B_0x1" description="Not full" start="0x1" />
+      </BitField>
+      <BitField name="OFTF" description="Output FIFO threshold flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Below threshold" start="0x0" />
+        <Enum name="B_0x1" description="At or above threshold" start="0x1" />
+      </BitField>
+      <BitField name="OFNEF" description="Output FIFO not empty flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Empty (data not available)" start="0x0" />
+        <Enum name="B_0x1" description="Not empty (data available)" start="0x1" />
+      </BitField>
+      <BitField name="EOCF" description="End of conversion flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="HPDF" description="Header parsing done flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="COF" description="Codec operation flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not in progress" start="0x0" />
+        <Enum name="B_0x1" description="In progress" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_CFR" description="JPEG clear flag register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEOCF" description="Clear end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear" start="0x1" />
+      </BitField>
+      <BitField name="CHPDF" description="Clear header parsing done flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_DIR" description="JPEG data input register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAIN" description="Data input FIFO" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="JPEG_DOR" description="JPEG data output register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAOUT" description="Data output FIFO" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="JPEG_QMEM0_0" description="JPEG quantization memory 0" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF0" description="Quantization coefficient 0" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF1" description="Quantization coefficient 1" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF2" description="Quantization coefficient 2" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF3" description="Quantization coefficient 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_1" description="JPEG quantization memory 0" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF4" description="Quantization coefficient 4" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF5" description="Quantization coefficient 5" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF6" description="Quantization coefficient 6" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF7" description="Quantization coefficient 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_2" description="JPEG quantization memory 0" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF8" description="Quantization coefficient 8" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF9" description="Quantization coefficient 9" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF10" description="Quantization coefficient 10" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF11" description="Quantization coefficient 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_3" description="JPEG quantization memory 0" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF12" description="Quantization coefficient 12" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF13" description="Quantization coefficient 13" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF14" description="Quantization coefficient 14" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF15" description="Quantization coefficient 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_4" description="JPEG quantization memory 0" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF16" description="Quantization coefficient 16" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF17" description="Quantization coefficient 17" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_5" description="JPEG quantization memory 0" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF20" description="Quantization coefficient 20" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF21" description="Quantization coefficient 21" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_6" description="JPEG quantization memory 0" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF24" description="Quantization coefficient 24" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_7" description="JPEG quantization memory 0" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF28" description="Quantization coefficient 28" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF29" description="Quantization coefficient 29" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_8" description="JPEG quantization memory 0" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF32" description="Quantization coefficient 32" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF33" description="Quantization coefficient 33" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF34" description="Quantization coefficient 34" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_9" description="JPEG quantization memory 0" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF36" description="Quantization coefficient 36" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF37" description="Quantization coefficient 37" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_10" description="JPEG quantization memory 0" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF40" description="Quantization coefficient 40" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF41" description="Quantization coefficient 41" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_11" description="JPEG quantization memory 0" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF44" description="Quantization coefficient 44" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_12" description="JPEG quantization memory 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF48" description="Quantization coefficient 48" start="0" size="8" access="Read/Write" />
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+    </Register>
+    <Register name="JPEG_QMEM3_4" description="JPEG quantization memory 3" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF16" description="Quantization coefficient 16" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF17" description="Quantization coefficient 17" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_5" description="JPEG quantization memory 3" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF20" description="Quantization coefficient 20" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF21" description="Quantization coefficient 21" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_6" description="JPEG quantization memory 3" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF24" description="Quantization coefficient 24" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_7" description="JPEG quantization memory 3" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF28" description="Quantization coefficient 28" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF29" description="Quantization coefficient 29" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_8" description="JPEG quantization memory 3" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF32" description="Quantization coefficient 32" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF33" description="Quantization coefficient 33" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF34" description="Quantization coefficient 34" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_9" description="JPEG quantization memory 3" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF36" description="Quantization coefficient 36" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF37" description="Quantization coefficient 37" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_10" description="JPEG quantization memory 3" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF40" description="Quantization coefficient 40" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF41" description="Quantization coefficient 41" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_11" description="JPEG quantization memory 3" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF44" description="Quantization coefficient 44" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_12" description="JPEG quantization memory 3" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF48" description="Quantization coefficient 48" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF49" description="Quantization coefficient 49" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF50" description="Quantization coefficient 50" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF51" description="Quantization coefficient 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_13" description="JPEG quantization memory 3" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF52" description="Quantization coefficient 52" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF53" description="Quantization coefficient 53" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF54" description="Quantization coefficient 54" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF55" description="Quantization coefficient 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_14" description="JPEG quantization memory 3" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF56" description="Quantization coefficient 56" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF57" description="Quantization coefficient 57" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF58" description="Quantization coefficient 58" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF59" description="Quantization coefficient 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_15" description="JPEG quantization memory 3" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF60" description="Quantization coefficient 60" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF61" description="Quantization coefficient 61" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF62" description="Quantization coefficient 62" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF63" description="Quantization coefficient 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN0_0" description="JPEG Huffman min" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN0_1" description="JPEG Huffman min" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN0_2" description="JPEG Huffman min" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN0_3" description="JPEG Huffman min 0" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN1_0" description="JPEG Huffman min" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN1_1" description="JPEG Huffman min" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN1_2" description="JPEG Huffman min" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN1_3" description="JPEG Huffman min 1" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN2_0" description="JPEG Huffman min" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN2_1" description="JPEG Huffman min" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN2_2" description="JPEG Huffman min" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN2_3" description="JPEG Huffman min 2" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN3_0" description="JPEG Huffman min" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN3_1" description="JPEG Huffman min" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN3_2" description="JPEG Huffman min" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN3_3" description="JPEG Huffman min 3" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE0" description="JPEG Huffman base" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Data 0" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA1" description="Data 1" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE1" description="JPEG Huffman base" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA2" description="Data 2" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA3" description="Data 3" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE2" description="JPEG Huffman base" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA4" description="Data 4" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA5" description="Data 5" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE3" description="JPEG Huffman base" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA6" description="Data 6" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA7" description="Data 7" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE4" description="JPEG Huffman base" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA8" description="Data 8" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA9" description="Data 9" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE5" description="JPEG Huffman base" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA10" description="Data 10" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA11" description="Data 11" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE6" description="JPEG Huffman base" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA12" description="Data 12" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA13" description="Data 13" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE7" description="JPEG Huffman base" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA14" description="Data 14" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA15" description="Data 15" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE8" description="JPEG Huffman base" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Data 16" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA17" description="Data 17" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE9" description="JPEG Huffman base" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA18" description="Data 18" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA19" description="Data 19" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE10" description="JPEG Huffman base" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Data 20" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA21" description="Data 21" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE11" description="JPEG Huffman base" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA22" description="Data 22" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA23" description="Data 23" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE12" description="JPEG Huffman base" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Data 24" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA25" description="Data 25" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE13" description="JPEG Huffman base" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA26" description="Data 26" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA27" description="Data 27" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE14" description="JPEG Huffman base" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Data 28" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA29" description="Data 29" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE15" description="JPEG Huffman base" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA30" description="Data 30" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA31" description="Data 31" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE16" description="JPEG Huffman base" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Data 32" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA33" description="Data 33" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE17" description="JPEG Huffman base" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA34" description="Data 34" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA35" description="Data 35" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE18" description="JPEG Huffman base" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Data 36" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA37" description="Data 37" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE19" description="JPEG Huffman base" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA38" description="Data 38" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA39" description="Data 39" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE20" description="JPEG Huffman base" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Data 40" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA41" description="Data 41" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE21" description="JPEG Huffman base" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA42" description="Data 42" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA43" description="Data 43" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE22" description="JPEG Huffman base" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Data 44" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA45" description="Data 45" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE23" description="JPEG Huffman base" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA46" description="Data 46" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA47" description="Data 47" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE24" description="JPEG Huffman base" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Data 48" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA49" description="Data 49" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE25" description="JPEG Huffman base" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA50" description="Data 50" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA51" description="Data 51" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE26" description="JPEG Huffman base" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA52" description="Data 52" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA53" description="Data 53" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE27" description="JPEG Huffman base" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA54" description="Data 54" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA55" description="Data 55" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE28" description="JPEG Huffman base" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA56" description="Data 56" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA57" description="Data 57" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE29" description="JPEG Huffman base" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA58" description="Data 58" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA59" description="Data 59" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE30" description="JPEG Huffman base" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA60" description="Data 60" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA61" description="Data 61" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE31" description="JPEG Huffman base" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA62" description="Data 62" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA63" description="Data 63" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB0" description="JPEG Huffman symbol" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Data 0" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA1" description="Data 1" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA2" description="Data 2" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA3" description="Data 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB1" description="JPEG Huffman symbol" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA4" description="Data 4" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA5" description="Data 5" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA6" description="Data 6" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA7" description="Data 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB2" description="JPEG Huffman symbol" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA8" description="Data 8" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA9" description="Data 9" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA10" description="Data 10" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA11" description="Data 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB3" description="JPEG Huffman symbol" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA12" description="Data 12" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA13" description="Data 13" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA14" description="Data 14" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA15" description="Data 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB4" description="JPEG Huffman symbol" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Data 16" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA17" description="Data 17" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA18" description="Data 18" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA19" description="Data 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB5" description="JPEG Huffman symbol" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Data 20" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA21" description="Data 21" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA22" description="Data 22" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA23" description="Data 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB6" description="JPEG Huffman symbol" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Data 24" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA25" description="Data 25" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA26" description="Data 26" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA27" description="Data 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB7" description="JPEG Huffman symbol" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Data 28" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA29" description="Data 29" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA30" description="Data 30" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA31" description="Data 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB8" description="JPEG Huffman symbol" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Data 32" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA34" description="Data 34" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA35" description="Data 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB9" description="JPEG Huffman symbol" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Data 36" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA38" description="Data 38" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA39" description="Data 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB10" description="JPEG Huffman symbol" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Data 40" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA41" description="Data 41" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA42" description="Data 42" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA43" description="Data 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB11" description="JPEG Huffman symbol" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Data 44" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA45" description="Data 45" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA46" description="Data 46" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA47" description="Data 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB12" description="JPEG Huffman symbol" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Data 48" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA50" description="Data 50" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA51" description="Data 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB13" description="JPEG Huffman symbol" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA54" description="Data 54" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA55" description="Data 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB14" description="JPEG Huffman symbol" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA58" description="Data 58" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA59" description="Data 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB15" description="JPEG Huffman symbol" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA63" description="Data 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB16" description="JPEG Huffman symbol" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA67" description="Data 67" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB17" description="JPEG Huffman symbol" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA71" description="Data 71" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB18" description="JPEG Huffman symbol" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA74" description="Data 74" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA75" description="Data 75" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB19" description="JPEG Huffman symbol" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA78" description="Data 78" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA79" description="Data 79" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB20" description="JPEG Huffman symbol" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA80" description="Data 80" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA82" description="Data 82" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA83" description="Data 83" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB21" description="JPEG Huffman symbol" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFSYMB23" description="JPEG Huffman symbol" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFSYMB25" description="JPEG Huffman symbol" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB26" description="JPEG Huffman symbol" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFSYMB28" description="JPEG Huffman symbol" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+      <BitField name="DATA119" description="Data 119" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB30" description="JPEG Huffman symbol" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB31" description="JPEG Huffman symbol" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFSYMB35" description="JPEG Huffman symbol" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB36" description="JPEG Huffman symbol" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFSYMB38" description="JPEG Huffman symbol" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    <Register name="JPEG_HUFFSYMB40" description="JPEG Huffman symbol" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB41" description="JPEG Huffman symbol" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB42" description="JPEG Huffman symbol" start="+0x2B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB43" description="JPEG Huffman symbol" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFSYMB44" description="JPEG Huffman symbol" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA176" description="Data 176" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA177" description="Data 177" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA178" description="Data 178" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA179" description="Data 179" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB45" description="JPEG Huffman symbol" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA180" description="Data 180" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA181" description="Data 181" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA182" description="Data 182" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA183" description="Data 183" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB46" description="JPEG Huffman symbol" start="+0x2C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA184" description="Data 184" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA185" description="Data 185" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA186" description="Data 186" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA187" description="Data 187" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB47" description="JPEG Huffman symbol" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA188" description="Data 188" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA189" description="Data 189" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA190" description="Data 190" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA191" description="Data 191" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB48" description="JPEG Huffman symbol" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA192" description="Data 192" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA193" description="Data 193" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA194" description="Data 194" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA195" description="Data 195" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB49" description="JPEG Huffman symbol" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA196" description="Data 196" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA197" description="Data 197" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA198" description="Data 198" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA199" description="Data 199" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB50" description="JPEG Huffman symbol" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA200" description="Data 200" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA201" description="Data 201" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA202" description="Data 202" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA203" description="Data 203" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB51" description="JPEG Huffman symbol" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA204" description="Data 204" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA205" description="Data 205" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA206" description="Data 206" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA207" description="Data 207" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB52" description="JPEG Huffman symbol" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA208" description="Data 208" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA209" description="Data 209" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA210" description="Data 210" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA211" description="Data 211" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB53" description="JPEG Huffman symbol" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA212" description="Data 212" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA213" description="Data 213" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA214" description="Data 214" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA215" description="Data 215" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB54" description="JPEG Huffman symbol" start="+0x2E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA216" description="Data 216" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA217" description="Data 217" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA218" description="Data 218" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA219" description="Data 219" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB55" description="JPEG Huffman symbol" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA220" description="Data 220" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA221" description="Data 221" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA222" description="Data 222" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA223" description="Data 223" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB56" description="JPEG Huffman symbol" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA224" description="Data 224" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA225" description="Data 225" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA226" description="Data 226" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA227" description="Data 227" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB57" description="JPEG Huffman symbol" start="+0x2F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA228" description="Data 228" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA229" description="Data 229" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA230" description="Data 230" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA231" description="Data 231" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB58" description="JPEG Huffman symbol" start="+0x2F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA232" description="Data 232" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA233" description="Data 233" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA234" description="Data 234" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA235" description="Data 235" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB59" description="JPEG Huffman symbol" start="+0x2FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA236" description="Data 236" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA237" description="Data 237" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA238" description="Data 238" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA239" description="Data 239" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB60" description="JPEG Huffman symbol" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA240" description="Data 240" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA241" description="Data 241" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA242" description="Data 242" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA243" description="Data 243" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB61" description="JPEG Huffman symbol" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA244" description="Data 244" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA245" description="Data 245" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA246" description="Data 246" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA247" description="Data 247" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB62" description="JPEG Huffman symbol" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA248" description="Data 248" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA249" description="Data 249" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA250" description="Data 250" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA251" description="Data 251" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB63" description="JPEG Huffman symbol" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA252" description="Data 252" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA253" description="Data 253" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA254" description="Data 254" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA255" description="Data 255" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB64" description="JPEG Huffman symbol" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA256" description="Data 256" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA257" description="Data 257" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA258" description="Data 258" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA259" description="Data 259" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB65" description="JPEG Huffman symbol" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA260" description="Data 260" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA261" description="Data 261" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA262" description="Data 262" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA263" description="Data 263" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB66" description="JPEG Huffman symbol" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA264" description="Data 264" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA265" description="Data 265" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA266" description="Data 266" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA267" description="Data 267" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB67" description="JPEG Huffman symbol" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA268" description="Data 268" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA269" description="Data 269" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA270" description="Data 270" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA271" description="Data 271" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB68" description="JPEG Huffman symbol" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA272" description="Data 272" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA273" description="Data 273" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA274" description="Data 274" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA275" description="Data 275" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB69" description="JPEG Huffman symbol" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA276" description="Data 276" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA277" description="Data 277" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA278" description="Data 278" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA279" description="Data 279" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB70" description="JPEG Huffman symbol" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA280" description="Data 280" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA281" description="Data 281" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA282" description="Data 282" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA283" description="Data 283" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB71" description="JPEG Huffman symbol" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA284" description="Data 284" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA285" description="Data 285" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA286" description="Data 286" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA287" description="Data 287" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB72" description="JPEG Huffman symbol" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA288" description="Data 288" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA289" description="Data 289" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA290" description="Data 290" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA291" description="Data 291" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB73" description="JPEG Huffman symbol" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA292" description="Data 292" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA293" description="Data 293" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA294" description="Data 294" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA295" description="Data 295" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB74" description="JPEG Huffman symbol" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA296" description="Data 296" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA297" description="Data 297" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA298" description="Data 298" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA299" description="Data 299" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB75" description="JPEG Huffman symbol" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA300" description="Data 300" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA301" description="Data 301" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA302" description="Data 302" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA303" description="Data 303" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB76" description="JPEG Huffman symbol" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA304" description="Data 304" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA305" description="Data 305" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA306" description="Data 306" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA307" description="Data 307" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB77" description="JPEG Huffman symbol" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA308" description="Data 308" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA309" description="Data 309" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA310" description="Data 310" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA311" description="Data 311" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB78" description="JPEG Huffman symbol" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA312" description="Data 312" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA313" description="Data 313" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA314" description="Data 314" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA315" description="Data 315" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB79" description="JPEG Huffman symbol" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA316" description="Data 316" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA317" description="Data 317" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA318" description="Data 318" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA319" description="Data 319" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB80" description="JPEG Huffman symbol" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA320" description="Data 320" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA321" description="Data 321" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA322" description="Data 322" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA323" description="Data 323" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB81" description="JPEG Huffman symbol" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA324" description="Data 324" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA325" description="Data 325" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA326" description="Data 326" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA327" description="Data 327" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB82" description="JPEG Huffman symbol" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA328" description="Data 328" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA329" description="Data 329" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA330" description="Data 330" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA331" description="Data 331" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB83" description="JPEG Huffman symbol" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA332" description="Data 332" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA333" description="Data 333" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA334" description="Data 334" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA335" description="Data 335" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM0" description="JPEG DHT memory" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Huffman table data 0" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA1" description="Huffman table data 1" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA2" description="Huffman table data 2" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA3" description="Huffman table data 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM1" description="JPEG DHT memory" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA4" description="Huffman table data 4" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA5" description="Huffman table data 5" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA6" description="Huffman table data 6" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA7" description="Huffman table data 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM2" description="JPEG DHT memory" start="+0x368" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA8" description="Huffman table data 8" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA9" description="Huffman table data 9" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA10" description="Huffman table data 10" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA11" description="Huffman table data 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM3" description="JPEG DHT memory" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA12" description="Huffman table data 12" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA13" description="Huffman table data 13" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA14" description="Huffman table data 14" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA15" description="Huffman table data 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM4" description="JPEG DHT memory" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Huffman table data 16" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA17" description="Huffman table data 17" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA18" description="Huffman table data 18" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA19" description="Huffman table data 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM5" description="JPEG DHT memory" start="+0x374" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Huffman table data 20" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA21" description="Huffman table data 21" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA22" description="Huffman table data 22" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA23" description="Huffman table data 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM6" description="JPEG DHT memory" start="+0x378" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Huffman table data 24" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA25" description="Huffman table data 25" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA26" description="Huffman table data 26" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA27" description="Huffman table data 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM7" description="JPEG DHT memory" start="+0x37C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Huffman table data 28" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA29" description="Huffman table data 29" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA30" description="Huffman table data 30" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA31" description="Huffman table data 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM8" description="JPEG DHT memory" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Huffman table data 32" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA33" description="Huffman table data 33" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA34" description="Huffman table data 34" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA35" description="Huffman table data 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM9" description="JPEG DHT memory" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Huffman table data 36" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA37" description="Huffman table data 37" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA38" description="Huffman table data 38" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA39" description="Huffman table data 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM10" description="JPEG DHT memory" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Huffman table data 40" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA41" description="Huffman table data 41" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA42" description="Huffman table data 42" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA43" description="Huffman table data 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM11" description="JPEG DHT memory" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Huffman table data 44" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA45" description="Huffman table data 45" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA46" description="Huffman table data 46" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA47" description="Huffman table data 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM12" description="JPEG DHT memory" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Huffman table data 48" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA49" description="Huffman table data 49" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA50" description="Huffman table data 50" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA51" description="Huffman table data 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM13" description="JPEG DHT memory" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA52" description="Huffman table data 52" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA53" description="Huffman table data 53" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA54" description="Huffman table data 54" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA55" description="Huffman table data 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM14" description="JPEG DHT memory" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA56" description="Huffman table data 56" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA57" description="Huffman table data 57" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA58" description="Huffman table data 58" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA59" description="Huffman table data 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM15" description="JPEG DHT memory" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA60" description="Huffman table data 60" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA61" description="Huffman table data 61" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA62" description="Huffman table data 62" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA63" description="Huffman table data 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM16" description="JPEG DHT memory" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA64" description="Huffman table data 64" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA65" description="Huffman table data 65" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA66" description="Huffman table data 66" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA67" description="Huffman table data 67" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM17" description="JPEG DHT memory" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA68" description="Huffman table data 68" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA69" description="Huffman table data 69" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA70" description="Huffman table data 70" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA71" description="Huffman table data 71" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM18" description="JPEG DHT memory" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA72" description="Huffman table data 72" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA73" description="Huffman table data 73" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA74" description="Huffman table data 74" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA75" description="Huffman table data 75" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM19" description="JPEG DHT memory" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA76" description="Huffman table data 76" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA77" description="Huffman table data 77" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA78" description="Huffman table data 78" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA79" description="Huffman table data 79" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM20" description="JPEG DHT memory" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA80" description="Huffman table data 80" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA81" description="Huffman table data 81" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA82" description="Huffman table data 82" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA83" description="Huffman table data 83" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM21" description="JPEG DHT memory" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA84" description="Huffman table data 84" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA85" description="Huffman table data 85" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA86" description="Huffman table data 86" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA87" description="Huffman table data 87" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM22" description="JPEG DHT memory" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA88" description="Huffman table data 88" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA89" description="Huffman table data 89" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA90" description="Huffman table data 90" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA91" description="Huffman table data 91" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM23" description="JPEG DHT memory" start="+0x3BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA92" description="Huffman table data 92" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA93" description="Huffman table data 93" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA94" description="Huffman table data 94" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA95" description="Huffman table data 95" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM24" description="JPEG DHT memory" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA96" description="Huffman table data 96" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA97" description="Huffman table data 97" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA98" description="Huffman table data 98" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA99" description="Huffman table data 99" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM25" description="JPEG DHT memory" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA100" description="Huffman table data 100" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA101" description="Huffman table data 101" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA102" description="Huffman table data 102" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA103" description="Huffman table data 103" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM26" description="JPEG DHT memory" start="+0x3C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA104" description="Huffman table data 104" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA105" description="Huffman table data 105" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA106" description="Huffman table data 106" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA107" description="Huffman table data 107" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM27" description="JPEG DHT memory" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA108" description="Huffman table data 108" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA109" description="Huffman table data 109" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA110" description="Huffman table data 110" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA111" description="Huffman table data 111" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM28" description="JPEG DHT memory" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA112" description="Huffman table data 112" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA113" description="Huffman table data 113" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA114" description="Huffman table data 114" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA115" description="Huffman table data 115" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM29" description="JPEG DHT memory" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA116" description="Huffman table data 116" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA117" description="Huffman table data 117" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA118" description="Huffman table data 118" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA119" description="Huffman table data 119" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM30" description="JPEG DHT memory" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA120" description="Huffman table data 120" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA121" description="Huffman table data 121" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA122" description="Huffman table data 122" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA123" description="Huffman table data 123" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM31" description="JPEG DHT memory" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA124" description="Huffman table data 124" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA125" description="Huffman table data 125" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA126" description="Huffman table data 126" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA127" description="Huffman table data 127" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM32" description="JPEG DHT memory" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA128" description="Huffman table data 128" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA129" description="Huffman table data 129" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA130" description="Huffman table data 130" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA131" description="Huffman table data 131" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM33" description="JPEG DHT memory" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA132" description="Huffman table data 132" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA133" description="Huffman table data 133" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA134" description="Huffman table data 134" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA135" description="Huffman table data 135" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM34" description="JPEG DHT memory" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA136" description="Huffman table data 136" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA137" description="Huffman table data 137" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA138" description="Huffman table data 138" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA139" description="Huffman table data 139" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM35" description="JPEG DHT memory" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA140" description="Huffman table data 140" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA141" description="Huffman table data 141" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA142" description="Huffman table data 142" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA143" description="Huffman table data 143" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM36" description="JPEG DHT memory" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA144" description="Huffman table data 144" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA145" description="Huffman table data 145" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA146" description="Huffman table data 146" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA147" description="Huffman table data 147" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM37" description="JPEG DHT memory" start="+0x3F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA148" description="Huffman table data 148" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA149" description="Huffman table data 149" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA150" description="Huffman table data 150" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA151" description="Huffman table data 151" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM38" description="JPEG DHT memory" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA152" description="Huffman table data 152" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA153" description="Huffman table data 153" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA154" description="Huffman table data 154" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA155" description="Huffman table data 155" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM39" description="JPEG DHT memory" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA156" description="Huffman table data 156" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA157" description="Huffman table data 157" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA158" description="Huffman table data 158" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA159" description="Huffman table data 159" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM40" description="JPEG DHT memory" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA160" description="Huffman table data 160" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA161" description="Huffman table data 161" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA162" description="Huffman table data 162" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA163" description="Huffman table data 163" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM41" description="JPEG DHT memory" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA164" description="Huffman table data 164" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA165" description="Huffman table data 165" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA166" description="Huffman table data 166" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA167" description="Huffman table data 167" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM42" description="JPEG DHT memory" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA168" description="Huffman table data 168" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA169" description="Huffman table data 169" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA170" description="Huffman table data 170" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA171" description="Huffman table data 171" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM43" description="JPEG DHT memory" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA172" description="Huffman table data 172" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA173" description="Huffman table data 173" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA174" description="Huffman table data 174" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA175" description="Huffman table data 175" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM44" description="JPEG DHT memory" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA176" description="Huffman table data 176" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA177" description="Huffman table data 177" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA178" description="Huffman table data 178" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA179" description="Huffman table data 179" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM45" description="JPEG DHT memory" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA180" description="Huffman table data 180" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA181" description="Huffman table data 181" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA182" description="Huffman table data 182" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA183" description="Huffman table data 183" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM46" description="JPEG DHT memory" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA184" description="Huffman table data 184" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA185" description="Huffman table data 185" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA186" description="Huffman table data 186" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA187" description="Huffman table data 187" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM47" description="JPEG DHT memory" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA188" description="Huffman table data 188" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA189" description="Huffman table data 189" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA190" description="Huffman table data 190" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA191" description="Huffman table data 191" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM48" description="JPEG DHT memory" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA192" description="Huffman table data 192" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA193" description="Huffman table data 193" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA194" description="Huffman table data 194" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA195" description="Huffman table data 195" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM49" description="JPEG DHT memory" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA196" description="Huffman table data 196" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA197" description="Huffman table data 197" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA198" description="Huffman table data 198" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA199" description="Huffman table data 199" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM50" description="JPEG DHT memory" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA200" description="Huffman table data 200" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA201" description="Huffman table data 201" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA202" description="Huffman table data 202" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA203" description="Huffman table data 203" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM51" description="JPEG DHT memory" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA204" description="Huffman table data 204" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA205" description="Huffman table data 205" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA206" description="Huffman table data 206" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA207" description="Huffman table data 207" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM52" description="JPEG DHT memory" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA208" description="Huffman table data 208" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA209" description="Huffman table data 209" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA210" description="Huffman table data 210" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA211" description="Huffman table data 211" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM53" description="JPEG DHT memory" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA212" description="Huffman table data 212" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA213" description="Huffman table data 213" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA214" description="Huffman table data 214" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA215" description="Huffman table data 215" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM54" description="JPEG DHT memory" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA216" description="Huffman table data 216" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA217" description="Huffman table data 217" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA218" description="Huffman table data 218" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA219" description="Huffman table data 219" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM55" description="JPEG DHT memory" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA220" description="Huffman table data 220" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA221" description="Huffman table data 221" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA222" description="Huffman table data 222" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA223" description="Huffman table data 223" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM56" description="JPEG DHT memory" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA224" description="Huffman table data 224" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA225" description="Huffman table data 225" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA226" description="Huffman table data 226" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA227" description="Huffman table data 227" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM57" description="JPEG DHT memory" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA228" description="Huffman table data 228" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA229" description="Huffman table data 229" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA230" description="Huffman table data 230" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA231" description="Huffman table data 231" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM58" description="JPEG DHT memory" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA232" description="Huffman table data 232" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA233" description="Huffman table data 233" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA234" description="Huffman table data 234" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA235" description="Huffman table data 235" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM59" description="JPEG DHT memory" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA236" description="Huffman table data 236" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA237" description="Huffman table data 237" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA238" description="Huffman table data 238" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA239" description="Huffman table data 239" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM60" description="JPEG DHT memory" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA240" description="Huffman table data 240" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA241" description="Huffman table data 241" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA242" description="Huffman table data 242" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA243" description="Huffman table data 243" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM61" description="JPEG DHT memory" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA244" description="Huffman table data 244" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA245" description="Huffman table data 245" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA246" description="Huffman table data 246" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA247" description="Huffman table data 247" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM62" description="JPEG DHT memory" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA248" description="Huffman table data 248" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA249" description="Huffman table data 249" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA250" description="Huffman table data 250" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA251" description="Huffman table data 251" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM63" description="JPEG DHT memory" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA252" description="Huffman table data 252" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA253" description="Huffman table data 253" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA254" description="Huffman table data 254" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA255" description="Huffman table data 255" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM64" description="JPEG DHT memory" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA256" description="Huffman table data 256" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA257" description="Huffman table data 257" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA258" description="Huffman table data 258" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA259" description="Huffman table data 259" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM65" description="JPEG DHT memory" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA260" description="Huffman table data 260" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA261" description="Huffman table data 261" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA262" description="Huffman table data 262" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA263" description="Huffman table data 263" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM66" description="JPEG DHT memory" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA264" description="Huffman table data 264" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA265" description="Huffman table data 265" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA266" description="Huffman table data 266" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA267" description="Huffman table data 267" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM67" description="JPEG DHT memory" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA268" description="Huffman table data 268" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA269" description="Huffman table data 269" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA270" description="Huffman table data 270" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA271" description="Huffman table data 271" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM68" description="JPEG DHT memory" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA272" description="Huffman table data 272" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA273" description="Huffman table data 273" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA274" description="Huffman table data 274" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA275" description="Huffman table data 275" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM69" description="JPEG DHT memory" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA276" description="Huffman table data 276" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA277" description="Huffman table data 277" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA278" description="Huffman table data 278" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA279" description="Huffman table data 279" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM70" description="JPEG DHT memory" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA280" description="Huffman table data 280" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA281" description="Huffman table data 281" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA282" description="Huffman table data 282" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA283" description="Huffman table data 283" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM71" description="JPEG DHT memory" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA284" description="Huffman table data 284" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA285" description="Huffman table data 285" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA286" description="Huffman table data 286" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA287" description="Huffman table data 287" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM72" description="JPEG DHT memory" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA288" description="Huffman table data 288" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA289" description="Huffman table data 289" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA290" description="Huffman table data 290" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA291" description="Huffman table data 291" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM73" description="JPEG DHT memory" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA292" description="Huffman table data 292" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA293" description="Huffman table data 293" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA294" description="Huffman table data 294" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA295" description="Huffman table data 295" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM74" description="JPEG DHT memory" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA296" description="Huffman table data 296" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA297" description="Huffman table data 297" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA298" description="Huffman table data 298" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA299" description="Huffman table data 299" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM75" description="JPEG DHT memory" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA300" description="Huffman table data 300" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA301" description="Huffman table data 301" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA302" description="Huffman table data 302" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA303" description="Huffman table data 303" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM76" description="JPEG DHT memory" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA304" description="Huffman table data 304" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA305" description="Huffman table data 305" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA306" description="Huffman table data 306" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA307" description="Huffman table data 307" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM77" description="JPEG DHT memory" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA308" description="Huffman table data 308" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA309" description="Huffman table data 309" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA310" description="Huffman table data 310" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA311" description="Huffman table data 311" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM78" description="JPEG DHT memory" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA312" description="Huffman table data 312" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA313" description="Huffman table data 313" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA314" description="Huffman table data 314" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA315" description="Huffman table data 315" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM79" description="JPEG DHT memory" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA316" description="Huffman table data 316" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA317" description="Huffman table data 317" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA318" description="Huffman table data 318" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA319" description="Huffman table data 319" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM80" description="JPEG DHT memory" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA320" description="Huffman table data 320" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA321" description="Huffman table data 321" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA322" description="Huffman table data 322" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA323" description="Huffman table data 323" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM81" description="JPEG DHT memory" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA324" description="Huffman table data 324" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA325" description="Huffman table data 325" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA326" description="Huffman table data 326" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA327" description="Huffman table data 327" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM82" description="JPEG DHT memory" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA328" description="Huffman table data 328" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA329" description="Huffman table data 329" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA330" description="Huffman table data 330" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA331" description="Huffman table data 331" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM83" description="JPEG DHT memory" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA332" description="Huffman table data 332" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA333" description="Huffman table data 333" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA334" description="Huffman table data 334" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA335" description="Huffman table data 335" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM84" description="JPEG DHT memory" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA336" description="Huffman table data 336" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA337" description="Huffman table data 337" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA338" description="Huffman table data 338" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA339" description="Huffman table data 339" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM85" description="JPEG DHT memory" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA340" description="Huffman table data 340" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA341" description="Huffman table data 341" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA342" description="Huffman table data 342" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA343" description="Huffman table data 343" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM86" description="JPEG DHT memory" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA344" description="Huffman table data 344" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA345" description="Huffman table data 345" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA346" description="Huffman table data 346" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA347" description="Huffman table data 347" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM87" description="JPEG DHT memory" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA348" description="Huffman table data 348" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA349" description="Huffman table data 349" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA350" description="Huffman table data 350" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA351" description="Huffman table data 351" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM88" description="JPEG DHT memory" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA352" description="Huffman table data 352" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA353" description="Huffman table data 353" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA354" description="Huffman table data 354" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA355" description="Huffman table data 355" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM89" description="JPEG DHT memory" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA356" description="Huffman table data 356" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA357" description="Huffman table data 357" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA358" description="Huffman table data 358" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA359" description="Huffman table data 359" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM90" description="JPEG DHT memory" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA360" description="Huffman table data 360" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA361" description="Huffman table data 361" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA362" description="Huffman table data 362" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA363" description="Huffman table data 363" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM91" description="JPEG DHT memory" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA364" description="Huffman table data 364" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA365" description="Huffman table data 365" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA366" description="Huffman table data 366" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA367" description="Huffman table data 367" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM92" description="JPEG DHT memory" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA368" description="Huffman table data 368" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA369" description="Huffman table data 369" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA370" description="Huffman table data 370" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA371" description="Huffman table data 371" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM93" description="JPEG DHT memory" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA372" description="Huffman table data 372" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA373" description="Huffman table data 373" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA374" description="Huffman table data 374" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA375" description="Huffman table data 375" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM94" description="JPEG DHT memory" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA376" description="Huffman table data 376" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA377" description="Huffman table data 377" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA378" description="Huffman table data 378" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA379" description="Huffman table data 379" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM95" description="JPEG DHT memory" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA380" description="Huffman table data 380" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA381" description="Huffman table data 381" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA382" description="Huffman table data 382" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA383" description="Huffman table data 383" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM96" description="JPEG DHT memory" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA384" description="Huffman table data 384" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA385" description="Huffman table data 385" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA386" description="Huffman table data 386" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA387" description="Huffman table data 387" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM97" description="JPEG DHT memory" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA388" description="Huffman table data 388" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA389" description="Huffman table data 389" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA390" description="Huffman table data 390" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA391" description="Huffman table data 391" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM98" description="JPEG DHT memory" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA392" description="Huffman table data 392" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA393" description="Huffman table data 393" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA394" description="Huffman table data 394" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA395" description="Huffman table data 395" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM99" description="JPEG DHT memory" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA396" description="Huffman table data 396" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA397" description="Huffman table data 397" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA398" description="Huffman table data 398" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA399" description="Huffman table data 399" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM100" description="JPEG DHT memory" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA400" description="Huffman table data 400" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA401" description="Huffman table data 401" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA402" description="Huffman table data 402" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA403" description="Huffman table data 403" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM101" description="JPEG DHT memory" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA404" description="Huffman table data 404" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA405" description="Huffman table data 405" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA406" description="Huffman table data 406" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA407" description="Huffman table data 407" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM102" description="JPEG DHT memory" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA408" description="Huffman table data 408" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA409" description="Huffman table data 409" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA410" description="Huffman table data 410" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA411" description="Huffman table data 411" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_0" description="JPEG Huffman encoder AC0" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_1" description="JPEG Huffman encoder AC0" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_2" description="JPEG Huffman encoder AC0" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_3" description="JPEG Huffman encoder AC0" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_4" description="JPEG Huffman encoder AC0" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_5" description="JPEG Huffman encoder AC0" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_6" description="JPEG Huffman encoder AC0" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_7" description="JPEG Huffman encoder AC0" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_8" description="JPEG Huffman encoder AC0" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE16" description="Huffman code 16" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN16" description="Huffman length 16" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE17" description="Huffman code 17" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN17" description="Huffman length 17" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_9" description="JPEG Huffman encoder AC0" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE18" description="Huffman code 18" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN18" description="Huffman length 18" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE19" description="Huffman code 19" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN19" description="Huffman length 19" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_10" description="JPEG Huffman encoder AC0" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE20" description="Huffman code 20" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN20" description="Huffman length 20" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE21" description="Huffman code 21" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN21" description="Huffman length 21" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_11" description="JPEG Huffman encoder AC0" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE22" description="Huffman code 22" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN22" description="Huffman length 22" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE23" description="Huffman code 23" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN23" description="Huffman length 23" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_12" description="JPEG Huffman encoder AC0" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE24" description="Huffman code 24" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN24" description="Huffman length 24" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE25" description="Huffman code 25" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN25" description="Huffman length 25" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_13" description="JPEG Huffman encoder AC0" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE26" description="Huffman code 26" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN26" description="Huffman length 26" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE27" description="Huffman code 27" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN27" description="Huffman length 27" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_14" description="JPEG Huffman encoder AC0" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE28" description="Huffman code 28" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN28" description="Huffman length 28" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE29" description="Huffman code 29" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN29" description="Huffman length 29" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_15" description="JPEG Huffman encoder AC0" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE30" description="Huffman code 30" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN30" description="Huffman length 30" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE31" description="Huffman code 31" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN31" description="Huffman length 31" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_16" description="JPEG Huffman encoder AC0" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE32" description="Huffman code 32" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN32" description="Huffman length 32" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE33" description="Huffman code 33" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN33" description="Huffman length 33" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_17" description="JPEG Huffman encoder AC0" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE34" description="Huffman code 34" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN34" description="Huffman length 34" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE35" description="Huffman code 35" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN35" description="Huffman length 35" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_18" description="JPEG Huffman encoder AC0" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE36" description="Huffman code 36" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN36" description="Huffman length 36" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE37" description="Huffman code 37" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN37" description="Huffman length 37" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_19" description="JPEG Huffman encoder AC0" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE38" description="Huffman code 38" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN38" description="Huffman length 38" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE39" description="Huffman code 39" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN39" description="Huffman length 39" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HCODE40" description="Huffman code 40" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN40" description="Huffman length 40" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE41" description="Huffman code 41" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN41" description="Huffman length 41" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_21" description="JPEG Huffman encoder AC0" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE42" description="Huffman code 42" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN42" description="Huffman length 42" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE43" description="Huffman code 43" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN43" description="Huffman length 43" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_22" description="JPEG Huffman encoder AC0" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE44" description="Huffman code 44" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN44" description="Huffman length 44" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE45" description="Huffman code 45" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN45" description="Huffman length 45" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_23" description="JPEG Huffman encoder AC0" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE46" description="Huffman code 46" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN46" description="Huffman length 46" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE47" description="Huffman code 47" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN47" description="Huffman length 47" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_24" description="JPEG Huffman encoder AC0" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE48" description="Huffman code 48" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN48" description="Huffman length 48" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE49" description="Huffman code 49" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN49" description="Huffman length 49" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_25" description="JPEG Huffman encoder AC0" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE50" description="Huffman code 50" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN50" description="Huffman length 50" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE51" description="Huffman code 51" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN51" description="Huffman length 51" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_26" description="JPEG Huffman encoder AC0" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE52" description="Huffman code 52" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN52" description="Huffman length 52" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE53" description="Huffman code 53" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN53" description="Huffman length 53" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_27" description="JPEG Huffman encoder AC0" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE54" description="Huffman code 54" start="0" size="8" access="Read/Write" />
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+      <BitField name="HCODE55" description="Huffman code 55" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN55" description="Huffman length 55" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_28" description="JPEG Huffman encoder AC0" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE56" description="Huffman code 56" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN56" description="Huffman length 56" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE57" description="Huffman code 57" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN57" description="Huffman length 57" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_29" description="JPEG Huffman encoder AC0" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE59" description="Huffman code 59" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN59" description="Huffman length 59" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_30" description="JPEG Huffman encoder AC0" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE60" description="Huffman code 60" start="0" size="8" access="Read/Write" />
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+      <BitField name="HCODE61" description="Huffman code 61" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN61" description="Huffman length 61" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_31" description="JPEG Huffman encoder AC0" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE63" description="Huffman code 63" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN63" description="Huffman length 63" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_32" description="JPEG Huffman encoder AC0" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN65" description="Huffman length 65" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_33" description="JPEG Huffman encoder AC0" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE67" description="Huffman code 67" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN67" description="Huffman length 67" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_34" description="JPEG Huffman encoder AC0" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE68" description="Huffman code 68" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN68" description="Huffman length 68" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE69" description="Huffman code 69" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN69" description="Huffman length 69" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_35" description="JPEG Huffman encoder AC0" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN70" description="Huffman length 70" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE71" description="Huffman code 71" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN71" description="Huffman length 71" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_36" description="JPEG Huffman encoder AC0" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN72" description="Huffman length 72" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE73" description="Huffman code 73" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN73" description="Huffman length 73" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_37" description="JPEG Huffman encoder AC0" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN74" description="Huffman length 74" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE75" description="Huffman code 75" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN75" description="Huffman length 75" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_38" description="JPEG Huffman encoder AC0" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN77" description="Huffman length 77" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_39" description="JPEG Huffman encoder AC0" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN79" description="Huffman length 79" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_40" description="JPEG Huffman encoder AC0" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN81" description="Huffman length 81" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_41" description="JPEG Huffman encoder AC0" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN82" description="Huffman length 82" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE83" description="Huffman code 83" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN83" description="Huffman length 83" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_42" description="JPEG Huffman encoder AC0" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE85" description="Huffman code 85" start="16" size="8" access="Read/Write" />
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_43" description="JPEG Huffman encoder AC0" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN86" description="Huffman length 86" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE87" description="Huffman code 87" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN87" description="Huffman length 87" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_44" description="JPEG Huffman encoder AC0" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN89" description="Huffman length 89" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_45" description="JPEG Huffman encoder AC0" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN91" description="Huffman length 91" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_46" description="JPEG Huffman encoder AC0" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE93" description="Huffman code 93" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN93" description="Huffman length 93" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_47" description="JPEG Huffman encoder AC0" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN95" description="Huffman length 95" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN97" description="Huffman length 97" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_49" description="JPEG Huffman encoder AC0" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+      <BitField name="HLEN101" description="Huffman length 101" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN103" description="Huffman length 103" start="24" size="4" access="Read/Write" />
+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+      <BitField name="HLEN113" description="Huffman length 113" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_57" description="JPEG Huffman encoder AC0" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN115" description="Huffman length 115" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN173" description="Huffman length 173" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_87" description="JPEG Huffman encoder AC1" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE174" description="Huffman code 174" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN174" description="Huffman length 174" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE175" description="Huffman code 175" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN175" description="Huffman length 175" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_0" description="JPEG Huffman encoder DC0" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_1" description="JPEG Huffman encoder DC0" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_2" description="JPEG Huffman encoder DC0" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_3" description="JPEG Huffman encoder DC0" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_4" description="JPEG Huffman encoder DC0" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_5" description="JPEG Huffman encoder DC0" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_6" description="JPEG Huffman encoder DC0" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_7" description="JPEG Huffman encoder DC0" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_0" description="JPEG Huffman encoder DC1" start="+0x7E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_1" description="JPEG Huffman encoder DC1" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_2" description="JPEG Huffman encoder DC1" start="+0x7E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_3" description="JPEG Huffman encoder DC1" start="+0x7EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_4" description="JPEG Huffman encoder DC1" start="+0x7F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_5" description="JPEG Huffman encoder DC1" start="+0x7F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_6" description="JPEG Huffman encoder DC1" start="+0x7F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_7" description="JPEG Huffman encoder DC1" start="+0x7FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="JPEG_S" description="JPEG codec" start="0x58023000">
+    <Register name="JPEG_CONFR0" description="JPEG codec control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="START" description="Start" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Stop/abort" start="0x0" />
+        <Enum name="B_0x1" description="Start" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_CONFR1" description="JPEG codec configuration register 1" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NF" description="Number of color components" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Grayscale (1 color component)" start="0x0" />
+        <Enum name="B_0x1" description="- (2 color components)" start="0x1" />
+        <Enum name="B_0x2" description="YUV or RGB (3 color components)" start="0x2" />
+        <Enum name="B_0x3" description="CMYK (4 color components)" start="0x3" />
+      </BitField>
+      <BitField name="DE" description="Codec operation as coder or decoder" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Code" start="0x0" />
+        <Enum name="B_0x1" description="Decode" start="0x1" />
+      </BitField>
+      <BitField name="COLSPACE" description="Color space" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Grayscale (1 quantization table)" start="0x0" />
+        <Enum name="B_0x1" description="YUV (2 quantization tables)" start="0x1" />
+        <Enum name="B_0x2" description="RGB (3 quantization tables)" start="0x2" />
+        <Enum name="B_0x3" description="CMYK (4 quantization tables)" start="0x3" />
+      </BitField>
+      <BitField name="NS" description="Number of components for scan" start="6" size="2" access="Read/Write" />
+      <BitField name="HDR" description="Header processing" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="YSIZE" description="Y Size" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR2" description="JPEG codec configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NMCU" description="Number of MCUs" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR3" description="JPEG codec configuration register 3" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSIZE" description="X size" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR4" description="JPEG codec configuration register 4" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR5" description="JPEG codec configuration register 5" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR6" description="JPEG codec configuration register 6" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CONFR7" description="JPEG codec configuration register 7" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HD" description="Huffman DC" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman DC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman DC table 1" start="0x1" />
+      </BitField>
+      <BitField name="HA" description="Huffman AC" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Huffman AC table 0" start="0x0" />
+        <Enum name="B_0x1" description="Huffman AC table 1" start="0x1" />
+      </BitField>
+      <BitField name="QT" description="Quantization table" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Quantization table 0" start="0x0" />
+        <Enum name="B_0x1" description="Quantization table 1" start="0x1" />
+        <Enum name="B_0x2" description="Quantization table 2" start="0x2" />
+        <Enum name="B_0x3" description="Quantization table 3" start="0x3" />
+      </BitField>
+      <BitField name="NB" description="Number of blocks" start="4" size="4" access="Read/Write" />
+      <BitField name="VSF" description="Vertical sampling factor" start="8" size="4" access="Read/Write" />
+      <BitField name="HSF" description="Horizontal sampling factor" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_CR" description="JPEG control register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JCEN" description="JPEG core enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (internal registers are reset)." start="0x0" />
+        <Enum name="B_0x1" description="Enabled (internal registers are accessible)." start="0x1" />
+      </BitField>
+      <BitField name="IFTIE" description="Input FIFO threshold interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFNFIE" description="Input FIFO not full interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="OFTIE" description="Output FIFO threshold interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="OFNEIE" description="Output FIFO not empty interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of conversion interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="HPDIE" description="Header parsing done interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMAEN" description="Input DMA enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="ODMAEN" description="Output DMA enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled" start="0x0" />
+        <Enum name="B_0x1" description="Enabled" start="0x1" />
+      </BitField>
+      <BitField name="IFF" description="Input FIFO flush" start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Input FIFO is flushed" start="0x1" />
+      </BitField>
+      <BitField name="OFF" description="Output FIFO flush" start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Output FIFO is flushed" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_SR" description="JPEG status register" start="+0x034" size="4" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
+      <BitField name="IFTF" description="Input FIFO threshold flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="At or above threshold" start="0x0" />
+        <Enum name="B_0x1" description="Below threshold." start="0x1" />
+      </BitField>
+      <BitField name="IFNFF" description="Input FIFO not full flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Full" start="0x0" />
+        <Enum name="B_0x1" description="Not full" start="0x1" />
+      </BitField>
+      <BitField name="OFTF" description="Output FIFO threshold flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Below threshold" start="0x0" />
+        <Enum name="B_0x1" description="At or above threshold" start="0x1" />
+      </BitField>
+      <BitField name="OFNEF" description="Output FIFO not empty flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Empty (data not available)" start="0x0" />
+        <Enum name="B_0x1" description="Not empty (data available)" start="0x1" />
+      </BitField>
+      <BitField name="EOCF" description="End of conversion flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="HPDF" description="Header parsing done flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="COF" description="Codec operation flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not in progress" start="0x0" />
+        <Enum name="B_0x1" description="In progress" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_CFR" description="JPEG clear flag register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEOCF" description="Clear end of conversion flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear" start="0x1" />
+      </BitField>
+      <BitField name="CHPDF" description="Clear header parsing done flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Clear" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="JPEG_DIR" description="JPEG data input register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAIN" description="Data input FIFO" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="JPEG_DOR" description="JPEG data output register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATAOUT" description="Data output FIFO" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="JPEG_QMEM0_0" description="JPEG quantization memory 0" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF0" description="Quantization coefficient 0" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF1" description="Quantization coefficient 1" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF2" description="Quantization coefficient 2" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF3" description="Quantization coefficient 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_1" description="JPEG quantization memory 0" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF4" description="Quantization coefficient 4" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF5" description="Quantization coefficient 5" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF6" description="Quantization coefficient 6" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF7" description="Quantization coefficient 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_2" description="JPEG quantization memory 0" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF8" description="Quantization coefficient 8" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF9" description="Quantization coefficient 9" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF10" description="Quantization coefficient 10" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF11" description="Quantization coefficient 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_3" description="JPEG quantization memory 0" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF12" description="Quantization coefficient 12" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF13" description="Quantization coefficient 13" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF14" description="Quantization coefficient 14" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF15" description="Quantization coefficient 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_4" description="JPEG quantization memory 0" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF16" description="Quantization coefficient 16" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF17" description="Quantization coefficient 17" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_5" description="JPEG quantization memory 0" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF20" description="Quantization coefficient 20" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF21" description="Quantization coefficient 21" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_6" description="JPEG quantization memory 0" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_7" description="JPEG quantization memory 0" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_8" description="JPEG quantization memory 0" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF34" description="Quantization coefficient 34" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_9" description="JPEG quantization memory 0" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_10" description="JPEG quantization memory 0" start="+0x78" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_11" description="JPEG quantization memory 0" start="+0x7C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_12" description="JPEG quantization memory 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF50" description="Quantization coefficient 50" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF51" description="Quantization coefficient 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_13" description="JPEG quantization memory 0" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF53" description="Quantization coefficient 53" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF54" description="Quantization coefficient 54" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF55" description="Quantization coefficient 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_14" description="JPEG quantization memory 0" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF58" description="Quantization coefficient 58" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF59" description="Quantization coefficient 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM0_15" description="JPEG quantization memory 0" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF62" description="Quantization coefficient 62" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF63" description="Quantization coefficient 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_0" description="JPEG quantization memory 1" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF1" description="Quantization coefficient 1" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF2" description="Quantization coefficient 2" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF3" description="Quantization coefficient 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_1" description="JPEG quantization memory 1" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF4" description="Quantization coefficient 4" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF5" description="Quantization coefficient 5" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF6" description="Quantization coefficient 6" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF7" description="Quantization coefficient 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_2" description="JPEG quantization memory 1" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF8" description="Quantization coefficient 8" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF9" description="Quantization coefficient 9" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF10" description="Quantization coefficient 10" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF11" description="Quantization coefficient 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_3" description="JPEG quantization memory 1" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF12" description="Quantization coefficient 12" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF13" description="Quantization coefficient 13" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF14" description="Quantization coefficient 14" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF15" description="Quantization coefficient 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_4" description="JPEG quantization memory 1" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF16" description="Quantization coefficient 16" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF17" description="Quantization coefficient 17" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_5" description="JPEG quantization memory 1" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF20" description="Quantization coefficient 20" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF21" description="Quantization coefficient 21" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_6" description="JPEG quantization memory 1" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF24" description="Quantization coefficient 24" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_7" description="JPEG quantization memory 1" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_8" description="JPEG quantization memory 1" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF32" description="Quantization coefficient 32" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF33" description="Quantization coefficient 33" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF34" description="Quantization coefficient 34" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_9" description="JPEG quantization memory 1" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_10" description="JPEG quantization memory 1" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF40" description="Quantization coefficient 40" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF41" description="Quantization coefficient 41" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_11" description="JPEG quantization memory 1" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF44" description="Quantization coefficient 44" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_12" description="JPEG quantization memory 1" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF48" description="Quantization coefficient 48" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF49" description="Quantization coefficient 49" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF50" description="Quantization coefficient 50" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF51" description="Quantization coefficient 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_13" description="JPEG quantization memory 1" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF52" description="Quantization coefficient 52" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF53" description="Quantization coefficient 53" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF54" description="Quantization coefficient 54" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF55" description="Quantization coefficient 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_14" description="JPEG quantization memory 1" start="+0xC8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF56" description="Quantization coefficient 56" start="0" size="8" access="Read/Write" />
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+      <BitField name="QCOEF58" description="Quantization coefficient 58" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF59" description="Quantization coefficient 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM1_15" description="JPEG quantization memory 1" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF62" description="Quantization coefficient 62" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF63" description="Quantization coefficient 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_0" description="JPEG quantization memory 2" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF3" description="Quantization coefficient 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_1" description="JPEG quantization memory 2" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF4" description="Quantization coefficient 4" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF5" description="Quantization coefficient 5" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF6" description="Quantization coefficient 6" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF7" description="Quantization coefficient 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_2" description="JPEG quantization memory 2" start="+0xD8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF8" description="Quantization coefficient 8" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF9" description="Quantization coefficient 9" start="8" size="8" access="Read/Write" />
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+      <BitField name="QCOEF11" description="Quantization coefficient 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_3" description="JPEG quantization memory 2" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF12" description="Quantization coefficient 12" start="0" size="8" access="Read/Write" />
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+      <BitField name="QCOEF14" description="Quantization coefficient 14" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF15" description="Quantization coefficient 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_4" description="JPEG quantization memory 2" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF16" description="Quantization coefficient 16" start="0" size="8" access="Read/Write" />
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+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF20" description="Quantization coefficient 20" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF21" description="Quantization coefficient 21" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF24" description="Quantization coefficient 24" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_7" description="JPEG quantization memory 2" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF29" description="Quantization coefficient 29" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_8" description="JPEG quantization memory 2" start="+0xF0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF32" description="Quantization coefficient 32" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF33" description="Quantization coefficient 33" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF34" description="Quantization coefficient 34" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_9" description="JPEG quantization memory 2" start="+0xF4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF37" description="Quantization coefficient 37" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_10" description="JPEG quantization memory 2" start="+0xF8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM2_12" description="JPEG quantization memory 2" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF49" description="Quantization coefficient 49" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF50" description="Quantization coefficient 50" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF51" description="Quantization coefficient 51" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF54" description="Quantization coefficient 54" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF55" description="Quantization coefficient 55" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF57" description="Quantization coefficient 57" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF58" description="Quantization coefficient 58" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF59" description="Quantization coefficient 59" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF62" description="Quantization coefficient 62" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF63" description="Quantization coefficient 63" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF3" description="Quantization coefficient 3" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF6" description="Quantization coefficient 6" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF7" description="Quantization coefficient 7" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF10" description="Quantization coefficient 10" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF11" description="Quantization coefficient 11" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF14" description="Quantization coefficient 14" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF15" description="Quantization coefficient 15" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF17" description="Quantization coefficient 17" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF18" description="Quantization coefficient 18" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF19" description="Quantization coefficient 19" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF22" description="Quantization coefficient 22" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF23" description="Quantization coefficient 23" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF25" description="Quantization coefficient 25" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF26" description="Quantization coefficient 26" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF27" description="Quantization coefficient 27" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF30" description="Quantization coefficient 30" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF31" description="Quantization coefficient 31" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF35" description="Quantization coefficient 35" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF37" description="Quantization coefficient 37" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF38" description="Quantization coefficient 38" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF39" description="Quantization coefficient 39" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF41" description="Quantization coefficient 41" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF42" description="Quantization coefficient 42" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF43" description="Quantization coefficient 43" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF44" description="Quantization coefficient 44" start="0" size="8" access="Read/Write" />
+      <BitField name="QCOEF45" description="Quantization coefficient 45" start="8" size="8" access="Read/Write" />
+      <BitField name="QCOEF46" description="Quantization coefficient 46" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF47" description="Quantization coefficient 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_12" description="JPEG quantization memory 3" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="QCOEF48" description="Quantization coefficient 48" start="0" size="8" access="Read/Write" />
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+      <BitField name="QCOEF50" description="Quantization coefficient 50" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF51" description="Quantization coefficient 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_13" description="JPEG quantization memory 3" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF54" description="Quantization coefficient 54" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF55" description="Quantization coefficient 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_QMEM3_14" description="JPEG quantization memory 3" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="QCOEF58" description="Quantization coefficient 58" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF59" description="Quantization coefficient 59" start="24" size="8" access="Read/Write" />
+    </Register>
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+      <BitField name="QCOEF62" description="Quantization coefficient 62" start="16" size="8" access="Read/Write" />
+      <BitField name="QCOEF63" description="Quantization coefficient 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFMIN0_0" description="JPEG Huffman min" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+    </Register>
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+      <BitField name="DATA0" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA1" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
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+      <BitField name="DATA2" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="32" access="Read/Write" />
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+    </Register>
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+      <BitField name="DATA3" description="Minimum Huffman value" start="0" size="4" access="Read/Write" />
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+    <Register name="JPEG_HUFFBASE0" description="JPEG Huffman base" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA3" description="Data 3" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE2" description="JPEG Huffman base" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA5" description="Data 5" start="16" size="9" access="Read/Write" />
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+      <BitField name="DATA7" description="Data 7" start="16" size="9" access="Read/Write" />
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+    <Register name="JPEG_HUFFBASE4" description="JPEG Huffman base" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA9" description="Data 9" start="16" size="9" access="Read/Write" />
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+    <Register name="JPEG_HUFFBASE5" description="JPEG Huffman base" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="DATA11" description="Data 11" start="16" size="9" access="Read/Write" />
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+      <BitField name="DATA13" description="Data 13" start="16" size="9" access="Read/Write" />
+    </Register>
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+      <BitField name="DATA15" description="Data 15" start="16" size="9" access="Read/Write" />
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+    <Register name="JPEG_HUFFBASE8" description="JPEG Huffman base" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Data 16" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA17" description="Data 17" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE9" description="JPEG Huffman base" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA18" description="Data 18" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA19" description="Data 19" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE10" description="JPEG Huffman base" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Data 20" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA21" description="Data 21" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE11" description="JPEG Huffman base" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA22" description="Data 22" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA23" description="Data 23" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE12" description="JPEG Huffman base" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Data 24" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA25" description="Data 25" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE13" description="JPEG Huffman base" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA26" description="Data 26" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA27" description="Data 27" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE14" description="JPEG Huffman base" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Data 28" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA29" description="Data 29" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE15" description="JPEG Huffman base" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA30" description="Data 30" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA31" description="Data 31" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE16" description="JPEG Huffman base" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Data 32" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA33" description="Data 33" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE17" description="JPEG Huffman base" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA34" description="Data 34" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA35" description="Data 35" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE18" description="JPEG Huffman base" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Data 36" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA37" description="Data 37" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE19" description="JPEG Huffman base" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA38" description="Data 38" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA39" description="Data 39" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE20" description="JPEG Huffman base" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Data 40" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA41" description="Data 41" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE21" description="JPEG Huffman base" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA42" description="Data 42" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA43" description="Data 43" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE22" description="JPEG Huffman base" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Data 44" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA45" description="Data 45" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE23" description="JPEG Huffman base" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA46" description="Data 46" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA47" description="Data 47" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE24" description="JPEG Huffman base" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Data 48" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA49" description="Data 49" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE25" description="JPEG Huffman base" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA50" description="Data 50" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA51" description="Data 51" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE26" description="JPEG Huffman base" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA52" description="Data 52" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA53" description="Data 53" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE27" description="JPEG Huffman base" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA54" description="Data 54" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA55" description="Data 55" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE28" description="JPEG Huffman base" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA56" description="Data 56" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA57" description="Data 57" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE29" description="JPEG Huffman base" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA58" description="Data 58" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA59" description="Data 59" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE30" description="JPEG Huffman base" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA60" description="Data 60" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA61" description="Data 61" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFBASE31" description="JPEG Huffman base" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA62" description="Data 62" start="0" size="9" access="Read/Write" />
+      <BitField name="DATA63" description="Data 63" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB0" description="JPEG Huffman symbol" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Data 0" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA1" description="Data 1" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA2" description="Data 2" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA3" description="Data 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB1" description="JPEG Huffman symbol" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA4" description="Data 4" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA5" description="Data 5" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA6" description="Data 6" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA7" description="Data 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB2" description="JPEG Huffman symbol" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA8" description="Data 8" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA9" description="Data 9" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA10" description="Data 10" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA11" description="Data 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB3" description="JPEG Huffman symbol" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA12" description="Data 12" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA13" description="Data 13" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA14" description="Data 14" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA15" description="Data 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB4" description="JPEG Huffman symbol" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Data 16" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA17" description="Data 17" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA18" description="Data 18" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA19" description="Data 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB5" description="JPEG Huffman symbol" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Data 20" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA21" description="Data 21" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA22" description="Data 22" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA23" description="Data 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB6" description="JPEG Huffman symbol" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Data 24" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA25" description="Data 25" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA26" description="Data 26" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA27" description="Data 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB7" description="JPEG Huffman symbol" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Data 28" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA29" description="Data 29" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA30" description="Data 30" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA31" description="Data 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB8" description="JPEG Huffman symbol" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Data 32" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA33" description="Data 33" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA34" description="Data 34" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA35" description="Data 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB9" description="JPEG Huffman symbol" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Data 36" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA37" description="Data 37" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA38" description="Data 38" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA39" description="Data 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB10" description="JPEG Huffman symbol" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Data 40" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA41" description="Data 41" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA42" description="Data 42" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA43" description="Data 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB11" description="JPEG Huffman symbol" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Data 44" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA45" description="Data 45" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA46" description="Data 46" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA47" description="Data 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB12" description="JPEG Huffman symbol" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Data 48" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA49" description="Data 49" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA50" description="Data 50" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA51" description="Data 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB13" description="JPEG Huffman symbol" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA52" description="Data 52" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA53" description="Data 53" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA54" description="Data 54" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA55" description="Data 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB14" description="JPEG Huffman symbol" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA56" description="Data 56" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA57" description="Data 57" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA58" description="Data 58" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA59" description="Data 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB15" description="JPEG Huffman symbol" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA60" description="Data 60" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA61" description="Data 61" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA62" description="Data 62" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA63" description="Data 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB16" description="JPEG Huffman symbol" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA64" description="Data 64" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA65" description="Data 65" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA66" description="Data 66" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA67" description="Data 67" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB17" description="JPEG Huffman symbol" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA68" description="Data 68" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA69" description="Data 69" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA70" description="Data 70" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA71" description="Data 71" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB18" description="JPEG Huffman symbol" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA72" description="Data 72" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA73" description="Data 73" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA74" description="Data 74" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA75" description="Data 75" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB19" description="JPEG Huffman symbol" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA76" description="Data 76" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA77" description="Data 77" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA78" description="Data 78" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA79" description="Data 79" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB20" description="JPEG Huffman symbol" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA80" description="Data 80" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA81" description="Data 81" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA82" description="Data 82" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA83" description="Data 83" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB21" description="JPEG Huffman symbol" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA84" description="Data 84" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA85" description="Data 85" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA86" description="Data 86" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA87" description="Data 87" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB22" description="JPEG Huffman symbol" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA88" description="Data 88" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA89" description="Data 89" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA90" description="Data 90" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA91" description="Data 91" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB23" description="JPEG Huffman symbol" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA92" description="Data 92" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA93" description="Data 93" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA94" description="Data 94" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA95" description="Data 95" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB24" description="JPEG Huffman symbol" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA96" description="Data 96" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA97" description="Data 97" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA98" description="Data 98" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA99" description="Data 99" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB25" description="JPEG Huffman symbol" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA100" description="Data 100" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA101" description="Data 101" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA102" description="Data 102" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA103" description="Data 103" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB26" description="JPEG Huffman symbol" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA104" description="Data 104" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA105" description="Data 105" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA106" description="Data 106" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA107" description="Data 107" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB27" description="JPEG Huffman symbol" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA108" description="Data 108" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA109" description="Data 109" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA110" description="Data 110" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA111" description="Data 111" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB28" description="JPEG Huffman symbol" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA112" description="Data 112" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA113" description="Data 113" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA114" description="Data 114" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA115" description="Data 115" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB29" description="JPEG Huffman symbol" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA116" description="Data 116" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA117" description="Data 117" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA118" description="Data 118" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA119" description="Data 119" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB30" description="JPEG Huffman symbol" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA120" description="Data 120" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA121" description="Data 121" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA122" description="Data 122" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA123" description="Data 123" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB31" description="JPEG Huffman symbol" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA124" description="Data 124" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA125" description="Data 125" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA126" description="Data 126" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA127" description="Data 127" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB32" description="JPEG Huffman symbol" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA128" description="Data 128" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA129" description="Data 129" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA130" description="Data 130" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA131" description="Data 131" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB33" description="JPEG Huffman symbol" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA132" description="Data 132" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA133" description="Data 133" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA134" description="Data 134" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA135" description="Data 135" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB34" description="JPEG Huffman symbol" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA136" description="Data 136" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA137" description="Data 137" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA138" description="Data 138" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA139" description="Data 139" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB35" description="JPEG Huffman symbol" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA140" description="Data 140" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA141" description="Data 141" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA142" description="Data 142" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA143" description="Data 143" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB36" description="JPEG Huffman symbol" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA144" description="Data 144" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA145" description="Data 145" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA146" description="Data 146" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA147" description="Data 147" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB37" description="JPEG Huffman symbol" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA148" description="Data 148" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA149" description="Data 149" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA150" description="Data 150" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA151" description="Data 151" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB38" description="JPEG Huffman symbol" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA152" description="Data 152" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA153" description="Data 153" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA154" description="Data 154" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA155" description="Data 155" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB39" description="JPEG Huffman symbol" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA156" description="Data 156" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA157" description="Data 157" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA158" description="Data 158" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA159" description="Data 159" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB40" description="JPEG Huffman symbol" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA160" description="Data 160" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA161" description="Data 161" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA162" description="Data 162" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA163" description="Data 163" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB41" description="JPEG Huffman symbol" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA164" description="Data 164" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA165" description="Data 165" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA166" description="Data 166" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA167" description="Data 167" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB42" description="JPEG Huffman symbol" start="+0x2B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA168" description="Data 168" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA169" description="Data 169" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA170" description="Data 170" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA171" description="Data 171" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB43" description="JPEG Huffman symbol" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA172" description="Data 172" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA173" description="Data 173" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA174" description="Data 174" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA175" description="Data 175" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB44" description="JPEG Huffman symbol" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA176" description="Data 176" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA177" description="Data 177" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA178" description="Data 178" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA179" description="Data 179" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB45" description="JPEG Huffman symbol" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA180" description="Data 180" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA181" description="Data 181" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA182" description="Data 182" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA183" description="Data 183" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB46" description="JPEG Huffman symbol" start="+0x2C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA184" description="Data 184" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA185" description="Data 185" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA186" description="Data 186" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA187" description="Data 187" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB47" description="JPEG Huffman symbol" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA188" description="Data 188" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA189" description="Data 189" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA190" description="Data 190" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA191" description="Data 191" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB48" description="JPEG Huffman symbol" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA192" description="Data 192" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA193" description="Data 193" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA194" description="Data 194" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA195" description="Data 195" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB49" description="JPEG Huffman symbol" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA196" description="Data 196" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA197" description="Data 197" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA198" description="Data 198" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA199" description="Data 199" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB50" description="JPEG Huffman symbol" start="+0x2D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA200" description="Data 200" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA201" description="Data 201" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA202" description="Data 202" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA203" description="Data 203" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB51" description="JPEG Huffman symbol" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA204" description="Data 204" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA205" description="Data 205" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA206" description="Data 206" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA207" description="Data 207" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB52" description="JPEG Huffman symbol" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA208" description="Data 208" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA209" description="Data 209" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA210" description="Data 210" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA211" description="Data 211" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB53" description="JPEG Huffman symbol" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA212" description="Data 212" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA214" description="Data 214" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA215" description="Data 215" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB54" description="JPEG Huffman symbol" start="+0x2E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA216" description="Data 216" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA217" description="Data 217" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA218" description="Data 218" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA219" description="Data 219" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB55" description="JPEG Huffman symbol" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA220" description="Data 220" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA221" description="Data 221" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA222" description="Data 222" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA223" description="Data 223" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB56" description="JPEG Huffman symbol" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA224" description="Data 224" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA225" description="Data 225" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA226" description="Data 226" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA227" description="Data 227" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB57" description="JPEG Huffman symbol" start="+0x2F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA228" description="Data 228" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA230" description="Data 230" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA231" description="Data 231" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB58" description="JPEG Huffman symbol" start="+0x2F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA232" description="Data 232" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA233" description="Data 233" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA234" description="Data 234" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA235" description="Data 235" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB59" description="JPEG Huffman symbol" start="+0x2FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA236" description="Data 236" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA237" description="Data 237" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA238" description="Data 238" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA239" description="Data 239" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB60" description="JPEG Huffman symbol" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA240" description="Data 240" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA241" description="Data 241" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA242" description="Data 242" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA243" description="Data 243" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB61" description="JPEG Huffman symbol" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA244" description="Data 244" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA245" description="Data 245" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA246" description="Data 246" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA247" description="Data 247" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB62" description="JPEG Huffman symbol" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA248" description="Data 248" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA249" description="Data 249" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA250" description="Data 250" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA251" description="Data 251" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB63" description="JPEG Huffman symbol" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA252" description="Data 252" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA254" description="Data 254" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA255" description="Data 255" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB64" description="JPEG Huffman symbol" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA256" description="Data 256" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA257" description="Data 257" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA258" description="Data 258" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA259" description="Data 259" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB65" description="JPEG Huffman symbol" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA260" description="Data 260" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA261" description="Data 261" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA262" description="Data 262" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA263" description="Data 263" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB66" description="JPEG Huffman symbol" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA264" description="Data 264" start="0" size="8" access="Read/Write" />
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+      <BitField name="DATA266" description="Data 266" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA267" description="Data 267" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB67" description="JPEG Huffman symbol" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA268" description="Data 268" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA269" description="Data 269" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA270" description="Data 270" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA271" description="Data 271" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB68" description="JPEG Huffman symbol" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA272" description="Data 272" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA273" description="Data 273" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA274" description="Data 274" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA275" description="Data 275" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB69" description="JPEG Huffman symbol" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA276" description="Data 276" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA277" description="Data 277" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA278" description="Data 278" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA279" description="Data 279" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB70" description="JPEG Huffman symbol" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA280" description="Data 280" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA281" description="Data 281" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA282" description="Data 282" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA283" description="Data 283" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB71" description="JPEG Huffman symbol" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA284" description="Data 284" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA285" description="Data 285" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA286" description="Data 286" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA287" description="Data 287" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB72" description="JPEG Huffman symbol" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA288" description="Data 288" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA289" description="Data 289" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA290" description="Data 290" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA291" description="Data 291" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB73" description="JPEG Huffman symbol" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA292" description="Data 292" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA293" description="Data 293" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA294" description="Data 294" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA295" description="Data 295" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB74" description="JPEG Huffman symbol" start="+0x338" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA296" description="Data 296" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA297" description="Data 297" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA298" description="Data 298" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA299" description="Data 299" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB75" description="JPEG Huffman symbol" start="+0x33C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA300" description="Data 300" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA301" description="Data 301" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA302" description="Data 302" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA303" description="Data 303" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB76" description="JPEG Huffman symbol" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA304" description="Data 304" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA305" description="Data 305" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA306" description="Data 306" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA307" description="Data 307" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB77" description="JPEG Huffman symbol" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA308" description="Data 308" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA309" description="Data 309" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA310" description="Data 310" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA311" description="Data 311" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB78" description="JPEG Huffman symbol" start="+0x348" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA312" description="Data 312" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA313" description="Data 313" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA314" description="Data 314" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA315" description="Data 315" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB79" description="JPEG Huffman symbol" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA316" description="Data 316" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA317" description="Data 317" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA318" description="Data 318" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA319" description="Data 319" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB80" description="JPEG Huffman symbol" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA320" description="Data 320" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA321" description="Data 321" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA322" description="Data 322" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA323" description="Data 323" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB81" description="JPEG Huffman symbol" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA324" description="Data 324" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA325" description="Data 325" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA326" description="Data 326" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA327" description="Data 327" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB82" description="JPEG Huffman symbol" start="+0x358" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA328" description="Data 328" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA329" description="Data 329" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA330" description="Data 330" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA331" description="Data 331" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFSYMB83" description="JPEG Huffman symbol" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA332" description="Data 332" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA333" description="Data 333" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA334" description="Data 334" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA335" description="Data 335" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM0" description="JPEG DHT memory" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA0" description="Huffman table data 0" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA1" description="Huffman table data 1" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA2" description="Huffman table data 2" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA3" description="Huffman table data 3" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM1" description="JPEG DHT memory" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA4" description="Huffman table data 4" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA5" description="Huffman table data 5" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA6" description="Huffman table data 6" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA7" description="Huffman table data 7" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM2" description="JPEG DHT memory" start="+0x368" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA8" description="Huffman table data 8" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA9" description="Huffman table data 9" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA10" description="Huffman table data 10" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA11" description="Huffman table data 11" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM3" description="JPEG DHT memory" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA12" description="Huffman table data 12" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA13" description="Huffman table data 13" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA14" description="Huffman table data 14" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA15" description="Huffman table data 15" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM4" description="JPEG DHT memory" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA16" description="Huffman table data 16" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA17" description="Huffman table data 17" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA18" description="Huffman table data 18" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA19" description="Huffman table data 19" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM5" description="JPEG DHT memory" start="+0x374" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA20" description="Huffman table data 20" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA21" description="Huffman table data 21" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA22" description="Huffman table data 22" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA23" description="Huffman table data 23" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM6" description="JPEG DHT memory" start="+0x378" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA24" description="Huffman table data 24" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA25" description="Huffman table data 25" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA26" description="Huffman table data 26" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA27" description="Huffman table data 27" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM7" description="JPEG DHT memory" start="+0x37C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA28" description="Huffman table data 28" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA29" description="Huffman table data 29" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA30" description="Huffman table data 30" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA31" description="Huffman table data 31" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM8" description="JPEG DHT memory" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA32" description="Huffman table data 32" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA33" description="Huffman table data 33" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA34" description="Huffman table data 34" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA35" description="Huffman table data 35" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM9" description="JPEG DHT memory" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA36" description="Huffman table data 36" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA37" description="Huffman table data 37" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA38" description="Huffman table data 38" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA39" description="Huffman table data 39" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM10" description="JPEG DHT memory" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA40" description="Huffman table data 40" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA41" description="Huffman table data 41" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA42" description="Huffman table data 42" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA43" description="Huffman table data 43" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM11" description="JPEG DHT memory" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA44" description="Huffman table data 44" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA45" description="Huffman table data 45" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA46" description="Huffman table data 46" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA47" description="Huffman table data 47" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM12" description="JPEG DHT memory" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA48" description="Huffman table data 48" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA49" description="Huffman table data 49" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA50" description="Huffman table data 50" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA51" description="Huffman table data 51" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM13" description="JPEG DHT memory" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA52" description="Huffman table data 52" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA53" description="Huffman table data 53" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA54" description="Huffman table data 54" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA55" description="Huffman table data 55" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM14" description="JPEG DHT memory" start="+0x398" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA56" description="Huffman table data 56" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA57" description="Huffman table data 57" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA58" description="Huffman table data 58" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA59" description="Huffman table data 59" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM15" description="JPEG DHT memory" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA60" description="Huffman table data 60" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA61" description="Huffman table data 61" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA62" description="Huffman table data 62" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA63" description="Huffman table data 63" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM16" description="JPEG DHT memory" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA64" description="Huffman table data 64" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA65" description="Huffman table data 65" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA66" description="Huffman table data 66" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA67" description="Huffman table data 67" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM17" description="JPEG DHT memory" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA68" description="Huffman table data 68" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA69" description="Huffman table data 69" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA70" description="Huffman table data 70" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA71" description="Huffman table data 71" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM18" description="JPEG DHT memory" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA72" description="Huffman table data 72" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA73" description="Huffman table data 73" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA74" description="Huffman table data 74" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA75" description="Huffman table data 75" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM19" description="JPEG DHT memory" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA76" description="Huffman table data 76" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA77" description="Huffman table data 77" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA78" description="Huffman table data 78" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA79" description="Huffman table data 79" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM20" description="JPEG DHT memory" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA80" description="Huffman table data 80" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA81" description="Huffman table data 81" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA82" description="Huffman table data 82" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA83" description="Huffman table data 83" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM21" description="JPEG DHT memory" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA84" description="Huffman table data 84" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA85" description="Huffman table data 85" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA86" description="Huffman table data 86" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA87" description="Huffman table data 87" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM22" description="JPEG DHT memory" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA88" description="Huffman table data 88" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA89" description="Huffman table data 89" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA90" description="Huffman table data 90" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA91" description="Huffman table data 91" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM23" description="JPEG DHT memory" start="+0x3BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA92" description="Huffman table data 92" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA93" description="Huffman table data 93" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA94" description="Huffman table data 94" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA95" description="Huffman table data 95" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM24" description="JPEG DHT memory" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA96" description="Huffman table data 96" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA97" description="Huffman table data 97" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA98" description="Huffman table data 98" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA99" description="Huffman table data 99" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM25" description="JPEG DHT memory" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA100" description="Huffman table data 100" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA101" description="Huffman table data 101" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA102" description="Huffman table data 102" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA103" description="Huffman table data 103" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM26" description="JPEG DHT memory" start="+0x3C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA104" description="Huffman table data 104" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA105" description="Huffman table data 105" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA106" description="Huffman table data 106" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA107" description="Huffman table data 107" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM27" description="JPEG DHT memory" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA108" description="Huffman table data 108" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA109" description="Huffman table data 109" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA110" description="Huffman table data 110" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA111" description="Huffman table data 111" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM28" description="JPEG DHT memory" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA112" description="Huffman table data 112" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA113" description="Huffman table data 113" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA114" description="Huffman table data 114" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA115" description="Huffman table data 115" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM29" description="JPEG DHT memory" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA116" description="Huffman table data 116" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA117" description="Huffman table data 117" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA118" description="Huffman table data 118" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA119" description="Huffman table data 119" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM30" description="JPEG DHT memory" start="+0x3D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA120" description="Huffman table data 120" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA121" description="Huffman table data 121" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA122" description="Huffman table data 122" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA123" description="Huffman table data 123" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM31" description="JPEG DHT memory" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA124" description="Huffman table data 124" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA125" description="Huffman table data 125" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA126" description="Huffman table data 126" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA127" description="Huffman table data 127" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM32" description="JPEG DHT memory" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA128" description="Huffman table data 128" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA129" description="Huffman table data 129" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA130" description="Huffman table data 130" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA131" description="Huffman table data 131" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM33" description="JPEG DHT memory" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA132" description="Huffman table data 132" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA133" description="Huffman table data 133" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA134" description="Huffman table data 134" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA135" description="Huffman table data 135" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM34" description="JPEG DHT memory" start="+0x3E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA136" description="Huffman table data 136" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA137" description="Huffman table data 137" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA138" description="Huffman table data 138" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA139" description="Huffman table data 139" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM35" description="JPEG DHT memory" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA140" description="Huffman table data 140" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA141" description="Huffman table data 141" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA142" description="Huffman table data 142" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA143" description="Huffman table data 143" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM36" description="JPEG DHT memory" start="+0x3F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA144" description="Huffman table data 144" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA145" description="Huffman table data 145" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA146" description="Huffman table data 146" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA147" description="Huffman table data 147" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM37" description="JPEG DHT memory" start="+0x3F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA148" description="Huffman table data 148" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA149" description="Huffman table data 149" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA150" description="Huffman table data 150" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA151" description="Huffman table data 151" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM38" description="JPEG DHT memory" start="+0x3F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA152" description="Huffman table data 152" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA153" description="Huffman table data 153" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA154" description="Huffman table data 154" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA155" description="Huffman table data 155" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM39" description="JPEG DHT memory" start="+0x3FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA156" description="Huffman table data 156" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA157" description="Huffman table data 157" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA158" description="Huffman table data 158" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA159" description="Huffman table data 159" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM40" description="JPEG DHT memory" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA160" description="Huffman table data 160" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA161" description="Huffman table data 161" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA162" description="Huffman table data 162" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA163" description="Huffman table data 163" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM41" description="JPEG DHT memory" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA164" description="Huffman table data 164" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA165" description="Huffman table data 165" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA166" description="Huffman table data 166" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA167" description="Huffman table data 167" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM42" description="JPEG DHT memory" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA168" description="Huffman table data 168" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA169" description="Huffman table data 169" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA170" description="Huffman table data 170" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA171" description="Huffman table data 171" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM43" description="JPEG DHT memory" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA172" description="Huffman table data 172" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA173" description="Huffman table data 173" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA174" description="Huffman table data 174" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA175" description="Huffman table data 175" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM44" description="JPEG DHT memory" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA176" description="Huffman table data 176" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA177" description="Huffman table data 177" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA178" description="Huffman table data 178" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA179" description="Huffman table data 179" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM45" description="JPEG DHT memory" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA180" description="Huffman table data 180" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA181" description="Huffman table data 181" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA182" description="Huffman table data 182" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA183" description="Huffman table data 183" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM46" description="JPEG DHT memory" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA184" description="Huffman table data 184" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA185" description="Huffman table data 185" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA186" description="Huffman table data 186" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA187" description="Huffman table data 187" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM47" description="JPEG DHT memory" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA188" description="Huffman table data 188" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA189" description="Huffman table data 189" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA190" description="Huffman table data 190" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA191" description="Huffman table data 191" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM48" description="JPEG DHT memory" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA192" description="Huffman table data 192" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA193" description="Huffman table data 193" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA194" description="Huffman table data 194" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA195" description="Huffman table data 195" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM49" description="JPEG DHT memory" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA196" description="Huffman table data 196" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA197" description="Huffman table data 197" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA198" description="Huffman table data 198" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA199" description="Huffman table data 199" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM50" description="JPEG DHT memory" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA200" description="Huffman table data 200" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA201" description="Huffman table data 201" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA202" description="Huffman table data 202" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA203" description="Huffman table data 203" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM51" description="JPEG DHT memory" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA204" description="Huffman table data 204" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA205" description="Huffman table data 205" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA206" description="Huffman table data 206" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA207" description="Huffman table data 207" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM52" description="JPEG DHT memory" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA208" description="Huffman table data 208" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA209" description="Huffman table data 209" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA210" description="Huffman table data 210" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA211" description="Huffman table data 211" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM53" description="JPEG DHT memory" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA212" description="Huffman table data 212" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA213" description="Huffman table data 213" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA214" description="Huffman table data 214" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA215" description="Huffman table data 215" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM54" description="JPEG DHT memory" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA216" description="Huffman table data 216" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA217" description="Huffman table data 217" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA218" description="Huffman table data 218" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA219" description="Huffman table data 219" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM55" description="JPEG DHT memory" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA220" description="Huffman table data 220" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA221" description="Huffman table data 221" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA222" description="Huffman table data 222" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA223" description="Huffman table data 223" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM56" description="JPEG DHT memory" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA224" description="Huffman table data 224" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA225" description="Huffman table data 225" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA226" description="Huffman table data 226" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA227" description="Huffman table data 227" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM57" description="JPEG DHT memory" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA228" description="Huffman table data 228" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA229" description="Huffman table data 229" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA230" description="Huffman table data 230" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA231" description="Huffman table data 231" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM58" description="JPEG DHT memory" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA232" description="Huffman table data 232" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA233" description="Huffman table data 233" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA234" description="Huffman table data 234" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA235" description="Huffman table data 235" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM59" description="JPEG DHT memory" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA236" description="Huffman table data 236" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA237" description="Huffman table data 237" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA238" description="Huffman table data 238" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA239" description="Huffman table data 239" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM60" description="JPEG DHT memory" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA240" description="Huffman table data 240" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA241" description="Huffman table data 241" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA242" description="Huffman table data 242" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA243" description="Huffman table data 243" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM61" description="JPEG DHT memory" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA244" description="Huffman table data 244" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA245" description="Huffman table data 245" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA246" description="Huffman table data 246" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA247" description="Huffman table data 247" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM62" description="JPEG DHT memory" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA248" description="Huffman table data 248" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA249" description="Huffman table data 249" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA250" description="Huffman table data 250" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA251" description="Huffman table data 251" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM63" description="JPEG DHT memory" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA252" description="Huffman table data 252" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA253" description="Huffman table data 253" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA254" description="Huffman table data 254" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA255" description="Huffman table data 255" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM64" description="JPEG DHT memory" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA256" description="Huffman table data 256" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA257" description="Huffman table data 257" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA258" description="Huffman table data 258" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA259" description="Huffman table data 259" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM65" description="JPEG DHT memory" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA260" description="Huffman table data 260" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA261" description="Huffman table data 261" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA262" description="Huffman table data 262" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA263" description="Huffman table data 263" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM66" description="JPEG DHT memory" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA264" description="Huffman table data 264" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA265" description="Huffman table data 265" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA266" description="Huffman table data 266" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA267" description="Huffman table data 267" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM67" description="JPEG DHT memory" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA268" description="Huffman table data 268" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA269" description="Huffman table data 269" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA270" description="Huffman table data 270" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA271" description="Huffman table data 271" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM68" description="JPEG DHT memory" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA272" description="Huffman table data 272" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA273" description="Huffman table data 273" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA274" description="Huffman table data 274" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA275" description="Huffman table data 275" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM69" description="JPEG DHT memory" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA276" description="Huffman table data 276" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA277" description="Huffman table data 277" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA278" description="Huffman table data 278" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA279" description="Huffman table data 279" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM70" description="JPEG DHT memory" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA280" description="Huffman table data 280" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA281" description="Huffman table data 281" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA282" description="Huffman table data 282" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA283" description="Huffman table data 283" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM71" description="JPEG DHT memory" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA284" description="Huffman table data 284" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA285" description="Huffman table data 285" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA286" description="Huffman table data 286" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA287" description="Huffman table data 287" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM72" description="JPEG DHT memory" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA288" description="Huffman table data 288" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA289" description="Huffman table data 289" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA290" description="Huffman table data 290" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA291" description="Huffman table data 291" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM73" description="JPEG DHT memory" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA292" description="Huffman table data 292" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA293" description="Huffman table data 293" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA294" description="Huffman table data 294" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA295" description="Huffman table data 295" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM74" description="JPEG DHT memory" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA296" description="Huffman table data 296" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA297" description="Huffman table data 297" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA298" description="Huffman table data 298" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA299" description="Huffman table data 299" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM75" description="JPEG DHT memory" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA300" description="Huffman table data 300" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA301" description="Huffman table data 301" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA302" description="Huffman table data 302" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA303" description="Huffman table data 303" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM76" description="JPEG DHT memory" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA304" description="Huffman table data 304" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA305" description="Huffman table data 305" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA306" description="Huffman table data 306" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA307" description="Huffman table data 307" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM77" description="JPEG DHT memory" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA308" description="Huffman table data 308" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA309" description="Huffman table data 309" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA310" description="Huffman table data 310" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA311" description="Huffman table data 311" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM78" description="JPEG DHT memory" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA312" description="Huffman table data 312" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA313" description="Huffman table data 313" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA314" description="Huffman table data 314" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA315" description="Huffman table data 315" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM79" description="JPEG DHT memory" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA316" description="Huffman table data 316" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA317" description="Huffman table data 317" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA318" description="Huffman table data 318" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA319" description="Huffman table data 319" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM80" description="JPEG DHT memory" start="+0x4A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA320" description="Huffman table data 320" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA321" description="Huffman table data 321" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA322" description="Huffman table data 322" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA323" description="Huffman table data 323" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM81" description="JPEG DHT memory" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA324" description="Huffman table data 324" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA325" description="Huffman table data 325" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA326" description="Huffman table data 326" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA327" description="Huffman table data 327" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM82" description="JPEG DHT memory" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA328" description="Huffman table data 328" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA329" description="Huffman table data 329" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA330" description="Huffman table data 330" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA331" description="Huffman table data 331" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM83" description="JPEG DHT memory" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA332" description="Huffman table data 332" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA333" description="Huffman table data 333" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA334" description="Huffman table data 334" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA335" description="Huffman table data 335" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM84" description="JPEG DHT memory" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA336" description="Huffman table data 336" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA337" description="Huffman table data 337" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA338" description="Huffman table data 338" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA339" description="Huffman table data 339" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM85" description="JPEG DHT memory" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA340" description="Huffman table data 340" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA341" description="Huffman table data 341" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA342" description="Huffman table data 342" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA343" description="Huffman table data 343" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM86" description="JPEG DHT memory" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA344" description="Huffman table data 344" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA345" description="Huffman table data 345" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA346" description="Huffman table data 346" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA347" description="Huffman table data 347" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM87" description="JPEG DHT memory" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA348" description="Huffman table data 348" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA349" description="Huffman table data 349" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA350" description="Huffman table data 350" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA351" description="Huffman table data 351" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM88" description="JPEG DHT memory" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA352" description="Huffman table data 352" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA353" description="Huffman table data 353" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA354" description="Huffman table data 354" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA355" description="Huffman table data 355" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM89" description="JPEG DHT memory" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA356" description="Huffman table data 356" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA357" description="Huffman table data 357" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA358" description="Huffman table data 358" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA359" description="Huffman table data 359" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM90" description="JPEG DHT memory" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA360" description="Huffman table data 360" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA361" description="Huffman table data 361" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA362" description="Huffman table data 362" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA363" description="Huffman table data 363" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM91" description="JPEG DHT memory" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA364" description="Huffman table data 364" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA365" description="Huffman table data 365" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA366" description="Huffman table data 366" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA367" description="Huffman table data 367" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM92" description="JPEG DHT memory" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA368" description="Huffman table data 368" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA369" description="Huffman table data 369" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA370" description="Huffman table data 370" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA371" description="Huffman table data 371" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM93" description="JPEG DHT memory" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA372" description="Huffman table data 372" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA373" description="Huffman table data 373" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA374" description="Huffman table data 374" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA375" description="Huffman table data 375" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM94" description="JPEG DHT memory" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA376" description="Huffman table data 376" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA377" description="Huffman table data 377" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA378" description="Huffman table data 378" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA379" description="Huffman table data 379" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM95" description="JPEG DHT memory" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA380" description="Huffman table data 380" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA381" description="Huffman table data 381" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA382" description="Huffman table data 382" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA383" description="Huffman table data 383" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM96" description="JPEG DHT memory" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA384" description="Huffman table data 384" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA385" description="Huffman table data 385" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA386" description="Huffman table data 386" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA387" description="Huffman table data 387" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM97" description="JPEG DHT memory" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA388" description="Huffman table data 388" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA389" description="Huffman table data 389" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA390" description="Huffman table data 390" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA391" description="Huffman table data 391" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM98" description="JPEG DHT memory" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA392" description="Huffman table data 392" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA393" description="Huffman table data 393" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA394" description="Huffman table data 394" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA395" description="Huffman table data 395" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM99" description="JPEG DHT memory" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA396" description="Huffman table data 396" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA397" description="Huffman table data 397" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA398" description="Huffman table data 398" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA399" description="Huffman table data 399" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM100" description="JPEG DHT memory" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA400" description="Huffman table data 400" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA401" description="Huffman table data 401" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA402" description="Huffman table data 402" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA403" description="Huffman table data 403" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM101" description="JPEG DHT memory" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA404" description="Huffman table data 404" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA405" description="Huffman table data 405" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA406" description="Huffman table data 406" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA407" description="Huffman table data 407" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_DHTMEM102" description="JPEG DHT memory" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="DATA408" description="Huffman table data 408" start="0" size="8" access="Read/Write" />
+      <BitField name="DATA409" description="Huffman table data 409" start="8" size="8" access="Read/Write" />
+      <BitField name="DATA410" description="Huffman table data 410" start="16" size="8" access="Read/Write" />
+      <BitField name="DATA411" description="Huffman table data 411" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_0" description="JPEG Huffman encoder AC0" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_1" description="JPEG Huffman encoder AC0" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_2" description="JPEG Huffman encoder AC0" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_3" description="JPEG Huffman encoder AC0" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_4" description="JPEG Huffman encoder AC0" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_6" description="JPEG Huffman encoder AC0" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_7" description="JPEG Huffman encoder AC0" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_8" description="JPEG Huffman encoder AC0" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE16" description="Huffman code 16" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN16" description="Huffman length 16" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE17" description="Huffman code 17" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN17" description="Huffman length 17" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_9" description="JPEG Huffman encoder AC0" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE18" description="Huffman code 18" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN18" description="Huffman length 18" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE19" description="Huffman code 19" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN19" description="Huffman length 19" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_10" description="JPEG Huffman encoder AC0" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE20" description="Huffman code 20" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN20" description="Huffman length 20" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE21" description="Huffman code 21" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN21" description="Huffman length 21" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_11" description="JPEG Huffman encoder AC0" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE22" description="Huffman code 22" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN22" description="Huffman length 22" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE23" description="Huffman code 23" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN23" description="Huffman length 23" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_12" description="JPEG Huffman encoder AC0" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE24" description="Huffman code 24" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN24" description="Huffman length 24" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE25" description="Huffman code 25" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN25" description="Huffman length 25" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_13" description="JPEG Huffman encoder AC0" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE26" description="Huffman code 26" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN26" description="Huffman length 26" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE27" description="Huffman code 27" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN27" description="Huffman length 27" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_14" description="JPEG Huffman encoder AC0" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE28" description="Huffman code 28" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN28" description="Huffman length 28" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE29" description="Huffman code 29" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN29" description="Huffman length 29" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_15" description="JPEG Huffman encoder AC0" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE30" description="Huffman code 30" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN30" description="Huffman length 30" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE31" description="Huffman code 31" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN31" description="Huffman length 31" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_16" description="JPEG Huffman encoder AC0" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE33" description="Huffman code 33" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN33" description="Huffman length 33" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_17" description="JPEG Huffman encoder AC0" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE35" description="Huffman code 35" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN35" description="Huffman length 35" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_18" description="JPEG Huffman encoder AC0" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE37" description="Huffman code 37" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN37" description="Huffman length 37" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_19" description="JPEG Huffman encoder AC0" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN38" description="Huffman length 38" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE39" description="Huffman code 39" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN39" description="Huffman length 39" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_20" description="JPEG Huffman encoder AC0" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HCODE41" description="Huffman code 41" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN41" description="Huffman length 41" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_21" description="JPEG Huffman encoder AC0" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN42" description="Huffman length 42" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE43" description="Huffman code 43" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN43" description="Huffman length 43" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_22" description="JPEG Huffman encoder AC0" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN44" description="Huffman length 44" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE45" description="Huffman code 45" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN45" description="Huffman length 45" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_23" description="JPEG Huffman encoder AC0" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE46" description="Huffman code 46" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN46" description="Huffman length 46" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE47" description="Huffman code 47" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN47" description="Huffman length 47" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_24" description="JPEG Huffman encoder AC0" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN48" description="Huffman length 48" start="8" size="4" access="Read/Write" />
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+      <BitField name="HLEN49" description="Huffman length 49" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_25" description="JPEG Huffman encoder AC0" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN50" description="Huffman length 50" start="8" size="4" access="Read/Write" />
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+      <BitField name="HLEN51" description="Huffman length 51" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_26" description="JPEG Huffman encoder AC0" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN52" description="Huffman length 52" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE53" description="Huffman code 53" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN53" description="Huffman length 53" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_27" description="JPEG Huffman encoder AC0" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+      <BitField name="HLEN54" description="Huffman length 54" start="8" size="4" access="Read/Write" />
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+      <BitField name="HLEN55" description="Huffman length 55" start="24" size="4" access="Read/Write" />
+    </Register>
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_30" description="JPEG Huffman encoder AC0" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_32" description="JPEG Huffman encoder AC0" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_34" description="JPEG Huffman encoder AC0" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_35" description="JPEG Huffman encoder AC0" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_36" description="JPEG Huffman encoder AC0" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_37" description="JPEG Huffman encoder AC0" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_38" description="JPEG Huffman encoder AC0" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_39" description="JPEG Huffman encoder AC0" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
+    <Register name="JPEG_HUFFENC_AC0_41" description="JPEG Huffman encoder AC0" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+      <BitField name="HCODE165" description="Huffman code 165" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN165" description="Huffman length 165" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN166" description="Huffman length 166" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE167" description="Huffman code 167" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN167" description="Huffman length 167" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HCODE168" description="Huffman code 168" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN168" description="Huffman length 168" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE169" description="Huffman code 169" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN169" description="Huffman length 169" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HCODE171" description="Huffman code 171" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN171" description="Huffman length 171" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN173" description="Huffman length 173" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN175" description="Huffman length 175" start="24" size="4" access="Read/Write" />
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+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
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+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
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+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+      <BitField name="HLEN19" description="Huffman length 19" start="24" size="4" access="Read/Write" />
+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+    </Register>
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+      <BitField name="HLEN143" description="Huffman length 143" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_72" description="JPEG Huffman encoder AC1" start="+0x780" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE144" description="Huffman code 144" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN144" description="Huffman length 144" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE145" description="Huffman code 145" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN145" description="Huffman length 145" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_73" description="JPEG Huffman encoder AC1" start="+0x784" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE146" description="Huffman code 146" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN146" description="Huffman length 146" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE147" description="Huffman code 147" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN147" description="Huffman length 147" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_74" description="JPEG Huffman encoder AC1" start="+0x788" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE148" description="Huffman code 148" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN148" description="Huffman length 148" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE149" description="Huffman code 149" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN149" description="Huffman length 149" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_75" description="JPEG Huffman encoder AC1" start="+0x78C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE150" description="Huffman code 150" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN150" description="Huffman length 150" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE151" description="Huffman code 151" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN151" description="Huffman length 151" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_76" description="JPEG Huffman encoder AC1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE152" description="Huffman code 152" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN152" description="Huffman length 152" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE153" description="Huffman code 153" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN153" description="Huffman length 153" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_77" description="JPEG Huffman encoder AC1" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE154" description="Huffman code 154" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN154" description="Huffman length 154" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE155" description="Huffman code 155" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN155" description="Huffman length 155" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_78" description="JPEG Huffman encoder AC1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE156" description="Huffman code 156" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN156" description="Huffman length 156" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE157" description="Huffman code 157" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN157" description="Huffman length 157" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_79" description="JPEG Huffman encoder AC1" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE158" description="Huffman code 158" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN158" description="Huffman length 158" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE159" description="Huffman code 159" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN159" description="Huffman length 159" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_80" description="JPEG Huffman encoder AC1" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE160" description="Huffman code 160" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN160" description="Huffman length 160" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE161" description="Huffman code 161" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN161" description="Huffman length 161" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_81" description="JPEG Huffman encoder AC1" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE162" description="Huffman code 162" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN162" description="Huffman length 162" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE163" description="Huffman code 163" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN163" description="Huffman length 163" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_82" description="JPEG Huffman encoder AC1" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE164" description="Huffman code 164" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN164" description="Huffman length 164" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE165" description="Huffman code 165" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN165" description="Huffman length 165" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_83" description="JPEG Huffman encoder AC1" start="+0x7AC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE166" description="Huffman code 166" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN166" description="Huffman length 166" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE167" description="Huffman code 167" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN167" description="Huffman length 167" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_84" description="JPEG Huffman encoder AC1" start="+0x7B0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE168" description="Huffman code 168" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN168" description="Huffman length 168" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE169" description="Huffman code 169" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN169" description="Huffman length 169" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_85" description="JPEG Huffman encoder AC1" start="+0x7B4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE170" description="Huffman code 170" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN170" description="Huffman length 170" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE171" description="Huffman code 171" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN171" description="Huffman length 171" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_86" description="JPEG Huffman encoder AC1" start="+0x7B8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE172" description="Huffman code 172" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN172" description="Huffman length 172" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE173" description="Huffman code 173" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN173" description="Huffman length 173" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_AC1_87" description="JPEG Huffman encoder AC1" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE174" description="Huffman code 174" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN174" description="Huffman length 174" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE175" description="Huffman code 175" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN175" description="Huffman length 175" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_0" description="JPEG Huffman encoder DC0" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_1" description="JPEG Huffman encoder DC0" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_2" description="JPEG Huffman encoder DC0" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_3" description="JPEG Huffman encoder DC0" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_4" description="JPEG Huffman encoder DC0" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_5" description="JPEG Huffman encoder DC0" start="+0x7D4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_6" description="JPEG Huffman encoder DC0" start="+0x7D8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC0_7" description="JPEG Huffman encoder DC0" start="+0x7DC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_0" description="JPEG Huffman encoder DC1" start="+0x7E0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE0" description="Huffman code 0" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN0" description="Huffman length 0" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE1" description="Huffman code 1" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN1" description="Huffman length 1" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_1" description="JPEG Huffman encoder DC1" start="+0x7E4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE2" description="Huffman code 2" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN2" description="Huffman length 2" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE3" description="Huffman code 3" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN3" description="Huffman length 3" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_2" description="JPEG Huffman encoder DC1" start="+0x7E8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE4" description="Huffman code 4" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN4" description="Huffman length 4" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE5" description="Huffman code 5" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN5" description="Huffman length 5" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_3" description="JPEG Huffman encoder DC1" start="+0x7EC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE6" description="Huffman code 6" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN6" description="Huffman length 6" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE7" description="Huffman code 7" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN7" description="Huffman length 7" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_4" description="JPEG Huffman encoder DC1" start="+0x7F0" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE8" description="Huffman code 8" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN8" description="Huffman length 8" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE9" description="Huffman code 9" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN9" description="Huffman length 9" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_5" description="JPEG Huffman encoder DC1" start="+0x7F4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE10" description="Huffman code 10" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN10" description="Huffman length 10" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE11" description="Huffman code 11" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN11" description="Huffman length 11" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_6" description="JPEG Huffman encoder DC1" start="+0x7F8" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE12" description="Huffman code 12" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN12" description="Huffman length 12" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE13" description="Huffman code 13" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN13" description="Huffman length 13" start="24" size="4" access="Read/Write" />
+    </Register>
+    <Register name="JPEG_HUFFENC_DC1_7" description="JPEG Huffman encoder DC1" start="+0x7FC" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="HCODE14" description="Huffman code 14" start="0" size="8" access="Read/Write" />
+      <BitField name="HLEN14" description="Huffman length 14" start="8" size="4" access="Read/Write" />
+      <BitField name="HCODE15" description="Huffman code 15" start="16" size="8" access="Read/Write" />
+      <BitField name="HLEN15" description="Huffman length 15" start="24" size="4" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LTDC" description="LCD-TFT display controller" start="0x48001000">
+    <Register name="LTDC_SSCR" description="LTDC synchronization size configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VSH" description="vertical synchronization height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="HSW" description="horizontal synchronization width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_BPCR" description="LTDC back porch configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVBP" description="accumulated Vertical back porch (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="AHBP" description="accumulated horizontal back porch (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_AWCR" description="LTDC active width configuration register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AAH" description="accumulated active height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="AAW" description="accumulated active width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_TWCR" description="LTDC total width configuration register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOTALH" description="total height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="TOTALW" description="total width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_GCR" description="LTDC global control register" start="+0x018" size="4" reset_value="0x00002220" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC global enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC disabled" start="0x0" />
+        <Enum name="B_0x1" description="LTDC enabled" start="0x1" />
+      </BitField>
+      <BitField name="GAMEN" description="Gamma correction enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma correction disabled (pixels bypass the gamma operator)" start="0x0" />
+        <Enum name="B_0x1" description="Gamma correction enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBW" description="dither blue width" start="4" size="3" access="ReadOnly" />
+      <BitField name="DGW" description="dither green width" start="8" size="3" access="ReadOnly" />
+      <BitField name="DRW" description="dither red width" start="12" size="3" access="ReadOnly" />
+      <BitField name="DEN" description="dither enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dither disabled" start="0x0" />
+        <Enum name="B_0x1" description="dither enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEN" description="CRC enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFEN" description="single-frame mode: mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="single-frame disabled: a trigger (on SFSWTR) generates a continuous flow." start="0x0" />
+        <Enum name="B_0x1" description="single-frame enabled: a trigger (on SFSWTR) generates a single frame." start="0x1" />
+      </BitField>
+      <BitField name="SFSWTR" description="single-frame mode: software trigger" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="triggers one frame" start="0x1" />
+      </BitField>
+      <BitField name="PCPOL" description="pixel clock polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the pixel and sync data are generated at the rising-edge of the output LCD_CLK clock." start="0x0" />
+        <Enum name="B_0x1" description="the pixel and sync data are generated at the falling-edge of the output LCD_CLK clock." start="0x1" />
+      </BitField>
+      <BitField name="DEPOL" description="blanking (no data/pixel) polarity" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blanking (no data/pixel) polarity is active low." start="0x0" />
+        <Enum name="B_0x1" description="blanking (no data/pixel) polarity is active high." start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="vertical synchronization polarity" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vertical synchronization is active low." start="0x0" />
+        <Enum name="B_0x1" description="vertical synchronization is active high." start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="horizontal synchronization polarity" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="horizontal synchronization polarity is active low." start="0x0" />
+        <Enum name="B_0x1" description="horizontal synchronization polarity is active high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_GC1R" description="LTDC global configuration 1 register" start="+0x01C" size="4" reset_value="0x6BE4D888" reset_mask="0xFFFFFFFF">
+      <BitField name="WBCH" description="width of blue channel output" start="0" size="4" access="ReadOnly" />
+      <BitField name="WGCH" description="width of green channel output" start="4" size="4" access="ReadOnly" />
+      <BitField name="WRCH" description="width of red channel output" start="8" size="4" access="ReadOnly" />
+      <BitField name="PRBA" description="precise blending ability" start="12" size="1" access="ReadOnly" />
+      <BitField name="DT" description="dithering technique implemented" start="14" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no dithering" start="0x0" />
+        <Enum name="B_0x1" description="ordered 4x4 Bayer" start="0x1" />
+        <Enum name="B_0x3" description="pseudo-random LFSR" start="0x3" />
+      </BitField>
+      <BitField name="GCT" description="gamma correction technique implemented" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="no gamma" start="0x0" />
+        <Enum name="B_0x1" description="gamma with 256 samples" start="0x1" />
+        <Enum name="B_0x2" description="gamma with 8 interpolated segments" start="0x2" />
+      </BitField>
+      <BitField name="SHRA" description="shadow registers ability" start="21" size="1" access="ReadOnly" />
+      <BitField name="BCP" description="background color programmability (unique color blended as background)" start="22" size="1" access="ReadOnly" />
+      <BitField name="BBA" description="background blending ability" start="23" size="1" access="ReadOnly" />
+      <BitField name="LNIP" description="line-IRQ: line position programmability" start="24" size="1" access="ReadOnly" />
+      <BitField name="TP" description="timing programmability" start="25" size="1" access="ReadOnly" />
+      <BitField name="SPP" description="sync polarity programmability" start="27" size="1" access="ReadOnly" />
+      <BitField name="DWP" description="dither width programmability" start="28" size="1" access="ReadOnly" />
+      <BitField name="STRA" description="status register ability" start="29" size="1" access="ReadOnly" />
+      <BitField name="CRMA" description="configuration reading mode ability" start="30" size="1" access="ReadOnly" />
+      <BitField name="BMA" description="blind mode ability" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_GC2R" description="LTDC global configuration 2 register" start="+0x020" size="4" reset_value="0x0000BB30" reset_mask="0xFFFFFFFF">
+      <BitField name="BLA" description="background layer ability (pixels of background layer are read from memory)" start="0" size="1" access="ReadOnly" />
+      <BitField name="STSA" description="slave timings synchronization ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="DVA" description="dual-view ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="DPA" description="secondary RGB output port ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="BW" description="bus width (log2 of number of bytes)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x2" description="32-bit bus" start="0x2" />
+        <Enum name="B_0x3" description="64-bit bus" start="0x3" />
+        <Enum name="B_0x4" description="128-bit bus" start="0x4" />
+      </BitField>
+      <BitField name="EDCA" description="external display control ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="OCA" description="output conversion ability (RGB to YCbCr)" start="8" size="1" access="ReadOnly" />
+      <BitField name="AXIIDA" description="AXIID ability" start="9" size="1" access="ReadOnly" />
+      <BitField name="ROTA" description="rotation support ability" start="10" size="1" access="ReadOnly" />
+      <BitField name="SISA" description="second interrupt set ability" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="second interrupt set not available" start="0x0" />
+        <Enum name="B_0x1" description="second interrupt set available" start="0x1" />
+      </BitField>
+      <BitField name="SFA" description="single frame mode ability" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="single frame not available" start="0x0" />
+        <Enum name="B_0x1" description="single frame available" start="0x1" />
+      </BitField>
+      <BitField name="CRCA" description="CRC ability" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CRC no computation available" start="0x0" />
+        <Enum name="B_0x1" description="CRC computation available" start="0x1" />
+      </BitField>
+      <BitField name="BOA" description="blending order ability" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="blending order fixed" start="0x0" />
+        <Enum name="B_0x1" description="blending order configurable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_SRCR" description="LTDC shadow reload configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_GCCR" description="LTDC gamma correction configuration register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDR" description="address of the R,G,B table where the COMP component is written" start="0" size="8" access="WriteOnly" />
+      <BitField name="COMP" description="color component to be written, in either (or all) the R,G,B tables" start="8" size="8" access="WriteOnly" />
+      <BitField name="BEN" description="write trigger to the blue table" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the blue table." start="0x1" />
+      </BitField>
+      <BitField name="GEN" description="write trigger to the green table" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the green table." start="0x1" />
+      </BitField>
+      <BitField name="REN" description="write trigger to the red table" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the red table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_BCCR" description="LTDC background color configuration register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCBLUE" description="background color blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="BCGREEN" description="background color green value" start="8" size="8" access="Read/Write" />
+      <BitField name="BCRED" description="background color red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_IER" description="LTDC interrupt enable register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIE" description="Line interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUWIE" description="FIFO underrun warning interrupt enable " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transfer Error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="transfer error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RRIE" description="Register reload interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="register reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUIE" description="FIFO underrun interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC error disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ISR" description="LTDC interrupt status register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIF" description="Line interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no line interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt generated when a programmed line is reached" start="0x1" />
+      </BitField>
+      <BitField name="FUWIF" description="FIFO underrun warning interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun warning interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TERRIF" description="Transfer error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+      <BitField name="RRIF" description="Register reload interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no register reload interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)" start="0x1" />
+      </BitField>
+      <BitField name="FUIF" description="FIFO underrun interrupt flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CRCIF" description="CRC error interrupt flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ICR" description="LTDC interrupt clear register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLIF" description="clears the line interrupt flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the LIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CFUWIF" description="clears the FIFO underrun warning interrupt flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUWIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CTERRIF" description="clears the transfer error interrupt flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the TERRIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CRRIF" description="clears register reload interrupt flag" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the RRIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CFUIF" description="clears the FIFO underrun interrupt flag" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CCRCIF" description="clears the CRC error interrupt flag" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the CRCIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_LIPCR" description="LTDC line interrupt position configuration register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIPOS" description="line interrupt position" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_CPSR" description="LTDC current position status register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CYPOS" description="current Y position " start="0" size="16" access="ReadOnly" />
+      <BitField name="CXPOS" description="current X position " start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_CDSR" description="LTDC current display status register" start="+0x048" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="VDES" description="vertical data enable display status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="HDES" description="horizontal data enable display status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCS" description="vertical synchronization display status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="HSYNCS" description="horizontal synchronization display status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_EDCR" description="LTDC external display control register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCYEN" description="output conversion to YCbCr 422 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="OCYSEL" description="output conversion to YCbCr 422" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="use ITU-R BT.601 set (for typically SDTV analog-like displays)" start="0x0" />
+        <Enum name="B_0x1" description="use ITU-R BT.709 set (for typically HDTV digital-like displays)" start="0x1" />
+      </BitField>
+      <BitField name="OCYCO" description="output conversion to YCbCr 422" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb is output first (Y0Cb, then Y1Cr, Y2Cb and so on)." start="0x0" />
+        <Enum name="B_0x1" description="Cr is output first (Y0Cr, then Y1Cb, Y2Cr and so on)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_IER2" description="LTDC interrupt enable register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIE" description="Line interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUWIE" description="FIFO underrun warning interrupt enable " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transfer error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="transfer error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RRIE" description="Register reload interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="register reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUIE" description="FIFO underrun interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC error disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ISR2" description="LTDC interrupt status register 2" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIF" description="Line interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no line interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt generated when a programmed line is reached" start="0x1" />
+      </BitField>
+      <BitField name="FUWIF" description="FIFO underrun warning interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun warning interrupt generated." start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TERRIF" description="Transfer error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+      <BitField name="RRIF" description="Register reload interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no register reload interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)" start="0x1" />
+      </BitField>
+      <BitField name="FUIF" description="FIFO underrun interrupt flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun interrupt generated." start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun interrupt generated, if one of the layer FIFO is empty and many pixel data are read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CRCIF" description="CRC Error interrupt flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ICR2" description="LTDC interrupt clear register 2" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLIF" description="clears the Line interrupt flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the LIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CFUWIF" description="clears the FIFO underrun warning interrupt flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUWIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CTERRIF" description="clears the Transfer Error interrupt flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the TERRIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CRRIF" description="clears register reload interrupt flag" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the RRIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CFUIF" description="clears the FIFO underrun interrupt flag" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CCRCIF" description="clears the CRC error interrupt flag" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the CRCIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_LIPCR2" description="LTDC line interrupt position configuration register 2" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIPOS" description="line interrupt position" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_ECRCR" description="LTDC expected CRC register" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECRC" description="expected CRC of frame" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_CCRCR" description="LTDC computed CRC register" start="+0x07C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRC" description="computed CRC of frame" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_FUTR" description="LTDC FIFO underrun threshold register" start="+0x090" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="THRE" description="threshold to trigger a FIFO underrun interrupt (per FIFO word, 64 bits)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1C0R" description="LTDC layerx configuration 0 register" start="+0x100" size="4" reset_value="0xFF50A076" reset_mask="0xFFFFFFFF">
+      <BitField name="CKTA" description="color key transparency ability" start="0" size="1" access="ReadOnly" />
+      <BitField name="CFBDA" description="color frame buffer duplication ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFBPA" description="color frame buffer pitch ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="APA" description="alpha plane ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="DCP" description="default color programmability" start="4" size="1" access="ReadOnly" />
+      <BitField name="WINA" description="windowing ability" start="5" size="1" access="ReadOnly" />
+      <BitField name="CLUTA" description="CLUT ability" start="6" size="1" access="ReadOnly" />
+      <BitField name="CKRA" description="color key replace ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="F21" description="blending factor 2, ability for: 1.0" start="8" size="1" access="ReadOnly" />
+      <BitField name="F20" description="blending factor 2, ability for: 0.0" start="9" size="1" access="ReadOnly" />
+      <BitField name="F2P" description="blending factor 2, ability for: pixel_alpha" start="10" size="1" access="ReadOnly" />
+      <BitField name="F21P" description="blending factor 2, ability for: 1.0 - pixel_alpha" start="11" size="1" access="ReadOnly" />
+      <BitField name="F2C" description="blending factor 2, ability for: constant_alpha" start="12" size="1" access="ReadOnly" />
+      <BitField name="F21C" description="blending factor 2, ability for: 1.0 - constant_alpha" start="13" size="1" access="ReadOnly" />
+      <BitField name="F2PC" description="blending factor 2, ability for: pixel_alpha * constant_alpha" start="14" size="1" access="ReadOnly" />
+      <BitField name="F21PC" description="blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="15" size="1" access="ReadOnly" />
+      <BitField name="F11" description="blending factor 1, ability for: 1.0" start="16" size="1" access="ReadOnly" />
+      <BitField name="F10" description="blending factor 1,ability for: 0.0" start="17" size="1" access="ReadOnly" />
+      <BitField name="F1P" description="blending factor 1, ability for: pixel_alpha" start="18" size="1" access="ReadOnly" />
+      <BitField name="F11P" description="blending factor 1, ability for: 1.0 - pixel_alpha" start="19" size="1" access="ReadOnly" />
+      <BitField name="F1C" description="blending factor 1, ability for: constant_alpha" start="20" size="1" access="ReadOnly" />
+      <BitField name="F11C" description="blending factor 1, ability for: 1.0 - constant_alpha" start="21" size="1" access="ReadOnly" />
+      <BitField name="F1PC" description="blending factor 1, ability for: pixel_alpha * constant_alpha" start="22" size="1" access="ReadOnly" />
+      <BitField name="F11PC" description="blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="23" size="1" access="ReadOnly" />
+      <BitField name="FF" description="flexible pixel format, ability" start="24" size="1" access="ReadOnly" />
+      <BitField name="RGB888" description="pixel format, ability for rgb888" start="25" size="1" access="ReadOnly" />
+      <BitField name="BGR565" description="pixel format, ability for bgr565" start="26" size="1" access="ReadOnly" />
+      <BitField name="RGB565" description="pixel format, ability for rgb565" start="27" size="1" access="ReadOnly" />
+      <BitField name="BGRA888" description="pixel format, ability for bgra8888" start="28" size="1" access="ReadOnly" />
+      <BitField name="RGBA8888" description="pixel format, ability for rgba8888" start="29" size="1" access="ReadOnly" />
+      <BitField name="ABGR8888" description="pixel format, ability for abgr8888" start="30" size="1" access="ReadOnly" />
+      <BitField name="ARGB8888" description="pixel format, ability for argb8888" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_L1C1R" description="LTDC layerx configuration 1 register" start="+0x104" size="4" reset_value="0x80000007" reset_mask="0xFFFFFFFF">
+      <BitField name="YIA" description="YCbCr 422 interleaved ability for that layer" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="interleaved not available" start="0x0" />
+        <Enum name="B_0x1" description="interleaved available" start="0x1" />
+      </BitField>
+      <BitField name="YSPA" description="YCbCr 420 semi-planar ability for that layer" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semi-planar not available" start="0x0" />
+        <Enum name="B_0x1" description="semi-planar available" start="0x1" />
+      </BitField>
+      <BitField name="YFPA" description="YCbCr 420 full-planar ability for that layer" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="full planar not available" start="0x0" />
+        <Enum name="B_0x1" description="full planar available" start="0x1" />
+      </BitField>
+      <BitField name="SCA" description="scaling ability for that layer" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="scaling not available" start="0x0" />
+        <Enum name="B_0x1" description="scaling available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1RCR" description="LTDC layerx reload control register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+      <BitField name="GRMSK" description="shadow reload control, global (centralized) reload masked" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="global reload active for this layer (control from LTDC_SRCR enabled)" start="0x0" />
+        <Enum name="B_0x1" description="global reload masked for this layer (control from LTDC_SRCR disabled)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CR" description="LTDC layerx control register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEN" description="layer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer disabled" start="0x0" />
+        <Enum name="B_0x1" description="layer enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN" description="color keying enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color keying disabled" start="0x0" />
+        <Enum name="B_0x1" description="color keying enabled: if RGB matches, then the ARGB are set to 0." start="0x1" />
+      </BitField>
+      <BitField name="CLUTEN" description="color look-up table enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color look-up table disabled" start="0x0" />
+        <Enum name="B_0x1" description="color look-up table enabled" start="0x1" />
+      </BitField>
+      <BitField name="HMEN" description="horizontal mirroring enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="mirror disabled" start="0x0" />
+        <Enum name="B_0x1" description="mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299)" start="0x1" />
+      </BitField>
+      <BitField name="DCBEN" description="default color blending enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blending disabled" start="0x0" />
+        <Enum name="B_0x1" description="blending enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1WHPCR" description="LTDC layerx window horizontal position configuration register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSTPOS" description="window horizontal start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WHSPPOS" description="window horizontal stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1WVPCR" description="LTDC layerx window vertical position configuration register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSTPOS" description="window vertical start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WVSPPOS" description="window vertical stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CKCR" description="LTDC layerx color keying configuration register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKBLUE" description="color key blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="CKGREEN" description="color key green value" start="8" size="8" access="Read/Write" />
+      <BitField name="CKRED" description="color key red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1PFCR" description="LTDC layerx pixel format configuration register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="pixel format" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888 (32 bpp)" start="0x0" />
+        <Enum name="B_0x1" description="ABGR888 (32 bpp)" start="0x1" />
+        <Enum name="B_0x2" description="RGBA888 (32 bpp)" start="0x2" />
+        <Enum name="B_0x3" description="BGRA8888 (32 bpp)" start="0x3" />
+        <Enum name="B_0x4" description="RGB565 (16 bpp, A = 255)" start="0x4" />
+        <Enum name="B_0x5" description="BGR565 (16 bpp, A = 255)" start="0x5" />
+        <Enum name="B_0x6" description="RGB888 (24 bpp packed, A = 255)" start="0x6" />
+        <Enum name="B_0x7" description="Flexible pixel format selected (see Section 38.7.50 and Section 38.7.51)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CACR" description="LTDC layerx constant alpha configuration register" start="+0x120" size="4" reset_value="0x000000FF" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="constant alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1DCCR" description="LTDC layerx default color configuration register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCBLUE" description="default color blue" start="0" size="8" access="Read/Write" />
+      <BitField name="DCGREEN" description="default color green" start="8" size="8" access="Read/Write" />
+      <BitField name="DCRED" description="default color red" start="16" size="8" access="Read/Write" />
+      <BitField name="DCALPHA" description="default color alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1BFCR" description="LTDC layerx blending factors configuration register" start="+0x128" size="4" reset_value="0x00000607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF2" description="blending factor 2 " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x5" description="1 - constant alpha" start="0x5" />
+        <Enum name="B_0x7" description="1 - (pixel alpha x constant alpha)" start="0x7" />
+      </BitField>
+      <BitField name="BF1" description="blending factor 1" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="constant alpha" start="0x4" />
+        <Enum name="B_0x6" description="pixel alpha x constant alpha" start="0x6" />
+      </BitField>
+      <BitField name="BOR" description="blending order" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer set in background" start="0x0" />
+        <Enum name="B_0x1" description="layer set in foreground" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1BLCR" description="LTDC layerx burst length configuration register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BL" description="burst length" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="maximum burst length (16 words 64 bits, thus 128 Bytes)" start="0x00" />
+        <Enum name="B_0x01" description="1 word (of 64 bits) per burst" start="0x01" />
+        <Enum name="B_0x10" description="16 words (of 64 bits) per burst" start="0x10" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1PCR" description="LTDC layerx planar configuration register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="YCEN" description="YCbCr-to-RGB conversion enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="YCbCr conversion enabled, using the YCM setting above" start="0x1" />
+      </BitField>
+      <BitField name="YCM" description="YCbCr conversion mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)" start="0x0" />
+        <Enum name="B_0x1" description="semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x1" />
+        <Enum name="B_0x2" description="full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x2" />
+      </BitField>
+      <BitField name="YF" description="Y component first" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Y component disabled (thus Cr or Cb component is on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="Y component enabled (thus Y component is on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="CBF" description="Cb component first" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb disabled (thus Cr component is on byte 0 and 1)" start="0x0" />
+        <Enum name="B_0x1" description="Cb enabled (thus Cb component is on byte 0 and 1)" start="0x1" />
+      </BitField>
+      <BitField name="OF" description="Odd pixel first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="odd pixel disabled (thus even pixel on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="odd pixel enabled (thus odd pixel on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="YREN" description="Y rescale enable for the color dynamic range" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="rescaling disabled (input component thus assumed provided in 0 to 255)" start="0x0" />
+        <Enum name="B_0x1" description="rescaling enabled (input component thus assumed provided in 16 to 235)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CFBAR" description="LTDC layerx color frame buffer address register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="color frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CFBLR" description="LTDC layerx color frame buffer length register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLL" description="color frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="CFBP" description="color frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CFBLNR" description="LTDC layerx color frame buffer line number register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBA0R" description="LTDC layer1 auxiliary frame buffer address 0 register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBADD0" description="frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBA1R" description="LTDC layer1 auxiliary frame buffer address 1 register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBADD1" description="auxiliary frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBLR" description="LTDC layer1 auxiliary frame buffer length register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBLL" description="auxiliary frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="AFBP" description="auxiliary frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBLNR" description="LTDC layer1 auxiliary frame buffer line number register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBLNBR" description="auxiliary frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CLUTWR" description="LTDC layerx CLUT write register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="blue value" start="0" size="8" access="WriteOnly" />
+      <BitField name="GREEN" description="green value" start="8" size="8" access="WriteOnly" />
+      <BitField name="RED" description="red value" start="16" size="8" access="WriteOnly" />
+      <BitField name="CLUTADD" description="CLUT address" start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="LTDC_L1CYR0R" description="LTDC layerx conversion YCbCr RGB 0 register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2R" description="Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2B" description="Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CYR1R" description="LTDC layerx conversion YCbCr RGB 1 register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2G" description="Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2G" description="Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1FPF0R" description="LTDC layerx flexible pixel format 0 register" start="+0x174" size="4" reset_value="0x00011100" reset_mask="0xFFFFFFFF">
+      <BitField name="APOS" description="Location of the Alpha component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="ALEN" description="Width of the Alpha component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="RPOS" description="Location of the Red component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="RLEN" description="Width of the Red component (in bits)" start="14" size="4" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1FPF1R" description="LTDC layerx flexible pixel format 1 register" start="+0x178" size="4" reset_value="0x00093110" reset_mask="0xFFFFFFFF">
+      <BitField name="GPOS" description="Location of the Green component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="GLEN" description="Width of the Green component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="BPOS" description="Location of the Blue component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="BLEN" description="Width of the Blue component (in bits)" start="14" size="4" access="Read/Write" />
+      <BitField name="PSIZE" description="Pixel size (in bytes)" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2C0R" description="LTDC layerx configuration 0 register" start="+0x200" size="4" reset_value="0xFF50A076" reset_mask="0xFFFFFFFF">
+      <BitField name="CKTA" description="color key transparency ability" start="0" size="1" access="ReadOnly" />
+      <BitField name="CFBDA" description="color frame buffer duplication ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFBPA" description="color frame buffer pitch ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="APA" description="alpha plane ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="DCP" description="default color programmability" start="4" size="1" access="ReadOnly" />
+      <BitField name="WINA" description="windowing ability" start="5" size="1" access="ReadOnly" />
+      <BitField name="CLUTA" description="CLUT ability" start="6" size="1" access="ReadOnly" />
+      <BitField name="CKRA" description="color key replace ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="F21" description="blending factor 2, ability for: 1.0" start="8" size="1" access="ReadOnly" />
+      <BitField name="F20" description="blending factor 2, ability for: 0.0" start="9" size="1" access="ReadOnly" />
+      <BitField name="F2P" description="blending factor 2, ability for: pixel_alpha" start="10" size="1" access="ReadOnly" />
+      <BitField name="F21P" description="blending factor 2, ability for: 1.0 - pixel_alpha" start="11" size="1" access="ReadOnly" />
+      <BitField name="F2C" description="blending factor 2, ability for: constant_alpha" start="12" size="1" access="ReadOnly" />
+      <BitField name="F21C" description="blending factor 2, ability for: 1.0 - constant_alpha" start="13" size="1" access="ReadOnly" />
+      <BitField name="F2PC" description="blending factor 2, ability for: pixel_alpha * constant_alpha" start="14" size="1" access="ReadOnly" />
+      <BitField name="F21PC" description="blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="15" size="1" access="ReadOnly" />
+      <BitField name="F11" description="blending factor 1, ability for: 1.0" start="16" size="1" access="ReadOnly" />
+      <BitField name="F10" description="blending factor 1,ability for: 0.0" start="17" size="1" access="ReadOnly" />
+      <BitField name="F1P" description="blending factor 1, ability for: pixel_alpha" start="18" size="1" access="ReadOnly" />
+      <BitField name="F11P" description="blending factor 1, ability for: 1.0 - pixel_alpha" start="19" size="1" access="ReadOnly" />
+      <BitField name="F1C" description="blending factor 1, ability for: constant_alpha" start="20" size="1" access="ReadOnly" />
+      <BitField name="F11C" description="blending factor 1, ability for: 1.0 - constant_alpha" start="21" size="1" access="ReadOnly" />
+      <BitField name="F1PC" description="blending factor 1, ability for: pixel_alpha * constant_alpha" start="22" size="1" access="ReadOnly" />
+      <BitField name="F11PC" description="blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="23" size="1" access="ReadOnly" />
+      <BitField name="FF" description="flexible pixel format, ability" start="24" size="1" access="ReadOnly" />
+      <BitField name="RGB888" description="pixel format, ability for rgb888" start="25" size="1" access="ReadOnly" />
+      <BitField name="BGR565" description="pixel format, ability for bgr565" start="26" size="1" access="ReadOnly" />
+      <BitField name="RGB565" description="pixel format, ability for rgb565" start="27" size="1" access="ReadOnly" />
+      <BitField name="BGRA888" description="pixel format, ability for bgra8888" start="28" size="1" access="ReadOnly" />
+      <BitField name="RGBA8888" description="pixel format, ability for rgba8888" start="29" size="1" access="ReadOnly" />
+      <BitField name="ABGR8888" description="pixel format, ability for abgr8888" start="30" size="1" access="ReadOnly" />
+      <BitField name="ARGB8888" description="pixel format, ability for argb8888" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_L2C1R" description="LTDC layerx configuration 1 register" start="+0x204" size="4" reset_value="0x80000001" reset_mask="0xFFFFFFFF">
+      <BitField name="YIA" description="YCbCr 422 interleaved ability for that layer" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="interleaved not available" start="0x0" />
+        <Enum name="B_0x1" description="interleaved available" start="0x1" />
+      </BitField>
+      <BitField name="YSPA" description="YCbCr 420 semi-planar ability for that layer" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semi-planar not available" start="0x0" />
+        <Enum name="B_0x1" description="semi-planar available" start="0x1" />
+      </BitField>
+      <BitField name="YFPA" description="YCbCr 420 full-planar ability for that layer" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="full planar not available" start="0x0" />
+        <Enum name="B_0x1" description="full planar available" start="0x1" />
+      </BitField>
+      <BitField name="SCA" description="scaling ability for that layer" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="scaling not available" start="0x0" />
+        <Enum name="B_0x1" description="scaling available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2RCR" description="LTDC layerx reload control register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+      <BitField name="GRMSK" description="shadow reload control, global (centralized) reload masked" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="global reload active for this layer (control from LTDC_SRCR enabled)" start="0x0" />
+        <Enum name="B_0x1" description="global reload masked for this layer (control from LTDC_SRCR disabled)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CR" description="LTDC layerx control register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEN" description="layer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer disabled" start="0x0" />
+        <Enum name="B_0x1" description="layer enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN" description="color keying enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color keying disabled" start="0x0" />
+        <Enum name="B_0x1" description="color keying enabled: if RGB matches, then the ARGB are set to 0." start="0x1" />
+      </BitField>
+      <BitField name="CLUTEN" description="color look-up table enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color look-up table disabled" start="0x0" />
+        <Enum name="B_0x1" description="color look-up table enabled" start="0x1" />
+      </BitField>
+      <BitField name="HMEN" description="horizontal mirroring enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="mirror disabled" start="0x0" />
+        <Enum name="B_0x1" description="mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299)" start="0x1" />
+      </BitField>
+      <BitField name="DCBEN" description="default color blending enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blending disabled" start="0x0" />
+        <Enum name="B_0x1" description="blending enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2WHPCR" description="LTDC layerx window horizontal position configuration register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSTPOS" description="window horizontal start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WHSPPOS" description="window horizontal stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2WVPCR" description="LTDC layerx window vertical position configuration register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSTPOS" description="window vertical start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WVSPPOS" description="window vertical stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CKCR" description="LTDC layerx color keying configuration register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKBLUE" description="color key blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="CKGREEN" description="color key green value" start="8" size="8" access="Read/Write" />
+      <BitField name="CKRED" description="color key red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2PFCR" description="LTDC layerx pixel format configuration register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="pixel format" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888 (32 bpp)" start="0x0" />
+        <Enum name="B_0x1" description="ABGR888 (32 bpp)" start="0x1" />
+        <Enum name="B_0x2" description="RGBA888 (32 bpp)" start="0x2" />
+        <Enum name="B_0x3" description="BGRA8888 (32 bpp)" start="0x3" />
+        <Enum name="B_0x4" description="RGB565 (16 bpp, A = 255)" start="0x4" />
+        <Enum name="B_0x5" description="BGR565 (16 bpp, A = 255)" start="0x5" />
+        <Enum name="B_0x6" description="RGB888 (24 bpp packed, A = 255)" start="0x6" />
+        <Enum name="B_0x7" description="Flexible pixel format selected (see Section 38.7.50 and Section 38.7.51)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CACR" description="LTDC layerx constant alpha configuration register" start="+0x220" size="4" reset_value="0x000000FF" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="constant alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2DCCR" description="LTDC layerx default color configuration register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCBLUE" description="default color blue" start="0" size="8" access="Read/Write" />
+      <BitField name="DCGREEN" description="default color green" start="8" size="8" access="Read/Write" />
+      <BitField name="DCRED" description="default color red" start="16" size="8" access="Read/Write" />
+      <BitField name="DCALPHA" description="default color alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2BFCR" description="LTDC layerx blending factors configuration register" start="+0x228" size="4" reset_value="0x00010607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF2" description="blending factor 2 " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x5" description="1 - constant alpha" start="0x5" />
+        <Enum name="B_0x7" description="1 - (pixel alpha x constant alpha)" start="0x7" />
+      </BitField>
+      <BitField name="BF1" description="blending factor 1" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="constant alpha" start="0x4" />
+        <Enum name="B_0x6" description="pixel alpha x constant alpha" start="0x6" />
+      </BitField>
+      <BitField name="BOR" description="blending order" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer set in background" start="0x0" />
+        <Enum name="B_0x1" description="layer set in foreground" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2BLCR" description="LTDC layerx burst length configuration register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BL" description="burst length" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="maximum burst length (16 words 64 bits, thus 128 Bytes)" start="0x00" />
+        <Enum name="B_0x01" description="1 word (of 64 bits) per burst" start="0x01" />
+        <Enum name="B_0x10" description="16 words (of 64 bits) per burst" start="0x10" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2PCR" description="LTDC layerx planar configuration register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="YCEN" description="YCbCr-to-RGB conversion enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="YCbCr conversion enabled, using the YCM setting above" start="0x1" />
+      </BitField>
+      <BitField name="YCM" description="YCbCr conversion mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)" start="0x0" />
+        <Enum name="B_0x1" description="semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x1" />
+        <Enum name="B_0x2" description="full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x2" />
+      </BitField>
+      <BitField name="YF" description="Y component first" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Y component disabled (thus Cr or Cb component is on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="Y component enabled (thus Y component is on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="CBF" description="Cb component first" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb disabled (thus Cr component is on byte 0 and 1)" start="0x0" />
+        <Enum name="B_0x1" description="Cb enabled (thus Cb component is on byte 0 and 1)" start="0x1" />
+      </BitField>
+      <BitField name="OF" description="Odd pixel first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="odd pixel disabled (thus even pixel on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="odd pixel enabled (thus odd pixel on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="YREN" description="Y rescale enable for the color dynamic range" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="rescaling disabled (input component thus assumed provided in 0 to 255)" start="0x0" />
+        <Enum name="B_0x1" description="rescaling enabled (input component thus assumed provided in 16 to 235)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CFBAR" description="LTDC layerx color frame buffer address register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="color frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CFBLR" description="LTDC layerx color frame buffer length register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLL" description="color frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="CFBP" description="color frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CFBLNR" description="LTDC layerx color frame buffer line number register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CLUTWR" description="LTDC layerx CLUT write register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="blue value" start="0" size="8" access="WriteOnly" />
+      <BitField name="GREEN" description="green value" start="8" size="8" access="WriteOnly" />
+      <BitField name="RED" description="red value" start="16" size="8" access="WriteOnly" />
+      <BitField name="CLUTADD" description="CLUT address" start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="LTDC_L2CYR0R" description="LTDC layerx conversion YCbCr RGB 0 register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2R" description="Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2B" description="Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CYR1R" description="LTDC layerx conversion YCbCr RGB 1 register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2G" description="Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2G" description="Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2FPF0R" description="LTDC layerx flexible pixel format 0 register" start="+0x274" size="4" reset_value="0x00011100" reset_mask="0xFFFFFFFF">
+      <BitField name="APOS" description="Location of the Alpha component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="ALEN" description="Width of the Alpha component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="RPOS" description="Location of the Red component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="RLEN" description="Width of the Red component (in bits)" start="14" size="4" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2FPF1R" description="LTDC layerx flexible pixel format 1 register" start="+0x278" size="4" reset_value="0x00093110" reset_mask="0xFFFFFFFF">
+      <BitField name="GPOS" description="Location of the Green component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="GLEN" description="Width of the Green component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="BPOS" description="Location of the Blue component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="BLEN" description="Width of the Blue component (in bits)" start="14" size="4" access="Read/Write" />
+      <BitField name="PSIZE" description="Pixel size (in bytes)" start="18" size="3" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LTDC_S" description="LCD-TFT display controller" start="0x58001000">
+    <Register name="LTDC_SSCR" description="LTDC synchronization size configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VSH" description="vertical synchronization height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="HSW" description="horizontal synchronization width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_BPCR" description="LTDC back porch configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AVBP" description="accumulated Vertical back porch (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="AHBP" description="accumulated horizontal back porch (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_AWCR" description="LTDC active width configuration register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AAH" description="accumulated active height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="AAW" description="accumulated active width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_TWCR" description="LTDC total width configuration register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOTALH" description="total height (in units of horizontal scan line)" start="0" size="16" access="Read/Write" />
+      <BitField name="TOTALW" description="total width (in units of pixel clock period)" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_GCR" description="LTDC global control register" start="+0x018" size="4" reset_value="0x00002220" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC global enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC disabled" start="0x0" />
+        <Enum name="B_0x1" description="LTDC enabled" start="0x1" />
+      </BitField>
+      <BitField name="GAMEN" description="Gamma correction enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Gamma correction disabled (pixels bypass the gamma operator)" start="0x0" />
+        <Enum name="B_0x1" description="Gamma correction enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBW" description="dither blue width" start="4" size="3" access="ReadOnly" />
+      <BitField name="DGW" description="dither green width" start="8" size="3" access="ReadOnly" />
+      <BitField name="DRW" description="dither red width" start="12" size="3" access="ReadOnly" />
+      <BitField name="DEN" description="dither enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dither disabled" start="0x0" />
+        <Enum name="B_0x1" description="dither enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEN" description="CRC enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC enabled" start="0x1" />
+      </BitField>
+      <BitField name="SFEN" description="single-frame mode: mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="single-frame disabled: a trigger (on SFSWTR) generates a continuous flow." start="0x0" />
+        <Enum name="B_0x1" description="single-frame enabled: a trigger (on SFSWTR) generates a single frame." start="0x1" />
+      </BitField>
+      <BitField name="SFSWTR" description="single-frame mode: software trigger" start="25" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action" start="0x0" />
+        <Enum name="B_0x1" description="triggers one frame" start="0x1" />
+      </BitField>
+      <BitField name="PCPOL" description="pixel clock polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the pixel and sync data are generated at the rising-edge of the output LCD_CLK clock." start="0x0" />
+        <Enum name="B_0x1" description="the pixel and sync data are generated at the falling-edge of the output LCD_CLK clock." start="0x1" />
+      </BitField>
+      <BitField name="DEPOL" description="blanking (no data/pixel) polarity" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blanking (no data/pixel) polarity is active low." start="0x0" />
+        <Enum name="B_0x1" description="blanking (no data/pixel) polarity is active high." start="0x1" />
+      </BitField>
+      <BitField name="VSPOL" description="vertical synchronization polarity" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vertical synchronization is active low." start="0x0" />
+        <Enum name="B_0x1" description="vertical synchronization is active high." start="0x1" />
+      </BitField>
+      <BitField name="HSPOL" description="horizontal synchronization polarity" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="horizontal synchronization polarity is active low." start="0x0" />
+        <Enum name="B_0x1" description="horizontal synchronization polarity is active high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_GC1R" description="LTDC global configuration 1 register" start="+0x01C" size="4" reset_value="0x6BE4D888" reset_mask="0xFFFFFFFF">
+      <BitField name="WBCH" description="width of blue channel output" start="0" size="4" access="ReadOnly" />
+      <BitField name="WGCH" description="width of green channel output" start="4" size="4" access="ReadOnly" />
+      <BitField name="WRCH" description="width of red channel output" start="8" size="4" access="ReadOnly" />
+      <BitField name="PRBA" description="precise blending ability" start="12" size="1" access="ReadOnly" />
+      <BitField name="DT" description="dithering technique implemented" start="14" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no dithering" start="0x0" />
+        <Enum name="B_0x1" description="ordered 4x4 Bayer" start="0x1" />
+        <Enum name="B_0x3" description="pseudo-random LFSR" start="0x3" />
+      </BitField>
+      <BitField name="GCT" description="gamma correction technique implemented" start="17" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="no gamma" start="0x0" />
+        <Enum name="B_0x1" description="gamma with 256 samples" start="0x1" />
+        <Enum name="B_0x2" description="gamma with 8 interpolated segments" start="0x2" />
+      </BitField>
+      <BitField name="SHRA" description="shadow registers ability" start="21" size="1" access="ReadOnly" />
+      <BitField name="BCP" description="background color programmability (unique color blended as background)" start="22" size="1" access="ReadOnly" />
+      <BitField name="BBA" description="background blending ability" start="23" size="1" access="ReadOnly" />
+      <BitField name="LNIP" description="line-IRQ: line position programmability" start="24" size="1" access="ReadOnly" />
+      <BitField name="TP" description="timing programmability" start="25" size="1" access="ReadOnly" />
+      <BitField name="SPP" description="sync polarity programmability" start="27" size="1" access="ReadOnly" />
+      <BitField name="DWP" description="dither width programmability" start="28" size="1" access="ReadOnly" />
+      <BitField name="STRA" description="status register ability" start="29" size="1" access="ReadOnly" />
+      <BitField name="CRMA" description="configuration reading mode ability" start="30" size="1" access="ReadOnly" />
+      <BitField name="BMA" description="blind mode ability" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_GC2R" description="LTDC global configuration 2 register" start="+0x020" size="4" reset_value="0x0000BB30" reset_mask="0xFFFFFFFF">
+      <BitField name="BLA" description="background layer ability (pixels of background layer are read from memory)" start="0" size="1" access="ReadOnly" />
+      <BitField name="STSA" description="slave timings synchronization ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="DVA" description="dual-view ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="DPA" description="secondary RGB output port ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="BW" description="bus width (log2 of number of bytes)" start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x2" description="32-bit bus" start="0x2" />
+        <Enum name="B_0x3" description="64-bit bus" start="0x3" />
+        <Enum name="B_0x4" description="128-bit bus" start="0x4" />
+      </BitField>
+      <BitField name="EDCA" description="external display control ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="OCA" description="output conversion ability (RGB to YCbCr)" start="8" size="1" access="ReadOnly" />
+      <BitField name="AXIIDA" description="AXIID ability" start="9" size="1" access="ReadOnly" />
+      <BitField name="ROTA" description="rotation support ability" start="10" size="1" access="ReadOnly" />
+      <BitField name="SISA" description="second interrupt set ability" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="second interrupt set not available" start="0x0" />
+        <Enum name="B_0x1" description="second interrupt set available" start="0x1" />
+      </BitField>
+      <BitField name="SFA" description="single frame mode ability" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="single frame not available" start="0x0" />
+        <Enum name="B_0x1" description="single frame available" start="0x1" />
+      </BitField>
+      <BitField name="CRCA" description="CRC ability" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CRC no computation available" start="0x0" />
+        <Enum name="B_0x1" description="CRC computation available" start="0x1" />
+      </BitField>
+      <BitField name="BOA" description="blending order ability" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="blending order fixed" start="0x0" />
+        <Enum name="B_0x1" description="blending order configurable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_SRCR" description="LTDC shadow reload configuration register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_GCCR" description="LTDC gamma correction configuration register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDR" description="address of the R,G,B table where the COMP component is written" start="0" size="8" access="WriteOnly" />
+      <BitField name="COMP" description="color component to be written, in either (or all) the R,G,B tables" start="8" size="8" access="WriteOnly" />
+      <BitField name="BEN" description="write trigger to the blue table" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the blue table." start="0x1" />
+      </BitField>
+      <BitField name="GEN" description="write trigger to the green table" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the green table." start="0x1" />
+      </BitField>
+      <BitField name="REN" description="write trigger to the red table" start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no action done" start="0x0" />
+        <Enum name="B_0x1" description="COMP is written at ADDR in the red table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_BCCR" description="LTDC background color configuration register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCBLUE" description="background color blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="BCGREEN" description="background color green value" start="8" size="8" access="Read/Write" />
+      <BitField name="BCRED" description="background color red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_IER" description="LTDC interrupt enable register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIE" description="Line interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUWIE" description="FIFO underrun warning interrupt enable " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transfer Error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="transfer error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RRIE" description="Register reload interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="register reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUIE" description="FIFO underrun interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC error disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ISR" description="LTDC interrupt status register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIF" description="Line interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no line interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt generated when a programmed line is reached" start="0x1" />
+      </BitField>
+      <BitField name="FUWIF" description="FIFO underrun warning interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun warning interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TERRIF" description="Transfer error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+      <BitField name="RRIF" description="Register reload interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no register reload interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)" start="0x1" />
+      </BitField>
+      <BitField name="FUIF" description="FIFO underrun interrupt flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CRCIF" description="CRC error interrupt flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ICR" description="LTDC interrupt clear register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLIF" description="clears the line interrupt flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the LIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CFUWIF" description="clears the FIFO underrun warning interrupt flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUWIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CTERRIF" description="clears the transfer error interrupt flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the TERRIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CRRIF" description="clears register reload interrupt flag" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the RRIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CFUIF" description="clears the FIFO underrun interrupt flag" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+      <BitField name="CCRCIF" description="clears the CRC error interrupt flag" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the CRCIF flag in LTDC_ISR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_LIPCR" description="LTDC line interrupt position configuration register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIPOS" description="line interrupt position" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_CPSR" description="LTDC current position status register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CYPOS" description="current Y position " start="0" size="16" access="ReadOnly" />
+      <BitField name="CXPOS" description="current X position " start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_CDSR" description="LTDC current display status register" start="+0x048" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="VDES" description="vertical data enable display status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="HDES" description="horizontal data enable display status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="VSYNCS" description="vertical synchronization display status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+      <BitField name="HSYNCS" description="horizontal synchronization display status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="active low" start="0x0" />
+        <Enum name="B_0x1" description="active high" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_EDCR" description="LTDC external display control register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCYEN" description="output conversion to YCbCr 422 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="OCYSEL" description="output conversion to YCbCr 422" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="use ITU-R BT.601 set (for typically SDTV analog-like displays)" start="0x0" />
+        <Enum name="B_0x1" description="use ITU-R BT.709 set (for typically HDTV digital-like displays)" start="0x1" />
+      </BitField>
+      <BitField name="OCYCO" description="output conversion to YCbCr 422" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb is output first (Y0Cb, then Y1Cr, Y2Cb and so on)." start="0x0" />
+        <Enum name="B_0x1" description="Cr is output first (Y0Cr, then Y1Cb, Y2Cr and so on)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_IER2" description="LTDC interrupt enable register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIE" description="Line interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="line interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUWIE" description="FIFO underrun warning interrupt enable " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transfer error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="transfer error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RRIE" description="Register reload interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="register reload interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FUIE" description="FIFO underrun interrupt enable " start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO underrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun Interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC error disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ISR2" description="LTDC interrupt status register 2" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIF" description="Line interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no line interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="line interrupt generated when a programmed line is reached" start="0x1" />
+      </BitField>
+      <BitField name="FUWIF" description="FIFO underrun warning interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun warning interrupt generated." start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="TERRIF" description="Transfer error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no transfer error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="transfer error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+      <BitField name="RRIF" description="Register reload interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no register reload interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)" start="0x1" />
+      </BitField>
+      <BitField name="FUIF" description="FIFO underrun interrupt flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no FIFO underrun interrupt generated." start="0x0" />
+        <Enum name="B_0x1" description="FIFO underrun interrupt generated, if one of the layer FIFO is empty and many pixel data are read from the FIFO" start="0x1" />
+      </BitField>
+      <BitField name="CRCIF" description="CRC Error interrupt flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error interrupt generated" start="0x0" />
+        <Enum name="B_0x1" description="CRC error interrupt generated when a bus error occurs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_ICR2" description="LTDC interrupt clear register 2" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLIF" description="clears the Line interrupt flag" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the LIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CFUWIF" description="clears the FIFO underrun warning interrupt flag" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUWIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CTERRIF" description="clears the Transfer Error interrupt flag" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the TERRIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CRRIF" description="clears register reload interrupt flag" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the RRIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CFUIF" description="clears the FIFO underrun interrupt flag" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the FUIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+      <BitField name="CCRCIF" description="clears the CRC error interrupt flag" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="clears the CRCIF flag in LTDC_ISR2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_LIPCR2" description="LTDC line interrupt position configuration register 2" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIPOS" description="line interrupt position" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_ECRCR" description="LTDC expected CRC register" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECRC" description="expected CRC of frame" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_CCRCR" description="LTDC computed CRC register" start="+0x07C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRC" description="computed CRC of frame" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_FUTR" description="LTDC FIFO underrun threshold register" start="+0x090" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="THRE" description="threshold to trigger a FIFO underrun interrupt (per FIFO word, 64 bits)" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1C0R" description="LTDC layerx configuration 0 register" start="+0x100" size="4" reset_value="0xFF50A076" reset_mask="0xFFFFFFFF">
+      <BitField name="CKTA" description="color key transparency ability" start="0" size="1" access="ReadOnly" />
+      <BitField name="CFBDA" description="color frame buffer duplication ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFBPA" description="color frame buffer pitch ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="APA" description="alpha plane ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="DCP" description="default color programmability" start="4" size="1" access="ReadOnly" />
+      <BitField name="WINA" description="windowing ability" start="5" size="1" access="ReadOnly" />
+      <BitField name="CLUTA" description="CLUT ability" start="6" size="1" access="ReadOnly" />
+      <BitField name="CKRA" description="color key replace ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="F21" description="blending factor 2, ability for: 1.0" start="8" size="1" access="ReadOnly" />
+      <BitField name="F20" description="blending factor 2, ability for: 0.0" start="9" size="1" access="ReadOnly" />
+      <BitField name="F2P" description="blending factor 2, ability for: pixel_alpha" start="10" size="1" access="ReadOnly" />
+      <BitField name="F21P" description="blending factor 2, ability for: 1.0 - pixel_alpha" start="11" size="1" access="ReadOnly" />
+      <BitField name="F2C" description="blending factor 2, ability for: constant_alpha" start="12" size="1" access="ReadOnly" />
+      <BitField name="F21C" description="blending factor 2, ability for: 1.0 - constant_alpha" start="13" size="1" access="ReadOnly" />
+      <BitField name="F2PC" description="blending factor 2, ability for: pixel_alpha * constant_alpha" start="14" size="1" access="ReadOnly" />
+      <BitField name="F21PC" description="blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="15" size="1" access="ReadOnly" />
+      <BitField name="F11" description="blending factor 1, ability for: 1.0" start="16" size="1" access="ReadOnly" />
+      <BitField name="F10" description="blending factor 1,ability for: 0.0" start="17" size="1" access="ReadOnly" />
+      <BitField name="F1P" description="blending factor 1, ability for: pixel_alpha" start="18" size="1" access="ReadOnly" />
+      <BitField name="F11P" description="blending factor 1, ability for: 1.0 - pixel_alpha" start="19" size="1" access="ReadOnly" />
+      <BitField name="F1C" description="blending factor 1, ability for: constant_alpha" start="20" size="1" access="ReadOnly" />
+      <BitField name="F11C" description="blending factor 1, ability for: 1.0 - constant_alpha" start="21" size="1" access="ReadOnly" />
+      <BitField name="F1PC" description="blending factor 1, ability for: pixel_alpha * constant_alpha" start="22" size="1" access="ReadOnly" />
+      <BitField name="F11PC" description="blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="23" size="1" access="ReadOnly" />
+      <BitField name="FF" description="flexible pixel format, ability" start="24" size="1" access="ReadOnly" />
+      <BitField name="RGB888" description="pixel format, ability for rgb888" start="25" size="1" access="ReadOnly" />
+      <BitField name="BGR565" description="pixel format, ability for bgr565" start="26" size="1" access="ReadOnly" />
+      <BitField name="RGB565" description="pixel format, ability for rgb565" start="27" size="1" access="ReadOnly" />
+      <BitField name="BGRA888" description="pixel format, ability for bgra8888" start="28" size="1" access="ReadOnly" />
+      <BitField name="RGBA8888" description="pixel format, ability for rgba8888" start="29" size="1" access="ReadOnly" />
+      <BitField name="ABGR8888" description="pixel format, ability for abgr8888" start="30" size="1" access="ReadOnly" />
+      <BitField name="ARGB8888" description="pixel format, ability for argb8888" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_L1C1R" description="LTDC layerx configuration 1 register" start="+0x104" size="4" reset_value="0x80000007" reset_mask="0xFFFFFFFF">
+      <BitField name="YIA" description="YCbCr 422 interleaved ability for that layer" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="interleaved not available" start="0x0" />
+        <Enum name="B_0x1" description="interleaved available" start="0x1" />
+      </BitField>
+      <BitField name="YSPA" description="YCbCr 420 semi-planar ability for that layer" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semi-planar not available" start="0x0" />
+        <Enum name="B_0x1" description="semi-planar available" start="0x1" />
+      </BitField>
+      <BitField name="YFPA" description="YCbCr 420 full-planar ability for that layer" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="full planar not available" start="0x0" />
+        <Enum name="B_0x1" description="full planar available" start="0x1" />
+      </BitField>
+      <BitField name="SCA" description="scaling ability for that layer" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="scaling not available" start="0x0" />
+        <Enum name="B_0x1" description="scaling available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1RCR" description="LTDC layerx reload control register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+      <BitField name="GRMSK" description="shadow reload control, global (centralized) reload masked" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="global reload active for this layer (control from LTDC_SRCR enabled)" start="0x0" />
+        <Enum name="B_0x1" description="global reload masked for this layer (control from LTDC_SRCR disabled)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CR" description="LTDC layerx control register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEN" description="layer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer disabled" start="0x0" />
+        <Enum name="B_0x1" description="layer enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN" description="color keying enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color keying disabled" start="0x0" />
+        <Enum name="B_0x1" description="color keying enabled: if RGB matches, then the ARGB are set to 0." start="0x1" />
+      </BitField>
+      <BitField name="CLUTEN" description="color look-up table enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color look-up table disabled" start="0x0" />
+        <Enum name="B_0x1" description="color look-up table enabled" start="0x1" />
+      </BitField>
+      <BitField name="HMEN" description="horizontal mirroring enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="mirror disabled" start="0x0" />
+        <Enum name="B_0x1" description="mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299)" start="0x1" />
+      </BitField>
+      <BitField name="DCBEN" description="default color blending enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blending disabled" start="0x0" />
+        <Enum name="B_0x1" description="blending enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1WHPCR" description="LTDC layerx window horizontal position configuration register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSTPOS" description="window horizontal start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WHSPPOS" description="window horizontal stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1WVPCR" description="LTDC layerx window vertical position configuration register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSTPOS" description="window vertical start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WVSPPOS" description="window vertical stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CKCR" description="LTDC layerx color keying configuration register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKBLUE" description="color key blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="CKGREEN" description="color key green value" start="8" size="8" access="Read/Write" />
+      <BitField name="CKRED" description="color key red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1PFCR" description="LTDC layerx pixel format configuration register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="pixel format" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888 (32 bpp)" start="0x0" />
+        <Enum name="B_0x1" description="ABGR888 (32 bpp)" start="0x1" />
+        <Enum name="B_0x2" description="RGBA888 (32 bpp)" start="0x2" />
+        <Enum name="B_0x3" description="BGRA8888 (32 bpp)" start="0x3" />
+        <Enum name="B_0x4" description="RGB565 (16 bpp, A = 255)" start="0x4" />
+        <Enum name="B_0x5" description="BGR565 (16 bpp, A = 255)" start="0x5" />
+        <Enum name="B_0x6" description="RGB888 (24 bpp packed, A = 255)" start="0x6" />
+        <Enum name="B_0x7" description="Flexible pixel format selected (see Section 38.7.50 and Section 38.7.51)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CACR" description="LTDC layerx constant alpha configuration register" start="+0x120" size="4" reset_value="0x000000FF" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="constant alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1DCCR" description="LTDC layerx default color configuration register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCBLUE" description="default color blue" start="0" size="8" access="Read/Write" />
+      <BitField name="DCGREEN" description="default color green" start="8" size="8" access="Read/Write" />
+      <BitField name="DCRED" description="default color red" start="16" size="8" access="Read/Write" />
+      <BitField name="DCALPHA" description="default color alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1BFCR" description="LTDC layerx blending factors configuration register" start="+0x128" size="4" reset_value="0x00000607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF2" description="blending factor 2 " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x5" description="1 - constant alpha" start="0x5" />
+        <Enum name="B_0x7" description="1 - (pixel alpha x constant alpha)" start="0x7" />
+      </BitField>
+      <BitField name="BF1" description="blending factor 1" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="constant alpha" start="0x4" />
+        <Enum name="B_0x6" description="pixel alpha x constant alpha" start="0x6" />
+      </BitField>
+      <BitField name="BOR" description="blending order" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer set in background" start="0x0" />
+        <Enum name="B_0x1" description="layer set in foreground" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1BLCR" description="LTDC layerx burst length configuration register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BL" description="burst length" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="maximum burst length (16 words 64 bits, thus 128 Bytes)" start="0x00" />
+        <Enum name="B_0x01" description="1 word (of 64 bits) per burst" start="0x01" />
+        <Enum name="B_0x10" description="16 words (of 64 bits) per burst" start="0x10" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1PCR" description="LTDC layerx planar configuration register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="YCEN" description="YCbCr-to-RGB conversion enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="YCbCr conversion enabled, using the YCM setting above" start="0x1" />
+      </BitField>
+      <BitField name="YCM" description="YCbCr conversion mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)" start="0x0" />
+        <Enum name="B_0x1" description="semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x1" />
+        <Enum name="B_0x2" description="full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x2" />
+      </BitField>
+      <BitField name="YF" description="Y component first" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Y component disabled (thus Cr or Cb component is on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="Y component enabled (thus Y component is on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="CBF" description="Cb component first" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb disabled (thus Cr component is on byte 0 and 1)" start="0x0" />
+        <Enum name="B_0x1" description="Cb enabled (thus Cb component is on byte 0 and 1)" start="0x1" />
+      </BitField>
+      <BitField name="OF" description="Odd pixel first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="odd pixel disabled (thus even pixel on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="odd pixel enabled (thus odd pixel on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="YREN" description="Y rescale enable for the color dynamic range" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="rescaling disabled (input component thus assumed provided in 0 to 255)" start="0x0" />
+        <Enum name="B_0x1" description="rescaling enabled (input component thus assumed provided in 16 to 235)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L1CFBAR" description="LTDC layerx color frame buffer address register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="color frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CFBLR" description="LTDC layerx color frame buffer length register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLL" description="color frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="CFBP" description="color frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CFBLNR" description="LTDC layerx color frame buffer line number register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBA0R" description="LTDC layer1 auxiliary frame buffer address 0 register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBADD0" description="frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBA1R" description="LTDC layer1 auxiliary frame buffer address 1 register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBADD1" description="auxiliary frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBLR" description="LTDC layer1 auxiliary frame buffer length register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBLL" description="auxiliary frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="AFBP" description="auxiliary frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1AFBLNR" description="LTDC layer1 auxiliary frame buffer line number register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFBLNBR" description="auxiliary frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CLUTWR" description="LTDC layerx CLUT write register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="blue value" start="0" size="8" access="WriteOnly" />
+      <BitField name="GREEN" description="green value" start="8" size="8" access="WriteOnly" />
+      <BitField name="RED" description="red value" start="16" size="8" access="WriteOnly" />
+      <BitField name="CLUTADD" description="CLUT address" start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="LTDC_L1CYR0R" description="LTDC layerx conversion YCbCr RGB 0 register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2R" description="Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2B" description="Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1CYR1R" description="LTDC layerx conversion YCbCr RGB 1 register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2G" description="Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2G" description="Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1FPF0R" description="LTDC layerx flexible pixel format 0 register" start="+0x174" size="4" reset_value="0x00011100" reset_mask="0xFFFFFFFF">
+      <BitField name="APOS" description="Location of the Alpha component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="ALEN" description="Width of the Alpha component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="RPOS" description="Location of the Red component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="RLEN" description="Width of the Red component (in bits)" start="14" size="4" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L1FPF1R" description="LTDC layerx flexible pixel format 1 register" start="+0x178" size="4" reset_value="0x00093110" reset_mask="0xFFFFFFFF">
+      <BitField name="GPOS" description="Location of the Green component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="GLEN" description="Width of the Green component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="BPOS" description="Location of the Blue component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="BLEN" description="Width of the Blue component (in bits)" start="14" size="4" access="Read/Write" />
+      <BitField name="PSIZE" description="Pixel size (in bytes)" start="18" size="3" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2C0R" description="LTDC layerx configuration 0 register" start="+0x200" size="4" reset_value="0xFF50A076" reset_mask="0xFFFFFFFF">
+      <BitField name="CKTA" description="color key transparency ability" start="0" size="1" access="ReadOnly" />
+      <BitField name="CFBDA" description="color frame buffer duplication ability" start="1" size="1" access="ReadOnly" />
+      <BitField name="CFBPA" description="color frame buffer pitch ability" start="2" size="1" access="ReadOnly" />
+      <BitField name="APA" description="alpha plane ability" start="3" size="1" access="ReadOnly" />
+      <BitField name="DCP" description="default color programmability" start="4" size="1" access="ReadOnly" />
+      <BitField name="WINA" description="windowing ability" start="5" size="1" access="ReadOnly" />
+      <BitField name="CLUTA" description="CLUT ability" start="6" size="1" access="ReadOnly" />
+      <BitField name="CKRA" description="color key replace ability" start="7" size="1" access="ReadOnly" />
+      <BitField name="F21" description="blending factor 2, ability for: 1.0" start="8" size="1" access="ReadOnly" />
+      <BitField name="F20" description="blending factor 2, ability for: 0.0" start="9" size="1" access="ReadOnly" />
+      <BitField name="F2P" description="blending factor 2, ability for: pixel_alpha" start="10" size="1" access="ReadOnly" />
+      <BitField name="F21P" description="blending factor 2, ability for: 1.0 - pixel_alpha" start="11" size="1" access="ReadOnly" />
+      <BitField name="F2C" description="blending factor 2, ability for: constant_alpha" start="12" size="1" access="ReadOnly" />
+      <BitField name="F21C" description="blending factor 2, ability for: 1.0 - constant_alpha" start="13" size="1" access="ReadOnly" />
+      <BitField name="F2PC" description="blending factor 2, ability for: pixel_alpha * constant_alpha" start="14" size="1" access="ReadOnly" />
+      <BitField name="F21PC" description="blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="15" size="1" access="ReadOnly" />
+      <BitField name="F11" description="blending factor 1, ability for: 1.0" start="16" size="1" access="ReadOnly" />
+      <BitField name="F10" description="blending factor 1,ability for: 0.0" start="17" size="1" access="ReadOnly" />
+      <BitField name="F1P" description="blending factor 1, ability for: pixel_alpha" start="18" size="1" access="ReadOnly" />
+      <BitField name="F11P" description="blending factor 1, ability for: 1.0 - pixel_alpha" start="19" size="1" access="ReadOnly" />
+      <BitField name="F1C" description="blending factor 1, ability for: constant_alpha" start="20" size="1" access="ReadOnly" />
+      <BitField name="F11C" description="blending factor 1, ability for: 1.0 - constant_alpha" start="21" size="1" access="ReadOnly" />
+      <BitField name="F1PC" description="blending factor 1, ability for: pixel_alpha * constant_alpha" start="22" size="1" access="ReadOnly" />
+      <BitField name="F11PC" description="blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha)" start="23" size="1" access="ReadOnly" />
+      <BitField name="FF" description="flexible pixel format, ability" start="24" size="1" access="ReadOnly" />
+      <BitField name="RGB888" description="pixel format, ability for rgb888" start="25" size="1" access="ReadOnly" />
+      <BitField name="BGR565" description="pixel format, ability for bgr565" start="26" size="1" access="ReadOnly" />
+      <BitField name="RGB565" description="pixel format, ability for rgb565" start="27" size="1" access="ReadOnly" />
+      <BitField name="BGRA888" description="pixel format, ability for bgra8888" start="28" size="1" access="ReadOnly" />
+      <BitField name="RGBA8888" description="pixel format, ability for rgba8888" start="29" size="1" access="ReadOnly" />
+      <BitField name="ABGR8888" description="pixel format, ability for abgr8888" start="30" size="1" access="ReadOnly" />
+      <BitField name="ARGB8888" description="pixel format, ability for argb8888" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LTDC_L2C1R" description="LTDC layerx configuration 1 register" start="+0x204" size="4" reset_value="0x80000001" reset_mask="0xFFFFFFFF">
+      <BitField name="YIA" description="YCbCr 422 interleaved ability for that layer" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="interleaved not available" start="0x0" />
+        <Enum name="B_0x1" description="interleaved available" start="0x1" />
+      </BitField>
+      <BitField name="YSPA" description="YCbCr 420 semi-planar ability for that layer" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="semi-planar not available" start="0x0" />
+        <Enum name="B_0x1" description="semi-planar available" start="0x1" />
+      </BitField>
+      <BitField name="YFPA" description="YCbCr 420 full-planar ability for that layer" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="full planar not available" start="0x0" />
+        <Enum name="B_0x1" description="full planar available" start="0x1" />
+      </BitField>
+      <BitField name="SCA" description="scaling ability for that layer" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="scaling not available" start="0x0" />
+        <Enum name="B_0x1" description="scaling available" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2RCR" description="LTDC layerx reload control register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMR" description="immediate reload trigger" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded immediately." start="0x1" />
+      </BitField>
+      <BitField name="VBR" description="vertical blanking reload request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no effect" start="0x0" />
+        <Enum name="B_0x1" description="The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)." start="0x1" />
+      </BitField>
+      <BitField name="GRMSK" description="shadow reload control, global (centralized) reload masked" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="global reload active for this layer (control from LTDC_SRCR enabled)" start="0x0" />
+        <Enum name="B_0x1" description="global reload masked for this layer (control from LTDC_SRCR disabled)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CR" description="LTDC layerx control register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEN" description="layer enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer disabled" start="0x0" />
+        <Enum name="B_0x1" description="layer enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN" description="color keying enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color keying disabled" start="0x0" />
+        <Enum name="B_0x1" description="color keying enabled: if RGB matches, then the ARGB are set to 0." start="0x1" />
+      </BitField>
+      <BitField name="CLUTEN" description="color look-up table enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="color look-up table disabled" start="0x0" />
+        <Enum name="B_0x1" description="color look-up table enabled" start="0x1" />
+      </BitField>
+      <BitField name="HMEN" description="horizontal mirroring enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="mirror disabled" start="0x0" />
+        <Enum name="B_0x1" description="mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299)" start="0x1" />
+      </BitField>
+      <BitField name="DCBEN" description="default color blending enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="blending disabled" start="0x0" />
+        <Enum name="B_0x1" description="blending enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2WHPCR" description="LTDC layerx window horizontal position configuration register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSTPOS" description="window horizontal start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WHSPPOS" description="window horizontal stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2WVPCR" description="LTDC layerx window vertical position configuration register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSTPOS" description="window vertical start position" start="0" size="16" access="Read/Write" />
+      <BitField name="WVSPPOS" description="window vertical stop position" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CKCR" description="LTDC layerx color keying configuration register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKBLUE" description="color key blue value" start="0" size="8" access="Read/Write" />
+      <BitField name="CKGREEN" description="color key green value" start="8" size="8" access="Read/Write" />
+      <BitField name="CKRED" description="color key red value" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2PFCR" description="LTDC layerx pixel format configuration register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="pixel format" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="ARGB8888 (32 bpp)" start="0x0" />
+        <Enum name="B_0x1" description="ABGR888 (32 bpp)" start="0x1" />
+        <Enum name="B_0x2" description="RGBA888 (32 bpp)" start="0x2" />
+        <Enum name="B_0x3" description="BGRA8888 (32 bpp)" start="0x3" />
+        <Enum name="B_0x4" description="RGB565 (16 bpp, A = 255)" start="0x4" />
+        <Enum name="B_0x5" description="BGR565 (16 bpp, A = 255)" start="0x5" />
+        <Enum name="B_0x6" description="RGB888 (24 bpp packed, A = 255)" start="0x6" />
+        <Enum name="B_0x7" description="Flexible pixel format selected (see Section 38.7.50 and Section 38.7.51)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CACR" description="LTDC layerx constant alpha configuration register" start="+0x220" size="4" reset_value="0x000000FF" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="constant alpha" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2DCCR" description="LTDC layerx default color configuration register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCBLUE" description="default color blue" start="0" size="8" access="Read/Write" />
+      <BitField name="DCGREEN" description="default color green" start="8" size="8" access="Read/Write" />
+      <BitField name="DCRED" description="default color red" start="16" size="8" access="Read/Write" />
+      <BitField name="DCALPHA" description="default color alpha" start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2BFCR" description="LTDC layerx blending factors configuration register" start="+0x228" size="4" reset_value="0x00010607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF2" description="blending factor 2 " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x5" description="1 - constant alpha" start="0x5" />
+        <Enum name="B_0x7" description="1 - (pixel alpha x constant alpha)" start="0x7" />
+      </BitField>
+      <BitField name="BF1" description="blending factor 1" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x4" description="constant alpha" start="0x4" />
+        <Enum name="B_0x6" description="pixel alpha x constant alpha" start="0x6" />
+      </BitField>
+      <BitField name="BOR" description="blending order" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="layer set in background" start="0x0" />
+        <Enum name="B_0x1" description="layer set in foreground" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2BLCR" description="LTDC layerx burst length configuration register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BL" description="burst length" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x00" description="maximum burst length (16 words 64 bits, thus 128 Bytes)" start="0x00" />
+        <Enum name="B_0x01" description="1 word (of 64 bits) per burst" start="0x01" />
+        <Enum name="B_0x10" description="16 words (of 64 bits) per burst" start="0x10" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2PCR" description="LTDC layerx planar configuration register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="YCEN" description="YCbCr-to-RGB conversion enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="YCbCr conversion enabled, using the YCM setting above" start="0x1" />
+      </BitField>
+      <BitField name="YCM" description="YCbCr conversion mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)" start="0x0" />
+        <Enum name="B_0x1" description="semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x1" />
+        <Enum name="B_0x2" description="full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers)." start="0x2" />
+      </BitField>
+      <BitField name="YF" description="Y component first" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Y component disabled (thus Cr or Cb component is on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="Y component enabled (thus Y component is on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="CBF" description="Cb component first" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cb disabled (thus Cr component is on byte 0 and 1)" start="0x0" />
+        <Enum name="B_0x1" description="Cb enabled (thus Cb component is on byte 0 and 1)" start="0x1" />
+      </BitField>
+      <BitField name="OF" description="Odd pixel first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="odd pixel disabled (thus even pixel on byte 0)" start="0x0" />
+        <Enum name="B_0x1" description="odd pixel enabled (thus odd pixel on byte 0)" start="0x1" />
+      </BitField>
+      <BitField name="YREN" description="Y rescale enable for the color dynamic range" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="rescaling disabled (input component thus assumed provided in 0 to 255)" start="0x0" />
+        <Enum name="B_0x1" description="rescaling enabled (input component thus assumed provided in 16 to 235)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LTDC_L2CFBAR" description="LTDC layerx color frame buffer address register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="color frame buffer start address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CFBLR" description="LTDC layerx color frame buffer length register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLL" description="color frame buffer line length" start="0" size="16" access="Read/Write" />
+      <BitField name="CFBP" description="color frame buffer pitch in bytes" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CFBLNR" description="LTDC layerx color frame buffer line number register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="frame buffer line number " start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CLUTWR" description="LTDC layerx CLUT write register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="blue value" start="0" size="8" access="WriteOnly" />
+      <BitField name="GREEN" description="green value" start="8" size="8" access="WriteOnly" />
+      <BitField name="RED" description="red value" start="16" size="8" access="WriteOnly" />
+      <BitField name="CLUTADD" description="CLUT address" start="24" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="LTDC_L2CYR0R" description="LTDC layerx conversion YCbCr RGB 0 register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2R" description="Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2B" description="Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2CYR1R" description="LTDC layerx conversion YCbCr RGB 1 register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR2G" description="Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="0" size="10" access="Read/Write" />
+      <BitField name="CB2G" description="Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals." start="16" size="10" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2FPF0R" description="LTDC layerx flexible pixel format 0 register" start="+0x274" size="4" reset_value="0x00011100" reset_mask="0xFFFFFFFF">
+      <BitField name="APOS" description="Location of the Alpha component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="ALEN" description="Width of the Alpha component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="RPOS" description="Location of the Red component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="RLEN" description="Width of the Red component (in bits)" start="14" size="4" access="Read/Write" />
+    </Register>
+    <Register name="LTDC_L2FPF1R" description="LTDC layerx flexible pixel format 1 register" start="+0x278" size="4" reset_value="0x00093110" reset_mask="0xFFFFFFFF">
+      <BitField name="GPOS" description="Location of the Green component inside the pixel memory word (in bits)" start="0" size="5" access="Read/Write" />
+      <BitField name="GLEN" description="Width of the Green component (in bits)" start="5" size="4" access="Read/Write" />
+      <BitField name="BPOS" description="Location of the Blue component inside the pixel memory word (in bits)" start="9" size="5" access="Read/Write" />
+      <BitField name="BLEN" description="Width of the Blue component (in bits)" start="14" size="4" access="Read/Write" />
+      <BitField name="PSIZE" description="Pixel size (in bytes)" start="18" size="3" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM1" description="Low-power timer" start="0x40002400">
+    <Register name="LPTIM1_ISR_OUTPUT" description="LPTIM1 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_ISR_INPUT" description="LPTIM1 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_ICR_OUTPUT" description="LPTIM1 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM1_ICR_INPUT" description="LPTIM1 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM1_DIER_OUTPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_DIER_INPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CFGR" description="LPTIM1 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CR" description="LPTIM1 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CCR1" description="LPTIM1 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_ARR" description="LPTIM1 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CNT" description="LPTIM1 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_CFGR2" description="LPTIM1 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_RCR" description="LPTIM1 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CCMR1" description="LPTIM1 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CCR2" description="LPTIM1 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM1_S" description="Low-power timer" start="0x50002400">
+    <Register name="LPTIM1_ISR_OUTPUT" description="LPTIM1 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_ISR_INPUT" description="LPTIM1 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_ICR_OUTPUT" description="LPTIM1 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM1_ICR_INPUT" description="LPTIM1 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM1_DIER_OUTPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_DIER_INPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CFGR" description="LPTIM1 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CR" description="LPTIM1 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CCR1" description="LPTIM1 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_ARR" description="LPTIM1 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CNT" description="LPTIM1 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM1_CFGR2" description="LPTIM1 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_RCR" description="LPTIM1 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM1_CCMR1" description="LPTIM1 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM1_CCR2" description="LPTIM1 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM2" description="Low-power timer" start="0x46002400">
+    <Register name="LPTIM2_ISR_OUTPUT" description="LPTIM2 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_ISR_INPUT" description="LPTIM2 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_ICR_OUTPUT" description="LPTIM2 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM2_ICR_INPUT" description="LPTIM2 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM2_DIER_OUTPUT" description="LPTIM2 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_DIER_INPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CFGR" description="LPTIM2 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CR" description="LPTIM2 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CCR1" description="LPTIM2 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_ARR" description="LPTIM2 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CNT" description="LPTIM2 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_CFGR2" description="LPTIM2 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_RCR" description="LPTIM2 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CCMR1" description="LPTIM2 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CCR2" description="LPTIM2 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM2_S" description="Low-power timer" start="0x56002400">
+    <Register name="LPTIM2_ISR_OUTPUT" description="LPTIM2 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_ISR_INPUT" description="LPTIM2 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_ICR_OUTPUT" description="LPTIM2 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM2_ICR_INPUT" description="LPTIM2 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM2_DIER_OUTPUT" description="LPTIM2 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_DIER_INPUT" description="LPTIM1 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CFGR" description="LPTIM2 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CR" description="LPTIM2 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CCR1" description="LPTIM2 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_ARR" description="LPTIM2 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CNT" description="LPTIM2 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM2_CFGR2" description="LPTIM2 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_RCR" description="LPTIM2 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM2_CCMR1" description="LPTIM2 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM2_CCR2" description="LPTIM2 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM3" description="Low-power timer" start="0x46002800">
+    <Register name="LPTIM3_ISR_OUTPUT" description="LPTIM3 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_ISR_INPUT" description="LPTIM3 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_ICR_OUTPUT" description="LPTIM3 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM3_ICR_INPUT" description="LPTIM3 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM3_DIER_OUTPUT" description="LPTIM3 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_DIER_INPUT" description="LPTIM3 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CFGR" description="LPTIM3 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CR" description="LPTIM3 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CCR1" description="LPTIM3 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_ARR" description="LPTIM3 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CNT" description="LPTIM3 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_CFGR2" description="LPTIM3 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_RCR" description="LPTIM3 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CCMR1" description="LPTIM3 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CCR2" description="LPTIM3 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM3_S" description="Low-power timer" start="0x56002800">
+    <Register name="LPTIM3_ISR_OUTPUT" description="LPTIM3 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Compare 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OK" description="Compare register 2 update OK" start="19" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_ISR_INPUT" description="LPTIM3 interrupt and status register [alternate]" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="capture 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="CC2IF" description="Capture 2 interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture 1 over-capture flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture 2 over-capture flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No over-capture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set." start="0x1" />
+      </BitField>
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_ICR_OUTPUT" description="LPTIM3 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMP2OKCF" description="Compare register 2 update OK clear flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM3_ICR_INPUT" description="LPTIM3 interrupt clear register [alternate]" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CC2CF" description="Capture/compare 2 clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CC1OCF" description="Capture/compare 1 over-capture clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="CC2OCF" description="Capture/compare 2 over-capture clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM3_DIER_OUTPUT" description="LPTIM3 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP2OKIE" description="Compare register 2 update OK interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_DIER_INPUT" description="LPTIM3 interrupt enable register [alternate]" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1OIE" description="Capture/compare 1 over-capture interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2OIE" description="Capture/compare 2 over-capture interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 over-capture interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 over-capture interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEDE" description="Update event DMA request enable " start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="UE DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CFGR" description="LPTIM3 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CR" description="LPTIM3 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CCR1" description="LPTIM3 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_ARR" description="LPTIM3 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CNT" description="LPTIM3 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM3_CFGR2" description="LPTIM3 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_RCR" description="LPTIM3 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM3_CCMR1" description="LPTIM3 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM3_CCR2" description="LPTIM3 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM4" description="Low-power timer" start="0x46002C00">
+    <Register name="LPTIM4_ISR" description="LPTIM4 interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM4_ICR" description="LPTIM4 interrupt clear register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM4_DIER" description="LPTIM4 interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CFGR" description="LPTIM4 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CR" description="LPTIM4 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CCR1" description="LPTIM4 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_ARR" description="LPTIM4 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CNT" description="LPTIM4 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM4_CFGR2" description="LPTIM4 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_RCR" description="LPTIM4 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CCMR1" description="LPTIM4 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CCR2" description="LPTIM4 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM4_S" description="Low-power timer" start="0x56002C00">
+    <Register name="LPTIM4_ISR" description="LPTIM4 interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM4_ICR" description="LPTIM4 interrupt clear register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM4_DIER" description="LPTIM4 interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CFGR" description="LPTIM4 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CR" description="LPTIM4 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CCR1" description="LPTIM4 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_ARR" description="LPTIM4 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CNT" description="LPTIM4 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM4_CFGR2" description="LPTIM4 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_RCR" description="LPTIM4 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM4_CCMR1" description="LPTIM4 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM4_CCR2" description="LPTIM4 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM5" description="Low-power timer" start="0x46003000">
+    <Register name="LPTIM5_ISR" description="LPTIM5 interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM5_ICR" description="LPTIM5 interrupt clear register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM5_DIER" description="LPTIM5 interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CFGR" description="LPTIM5 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CR" description="LPTIM5 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CCR1" description="LPTIM5 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_ARR" description="LPTIM5 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CNT" description="LPTIM5 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM5_CFGR2" description="LPTIM5 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_RCR" description="LPTIM5 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CCMR1" description="LPTIM5 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CCR2" description="LPTIM5 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM5_S" description="Low-power timer" start="0x56003000">
+    <Register name="LPTIM5_ISR" description="LPTIM5 interrupt and status register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Compare 1 interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No match" start="0x0" />
+        <Enum name="B_0x1" description="The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value" start="0x1" />
+      </BitField>
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" access="ReadOnly" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" access="ReadOnly" />
+      <BitField name="CMP1OK" description="Compare register 1 update OK" start="3" size="1" access="ReadOnly" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" access="ReadOnly" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" access="ReadOnly" />
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" access="ReadOnly" />
+      <BitField name="UE" description="LPTIM update event occurred" start="7" size="1" access="ReadOnly" />
+      <BitField name="REPOK" description="Repetition register update OK" start="8" size="1" access="ReadOnly" />
+      <BitField name="DIEROK" description="Interrupt enable register update OK" start="24" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM5_ICR" description="LPTIM5 interrupt clear register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1CF" description="Capture/compare 1 clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="ARRMCF" description="Autoreload match clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CMP1OKCF" description="Compare register 1 update OK clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="ARROKCF" description="Autoreload register update OK clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="UPCF" description="Direction change to UP clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="DOWNCF" description="Direction change to down clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="UECF" description="Update event clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="REPOKCF" description="Repetition register update OK clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="DIEROKCF" description="Interrupt enable register update OK clear flag" start="24" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPTIM5_DIER" description="LPTIM5 interrupt enable register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture/compare 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Capture/compare 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARRM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARRM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EXTTRIG interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EXTTRIG interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMP1OKIE" description="Compare register 1 update OK interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMPOK register 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CMPOK register 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ARROK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ARROK interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DOWN interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DOWN interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UEIE" description="Update event interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="REPOKIE" description="Repetition register update OK interrupt Enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Repetition register update OK interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Repetition register update OK interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CFGR" description="LPTIM5 configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is clocked by an external clock source through the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="the rising edge is the active edge used for counting." start="0x0" />
+        <Enum name="B_0x1" description="the falling edge is the active edge used for counting." start="0x1" />
+        <Enum name="B_0x2" description="both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency." start="0x2" />
+        <Enum name="B_0x3" description="not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external clock signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any trigger active level change is considered as a valid trigger" start="0x0" />
+        <Enum name="B_0x1" description="trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger." start="0x1" />
+        <Enum name="B_0x2" description="trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger." start="0x2" />
+        <Enum name="B_0x3" description="trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger." start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="/1" start="0x0" />
+        <Enum name="B_0x1" description="/2" start="0x1" />
+        <Enum name="B_0x2" description="/4" start="0x2" />
+        <Enum name="B_0x3" description="/8" start="0x3" />
+        <Enum name="B_0x4" description="/16" start="0x4" />
+        <Enum name="B_0x5" description="/32" start="0x5" />
+        <Enum name="B_0x6" description="/64" start="0x6" />
+        <Enum name="B_0x7" description="/128" start="0x7" />
+      </BitField>
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ext_trig0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ext_trig1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ext_trig2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ext_trig3" start="0x3" />
+        <Enum name="B_0x4" description="lptim_ext_trig4" start="0x4" />
+        <Enum name="B_0x5" description="lptim_ext_trig5" start="0x5" />
+        <Enum name="B_0x6" description="lptim_ext_trig6" start="0x6" />
+        <Enum name="B_0x7" description="lptim_ext_trig7" start="0x7" />
+      </BitField>
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="software trigger (counting start is initiated by software)" start="0x0" />
+        <Enum name="B_0x1" description="rising edge is the active edge" start="0x1" />
+        <Enum name="B_0x2" description="falling edge is the active edge" start="0x2" />
+        <Enum name="B_0x3" description="both edges are active edges" start="0x3" />
+      </BitField>
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A trigger event arriving when the timer is already started is ignored" start="0x0" />
+        <Enum name="B_0x1" description="A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter" start="0x1" />
+      </BitField>
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deactivate Set-once mode" start="0x0" />
+        <Enum name="B_0x1" description="Activate the Set-once mode" start="0x1" />
+      </BitField>
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1" description="The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers" start="0x1" />
+      </BitField>
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Registers are updated after each APB bus write access" start="0x0" />
+        <Enum name="B_0x1" description="Registers are updated at the end of the current LPTIM period" start="0x1" />
+      </BitField>
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the counter is incremented following each internal clock pulse" start="0x0" />
+        <Enum name="B_0x1" description="the counter is incremented following each valid clock pulse on the LPTIM external Input1" start="0x1" />
+      </BitField>
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Encoder mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CR" description="LPTIM5 control register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests)." start="0x0" />
+        <Enum name="B_0x1" description="LPTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SNGSTRT" description="LPTIM start in Single mode" start="1" size="1" access="Read/Write" />
+      <BitField name="CNTSTRT" description="Timer start in Continuous mode" start="2" size="1" access="Read/Write" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" access="Read/Write" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CCR1" description="LPTIM5 compare register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_ARR" description="LPTIM5 autoreload register" start="+0x018" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CNT" description="LPTIM5 counter register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="LPTIM5_CFGR2" description="LPTIM5 configuration register 2" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM input 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IN2SEL" description="LPTIM input 2 selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_in2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_in2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_in2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_in2_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC1SEL" description="LPTIM input capture 1 selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic1_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic1_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic1_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic1_mux3" start="0x3" />
+      </BitField>
+      <BitField name="IC2SEL" description="LPTIM input capture 2 selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="lptim_ic2_mux0" start="0x0" />
+        <Enum name="B_0x1" description="lptim_ic2_mux1" start="0x1" />
+        <Enum name="B_0x2" description="lptim_ic2_mux2" start="0x2" />
+        <Enum name="B_0x3" description="lptim_ic2_mux3" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_RCR" description="LPTIM5 repetition register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition register value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPTIM5_CCMR1" description="LPTIM5 capture/compare mode register 1" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1SEL" description="Capture/compare 1 selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC1E" description="Capture/compare 1 output enable." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="Off - OC1 is not active. Writing '0' to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="On - OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity." start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC1_AS_OUTPUT" description="OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x0" />
+        <Enum name="B_0x1_CC1_AS_OUTPUT" description="OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers" start="0x1" />
+        <Enum name="B_0x3_CC1_AS_INPUT" description="both edges, circuit is sensitive to both IC1 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+      <BitField name="CC2SEL" description="Capture/compare 2 selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured in output PWM mode" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured in input capture mode" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="Off - OC2 is not active. Writing '0' to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled." start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="On - OC2 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC2P" description="Capture/compare 2 output polarity." start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0_CC2_AS_OUTPUT" description="OC2 active high" start="0x0" />
+        <Enum name="B_0x1_CC2_AS_OUTPUT" description="OC2 active low" start="0x1" />
+        <Enum name="B_0x3_CC2_AS_INPUT" description="both edges, circuit is sensitive to both IC2 rising and falling edges." start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC2F" description="Input capture 2 filter" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="any external input capture signal level change is considered as a valid transition" start="0x0" />
+        <Enum name="B_0x1" description="external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition." start="0x1" />
+        <Enum name="B_0x2" description="external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition." start="0x2" />
+        <Enum name="B_0x3" description="external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="LPTIM5_CCR2" description="LPTIM5 compare register 2" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPUART1" description="Low-power universal asynchronous receiver transmitter" start="0x46000C00">
+    <Register name="LPUART_CR1_ENABLED" description="LPUART control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="LPUART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="LPUART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="LPUART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wake-up method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_CR1_DISABLED" description="LPUART control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="LPUART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="LPUART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="LPUART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wake-up method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_CR2" description="LPUART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="STOP bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the LPUART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_CR3" description="LPUART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred." start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="WUS0" description="Wake-up from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wake-up from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wake-up from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth." start="0x1" />
+        <Enum name="B_0x6" description="Receive FIFO reaches 1/2 of its depth." start="0x6" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth." start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth." start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full." start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth." start="0x1" />
+        <Enum name="B_0x6" description="TXFIFO reaches 1/2 of its depth." start="0x6" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth." start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth." start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_BRR" description="LPUART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="LPUART baud rate division (LPUARTDIV)" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_RQR" description="LPUART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPUART_ISR_ENABLED" description="LPUART interrupt and status register" start="+0x1C" size="4" reset_value="0x008000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Start bit noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register is full/Transmit FIFO is full." start="0x0" />
+        <Enum name="B_0x1" description="Data register/Transmit FIFO is not full." start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LPUART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wake-up from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wake-up from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO is not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO is empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO is not Full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO is Full." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_ISR_DISABLED" description="LPUART interrupt and status register" start="+0x1C" size="4" reset_value="0x008000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Start bit noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register is full/Transmit FIFO is full." start="0x0" />
+        <Enum name="B_0x1" description="Data register/Transmit FIFO is not full." start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LPUART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wake-up from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wake-up from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPUART_ICR" description="LPUART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wake-up from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPUART_RDR" description="LPUART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="LPUART_TDR" description="LPUART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_PRESC" description="LPUART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPUART1_S" description="Low-power universal asynchronous receiver transmitter" start="0x56000C00">
+    <Register name="LPUART_CR1_ENABLED" description="LPUART control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="LPUART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="LPUART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="LPUART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wake-up method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_CR1_DISABLED" description="LPUART control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="LPUART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="LPUART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="LPUART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wake-up method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_CR2" description="LPUART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="STOP bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the LPUART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_CR3" description="LPUART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred." start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="WUS0" description="Wake-up from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wake-up from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wake-up from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the LPUART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth." start="0x1" />
+        <Enum name="B_0x6" description="Receive FIFO reaches 1/2 of its depth." start="0x6" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth." start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth." start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full." start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth." start="0x1" />
+        <Enum name="B_0x6" description="TXFIFO reaches 1/2 of its depth." start="0x6" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth." start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth." start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_BRR" description="LPUART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="LPUART baud rate division (LPUARTDIV)" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_RQR" description="LPUART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPUART_ISR_ENABLED" description="LPUART interrupt and status register" start="+0x1C" size="4" reset_value="0x008000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Start bit noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register is full/Transmit FIFO is full." start="0x0" />
+        <Enum name="B_0x1" description="Data register/Transmit FIFO is not full." start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LPUART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wake-up from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wake-up from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO is not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO is empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO is not Full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO is Full." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="LPUART_ISR_DISABLED" description="LPUART interrupt and status register" start="+0x1C" size="4" reset_value="0x008000C0" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Start bit noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register is full/Transmit FIFO is full." start="0x0" />
+        <Enum name="B_0x1" description="Data register/Transmit FIFO is not full." start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LPUART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wake-up from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wake-up from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="LPUART_ICR" description="LPUART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wake-up from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="LPUART_RDR" description="LPUART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="LPUART_TDR" description="LPUART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="LPUART_PRESC" description="LPUART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE1" description="Memory cipher engine" start="0x4802B800">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE1_S" description="Memory cipher engine" start="0x5802B800">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE2" description="Memory cipher engine" start="0x4802BC00">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE2_S" description="Memory cipher engine" start="0x5802BC00">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE3" description="Memory cipher engine" start="0x4802C000">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE3_S" description="Memory cipher engine" start="0x5802C000">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE4" description="Memory cipher engine" start="0x4802E000">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCE4_S" description="Memory cipher engine" start="0x5802E000">
+    <Register name="MCE_CR" description="MCE configuration register" start="+0x000" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE registers are writable" start="0x0" />
+        <Enum name="B_0x1" description="All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers." start="0x1" />
+      </BitField>
+      <BitField name="MKLOCK" description="Master keys lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="CIPHERSEL" description="Cipher selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="AES-128 cipher selected for all encrypted regions" start="0x1" />
+        <Enum name="B_0x2" description="Noekeon cipher selected for all encrypted regions" start="0x2" />
+        <Enum name="B_0x3" description="AES-256 cipher selected for all encrypted regions" start="0x3" />
+        <Enum name="B_0x0" description="No cipher is selected. Any read (resp. write) to an encrypted region with BREN=1 returns zero (resp. is ignored), and illegal access flag IAEF bit is set." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SR" description="MCE status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKVALID" description="Master key valid" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_MKEYRx registers, or a valid unlocked master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_MKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="FMKVALID" description="Fast master key valid" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A valid key has not been written in MCE_FMKEYRx registers, or a valid unlocked fast master key has been erased by hardware (if bit was set before)" start="0x0" />
+        <Enum name="B_0x1" description="A valid key has been written in MCE_FMKEYRx registers (write R0 -&gt; R1 -&gt; R2 -&gt; R3 or the reverse)" start="0x1" />
+      </BitField>
+      <BitField name="ENCDIS" description="encryption disabled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="When ENC bit and BREN are set in MCE_REGCRx all allowed write accesses in region x are encrypted, and all allowed read requests are decrypted." start="0x0" />
+        <Enum name="B_0x1" description="When ENC bit and BREN are set in any MCE_REGCRx all write accesses in region x are ignored, and all read requests return zero. All previously written key material are also erased." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IASR" description="MCE illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_IACR" description="MCE illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEF" description="Illegal access error flag clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_IAIER" description="MCE illegal access interrupt enable register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IAEIE" description="Illegal access error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Interrupt generation on illegal access errors is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt generation when an illegal access error occurs (IAEF=1)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MCE_IADDR" description="MCE illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="Illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="MCE_REGCR1" description="MCE region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR1" description="MCE start address for region 1 register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR1" description="MCE end address for region 1 register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR2" description="MCE region 2 configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR2" description="MCE start address for region 2 register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR2" description="MCE end address for region 2 register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR3" description="MCE region 3 configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR3" description="MCE start address for region 3 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR3" description="MCE end address for region 3 register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_REGCR4" description="MCE region 4 configuration register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Region x is disabled. Access control of primary region (privileged or unprivileged, no encryption) applies to any access between this region start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Region x is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="CTXID" description="Context ID" start="9" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If ENC=10 (resp. 11) the key stored in MCE_MKEYR (resp. MCE_FMKEYR) registers is used by the block cipher. If ENC=01 bypass mode is selected instead of stream cipher." start="0x0" />
+        <Enum name="B_0x1" description="If ENC=10 or 11 the key stored in MCE_CC1KEYR is used by the block cipher." start="0x1" />
+        <Enum name="B_0x2" description="If ENC=10 or 11 the key stored in MCE_CC2KEYR is used by the block cipher." start="0x2" />
+      </BitField>
+      <BitField name="ENC" description="Encrypted region" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No effects" start="0x0" />
+        <Enum name="B_0x1" description="Stream cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the stream cipher, when CCEN bit is set in MCE_CCzCFGR (where CTXID=z)." start="0x1" />
+        <Enum name="B_0x2" description="Block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the SCA resistant block cipher. If CTXID=0 and MKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher - All allowed read (resp. write) requests are decrypted (resp. encrypted) using the fast block cipher. If CTXID=0 and FMKVALID=0 bypass mode is selected instead. If CTXID=z and CCEN bit is cleared in MCE_CCzCFGR bypass mode is also selected." start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MCE_SADDR4" description="MCE start address for region 4 register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Region address start" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_EADDR4" description="MCE end address for region 4 register" start="+0x78" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Region address end" start="12" size="20" access="Read/Write" />
+    </Register>
+    <Register name="MCE_MKEYR0" description=".MCE master key 0" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY0" description="Master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY1" description="Master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY2" description="Master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY3" description="Master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY4" description="Master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY5" description="Master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY6" description="Master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY7" description="Master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY8" description="Master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY9" description="Master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY10" description="Master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY11" description="Master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY12" description="Master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY13" description="Master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY14" description="Master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY15" description="Master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY16" description="Master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY17" description="Master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY18" description="Master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY19" description="Master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY20" description="Master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY21" description="Master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY22" description="Master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY23" description="Master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY24" description="Master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY25" description="Master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY26" description="Master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY27" description="Master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY28" description="Master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY29" description="Master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY30" description="Master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY31" description="Master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR1" description=".MCE master key 1" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY32" description="Master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY33" description="Master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY34" description="Master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY35" description="Master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY36" description="Master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY37" description="Master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY38" description="Master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY39" description="Master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY40" description="Master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY41" description="Master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY42" description="Master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY43" description="Master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY44" description="Master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY45" description="Master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY46" description="Master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY47" description="Master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY48" description="Master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY49" description="Master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY50" description="Master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY51" description="Master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY52" description="Master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY53" description="Master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY54" description="Master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY55" description="Master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY56" description="Master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY57" description="Master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY58" description="Master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY59" description="Master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY60" description="Master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY61" description="Master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY62" description="Master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY63" description="Master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR2" description=".MCE master key 2" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY64" description="Master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY65" description="Master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY66" description="Master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY67" description="Master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY68" description="Master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY69" description="Master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY70" description="Master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY71" description="Master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY72" description="Master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY73" description="Master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY74" description="Master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY75" description="Master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY76" description="Master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY77" description="Master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY78" description="Master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY79" description="Master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY80" description="Master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY81" description="Master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY82" description="Master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY83" description="Master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY84" description="Master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY85" description="Master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY86" description="Master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY87" description="Master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY88" description="Master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY89" description="Master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY90" description="Master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY91" description="Master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY92" description="Master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY93" description="Master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY94" description="Master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY95" description="Master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR3" description=".MCE master key 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY96" description="Master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY97" description="Master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY98" description="Master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY99" description="Master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY100" description="Master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY101" description="Master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY102" description="Master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY103" description="Master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY104" description="Master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY105" description="Master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY106" description="Master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY107" description="Master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY108" description="Master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY109" description="Master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY110" description="Master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY111" description="Master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY112" description="Master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY113" description="Master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY114" description="Master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY115" description="Master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY116" description="Master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY117" description="Master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY118" description="Master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY119" description="Master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY120" description="Master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY121" description="Master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY122" description="Master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY123" description="Master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY124" description="Master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY125" description="Master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY126" description="Master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY127" description="Master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR4" description=".MCE master key 4" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY128" description="Master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY129" description="Master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY130" description="Master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY131" description="Master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY132" description="Master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY133" description="Master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY134" description="Master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY135" description="Master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY136" description="Master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY137" description="Master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY138" description="Master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY139" description="Master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY140" description="Master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY141" description="Master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY142" description="Master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY143" description="Master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY144" description="Master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY145" description="Master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY146" description="Master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY147" description="Master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY148" description="Master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY149" description="Master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY150" description="Master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY151" description="Master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY152" description="Master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY153" description="Master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY154" description="Master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY155" description="Master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY156" description="Master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY157" description="Master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY158" description="Master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY159" description="Master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR5" description=".MCE master key 5" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY160" description="Master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY161" description="Master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY162" description="Master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY163" description="Master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY164" description="Master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY165" description="Master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY166" description="Master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY167" description="Master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY168" description="Master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY169" description="Master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY170" description="Master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY171" description="Master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY172" description="Master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY173" description="Master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY174" description="Master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY175" description="Master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY176" description="Master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY177" description="Master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY178" description="Master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY179" description="Master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY180" description="Master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY181" description="Master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY182" description="Master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY183" description="Master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY184" description="Master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY185" description="Master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY186" description="Master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY187" description="Master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY188" description="Master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY189" description="Master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY190" description="Master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY191" description="Master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR6" description=".MCE master key 6" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY192" description="Master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY193" description="Master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY194" description="Master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY195" description="Master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY196" description="Master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY197" description="Master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY198" description="Master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY199" description="Master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY200" description="Master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY201" description="Master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY202" description="Master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY203" description="Master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY204" description="Master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY205" description="Master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY206" description="Master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY207" description="Master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY208" description="Master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY209" description="Master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY210" description="Master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY211" description="Master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY212" description="Master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY213" description="Master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY214" description="Master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY215" description="Master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY216" description="Master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY217" description="Master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY218" description="Master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY219" description="Master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY220" description="Master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY221" description="Master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY222" description="Master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY223" description="Master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_MKEYR7" description=".MCE master key 7" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MKEY224" description="Master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="MKEY225" description="Master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="MKEY226" description="Master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="MKEY227" description="Master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="MKEY228" description="Master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="MKEY229" description="Master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="MKEY230" description="Master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="MKEY231" description="Master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="MKEY232" description="Master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="MKEY233" description="Master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="MKEY234" description="Master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="MKEY235" description="Master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="MKEY236" description="Master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="MKEY237" description="Master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="MKEY238" description="Master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="MKEY239" description="Master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="MKEY240" description="Master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="MKEY241" description="Master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="MKEY242" description="Master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="MKEY243" description="Master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="MKEY244" description="Master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="MKEY245" description="Master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="MKEY246" description="Master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="MKEY247" description="Master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="MKEY248" description="Master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="MKEY249" description="Master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="MKEY250" description="Master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="MKEY251" description="Master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="MKEY252" description="Master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="MKEY253" description="Master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="MKEY254" description="Master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="MKEY255" description="Master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR0" description="MCE fast master key 0" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY0" description="Fast master key bit 0 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY1" description="Fast master key bit 1 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY2" description="Fast master key bit 2 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY3" description="Fast master key bit 3 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY4" description="Fast master key bit 4 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY5" description="Fast master key bit 5 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY6" description="Fast master key bit 6 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY7" description="Fast master key bit 7 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY8" description="Fast master key bit 8 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY9" description="Fast master key bit 9 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY10" description="Fast master key bit 10 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY11" description="Fast master key bit 11 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY12" description="Fast master key bit 12 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY13" description="Fast master key bit 13 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY14" description="Fast master key bit 14 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY15" description="Fast master key bit 15 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY16" description="Fast master key bit 16 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY17" description="Fast master key bit 17 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY18" description="Fast master key bit 18 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY19" description="Fast master key bit 19 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY20" description="Fast master key bit 20 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY21" description="Fast master key bit 21 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY22" description="Fast master key bit 22 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY23" description="Fast master key bit 23 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY24" description="Fast master key bit 24 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY25" description="Fast master key bit 25 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY26" description="Fast master key bit 26 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY27" description="Fast master key bit 27 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY28" description="Fast master key bit 28 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY29" description="Fast master key bit 29 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY30" description="Fast master key bit 30 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY31" description="Fast master key bit 31 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR1" description="MCE fast master key 1" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY32" description="Fast master key bit 32 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY33" description="Fast master key bit 33 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY34" description="Fast master key bit 34 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY35" description="Fast master key bit 35 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY36" description="Fast master key bit 36 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY37" description="Fast master key bit 37 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY38" description="Fast master key bit 38 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY39" description="Fast master key bit 39 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY40" description="Fast master key bit 40 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY41" description="Fast master key bit 41 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY42" description="Fast master key bit 42 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY43" description="Fast master key bit 43 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY44" description="Fast master key bit 44 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY45" description="Fast master key bit 45 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY46" description="Fast master key bit 46 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY47" description="Fast master key bit 47 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY48" description="Fast master key bit 48 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY49" description="Fast master key bit 49 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY50" description="Fast master key bit 50 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY51" description="Fast master key bit 51 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY52" description="Fast master key bit 52 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY53" description="Fast master key bit 53 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY54" description="Fast master key bit 54 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY55" description="Fast master key bit 55 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY56" description="Fast master key bit 56 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY57" description="Fast master key bit 57 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY58" description="Fast master key bit 58 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY59" description="Fast master key bit 59 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY60" description="Fast master key bit 60 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY61" description="Fast master key bit 61 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY62" description="Fast master key bit 62 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY63" description="Fast master key bit 63 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR2" description="MCE fast master key 2" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY64" description="Fast master key bit 64 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY65" description="Fast master key bit 65 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY66" description="Fast master key bit 66 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY67" description="Fast master key bit 67 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY68" description="Fast master key bit 68 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY69" description="Fast master key bit 69 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY70" description="Fast master key bit 70 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY71" description="Fast master key bit 71 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY72" description="Fast master key bit 72 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY73" description="Fast master key bit 73 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY74" description="Fast master key bit 74 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY75" description="Fast master key bit 75 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY76" description="Fast master key bit 76 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY77" description="Fast master key bit 77 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY78" description="Fast master key bit 78 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY79" description="Fast master key bit 79 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY80" description="Fast master key bit 80 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY81" description="Fast master key bit 81 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY82" description="Fast master key bit 82 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY83" description="Fast master key bit 83 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY84" description="Fast master key bit 84 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY85" description="Fast master key bit 85 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY86" description="Fast master key bit 86 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY87" description="Fast master key bit 87 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY88" description="Fast master key bit 88 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY89" description="Fast master key bit 89 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY90" description="Fast master key bit 90 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY91" description="Fast master key bit 91 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY92" description="Fast master key bit 92 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY93" description="Fast master key bit 93 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY94" description="Fast master key bit 94 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY95" description="Fast master key bit 95 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR3" description="MCE fast master key 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY96" description="Fast master key bit 96 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY97" description="Fast master key bit 97 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY98" description="Fast master key bit 98 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY99" description="Fast master key bit 99 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY100" description="Fast master key bit 100 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY101" description="Fast master key bit 101 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY102" description="Fast master key bit 102 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY103" description="Fast master key bit 103 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY104" description="Fast master key bit 104 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY105" description="Fast master key bit 105 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY106" description="Fast master key bit 106 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY107" description="Fast master key bit 107 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY108" description="Fast master key bit 108 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY109" description="Fast master key bit 109 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY110" description="Fast master key bit 110 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY111" description="Fast master key bit 111 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY112" description="Fast master key bit 112 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY113" description="Fast master key bit 113 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY114" description="Fast master key bit 114 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY115" description="Fast master key bit 115 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY116" description="Fast master key bit 116 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY117" description="Fast master key bit 117 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY118" description="Fast master key bit 118 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY119" description="Fast master key bit 119 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY120" description="Fast master key bit 120 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY121" description="Fast master key bit 121 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY122" description="Fast master key bit 122 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY123" description="Fast master key bit 123 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY124" description="Fast master key bit 124 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY125" description="Fast master key bit 125 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY126" description="Fast master key bit 126 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY127" description="Fast master key bit 127 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR4" description="MCE fast master key 4" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY128" description="Fast master key bit 128 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY129" description="Fast master key bit 129 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY130" description="Fast master key bit 130 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY131" description="Fast master key bit 131 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY132" description="Fast master key bit 132 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY133" description="Fast master key bit 133 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY134" description="Fast master key bit 134 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY135" description="Fast master key bit 135 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY136" description="Fast master key bit 136 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY137" description="Fast master key bit 137 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY138" description="Fast master key bit 138 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY139" description="Fast master key bit 139 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY140" description="Fast master key bit 140 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY141" description="Fast master key bit 141 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY142" description="Fast master key bit 142 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY143" description="Fast master key bit 143 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY144" description="Fast master key bit 144 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY145" description="Fast master key bit 145 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY146" description="Fast master key bit 146 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY147" description="Fast master key bit 147 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY148" description="Fast master key bit 148 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY149" description="Fast master key bit 149 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY150" description="Fast master key bit 150 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY151" description="Fast master key bit 151 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY152" description="Fast master key bit 152 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY153" description="Fast master key bit 153 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY154" description="Fast master key bit 154 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY155" description="Fast master key bit 155 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY156" description="Fast master key bit 156 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY157" description="Fast master key bit 157 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY158" description="Fast master key bit 158 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY159" description="Fast master key bit 159 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR5" description="MCE fast master key 5" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY160" description="Fast master key bit 160 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY161" description="Fast master key bit 161 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY162" description="Fast master key bit 162 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY163" description="Fast master key bit 163 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY164" description="Fast master key bit 164 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY165" description="Fast master key bit 165 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY166" description="Fast master key bit 166 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY167" description="Fast master key bit 167 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY168" description="Fast master key bit 168 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY169" description="Fast master key bit 169 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY170" description="Fast master key bit 170 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY171" description="Fast master key bit 171 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY172" description="Fast master key bit 172 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY173" description="Fast master key bit 173 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY174" description="Fast master key bit 174 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY175" description="Fast master key bit 175 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY176" description="Fast master key bit 176 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY177" description="Fast master key bit 177 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY178" description="Fast master key bit 178 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY179" description="Fast master key bit 179 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY180" description="Fast master key bit 180 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY181" description="Fast master key bit 181 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY182" description="Fast master key bit 182 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY183" description="Fast master key bit 183 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY184" description="Fast master key bit 184 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY185" description="Fast master key bit 185 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY186" description="Fast master key bit 186 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY187" description="Fast master key bit 187 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY188" description="Fast master key bit 188 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY189" description="Fast master key bit 189 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY190" description="Fast master key bit 190 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY191" description="Fast master key bit 191 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR6" description="MCE fast master key 6" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY192" description="Fast master key bit 192 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY193" description="Fast master key bit 193 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY194" description="Fast master key bit 194 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY195" description="Fast master key bit 195 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY196" description="Fast master key bit 196 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY197" description="Fast master key bit 197 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY198" description="Fast master key bit 198 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY199" description="Fast master key bit 199 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY200" description="Fast master key bit 200 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY201" description="Fast master key bit 201 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY202" description="Fast master key bit 202 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY203" description="Fast master key bit 203 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY204" description="Fast master key bit 204 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY205" description="Fast master key bit 205 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY206" description="Fast master key bit 206 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY207" description="Fast master key bit 207 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY208" description="Fast master key bit 208 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY209" description="Fast master key bit 209 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY210" description="Fast master key bit 210 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY211" description="Fast master key bit 211 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY212" description="Fast master key bit 212 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY213" description="Fast master key bit 213 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY214" description="Fast master key bit 214 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY215" description="Fast master key bit 215 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY216" description="Fast master key bit 216 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY217" description="Fast master key bit 217 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY218" description="Fast master key bit 218 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY219" description="Fast master key bit 219 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY220" description="Fast master key bit 220 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY221" description="Fast master key bit 221 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY222" description="Fast master key bit 222 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY223" description="Fast master key bit 223 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_FMKEYR7" description="MCE fast master key 7" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMKEY224" description="Fast master key bit 224 (i = 31 to 0)" start="0" size="1" access="WriteOnly" />
+      <BitField name="FMKEY225" description="Fast master key bit 225 (i = 31 to 0)" start="1" size="1" access="WriteOnly" />
+      <BitField name="FMKEY226" description="Fast master key bit 226 (i = 31 to 0)" start="2" size="1" access="WriteOnly" />
+      <BitField name="FMKEY227" description="Fast master key bit 227 (i = 31 to 0)" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMKEY228" description="Fast master key bit 228 (i = 31 to 0)" start="4" size="1" access="WriteOnly" />
+      <BitField name="FMKEY229" description="Fast master key bit 229 (i = 31 to 0)" start="5" size="1" access="WriteOnly" />
+      <BitField name="FMKEY230" description="Fast master key bit 230 (i = 31 to 0)" start="6" size="1" access="WriteOnly" />
+      <BitField name="FMKEY231" description="Fast master key bit 231 (i = 31 to 0)" start="7" size="1" access="WriteOnly" />
+      <BitField name="FMKEY232" description="Fast master key bit 232 (i = 31 to 0)" start="8" size="1" access="WriteOnly" />
+      <BitField name="FMKEY233" description="Fast master key bit 233 (i = 31 to 0)" start="9" size="1" access="WriteOnly" />
+      <BitField name="FMKEY234" description="Fast master key bit 234 (i = 31 to 0)" start="10" size="1" access="WriteOnly" />
+      <BitField name="FMKEY235" description="Fast master key bit 235 (i = 31 to 0)" start="11" size="1" access="WriteOnly" />
+      <BitField name="FMKEY236" description="Fast master key bit 236 (i = 31 to 0)" start="12" size="1" access="WriteOnly" />
+      <BitField name="FMKEY237" description="Fast master key bit 237 (i = 31 to 0)" start="13" size="1" access="WriteOnly" />
+      <BitField name="FMKEY238" description="Fast master key bit 238 (i = 31 to 0)" start="14" size="1" access="WriteOnly" />
+      <BitField name="FMKEY239" description="Fast master key bit 239 (i = 31 to 0)" start="15" size="1" access="WriteOnly" />
+      <BitField name="FMKEY240" description="Fast master key bit 240 (i = 31 to 0)" start="16" size="1" access="WriteOnly" />
+      <BitField name="FMKEY241" description="Fast master key bit 241 (i = 31 to 0)" start="17" size="1" access="WriteOnly" />
+      <BitField name="FMKEY242" description="Fast master key bit 242 (i = 31 to 0)" start="18" size="1" access="WriteOnly" />
+      <BitField name="FMKEY243" description="Fast master key bit 243 (i = 31 to 0)" start="19" size="1" access="WriteOnly" />
+      <BitField name="FMKEY244" description="Fast master key bit 244 (i = 31 to 0)" start="20" size="1" access="WriteOnly" />
+      <BitField name="FMKEY245" description="Fast master key bit 245 (i = 31 to 0)" start="21" size="1" access="WriteOnly" />
+      <BitField name="FMKEY246" description="Fast master key bit 246 (i = 31 to 0)" start="22" size="1" access="WriteOnly" />
+      <BitField name="FMKEY247" description="Fast master key bit 247 (i = 31 to 0)" start="23" size="1" access="WriteOnly" />
+      <BitField name="FMKEY248" description="Fast master key bit 248 (i = 31 to 0)" start="24" size="1" access="WriteOnly" />
+      <BitField name="FMKEY249" description="Fast master key bit 249 (i = 31 to 0)" start="25" size="1" access="WriteOnly" />
+      <BitField name="FMKEY250" description="Fast master key bit 250 (i = 31 to 0)" start="26" size="1" access="WriteOnly" />
+      <BitField name="FMKEY251" description="Fast master key bit 251 (i = 31 to 0)" start="27" size="1" access="WriteOnly" />
+      <BitField name="FMKEY252" description="Fast master key bit 252 (i = 31 to 0)" start="28" size="1" access="WriteOnly" />
+      <BitField name="FMKEY253" description="Fast master key bit 253 (i = 31 to 0)" start="29" size="1" access="WriteOnly" />
+      <BitField name="FMKEY254" description="Fast master key bit 254 (i = 31 to 0)" start="30" size="1" access="WriteOnly" />
+      <BitField name="FMKEY255" description="Fast master key bit 255 (i = 31 to 0)" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1CFGR" description="MCE cipher context 1 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR0" description="MCE cipher context 1 nonce register 0" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1NR1" description="MCE cipher context 1 nonce register 1" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC1KEYR0" description="MCE cipher context 1 key register 0" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR1" description="MCE cipher context 1 key register 1" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR2" description="MCE cipher context 1 key register 2" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC1KEYR3" description="MCE cipher context 1 key register 3" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2CFGR" description="MCE cipher context 2 configuration register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCEN" description="Cipher context enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If an enabled region selects CTXID=z bypass mode is selected by MCE" start="0x0" />
+        <Enum name="B_0x1" description="If an enabled region selects CTXID=z with ENC=01 MCE selects with the stream cipher the information stored in MCE_CCzCFGR, MCE_CCzNR and MCE_CCzKEYR. If the enabled region selects ENC=10 or 11 instead MCE selects with the block cipher the key information stored in MCE_CCzKEYR. When CCEN is set and MODE[1:0] bits do not allow the configuration written in ENC[1:0] bits (see MODE bitfield) reads return zero and writes are ignored." start="0x1" />
+      </BitField>
+      <BitField name="CCLOCK" description="Cipher context lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzCFGR and MCE_CCzNR registers are ignored until next MCE reset." start="0x1" />
+      </BitField>
+      <BitField name="KEYLOCK" description="Key lock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to MCE_CCzKEYR registers are allowed" start="0x0" />
+        <Enum name="B_0x1" description="Writes to MCE_CCzKEYR registers are ignored until next MCE reset. KEYCRC bitfield value does not change." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="Authorized cipher mode" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Block cipher is allowed with this cipher context" start="0x2" />
+        <Enum name="B_0x3" description="Fast block cipher is allowed with this cipher context" start="0x3" />
+      </BitField>
+      <BitField name="KEYCRC" description="Key CRC" start="8" size="8" access="ReadOnly" />
+      <BitField name="VERSION" description="Version" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR0" description="MCE cipher context 2 nonce register 0" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2NR1" description="MCE cipher context 2 nonce register 1" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCNONCE" description="Stream cipher nonce, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MCE_CC2KEYR0" description="MCE cipher context 2 key register 0" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR1" description="MCE cipher context 2 key register 1" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR2" description="MCE cipher context 2 key register 2" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="MCE_CC2KEYR3" description="MCE cipher context 2 key register 3" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="cipher key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDF1" description="MDF register block" start="0x42025000">
+    <Register name="MDF_GCR" description="MDF global control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRGO" description="Trigger output control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write 0 has no effect. Read 0 means that the trigger can be set again to 1." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 generates a positive pulse on mdf_trgo signal and triggers the acquisition on the enabled filters having ACQMOD[2:0] = 0x1 and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active." start="0x1" />
+      </BitField>
+      <BitField name="ILVNB" description="Interleaved number" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Interleaved-transfer mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data from DFLT0 and DFLT1 are interleaved." start="0x1" />
+        <Enum name="B_0x2" description="Data from DFLT0, DFLT1 and DFLT2 are interleaved." start="0x2" />
+        <Enum name="B_0xF" description="Data from DFLT0 to DFLT15 are interleaved." start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="MDF_CKGCR" description="MDF clock generator control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKGDEN" description="CKGEN dividers enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKGEN dividers disabled" start="0x0" />
+        <Enum name="B_0x1" description="CKGEN dividers enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCK0EN" description="MDF_CCK0 clock enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the MDF_CCK0 pad" start="0x1" />
+      </BitField>
+      <BitField name="CCK1EN" description="MDF_CCK1 clock enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the MDF_CCK1 pad" start="0x1" />
+      </BitField>
+      <BitField name="CKGMOD" description="Clock generator mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The kernel clock is provided to the dividers as soon as CKGDEN is set to 1." start="0x0" />
+        <Enum name="B_0x1" description="The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met." start="0x1" />
+      </BitField>
+      <BitField name="CCK0DIR" description="MDF_CCK0 direction" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF_CCK0 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="MDF_CCK0 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="CCK1DIR" description="MDF_CCK1 direction" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF_CCK1 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="MDF_CCK1 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="TRGSENS" description="CKGEN trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the activation of CKGEN dividers." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the activation of CKGEN dividers." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0x3" description="mdf_trg[1] selected" start="0x3" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="CCKDIV" description="Divider to control the MDF_CCK clock" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="The MDF_CCK clock is mdf_proc_ck." start="0x0" />
+        <Enum name="B_0x1" description="The MDF_CCK clock is mdf_proc_ck / 2." start="0x1" />
+        <Enum name="B_0x2" description="The MDF_CCK clock is mdf_proc_ck / 3." start="0x2" />
+        <Enum name="B_0xF" description="The MDF_CCK clock is mdf_proc_ck / 16." start="0xF" />
+      </BitField>
+      <BitField name="PROCDIV" description="Divider to control the serial interface clock" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="mdf_ker_ck provided to the SITF" start="0x0" />
+        <Enum name="B_0x1" description="mdf_ker_ck/2 provided to the SITF" start="0x1" />
+      </BitField>
+      <BitField name="CKGACTIVE" description="Clock generator active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The clock generator is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The clock generator is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SITF0CR" description="MDF serial interface control register 0" start="+0x80" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX0CR" description="MDF bitstream matrix control register 0" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0CR" description="MDF digital filter control register 0" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0CICR" description="MDF digital filter configuration register 0" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0RSFR" description="MDF reshape filter configuration register 0" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0INTR" description="MDF integrator configuration register 0" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD0CR" description="MDF out-of limit detector control register 0" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD0THLR" description="MDF OLD0 low threshold register 0" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD0THHR" description="MDF OLD0 high threshold register 0" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY0CR" description="MDF delay control register 0" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD0CR" description="MDF short circuit detector control register 0" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0IER" description="MDF DFLT0 interrupt enable register 0" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLD0 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLD0 event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLD0 event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCD0 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCD0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCD0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0ISR" description="MDF DFLT0 interrupt status register 0" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLD0 flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLD0 event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLD0 event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLD0 event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLD0 event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLD0 event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLD0 event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD0 event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD0 event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC0CR" description="MDF offset error compensation control register 0" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS0DR" description="MDF snapshot data register 0" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT0DR" description="MDF digital filter data register 0" start="+0xF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF1CR" description="MDF serial interface control register 1" start="+0x100" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX1CR" description="MDF bitstream matrix control register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1CR" description="MDF digital filter control register 1" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1CICR" description="MDF digital filter configuration register 1" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1RSFR" description="MDF reshape filter configuration register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1INTR" description="MDF integrator configuration register 1" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD1CR" description="MDF out-of limit detector control register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD1THLR" description="MDF OLD1 low threshold register 1" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD1THHR" description="MDF OLD1 high threshold register 1" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY1CR" description="MDF delay control register 1" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD1CR" description="MDF short circuit detector control register 1" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1IER" description="MDF DFLT1 interrupt enable register 1" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1ISR" description="MDF DFLT1 interrupt status register 1" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC1CR" description="MDF offset error compensation control register 1" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS1DR" description="MDF snapshot data register 1" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT1DR" description="MDF digital filter data register 1" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF2CR" description="MDF serial interface control register 2" start="+0x180" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX2CR" description="MDF bitstream matrix control register 2" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2CR" description="MDF digital filter control register 2" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2CICR" description="MDF digital filter configuration register 2" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2RSFR" description="MDF reshape filter configuration register 2" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2INTR" description="MDF integrator configuration register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD2CR" description="MDF out-of limit detector control register 2" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD2THLR" description="MDF OLD2 low threshold register 2" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD2THHR" description="MDF OLD2 high threshold register 2" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY2CR" description="MDF delay control register 2" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD2CR" description="MDF short circuit detector control register 2" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2IER" description="MDF DFLT2 interrupt enable register 2" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2ISR" description="MDF DFLT2 interrupt status register 2" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC2CR" description="MDF offset error compensation control register 2" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS2DR" description="MDF snapshot data register 2" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT2DR" description="MDF digital filter data register 2" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF3CR" description="MDF serial interface control register 3" start="+0x200" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX3CR" description="MDF bitstream matrix control register 3" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3CR" description="MDF digital filter control register 3" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3CICR" description="MDF digital filter configuration register 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3RSFR" description="MDF reshape filter configuration register 3" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3INTR" description="MDF integrator configuration register 3" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD3CR" description="MDF out-of limit detector control register 3" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD3THLR" description="MDF OLD3 low threshold register 3" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD3THHR" description="MDF OLD3 high threshold register 3" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY3CR" description="MDF delay control register 3" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD3CR" description="MDF short circuit detector control register 3" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3IER" description="MDF DFLT3 interrupt enable register 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3ISR" description="MDF DFLT3 interrupt status register 3" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC3CR" description="MDF offset error compensation control register 3" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS3DR" description="MDF snapshot data register 3" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT3DR" description="MDF digital filter data register 3" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF4CR" description="MDF serial interface control register 4" start="+0x280" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX4CR" description="MDF bitstream matrix control register 4" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4CR" description="MDF digital filter control register 4" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4CICR" description="MDF digital filter configuration register 4" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4RSFR" description="MDF reshape filter configuration register 4" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4INTR" description="MDF integrator configuration register 4" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD4CR" description="MDF out-of limit detector control register 4" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD4THLR" description="MDF OLD4 low threshold register 4" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD4THHR" description="MDF OLD4 high threshold register 4" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY4CR" description="MDF delay control register 4" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD4CR" description="MDF short circuit detector control register 4" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4IER" description="MDF DFLT4 interrupt enable register 4" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4ISR" description="MDF DFLT4 interrupt status register 4" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC4CR" description="MDF offset error compensation control register 4" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS4DR" description="MDF snapshot data register 4" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT4DR" description="MDF digital filter data register 4" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF5CR" description="MDF serial interface control register 5" start="+0x300" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX5CR" description="MDF bitstream matrix control register 5" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5CR" description="MDF digital filter control register 5" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5CICR" description="MDF digital filter configuration register 5" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5RSFR" description="MDF reshape filter configuration register 5" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5INTR" description="MDF integrator configuration register 5" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD5CR" description="MDF out-of limit detector control register 5" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD5THLR" description="MDF OLD5 low threshold register 5" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD5THHR" description="MDF OLD5 high threshold register 5" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY5CR" description="MDF delay control register 5" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD5CR" description="MDF short circuit detector control register 5" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5IER" description="MDF DFLT5 interrupt enable register 5" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5ISR" description="MDF DFLT5 interrupt status register 5" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC5CR" description="MDF offset error compensation control register 5" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS5DR" description="MDF snapshot data register 5" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT5DR" description="MDF digital filter data register 5" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDF1_S" description="MDF register block" start="0x52025000">
+    <Register name="MDF_GCR" description="MDF global control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRGO" description="Trigger output control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write 0 has no effect. Read 0 means that the trigger can be set again to 1." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 generates a positive pulse on mdf_trgo signal and triggers the acquisition on the enabled filters having ACQMOD[2:0] = 0x1 and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active." start="0x1" />
+      </BitField>
+      <BitField name="ILVNB" description="Interleaved number" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Interleaved-transfer mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data from DFLT0 and DFLT1 are interleaved." start="0x1" />
+        <Enum name="B_0x2" description="Data from DFLT0, DFLT1 and DFLT2 are interleaved." start="0x2" />
+        <Enum name="B_0xF" description="Data from DFLT0 to DFLT15 are interleaved." start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="MDF_CKGCR" description="MDF clock generator control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKGDEN" description="CKGEN dividers enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKGEN dividers disabled" start="0x0" />
+        <Enum name="B_0x1" description="CKGEN dividers enabled" start="0x1" />
+      </BitField>
+      <BitField name="CCK0EN" description="MDF_CCK0 clock enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the MDF_CCK0 pad" start="0x1" />
+      </BitField>
+      <BitField name="CCK1EN" description="MDF_CCK1 clock enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bitstream clock not generated" start="0x0" />
+        <Enum name="B_0x1" description="Bitstream clock generated on the MDF_CCK1 pad" start="0x1" />
+      </BitField>
+      <BitField name="CKGMOD" description="Clock generator mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The kernel clock is provided to the dividers as soon as CKGDEN is set to 1." start="0x0" />
+        <Enum name="B_0x1" description="The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met." start="0x1" />
+      </BitField>
+      <BitField name="CCK0DIR" description="MDF_CCK0 direction" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF_CCK0 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="MDF_CCK0 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="CCK1DIR" description="MDF_CCK1 direction" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF_CCK1 pin direction is in input." start="0x0" />
+        <Enum name="B_0x1" description="MDF_CCK1 pin direction is in output." start="0x1" />
+      </BitField>
+      <BitField name="TRGSENS" description="CKGEN trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the activation of CKGEN dividers." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the activation of CKGEN dividers." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0x3" description="mdf_trg[1] selected" start="0x3" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="CCKDIV" description="Divider to control the MDF_CCK clock" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="The MDF_CCK clock is mdf_proc_ck." start="0x0" />
+        <Enum name="B_0x1" description="The MDF_CCK clock is mdf_proc_ck / 2." start="0x1" />
+        <Enum name="B_0x2" description="The MDF_CCK clock is mdf_proc_ck / 3." start="0x2" />
+        <Enum name="B_0xF" description="The MDF_CCK clock is mdf_proc_ck / 16." start="0xF" />
+      </BitField>
+      <BitField name="PROCDIV" description="Divider to control the serial interface clock" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="mdf_ker_ck provided to the SITF" start="0x0" />
+        <Enum name="B_0x1" description="mdf_ker_ck/2 provided to the SITF" start="0x1" />
+      </BitField>
+      <BitField name="CKGACTIVE" description="Clock generator active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The clock generator is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The clock generator is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SITF0CR" description="MDF serial interface control register 0" start="+0x80" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX0CR" description="MDF bitstream matrix control register 0" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0CR" description="MDF digital filter control register 0" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0CICR" description="MDF digital filter configuration register 0" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0RSFR" description="MDF reshape filter configuration register 0" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0INTR" description="MDF integrator configuration register 0" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD0CR" description="MDF out-of limit detector control register 0" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD0THLR" description="MDF OLD0 low threshold register 0" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD0THHR" description="MDF OLD0 high threshold register 0" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY0CR" description="MDF delay control register 0" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD0CR" description="MDF short circuit detector control register 0" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0IER" description="MDF DFLT0 interrupt enable register 0" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLD0 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLD0 event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLD0 event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCD0 interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCD0 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCD0 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT0ISR" description="MDF DFLT0 interrupt status register 0" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLD0 flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLD0 event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLD0 event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLD0 event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLD0 event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLD0 event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLD0 event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD0 event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD0 event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC0CR" description="MDF offset error compensation control register 0" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS0DR" description="MDF snapshot data register 0" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT0DR" description="MDF digital filter data register 0" start="+0xF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF1CR" description="MDF serial interface control register 1" start="+0x100" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX1CR" description="MDF bitstream matrix control register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1CR" description="MDF digital filter control register 1" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1CICR" description="MDF digital filter configuration register 1" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1RSFR" description="MDF reshape filter configuration register 1" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1INTR" description="MDF integrator configuration register 1" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD1CR" description="MDF out-of limit detector control register 1" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD1THLR" description="MDF OLD1 low threshold register 1" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD1THHR" description="MDF OLD1 high threshold register 1" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY1CR" description="MDF delay control register 1" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD1CR" description="MDF short circuit detector control register 1" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1IER" description="MDF DFLT1 interrupt enable register 1" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT1ISR" description="MDF DFLT1 interrupt status register 1" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC1CR" description="MDF offset error compensation control register 1" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS1DR" description="MDF snapshot data register 1" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT1DR" description="MDF digital filter data register 1" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF2CR" description="MDF serial interface control register 2" start="+0x180" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX2CR" description="MDF bitstream matrix control register 2" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2CR" description="MDF digital filter control register 2" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2CICR" description="MDF digital filter configuration register 2" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2RSFR" description="MDF reshape filter configuration register 2" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2INTR" description="MDF integrator configuration register 2" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD2CR" description="MDF out-of limit detector control register 2" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD2THLR" description="MDF OLD2 low threshold register 2" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD2THHR" description="MDF OLD2 high threshold register 2" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY2CR" description="MDF delay control register 2" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD2CR" description="MDF short circuit detector control register 2" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2IER" description="MDF DFLT2 interrupt enable register 2" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT2ISR" description="MDF DFLT2 interrupt status register 2" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC2CR" description="MDF offset error compensation control register 2" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS2DR" description="MDF snapshot data register 2" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT2DR" description="MDF digital filter data register 2" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF3CR" description="MDF serial interface control register 3" start="+0x200" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX3CR" description="MDF bitstream matrix control register 3" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3CR" description="MDF digital filter control register 3" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3CICR" description="MDF digital filter configuration register 3" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3RSFR" description="MDF reshape filter configuration register 3" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3INTR" description="MDF integrator configuration register 3" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD3CR" description="MDF out-of limit detector control register 3" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD3THLR" description="MDF OLD3 low threshold register 3" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD3THHR" description="MDF OLD3 high threshold register 3" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY3CR" description="MDF delay control register 3" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD3CR" description="MDF short circuit detector control register 3" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3IER" description="MDF DFLT3 interrupt enable register 3" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT3ISR" description="MDF DFLT3 interrupt status register 3" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC3CR" description="MDF offset error compensation control register 3" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS3DR" description="MDF snapshot data register 3" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT3DR" description="MDF digital filter data register 3" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF4CR" description="MDF serial interface control register 4" start="+0x280" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX4CR" description="MDF bitstream matrix control register 4" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4CR" description="MDF digital filter control register 4" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4CICR" description="MDF digital filter configuration register 4" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4RSFR" description="MDF reshape filter configuration register 4" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4INTR" description="MDF integrator configuration register 4" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD4CR" description="MDF out-of limit detector control register 4" start="+0x298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD4THLR" description="MDF OLD4 low threshold register 4" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD4THHR" description="MDF OLD4 high threshold register 4" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY4CR" description="MDF delay control register 4" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD4CR" description="MDF short circuit detector control register 4" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4IER" description="MDF DFLT4 interrupt enable register 4" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT4ISR" description="MDF DFLT4 interrupt status register 4" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC4CR" description="MDF offset error compensation control register 4" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS4DR" description="MDF snapshot data register 4" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT4DR" description="MDF digital filter data register 4" start="+0x2F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_SITF5CR" description="MDF serial interface control register 5" start="+0x300" size="4" reset_value="0x00001F00" reset_mask="0xFFFFFFFF">
+      <BitField name="SITFEN" description="Serial interface enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="Serial interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCKSRC" description="Serial clock source" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Serial clock source is MDF_CCK0." start="0x0" />
+        <Enum name="B_0x1" description="Serial clock source is MDF_CCK1." start="0x1" />
+      </BitField>
+      <BitField name="SITFMOD" description="Serial interface type" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LF_MASTER SPI mode" start="0x0" />
+        <Enum name="B_0x1" description="Normal SPI mode" start="0x1" />
+        <Enum name="B_0x2" description="Manchester mode: rising edge = logic 0, falling edge = logic 1" start="0x2" />
+        <Enum name="B_0x3" description="Manchester mode: rising edge = logic 1, falling edge = logic 0" start="0x3" />
+      </BitField>
+      <BitField name="STH" description="Manchester symbol threshold/SPI threshold" start="8" size="5" access="Read/Write" />
+      <BitField name="SITFACTIVE" description="Serial interface active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The serial interface is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="The serial interface is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_BSMX5CR" description="MDF bitstream matrix control register 5" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSSEL" description="Bitstream Selection" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="bs0_r provided to DFLTx and SCDx" start="0x0" />
+        <Enum name="B_0x1" description="bs0_f provided to DFLTx and SCDx" start="0x1" />
+        <Enum name="B_0x2" description="bs1_r provided to DFLTx and SCDx (if instantiated)" start="0x2" />
+        <Enum name="B_0x3" description="bs1_f provided to DFLTx and SCDx (if instantiated)" start="0x3" />
+        <Enum name="B_0x1E" description="bs15_r provided to DFLTx and SCDx (if instantiated)" start="0x1E" />
+        <Enum name="B_0x1F" description="bs15_f provided to DFLTx and SCDx (if instantiated)" start="0x1F" />
+      </BitField>
+      <BitField name="BSMXACTIVE" description="BSMX active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BSMX is not active and can be configured if needed." start="0x0" />
+        <Enum name="B_0x1" description="BSMX is active and protected fields cannot be configured." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5CR" description="MDF digital filter control register 5" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFLTEN" description="Digital filter enable" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="Acquisition immediately stopped" start="0x0" />
+        <Enum name="B_0x1" description="Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA requests enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA interface for the corresponding digital filter disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA interface for the corresponding digital filter enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTH" description="RXFIFO Threshold selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold event generated when the RXFIFO is not empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold event generated when the RXFIFO is half-full" start="0x1" />
+      </BitField>
+      <BitField name="ACQMOD" description="Digital filter trigger mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Asynchronous continuous acquisition mode" start="0x0" />
+        <Enum name="B_0x1" description="Asynchronous single-shot acquisition mode" start="0x1" />
+        <Enum name="B_0x2" description="Synchronous continuous acquisition mode" start="0x2" />
+        <Enum name="B_0x3" description="Synchronous, single-shot acquisition mode" start="0x3" />
+        <Enum name="B_0x4" description="Window continuous acquisition mode" start="0x4" />
+        <Enum name="B_0x5" description="Synchronous snapshot mode" start="0x5" />
+      </BitField>
+      <BitField name="TRGSENS" description="Digital filter trigger sensitivity selection" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="A rising edge event triggers the acquisition." start="0x0" />
+        <Enum name="B_0x1" description="A falling edge even triggers the acquisition." start="0x1" />
+      </BitField>
+      <BitField name="TRGSRC" description="Digital filter trigger signal selection" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TRGO selected" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event selected" start="0x1" />
+        <Enum name="B_0x2" description="mdf_trg[0] selected" start="0x2" />
+        <Enum name="B_0xF" description="mdf_trg[13] selected" start="0xF" />
+      </BitField>
+      <BitField name="SNPSFMT" description="Snapshot data format" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Integrator counter (INT_CNT) not inserted into MDF_SNPSxDR, leaving a data resolution of 23 bits" start="0x0" />
+        <Enum name="B_0x1" description="Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPSxDR, leaving a data resolution of 16 bits." start="0x1" />
+      </BitField>
+      <BitField name="NBDIS" description="Number of samples to be discarded" start="20" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="No sample discarded" start="0x0" />
+        <Enum name="B_0x1" description="1 sample discarded" start="0x1" />
+      </BitField>
+      <BitField name="DFLTRUN" description="Digital filter run status flag" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not running and ready to accept a new trigger event" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter running" start="0x1" />
+      </BitField>
+      <BitField name="DFLTACTIVE" description="Digital filter active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Digital filter not active (can be re-enabled again, via DFLTEN, if needed)" start="0x0" />
+        <Enum name="B_0x1" description="Digital filter active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5CICR" description="MDF digital filter configuration register 5" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATSRC" description="Source data for the digital filter" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Stream coming from the ADCITF1 selected" start="0x2" />
+        <Enum name="B_0x3" description="Stream coming from the ADCITF2 selected" start="0x3" />
+      </BitField>
+      <BitField name="CICMOD" description="Select the CIC mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CIC split in two filters and MCIC configured in FastSinc filter" start="0x0" />
+        <Enum name="B_0x1" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;1less than/sup&gt; filter" start="0x1" />
+        <Enum name="B_0x2" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;2less than/sup&gt; filter" start="0x2" />
+        <Enum name="B_0x3" description="CIC split in two filters and MCIC configured in Sincless thansup&gt;3less than/sup&gt; filter" start="0x3" />
+        <Enum name="B_0x4" description="CIC configured in single Sincless thansup&gt;4less than/sup&gt; filter" start="0x4" />
+      </BitField>
+      <BitField name="MCICD" description="CIC decimation ratio selection" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="MCICD8" description="CIC decimation ratio selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 2." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor selection" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="0 dB" start="0x0" />
+        <Enum name="B_0x1" description="+ 3.5 dB" start="0x1" />
+        <Enum name="B_0x2" description="+ 6 dB or shift left by 1 bit" start="0x2" />
+        <Enum name="B_0x18" description="+ 72 dB or shift left by 12 bits" start="0x18" />
+        <Enum name="B_0x20" description="- 48.2 dB or shift right by 8 bits (default value)" start="0x20" />
+        <Enum name="B_0x21" description="- 44.6 dB" start="0x21" />
+        <Enum name="B_0x22" description="- 42.1 dB or shift right by 7 bits" start="0x22" />
+        <Enum name="B_0x23" description="- 38.6 dB" start="0x23" />
+        <Enum name="B_0x2E" description="- 6 dB or shift right by 1 bit" start="0x2E" />
+        <Enum name="B_0x2F" description="- 2.5 dB" start="0x2F" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5RSFR" description="MDF reshape filter configuration register 5" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RSFLTBYP" description="Reshaper filter bypass" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter bypassed" start="0x1" />
+      </BitField>
+      <BitField name="RSFLTD" description="Reshaper filter decimation ratio" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 4 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 1." start="0x1" />
+      </BitField>
+      <BitField name="HPFBYP" description="High-pass filter bypass" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPF not bypassed (default value)" start="0x0" />
+        <Enum name="B_0x1" description="HPF bypassed" start="0x1" />
+      </BitField>
+      <BitField name="HPFC" description="High-pass filter cut-off frequency" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Cut-off frequency = 0.000625 x Fless thansub&gt;PCMless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="Cut-off frequency = 0.00125 x Fless thansub&gt;PCMless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="Cut-off frequency = 0.00250 x Fless thansub&gt;PCMless than/sub&gt;" start="0x2" />
+        <Enum name="B_0x3" description="Cut-off frequency = 0.00950 x Fless thansub&gt;PCMless than/sub&gt;" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5INTR" description="MDF integrator configuration register 5" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTDIV" description="Integrator output division" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The integrator data outputs are divided by 128 (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The integrator data outputs are divided by 32." start="0x1" />
+        <Enum name="B_0x2" description="The integrator data outputs are divided by 4." start="0x2" />
+        <Enum name="B_0x3" description="The integrator data outputs are not divided." start="0x3" />
+      </BitField>
+      <BitField name="INTVAL" description="Integration value selection" start="4" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="The integration value is 1, meaning bypass mode (default after reset)." start="0x0" />
+        <Enum name="B_0x1" description="The integration value is 2." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD5CR" description="MDF out-of limit detector control register 5" start="+0x318" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDEN" description="OLDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx disabled (default value)" start="0x0" />
+        <Enum name="B_0x1" description="OLDx enabled, including the ACIC filter working in continuous mode" start="0x1" />
+      </BitField>
+      <BitField name="THINB" description="Threshold In band" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value)." start="0x0" />
+        <Enum name="B_0x1" description="The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL" start="0x1" />
+      </BitField>
+      <BitField name="BKOLD" description="Break signal assignment for out-of limit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="ACICN" description="OLDx CIC order selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FastSinc filter type" start="0x0" />
+        <Enum name="B_0x1" description="Sincless thansup&gt;1less than/sup&gt; filter type" start="0x1" />
+        <Enum name="B_0x2" description="Sincless thansup&gt;2less than/sup&gt; filter type" start="0x2" />
+        <Enum name="B_0x3" description="Sincless thansup&gt;3less than/sup&gt; filter type" start="0x3" />
+      </BitField>
+      <BitField name="ACICD" description="OLDx CIC decimation ratio selection" start="17" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Decimation ratio is 1." start="0x0" />
+        <Enum name="B_0x1" description="Decimation ratio is 2." start="0x1" />
+      </BitField>
+      <BitField name="OLDACTIVE" description="OLDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="OLDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="OLDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OLD5THLR" description="MDF OLD5 low threshold register 5" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHL" description="OLD low threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_OLD5THHR" description="MDF OLD5 high threshold register 5" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OLDTHH" description="OLDx high threshold value" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_DLY5CR" description="MDF delay control register 5" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SKPDLY" description="Delay to apply to a bitstream" start="0" size="7" access="Read/Write">
+        <Enum name="B_0x0" description="No input sample skipped" start="0x0" />
+        <Enum name="B_0x1" description="1 input sample skipped" start="0x1" />
+      </BitField>
+      <BitField name="SKPBF" description="Skip busy flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MDF ready to accept a new value into SKPDLY[6:0]" start="0x0" />
+        <Enum name="B_0x1" description="Last valid SKPDLY[6:0] still under processing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_SCD5CR" description="MDF short circuit detector control register 5" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDEN" description="SCDx enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSCDx enabled," start="0x1" />
+      </BitField>
+      <BitField name="BKSCD" description="Break signal assignment for short circuit detector" start="4" size="4" access="Read/Write" />
+      <BitField name="SCDT" description="SCDx threshold" start="12" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="2 consecutive 1's or 0's generate an event." start="0x0" />
+        <Enum name="B_0x1" description="2 consecutive 1's or 0's generate an event." start="0x1" />
+      </BitField>
+      <BitField name="SCDACTIVE" description="SCDx active flag" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SCDx not active and can be configured if needed" start="0x0" />
+        <Enum name="B_0x1" description="SCDx active and protected fields cannot be configured" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5IER" description="MDF DFLT5 interrupt enable register 5" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHIE" description="RXFIFO threshold interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXFIFO threshold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DOVRIE" description="Data overflow interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data overflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSDRIE" description="Snapshot data ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot data ready interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot data ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OLDIE" description="OLDx interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OLDx event interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OLDx event interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SSOVRIE" description="Snapshot overrun interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Snapshot overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Snapshot overrun interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCDIE" description="SCDx interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCDx interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SCDx interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SATIE" description="Saturation detection interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Saturation interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Saturation interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKABIE" description="Clock absence detection interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock absence interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock absence interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RFOVRIE" description="Reshape filter overrun interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reshape filter overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Reshape filter overrun interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_DFLT5ISR" description="MDF DFLT5 interrupt status register 5" start="+0x330" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTHF" description="RXFIFO threshold flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO threshold not reached" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO threshold reached" start="0x1" />
+      </BitField>
+      <BitField name="DOVRF" description="Data overflow flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no overflow is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an overflow is detected; Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SSDRF" description="Snapshot data ready flag" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no data is available. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a new data is available. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RXNEF" description="RXFIFO not-empty flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO empty" start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO not empty" start="0x1" />
+      </BitField>
+      <BitField name="OLDF" description="OLDx flag" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no OLDx event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF." start="0x1" />
+      </BitField>
+      <BitField name="THLF" description="Low-threshold status flag" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was higher than OLDTHL when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was lower than OLDTHL when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="THHF" description="High-threshold status flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The signal was lower than OLDTHH when the last OLDx event occurred." start="0x0" />
+        <Enum name="B_0x1" description="The signal was higher than OLDTHH when the last OLDx event occurred." start="0x1" />
+      </BitField>
+      <BitField name="SSOVRF" description="Snapshot overrun flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no snapshot overrun event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SCDF" description="Short-circuit detector flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no SCD event is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a SCD event is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="SATF" description="Saturation detection flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no saturation is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a saturation is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="CKABF" description="Clock absence detection flag" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no clock absence is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that a clock absence is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+      <BitField name="RFOVRF" description="Reshape filter overrun detection flag" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read 0 means that no reshape filter overrun is detected. Write 0 has no effect." start="0x0" />
+        <Enum name="B_0x1" description="Read 1 means that reshape filter overrun is detected. Write 1 clears this flag." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDF_OEC5CR" description="MDF offset error compensation control register 5" start="+0x334" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Offset error compensation" start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="MDF_SNPS5DR" description="MDF snapshot data register 5" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCICDC" description="Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)" start="0" size="9" access="ReadOnly" />
+      <BitField name="EXTSDR" description="Extended data size" start="9" size="7" access="ReadOnly" />
+      <BitField name="SDR" description="Contains the 16 MSB of the last valid data processed by the digital filter." start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDF_DFLT5DR" description="MDF digital filter data register 5" start="+0x370" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data processed by digital filter" start="8" size="24" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDIOS" description="Management data input/output" start="0x40009400">
+    <Register name="MDIOS_CR" description="MDIOS configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO)." start="0x1" />
+      </BitField>
+      <BitField name="WRIE" description="register write interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="RDIE" description="register read interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="EIE" description="error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DPC" description="disable preamble check" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIO master must give preamble before each frame." start="0x0" />
+        <Enum name="B_0x1" description="MDIO master can send each frame without a preceding preamble, and the MDIOS does not signal a preamble error." start="0x1" />
+      </BitField>
+      <BitField name="PORT_ADDRESS" description="slave address" start="8" size="5" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_WRFR" description="MDIOS write flag register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRF" description="write flags for MDIOS registers 0 to 31." start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="MDIOS register x is not written by the MDIO master." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS register x is written by the MDIO master and the data is available in DIN[15:0] in the MDIOS_DINRx register." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CWRFR" description="MDIOS clear write flag register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWRF" description="clear the write flag" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_RDFR" description="MDIOS read flag register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDF" description="read flags for MDIOS registers 0 to 31." start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="MDIOS register x is not read by the MDIO master." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS register x is read by the MDIO master." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CRDFR" description="MDIOS clear read flag register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRDF" description="clear the read flag" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_SR" description="MDIOS status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERF" description="preamble error flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No preamble error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A preamble error has occurred." start="0x1" />
+      </BitField>
+      <BitField name="SERF" description="start error flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No start error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A start error has occurred." start="0x1" />
+      </BitField>
+      <BitField name="TERF" description="turnaround error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No turnaround error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A turnaround error has occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CLRFR" description="MDIOS clear flag register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CPERF" description="clear the preamble error flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CSERF" description="clear the start error flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CTERF" description="clear the turnaround error flag" start="2" size="1" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DINR0" description="MDIOS input data register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR1" description="MDIOS input data register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR2" description="MDIOS input data register 2" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR3" description="MDIOS input data register 3" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR4" description="MDIOS input data register 4" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR5" description="MDIOS input data register 5" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR6" description="MDIOS input data register 6" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR7" description="MDIOS input data register 7" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR8" description="MDIOS input data register 8" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR9" description="MDIOS input data register 9" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR10" description="MDIOS input data register 10" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR11" description="MDIOS input data register 11" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR12" description="MDIOS input data register 12" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR13" description="MDIOS input data register 13" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR14" description="MDIOS input data register 14" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR15" description="MDIOS input data register 15" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR16" description="MDIOS input data register 16" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR17" description="MDIOS input data register 17" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR18" description="MDIOS input data register 18" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR19" description="MDIOS input data register 19" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR20" description="MDIOS input data register 20" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR21" description="MDIOS input data register 21" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR22" description="MDIOS input data register 22" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR23" description="MDIOS input data register 23" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR24" description="MDIOS input data register 24" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR25" description="MDIOS input data register 25" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR26" description="MDIOS input data register 26" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR27" description="MDIOS input data register 27" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR28" description="MDIOS input data register 28" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR29" description="MDIOS input data register 29" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR30" description="MDIOS input data register 30" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR31" description="MDIOS input data register 31" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DOUTR0" description="MDIOS output data register 0" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR1" description="MDIOS output data register 1" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR2" description="MDIOS output data register 2" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR3" description="MDIOS output data register 3" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR4" description="MDIOS output data register 4" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR5" description="MDIOS output data register 5" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR6" description="MDIOS output data register 6" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR7" description="MDIOS output data register 7" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR8" description="MDIOS output data register 8" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR9" description="MDIOS output data register 9" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR10" description="MDIOS output data register 10" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR11" description="MDIOS output data register 11" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR12" description="MDIOS output data register 12" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR13" description="MDIOS output data register 13" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR14" description="MDIOS output data register 14" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR15" description="MDIOS output data register 15" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR16" description="MDIOS output data register 16" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR17" description="MDIOS output data register 17" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR18" description="MDIOS output data register 18" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR19" description="MDIOS output data register 19" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR20" description="MDIOS output data register 20" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR21" description="MDIOS output data register 21" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR22" description="MDIOS output data register 22" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR23" description="MDIOS output data register 23" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR24" description="MDIOS output data register 24" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR25" description="MDIOS output data register 25" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR26" description="MDIOS output data register 26" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR27" description="MDIOS output data register 27" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR28" description="MDIOS output data register 28" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR29" description="MDIOS output data register 29" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR30" description="MDIOS output data register 30" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR31" description="MDIOS output data register 31" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDIOS_S" description="Management data input/output" start="0x50009400">
+    <Register name="MDIOS_CR" description="MDIOS configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO)." start="0x1" />
+      </BitField>
+      <BitField name="WRIE" description="register write interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="RDIE" description="register read interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="EIE" description="error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled." start="0x1" />
+      </BitField>
+      <BitField name="DPC" description="disable preamble check" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIO master must give preamble before each frame." start="0x0" />
+        <Enum name="B_0x1" description="MDIO master can send each frame without a preceding preamble, and the MDIOS does not signal a preamble error." start="0x1" />
+      </BitField>
+      <BitField name="PORT_ADDRESS" description="slave address" start="8" size="5" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_WRFR" description="MDIOS write flag register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRF" description="write flags for MDIOS registers 0 to 31." start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="MDIOS register x is not written by the MDIO master." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS register x is written by the MDIO master and the data is available in DIN[15:0] in the MDIOS_DINRx register." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CWRFR" description="MDIOS clear write flag register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWRF" description="clear the write flag" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_RDFR" description="MDIOS read flag register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDF" description="read flags for MDIOS registers 0 to 31." start="0" size="32" access="ReadOnly">
+        <Enum name="B_0x0" description="MDIOS register x is not read by the MDIO master." start="0x0" />
+        <Enum name="B_0x1" description="MDIOS register x is read by the MDIO master." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CRDFR" description="MDIOS clear read flag register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRDF" description="clear the read flag" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_SR" description="MDIOS status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERF" description="preamble error flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No preamble error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A preamble error has occurred." start="0x1" />
+      </BitField>
+      <BitField name="SERF" description="start error flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No start error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A start error has occurred." start="0x1" />
+      </BitField>
+      <BitField name="TERF" description="turnaround error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No turnaround error has occurred." start="0x0" />
+        <Enum name="B_0x1" description="A turnaround error has occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="MDIOS_CLRFR" description="MDIOS clear flag register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CPERF" description="clear the preamble error flag" start="0" size="1" access="Read/Write" />
+      <BitField name="CSERF" description="clear the start error flag" start="1" size="1" access="Read/Write" />
+      <BitField name="CTERF" description="clear the turnaround error flag" start="2" size="1" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DINR0" description="MDIOS input data register 0" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR1" description="MDIOS input data register 1" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR2" description="MDIOS input data register 2" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR3" description="MDIOS input data register 3" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR4" description="MDIOS input data register 4" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR5" description="MDIOS input data register 5" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR6" description="MDIOS input data register 6" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR7" description="MDIOS input data register 7" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR8" description="MDIOS input data register 8" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR9" description="MDIOS input data register 9" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR10" description="MDIOS input data register 10" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR11" description="MDIOS input data register 11" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR12" description="MDIOS input data register 12" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR13" description="MDIOS input data register 13" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR14" description="MDIOS input data register 14" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR15" description="MDIOS input data register 15" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR16" description="MDIOS input data register 16" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR17" description="MDIOS input data register 17" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR18" description="MDIOS input data register 18" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR19" description="MDIOS input data register 19" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR20" description="MDIOS input data register 20" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR21" description="MDIOS input data register 21" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR22" description="MDIOS input data register 22" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR23" description="MDIOS input data register 23" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR24" description="MDIOS input data register 24" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR25" description="MDIOS input data register 25" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR26" description="MDIOS input data register 26" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR27" description="MDIOS input data register 27" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR28" description="MDIOS input data register 28" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR29" description="MDIOS input data register 29" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR30" description="MDIOS input data register 30" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DINR31" description="MDIOS input data register 31" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="input data received from MDIO master during write frames" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="MDIOS_DOUTR0" description="MDIOS output data register 0" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR1" description="MDIOS output data register 1" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR2" description="MDIOS output data register 2" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR3" description="MDIOS output data register 3" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR4" description="MDIOS output data register 4" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR5" description="MDIOS output data register 5" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR6" description="MDIOS output data register 6" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR7" description="MDIOS output data register 7" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR8" description="MDIOS output data register 8" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR9" description="MDIOS output data register 9" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR10" description="MDIOS output data register 10" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR11" description="MDIOS output data register 11" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR12" description="MDIOS output data register 12" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR13" description="MDIOS output data register 13" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR14" description="MDIOS output data register 14" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR15" description="MDIOS output data register 15" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR16" description="MDIOS output data register 16" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR17" description="MDIOS output data register 17" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR18" description="MDIOS output data register 18" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR19" description="MDIOS output data register 19" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR20" description="MDIOS output data register 20" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR21" description="MDIOS output data register 21" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR22" description="MDIOS output data register 22" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR23" description="MDIOS output data register 23" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR24" description="MDIOS output data register 24" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR25" description="MDIOS output data register 25" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR26" description="MDIOS output data register 26" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR27" description="MDIOS output data register 27" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR28" description="MDIOS output data register 28" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR29" description="MDIOS output data register 29" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR30" description="MDIOS output data register 30" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="MDIOS_DOUTR31" description="MDIOS output data register 31" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="output data sent to MDIO Master during read frames" start="0" size="16" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1" description="USB on-the-go high-speed" start="0x48040000">
+    <Register name="OTG_GOTGCTL" description="OTG control and status register" start="+0x000" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="VBVALOEN" description="Vless thansub&gt;BUSless than/sub&gt; valid override enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Vless thansub&gt;BUSless than/sub&gt; valid override value." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vbusvalid value is '0' when VBVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="vbusvalid value is '1' when VBVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="AVALOEN" description="A-peripheral session valid override enable." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Avalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally Avalid received from the PHY is overridden with AVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="AVALOVAL" description="A-peripheral session valid override value." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Avalid value is '0' when AVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Avalid value is '1' when AVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="BVALOEN" description="B-peripheral session valid override enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+      </BitField>
+      <BitField name="BVALOVAL" description="B-peripheral session valid override value." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bvalid value is '0' when BVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Bvalid value is '1' when BVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="EHEN" description="Embedded host enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG A device state machine is selected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded host state machine is selected" start="0x1" />
+      </BitField>
+      <BitField name="CIDSTS" description="Connector ID status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The OTG controller is in A-device mode" start="0x0" />
+        <Enum name="B_0x1" description="The OTG controller is in B-device mode" start="0x1" />
+      </BitField>
+      <BitField name="DBCT" description="Long/short debounce time" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Long debounce time, used for physical connections (100 ms + 2.5 s)" start="0x0" />
+        <Enum name="B_0x1" description="Short debounce time, used for soft connections (2.5 s)" start="0x1" />
+      </BitField>
+      <BitField name="ASVLD" description="A-session valid" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A-session is not valid" start="0x0" />
+        <Enum name="B_0x1" description="A-session is valid" start="0x1" />
+      </BitField>
+      <BitField name="BSVLD" description="B-session valid" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="B-session is not valid." start="0x0" />
+        <Enum name="B_0x1" description="B-session is valid." start="0x1" />
+      </BitField>
+      <BitField name="OTGVER" description="OTG version" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG Version 1.3. OTG1.3 is obsolete for new product development." start="0x0" />
+        <Enum name="B_0x1" description="OTG Version 2.0. In this version the core supports only data line pulsing for SRP." start="0x1" />
+      </BitField>
+      <BitField name="CURMOD" description="Current mode of operation" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GOTGINT" description="OTG interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDET" description="Session end detected" start="2" size="1" access="Read/Write" />
+      <BitField name="ADTOCHG" description="A-device timeout change" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GAHBCFG" description="OTG AHB configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GINTMSK" description="Global interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Mask the interrupt assertion to the application." start="0x0" />
+        <Enum name="B_0x1" description="Unmask the interrupt assertion to the application." start="0x1" />
+      </BitField>
+      <BitField name="HBSTLEN" description="Burst length/type " start="1" size="4" access="Read/Write" />
+      <BitField name="DMAEN" description="DMA enabled" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core operates in slave mode" start="0x0" />
+        <Enum name="B_0x1" description="The core operates in DMA mode" start="0x1" />
+      </BitField>
+      <BitField name="TXFELVL" description="Tx FIFO empty level" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+      <BitField name="PTXFELVL" description="Periodic Tx FIFO empty level" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GUSBCFG" description="OTG USB configuration register" start="+0x00C" size="4" reset_value="0x00001400" reset_mask="0xFFFFFFFF">
+      <BitField name="TOCAL" description="FS timeout calibration" start="0" size="3" access="Read/Write" />
+      <BitField name="TRDT" description="USB turnaround time" start="10" size="4" access="Read/Write" />
+      <BitField name="PHYLPC" description="PHY Low-power clock select " start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="480 MHz internal PLL clock" start="0x0" />
+        <Enum name="B_0x1" description="48 MHz external clock" start="0x1" />
+      </BitField>
+      <BitField name="TSDPS" description="TermSel DLine pulsing selection " start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data line pulsing using utmi_txvalid (default)" start="0x0" />
+        <Enum name="B_0x1" description="Data line pulsing using utmi_termsel" start="0x1" />
+      </BitField>
+      <BitField name="FHMOD" description="Force host mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode" start="0x1" />
+      </BitField>
+      <BitField name="FDMOD" description="Force device mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force device mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRSTCTL" description="OTG reset register" start="+0x010" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSRST" description="Core soft reset" start="0" size="1" access="Read/Write" />
+      <BitField name="PSRST" description="Partial soft reset" start="1" size="1" access="Read/Write" />
+      <BitField name="FCRST" description="Host frame counter reset" start="2" size="1" access="Read/Write" />
+      <BitField name="RXFFLSH" description="Rx FIFO flush" start="4" size="1" access="Read/Write" />
+      <BitField name="TXFFLSH" description="Tx FIFO flush" start="5" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_HOST_MODE" description="Non-periodic Tx FIFO flush" start="0x0" />
+        <Enum name="B_0x1_HOST_MODE" description="Periodic Tx FIFO flush" start="0x1" />
+        <Enum name="B_0x10_HOST_MODE" description="Flush all the transmit FIFOs" start="0x10" />
+        <Enum name="B_0x2_DEVICE_MODE" description="Tx FIFO 2 flush" start="0x2" />
+        <Enum name="B_0xF_DEVICE_MODE" description="Tx FIFO 15 flush" start="0xF" />
+      </BitField>
+      <BitField name="DMAREQ" description="DMA request signal enabled" start="30" size="1" access="ReadOnly" />
+      <BitField name="AHBIDL" description="AHB master idle" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GINTSTS" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="IPXFR" description="Incomplete periodic transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTSTS_ALTERNATE" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="INCOMPISOOUT" description="Incomplete isochronous OUT transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTMSK" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NPTXFEM" description="Non-periodic Tx FIFO empty mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IPXFRM" description="Incomplete periodic transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PRTIM" description="Host port interrupt mask" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="HCIM" description="Host channels interrupt mask" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PTXFEM" description="Periodic Tx FIFO empty mask" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DISCINT" description="Disconnect detected interrupt mask" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GINTMSK_ALTERNATE" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GINAKEFFM" description="Global non-periodic IN NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GONAKEFFM" description="Global OUT NAK effective mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ESUSPM" description="Early suspend mask" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBSUSPM" description="USB suspend mask" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBRST" description="USB reset mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ENUMDNEM" description="Enumeration done mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ISOODRPM" description="Isochronous OUT packet dropped interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EOPFM" description="End of periodic frame interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IEPINT" description="IN endpoints interrupt mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPINT" description="OUT endpoints interrupt mask" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOIXFRM" description="Incomplete isochronous IN transfer mask" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOOXFRM" description="Incomplete isochronous OUT transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FSUSPM" description="Data fetch suspended mask" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RSTDETM" description="Reset detected interrupt mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSR" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSR_ALTERNATE" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSP" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSP_ALTERNATE" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXFSIZ" description="OTG receive FIFO size register" start="+0x024" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFD" description="Rx FIFO depth" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSA" description="Non-periodic transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="NPTXFD" description="Non-periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ_ALTERNATE" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TX0FSA" description="Endpoint 0 transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="TX0FD" description="Endpoint 0 Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXSTS" description="OTG non-periodic transmit FIFO/queue status register" start="+0x02C" size="4" reset_value="0x00080400" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSAV" description="Non-periodic Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="NPTQXSAV" description="Non-periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="NPTXQTOP" description="Top of the non-periodic transmit request queue" start="24" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GCCFG" description="OTG general core configuration register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="CHGDET" description="Charger detection, result of the current mode (primary or secondary)." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Low value on pin" start="0x0" />
+        <Enum name="B_0x1" description="High value on pin" start="0x1" />
+      </BitField>
+      <BitField name="FSVPLUS" description="Single-Ended DP indicator" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="FSVMINUS" description="Single-Ended DM indicator" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="SESSVLD" description="VBUS session indicator" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS session threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS session threshold" start="0x1" />
+      </BitField>
+      <BitField name="VBUSVLD" description="VBUS valid indicator" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS valid threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS valid threshold" start="0x1" />
+      </BitField>
+      <BitField name="HCDPEN" description="Host CDP behavior enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable CDP behavior" start="0x0" />
+        <Enum name="B_0x1" description="Enable CDP behavior" start="0x1" />
+      </BitField>
+      <BitField name="HCDPDETEN" description="Host CDP port voltage detector enable on DP" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DP voltage detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="DP voltage detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="HVDMSRCEN" description="Host CDP port Voltage source enable on DM" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DM voltage source disabled" start="0x0" />
+        <Enum name="B_0x1" description="DM Voltage source enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCDEN" description="Data Contact Detection enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data Contact Detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data Contact Detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="PDEN" description="Primary detection enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Primary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Primary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="Secondary detection enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secondary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Secondary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Software override value of the VBUS B-session detection" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="B-session inactive" start="0x0" />
+        <Enum name="B_0x1" description="B-session active" start="0x1" />
+      </BitField>
+      <BitField name="FORCEHOSTPD" description="Force host mode pull-downs" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force host mode pull-downs" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode pull-downs" start="0x1" />
+      </BitField>
+      <BitField name="BCDEN" description="Force Battery charging (BC) mode" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal USB mode" start="0x0" />
+        <Enum name="B_0x1" description="Battery Charging mode" start="0x1" />
+      </BitField>
+      <BitField name="IDPULLUPDIS" description="Disable ID pin pull-up" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enables ID pin pull-up" start="0x0" />
+        <Enum name="B_0x1" description="Disable ID pin pull-up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_CID" description="OTG core ID register" start="+0x03C" size="4" reset_value="0x00005000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRODUCT_ID" description="Product ID field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GLPMCFG" description="OTG core LPM configuration register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPMEN" description="LPM support enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPM capability is not enabled" start="0x0" />
+        <Enum name="B_0x1" description="LPM capability is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPMACK" description="LPM token acknowledge enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="ACK" start="0x1" />
+        <Enum name="B_0x0" description="NYET" start="0x0" />
+      </BitField>
+      <BitField name="BESL" description="Best effort service latency" start="2" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="125" start="0x0" />
+        <Enum name="B_0x1" description="150" start="0x1" />
+        <Enum name="B_0x2" description="200" start="0x2" />
+        <Enum name="B_0x3" description="300" start="0x3" />
+        <Enum name="B_0x4" description="400" start="0x4" />
+        <Enum name="B_0x5" description="500" start="0x5" />
+        <Enum name="B_0x6" description="1000" start="0x6" />
+        <Enum name="B_0x7" description="2000" start="0x7" />
+        <Enum name="B_0x8" description="3000" start="0x8" />
+        <Enum name="B_0x9" description="4000" start="0x9" />
+        <Enum name="B_0xA" description="5000" start="0xA" />
+        <Enum name="B_0xB" description="6000" start="0xB" />
+        <Enum name="B_0xC" description="7000" start="0xC" />
+        <Enum name="B_0xD" description="8000" start="0xD" />
+        <Enum name="B_0xE" description="9000" start="0xE" />
+        <Enum name="B_0xF" description="10000" start="0xF" />
+      </BitField>
+      <BitField name="REMWAKE" description="bRemoteWake value" start="6" size="1" access="Read/Write" />
+      <BitField name="L1SSEN" description="L1 Shallow Sleep enable" start="7" size="1" access="Read/Write" />
+      <BitField name="BESLTHRS" description="BESL threshold" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="75" start="0x0" />
+        <Enum name="B_0x1" description="100" start="0x1" />
+        <Enum name="B_0x2" description="150" start="0x2" />
+        <Enum name="B_0x3" description="250" start="0x3" />
+        <Enum name="B_0x4" description="350" start="0x4" />
+        <Enum name="B_0x5" description="450" start="0x5" />
+        <Enum name="B_0x6" description="950" start="0x6" />
+      </BitField>
+      <BitField name="L1DSEN" description="L1 deep sleep enable" start="12" size="1" access="Read/Write" />
+      <BitField name="LPMRSP" description="LPM response" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x3" description="ACK" start="0x3" />
+        <Enum name="B_0x2" description="NYET" start="0x2" />
+        <Enum name="B_0x1" description="STALL" start="0x1" />
+        <Enum name="B_0x0" description="ERROR (No handshake response)" start="0x0" />
+      </BitField>
+      <BitField name="SLPSTS" description="Port sleep status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Core not in L1" start="0x0" />
+        <Enum name="B_0x1" description="Core in L1" start="0x1" />
+      </BitField>
+      <BitField name="L1RSMOK" description="Sleep state resume OK" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="The application or host can start resume from Sleep state" start="0x1" />
+        <Enum name="B_0x0" description="The application or host cannot start resume from Sleep state" start="0x0" />
+      </BitField>
+      <BitField name="LPMCHIDX" description="LPM Channel Index" start="17" size="4" access="Read/Write" />
+      <BitField name="LPMRCNT" description="LPM retry count" start="21" size="3" access="Read/Write" />
+      <BitField name="SNDLPM" description="Send LPM transaction" start="24" size="1" access="Read/Write" />
+      <BitField name="LPMRCNTSTS" description="LPM retry count status" start="25" size="3" access="ReadOnly" />
+      <BitField name="ENBESL" description="Enable best effort service latency" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core works as described in the following document:" start="0x0" />
+        <Enum name="B_0x1" description="The core works as described in the LPM Errata:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPTXFSIZ" description="OTG host periodic transmit FIFO size register" start="+0x100" size="4" reset_value="0x04000800" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXSA" description="Host periodic Tx FIFO start address" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXFSIZ" description="Host periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF1" description="OTG device IN endpoint transmit FIFO 1 size register" start="+0x104" size="4" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF2" description="OTG device IN endpoint transmit FIFO 2 size register" start="+0x108" size="4" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF3" description="OTG device IN endpoint transmit FIFO 3 size register" start="+0x10C" size="4" reset_value="0x02000800" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF4" description="OTG device IN endpoint transmit FIFO 4 size register" start="+0x110" size="4" reset_value="0x02000A00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF5" description="OTG device IN endpoint transmit FIFO 5 size register" start="+0x114" size="4" reset_value="0x02000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF6" description="OTG device IN endpoint transmit FIFO 6 size register" start="+0x118" size="4" reset_value="0x02000E00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF7" description="OTG device IN endpoint transmit FIFO 7 size register" start="+0x11C" size="4" reset_value="0x02001000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF8" description="OTG device IN endpoint transmit FIFO 8 size register" start="+0x120" size="4" reset_value="0x02001200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCFG" description="OTG host configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x1_FS_HOST_MODE" description="PHY clock is running at 48 MHz" start="0x1" />
+        <Enum name="B_0x2_LS_HOST_MODE" description="Select 6 MHz PHY clock frequency" start="0x2" />
+      </BitField>
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HFIR" description="OTG host frame interval register" start="+0x404" size="4" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval " start="0" size="16" access="Read/Write" />
+      <BitField name="RLDCTRL" description="Reload control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The HFIR cannot be reloaded dynamically" start="0x0" />
+        <Enum name="B_0x1" description="The HFIR can be dynamically reloaded during run time." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HFNUM" description="OTG host frame number/frame time remaining register" start="+0x408" size="4" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" access="ReadOnly" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HPTXSTS" description="OTG_Host periodic transmit FIFO/queue status register" start="+0x410" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINT" description="OTG host all channels interrupt register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINTMSK" description="OTG host all channels interrupt mask register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPRT" description="OTG host port control and status register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No device is attached to the port" start="0x0" />
+        <Enum name="B_0x1" description="A device is attached to the port" start="0x1" />
+      </BitField>
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port disabled" start="0x0" />
+        <Enum name="B_0x1" description="Port enabled" start="0x1" />
+      </BitField>
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overcurrent condition" start="0x0" />
+        <Enum name="B_0x1" description="Overcurrent condition" start="0x1" />
+      </BitField>
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No resume driven" start="0x0" />
+        <Enum name="B_0x1" description="Resume driven" start="0x1" />
+      </BitField>
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in suspend mode" start="0x0" />
+        <Enum name="B_0x1" description="Port in suspend mode" start="0x1" />
+      </BitField>
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in reset" start="0x0" />
+        <Enum name="B_0x1" description="Port in reset" start="0x1" />
+      </BitField>
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Power off" start="0x0" />
+        <Enum name="B_0x1" description="Power on" start="0x1" />
+      </BitField>
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+        <Enum name="B_0x2" description="Low speed" start="0x2" />
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCCHAR0" description="OTG host channel 0 characteristics register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT0" description="OTG host channel 0 split control register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT0" description="OTG host channel 0 interrupt register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK0" description="OTG host channel 0 interrupt mask register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ0" description="OTG host channel 0 transfer size register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA0" description="OTG host channel 0 DMA address register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR1" description="OTG host channel 1 characteristics register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT1" description="OTG host channel 1 split control register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT1" description="OTG host channel 1 interrupt register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK1" description="OTG host channel 1 interrupt mask register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ1" description="OTG host channel 1 transfer size register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA1" description="OTG host channel 1 DMA address register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR2" description="OTG host channel 2 characteristics register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT2" description="OTG host channel 2 split control register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT2" description="OTG host channel 2 interrupt register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK2" description="OTG host channel 2 interrupt mask register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ2" description="OTG host channel 2 transfer size register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA2" description="OTG host channel 2 DMA address register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR3" description="OTG host channel 3 characteristics register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT3" description="OTG host channel 3 split control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT3" description="OTG host channel 3 interrupt register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK3" description="OTG host channel 3 interrupt mask register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ3" description="OTG host channel 3 transfer size register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA3" description="OTG host channel 3 DMA address register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR4" description="OTG host channel 4 characteristics register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT4" description="OTG host channel 4 split control register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT4" description="OTG host channel 4 interrupt register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK4" description="OTG host channel 4 interrupt mask register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ4" description="OTG host channel 4 transfer size register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA4" description="OTG host channel 4 DMA address register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR5" description="OTG host channel 5 characteristics register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT5" description="OTG host channel 5 split control register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT5" description="OTG host channel 5 interrupt register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK5" description="OTG host channel 5 interrupt mask register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ5" description="OTG host channel 5 transfer size register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA5" description="OTG host channel 5 DMA address register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR6" description="OTG host channel 6 characteristics register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT6" description="OTG host channel 6 split control register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT6" description="OTG host channel 6 interrupt register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK6" description="OTG host channel 6 interrupt mask register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ6" description="OTG host channel 6 transfer size register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA6" description="OTG host channel 6 DMA address register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR7" description="OTG host channel 7 characteristics register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT7" description="OTG host channel 7 split control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT7" description="OTG host channel 7 interrupt register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK7" description="OTG host channel 7 interrupt mask register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ7" description="OTG host channel 7 transfer size register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA7" description="OTG host channel 7 DMA address register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR8" description="OTG host channel 8 characteristics register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT8" description="OTG host channel 8 split control register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT8" description="OTG host channel 8 interrupt register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK8" description="OTG host channel 8 interrupt mask register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ8" description="OTG host channel 8 transfer size register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA8" description="OTG host channel 8 DMA address register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR9" description="OTG host channel 9 characteristics register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT9" description="OTG host channel 9 split control register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT9" description="OTG host channel 9 interrupt register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK9" description="OTG host channel 9 interrupt mask register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ9" description="OTG host channel 9 transfer size register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA9" description="OTG host channel 9 DMA address register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR10" description="OTG host channel 10 characteristics register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT10" description="OTG host channel 10 split control register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT10" description="OTG host channel 10 interrupt register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK10" description="OTG host channel 10 interrupt mask register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ10" description="OTG host channel 10 transfer size register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA10" description="OTG host channel 10 DMA address register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR11" description="OTG host channel 11 characteristics register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT11" description="OTG host channel 11 split control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT11" description="OTG host channel 11 interrupt register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK11" description="OTG host channel 11 interrupt mask register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ11" description="OTG host channel 11 transfer size register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA11" description="OTG host channel 11 DMA address register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR12" description="OTG host channel 12 characteristics register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT12" description="OTG host channel 12 split control register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT12" description="OTG host channel 12 interrupt register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK12" description="OTG host channel 12 interrupt mask register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ12" description="OTG host channel 12 transfer size register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA12" description="OTG host channel 12 DMA address register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR13" description="OTG host channel 13 characteristics register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT13" description="OTG host channel 13 split control register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT13" description="OTG host channel 13 interrupt register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK13" description="OTG host channel 13 interrupt mask register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ13" description="OTG host channel 13 transfer size register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA13" description="OTG host channel 13 DMA address register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR14" description="OTG host channel 14 characteristics register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT14" description="OTG host channel 14 split control register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT14" description="OTG host channel 14 interrupt register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK14" description="OTG host channel 14 interrupt mask register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ14" description="OTG host channel 14 transfer size register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA14" description="OTG host channel 14 DMA address register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR15" description="OTG host channel 15 characteristics register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT15" description="OTG host channel 15 split control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT15" description="OTG host channel 15 interrupt register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK15" description="OTG host channel 15 interrupt mask register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ15" description="OTG host channel 15 transfer size register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA15" description="OTG host channel 15 DMA address register" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DCFG" description="OTG device configuration register" start="+0x800" size="4" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+      </BitField>
+      <BitField name="NZLSOHSK" description="Non-zero-length status OUT handshake" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application." start="0x1" />
+        <Enum name="B_0x0" description="Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register." start="0x0" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="4" size="7" access="Read/Write" />
+      <BitField name="PFIVL" description="Periodic frame interval" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="80% of the frame interval" start="0x0" />
+        <Enum name="B_0x1" description="85% of the frame interval" start="0x1" />
+        <Enum name="B_0x2" description="90% of the frame interval" start="0x2" />
+        <Enum name="B_0x3" description="95% of the frame interval" start="0x3" />
+      </BitField>
+      <BitField name="ERRATIM" description="Erratic error interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Mask early suspend interrupt on erratic error" start="0x1" />
+        <Enum name="B_0x0" description="Early suspend interrupt is generated on erratic error" start="0x0" />
+      </BitField>
+      <BitField name="PERSCHIVL" description="Periodic schedule interval" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="25% of (micro)frame" start="0x0" />
+        <Enum name="B_0x1" description="50% of (micro)frame" start="0x1" />
+        <Enum name="B_0x2" description="75% of (micro)frame" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DCTL" description="OTG device control register" start="+0x804" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wake-up signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration." start="0x0" />
+        <Enum name="B_0x1" description="The core generates a device disconnect event to the USB host." start="0x1" />
+      </BitField>
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent out based on the data availability in the transmit FIFO." start="0x0" />
+        <Enum name="B_0x1" description="A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO." start="0x1" />
+      </BitField>
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent based on the FIFO status and the NAK and STALL bit settings." start="0x0" />
+        <Enum name="B_0x1" description="No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped." start="0x1" />
+      </BitField>
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+      <BitField name="DSBESLRJCT" description="Deep sleep BESL reject" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DSTS" description="OTG device status register" start="+0x808" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" access="ReadOnly" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="High Speed" start="0x0" />
+        <Enum name="B_0x1" description="Full Speed" start="0x1" />
+      </BitField>
+      <BitField name="EERR" description="Erratic error" start="3" size="1" access="ReadOnly" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" access="ReadOnly" />
+      <BitField name="DEVLNSTS" description="Device line status" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DIEPMSK" description="OTG device IN endpoint common interrupt mask register" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TOM" description="Timeout condition mask (Non-isochronous endpoints)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ITTXFEMSK" description="IN token received when Tx FIFO empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPMSK" description="OTG device OUT endpoint common interrupt mask register" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STUPM" description="STUPM: SETUP phase done mask. Applies to control endpoints only." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STSPHSRXM" description="Status phase received for control write mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="B2BSTUPM" description="Back-to-back SETUP packets received mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OUTPKTERRM" description="Out packet error mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BERRM" description="Babble error interrupt mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKMSK" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYETMSK" description="NYET interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DAINT" description="OTG device all endpoints interrupt register" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DAINTMSK" description="OTG all endpoints interrupt mask register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DTHRCTL" description="OTG device threshold control register" start="+0x0830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" access="Read/Write" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" access="Read/Write" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" access="Read/Write" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPEMPMSK" description="OTG device IN endpoint FIFO empty interrupt mask register" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL0" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL0_ALTERNATE" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT0" description="OTG device IN endpoint 0 interrupt register" start="+0x908" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ0" description="OTG device IN endpoint 0 transfer size register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPDMA0" description="OTG device IN endpoint 0 DMA address register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS0" description="OTG device IN endpoint transmit FIFO status register" start="+0x918" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL1" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL1_ALTERNATE" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT1" description="OTG device IN endpoint 1 interrupt register" start="+0x928" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ1" description="OTG device IN endpoint 1 transfer size register" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA1" description="OTG device IN endpoint 1 DMA address register" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS1" description="OTG device IN endpoint transmit FIFO status register" start="+0x938" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL2" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL2_ALTERNATE" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT2" description="OTG device IN endpoint 2 interrupt register" start="+0x948" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ2" description="OTG device IN endpoint 2 transfer size register" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA2" description="OTG device IN endpoint 2 DMA address register" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS2" description="OTG device IN endpoint transmit FIFO status register" start="+0x958" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL3" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL3_ALTERNATE" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT3" description="OTG device IN endpoint 3 interrupt register" start="+0x968" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ3" description="OTG device IN endpoint 3 transfer size register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA3" description="OTG device IN endpoint 3 DMA address register" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS3" description="OTG device IN endpoint transmit FIFO status register" start="+0x978" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL4" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL4_ALTERNATE" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT4" description="OTG device IN endpoint 4 interrupt register" start="+0x988" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ4" description="OTG device IN endpoint 4 transfer size register" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA4" description="OTG device IN endpoint 4 DMA address register" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS4" description="OTG device IN endpoint transmit FIFO status register" start="+0x998" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL5" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL5_ALTERNATE" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT5" description="OTG device IN endpoint 5 interrupt register" start="+0x9A8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ5" description="OTG device IN endpoint 5 transfer size register" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA5" description="OTG device IN endpoint 5 DMA address register" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS5" description="OTG device IN endpoint transmit FIFO status register" start="+0x9B8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL6" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL6_ALTERNATE" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT6" description="OTG device IN endpoint 6 interrupt register" start="+0x9C8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ6" description="OTG device IN endpoint 6 transfer size register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA6" description="OTG device IN endpoint 6 DMA address register" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS6" description="OTG device IN endpoint transmit FIFO status register" start="+0x9D8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL7" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL7_ALTERNATE" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT7" description="OTG device IN endpoint 7 interrupt register" start="+0x9E8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ7" description="OTG device IN endpoint 7 transfer size register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA7" description="OTG device IN endpoint 7 DMA address register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS7" description="OTG device IN endpoint transmit FIFO status register" start="+0x9F8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL8" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL8_ALTERNATE" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT8" description="OTG device IN endpoint 8 interrupt register" start="+0xA08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ8" description="OTG device IN endpoint 8 transfer size register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA8" description="OTG device IN endpoint 8 DMA address register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS8" description="OTG device IN endpoint transmit FIFO status register" start="+0xA18" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPCTL0" description="OTG device control OUT endpoint 0 control register" start="+0xB00" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="32 bytes" start="0x1" />
+        <Enum name="B_0x2" description="16 bytes" start="0x2" />
+        <Enum name="B_0x3" description="8 bytes" start="0x3" />
+      </BitField>
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_DOEPINT0" description="OTG device OUT endpoint 0 interrupt register" start="+0xB08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ0" description="OTG device OUT endpoint 0 transfer size register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" access="Read/Write" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA0" description="OTG device OUT endpoint 0 DMA address register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1_ALTERNATE" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT1" description="OTG device OUT endpoint 1 interrupt register" start="+0xB28" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ1" description="OTG device OUT endpoint 1 transfer size register" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA1" description="OTG device OUT endpoint 1 DMA address register" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2_ALTERNATE" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT2" description="OTG device OUT endpoint 2 interrupt register" start="+0xB48" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ2" description="OTG device OUT endpoint 2 transfer size register" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA2" description="OTG device OUT endpoint 2 DMA address register" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3_ALTERNATE" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT3" description="OTG device OUT endpoint 3 interrupt register" start="+0xB68" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ3" description="OTG device OUT endpoint 3 transfer size register" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA3" description="OTG device OUT endpoint 3 DMA address register" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4_ALTERNATE" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT4" description="OTG device OUT endpoint 4 interrupt register" start="+0xB88" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ4" description="OTG device OUT endpoint 4 transfer size register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA4" description="OTG device OUT endpoint 4 DMA address register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5_ALTERNATE" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT5" description="OTG device OUT endpoint 5 interrupt register" start="+0xBA8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ5" description="OTG device OUT endpoint 5 transfer size register" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA5" description="OTG device OUT endpoint 5 DMA address register" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6_ALTERNATE" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT6" description="OTG device OUT endpoint 6 interrupt register" start="+0xBC8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ6" description="OTG device OUT endpoint 6 transfer size register" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA6" description="OTG device OUT endpoint 6 DMA address register" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7_ALTERNATE" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT7" description="OTG device OUT endpoint 7 interrupt register" start="+0xBE8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ7" description="OTG device OUT endpoint 7 transfer size register" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA7" description="OTG device OUT endpoint 7 DMA address register" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8_ALTERNATE" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT8" description="OTG device OUT endpoint 8 interrupt register" start="+0xC08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ8" description="OTG device OUT endpoint 8 transfer size register" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA8" description="OTG device OUT endpoint 8 DMA address register" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_PCGCCTL" description="OTG power and clock gating control register" start="+0xE00" size="4" reset_value="0x200B8000" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" access="Read/Write" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" access="Read/Write" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" access="ReadOnly" />
+      <BitField name="ENL1GTG" description="Enable sleep clock gating" start="5" size="1" access="Read/Write" />
+      <BitField name="PHYSLEEP" description="PHY in Sleep" start="6" size="1" access="ReadOnly" />
+      <BitField name="SUSP" description="Deep Sleep" start="7" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_PCGCCTL1" description="OTG power and clock gating control register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GATEEN" description="Enable active clock gating" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTGATECLK" description="Counter for clock gating" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64 clocks" start="0x0" />
+        <Enum name="B_0x1" description="128 clocks" start="0x1" />
+      </BitField>
+      <BitField name="RAMGATEEN" description="Enable RAM clock gating" start="3" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1_S" description="USB on-the-go high-speed" start="0x58040000">
+    <Register name="OTG_GOTGCTL" description="OTG control and status register" start="+0x000" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="VBVALOEN" description="Vless thansub&gt;BUSless than/sub&gt; valid override enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Vless thansub&gt;BUSless than/sub&gt; valid override value." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vbusvalid value is '0' when VBVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="vbusvalid value is '1' when VBVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="AVALOEN" description="A-peripheral session valid override enable." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Avalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally Avalid received from the PHY is overridden with AVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="AVALOVAL" description="A-peripheral session valid override value." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Avalid value is '0' when AVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Avalid value is '1' when AVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="BVALOEN" description="B-peripheral session valid override enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+      </BitField>
+      <BitField name="BVALOVAL" description="B-peripheral session valid override value." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bvalid value is '0' when BVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Bvalid value is '1' when BVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="EHEN" description="Embedded host enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG A device state machine is selected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded host state machine is selected" start="0x1" />
+      </BitField>
+      <BitField name="CIDSTS" description="Connector ID status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The OTG controller is in A-device mode" start="0x0" />
+        <Enum name="B_0x1" description="The OTG controller is in B-device mode" start="0x1" />
+      </BitField>
+      <BitField name="DBCT" description="Long/short debounce time" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Long debounce time, used for physical connections (100 ms + 2.5 s)" start="0x0" />
+        <Enum name="B_0x1" description="Short debounce time, used for soft connections (2.5 s)" start="0x1" />
+      </BitField>
+      <BitField name="ASVLD" description="A-session valid" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A-session is not valid" start="0x0" />
+        <Enum name="B_0x1" description="A-session is valid" start="0x1" />
+      </BitField>
+      <BitField name="BSVLD" description="B-session valid" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="B-session is not valid." start="0x0" />
+        <Enum name="B_0x1" description="B-session is valid." start="0x1" />
+      </BitField>
+      <BitField name="OTGVER" description="OTG version" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG Version 1.3. OTG1.3 is obsolete for new product development." start="0x0" />
+        <Enum name="B_0x1" description="OTG Version 2.0. In this version the core supports only data line pulsing for SRP." start="0x1" />
+      </BitField>
+      <BitField name="CURMOD" description="Current mode of operation" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GOTGINT" description="OTG interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDET" description="Session end detected" start="2" size="1" access="Read/Write" />
+      <BitField name="ADTOCHG" description="A-device timeout change" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GAHBCFG" description="OTG AHB configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GINTMSK" description="Global interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Mask the interrupt assertion to the application." start="0x0" />
+        <Enum name="B_0x1" description="Unmask the interrupt assertion to the application." start="0x1" />
+      </BitField>
+      <BitField name="HBSTLEN" description="Burst length/type " start="1" size="4" access="Read/Write" />
+      <BitField name="DMAEN" description="DMA enabled" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core operates in slave mode" start="0x0" />
+        <Enum name="B_0x1" description="The core operates in DMA mode" start="0x1" />
+      </BitField>
+      <BitField name="TXFELVL" description="Tx FIFO empty level" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+      <BitField name="PTXFELVL" description="Periodic Tx FIFO empty level" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GUSBCFG" description="OTG USB configuration register" start="+0x00C" size="4" reset_value="0x00001400" reset_mask="0xFFFFFFFF">
+      <BitField name="TOCAL" description="FS timeout calibration" start="0" size="3" access="Read/Write" />
+      <BitField name="TRDT" description="USB turnaround time" start="10" size="4" access="Read/Write" />
+      <BitField name="PHYLPC" description="PHY Low-power clock select " start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="480 MHz internal PLL clock" start="0x0" />
+        <Enum name="B_0x1" description="48 MHz external clock" start="0x1" />
+      </BitField>
+      <BitField name="TSDPS" description="TermSel DLine pulsing selection " start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data line pulsing using utmi_txvalid (default)" start="0x0" />
+        <Enum name="B_0x1" description="Data line pulsing using utmi_termsel" start="0x1" />
+      </BitField>
+      <BitField name="FHMOD" description="Force host mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode" start="0x1" />
+      </BitField>
+      <BitField name="FDMOD" description="Force device mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force device mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRSTCTL" description="OTG reset register" start="+0x010" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSRST" description="Core soft reset" start="0" size="1" access="Read/Write" />
+      <BitField name="PSRST" description="Partial soft reset" start="1" size="1" access="Read/Write" />
+      <BitField name="FCRST" description="Host frame counter reset" start="2" size="1" access="Read/Write" />
+      <BitField name="RXFFLSH" description="Rx FIFO flush" start="4" size="1" access="Read/Write" />
+      <BitField name="TXFFLSH" description="Tx FIFO flush" start="5" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_HOST_MODE" description="Non-periodic Tx FIFO flush" start="0x0" />
+        <Enum name="B_0x1_HOST_MODE" description="Periodic Tx FIFO flush" start="0x1" />
+        <Enum name="B_0x10_HOST_MODE" description="Flush all the transmit FIFOs" start="0x10" />
+        <Enum name="B_0x2_DEVICE_MODE" description="Tx FIFO 2 flush" start="0x2" />
+        <Enum name="B_0xF_DEVICE_MODE" description="Tx FIFO 15 flush" start="0xF" />
+      </BitField>
+      <BitField name="DMAREQ" description="DMA request signal enabled" start="30" size="1" access="ReadOnly" />
+      <BitField name="AHBIDL" description="AHB master idle" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GINTSTS" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="IPXFR" description="Incomplete periodic transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTSTS_ALTERNATE" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="INCOMPISOOUT" description="Incomplete isochronous OUT transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTMSK" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NPTXFEM" description="Non-periodic Tx FIFO empty mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IPXFRM" description="Incomplete periodic transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PRTIM" description="Host port interrupt mask" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="HCIM" description="Host channels interrupt mask" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PTXFEM" description="Periodic Tx FIFO empty mask" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DISCINT" description="Disconnect detected interrupt mask" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GINTMSK_ALTERNATE" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GINAKEFFM" description="Global non-periodic IN NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GONAKEFFM" description="Global OUT NAK effective mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ESUSPM" description="Early suspend mask" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBSUSPM" description="USB suspend mask" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBRST" description="USB reset mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ENUMDNEM" description="Enumeration done mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ISOODRPM" description="Isochronous OUT packet dropped interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EOPFM" description="End of periodic frame interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IEPINT" description="IN endpoints interrupt mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPINT" description="OUT endpoints interrupt mask" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOIXFRM" description="Incomplete isochronous IN transfer mask" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOOXFRM" description="Incomplete isochronous OUT transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FSUSPM" description="Data fetch suspended mask" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RSTDETM" description="Reset detected interrupt mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSR" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSR_ALTERNATE" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSP" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSP_ALTERNATE" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXFSIZ" description="OTG receive FIFO size register" start="+0x024" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFD" description="Rx FIFO depth" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSA" description="Non-periodic transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="NPTXFD" description="Non-periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ_ALTERNATE" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TX0FSA" description="Endpoint 0 transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="TX0FD" description="Endpoint 0 Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXSTS" description="OTG non-periodic transmit FIFO/queue status register" start="+0x02C" size="4" reset_value="0x00080400" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSAV" description="Non-periodic Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="NPTQXSAV" description="Non-periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="NPTXQTOP" description="Top of the non-periodic transmit request queue" start="24" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GCCFG" description="OTG general core configuration register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="CHGDET" description="Charger detection, result of the current mode (primary or secondary)." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Low value on pin" start="0x0" />
+        <Enum name="B_0x1" description="High value on pin" start="0x1" />
+      </BitField>
+      <BitField name="FSVPLUS" description="Single-Ended DP indicator" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="FSVMINUS" description="Single-Ended DM indicator" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="SESSVLD" description="VBUS session indicator" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS session threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS session threshold" start="0x1" />
+      </BitField>
+      <BitField name="VBUSVLD" description="VBUS valid indicator" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS valid threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS valid threshold" start="0x1" />
+      </BitField>
+      <BitField name="HCDPEN" description="Host CDP behavior enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable CDP behavior" start="0x0" />
+        <Enum name="B_0x1" description="Enable CDP behavior" start="0x1" />
+      </BitField>
+      <BitField name="HCDPDETEN" description="Host CDP port voltage detector enable on DP" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DP voltage detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="DP voltage detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="HVDMSRCEN" description="Host CDP port Voltage source enable on DM" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DM voltage source disabled" start="0x0" />
+        <Enum name="B_0x1" description="DM Voltage source enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCDEN" description="Data Contact Detection enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data Contact Detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data Contact Detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="PDEN" description="Primary detection enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Primary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Primary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="Secondary detection enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secondary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Secondary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Software override value of the VBUS B-session detection" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="B-session inactive" start="0x0" />
+        <Enum name="B_0x1" description="B-session active" start="0x1" />
+      </BitField>
+      <BitField name="FORCEHOSTPD" description="Force host mode pull-downs" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force host mode pull-downs" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode pull-downs" start="0x1" />
+      </BitField>
+      <BitField name="BCDEN" description="Force Battery charging (BC) mode" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal USB mode" start="0x0" />
+        <Enum name="B_0x1" description="Battery Charging mode" start="0x1" />
+      </BitField>
+      <BitField name="IDPULLUPDIS" description="Disable ID pin pull-up" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enables ID pin pull-up" start="0x0" />
+        <Enum name="B_0x1" description="Disable ID pin pull-up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_CID" description="OTG core ID register" start="+0x03C" size="4" reset_value="0x00005000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRODUCT_ID" description="Product ID field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GLPMCFG" description="OTG core LPM configuration register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPMEN" description="LPM support enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPM capability is not enabled" start="0x0" />
+        <Enum name="B_0x1" description="LPM capability is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPMACK" description="LPM token acknowledge enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="ACK" start="0x1" />
+        <Enum name="B_0x0" description="NYET" start="0x0" />
+      </BitField>
+      <BitField name="BESL" description="Best effort service latency" start="2" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="125" start="0x0" />
+        <Enum name="B_0x1" description="150" start="0x1" />
+        <Enum name="B_0x2" description="200" start="0x2" />
+        <Enum name="B_0x3" description="300" start="0x3" />
+        <Enum name="B_0x4" description="400" start="0x4" />
+        <Enum name="B_0x5" description="500" start="0x5" />
+        <Enum name="B_0x6" description="1000" start="0x6" />
+        <Enum name="B_0x7" description="2000" start="0x7" />
+        <Enum name="B_0x8" description="3000" start="0x8" />
+        <Enum name="B_0x9" description="4000" start="0x9" />
+        <Enum name="B_0xA" description="5000" start="0xA" />
+        <Enum name="B_0xB" description="6000" start="0xB" />
+        <Enum name="B_0xC" description="7000" start="0xC" />
+        <Enum name="B_0xD" description="8000" start="0xD" />
+        <Enum name="B_0xE" description="9000" start="0xE" />
+        <Enum name="B_0xF" description="10000" start="0xF" />
+      </BitField>
+      <BitField name="REMWAKE" description="bRemoteWake value" start="6" size="1" access="Read/Write" />
+      <BitField name="L1SSEN" description="L1 Shallow Sleep enable" start="7" size="1" access="Read/Write" />
+      <BitField name="BESLTHRS" description="BESL threshold" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="75" start="0x0" />
+        <Enum name="B_0x1" description="100" start="0x1" />
+        <Enum name="B_0x2" description="150" start="0x2" />
+        <Enum name="B_0x3" description="250" start="0x3" />
+        <Enum name="B_0x4" description="350" start="0x4" />
+        <Enum name="B_0x5" description="450" start="0x5" />
+        <Enum name="B_0x6" description="950" start="0x6" />
+      </BitField>
+      <BitField name="L1DSEN" description="L1 deep sleep enable" start="12" size="1" access="Read/Write" />
+      <BitField name="LPMRSP" description="LPM response" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x3" description="ACK" start="0x3" />
+        <Enum name="B_0x2" description="NYET" start="0x2" />
+        <Enum name="B_0x1" description="STALL" start="0x1" />
+        <Enum name="B_0x0" description="ERROR (No handshake response)" start="0x0" />
+      </BitField>
+      <BitField name="SLPSTS" description="Port sleep status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Core not in L1" start="0x0" />
+        <Enum name="B_0x1" description="Core in L1" start="0x1" />
+      </BitField>
+      <BitField name="L1RSMOK" description="Sleep state resume OK" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="The application or host can start resume from Sleep state" start="0x1" />
+        <Enum name="B_0x0" description="The application or host cannot start resume from Sleep state" start="0x0" />
+      </BitField>
+      <BitField name="LPMCHIDX" description="LPM Channel Index" start="17" size="4" access="Read/Write" />
+      <BitField name="LPMRCNT" description="LPM retry count" start="21" size="3" access="Read/Write" />
+      <BitField name="SNDLPM" description="Send LPM transaction" start="24" size="1" access="Read/Write" />
+      <BitField name="LPMRCNTSTS" description="LPM retry count status" start="25" size="3" access="ReadOnly" />
+      <BitField name="ENBESL" description="Enable best effort service latency" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core works as described in the following document:" start="0x0" />
+        <Enum name="B_0x1" description="The core works as described in the LPM Errata:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPTXFSIZ" description="OTG host periodic transmit FIFO size register" start="+0x100" size="4" reset_value="0x04000800" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXSA" description="Host periodic Tx FIFO start address" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXFSIZ" description="Host periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF1" description="OTG device IN endpoint transmit FIFO 1 size register" start="+0x104" size="4" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF2" description="OTG device IN endpoint transmit FIFO 2 size register" start="+0x108" size="4" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF3" description="OTG device IN endpoint transmit FIFO 3 size register" start="+0x10C" size="4" reset_value="0x02000800" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF4" description="OTG device IN endpoint transmit FIFO 4 size register" start="+0x110" size="4" reset_value="0x02000A00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF5" description="OTG device IN endpoint transmit FIFO 5 size register" start="+0x114" size="4" reset_value="0x02000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF6" description="OTG device IN endpoint transmit FIFO 6 size register" start="+0x118" size="4" reset_value="0x02000E00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF7" description="OTG device IN endpoint transmit FIFO 7 size register" start="+0x11C" size="4" reset_value="0x02001000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF8" description="OTG device IN endpoint transmit FIFO 8 size register" start="+0x120" size="4" reset_value="0x02001200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCFG" description="OTG host configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x1_FS_HOST_MODE" description="PHY clock is running at 48 MHz" start="0x1" />
+        <Enum name="B_0x2_LS_HOST_MODE" description="Select 6 MHz PHY clock frequency" start="0x2" />
+      </BitField>
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HFIR" description="OTG host frame interval register" start="+0x404" size="4" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval " start="0" size="16" access="Read/Write" />
+      <BitField name="RLDCTRL" description="Reload control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The HFIR cannot be reloaded dynamically" start="0x0" />
+        <Enum name="B_0x1" description="The HFIR can be dynamically reloaded during run time." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HFNUM" description="OTG host frame number/frame time remaining register" start="+0x408" size="4" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" access="ReadOnly" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HPTXSTS" description="OTG_Host periodic transmit FIFO/queue status register" start="+0x410" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINT" description="OTG host all channels interrupt register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINTMSK" description="OTG host all channels interrupt mask register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPRT" description="OTG host port control and status register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No device is attached to the port" start="0x0" />
+        <Enum name="B_0x1" description="A device is attached to the port" start="0x1" />
+      </BitField>
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port disabled" start="0x0" />
+        <Enum name="B_0x1" description="Port enabled" start="0x1" />
+      </BitField>
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overcurrent condition" start="0x0" />
+        <Enum name="B_0x1" description="Overcurrent condition" start="0x1" />
+      </BitField>
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No resume driven" start="0x0" />
+        <Enum name="B_0x1" description="Resume driven" start="0x1" />
+      </BitField>
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in suspend mode" start="0x0" />
+        <Enum name="B_0x1" description="Port in suspend mode" start="0x1" />
+      </BitField>
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in reset" start="0x0" />
+        <Enum name="B_0x1" description="Port in reset" start="0x1" />
+      </BitField>
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Power off" start="0x0" />
+        <Enum name="B_0x1" description="Power on" start="0x1" />
+      </BitField>
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+        <Enum name="B_0x2" description="Low speed" start="0x2" />
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCCHAR0" description="OTG host channel 0 characteristics register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT0" description="OTG host channel 0 split control register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT0" description="OTG host channel 0 interrupt register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK0" description="OTG host channel 0 interrupt mask register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ0" description="OTG host channel 0 transfer size register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA0" description="OTG host channel 0 DMA address register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR1" description="OTG host channel 1 characteristics register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT1" description="OTG host channel 1 split control register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT1" description="OTG host channel 1 interrupt register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK1" description="OTG host channel 1 interrupt mask register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ1" description="OTG host channel 1 transfer size register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA1" description="OTG host channel 1 DMA address register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR2" description="OTG host channel 2 characteristics register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT2" description="OTG host channel 2 split control register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT2" description="OTG host channel 2 interrupt register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK2" description="OTG host channel 2 interrupt mask register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ2" description="OTG host channel 2 transfer size register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA2" description="OTG host channel 2 DMA address register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR3" description="OTG host channel 3 characteristics register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT3" description="OTG host channel 3 split control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT3" description="OTG host channel 3 interrupt register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK3" description="OTG host channel 3 interrupt mask register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ3" description="OTG host channel 3 transfer size register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA3" description="OTG host channel 3 DMA address register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR4" description="OTG host channel 4 characteristics register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT4" description="OTG host channel 4 split control register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT4" description="OTG host channel 4 interrupt register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK4" description="OTG host channel 4 interrupt mask register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ4" description="OTG host channel 4 transfer size register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA4" description="OTG host channel 4 DMA address register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR5" description="OTG host channel 5 characteristics register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT5" description="OTG host channel 5 split control register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT5" description="OTG host channel 5 interrupt register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK5" description="OTG host channel 5 interrupt mask register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ5" description="OTG host channel 5 transfer size register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA5" description="OTG host channel 5 DMA address register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR6" description="OTG host channel 6 characteristics register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT6" description="OTG host channel 6 split control register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT6" description="OTG host channel 6 interrupt register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK6" description="OTG host channel 6 interrupt mask register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ6" description="OTG host channel 6 transfer size register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA6" description="OTG host channel 6 DMA address register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR7" description="OTG host channel 7 characteristics register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT7" description="OTG host channel 7 split control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT7" description="OTG host channel 7 interrupt register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK7" description="OTG host channel 7 interrupt mask register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ7" description="OTG host channel 7 transfer size register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA7" description="OTG host channel 7 DMA address register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR8" description="OTG host channel 8 characteristics register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT8" description="OTG host channel 8 split control register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT8" description="OTG host channel 8 interrupt register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK8" description="OTG host channel 8 interrupt mask register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ8" description="OTG host channel 8 transfer size register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA8" description="OTG host channel 8 DMA address register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR9" description="OTG host channel 9 characteristics register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT9" description="OTG host channel 9 split control register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT9" description="OTG host channel 9 interrupt register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK9" description="OTG host channel 9 interrupt mask register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ9" description="OTG host channel 9 transfer size register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA9" description="OTG host channel 9 DMA address register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR10" description="OTG host channel 10 characteristics register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT10" description="OTG host channel 10 split control register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT10" description="OTG host channel 10 interrupt register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK10" description="OTG host channel 10 interrupt mask register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ10" description="OTG host channel 10 transfer size register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA10" description="OTG host channel 10 DMA address register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR11" description="OTG host channel 11 characteristics register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT11" description="OTG host channel 11 split control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT11" description="OTG host channel 11 interrupt register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK11" description="OTG host channel 11 interrupt mask register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ11" description="OTG host channel 11 transfer size register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA11" description="OTG host channel 11 DMA address register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR12" description="OTG host channel 12 characteristics register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT12" description="OTG host channel 12 split control register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT12" description="OTG host channel 12 interrupt register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK12" description="OTG host channel 12 interrupt mask register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ12" description="OTG host channel 12 transfer size register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA12" description="OTG host channel 12 DMA address register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR13" description="OTG host channel 13 characteristics register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT13" description="OTG host channel 13 split control register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT13" description="OTG host channel 13 interrupt register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK13" description="OTG host channel 13 interrupt mask register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ13" description="OTG host channel 13 transfer size register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA13" description="OTG host channel 13 DMA address register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR14" description="OTG host channel 14 characteristics register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT14" description="OTG host channel 14 split control register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT14" description="OTG host channel 14 interrupt register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK14" description="OTG host channel 14 interrupt mask register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ14" description="OTG host channel 14 transfer size register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA14" description="OTG host channel 14 DMA address register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR15" description="OTG host channel 15 characteristics register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT15" description="OTG host channel 15 split control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT15" description="OTG host channel 15 interrupt register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK15" description="OTG host channel 15 interrupt mask register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ15" description="OTG host channel 15 transfer size register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA15" description="OTG host channel 15 DMA address register" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DCFG" description="OTG device configuration register" start="+0x800" size="4" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+      </BitField>
+      <BitField name="NZLSOHSK" description="Non-zero-length status OUT handshake" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application." start="0x1" />
+        <Enum name="B_0x0" description="Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register." start="0x0" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="4" size="7" access="Read/Write" />
+      <BitField name="PFIVL" description="Periodic frame interval" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="80% of the frame interval" start="0x0" />
+        <Enum name="B_0x1" description="85% of the frame interval" start="0x1" />
+        <Enum name="B_0x2" description="90% of the frame interval" start="0x2" />
+        <Enum name="B_0x3" description="95% of the frame interval" start="0x3" />
+      </BitField>
+      <BitField name="ERRATIM" description="Erratic error interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Mask early suspend interrupt on erratic error" start="0x1" />
+        <Enum name="B_0x0" description="Early suspend interrupt is generated on erratic error" start="0x0" />
+      </BitField>
+      <BitField name="PERSCHIVL" description="Periodic schedule interval" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="25% of (micro)frame" start="0x0" />
+        <Enum name="B_0x1" description="50% of (micro)frame" start="0x1" />
+        <Enum name="B_0x2" description="75% of (micro)frame" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DCTL" description="OTG device control register" start="+0x804" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wake-up signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration." start="0x0" />
+        <Enum name="B_0x1" description="The core generates a device disconnect event to the USB host." start="0x1" />
+      </BitField>
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent out based on the data availability in the transmit FIFO." start="0x0" />
+        <Enum name="B_0x1" description="A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO." start="0x1" />
+      </BitField>
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent based on the FIFO status and the NAK and STALL bit settings." start="0x0" />
+        <Enum name="B_0x1" description="No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped." start="0x1" />
+      </BitField>
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+      <BitField name="DSBESLRJCT" description="Deep sleep BESL reject" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DSTS" description="OTG device status register" start="+0x808" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" access="ReadOnly" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="High Speed" start="0x0" />
+        <Enum name="B_0x1" description="Full Speed" start="0x1" />
+      </BitField>
+      <BitField name="EERR" description="Erratic error" start="3" size="1" access="ReadOnly" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" access="ReadOnly" />
+      <BitField name="DEVLNSTS" description="Device line status" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DIEPMSK" description="OTG device IN endpoint common interrupt mask register" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TOM" description="Timeout condition mask (Non-isochronous endpoints)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ITTXFEMSK" description="IN token received when Tx FIFO empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPMSK" description="OTG device OUT endpoint common interrupt mask register" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STUPM" description="STUPM: SETUP phase done mask. Applies to control endpoints only." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STSPHSRXM" description="Status phase received for control write mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="B2BSTUPM" description="Back-to-back SETUP packets received mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OUTPKTERRM" description="Out packet error mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BERRM" description="Babble error interrupt mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKMSK" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYETMSK" description="NYET interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DAINT" description="OTG device all endpoints interrupt register" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DAINTMSK" description="OTG all endpoints interrupt mask register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DTHRCTL" description="OTG device threshold control register" start="+0x0830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" access="Read/Write" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" access="Read/Write" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" access="Read/Write" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPEMPMSK" description="OTG device IN endpoint FIFO empty interrupt mask register" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL0" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL0_ALTERNATE" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT0" description="OTG device IN endpoint 0 interrupt register" start="+0x908" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ0" description="OTG device IN endpoint 0 transfer size register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPDMA0" description="OTG device IN endpoint 0 DMA address register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS0" description="OTG device IN endpoint transmit FIFO status register" start="+0x918" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL1" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL1_ALTERNATE" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT1" description="OTG device IN endpoint 1 interrupt register" start="+0x928" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ1" description="OTG device IN endpoint 1 transfer size register" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA1" description="OTG device IN endpoint 1 DMA address register" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS1" description="OTG device IN endpoint transmit FIFO status register" start="+0x938" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL2" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL2_ALTERNATE" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT2" description="OTG device IN endpoint 2 interrupt register" start="+0x948" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ2" description="OTG device IN endpoint 2 transfer size register" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA2" description="OTG device IN endpoint 2 DMA address register" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS2" description="OTG device IN endpoint transmit FIFO status register" start="+0x958" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL3" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL3_ALTERNATE" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT3" description="OTG device IN endpoint 3 interrupt register" start="+0x968" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ3" description="OTG device IN endpoint 3 transfer size register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA3" description="OTG device IN endpoint 3 DMA address register" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS3" description="OTG device IN endpoint transmit FIFO status register" start="+0x978" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL4" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL4_ALTERNATE" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT4" description="OTG device IN endpoint 4 interrupt register" start="+0x988" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ4" description="OTG device IN endpoint 4 transfer size register" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA4" description="OTG device IN endpoint 4 DMA address register" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS4" description="OTG device IN endpoint transmit FIFO status register" start="+0x998" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL5" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL5_ALTERNATE" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT5" description="OTG device IN endpoint 5 interrupt register" start="+0x9A8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ5" description="OTG device IN endpoint 5 transfer size register" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA5" description="OTG device IN endpoint 5 DMA address register" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS5" description="OTG device IN endpoint transmit FIFO status register" start="+0x9B8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL6" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL6_ALTERNATE" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT6" description="OTG device IN endpoint 6 interrupt register" start="+0x9C8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ6" description="OTG device IN endpoint 6 transfer size register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA6" description="OTG device IN endpoint 6 DMA address register" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS6" description="OTG device IN endpoint transmit FIFO status register" start="+0x9D8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL7" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL7_ALTERNATE" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT7" description="OTG device IN endpoint 7 interrupt register" start="+0x9E8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ7" description="OTG device IN endpoint 7 transfer size register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA7" description="OTG device IN endpoint 7 DMA address register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS7" description="OTG device IN endpoint transmit FIFO status register" start="+0x9F8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL8" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL8_ALTERNATE" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT8" description="OTG device IN endpoint 8 interrupt register" start="+0xA08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ8" description="OTG device IN endpoint 8 transfer size register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA8" description="OTG device IN endpoint 8 DMA address register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS8" description="OTG device IN endpoint transmit FIFO status register" start="+0xA18" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPCTL0" description="OTG device control OUT endpoint 0 control register" start="+0xB00" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="32 bytes" start="0x1" />
+        <Enum name="B_0x2" description="16 bytes" start="0x2" />
+        <Enum name="B_0x3" description="8 bytes" start="0x3" />
+      </BitField>
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_DOEPINT0" description="OTG device OUT endpoint 0 interrupt register" start="+0xB08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ0" description="OTG device OUT endpoint 0 transfer size register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" access="Read/Write" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA0" description="OTG device OUT endpoint 0 DMA address register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1_ALTERNATE" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT1" description="OTG device OUT endpoint 1 interrupt register" start="+0xB28" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ1" description="OTG device OUT endpoint 1 transfer size register" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA1" description="OTG device OUT endpoint 1 DMA address register" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2_ALTERNATE" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT2" description="OTG device OUT endpoint 2 interrupt register" start="+0xB48" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ2" description="OTG device OUT endpoint 2 transfer size register" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA2" description="OTG device OUT endpoint 2 DMA address register" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3_ALTERNATE" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT3" description="OTG device OUT endpoint 3 interrupt register" start="+0xB68" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ3" description="OTG device OUT endpoint 3 transfer size register" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA3" description="OTG device OUT endpoint 3 DMA address register" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4_ALTERNATE" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT4" description="OTG device OUT endpoint 4 interrupt register" start="+0xB88" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ4" description="OTG device OUT endpoint 4 transfer size register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA4" description="OTG device OUT endpoint 4 DMA address register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5_ALTERNATE" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT5" description="OTG device OUT endpoint 5 interrupt register" start="+0xBA8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ5" description="OTG device OUT endpoint 5 transfer size register" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA5" description="OTG device OUT endpoint 5 DMA address register" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6_ALTERNATE" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT6" description="OTG device OUT endpoint 6 interrupt register" start="+0xBC8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ6" description="OTG device OUT endpoint 6 transfer size register" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA6" description="OTG device OUT endpoint 6 DMA address register" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7_ALTERNATE" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT7" description="OTG device OUT endpoint 7 interrupt register" start="+0xBE8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ7" description="OTG device OUT endpoint 7 transfer size register" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA7" description="OTG device OUT endpoint 7 DMA address register" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8_ALTERNATE" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT8" description="OTG device OUT endpoint 8 interrupt register" start="+0xC08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ8" description="OTG device OUT endpoint 8 transfer size register" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA8" description="OTG device OUT endpoint 8 DMA address register" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_PCGCCTL" description="OTG power and clock gating control register" start="+0xE00" size="4" reset_value="0x200B8000" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" access="Read/Write" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" access="Read/Write" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" access="ReadOnly" />
+      <BitField name="ENL1GTG" description="Enable sleep clock gating" start="5" size="1" access="Read/Write" />
+      <BitField name="PHYSLEEP" description="PHY in Sleep" start="6" size="1" access="ReadOnly" />
+      <BitField name="SUSP" description="Deep Sleep" start="7" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_PCGCCTL1" description="OTG power and clock gating control register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GATEEN" description="Enable active clock gating" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTGATECLK" description="Counter for clock gating" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64 clocks" start="0x0" />
+        <Enum name="B_0x1" description="128 clocks" start="0x1" />
+      </BitField>
+      <BitField name="RAMGATEEN" description="Enable RAM clock gating" start="3" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG2" description="USB on-the-go high-speed" start="0x48080000">
+    <Register name="OTG_GOTGCTL" description="OTG control and status register" start="+0x000" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="VBVALOEN" description="Vless thansub&gt;BUSless than/sub&gt; valid override enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Vless thansub&gt;BUSless than/sub&gt; valid override value." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vbusvalid value is '0' when VBVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="vbusvalid value is '1' when VBVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="AVALOEN" description="A-peripheral session valid override enable." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Avalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally Avalid received from the PHY is overridden with AVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="AVALOVAL" description="A-peripheral session valid override value." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Avalid value is '0' when AVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Avalid value is '1' when AVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="BVALOEN" description="B-peripheral session valid override enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+      </BitField>
+      <BitField name="BVALOVAL" description="B-peripheral session valid override value." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bvalid value is '0' when BVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Bvalid value is '1' when BVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="EHEN" description="Embedded host enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG A device state machine is selected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded host state machine is selected" start="0x1" />
+      </BitField>
+      <BitField name="CIDSTS" description="Connector ID status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The OTG controller is in A-device mode" start="0x0" />
+        <Enum name="B_0x1" description="The OTG controller is in B-device mode" start="0x1" />
+      </BitField>
+      <BitField name="DBCT" description="Long/short debounce time" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Long debounce time, used for physical connections (100 ms + 2.5 s)" start="0x0" />
+        <Enum name="B_0x1" description="Short debounce time, used for soft connections (2.5 s)" start="0x1" />
+      </BitField>
+      <BitField name="ASVLD" description="A-session valid" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A-session is not valid" start="0x0" />
+        <Enum name="B_0x1" description="A-session is valid" start="0x1" />
+      </BitField>
+      <BitField name="BSVLD" description="B-session valid" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="B-session is not valid." start="0x0" />
+        <Enum name="B_0x1" description="B-session is valid." start="0x1" />
+      </BitField>
+      <BitField name="OTGVER" description="OTG version" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG Version 1.3. OTG1.3 is obsolete for new product development." start="0x0" />
+        <Enum name="B_0x1" description="OTG Version 2.0. In this version the core supports only data line pulsing for SRP." start="0x1" />
+      </BitField>
+      <BitField name="CURMOD" description="Current mode of operation" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GOTGINT" description="OTG interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDET" description="Session end detected" start="2" size="1" access="Read/Write" />
+      <BitField name="ADTOCHG" description="A-device timeout change" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GAHBCFG" description="OTG AHB configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GINTMSK" description="Global interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Mask the interrupt assertion to the application." start="0x0" />
+        <Enum name="B_0x1" description="Unmask the interrupt assertion to the application." start="0x1" />
+      </BitField>
+      <BitField name="HBSTLEN" description="Burst length/type " start="1" size="4" access="Read/Write" />
+      <BitField name="DMAEN" description="DMA enabled" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core operates in slave mode" start="0x0" />
+        <Enum name="B_0x1" description="The core operates in DMA mode" start="0x1" />
+      </BitField>
+      <BitField name="TXFELVL" description="Tx FIFO empty level" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+      <BitField name="PTXFELVL" description="Periodic Tx FIFO empty level" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GUSBCFG" description="OTG USB configuration register" start="+0x00C" size="4" reset_value="0x00001400" reset_mask="0xFFFFFFFF">
+      <BitField name="TOCAL" description="FS timeout calibration" start="0" size="3" access="Read/Write" />
+      <BitField name="TRDT" description="USB turnaround time" start="10" size="4" access="Read/Write" />
+      <BitField name="PHYLPC" description="PHY Low-power clock select " start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="480 MHz internal PLL clock" start="0x0" />
+        <Enum name="B_0x1" description="48 MHz external clock" start="0x1" />
+      </BitField>
+      <BitField name="TSDPS" description="TermSel DLine pulsing selection " start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data line pulsing using utmi_txvalid (default)" start="0x0" />
+        <Enum name="B_0x1" description="Data line pulsing using utmi_termsel" start="0x1" />
+      </BitField>
+      <BitField name="FHMOD" description="Force host mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode" start="0x1" />
+      </BitField>
+      <BitField name="FDMOD" description="Force device mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force device mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRSTCTL" description="OTG reset register" start="+0x010" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSRST" description="Core soft reset" start="0" size="1" access="Read/Write" />
+      <BitField name="PSRST" description="Partial soft reset" start="1" size="1" access="Read/Write" />
+      <BitField name="FCRST" description="Host frame counter reset" start="2" size="1" access="Read/Write" />
+      <BitField name="RXFFLSH" description="Rx FIFO flush" start="4" size="1" access="Read/Write" />
+      <BitField name="TXFFLSH" description="Tx FIFO flush" start="5" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_HOST_MODE" description="Non-periodic Tx FIFO flush" start="0x0" />
+        <Enum name="B_0x1_HOST_MODE" description="Periodic Tx FIFO flush" start="0x1" />
+        <Enum name="B_0x10_HOST_MODE" description="Flush all the transmit FIFOs" start="0x10" />
+        <Enum name="B_0x2_DEVICE_MODE" description="Tx FIFO 2 flush" start="0x2" />
+        <Enum name="B_0xF_DEVICE_MODE" description="Tx FIFO 15 flush" start="0xF" />
+      </BitField>
+      <BitField name="DMAREQ" description="DMA request signal enabled" start="30" size="1" access="ReadOnly" />
+      <BitField name="AHBIDL" description="AHB master idle" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GINTSTS" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="IPXFR" description="Incomplete periodic transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTSTS_ALTERNATE" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="INCOMPISOOUT" description="Incomplete isochronous OUT transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTMSK" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NPTXFEM" description="Non-periodic Tx FIFO empty mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IPXFRM" description="Incomplete periodic transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PRTIM" description="Host port interrupt mask" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="HCIM" description="Host channels interrupt mask" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PTXFEM" description="Periodic Tx FIFO empty mask" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DISCINT" description="Disconnect detected interrupt mask" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GINTMSK_ALTERNATE" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GINAKEFFM" description="Global non-periodic IN NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GONAKEFFM" description="Global OUT NAK effective mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ESUSPM" description="Early suspend mask" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBSUSPM" description="USB suspend mask" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBRST" description="USB reset mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ENUMDNEM" description="Enumeration done mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ISOODRPM" description="Isochronous OUT packet dropped interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EOPFM" description="End of periodic frame interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IEPINT" description="IN endpoints interrupt mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPINT" description="OUT endpoints interrupt mask" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOIXFRM" description="Incomplete isochronous IN transfer mask" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOOXFRM" description="Incomplete isochronous OUT transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FSUSPM" description="Data fetch suspended mask" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RSTDETM" description="Reset detected interrupt mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSR" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSR_ALTERNATE" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSP" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSP_ALTERNATE" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXFSIZ" description="OTG receive FIFO size register" start="+0x024" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFD" description="Rx FIFO depth" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSA" description="Non-periodic transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="NPTXFD" description="Non-periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ_ALTERNATE" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TX0FSA" description="Endpoint 0 transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="TX0FD" description="Endpoint 0 Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXSTS" description="OTG non-periodic transmit FIFO/queue status register" start="+0x02C" size="4" reset_value="0x00080400" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSAV" description="Non-periodic Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="NPTQXSAV" description="Non-periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="NPTXQTOP" description="Top of the non-periodic transmit request queue" start="24" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GCCFG" description="OTG general core configuration register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="CHGDET" description="Charger detection, result of the current mode (primary or secondary)." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Low value on pin" start="0x0" />
+        <Enum name="B_0x1" description="High value on pin" start="0x1" />
+      </BitField>
+      <BitField name="FSVPLUS" description="Single-Ended DP indicator" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="FSVMINUS" description="Single-Ended DM indicator" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="SESSVLD" description="VBUS session indicator" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS session threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS session threshold" start="0x1" />
+      </BitField>
+      <BitField name="VBUSVLD" description="VBUS valid indicator" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS valid threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS valid threshold" start="0x1" />
+      </BitField>
+      <BitField name="HCDPEN" description="Host CDP behavior enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable CDP behavior" start="0x0" />
+        <Enum name="B_0x1" description="Enable CDP behavior" start="0x1" />
+      </BitField>
+      <BitField name="HCDPDETEN" description="Host CDP port voltage detector enable on DP" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DP voltage detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="DP voltage detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="HVDMSRCEN" description="Host CDP port Voltage source enable on DM" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DM voltage source disabled" start="0x0" />
+        <Enum name="B_0x1" description="DM Voltage source enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCDEN" description="Data Contact Detection enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data Contact Detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data Contact Detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="PDEN" description="Primary detection enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Primary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Primary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="Secondary detection enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secondary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Secondary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Software override value of the VBUS B-session detection" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="B-session inactive" start="0x0" />
+        <Enum name="B_0x1" description="B-session active" start="0x1" />
+      </BitField>
+      <BitField name="FORCEHOSTPD" description="Force host mode pull-downs" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force host mode pull-downs" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode pull-downs" start="0x1" />
+      </BitField>
+      <BitField name="BCDEN" description="Force Battery charging (BC) mode" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal USB mode" start="0x0" />
+        <Enum name="B_0x1" description="Battery Charging mode" start="0x1" />
+      </BitField>
+      <BitField name="IDPULLUPDIS" description="Disable ID pin pull-up" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enables ID pin pull-up" start="0x0" />
+        <Enum name="B_0x1" description="Disable ID pin pull-up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_CID" description="OTG core ID register" start="+0x03C" size="4" reset_value="0x00005000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRODUCT_ID" description="Product ID field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GLPMCFG" description="OTG core LPM configuration register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPMEN" description="LPM support enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPM capability is not enabled" start="0x0" />
+        <Enum name="B_0x1" description="LPM capability is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPMACK" description="LPM token acknowledge enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="ACK" start="0x1" />
+        <Enum name="B_0x0" description="NYET" start="0x0" />
+      </BitField>
+      <BitField name="BESL" description="Best effort service latency" start="2" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="125" start="0x0" />
+        <Enum name="B_0x1" description="150" start="0x1" />
+        <Enum name="B_0x2" description="200" start="0x2" />
+        <Enum name="B_0x3" description="300" start="0x3" />
+        <Enum name="B_0x4" description="400" start="0x4" />
+        <Enum name="B_0x5" description="500" start="0x5" />
+        <Enum name="B_0x6" description="1000" start="0x6" />
+        <Enum name="B_0x7" description="2000" start="0x7" />
+        <Enum name="B_0x8" description="3000" start="0x8" />
+        <Enum name="B_0x9" description="4000" start="0x9" />
+        <Enum name="B_0xA" description="5000" start="0xA" />
+        <Enum name="B_0xB" description="6000" start="0xB" />
+        <Enum name="B_0xC" description="7000" start="0xC" />
+        <Enum name="B_0xD" description="8000" start="0xD" />
+        <Enum name="B_0xE" description="9000" start="0xE" />
+        <Enum name="B_0xF" description="10000" start="0xF" />
+      </BitField>
+      <BitField name="REMWAKE" description="bRemoteWake value" start="6" size="1" access="Read/Write" />
+      <BitField name="L1SSEN" description="L1 Shallow Sleep enable" start="7" size="1" access="Read/Write" />
+      <BitField name="BESLTHRS" description="BESL threshold" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="75" start="0x0" />
+        <Enum name="B_0x1" description="100" start="0x1" />
+        <Enum name="B_0x2" description="150" start="0x2" />
+        <Enum name="B_0x3" description="250" start="0x3" />
+        <Enum name="B_0x4" description="350" start="0x4" />
+        <Enum name="B_0x5" description="450" start="0x5" />
+        <Enum name="B_0x6" description="950" start="0x6" />
+      </BitField>
+      <BitField name="L1DSEN" description="L1 deep sleep enable" start="12" size="1" access="Read/Write" />
+      <BitField name="LPMRSP" description="LPM response" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x3" description="ACK" start="0x3" />
+        <Enum name="B_0x2" description="NYET" start="0x2" />
+        <Enum name="B_0x1" description="STALL" start="0x1" />
+        <Enum name="B_0x0" description="ERROR (No handshake response)" start="0x0" />
+      </BitField>
+      <BitField name="SLPSTS" description="Port sleep status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Core not in L1" start="0x0" />
+        <Enum name="B_0x1" description="Core in L1" start="0x1" />
+      </BitField>
+      <BitField name="L1RSMOK" description="Sleep state resume OK" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="The application or host can start resume from Sleep state" start="0x1" />
+        <Enum name="B_0x0" description="The application or host cannot start resume from Sleep state" start="0x0" />
+      </BitField>
+      <BitField name="LPMCHIDX" description="LPM Channel Index" start="17" size="4" access="Read/Write" />
+      <BitField name="LPMRCNT" description="LPM retry count" start="21" size="3" access="Read/Write" />
+      <BitField name="SNDLPM" description="Send LPM transaction" start="24" size="1" access="Read/Write" />
+      <BitField name="LPMRCNTSTS" description="LPM retry count status" start="25" size="3" access="ReadOnly" />
+      <BitField name="ENBESL" description="Enable best effort service latency" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core works as described in the following document:" start="0x0" />
+        <Enum name="B_0x1" description="The core works as described in the LPM Errata:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPTXFSIZ" description="OTG host periodic transmit FIFO size register" start="+0x100" size="4" reset_value="0x04000800" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXSA" description="Host periodic Tx FIFO start address" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXFSIZ" description="Host periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF1" description="OTG device IN endpoint transmit FIFO 1 size register" start="+0x104" size="4" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF2" description="OTG device IN endpoint transmit FIFO 2 size register" start="+0x108" size="4" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF3" description="OTG device IN endpoint transmit FIFO 3 size register" start="+0x10C" size="4" reset_value="0x02000800" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF4" description="OTG device IN endpoint transmit FIFO 4 size register" start="+0x110" size="4" reset_value="0x02000A00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF5" description="OTG device IN endpoint transmit FIFO 5 size register" start="+0x114" size="4" reset_value="0x02000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF6" description="OTG device IN endpoint transmit FIFO 6 size register" start="+0x118" size="4" reset_value="0x02000E00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF7" description="OTG device IN endpoint transmit FIFO 7 size register" start="+0x11C" size="4" reset_value="0x02001000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF8" description="OTG device IN endpoint transmit FIFO 8 size register" start="+0x120" size="4" reset_value="0x02001200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCFG" description="OTG host configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x1_FS_HOST_MODE" description="PHY clock is running at 48 MHz" start="0x1" />
+        <Enum name="B_0x2_LS_HOST_MODE" description="Select 6 MHz PHY clock frequency" start="0x2" />
+      </BitField>
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HFIR" description="OTG host frame interval register" start="+0x404" size="4" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval " start="0" size="16" access="Read/Write" />
+      <BitField name="RLDCTRL" description="Reload control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The HFIR cannot be reloaded dynamically" start="0x0" />
+        <Enum name="B_0x1" description="The HFIR can be dynamically reloaded during run time." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HFNUM" description="OTG host frame number/frame time remaining register" start="+0x408" size="4" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" access="ReadOnly" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HPTXSTS" description="OTG_Host periodic transmit FIFO/queue status register" start="+0x410" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINT" description="OTG host all channels interrupt register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINTMSK" description="OTG host all channels interrupt mask register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPRT" description="OTG host port control and status register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No device is attached to the port" start="0x0" />
+        <Enum name="B_0x1" description="A device is attached to the port" start="0x1" />
+      </BitField>
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port disabled" start="0x0" />
+        <Enum name="B_0x1" description="Port enabled" start="0x1" />
+      </BitField>
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overcurrent condition" start="0x0" />
+        <Enum name="B_0x1" description="Overcurrent condition" start="0x1" />
+      </BitField>
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No resume driven" start="0x0" />
+        <Enum name="B_0x1" description="Resume driven" start="0x1" />
+      </BitField>
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in suspend mode" start="0x0" />
+        <Enum name="B_0x1" description="Port in suspend mode" start="0x1" />
+      </BitField>
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in reset" start="0x0" />
+        <Enum name="B_0x1" description="Port in reset" start="0x1" />
+      </BitField>
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Power off" start="0x0" />
+        <Enum name="B_0x1" description="Power on" start="0x1" />
+      </BitField>
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+        <Enum name="B_0x2" description="Low speed" start="0x2" />
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCCHAR0" description="OTG host channel 0 characteristics register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT0" description="OTG host channel 0 split control register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT0" description="OTG host channel 0 interrupt register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK0" description="OTG host channel 0 interrupt mask register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ0" description="OTG host channel 0 transfer size register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA0" description="OTG host channel 0 DMA address register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR1" description="OTG host channel 1 characteristics register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT1" description="OTG host channel 1 split control register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT1" description="OTG host channel 1 interrupt register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK1" description="OTG host channel 1 interrupt mask register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ1" description="OTG host channel 1 transfer size register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA1" description="OTG host channel 1 DMA address register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR2" description="OTG host channel 2 characteristics register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT2" description="OTG host channel 2 split control register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT2" description="OTG host channel 2 interrupt register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK2" description="OTG host channel 2 interrupt mask register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ2" description="OTG host channel 2 transfer size register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA2" description="OTG host channel 2 DMA address register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR3" description="OTG host channel 3 characteristics register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT3" description="OTG host channel 3 split control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT3" description="OTG host channel 3 interrupt register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK3" description="OTG host channel 3 interrupt mask register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ3" description="OTG host channel 3 transfer size register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA3" description="OTG host channel 3 DMA address register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR4" description="OTG host channel 4 characteristics register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT4" description="OTG host channel 4 split control register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT4" description="OTG host channel 4 interrupt register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK4" description="OTG host channel 4 interrupt mask register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ4" description="OTG host channel 4 transfer size register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA4" description="OTG host channel 4 DMA address register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR5" description="OTG host channel 5 characteristics register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT5" description="OTG host channel 5 split control register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT5" description="OTG host channel 5 interrupt register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK5" description="OTG host channel 5 interrupt mask register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ5" description="OTG host channel 5 transfer size register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA5" description="OTG host channel 5 DMA address register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR6" description="OTG host channel 6 characteristics register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT6" description="OTG host channel 6 split control register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT6" description="OTG host channel 6 interrupt register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK6" description="OTG host channel 6 interrupt mask register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ6" description="OTG host channel 6 transfer size register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA6" description="OTG host channel 6 DMA address register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR7" description="OTG host channel 7 characteristics register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT7" description="OTG host channel 7 split control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT7" description="OTG host channel 7 interrupt register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK7" description="OTG host channel 7 interrupt mask register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ7" description="OTG host channel 7 transfer size register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA7" description="OTG host channel 7 DMA address register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR8" description="OTG host channel 8 characteristics register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT8" description="OTG host channel 8 split control register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT8" description="OTG host channel 8 interrupt register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK8" description="OTG host channel 8 interrupt mask register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ8" description="OTG host channel 8 transfer size register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA8" description="OTG host channel 8 DMA address register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR9" description="OTG host channel 9 characteristics register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT9" description="OTG host channel 9 split control register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT9" description="OTG host channel 9 interrupt register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK9" description="OTG host channel 9 interrupt mask register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ9" description="OTG host channel 9 transfer size register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA9" description="OTG host channel 9 DMA address register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR10" description="OTG host channel 10 characteristics register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT10" description="OTG host channel 10 split control register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT10" description="OTG host channel 10 interrupt register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK10" description="OTG host channel 10 interrupt mask register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ10" description="OTG host channel 10 transfer size register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA10" description="OTG host channel 10 DMA address register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR11" description="OTG host channel 11 characteristics register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT11" description="OTG host channel 11 split control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT11" description="OTG host channel 11 interrupt register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK11" description="OTG host channel 11 interrupt mask register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ11" description="OTG host channel 11 transfer size register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA11" description="OTG host channel 11 DMA address register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR12" description="OTG host channel 12 characteristics register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT12" description="OTG host channel 12 split control register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT12" description="OTG host channel 12 interrupt register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK12" description="OTG host channel 12 interrupt mask register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ12" description="OTG host channel 12 transfer size register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA12" description="OTG host channel 12 DMA address register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR13" description="OTG host channel 13 characteristics register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT13" description="OTG host channel 13 split control register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT13" description="OTG host channel 13 interrupt register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK13" description="OTG host channel 13 interrupt mask register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ13" description="OTG host channel 13 transfer size register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA13" description="OTG host channel 13 DMA address register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR14" description="OTG host channel 14 characteristics register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT14" description="OTG host channel 14 split control register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT14" description="OTG host channel 14 interrupt register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK14" description="OTG host channel 14 interrupt mask register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ14" description="OTG host channel 14 transfer size register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA14" description="OTG host channel 14 DMA address register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR15" description="OTG host channel 15 characteristics register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT15" description="OTG host channel 15 split control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT15" description="OTG host channel 15 interrupt register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK15" description="OTG host channel 15 interrupt mask register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ15" description="OTG host channel 15 transfer size register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA15" description="OTG host channel 15 DMA address register" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DCFG" description="OTG device configuration register" start="+0x800" size="4" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+      </BitField>
+      <BitField name="NZLSOHSK" description="Non-zero-length status OUT handshake" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application." start="0x1" />
+        <Enum name="B_0x0" description="Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register." start="0x0" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="4" size="7" access="Read/Write" />
+      <BitField name="PFIVL" description="Periodic frame interval" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="80% of the frame interval" start="0x0" />
+        <Enum name="B_0x1" description="85% of the frame interval" start="0x1" />
+        <Enum name="B_0x2" description="90% of the frame interval" start="0x2" />
+        <Enum name="B_0x3" description="95% of the frame interval" start="0x3" />
+      </BitField>
+      <BitField name="ERRATIM" description="Erratic error interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Mask early suspend interrupt on erratic error" start="0x1" />
+        <Enum name="B_0x0" description="Early suspend interrupt is generated on erratic error" start="0x0" />
+      </BitField>
+      <BitField name="PERSCHIVL" description="Periodic schedule interval" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="25% of (micro)frame" start="0x0" />
+        <Enum name="B_0x1" description="50% of (micro)frame" start="0x1" />
+        <Enum name="B_0x2" description="75% of (micro)frame" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DCTL" description="OTG device control register" start="+0x804" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wake-up signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration." start="0x0" />
+        <Enum name="B_0x1" description="The core generates a device disconnect event to the USB host." start="0x1" />
+      </BitField>
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent out based on the data availability in the transmit FIFO." start="0x0" />
+        <Enum name="B_0x1" description="A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO." start="0x1" />
+      </BitField>
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent based on the FIFO status and the NAK and STALL bit settings." start="0x0" />
+        <Enum name="B_0x1" description="No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped." start="0x1" />
+      </BitField>
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+      <BitField name="DSBESLRJCT" description="Deep sleep BESL reject" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DSTS" description="OTG device status register" start="+0x808" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" access="ReadOnly" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="High Speed" start="0x0" />
+        <Enum name="B_0x1" description="Full Speed" start="0x1" />
+      </BitField>
+      <BitField name="EERR" description="Erratic error" start="3" size="1" access="ReadOnly" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" access="ReadOnly" />
+      <BitField name="DEVLNSTS" description="Device line status" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DIEPMSK" description="OTG device IN endpoint common interrupt mask register" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TOM" description="Timeout condition mask (Non-isochronous endpoints)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ITTXFEMSK" description="IN token received when Tx FIFO empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPMSK" description="OTG device OUT endpoint common interrupt mask register" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STUPM" description="STUPM: SETUP phase done mask. Applies to control endpoints only." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STSPHSRXM" description="Status phase received for control write mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="B2BSTUPM" description="Back-to-back SETUP packets received mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OUTPKTERRM" description="Out packet error mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BERRM" description="Babble error interrupt mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKMSK" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYETMSK" description="NYET interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DAINT" description="OTG device all endpoints interrupt register" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DAINTMSK" description="OTG all endpoints interrupt mask register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DTHRCTL" description="OTG device threshold control register" start="+0x0830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" access="Read/Write" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" access="Read/Write" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" access="Read/Write" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPEMPMSK" description="OTG device IN endpoint FIFO empty interrupt mask register" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL0" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL0_ALTERNATE" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT0" description="OTG device IN endpoint 0 interrupt register" start="+0x908" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ0" description="OTG device IN endpoint 0 transfer size register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPDMA0" description="OTG device IN endpoint 0 DMA address register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS0" description="OTG device IN endpoint transmit FIFO status register" start="+0x918" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL1" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL1_ALTERNATE" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT1" description="OTG device IN endpoint 1 interrupt register" start="+0x928" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ1" description="OTG device IN endpoint 1 transfer size register" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA1" description="OTG device IN endpoint 1 DMA address register" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS1" description="OTG device IN endpoint transmit FIFO status register" start="+0x938" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL2" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL2_ALTERNATE" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT2" description="OTG device IN endpoint 2 interrupt register" start="+0x948" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ2" description="OTG device IN endpoint 2 transfer size register" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA2" description="OTG device IN endpoint 2 DMA address register" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS2" description="OTG device IN endpoint transmit FIFO status register" start="+0x958" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL3" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL3_ALTERNATE" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT3" description="OTG device IN endpoint 3 interrupt register" start="+0x968" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ3" description="OTG device IN endpoint 3 transfer size register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA3" description="OTG device IN endpoint 3 DMA address register" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS3" description="OTG device IN endpoint transmit FIFO status register" start="+0x978" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL4" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL4_ALTERNATE" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT4" description="OTG device IN endpoint 4 interrupt register" start="+0x988" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ4" description="OTG device IN endpoint 4 transfer size register" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA4" description="OTG device IN endpoint 4 DMA address register" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS4" description="OTG device IN endpoint transmit FIFO status register" start="+0x998" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL5" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL5_ALTERNATE" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT5" description="OTG device IN endpoint 5 interrupt register" start="+0x9A8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ5" description="OTG device IN endpoint 5 transfer size register" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA5" description="OTG device IN endpoint 5 DMA address register" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS5" description="OTG device IN endpoint transmit FIFO status register" start="+0x9B8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL6" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL6_ALTERNATE" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT6" description="OTG device IN endpoint 6 interrupt register" start="+0x9C8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ6" description="OTG device IN endpoint 6 transfer size register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA6" description="OTG device IN endpoint 6 DMA address register" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS6" description="OTG device IN endpoint transmit FIFO status register" start="+0x9D8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL7" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL7_ALTERNATE" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT7" description="OTG device IN endpoint 7 interrupt register" start="+0x9E8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ7" description="OTG device IN endpoint 7 transfer size register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA7" description="OTG device IN endpoint 7 DMA address register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS7" description="OTG device IN endpoint transmit FIFO status register" start="+0x9F8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL8" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL8_ALTERNATE" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT8" description="OTG device IN endpoint 8 interrupt register" start="+0xA08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ8" description="OTG device IN endpoint 8 transfer size register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA8" description="OTG device IN endpoint 8 DMA address register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS8" description="OTG device IN endpoint transmit FIFO status register" start="+0xA18" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPCTL0" description="OTG device control OUT endpoint 0 control register" start="+0xB00" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="32 bytes" start="0x1" />
+        <Enum name="B_0x2" description="16 bytes" start="0x2" />
+        <Enum name="B_0x3" description="8 bytes" start="0x3" />
+      </BitField>
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_DOEPINT0" description="OTG device OUT endpoint 0 interrupt register" start="+0xB08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ0" description="OTG device OUT endpoint 0 transfer size register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" access="Read/Write" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA0" description="OTG device OUT endpoint 0 DMA address register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1_ALTERNATE" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT1" description="OTG device OUT endpoint 1 interrupt register" start="+0xB28" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ1" description="OTG device OUT endpoint 1 transfer size register" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA1" description="OTG device OUT endpoint 1 DMA address register" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2_ALTERNATE" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT2" description="OTG device OUT endpoint 2 interrupt register" start="+0xB48" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ2" description="OTG device OUT endpoint 2 transfer size register" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA2" description="OTG device OUT endpoint 2 DMA address register" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3_ALTERNATE" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT3" description="OTG device OUT endpoint 3 interrupt register" start="+0xB68" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ3" description="OTG device OUT endpoint 3 transfer size register" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA3" description="OTG device OUT endpoint 3 DMA address register" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4_ALTERNATE" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT4" description="OTG device OUT endpoint 4 interrupt register" start="+0xB88" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ4" description="OTG device OUT endpoint 4 transfer size register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA4" description="OTG device OUT endpoint 4 DMA address register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5_ALTERNATE" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT5" description="OTG device OUT endpoint 5 interrupt register" start="+0xBA8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ5" description="OTG device OUT endpoint 5 transfer size register" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA5" description="OTG device OUT endpoint 5 DMA address register" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6_ALTERNATE" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT6" description="OTG device OUT endpoint 6 interrupt register" start="+0xBC8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ6" description="OTG device OUT endpoint 6 transfer size register" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA6" description="OTG device OUT endpoint 6 DMA address register" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7_ALTERNATE" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT7" description="OTG device OUT endpoint 7 interrupt register" start="+0xBE8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ7" description="OTG device OUT endpoint 7 transfer size register" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA7" description="OTG device OUT endpoint 7 DMA address register" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8_ALTERNATE" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT8" description="OTG device OUT endpoint 8 interrupt register" start="+0xC08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ8" description="OTG device OUT endpoint 8 transfer size register" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA8" description="OTG device OUT endpoint 8 DMA address register" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_PCGCCTL" description="OTG power and clock gating control register" start="+0xE00" size="4" reset_value="0x200B8000" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" access="Read/Write" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" access="Read/Write" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" access="ReadOnly" />
+      <BitField name="ENL1GTG" description="Enable sleep clock gating" start="5" size="1" access="Read/Write" />
+      <BitField name="PHYSLEEP" description="PHY in Sleep" start="6" size="1" access="ReadOnly" />
+      <BitField name="SUSP" description="Deep Sleep" start="7" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_PCGCCTL1" description="OTG power and clock gating control register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GATEEN" description="Enable active clock gating" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTGATECLK" description="Counter for clock gating" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64 clocks" start="0x0" />
+        <Enum name="B_0x1" description="128 clocks" start="0x1" />
+      </BitField>
+      <BitField name="RAMGATEEN" description="Enable RAM clock gating" start="3" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG2_S" description="USB on-the-go high-speed" start="0x58080000">
+    <Register name="OTG_GOTGCTL" description="OTG control and status register" start="+0x000" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="VBVALOEN" description="Vless thansub&gt;BUSless than/sub&gt; valid override enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Vless thansub&gt;BUSless than/sub&gt; valid override value." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="vbusvalid value is '0' when VBVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="vbusvalid value is '1' when VBVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="AVALOEN" description="A-peripheral session valid override enable." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Avalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+        <Enum name="B_0x1" description="Internally Avalid received from the PHY is overridden with AVALOVAL bit value" start="0x1" />
+      </BitField>
+      <BitField name="AVALOVAL" description="A-peripheral session valid override value." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Avalid value is '0' when AVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Avalid value is '1' when AVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="BVALOEN" description="B-peripheral session valid override enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core" start="0x0" />
+      </BitField>
+      <BitField name="BVALOVAL" description="B-peripheral session valid override value." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bvalid value is '0' when BVALOEN = 1" start="0x0" />
+        <Enum name="B_0x1" description="Bvalid value is '1' when BVALOEN = 1" start="0x1" />
+      </BitField>
+      <BitField name="EHEN" description="Embedded host enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG A device state machine is selected" start="0x0" />
+        <Enum name="B_0x1" description="Embedded host state machine is selected" start="0x1" />
+      </BitField>
+      <BitField name="CIDSTS" description="Connector ID status" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The OTG controller is in A-device mode" start="0x0" />
+        <Enum name="B_0x1" description="The OTG controller is in B-device mode" start="0x1" />
+      </BitField>
+      <BitField name="DBCT" description="Long/short debounce time" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Long debounce time, used for physical connections (100 ms + 2.5 s)" start="0x0" />
+        <Enum name="B_0x1" description="Short debounce time, used for soft connections (2.5 s)" start="0x1" />
+      </BitField>
+      <BitField name="ASVLD" description="A-session valid" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A-session is not valid" start="0x0" />
+        <Enum name="B_0x1" description="A-session is valid" start="0x1" />
+      </BitField>
+      <BitField name="BSVLD" description="B-session valid" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="B-session is not valid." start="0x0" />
+        <Enum name="B_0x1" description="B-session is valid." start="0x1" />
+      </BitField>
+      <BitField name="OTGVER" description="OTG version" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG Version 1.3. OTG1.3 is obsolete for new product development." start="0x0" />
+        <Enum name="B_0x1" description="OTG Version 2.0. In this version the core supports only data line pulsing for SRP." start="0x1" />
+      </BitField>
+      <BitField name="CURMOD" description="Current mode of operation" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GOTGINT" description="OTG interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDET" description="Session end detected" start="2" size="1" access="Read/Write" />
+      <BitField name="ADTOCHG" description="A-device timeout change" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GAHBCFG" description="OTG AHB configuration register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GINTMSK" description="Global interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Mask the interrupt assertion to the application." start="0x0" />
+        <Enum name="B_0x1" description="Unmask the interrupt assertion to the application." start="0x1" />
+      </BitField>
+      <BitField name="HBSTLEN" description="Burst length/type " start="1" size="4" access="Read/Write" />
+      <BitField name="DMAEN" description="DMA enabled" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core operates in slave mode" start="0x0" />
+        <Enum name="B_0x1" description="The core operates in DMA mode" start="0x1" />
+      </BitField>
+      <BitField name="TXFELVL" description="Tx FIFO empty level" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1_DEVICE_MODE" description="The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+      <BitField name="PTXFELVL" description="Periodic Tx FIFO empty level" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty" start="0x0" />
+        <Enum name="B_0x1" description="PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GUSBCFG" description="OTG USB configuration register" start="+0x00C" size="4" reset_value="0x00001400" reset_mask="0xFFFFFFFF">
+      <BitField name="TOCAL" description="FS timeout calibration" start="0" size="3" access="Read/Write" />
+      <BitField name="TRDT" description="USB turnaround time" start="10" size="4" access="Read/Write" />
+      <BitField name="PHYLPC" description="PHY Low-power clock select " start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="480 MHz internal PLL clock" start="0x0" />
+        <Enum name="B_0x1" description="48 MHz external clock" start="0x1" />
+      </BitField>
+      <BitField name="TSDPS" description="TermSel DLine pulsing selection " start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data line pulsing using utmi_txvalid (default)" start="0x0" />
+        <Enum name="B_0x1" description="Data line pulsing using utmi_termsel" start="0x1" />
+      </BitField>
+      <BitField name="FHMOD" description="Force host mode" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode" start="0x1" />
+      </BitField>
+      <BitField name="FDMOD" description="Force device mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Force device mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRSTCTL" description="OTG reset register" start="+0x010" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSRST" description="Core soft reset" start="0" size="1" access="Read/Write" />
+      <BitField name="PSRST" description="Partial soft reset" start="1" size="1" access="Read/Write" />
+      <BitField name="FCRST" description="Host frame counter reset" start="2" size="1" access="Read/Write" />
+      <BitField name="RXFFLSH" description="Rx FIFO flush" start="4" size="1" access="Read/Write" />
+      <BitField name="TXFFLSH" description="Tx FIFO flush" start="5" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x0_HOST_MODE" description="Non-periodic Tx FIFO flush" start="0x0" />
+        <Enum name="B_0x1_HOST_MODE" description="Periodic Tx FIFO flush" start="0x1" />
+        <Enum name="B_0x10_HOST_MODE" description="Flush all the transmit FIFOs" start="0x10" />
+        <Enum name="B_0x2_DEVICE_MODE" description="Tx FIFO 2 flush" start="0x2" />
+        <Enum name="B_0xF_DEVICE_MODE" description="Tx FIFO 15 flush" start="0xF" />
+      </BitField>
+      <BitField name="DMAREQ" description="DMA request signal enabled" start="30" size="1" access="ReadOnly" />
+      <BitField name="AHBIDL" description="AHB master idle" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GINTSTS" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="IPXFR" description="Incomplete periodic transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTSTS_ALTERNATE" description="OTG core interrupt register [alternate]" start="+0x014" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Device mode" start="0x0" />
+        <Enum name="B_0x1" description="Host mode" start="0x1" />
+      </BitField>
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="Rx FIFO non-empty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Non-periodic Tx FIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN non-periodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="GONAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="INCOMPISOOUT" description="Incomplete isochronous OUT transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended " start="22" size="1" access="Read/Write" />
+      <BitField name="RSTDET" description="Reset detected interrupt" start="23" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic Tx FIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="LPMINT" description="LPM interrupt" start="27" size="1" access="Read/Write" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUPINT" description="Resume/remote wake-up detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GINTMSK" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NPTXFEM" description="Non-periodic Tx FIFO empty mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IPXFRM" description="Incomplete periodic transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PRTIM" description="Host port interrupt mask" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="HCIM" description="Host channels interrupt mask" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="PTXFEM" description="Periodic Tx FIFO empty mask" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DISCINT" description="Disconnect detected interrupt mask" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GINTMSK_ALTERNATE" description="OTG interrupt mask register [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RXFLVLM" description="Receive FIFO non-empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GINAKEFFM" description="Global non-periodic IN NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="GONAKEFFM" description="Global OUT NAK effective mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ESUSPM" description="Early suspend mask" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBSUSPM" description="USB suspend mask" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="USBRST" description="USB reset mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ENUMDNEM" description="Enumeration done mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ISOODRPM" description="Isochronous OUT packet dropped interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EOPFM" description="End of periodic frame interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IEPINT" description="IN endpoints interrupt mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPINT" description="OUT endpoints interrupt mask" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOIXFRM" description="Incomplete isochronous IN transfer mask" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="IISOOXFRM" description="Incomplete isochronous OUT transfer mask" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FSUSPM" description="Data fetch suspended mask" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="RSTDETM" description="Reset detected interrupt mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="WUIM" description="Resume/remote wake-up detected interrupt mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSR" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSR_ALTERNATE" description="OTG receive status debug read register [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXSTSP" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x1" description="Global OUT NAK (triggers an interrupt)" start="0x1" />
+        <Enum name="B_0x2" description="OUT data packet received" start="0x2" />
+        <Enum name="B_0x3" description="OUT transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x4" description="SETUP transaction completed (triggers an interrupt)" start="0x4" />
+        <Enum name="B_0x6" description="SETUP data packet received" start="0x6" />
+      </BitField>
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" access="ReadOnly" />
+      <BitField name="STSPHST" description="Status phase start" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GRXSTSP_ALTERNATE" description="OTG status read and pop registers" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" access="ReadOnly" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" access="ReadOnly" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x3" description="MDATA" start="0x3" />
+      </BitField>
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" access="ReadOnly">
+        <Enum name="B_0x2" description="IN data packet received" start="0x2" />
+        <Enum name="B_0x3" description="IN transfer completed (triggers an interrupt)" start="0x3" />
+        <Enum name="B_0x5" description="Data toggle error (triggers an interrupt)" start="0x5" />
+        <Enum name="B_0x7" description="Channel halted (triggers an interrupt)" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="OTG_GRXFSIZ" description="OTG receive FIFO size register" start="+0x024" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFD" description="Rx FIFO depth" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSA" description="Non-periodic transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="NPTXFD" description="Non-periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXFSIZ_ALTERNATE" description="OTG host non-periodic transmit FIFO size register [alternate]" start="+0x028" size="4" reset_value="0x02000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TX0FSA" description="Endpoint 0 transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="TX0FD" description="Endpoint 0 Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HNPTXSTS" description="OTG non-periodic transmit FIFO/queue status register" start="+0x02C" size="4" reset_value="0x00080400" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSAV" description="Non-periodic Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="NPTQXSAV" description="Non-periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Non-periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="NPTXQTOP" description="Top of the non-periodic transmit request queue" start="24" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_GCCFG" description="OTG general core configuration register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
+      <BitField name="CHGDET" description="Charger detection, result of the current mode (primary or secondary)." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Low value on pin" start="0x0" />
+        <Enum name="B_0x1" description="High value on pin" start="0x1" />
+      </BitField>
+      <BitField name="FSVPLUS" description="Single-Ended DP indicator" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="FSVMINUS" description="Single-Ended DM indicator" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DM voltage at low level" start="0x0" />
+        <Enum name="B_0x1" description="DM voltage at high level" start="0x1" />
+      </BitField>
+      <BitField name="SESSVLD" description="VBUS session indicator" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS session threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS session threshold" start="0x1" />
+      </BitField>
+      <BitField name="VBUSVLD" description="VBUS valid indicator" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VBUS is below VBUS valid threshold" start="0x0" />
+        <Enum name="B_0x1" description="VBUS is above VBUS valid threshold" start="0x1" />
+      </BitField>
+      <BitField name="HCDPEN" description="Host CDP behavior enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable CDP behavior" start="0x0" />
+        <Enum name="B_0x1" description="Enable CDP behavior" start="0x1" />
+      </BitField>
+      <BitField name="HCDPDETEN" description="Host CDP port voltage detector enable on DP" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DP voltage detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="DP voltage detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="HVDMSRCEN" description="Host CDP port Voltage source enable on DM" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DM voltage source disabled" start="0x0" />
+        <Enum name="B_0x1" description="DM Voltage source enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCDEN" description="Data Contact Detection enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data Contact Detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data Contact Detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="PDEN" description="Primary detection enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Primary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Primary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDEN" description="Secondary detection enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secondary detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="Secondary detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBVALOVAL" description="Software override value of the VBUS B-session detection" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="B-session inactive" start="0x0" />
+        <Enum name="B_0x1" description="B-session active" start="0x1" />
+      </BitField>
+      <BitField name="FORCEHOSTPD" description="Force host mode pull-downs" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force host mode pull-downs" start="0x0" />
+        <Enum name="B_0x1" description="Force host mode pull-downs" start="0x1" />
+      </BitField>
+      <BitField name="BCDEN" description="Force Battery charging (BC) mode" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal USB mode" start="0x0" />
+        <Enum name="B_0x1" description="Battery Charging mode" start="0x1" />
+      </BitField>
+      <BitField name="IDPULLUPDIS" description="Disable ID pin pull-up" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enables ID pin pull-up" start="0x0" />
+        <Enum name="B_0x1" description="Disable ID pin pull-up" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_CID" description="OTG core ID register" start="+0x03C" size="4" reset_value="0x00005000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRODUCT_ID" description="Product ID field" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_GLPMCFG" description="OTG core LPM configuration register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPMEN" description="LPM support enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPM capability is not enabled" start="0x0" />
+        <Enum name="B_0x1" description="LPM capability is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPMACK" description="LPM token acknowledge enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="ACK" start="0x1" />
+        <Enum name="B_0x0" description="NYET" start="0x0" />
+      </BitField>
+      <BitField name="BESL" description="Best effort service latency" start="2" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="125" start="0x0" />
+        <Enum name="B_0x1" description="150" start="0x1" />
+        <Enum name="B_0x2" description="200" start="0x2" />
+        <Enum name="B_0x3" description="300" start="0x3" />
+        <Enum name="B_0x4" description="400" start="0x4" />
+        <Enum name="B_0x5" description="500" start="0x5" />
+        <Enum name="B_0x6" description="1000" start="0x6" />
+        <Enum name="B_0x7" description="2000" start="0x7" />
+        <Enum name="B_0x8" description="3000" start="0x8" />
+        <Enum name="B_0x9" description="4000" start="0x9" />
+        <Enum name="B_0xA" description="5000" start="0xA" />
+        <Enum name="B_0xB" description="6000" start="0xB" />
+        <Enum name="B_0xC" description="7000" start="0xC" />
+        <Enum name="B_0xD" description="8000" start="0xD" />
+        <Enum name="B_0xE" description="9000" start="0xE" />
+        <Enum name="B_0xF" description="10000" start="0xF" />
+      </BitField>
+      <BitField name="REMWAKE" description="bRemoteWake value" start="6" size="1" access="Read/Write" />
+      <BitField name="L1SSEN" description="L1 Shallow Sleep enable" start="7" size="1" access="Read/Write" />
+      <BitField name="BESLTHRS" description="BESL threshold" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="75" start="0x0" />
+        <Enum name="B_0x1" description="100" start="0x1" />
+        <Enum name="B_0x2" description="150" start="0x2" />
+        <Enum name="B_0x3" description="250" start="0x3" />
+        <Enum name="B_0x4" description="350" start="0x4" />
+        <Enum name="B_0x5" description="450" start="0x5" />
+        <Enum name="B_0x6" description="950" start="0x6" />
+      </BitField>
+      <BitField name="L1DSEN" description="L1 deep sleep enable" start="12" size="1" access="Read/Write" />
+      <BitField name="LPMRSP" description="LPM response" start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x3" description="ACK" start="0x3" />
+        <Enum name="B_0x2" description="NYET" start="0x2" />
+        <Enum name="B_0x1" description="STALL" start="0x1" />
+        <Enum name="B_0x0" description="ERROR (No handshake response)" start="0x0" />
+      </BitField>
+      <BitField name="SLPSTS" description="Port sleep status" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Core not in L1" start="0x0" />
+        <Enum name="B_0x1" description="Core in L1" start="0x1" />
+      </BitField>
+      <BitField name="L1RSMOK" description="Sleep state resume OK" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="The application or host can start resume from Sleep state" start="0x1" />
+        <Enum name="B_0x0" description="The application or host cannot start resume from Sleep state" start="0x0" />
+      </BitField>
+      <BitField name="LPMCHIDX" description="LPM Channel Index" start="17" size="4" access="Read/Write" />
+      <BitField name="LPMRCNT" description="LPM retry count" start="21" size="3" access="Read/Write" />
+      <BitField name="SNDLPM" description="Send LPM transaction" start="24" size="1" access="Read/Write" />
+      <BitField name="LPMRCNTSTS" description="LPM retry count status" start="25" size="3" access="ReadOnly" />
+      <BitField name="ENBESL" description="Enable best effort service latency" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The core works as described in the following document:" start="0x0" />
+        <Enum name="B_0x1" description="The core works as described in the LPM Errata:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPTXFSIZ" description="OTG host periodic transmit FIFO size register" start="+0x100" size="4" reset_value="0x04000800" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXSA" description="Host periodic Tx FIFO start address" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXFSIZ" description="Host periodic Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF1" description="OTG device IN endpoint transmit FIFO 1 size register" start="+0x104" size="4" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF2" description="OTG device IN endpoint transmit FIFO 2 size register" start="+0x108" size="4" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF3" description="OTG device IN endpoint transmit FIFO 3 size register" start="+0x10C" size="4" reset_value="0x02000800" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF4" description="OTG device IN endpoint transmit FIFO 4 size register" start="+0x110" size="4" reset_value="0x02000A00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF5" description="OTG device IN endpoint transmit FIFO 5 size register" start="+0x114" size="4" reset_value="0x02000C00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF6" description="OTG device IN endpoint transmit FIFO 6 size register" start="+0x118" size="4" reset_value="0x02000E00" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF7" description="OTG device IN endpoint transmit FIFO 7 size register" start="+0x11C" size="4" reset_value="0x02001000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTXF8" description="OTG device IN endpoint transmit FIFO 8 size register" start="+0x120" size="4" reset_value="0x02001200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" access="Read/Write" />
+      <BitField name="INEPTXFD" description="IN endpoint Tx FIFO depth" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCFG" description="OTG host configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x1_FS_HOST_MODE" description="PHY clock is running at 48 MHz" start="0x1" />
+        <Enum name="B_0x2_LS_HOST_MODE" description="Select 6 MHz PHY clock frequency" start="0x2" />
+      </BitField>
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HFIR" description="OTG host frame interval register" start="+0x404" size="4" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval " start="0" size="16" access="Read/Write" />
+      <BitField name="RLDCTRL" description="Reload control" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The HFIR cannot be reloaded dynamically" start="0x0" />
+        <Enum name="B_0x1" description="The HFIR can be dynamically reloaded during run time." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HFNUM" description="OTG host frame number/frame time remaining register" start="+0x408" size="4" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" access="ReadOnly" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HPTXSTS" description="OTG_Host periodic transmit FIFO/queue status register" start="+0x410" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly">
+        <Enum name="B_0x0" description="Periodic transmit request queue is full" start="0x0" />
+        <Enum name="B_0x1" description="1 location available" start="0x1" />
+      </BitField>
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINT" description="OTG host all channels interrupt register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HAINTMSK" description="OTG host all channels interrupt mask register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HPRT" description="OTG host port control and status register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No device is attached to the port" start="0x0" />
+        <Enum name="B_0x1" description="A device is attached to the port" start="0x1" />
+      </BitField>
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port disabled" start="0x0" />
+        <Enum name="B_0x1" description="Port enabled" start="0x1" />
+      </BitField>
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overcurrent condition" start="0x0" />
+        <Enum name="B_0x1" description="Overcurrent condition" start="0x1" />
+      </BitField>
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No resume driven" start="0x0" />
+        <Enum name="B_0x1" description="Resume driven" start="0x1" />
+      </BitField>
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in suspend mode" start="0x0" />
+        <Enum name="B_0x1" description="Port in suspend mode" start="0x1" />
+      </BitField>
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Port not in reset" start="0x0" />
+        <Enum name="B_0x1" description="Port in reset" start="0x1" />
+      </BitField>
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Power off" start="0x0" />
+        <Enum name="B_0x1" description="Power on" start="0x1" />
+      </BitField>
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly">
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+        <Enum name="B_0x2" description="Low speed" start="0x2" />
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCCHAR0" description="OTG host channel 0 characteristics register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT0" description="OTG host channel 0 split control register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT0" description="OTG host channel 0 interrupt register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK0" description="OTG host channel 0 interrupt mask register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ0" description="OTG host channel 0 transfer size register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA0" description="OTG host channel 0 DMA address register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR1" description="OTG host channel 1 characteristics register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT1" description="OTG host channel 1 split control register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT1" description="OTG host channel 1 interrupt register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK1" description="OTG host channel 1 interrupt mask register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ1" description="OTG host channel 1 transfer size register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA1" description="OTG host channel 1 DMA address register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR2" description="OTG host channel 2 characteristics register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT2" description="OTG host channel 2 split control register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT2" description="OTG host channel 2 interrupt register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK2" description="OTG host channel 2 interrupt mask register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ2" description="OTG host channel 2 transfer size register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA2" description="OTG host channel 2 DMA address register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR3" description="OTG host channel 3 characteristics register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT3" description="OTG host channel 3 split control register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT3" description="OTG host channel 3 interrupt register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK3" description="OTG host channel 3 interrupt mask register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ3" description="OTG host channel 3 transfer size register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA3" description="OTG host channel 3 DMA address register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR4" description="OTG host channel 4 characteristics register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT4" description="OTG host channel 4 split control register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT4" description="OTG host channel 4 interrupt register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK4" description="OTG host channel 4 interrupt mask register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ4" description="OTG host channel 4 transfer size register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA4" description="OTG host channel 4 DMA address register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR5" description="OTG host channel 5 characteristics register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT5" description="OTG host channel 5 split control register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT5" description="OTG host channel 5 interrupt register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK5" description="OTG host channel 5 interrupt mask register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ5" description="OTG host channel 5 transfer size register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA5" description="OTG host channel 5 DMA address register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR6" description="OTG host channel 6 characteristics register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT6" description="OTG host channel 6 split control register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT6" description="OTG host channel 6 interrupt register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK6" description="OTG host channel 6 interrupt mask register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ6" description="OTG host channel 6 transfer size register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA6" description="OTG host channel 6 DMA address register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR7" description="OTG host channel 7 characteristics register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT7" description="OTG host channel 7 split control register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT7" description="OTG host channel 7 interrupt register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK7" description="OTG host channel 7 interrupt mask register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ7" description="OTG host channel 7 transfer size register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA7" description="OTG host channel 7 DMA address register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR8" description="OTG host channel 8 characteristics register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT8" description="OTG host channel 8 split control register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT8" description="OTG host channel 8 interrupt register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK8" description="OTG host channel 8 interrupt mask register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ8" description="OTG host channel 8 transfer size register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA8" description="OTG host channel 8 DMA address register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR9" description="OTG host channel 9 characteristics register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT9" description="OTG host channel 9 split control register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT9" description="OTG host channel 9 interrupt register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK9" description="OTG host channel 9 interrupt mask register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ9" description="OTG host channel 9 transfer size register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA9" description="OTG host channel 9 DMA address register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR10" description="OTG host channel 10 characteristics register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT10" description="OTG host channel 10 split control register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT10" description="OTG host channel 10 interrupt register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK10" description="OTG host channel 10 interrupt mask register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ10" description="OTG host channel 10 transfer size register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA10" description="OTG host channel 10 DMA address register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR11" description="OTG host channel 11 characteristics register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT11" description="OTG host channel 11 split control register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT11" description="OTG host channel 11 interrupt register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK11" description="OTG host channel 11 interrupt mask register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ11" description="OTG host channel 11 transfer size register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA11" description="OTG host channel 11 DMA address register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR12" description="OTG host channel 12 characteristics register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT12" description="OTG host channel 12 split control register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT12" description="OTG host channel 12 interrupt register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK12" description="OTG host channel 12 interrupt mask register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ12" description="OTG host channel 12 transfer size register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA12" description="OTG host channel 12 DMA address register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR13" description="OTG host channel 13 characteristics register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT13" description="OTG host channel 13 split control register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT13" description="OTG host channel 13 interrupt register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK13" description="OTG host channel 13 interrupt mask register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ13" description="OTG host channel 13 transfer size register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA13" description="OTG host channel 13 DMA address register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR14" description="OTG host channel 14 characteristics register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT14" description="OTG host channel 14 split control register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT14" description="OTG host channel 14 interrupt register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK14" description="OTG host channel 14 interrupt mask register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ14" description="OTG host channel 14 transfer size register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA14" description="OTG host channel 14 DMA address register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCCHAR15" description="OTG host channel 15 characteristics register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" access="Read/Write" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OUT" start="0x0" />
+        <Enum name="B_0x1" description="IN" start="0x1" />
+      </BitField>
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" access="Read/Write" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="MCNT" description="Multicount" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 transaction" start="0x1" />
+        <Enum name="B_0x2" description="2 transactions per frame to be issued for this endpoint" start="0x2" />
+        <Enum name="B_0x3" description="3 transactions per frame to be issued for this endpoint" start="0x3" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="22" size="7" access="Read/Write" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" access="Read/Write" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCSPLT15" description="OTG host channel 15 split control register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" access="Read/Write" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" access="Read/Write" />
+      <BitField name="XACTPOS" description="Transaction position" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x3" description="All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes)" start="0x3" />
+        <Enum name="B_0x2" description="Begin. This is the first data payload of this transaction (which is larger than 188 bytes)" start="0x2" />
+        <Enum name="B_0x0" description="Mid. This is the middle payload of this transaction (which is larger than 188 bytes)" start="0x0" />
+        <Enum name="B_0x1" description="End. This is the last payload of this transaction (which is larger than 188 bytes)" start="0x1" />
+      </BitField>
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" access="Read/Write" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINT15" description="OTG host channel 15 interrupt register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed." start="0" size="1" access="Read/Write" />
+      <BitField name="CHH" description="Channel halted. " start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL response received interrupt." start="3" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK response received interrupt." start="4" size="1" access="Read/Write" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt." start="5" size="1" access="Read/Write" />
+      <BitField name="NYET" description="Not yet ready response received interrupt." start="6" size="1" access="Read/Write" />
+      <BitField name="TXERR" description="Transaction error." start="7" size="1" access="Read/Write" />
+      <BitField name="BBERR" description="Babble error." start="8" size="1" access="Read/Write" />
+      <BitField name="FRMOR" description="Frame overrun." start="9" size="1" access="Read/Write" />
+      <BitField name="DTERR" description="Data toggle error." start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCINTMSK15" description="OTG host channel 15 interrupt mask register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STALLM" description="STALL response received interrupt mask." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK response received interrupt mask." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYET" description="response received interrupt mask." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXERRM" description="Transaction error mask." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BBERRM" description="Babble error mask." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="FRMORM" description="Frame overrun mask." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="DTERRM" description="Data toggle error mask." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_HCTSIZ15" description="OTG host channel 15 transfer size register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA2" start="0x1" />
+        <Enum name="B_0x2" description="DATA1" start="0x2" />
+        <Enum name="B_0x3" description="SETUP (control) / MDATA (non-control)" start="0x3" />
+      </BitField>
+      <BitField name="DOPNG" description="Do Ping" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HCDMA15" description="OTG host channel 15 DMA address register" start="+0x6F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DCFG" description="OTG device configuration register" start="+0x800" size="4" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="High speed" start="0x0" />
+        <Enum name="B_0x1" description="Full speed" start="0x1" />
+      </BitField>
+      <BitField name="NZLSOHSK" description="Non-zero-length status OUT handshake" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application." start="0x1" />
+        <Enum name="B_0x0" description="Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register." start="0x0" />
+      </BitField>
+      <BitField name="DAD" description="Device address" start="4" size="7" access="Read/Write" />
+      <BitField name="PFIVL" description="Periodic frame interval" start="11" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="80% of the frame interval" start="0x0" />
+        <Enum name="B_0x1" description="85% of the frame interval" start="0x1" />
+        <Enum name="B_0x2" description="90% of the frame interval" start="0x2" />
+        <Enum name="B_0x3" description="95% of the frame interval" start="0x3" />
+      </BitField>
+      <BitField name="ERRATIM" description="Erratic error interrupt mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Mask early suspend interrupt on erratic error" start="0x1" />
+        <Enum name="B_0x0" description="Early suspend interrupt is generated on erratic error" start="0x0" />
+      </BitField>
+      <BitField name="PERSCHIVL" description="Periodic schedule interval" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="25% of (micro)frame" start="0x0" />
+        <Enum name="B_0x1" description="50% of (micro)frame" start="0x1" />
+        <Enum name="B_0x2" description="75% of (micro)frame" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DCTL" description="OTG device control register" start="+0x804" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wake-up signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration." start="0x0" />
+        <Enum name="B_0x1" description="The core generates a device disconnect event to the USB host." start="0x1" />
+      </BitField>
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent out based on the data availability in the transmit FIFO." start="0x0" />
+        <Enum name="B_0x1" description="A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO." start="0x1" />
+      </BitField>
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="A handshake is sent based on the FIFO status and the NAK and STALL bit settings." start="0x0" />
+        <Enum name="B_0x1" description="No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped." start="0x1" />
+      </BitField>
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Test mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Test_J mode" start="0x1" />
+        <Enum name="B_0x2" description="Test_K mode" start="0x2" />
+        <Enum name="B_0x3" description="Test_SE0_NAK mode" start="0x3" />
+        <Enum name="B_0x4" description="Test_Packet mode" start="0x4" />
+        <Enum name="B_0x5" description="Test_Force_Enable" start="0x5" />
+      </BitField>
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+      <BitField name="DSBESLRJCT" description="Deep sleep BESL reject" start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DSTS" description="OTG device status register" start="+0x808" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" access="ReadOnly" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="High Speed" start="0x0" />
+        <Enum name="B_0x1" description="Full Speed" start="0x1" />
+      </BitField>
+      <BitField name="EERR" description="Erratic error" start="3" size="1" access="ReadOnly" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" access="ReadOnly" />
+      <BitField name="DEVLNSTS" description="Device line status" start="22" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DIEPMSK" description="OTG device IN endpoint common interrupt mask register" start="+0x810" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TOM" description="Timeout condition mask (Non-isochronous endpoints)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="ITTXFEMSK" description="IN token received when Tx FIFO empty mask" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKM" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPMSK" description="OTG device OUT endpoint common interrupt mask register" start="+0x814" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="AHBERRM" description="AHB error mask" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STUPM" description="STUPM: SETUP phase done mask. Applies to control endpoints only." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="STSPHSRXM" description="Status phase received for control write mask" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="B2BSTUPM" description="Back-to-back SETUP packets received mask" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OUTPKTERRM" description="Out packet error mask" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="BERRM" description="Babble error interrupt mask" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NAKMSK" description="NAK interrupt mask" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="NYETMSK" description="NYET interrupt mask" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DAINT" description="OTG device all endpoints interrupt register" start="+0x818" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_DAINTMSK" description="OTG all endpoints interrupt mask register" start="+0x81C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DTHRCTL" description="OTG device threshold control register" start="+0x0830" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" access="Read/Write" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" access="Read/Write" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" access="Read/Write" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" access="Read/Write" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" access="Read/Write" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPEMPMSK" description="OTG device IN endpoint FIFO empty interrupt mask register" start="+0x834" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Masked interrupt" start="0x0" />
+        <Enum name="B_0x1" description="Unmasked interrupt" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL0" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL0_ALTERNATE" description="OTG device IN endpoint 0 control register [alternate]" start="+0x900" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT0" description="OTG device IN endpoint 0 interrupt register" start="+0x908" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ0" description="OTG device IN endpoint 0 transfer size register" start="+0x910" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPDMA0" description="OTG device IN endpoint 0 DMA address register" start="+0x914" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS0" description="OTG device IN endpoint transmit FIFO status register" start="+0x918" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL1" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL1_ALTERNATE" description="OTG device IN endpoint 1 control register [alternate]" start="+0x920" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT1" description="OTG device IN endpoint 1 interrupt register" start="+0x928" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ1" description="OTG device IN endpoint 1 transfer size register" start="+0x930" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA1" description="OTG device IN endpoint 1 DMA address register" start="+0x934" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS1" description="OTG device IN endpoint transmit FIFO status register" start="+0x938" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL2" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL2_ALTERNATE" description="OTG device IN endpoint 2 control register [alternate]" start="+0x940" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT2" description="OTG device IN endpoint 2 interrupt register" start="+0x948" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ2" description="OTG device IN endpoint 2 transfer size register" start="+0x950" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA2" description="OTG device IN endpoint 2 DMA address register" start="+0x954" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS2" description="OTG device IN endpoint transmit FIFO status register" start="+0x958" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL3" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL3_ALTERNATE" description="OTG device IN endpoint 3 control register [alternate]" start="+0x960" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT3" description="OTG device IN endpoint 3 interrupt register" start="+0x968" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ3" description="OTG device IN endpoint 3 transfer size register" start="+0x970" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA3" description="OTG device IN endpoint 3 DMA address register" start="+0x974" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS3" description="OTG device IN endpoint transmit FIFO status register" start="+0x978" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL4" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL4_ALTERNATE" description="OTG device IN endpoint 4 control register [alternate]" start="+0x980" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT4" description="OTG device IN endpoint 4 interrupt register" start="+0x988" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ4" description="OTG device IN endpoint 4 transfer size register" start="+0x990" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA4" description="OTG device IN endpoint 4 DMA address register" start="+0x994" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS4" description="OTG device IN endpoint transmit FIFO status register" start="+0x998" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL5" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL5_ALTERNATE" description="OTG device IN endpoint 5 control register [alternate]" start="+0x9A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT5" description="OTG device IN endpoint 5 interrupt register" start="+0x9A8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ5" description="OTG device IN endpoint 5 transfer size register" start="+0x9B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA5" description="OTG device IN endpoint 5 DMA address register" start="+0x9B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS5" description="OTG device IN endpoint transmit FIFO status register" start="+0x9B8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL6" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL6_ALTERNATE" description="OTG device IN endpoint 6 control register [alternate]" start="+0x9C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT6" description="OTG device IN endpoint 6 interrupt register" start="+0x9C8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ6" description="OTG device IN endpoint 6 transfer size register" start="+0x9D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA6" description="OTG device IN endpoint 6 DMA address register" start="+0x9D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS6" description="OTG device IN endpoint transmit FIFO status register" start="+0x9D8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL7" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL7_ALTERNATE" description="OTG device IN endpoint 7 control register [alternate]" start="+0x9E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT7" description="OTG device IN endpoint 7 interrupt register" start="+0x9E8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ7" description="OTG device IN endpoint 7 transfer size register" start="+0x9F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA7" description="OTG device IN endpoint 7 DMA address register" start="+0x9F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS7" description="OTG device IN endpoint transmit FIFO status register" start="+0x9F8" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPCTL8" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPCTL8_ALTERNATE" description="OTG device IN endpoint 8 control register [alternate]" start="+0xA00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="Tx FIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPINT8" description="OTG device IN endpoint 8 interrupt register" start="+0xA08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when Tx FIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNM" description="IN token received with EP mismatch" start="5" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun (TxfifoUndrn)" start="8" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DIEPTSIZ8" description="OTG device IN endpoint 8 transfer size register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DIEPDMA8" description="OTG device IN endpoint 8 DMA address register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DTXFSTS8" description="OTG device IN endpoint transmit FIFO status register" start="+0xA18" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint Tx FIFO space available" start="0" size="16" access="ReadOnly">
+        <Enum name="B_0x0" description="Endpoint Tx FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="1 word available" start="0x1" />
+        <Enum name="B_0x2" description="2 words available" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPCTL0" description="OTG device control OUT endpoint 0 control register" start="+0xB00" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="64 bytes" start="0x0" />
+        <Enum name="B_0x1" description="32 bytes" start="0x1" />
+        <Enum name="B_0x2" description="16 bytes" start="0x2" />
+        <Enum name="B_0x3" description="8 bytes" start="0x3" />
+      </BitField>
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_DOEPINT0" description="OTG device OUT endpoint 0 interrupt register" start="+0xB08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ0" description="OTG device OUT endpoint 0 transfer size register" start="+0xB10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" access="Read/Write" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="1 packet" start="0x1" />
+        <Enum name="B_0x2" description="2 packets" start="0x2" />
+        <Enum name="B_0x3" description="3 packets" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA0" description="OTG device OUT endpoint 0 DMA address register" start="+0xB14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL1_ALTERNATE" description="OTG device OUT endpoint 1 control register [alternate]" start="+0xB20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT1" description="OTG device OUT endpoint 1 interrupt register" start="+0xB28" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ1" description="OTG device OUT endpoint 1 transfer size register" start="+0xB30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA1" description="OTG device OUT endpoint 1 DMA address register" start="+0xB34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL2_ALTERNATE" description="OTG device OUT endpoint 2 control register [alternate]" start="+0xB40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT2" description="OTG device OUT endpoint 2 interrupt register" start="+0xB48" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ2" description="OTG device OUT endpoint 2 transfer size register" start="+0xB50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA2" description="OTG device OUT endpoint 2 DMA address register" start="+0xB54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL3_ALTERNATE" description="OTG device OUT endpoint 3 control register [alternate]" start="+0xB60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT3" description="OTG device OUT endpoint 3 interrupt register" start="+0xB68" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ3" description="OTG device OUT endpoint 3 transfer size register" start="+0xB70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA3" description="OTG device OUT endpoint 3 DMA address register" start="+0xB74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL4_ALTERNATE" description="OTG device OUT endpoint 4 control register [alternate]" start="+0xB80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT4" description="OTG device OUT endpoint 4 interrupt register" start="+0xB88" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ4" description="OTG device OUT endpoint 4 transfer size register" start="+0xB90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA4" description="OTG device OUT endpoint 4 DMA address register" start="+0xB94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL5_ALTERNATE" description="OTG device OUT endpoint 5 control register [alternate]" start="+0xBA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT5" description="OTG device OUT endpoint 5 interrupt register" start="+0xBA8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ5" description="OTG device OUT endpoint 5 transfer size register" start="+0xBB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA5" description="OTG device OUT endpoint 5 DMA address register" start="+0xBB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL6_ALTERNATE" description="OTG device OUT endpoint 6 control register [alternate]" start="+0xBC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT6" description="OTG device OUT endpoint 6 interrupt register" start="+0xBC8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ6" description="OTG device OUT endpoint 6 transfer size register" start="+0xBD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA6" description="OTG device OUT endpoint 6 DMA address register" start="+0xBD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL7_ALTERNATE" description="OTG device OUT endpoint 7 control register [alternate]" start="+0xBE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT7" description="OTG device OUT endpoint 7 interrupt register" start="+0xBE8" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ7" description="OTG device OUT endpoint 7 transfer size register" start="+0xBF0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA7" description="OTG device OUT endpoint 7 DMA address register" start="+0xBF4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="DPID" description="Endpoint data PID" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="DATA0" start="0x0" />
+        <Enum name="B_0x1" description="DATA1" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SD1PID" description="Set DATA1 PID" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPCTL8_ALTERNATE" description="OTG device OUT endpoint 8 control register [alternate]" start="+0xC00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM" description="Even/odd frame" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Even frame" start="0x0" />
+        <Enum name="B_0x1" description="Odd frame" start="0x1" />
+      </BitField>
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The core is transmitting non-NAK handshakes based on the FIFO status." start="0x0" />
+        <Enum name="B_0x1" description="The core is transmitting NAK handshakes on this endpoint." start="0x1" />
+      </BitField>
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Control" start="0x0" />
+        <Enum name="B_0x1" description="Isochronous" start="0x1" />
+        <Enum name="B_0x2" description="Bulk" start="0x2" />
+        <Enum name="B_0x3" description="Interrupt" start="0x3" />
+      </BitField>
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="STALL" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SEVNFRM" description="Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPINT8" description="OTG device OUT endpoint 8 interrupt register" start="+0xC08" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" access="Read/Write" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" access="Read/Write" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" access="Read/Write" />
+      <BitField name="STSPHSRX" description="Status phase received for control write" start="5" size="1" access="Read/Write" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" access="Read/Write" />
+      <BitField name="OUTPKTERR" description="OUT packet error" start="8" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK input" start="13" size="1" access="Read/Write" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="STPKTRX" description="Setup packet received" start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_DOEPTSIZ8" description="OTG device OUT endpoint 8 transfer size register" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" access="Read/Write" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" access="Read/Write" />
+      <BitField name="RXDPID" description="Received data PID" start="29" size="2" access="Read/Write">
+        <Enum name="B_0x0_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA0" start="0x0" />
+        <Enum name="B_0x1_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA2" start="0x1" />
+        <Enum name="B_0x2_ISOCHRONOUS_OUT_ENDPOINTS" description="DATA1" start="0x2" />
+        <Enum name="B_0x3_ISOCHRONOUS_OUT_ENDPOINTS" description="MDATA" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="OTG_DOEPDMA8" description="OTG device OUT endpoint 8 DMA address register" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="OTG_PCGCCTL" description="OTG power and clock gating control register" start="+0xE00" size="4" reset_value="0x200B8000" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" access="Read/Write" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" access="Read/Write" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" access="ReadOnly" />
+      <BitField name="ENL1GTG" description="Enable sleep clock gating" start="5" size="1" access="Read/Write" />
+      <BitField name="PHYSLEEP" description="PHY in Sleep" start="6" size="1" access="ReadOnly" />
+      <BitField name="SUSP" description="Deep Sleep" start="7" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_PCGCCTL1" description="OTG power and clock gating control register 1" start="+0xE04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GATEEN" description="Enable active clock gating" start="0" size="1" access="Read/Write" />
+      <BitField name="CNTGATECLK" description="Counter for clock gating" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="64 clocks" start="0x0" />
+        <Enum name="B_0x1" description="128 clocks" start="0x1" />
+      </BitField>
+      <BitField name="RAMGATEEN" description="Enable RAM clock gating" start="3" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PKA" description="Public key accelerator" start="0x44022000">
+    <Register name="PKA_CR" description="PKA control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="PKA enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable PKA" start="0x0" />
+        <Enum name="B_0x1" description="Enable PKA.PKA becomes functional when INITOK is set by hardware in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="START" description="start the operation" start="1" size="1" access="Read/Write" />
+      <BitField name="MODE" description="PKA operation code" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Montgomery parameter computation then modular exponentiation" start="0x0" />
+        <Enum name="B_0x1" description="Montgomery parameter computation only" start="0x1" />
+        <Enum name="B_0x2" description="Modular exponentiation only (Montgomery parameter must be loaded first)" start="0x2" />
+        <Enum name="B_0x3" description="Modular exponentiation (protected, used when manipulating secrets)" start="0x3" />
+        <Enum name="B_0x20" description="Montgomery parameter computation then ECC scalar multiplication" start="0x20" />
+        <Enum name="B_0x24" description="ECDSA sign" start="0x24" />
+        <Enum name="B_0x26" description="ECDSA verification" start="0x26" />
+        <Enum name="B_0x28" description="Point on elliptic curve Fp check" start="0x28" />
+        <Enum name="B_0x7" description="RSA CRT exponentiation" start="0x7" />
+        <Enum name="B_0x8" description="Modular inversion" start="0x8" />
+        <Enum name="B_0x9" description="Arithmetic addition" start="0x9" />
+        <Enum name="B_0xA" description="Arithmetic subtraction" start="0xA" />
+        <Enum name="B_0xB" description="Arithmetic multiplication" start="0xB" />
+        <Enum name="B_0xC" description="Arithmetic comparison" start="0xC" />
+        <Enum name="B_0xD" description="Modular reduction" start="0xD" />
+        <Enum name="B_0xE" description="Modular addition" start="0xE" />
+        <Enum name="B_0xF" description="Modular subtraction" start="0xF" />
+        <Enum name="B_0x10" description="Montgomery multiplication" start="0x10" />
+        <Enum name="B_0x23" description="ECC complete addition" start="0x23" />
+        <Enum name="B_0x27" description="ECC double base ladder" start="0x27" />
+        <Enum name="B_0x2F" description="ECC projective to affine" start="0x2F" />
+      </BitField>
+      <BitField name="PROCENDIE" description="End of operation interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when PROCENDF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when PROCENDF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="RAMERRIE" description="RAM error interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when RAMERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when RAMERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRIE" description="Address error interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when ADDRERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when ADDRERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="OPERRIE" description="Operation error interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when OPERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when OPERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PKA_SR" description="PKA status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INITOK" description="PKA initialization OK" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PKA is not initialized correctly. START bit cannot be set." start="0x0" />
+        <Enum name="B_0x1" description="PKA is initialized correctly and can be used normally." start="0x1" />
+      </BitField>
+      <BitField name="LMF" description="Limited mode flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="All values documented in MODE bitfield can be used." start="0x0" />
+        <Enum name="B_0x1" description="Only ECDSA verification (MODE = 0x26) is supported by the PKA." start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="PKA operation is in progress" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No operation is in progress (default)" start="0x0" />
+        <Enum name="B_0x1" description="An operation is in progress" start="0x1" />
+      </BitField>
+      <BitField name="PROCENDF" description="PKA End of Operation flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Operation in progress" start="0x0" />
+        <Enum name="B_0x1" description="PKA operation is completed. This flag is set when the BUSY bit is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="RAMERRF" description="PKA RAM error flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No PKA RAM access error" start="0x0" />
+        <Enum name="B_0x1" description="An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress)." start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRF" description="Address error flag" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No address error" start="0x0" />
+        <Enum name="B_0x1" description="Address access is out of range (unmapped address)" start="0x1" />
+      </BitField>
+      <BitField name="OPERRF" description="Operation error flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No event error" start="0x0" />
+        <Enum name="B_0x1" description="An illegal or unknown operation has been selected in PKA_CR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PKA_CLRFR" description="PKA clear flag register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCENDFC" description="Clear PKA End of Operation flag" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the PROCENDF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="RAMERRFC" description="Clear PKA RAM error flag" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the RAMERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRFC" description="Clear address error flag" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the ADDRERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="OPERRFC" description="Clear operation error flag" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the OPERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PKA_S" description="Public key accelerator" start="0x54022000">
+    <Register name="PKA_CR" description="PKA control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="PKA enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable PKA" start="0x0" />
+        <Enum name="B_0x1" description="Enable PKA.PKA becomes functional when INITOK is set by hardware in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="START" description="start the operation" start="1" size="1" access="Read/Write" />
+      <BitField name="MODE" description="PKA operation code" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Montgomery parameter computation then modular exponentiation" start="0x0" />
+        <Enum name="B_0x1" description="Montgomery parameter computation only" start="0x1" />
+        <Enum name="B_0x2" description="Modular exponentiation only (Montgomery parameter must be loaded first)" start="0x2" />
+        <Enum name="B_0x3" description="Modular exponentiation (protected, used when manipulating secrets)" start="0x3" />
+        <Enum name="B_0x20" description="Montgomery parameter computation then ECC scalar multiplication" start="0x20" />
+        <Enum name="B_0x24" description="ECDSA sign" start="0x24" />
+        <Enum name="B_0x26" description="ECDSA verification" start="0x26" />
+        <Enum name="B_0x28" description="Point on elliptic curve Fp check" start="0x28" />
+        <Enum name="B_0x7" description="RSA CRT exponentiation" start="0x7" />
+        <Enum name="B_0x8" description="Modular inversion" start="0x8" />
+        <Enum name="B_0x9" description="Arithmetic addition" start="0x9" />
+        <Enum name="B_0xA" description="Arithmetic subtraction" start="0xA" />
+        <Enum name="B_0xB" description="Arithmetic multiplication" start="0xB" />
+        <Enum name="B_0xC" description="Arithmetic comparison" start="0xC" />
+        <Enum name="B_0xD" description="Modular reduction" start="0xD" />
+        <Enum name="B_0xE" description="Modular addition" start="0xE" />
+        <Enum name="B_0xF" description="Modular subtraction" start="0xF" />
+        <Enum name="B_0x10" description="Montgomery multiplication" start="0x10" />
+        <Enum name="B_0x23" description="ECC complete addition" start="0x23" />
+        <Enum name="B_0x27" description="ECC double base ladder" start="0x27" />
+        <Enum name="B_0x2F" description="ECC projective to affine" start="0x2F" />
+      </BitField>
+      <BitField name="PROCENDIE" description="End of operation interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when PROCENDF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when PROCENDF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="RAMERRIE" description="RAM error interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when RAMERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when RAMERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRIE" description="Address error interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when ADDRERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when ADDRERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+      <BitField name="OPERRIE" description="Operation error interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt is generated when OPERRF flag is set in PKA_SR." start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated when OPERRF flag is set in PKA_SR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PKA_SR" description="PKA status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INITOK" description="PKA initialization OK" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PKA is not initialized correctly. START bit cannot be set." start="0x0" />
+        <Enum name="B_0x1" description="PKA is initialized correctly and can be used normally." start="0x1" />
+      </BitField>
+      <BitField name="LMF" description="Limited mode flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="All values documented in MODE bitfield can be used." start="0x0" />
+        <Enum name="B_0x1" description="Only ECDSA verification (MODE = 0x26) is supported by the PKA." start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="PKA operation is in progress" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No operation is in progress (default)" start="0x0" />
+        <Enum name="B_0x1" description="An operation is in progress" start="0x1" />
+      </BitField>
+      <BitField name="PROCENDF" description="PKA End of Operation flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Operation in progress" start="0x0" />
+        <Enum name="B_0x1" description="PKA operation is completed. This flag is set when the BUSY bit is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="RAMERRF" description="PKA RAM error flag" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No PKA RAM access error" start="0x0" />
+        <Enum name="B_0x1" description="An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress)." start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRF" description="Address error flag" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No address error" start="0x0" />
+        <Enum name="B_0x1" description="Address access is out of range (unmapped address)" start="0x1" />
+      </BitField>
+      <BitField name="OPERRF" description="Operation error flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No event error" start="0x0" />
+        <Enum name="B_0x1" description="An illegal or unknown operation has been selected in PKA_CR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PKA_CLRFR" description="PKA clear flag register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCENDFC" description="Clear PKA End of Operation flag" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the PROCENDF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="RAMERRFC" description="Clear PKA RAM error flag" start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the RAMERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="ADDRERRFC" description="Clear address error flag" start="20" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the ADDRERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+      <BitField name="OPERRFC" description="Clear operation error flag" start="21" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Clear the OPERRF flag in PKA_SR" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PSSI" description="Parallel synchronous slave interface" start="0x48026400">
+    <Register name="PSSI_CR" description="PSSI control register" start="+0x00" size="4" reset_value="0x40000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKPOL" description="Parallel data clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active for inputs or rising edge active for outputs" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active for inputs or falling edge active for outputs." start="0x1" />
+      </BitField>
+      <BitField name="DEPOL" description="Data enable (PSSI_DE) polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE active low (0 indicates that data is valid)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_DE active high (1 indicates that data is valid)" start="0x1" />
+      </BitField>
+      <BitField name="RDYPOL" description="Ready (PSSI_RDY) polarity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_RDY active low (0 indicates that the receiver is ready to receive)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_RDY active high (1 indicates that the receiver is ready to receive)" start="0x1" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every parallel data clock" start="0x0" />
+        <Enum name="B_0x3" description="The interface captures 16-bit data on every parallel data clock" start="0x3" />
+      </BitField>
+      <BitField name="ENABLE" description="PSSI enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI disabled" start="0x0" />
+        <Enum name="B_0x1" description="PSSI enabled" start="0x1" />
+      </BitField>
+      <BitField name="DERDYCFG" description="Data enable and ready configuration" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE and PSSI_RDY both disabled" start="0x0" />
+        <Enum name="B_0x1" description="Only PSSI_RDY enabled" start="0x1" />
+        <Enum name="B_0x2" description="Only PSSI_DE enabled" start="0x2" />
+        <Enum name="B_0x3" description="Both PSSI_RDY and PSSI_DE alternate functions enabled" start="0x3" />
+        <Enum name="B_0x4" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2004)" start="0x4" />
+        <Enum name="B_0x5" description="Only PSSI_RDY function enabled, but mapped to PSSI_DE pin" start="0x5" />
+        <Enum name="B_0x6" description="Only PSSI_DE function enabled, but mapped to PSSI_RDY pin" start="0x6" />
+        <Enum name="B_0x7" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2004)" start="0x7" />
+      </BitField>
+      <BitField name="CKSRC" description="Clock source" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock (PSSI_PDCK in input)" start="0x0" />
+        <Enum name="B_0x1" description="Internal clock (PSSI_PDCK in output)" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable bit" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled." start="0x0" />
+        <Enum name="B_0x1" description="DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR." start="0x1" />
+      </BitField>
+      <BitField name="OUTEN" description="Data direction selection bit" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive mode: data is input synchronously with PSSI_PDCK" start="0x0" />
+        <Enum name="B_0x1" description="Transmit mode: data is output synchronously with PSSI_PDCK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_SR" description="PSSI status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTT4B" description="FIFO is ready to transfer four bytes" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a four-byte transfer" start="0x0" />
+      </BitField>
+      <BitField name="RTT1B" description="FIFO is ready to transfer one byte" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a 1-byte transfer" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_RIS" description="PSSI raw interrupt status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_RIS" description="Data buffer overrun/underrun raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_IER" description="PSSI interrupt enable register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_IE" description="Data buffer overrun/underrun interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if either an overrun or an underrun error occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_MIS" description="PSSI masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_MIS" description="Data buffer overrun/underrun masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated when an overrun/underrun error occurs" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_ICR" description="PSSI interrupt clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_ISC" description="Data buffer overrun/underrun interrupt status clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="PSSI_DR" description="PSSI data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTE0" description="Data byte 0" start="0" size="8" access="Read/Write" />
+      <BitField name="BYTE1" description="Data byte 1" start="8" size="8" access="Read/Write" />
+      <BitField name="BYTE2" description="Data byte 2" start="16" size="8" access="Read/Write" />
+      <BitField name="BYTE3" description="Data byte 3" start="24" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PSSI_S" description="Parallel synchronous slave interface" start="0x58026400">
+    <Register name="PSSI_CR" description="PSSI control register" start="+0x00" size="4" reset_value="0x40000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKPOL" description="Parallel data clock polarity" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active for inputs or rising edge active for outputs" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active for inputs or falling edge active for outputs." start="0x1" />
+      </BitField>
+      <BitField name="DEPOL" description="Data enable (PSSI_DE) polarity" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE active low (0 indicates that data is valid)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_DE active high (1 indicates that data is valid)" start="0x1" />
+      </BitField>
+      <BitField name="RDYPOL" description="Ready (PSSI_RDY) polarity" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_RDY active low (0 indicates that the receiver is ready to receive)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_RDY active high (1 indicates that the receiver is ready to receive)" start="0x1" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every parallel data clock" start="0x0" />
+        <Enum name="B_0x3" description="The interface captures 16-bit data on every parallel data clock" start="0x3" />
+      </BitField>
+      <BitField name="ENABLE" description="PSSI enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI disabled" start="0x0" />
+        <Enum name="B_0x1" description="PSSI enabled" start="0x1" />
+      </BitField>
+      <BitField name="DERDYCFG" description="Data enable and ready configuration" start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE and PSSI_RDY both disabled" start="0x0" />
+        <Enum name="B_0x1" description="Only PSSI_RDY enabled" start="0x1" />
+        <Enum name="B_0x2" description="Only PSSI_DE enabled" start="0x2" />
+        <Enum name="B_0x3" description="Both PSSI_RDY and PSSI_DE alternate functions enabled" start="0x3" />
+        <Enum name="B_0x4" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2004)" start="0x4" />
+        <Enum name="B_0x5" description="Only PSSI_RDY function enabled, but mapped to PSSI_DE pin" start="0x5" />
+        <Enum name="B_0x6" description="Only PSSI_DE function enabled, but mapped to PSSI_RDY pin" start="0x6" />
+        <Enum name="B_0x7" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 2004)" start="0x7" />
+      </BitField>
+      <BitField name="CKSRC" description="Clock source" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock (PSSI_PDCK in input)" start="0x0" />
+        <Enum name="B_0x1" description="Internal clock (PSSI_PDCK in output)" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable bit" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled." start="0x0" />
+        <Enum name="B_0x1" description="DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR." start="0x1" />
+      </BitField>
+      <BitField name="OUTEN" description="Data direction selection bit" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive mode: data is input synchronously with PSSI_PDCK" start="0x0" />
+        <Enum name="B_0x1" description="Transmit mode: data is output synchronously with PSSI_PDCK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_SR" description="PSSI status register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTT4B" description="FIFO is ready to transfer four bytes" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a four-byte transfer" start="0x0" />
+      </BitField>
+      <BitField name="RTT1B" description="FIFO is ready to transfer one byte" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a 1-byte transfer" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_RIS" description="PSSI raw interrupt status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_RIS" description="Data buffer overrun/underrun raw interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_IER" description="PSSI interrupt enable register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_IE" description="Data buffer overrun/underrun interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if either an overrun or an underrun error occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_MIS" description="PSSI masked interrupt status register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_MIS" description="Data buffer overrun/underrun masked interrupt status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated when an overrun/underrun error occurs" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_ICR" description="PSSI interrupt clear register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_ISC" description="Data buffer overrun/underrun interrupt status clear" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="PSSI_DR" description="PSSI data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTE0" description="Data byte 0" start="0" size="8" access="Read/Write" />
+      <BitField name="BYTE1" description="Data byte 1" start="8" size="8" access="Read/Write" />
+      <BitField name="BYTE2" description="Data byte 2" start="16" size="8" access="Read/Write" />
+      <BitField name="BYTE3" description="Data byte 3" start="24" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PWR" description="Power control" start="0x46024800">
+    <Register name="PWR_CR1" description="PWR control register 1" start="+0x000" size="4" reset_value="0x00000024" reset_mask="0xFFFFFFFF">
+      <BitField name="SDEN" description="SMPS step-down converter enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMPS step-down converter disabled" start="0x0" />
+        <Enum name="B_0x1" description="SMPS step-down converter enabled (default)" start="0x1" />
+      </BitField>
+      <BitField name="MODE_PDN" description="Enables the pull down on output voltage during power-down mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down disabled. The output is in high impedance during the shutdown (default)." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPDS08V" description="SMPS low-power mode enable (SVOS high only)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMPS low-power mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="SMPS low-power mode enabled (high-efficiency mode) (default)" start="0x1" />
+      </BitField>
+      <BitField name="POPL" description="pwr_on pulse low configuration." start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="No guaranteed minimum low time" start="0x0" />
+        <Enum name="B_0x1" description="~ 1 ms guaranteed minimum low time (1 x 32 LSI cycles)" start="0x1" />
+        <Enum name="B_0x2" description="~ 2 ms guaranteed minimum low time (2 x 32 LSI cycles)" start="0x2" />
+        <Enum name="B_0x1F" description="~ 31 ms guaranteed minimum low time (31 x 32 LSI cycles)" start="0x1F" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR2" description="PWR control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVDEN" description="Programmable voltage detector enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PVD disabled" start="0x0" />
+        <Enum name="B_0x1" description="PVD enabled" start="0x1" />
+      </BitField>
+      <BitField name="PVDO" description="Programmable voltage detect output" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Voltage level on PVD_IN is equal or higher than the internal VREFINT." start="0x0" />
+        <Enum name="B_0x1" description="Voltage level on PVD_IN is lower than the internal VREFINT." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR3" description="PWR control register 3" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VCOREMONEN" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring enabled" start="0x1" />
+      </BitField>
+      <BitField name="VCORELLS" description="Vless thansub&gt;DDCOREless than/sub&gt; voltage detector low-level selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; low-voltage threshold 1 selected (VOS low)" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; low-voltage threshold 2 selected (VOS high)" start="0x1" />
+      </BitField>
+      <BitField name="VCOREL" description="Monitored Vless thansub&gt;DDCOREless than/sub&gt; level above low threshold" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; level above low threshold level, or monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; level equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="VCOREH" description="Monitored Vless thansub&gt;DDCOREless than/sub&gt; level above high threshold" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; level below high threshold level, or monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; level equal or above high threshold level" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR4" description="PWR control register 4" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCMRBSEN" description="I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I-TCM and D-TCM RAMs backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="I-TCM and D-TCM RAMs backup supply enabled in Standby mode" start="0x1" />
+      </BitField>
+      <BitField name="TCMFLXRBSEN" description="I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I-TCM FLEXMEM backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="I-TCM FLEXMEM backup supply enabled in Standby mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_VOSCR" description="PWR voltage scaling control register" start="+0x020" size="4" reset_value="0x00020002" reset_mask="0xFFFFFFFF">
+      <BitField name="VOS" description="Voltage scaling selection according to performance" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VOS low level (default)" start="0x0" />
+        <Enum name="B_0x1" description="VOS high level" start="0x1" />
+      </BitField>
+      <BitField name="VOSRDY" description="VOS ready bit for Vless thansub&gt;COREless than/sub&gt; voltage scaling output selection" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not ready, voltage level below VOS selected level" start="0x0" />
+        <Enum name="B_0x1" description="Ready, voltage level at or above VOS selected level" start="0x1" />
+      </BitField>
+      <BitField name="ACTVOS" description="VOS currently applied for Vless thansub&gt;COREless than/sub&gt; voltage scaling selection" start="16" size="1" access="ReadOnly" />
+      <BitField name="ACTVOSRDY" description="Voltage level ready bit for currently used ACTVOS " start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Voltage level invalid, above or below current ACTVOS" start="0x0" />
+        <Enum name="B_0x1" description="Voltage level valid, at current ACTVOS" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_BDCR1" description="PWR backup domain control register 1" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MONEN" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBATL" description="Vless thansub&gt;BATless than/sub&gt; level monitoring versus low threshold" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; level above low threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; level equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="VBATH" description="Vless thansub&gt;BATless than/sub&gt; level monitoring versus high threshold" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; level below high threshold level." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; level equal or above high threshold level" start="0x1" />
+      </BitField>
+      <BitField name="TEMPL" description="Temperature level monitoring versus low threshold" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Temperature above low threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Temperature equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="TEMPH" description="Temperature level monitoring versus high threshold" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Temperature below high threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Temperature equal or above high threshold level" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_BDCR2" description="PWR backup domain control register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKPRBSEN" description="Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and Vless thansub&gt;BATless than/sub&gt; modes)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM backup supply enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_DBPCR" description="PWR disable backup protection control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBP" description="Disable backup domain write protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write access to backup domain disabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to backup domain enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CPUCR" description="PWR CPU control register" start="+0x030" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDDS" description="Power-down deepsleep selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop mode when device enters deepsleep" start="0x0" />
+        <Enum name="B_0x1" description="Standby mode when device enters deepsleep" start="0x1" />
+      </BitField>
+      <BitField name="CSSF" description="Clear Standby and Stop flags (always read as 0)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="When written, clear the CPU flags (STOPF, SBF)." start="0x1" />
+      </BitField>
+      <BitField name="STOPF" description="Stop flag " start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="System has not been in Stop mode." start="0x0" />
+        <Enum name="B_0x1" description="System has been in Stop mode." start="0x1" />
+      </BitField>
+      <BitField name="SBF" description="Standby flag " start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="System has not been in Standby mode." start="0x0" />
+        <Enum name="B_0x1" description="System has been in Standby mode." start="0x1" />
+      </BitField>
+      <BitField name="SVOS" description="System Stop mode voltage scaling selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SVOS low" start="0x0" />
+        <Enum name="B_0x1" description="SVOS high (default)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR1" description="PWR supply voltage monitoring control register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO4VMEN" description="Vless thansub&gt;DDIO4 less than/sub&gt;independent I/O voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4SV" description="Vless thansub&gt;DDIO4 less than/sub&gt;independent I/O supply valid." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4RDY" description="Vless thansub&gt;DDIO4 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; is below the threshold of the Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; is equal or above the threshold of the Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4VRSEL" description="Vless thansub&gt;DDIO4less than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO4less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO4 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO4less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4VRSTBY" description="Vless thansub&gt;DDIO4less than/sub&gt; I/O voltage range Standby mode " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO4VRSEL not retained in Standby mode" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO4VRSEL retained in Standby mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR2" description="PWR supply voltage monitoring control register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO5VMEN" description="Vless thansub&gt;DDIO5 less than/sub&gt;independent voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5 less than/sub&gt;voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5 less than/sub&gt;voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5SV" description="Vless thansub&gt;DDIO5 less than/sub&gt;independent supply valid" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5RDY" description="Vless thansub&gt;DDIO5 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5less than/sub&gt; is below the threshold of the Vless thansub&gt;DDIO5less than/sub&gt; voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5less than/sub&gt; is equal or above the threshold of the Vless thansub&gt;DDIO5less than/sub&gt; voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5VRSEL" description="Vless thansub&gt;DDIO5less than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO5less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO5 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO5less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5VRSTBY" description="Vless thansub&gt;DDIO5less than/sub&gt; I/O voltage range Standby mode " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO5VRSEL not retained in Standby mode" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO5VRSEL retained in Standby mod." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR3" description="PWR supply voltage monitoring control register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO2VMEN" description="Vless thansub&gt;DDIO2 less than/sub&gt;independent voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3VMEN" description="Vless thansub&gt;DDIO3 less than/sub&gt;independent voltage monitor enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="USB33VMEN" description="Vless thansub&gt;DD33USB less than/sub&gt;independent USB 33 voltage monitor enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="AVMEN" description="Vless thansub&gt;DDA18ADC less than/sub&gt;independent ADC voltage monitor enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2SV" description="Vless thansub&gt;DDIO2 less than/sub&gt;independent supply valid." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3SV" description="Vless thansub&gt;DDIO3 less than/sub&gt;independent supply valid" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="USB33SV" description="Vless thansub&gt;DD33USB less than/sub&gt;independent supply valid" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="ASV" description="Vless thansub&gt;DDA18ADC less than/sub&gt;independent supply valid" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2RDY" description="Vless thansub&gt;DDIO2 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; is below the threshold of the VDDIO2 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; is equal or above the threshold of the VDDIO2 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3RDY" description="Vless thansub&gt;DDIO3 less than/sub&gt;ready" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; is below the threshold of the VDDIO3 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; is equal or above the threshold of the VDDIO3 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="USB33RDY" description="Vless thansub&gt;DD33USB less than/sub&gt;ready" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; is below the threshold of the USB33 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; is equal or above the threshold of the USB33 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="ARDY" description="Vless thansub&gt;DDA18ADC less than/sub&gt;ready" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is below the threshold of the VDDA18ADC voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is equal or above the threshold of the VDDA18ADC voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIOVRSEL" description="Vless thansub&gt;DDless than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDless than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDD option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDless than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2VRSEL" description="Vless thansub&gt;DDIO2less than/sub&gt; I/O voltage range selection " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO2less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO2 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO2less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3VRSEL" description="Vless thansub&gt;DDIO3less than/sub&gt; I/O voltage range selection" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO3less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO3 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO3less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPCR" description="PWR wake-up clear register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPC1" description="Clear wake-up flag for WKUP1 pin" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF1 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC2" description="Clear wake-up flag for WKUP2 pin" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF2 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC3" description="Clear wake-up flag for WKUP3 pin" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF3 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC4" description="Clear wake-up flag for WKUP4 pin" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF4 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPSR" description="PWR wake-up status register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPF1" description="Wake-up flag for WKUP1 pin before enable" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP1 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF2" description="Wake-up flag for WKUP2 pin before enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP2 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF3" description="Wake-up flag for WKUP3 pin before enable" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP3 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF4" description="Wake-up flag for WKUP4 pin before enable" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP4 pin." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPEPR" description="PWR wake-up enable and polarity register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPEN1" description="Enable WKUP1 pin" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP1 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP1 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN2" description="Enable WKUP2 pin" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP2 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP2 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN3" description="Enable WKUP3 pin" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP3 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP3 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN4" description="Enable WKUP4 pin" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP4 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP4 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPP1" description="Wake-up polarity bit for WKUP1 pin" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP2" description="Wake-up polarity bit for WKUP2 pin" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP3" description="Wake-up polarity bit for WKUP3 pin" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP4" description="Wake-up polarity bit for WKUP4 pin" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPPUPD1" description="Wake-up pull configuration for WKUP1 pin" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD2" description="Wake-up pull configuration for WKUP2 pin" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD3" description="Wake-up pull configuration for WKUP3 pin" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD4" description="Wake-up pull configuration for WKUP4 pin" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SECCFGR" description="PWR security configuration register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="System supply configuration secure protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR1 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR1 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="Programmable voltage detector secure protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR2 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR2 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="Vless thansub&gt;DDCOREless than/sub&gt; monitor secure protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR3 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR3 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR4 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR4 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="Voltage scaling selection secure protection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_VOSCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_VOSCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="Backup domain secure protection" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="CPU power control secure protection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CPUCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CPUCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="Peripheral voltage monitor secure protection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC1" description="WKUP1 pin secure protection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC2" description="WKUP2 pin secure protection" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC3" description="WKUP3 pin secure protection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC4" description="WKUP4 pin secure protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_PRIVCFGR" description="PWR privilege configuration register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="System supply configuration privileged protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR1 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR1 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="Programmable voltage detector privileged protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR2 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR2 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="Vless thansub&gt;DDCOREless than/sub&gt; monitor privileged protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR3 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR3 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I-TCM, D-TCM, and I-TCM FLEX MEM low power control privileged protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR4 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR4 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="Voltage scaling selection privileged protection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_VOSCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_VOSCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="Backup domain privileged protection" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="CPU power control privileged protection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CPUCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CPUCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="Peripheral voltage monitor privileged protection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV1" description="WKUP1 pin privileged protection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV2" description="WKUP2 pin privileged protection" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV3" description="WKUP3 pin privileged protection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV4" description="WKUP4 pin privileged protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PWR_S" description="Power control" start="0x56024800">
+    <Register name="PWR_CR1" description="PWR control register 1" start="+0x000" size="4" reset_value="0x00000024" reset_mask="0xFFFFFFFF">
+      <BitField name="SDEN" description="SMPS step-down converter enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMPS step-down converter disabled" start="0x0" />
+        <Enum name="B_0x1" description="SMPS step-down converter enabled (default)" start="0x1" />
+      </BitField>
+      <BitField name="MODE_PDN" description="Enables the pull down on output voltage during power-down mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down disabled. The output is in high impedance during the shutdown (default)." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPDS08V" description="SMPS low-power mode enable (SVOS high only)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMPS low-power mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="SMPS low-power mode enabled (high-efficiency mode) (default)" start="0x1" />
+      </BitField>
+      <BitField name="POPL" description="pwr_on pulse low configuration." start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="No guaranteed minimum low time" start="0x0" />
+        <Enum name="B_0x1" description="~ 1 ms guaranteed minimum low time (1 x 32 LSI cycles)" start="0x1" />
+        <Enum name="B_0x2" description="~ 2 ms guaranteed minimum low time (2 x 32 LSI cycles)" start="0x2" />
+        <Enum name="B_0x1F" description="~ 31 ms guaranteed minimum low time (31 x 32 LSI cycles)" start="0x1F" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR2" description="PWR control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVDEN" description="Programmable voltage detector enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PVD disabled" start="0x0" />
+        <Enum name="B_0x1" description="PVD enabled" start="0x1" />
+      </BitField>
+      <BitField name="PVDO" description="Programmable voltage detect output" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Voltage level on PVD_IN is equal or higher than the internal VREFINT." start="0x0" />
+        <Enum name="B_0x1" description="Voltage level on PVD_IN is lower than the internal VREFINT." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR3" description="PWR control register 3" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VCOREMONEN" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; monitoring enabled" start="0x1" />
+      </BitField>
+      <BitField name="VCORELLS" description="Vless thansub&gt;DDCOREless than/sub&gt; voltage detector low-level selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; low-voltage threshold 1 selected (VOS low)" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; low-voltage threshold 2 selected (VOS high)" start="0x1" />
+      </BitField>
+      <BitField name="VCOREL" description="Monitored Vless thansub&gt;DDCOREless than/sub&gt; level above low threshold" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; level above low threshold level, or monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; level equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="VCOREH" description="Monitored Vless thansub&gt;DDCOREless than/sub&gt; level above high threshold" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDCOREless than/sub&gt; level below high threshold level, or monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDCOREless than/sub&gt; level equal or above high threshold level" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CR4" description="PWR control register 4" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCMRBSEN" description="I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I-TCM and D-TCM RAMs backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="I-TCM and D-TCM RAMs backup supply enabled in Standby mode" start="0x1" />
+      </BitField>
+      <BitField name="TCMFLXRBSEN" description="I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I-TCM FLEXMEM backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="I-TCM FLEXMEM backup supply enabled in Standby mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_VOSCR" description="PWR voltage scaling control register" start="+0x020" size="4" reset_value="0x00020002" reset_mask="0xFFFFFFFF">
+      <BitField name="VOS" description="Voltage scaling selection according to performance" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VOS low level (default)" start="0x0" />
+        <Enum name="B_0x1" description="VOS high level" start="0x1" />
+      </BitField>
+      <BitField name="VOSRDY" description="VOS ready bit for Vless thansub&gt;COREless than/sub&gt; voltage scaling output selection" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not ready, voltage level below VOS selected level" start="0x0" />
+        <Enum name="B_0x1" description="Ready, voltage level at or above VOS selected level" start="0x1" />
+      </BitField>
+      <BitField name="ACTVOS" description="VOS currently applied for Vless thansub&gt;COREless than/sub&gt; voltage scaling selection" start="16" size="1" access="ReadOnly" />
+      <BitField name="ACTVOSRDY" description="Voltage level ready bit for currently used ACTVOS " start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Voltage level invalid, above or below current ACTVOS" start="0x0" />
+        <Enum name="B_0x1" description="Voltage level valid, at current ACTVOS" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_BDCR1" description="PWR backup domain control register 1" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MONEN" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; and temperature monitoring enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBATL" description="Vless thansub&gt;BATless than/sub&gt; level monitoring versus low threshold" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; level above low threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; level equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="VBATH" description="Vless thansub&gt;BATless than/sub&gt; level monitoring versus high threshold" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;BATless than/sub&gt; level below high threshold level." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;BATless than/sub&gt; level equal or above high threshold level" start="0x1" />
+      </BitField>
+      <BitField name="TEMPL" description="Temperature level monitoring versus low threshold" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Temperature above low threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Temperature equal or below low threshold level" start="0x1" />
+      </BitField>
+      <BitField name="TEMPH" description="Temperature level monitoring versus high threshold" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Temperature below high threshold level" start="0x0" />
+        <Enum name="B_0x1" description="Temperature equal or above high threshold level" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_BDCR2" description="PWR backup domain control register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKPRBSEN" description="Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and Vless thansub&gt;BATless than/sub&gt; modes)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM backup supply disabled" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM backup supply enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_DBPCR" description="PWR disable backup protection control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBP" description="Disable backup domain write protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Write access to backup domain disabled" start="0x0" />
+        <Enum name="B_0x1" description="Write access to backup domain enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_CPUCR" description="PWR CPU control register" start="+0x030" size="4" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDDS" description="Power-down deepsleep selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop mode when device enters deepsleep" start="0x0" />
+        <Enum name="B_0x1" description="Standby mode when device enters deepsleep" start="0x1" />
+      </BitField>
+      <BitField name="CSSF" description="Clear Standby and Stop flags (always read as 0)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="When written, clear the CPU flags (STOPF, SBF)." start="0x1" />
+      </BitField>
+      <BitField name="STOPF" description="Stop flag " start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="System has not been in Stop mode." start="0x0" />
+        <Enum name="B_0x1" description="System has been in Stop mode." start="0x1" />
+      </BitField>
+      <BitField name="SBF" description="Standby flag " start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="System has not been in Standby mode." start="0x0" />
+        <Enum name="B_0x1" description="System has been in Standby mode." start="0x1" />
+      </BitField>
+      <BitField name="SVOS" description="System Stop mode voltage scaling selection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SVOS low" start="0x0" />
+        <Enum name="B_0x1" description="SVOS high (default)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR1" description="PWR supply voltage monitoring control register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO4VMEN" description="Vless thansub&gt;DDIO4 less than/sub&gt;independent I/O voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4SV" description="Vless thansub&gt;DDIO4 less than/sub&gt;independent I/O supply valid." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4RDY" description="Vless thansub&gt;DDIO4 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO4less than/sub&gt; is below the threshold of the Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO4less than/sub&gt; is equal or above the threshold of the Vless thansub&gt;DDIO4less than/sub&gt; voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4VRSEL" description="Vless thansub&gt;DDIO4less than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO4less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO4 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO4less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO4VRSTBY" description="Vless thansub&gt;DDIO4less than/sub&gt; I/O voltage range Standby mode " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO4VRSEL not retained in Standby mode" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO4VRSEL retained in Standby mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR2" description="PWR supply voltage monitoring control register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO5VMEN" description="Vless thansub&gt;DDIO5 less than/sub&gt;independent voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5 less than/sub&gt;voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5 less than/sub&gt;voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5SV" description="Vless thansub&gt;DDIO5 less than/sub&gt;independent supply valid" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5RDY" description="Vless thansub&gt;DDIO5 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO5less than/sub&gt; is below the threshold of the Vless thansub&gt;DDIO5less than/sub&gt; voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO5less than/sub&gt; is equal or above the threshold of the Vless thansub&gt;DDIO5less than/sub&gt; voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5VRSEL" description="Vless thansub&gt;DDIO5less than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO5less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO5 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO5less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO5VRSTBY" description="Vless thansub&gt;DDIO5less than/sub&gt; I/O voltage range Standby mode " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO5VRSEL not retained in Standby mode" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO5VRSEL retained in Standby mod." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SVMCR3" description="PWR supply voltage monitoring control register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VDDIO2VMEN" description="Vless thansub&gt;DDIO2 less than/sub&gt;independent voltage monitor enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3VMEN" description="Vless thansub&gt;DDIO3 less than/sub&gt;independent voltage monitor enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="USB33VMEN" description="Vless thansub&gt;DD33USB less than/sub&gt;independent USB 33 voltage monitor enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="AVMEN" description="Vless thansub&gt;DDA18ADC less than/sub&gt;independent ADC voltage monitor enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; voltage monitor disabled" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; voltage monitor enabled" start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2SV" description="Vless thansub&gt;DDIO2 less than/sub&gt;independent supply valid." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3SV" description="Vless thansub&gt;DDIO3 less than/sub&gt;independent supply valid" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="USB33SV" description="Vless thansub&gt;DD33USB less than/sub&gt;independent supply valid" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="ASV" description="Vless thansub&gt;DDA18ADC less than/sub&gt;independent supply valid" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is not present. Logical and electrical isolation is applied to ignore this supply." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is valid." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2RDY" description="Vless thansub&gt;DDIO2 less than/sub&gt;ready" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO2less than/sub&gt; is below the threshold of the VDDIO2 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO2less than/sub&gt; is equal or above the threshold of the VDDIO2 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3RDY" description="Vless thansub&gt;DDIO3 less than/sub&gt;ready" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDIO3less than/sub&gt; is below the threshold of the VDDIO3 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDIO3less than/sub&gt; is equal or above the threshold of the VDDIO3 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="USB33RDY" description="Vless thansub&gt;DD33USB less than/sub&gt;ready" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DD33USBless than/sub&gt; is below the threshold of the USB33 voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DD33USBless than/sub&gt; is equal or above the threshold of the USB33 voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="ARDY" description="Vless thansub&gt;DDA18ADC less than/sub&gt;ready" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is below the threshold of the VDDA18ADC voltage monitor." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;DDA18ADCless than/sub&gt; is equal or above the threshold of the VDDA18ADC voltage monitor." start="0x1" />
+      </BitField>
+      <BitField name="VDDIOVRSEL" description="Vless thansub&gt;DDless than/sub&gt; I/O voltage range selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDless than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDD option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDless than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO2VRSEL" description="Vless thansub&gt;DDIO2less than/sub&gt; I/O voltage range selection " start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO2less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO2 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO2less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+      <BitField name="VDDIO3VRSEL" description="Vless thansub&gt;DDIO3less than/sub&gt; I/O voltage range selection" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3v3 voltage range selected. If Vless thansub&gt;DDIO3less than/sub&gt; is in 1v8 range with this setting, I/Os work in degraded mode." start="0x0" />
+        <Enum name="B_0x1" description="1v8 voltage range selected. HSLV_VDDIO3 option bit must be set to allow 1v8 voltage range operation. Setting this configuration while Vless thansub&gt;DDIO3less than/sub&gt; is in 3v3 range damages the device." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPCR" description="PWR wake-up clear register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPC1" description="Clear wake-up flag for WKUP1 pin" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF1 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC2" description="Clear wake-up flag for WKUP2 pin" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF2 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC3" description="Clear wake-up flag for WKUP3 pin" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF3 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+      <BitField name="WKUPC4" description="Clear wake-up flag for WKUP4 pin" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 clears WKUPF4 in PWR_WKUPSR." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPSR" description="PWR wake-up status register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPF1" description="Wake-up flag for WKUP1 pin before enable" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP1 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF2" description="Wake-up flag for WKUP2 pin before enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP2 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF3" description="Wake-up flag for WKUP3 pin before enable" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP3 pin." start="0x1" />
+      </BitField>
+      <BitField name="WKUPF4" description="Wake-up flag for WKUP4 pin before enable" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No wake-up event occurred" start="0x0" />
+        <Enum name="B_0x1" description="A wake-up event was received from WKUP4 pin." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_WKUPEPR" description="PWR wake-up enable and polarity register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPEN1" description="Enable WKUP1 pin" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP1 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP1 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN2" description="Enable WKUP2 pin" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP2 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP2 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN3" description="Enable WKUP3 pin" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP3 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP3 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPEN4" description="Enable WKUP4 pin" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="An event on WKUP4 pin does not wake up the system from Standby and Stop modes." start="0x0" />
+        <Enum name="B_0x1" description="A rising or falling edge on WKUP4 pin wakes up the system from Standby and Stop modes." start="0x1" />
+      </BitField>
+      <BitField name="WKUPP1" description="Wake-up polarity bit for WKUP1 pin" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP2" description="Wake-up polarity bit for WKUP2 pin" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP3" description="Wake-up polarity bit for WKUP3 pin" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPP4" description="Wake-up polarity bit for WKUP4 pin" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Detection on high level (rising edge)" start="0x0" />
+        <Enum name="B_0x1" description="Detection on low level (falling edge)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPPUPD1" description="Wake-up pull configuration for WKUP1 pin" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD2" description="Wake-up pull configuration for WKUP2 pin" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD3" description="Wake-up pull configuration for WKUP3 pin" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+      <BitField name="WKUPPUPD4" description="Wake-up pull configuration for WKUP4 pin" start="22" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No pulls" start="0x0" />
+        <Enum name="B_0x1" description="Pull-up" start="0x1" />
+        <Enum name="B_0x2" description="Pull-down" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="PWR_SECCFGR" description="PWR security configuration register" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="System supply configuration secure protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR1 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR1 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="Programmable voltage detector secure protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR2 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR2 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="Vless thansub&gt;DDCOREless than/sub&gt; monitor secure protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR3 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR3 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR4 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR4 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="Voltage scaling selection secure protection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_VOSCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_VOSCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="Backup domain secure protection" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="CPU power control secure protection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CPUCR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CPUCR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="Peripheral voltage monitor secure protection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC1" description="WKUP1 pin secure protection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC2" description="WKUP2 pin secure protection" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC3" description="WKUP3 pin secure protection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPSEC4" description="WKUP4 pin secure protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with secure or non-secure access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with secure access." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PWR_PRIVCFGR" description="PWR privilege configuration register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="System supply configuration privileged protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR1 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR1 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="Programmable voltage detector privileged protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR2 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR2 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="Vless thansub&gt;DDCOREless than/sub&gt; monitor privileged protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR3 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR3 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="I-TCM, D-TCM, and I-TCM FLEX MEM low power control privileged protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CR4 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CR4 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="Voltage scaling selection privileged protection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_VOSCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_VOSCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="Backup domain privileged protection" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="CPU power control privileged protection" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_CPUCR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_CPUCR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="Peripheral voltage monitor privileged protection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV1" description="WKUP1 pin privileged protection" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV2" description="WKUP2 pin privileged protection" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV3" description="WKUP3 pin privileged protection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="WKUPPRIV4" description="WKUP4 pin privileged protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR can be read and written only with privileged access." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RAMCFG" description="SRAM configuration controller" start="0x42023000">
+    <Register name="RAMCFG_AXISRAM1CR" description="RAMCFG AXISRAM1 control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM1ISR" description="RAMCFG AXISRAM1 interrupt status register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM1ERKEYR" description="RAMCFG AXISRAM1 erase key register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM2CR" description="RAMCFG AXISRAM2 control register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM2ISR" description="RAMCFG AXISRAM2 interrupt status register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM2ERKEYR" description="RAMCFG AXISRAM2 erase key register" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM3CR" description="RAMCFG AXISRAM3 control register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM3ISR" description="RAMCFG AXISRAM3 interrupt status register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM3ERKEYR" description="RAMCFG AXISRAM3 erase key register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM4CR" description="RAMCFG AXISRAM4 control register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM4ISR" description="RAMCFG AXISRAM4 interrupt status register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM4ERKEYR" description="RAMCFG AXISRAM4 erase key register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM5CR" description="RAMCFG AXISRAM5 control register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM5ISR" description="RAMCFG AXISRAM5 interrupt status register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM5ERKEYR" description="RAMCFG AXISRAM5 erase key register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM6CR" description="RAMCFG AXISRAM6 control register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM6ISR" description="RAMCFG AXISRAM6 interrupt status register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM6ERKEYR" description="RAMCFG AXISRAM6 erase key register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1CR" description="RAMCFG AHBSRAM1 control register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1ISR" description="RAMCFG AHBSRAM1 interrupt status register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1ERKEYR" description="RAMCFG AHBSRAM1 erase key register" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2CR" description="RAMCFG AHBSRAM2 control register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2ISR" description="RAMCFG AHBSRAM2 interrupt status register" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2ERKEYR" description="RAMCFG AHBSRAM2 erase key register" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_VENCRAMCR" description="RAMCFG VENCRAM control register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_VENCRAMISR" description="RAMCFG VENCRAM interrupt status register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_VENCRAMERKEYR" description="RAMCFG VENCRAM erase key register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMCR" description="RAMCFG BKPSRAM control register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCE" description="ECC enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC disabled" start="0x0" />
+        <Enum name="B_0x1" description="ECC enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALE" description="Address latch enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Failing address not stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR" start="0x0" />
+        <Enum name="B_0x1" description="Failing address stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR" start="0x1" />
+      </BitField>
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMIER" description="RAMCFG BKPSRAM interrupt enable register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEIE" description="ECC single error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Single error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEIE" description="ECC double error interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Double error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Double error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMISR" description="RAMCFG BKPSRAM interrupt status register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC" description="ECC single error detected" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No single error detected" start="0x0" />
+        <Enum name="B_0x1" description="Single error detected and corrected" start="0x1" />
+      </BitField>
+      <BitField name="DED" description="ECC double-error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double error" start="0x0" />
+        <Enum name="B_0x1" description="Double error detected" start="0x1" />
+      </BitField>
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMESEAR" description="RAMCFG BKPSRAM single error address register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESEA" description="ECC single error address" start="0" size="11" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMEDEAR" description="RAMCFG BKPSRAM double error address register" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EDEA" description="ECC double error address" start="0" size="11" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMICR" description="RAMCFG BKPSRAM interrupt clear register" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSED" description="Clear ECC single-error interrupt" start="0" size="1" access="WriteOnly" />
+      <BitField name="CDED" description="Clear ECC double-error interrupt" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMECCKEYR" description="RAMCFG BKPSRAM ECC key register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCKEY" description="ECC write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMERKEYR" description="RAMCFG BKPSRAM erase key register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_FLEXRAMCR" description="RAMCFG FLEXRAM control register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMHWERDIS" description="SRAM hardware erase disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Erase operation done after a system reset" start="0x0" />
+        <Enum name="B_0x1" description="No erase operation done after a system reset, only for the retention part of the FLEXMEM when it is used as AXI RAM" start="0x1" />
+      </BitField>
+      <BitField name="ITCMCFG" description="Configuration of the FLEXMEM I-TCM extension" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXMEM I-TCM extension entirely allocated as AXI RAM" start="0x0" />
+        <Enum name="B_0x1" description="First 64 Kbytes (and corresponding ECC) allocated as I-TCM, remaining part allocated as AXI RAM" start="0x1" />
+        <Enum name="B_0x2" description="FLEXMEM I-TCM extension entirely allocated as AXI RAM" start="0x2" />
+      </BitField>
+      <BitField name="DTCMCFG" description="Configuration of the FLEXMEM D-TCM extension" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXMEM D-TCM extension allocated as AXI RAM" start="0x0" />
+        <Enum name="B_0x1" description="FLEXMEM D-TCM extension allocated as DTCM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_FLEXRAMISR" description="RAMCFG FLEXRAM interrupt status register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_FLEXRAMERKEYR" description="RAMCFG FLEXRAM erase key register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RAMCFG_S" description="SRAM configuration controller" start="0x52023000">
+    <Register name="RAMCFG_AXISRAM1CR" description="RAMCFG AXISRAM1 control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM1ISR" description="RAMCFG AXISRAM1 interrupt status register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM1ERKEYR" description="RAMCFG AXISRAM1 erase key register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM2CR" description="RAMCFG AXISRAM2 control register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM2ISR" description="RAMCFG AXISRAM2 interrupt status register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM2ERKEYR" description="RAMCFG AXISRAM2 erase key register" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM3CR" description="RAMCFG AXISRAM3 control register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM3ISR" description="RAMCFG AXISRAM3 interrupt status register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM3ERKEYR" description="RAMCFG AXISRAM3 erase key register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM4CR" description="RAMCFG AXISRAM4 control register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM4ISR" description="RAMCFG AXISRAM4 interrupt status register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM4ERKEYR" description="RAMCFG AXISRAM4 erase key register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM5CR" description="RAMCFG AXISRAM5 control register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM5ISR" description="RAMCFG AXISRAM5 interrupt status register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM5ERKEYR" description="RAMCFG AXISRAM5 erase key register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AXISRAM6CR" description="RAMCFG AXISRAM6 control register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMSD" description="Shutdown AXISRAMx" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAMx memory is powered." start="0x0" />
+        <Enum name="B_0x1" description="AXISRAMx memory is in shutdown, and its content is not retained." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM6ISR" description="RAMCFG AXISRAM6 interrupt status register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AXISRAM6ERKEYR" description="RAMCFG AXISRAM6 erase key register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1CR" description="RAMCFG AHBSRAM1 control register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1ISR" description="RAMCFG AHBSRAM1 interrupt status register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM1ERKEYR" description="RAMCFG AHBSRAM1 erase key register" start="+0x328" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2CR" description="RAMCFG AHBSRAM2 control register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2ISR" description="RAMCFG AHBSRAM2 interrupt status register" start="+0x388" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_AHBSRAM2ERKEYR" description="RAMCFG AHBSRAM2 erase key register" start="+0x3A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_VENCRAMCR" description="RAMCFG VENCRAM control register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_VENCRAMISR" description="RAMCFG VENCRAM interrupt status register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_VENCRAMERKEYR" description="RAMCFG VENCRAM erase key register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMCR" description="RAMCFG BKPSRAM control register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCE" description="ECC enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ECC disabled" start="0x0" />
+        <Enum name="B_0x1" description="ECC enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALE" description="Address latch enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Failing address not stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR" start="0x0" />
+        <Enum name="B_0x1" description="Failing address stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR" start="0x1" />
+      </BitField>
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMIER" description="RAMCFG BKPSRAM interrupt enable register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEIE" description="ECC single error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Single error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DEIE" description="ECC double error interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Double error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Double error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMISR" description="RAMCFG BKPSRAM interrupt status register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC" description="ECC single error detected" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No single error detected" start="0x0" />
+        <Enum name="B_0x1" description="Single error detected and corrected" start="0x1" />
+      </BitField>
+      <BitField name="DED" description="ECC double-error interrupt enable" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No double error" start="0x0" />
+        <Enum name="B_0x1" description="Double error detected" start="0x1" />
+      </BitField>
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_BKPSRAMESEAR" description="RAMCFG BKPSRAM single error address register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ESEA" description="ECC single error address" start="0" size="11" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMEDEAR" description="RAMCFG BKPSRAM double error address register" start="+0x490" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EDEA" description="ECC double error address" start="0" size="11" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMICR" description="RAMCFG BKPSRAM interrupt clear register" start="+0x494" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSED" description="Clear ECC single-error interrupt" start="0" size="1" access="WriteOnly" />
+      <BitField name="CDED" description="Clear ECC double-error interrupt" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMECCKEYR" description="RAMCFG BKPSRAM ECC key register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCKEY" description="ECC write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_BKPSRAMERKEYR" description="RAMCFG BKPSRAM erase key register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RAMCFG_FLEXRAMCR" description="RAMCFG FLEXRAM control register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMER" description="SRAM erase" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+      <BitField name="SRAMHWERDIS" description="SRAM hardware erase disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Erase operation done after a system reset" start="0x0" />
+        <Enum name="B_0x1" description="No erase operation done after a system reset, only for the retention part of the FLEXMEM when it is used as AXI RAM" start="0x1" />
+      </BitField>
+      <BitField name="ITCMCFG" description="Configuration of the FLEXMEM I-TCM extension" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXMEM I-TCM extension entirely allocated as AXI RAM" start="0x0" />
+        <Enum name="B_0x1" description="First 64 Kbytes (and corresponding ECC) allocated as I-TCM, remaining part allocated as AXI RAM" start="0x1" />
+        <Enum name="B_0x2" description="FLEXMEM I-TCM extension entirely allocated as AXI RAM" start="0x2" />
+      </BitField>
+      <BitField name="DTCMCFG" description="Configuration of the FLEXMEM D-TCM extension" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXMEM D-TCM extension allocated as AXI RAM" start="0x0" />
+        <Enum name="B_0x1" description="FLEXMEM D-TCM extension allocated as DTCM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_FLEXRAMISR" description="RAMCFG FLEXRAM interrupt status register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SRAMBUSY" description="SRAM busy with erase operation" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No erase operation ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Erase operation ongoing" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RAMCFG_FLEXRAMERKEYR" description="RAMCFG FLEXRAM erase key register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ERASEKEY" description="Erase write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RCC" description="Reset and clock control" start="0x46028000">
+    <Register name="RCC_CR" description="RCC control register" start="+0x0" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSION" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="LSEON" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="MSION" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSION" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI is OFF" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ON (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="HSEON" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL1ON" description="PLL1 enable in Run/Sleep mode." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL2ON" description="PLL2 enable in Run/Sleep mode." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL3ON" description="PLL3 enable in Run/Sleep mode." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL4ON" description="PLL4 enable in Run/Sleep mode." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 is ON" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SR" description="RCC status register" start="+0x4" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDY" description="LSI clock ready flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LSI is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ready" start="0x1" />
+      </BitField>
+      <BitField name="LSERDY" description="LSE clock ready flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LSE is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ready" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDY" description="MSI clock ready flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MSI is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ready" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDY" description="HSI clock ready flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="HSI is not ready" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ready (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="HSERDY" description="HSE clock ready flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="HSE is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE is ready" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDY" description="PLL1 clock ready flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL1 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDY" description="PLL2 clock ready flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL2 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDY" description="PLL3 clock ready flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL3 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDY" description="PLL4 clock ready flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL4 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_STOPCR" description="RCC Stop mode control register" start="+0x8" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISTOPEN" description="LSI oscillator enable in Stop mode." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="LSESTOPEN" description="LSE oscillator enable in Stop mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="MSISTOPEN" description="MSI oscillator enable in Stop mode." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSISTOPEN" description="HSI oscillator enable in Stop mode." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI is OFF" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ON (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CFGR1" description="RCC configuration register 1" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STOPWUCK" description="System clock selection after a wake up from system Stop." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI selected as wake up clock from system Stop (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI selected as wake up clock from system Stop" start="0x1" />
+      </BitField>
+      <BitField name="CPUSW" description="CPU clock switch selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic1_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="CPUSWS" description="CPU clock switch status" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic1_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="SYSSW" description="System clock switch selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic2_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="SYSSWS" description="System clock switch status" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic2_ck selected as system clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CFGR2" description="RCC configuration register 2" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPRE1" description="CPU domain APB1 prescaler" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk1 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk1 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE2" description="CPU domain APB2 prescaler" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk2 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk2 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE4" description="CPU domain APB4 prescaler" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk4 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk4 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE5" description="CPU domain APB5 prescaler" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk5 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk5 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="HPRE" description="AHB clock prescaler" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="sys_bus2_ck= sys_bus_ck" start="0x0" />
+        <Enum name="B_0x1" description="sys_bus2_ck = sys_bus_ck / 2 (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="sys_bus2_ck= sys_bus_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="sys_bus2_ck = sys_bus_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="sys_bus2_ck = sys_bus_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="sys_bus2_ck = sys_bus_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="sys_bus2_ck = sys_bus_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="sys_bus2_ck = sys_bus_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="TIMPRE" description="Timers clocks prescaler selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="timg_ck = sys_bus_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="timg_ck = sys_bus_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="timg_ck = sys_bus_ck / 4" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CKPROTR" description="RCC clock protection register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSPI3SELS" description="XSPI3 clock selection current status" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI3 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI3 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI3 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI3 clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI2SELS" description="XSPI2 clock selection current status" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI2 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI2 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI2 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI2 clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI1SELS" description="XSPI1 clock selection current status" start="24" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI1 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI1 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI1 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI1 clock" start="0x3" />
+      </BitField>
+      <BitField name="FMCSELS" description="FMC clock selection current status" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as FMC clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as FMC clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as FMC clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as FMC clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BDCR" description="RCC backup domain protection register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VSWRST" description="VSW domain software reset." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSW domain is not reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VSW domain is reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_HWRSR" description="RCC reset status register for hardware" start="+0x30" size="4" reset_value="0x00E00000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clear of the reset flags not activated (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="clear the value of the reset flags" start="0x1" />
+      </BitField>
+      <BitField name="LCKRSTF" description="CPU lockup reset flag." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No reset from CPU lockup occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from CPU lockup occurred" start="0x1" />
+      </BitField>
+      <BitField name="BORRSTF" description="BOR flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no BOR occurred" start="0x0" />
+        <Enum name="B_0x1" description="BOR occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset from pin occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from Pin occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PORRSTF" description="POR/PDR flag." start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no POR/PDR reset occurred" start="0x0" />
+        <Enum name="B_0x1" description="POR/PDR reset occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="SFTRSTF" description="Software system reset flag (1)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Software System reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="a Software System reset has been generated by the CPU" start="0x1" />
+      </BitField>
+      <BitField name="IWDGRSTF" description="Independent Watchdog reset flag." start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Independent Watchdog Reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Independent Watchdog Reset occurred" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRSTF" description="Window watchdog reset flag" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Window Watchdog Reset occurred from WWDG (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Window Watchdog Reset occurred from WWDG" start="0x1" />
+      </BitField>
+      <BitField name="LPWRRSTF" description="Illegal Stop or Standby flag." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no illegal reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="illegal Stop or Standby reset occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_RSR" description="RCC reset register" start="+0x34" size="4" reset_value="0x00E00000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clear of the reset flags not activated (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="clear the value of the reset flags" start="0x1" />
+      </BitField>
+      <BitField name="LCKRSTF" description="CPU lockup reset flag." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No reset from CPU lockup occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from CPU lockup occurred" start="0x1" />
+      </BitField>
+      <BitField name="BORRSTF" description="BOR flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no BOR occurred" start="0x0" />
+        <Enum name="B_0x1" description="BOR occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset from Pin occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from Pin occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PORRSTF" description="POR/PDR flag." start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no POR/PDR reset occurred" start="0x0" />
+        <Enum name="B_0x1" description="POR/PDR reset occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="SFTRSTF" description="Software System reset flag (1)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Software System reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="a Software System reset has been generated by the CPU" start="0x1" />
+      </BitField>
+      <BitField name="IWDGRSTF" description="Independent Watchdog reset flag." start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Independent Watchdog reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Independent Watchdog reset occurred" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRSTF" description="Window Watchdog reset flag" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Window Watchdog reset occurred from WWDG (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Window Watchdog reset occurred from WWDG" start="0x1" />
+      </BitField>
+      <BitField name="LPWRRSTF" description="Illegal Stop or Standby flag." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no illegal reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="illegal Stop or Standby reset occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LSECFGR" description="RCC LSE configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSECSSON" description="LSE clock security system (CSS) enable" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clock Security System on the LSE oscillator OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System on the LSE oscillator ON" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSRA" description="LSE clock security system (CSS) re-arm function" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 generates a re-arm pulse for the LSECSS function" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSD" description="LSE clock security system (CSS) failure detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No failure detected on the oscillator (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Failure detected on the oscillator" start="0x1" />
+      </BitField>
+      <BitField name="LSEBYP" description="LSE clock bypass" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE oscillator not bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE oscillator bypassed with an external clock" start="0x1" />
+      </BitField>
+      <BitField name="LSEEXT" description="LSE clock type in Bypass mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE in analog mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE in digital mode" start="0x1" />
+      </BitField>
+      <BitField name="LSEGFON" description="LSE clock glitch filter enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE clock glitch filter is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE clock glitch filter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSEDRV" description="LSE oscillator driving capability" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Lowest drive (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Medium low drive" start="0x1" />
+        <Enum name="B_0x2" description="Medium high drive" start="0x2" />
+        <Enum name="B_0x3" description="Highest drive" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MSICFGR" description="RCC MSI configuration register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSIFREQSEL" description="MSI oscillator frequency select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI oscillator frequency is 4 MHz (default after backup domain reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI oscillator frequency is 16 MHz" start="0x1" />
+      </BitField>
+      <BitField name="MSITRIM" description="MSI clock trimming" start="16" size="5" access="Read/Write" />
+      <BitField name="MSICAL" description="MSI clock calibration" start="23" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSICFGR" description="RCC HSI configuration register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIDIV" description="HSI clock divider" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck = hsi_osc_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="hsi_ck = hsi_osc_ck / 2" start="0x1" />
+      </BitField>
+      <BitField name="HSITRIM" description="HSI clock trimming" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x40" description="bsec_hsi_cal[8:0] - 64" start="0x40" />
+        <Enum name="B_0x41" description="bsec_hsi_cal[8:0] - 63" start="0x41" />
+        <Enum name="B_0x0" description="bsec_hsi_cal[8:0] (default after reset)" start="0x0" />
+        <Enum name="B_0x3E" description="bsec_hsi_cal[8:0] + 62" start="0x3E" />
+        <Enum name="B_0x3F" description="bsec_hsi_cal[8:0] + 63" start="0x3F" />
+      </BitField>
+      <BitField name="HSICAL" description="HSI clock calibration" start="23" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSIMCR" description="RCC HSI monitor control register" start="+0x4C" size="4" reset_value="0x001F07A1" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIREF" description="HSI clock cycle counter reference value." start="0" size="11" access="Read/Write" />
+      <BitField name="HSIDEV" description="HSI clock count deviation value" start="16" size="6" access="Read/Write" />
+      <BitField name="HSIMONEN" description="HSI clock period monitor enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing '0' disables the HSI clock period monitoring, reading '0' means that the HSI clock period monitoring is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Writing '1' enables the HSI clock period monitoring, reading '1' means that the HSI clock period monitoring is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_HSIMSR" description="RCC HSI monitor status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIVAL" description="HSI clock cycle counter measured value." start="0" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSECFGR" description="RCC HSE configuration register" start="+0x54" size="4" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
+      <BitField name="HSEDIV2BYP" description="HSE div2 oscillator clock in Bypass mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE: hse_div2_osc_ck = hse_osc_ck/2 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE: hse_div2_osc_ck = hse_osc_ck" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSON" description="HSE clock security system (CSS) enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="clock Security System on the HSE oscillator OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System on the HSE oscillator ON" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSRA" description="HSE clock security system (CSS) re-arm function" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 generates a re-arm pulse for the HSECSS function" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSD" description="HSE clock security system (CSS) failure detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No failure detected on the oscillator (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Failure detected on the oscillator" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSBYP" description="HSE clock security system (CSS) bypass enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="clock Security System Bypass of the HSE oscillator is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System Bypass on the HSE oscillator is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSBPRE" description="HSE clock security system (CSS) bypass divider" start="11" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="HSI clock is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="HSI clock is divided by 2 (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="HSI clock is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="HSI clock is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="HSI clock is divided by 15" start="0xF" />
+      </BitField>
+      <BitField name="HSEBYP" description="HSE clock bypass" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE oscillator not bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE oscillator bypassed with an external clock" start="0x1" />
+      </BitField>
+      <BitField name="HSEEXT" description="HSE clock type in Bypass mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE in analog mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE in digital mode" start="0x1" />
+      </BitField>
+      <BitField name="HSEGFON" description="HSE clock glitch filter enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE clock glitch filter is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE clock glitch filter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSEDRV" description="HSE oscillator driving capability" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Lowest drive (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Medium low drive" start="0x1" />
+        <Enum name="B_0x2" description="Medium high drive" start="0x2" />
+        <Enum name="B_0x3" description="Highest drive" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL1CFGR1" description="RCC PLL1 configuration register 1" start="+0x80" size="4" reset_value="0x08202500" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1DIVN" description="PLL1 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL1DIVM" description="PLL1 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL1BYP" description="PLL1 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1SEL" description="PLL1 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL1CFGR2" description="RCC PLL1 configuration register 2" start="+0x84" size="4" reset_value="0x00800000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1DIVNFRAC" description="PLL1 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL1CFGR3" description="RCC PLL1 configuration register 3" start="+0x88" size="4" reset_value="0x4900000D" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1MODSSRST" description="PLL1 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL1 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL1 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1DACEN" description="PLL1 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODSSDIS" description="PLL1 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODDSEN" description="PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODSPRDW" description="PLL1 Modulation Spread-Spectrum Down" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODDIV" description="PLL1 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL1MODSPR" description="PLL1 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL1PDIV2" description="PLL1 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL1PDIV1" description="PLL1 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL1PDIVEN" description="PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL2CFGR1" description="RCC PLL2 configuration register 1" start="+0x90" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2DIVN" description="PLL2 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL2DIVM" description="PLL2 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL2BYP" description="PLL2 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2SEL" description="PLL2 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL2CFGR2" description="RCC PLL2 configuration register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2DIVNFRAC" description="PLL2 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL2CFGR3" description="RCC PLL2 configuration register 3" start="+0x98" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2MODSSRST" description="PLL2 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL2 Modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL2 Modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2DACEN" description="PLL2 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODSSDIS" description="PLL2 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODDSEN" description="PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODSPRDW" description="PLL2 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODDIV" description="PLL2 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL2MODSPR" description="PLL2 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL2PDIV2" description="PLL2 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL2PDIV1" description="PLL2 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL2PDIVEN" description="PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL3CFGR1" description="RCC PLL3 configuration register 1" start="+0xA0" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3DIVN" description="PLL3 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL3DIVM" description="PLL3 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL3BYP" description="PLL3 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3SEL" description="PLL3 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL3CFGR2" description="RCC PLL3 configuration register 2" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3DIVNFRAC" description="PLL3 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL3CFGR3" description="RCC PLL3 configuration register 3" start="+0xA8" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3MODSSRST" description="PLL3 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL3 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL3 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3DACEN" description="PLL3 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODSSDIS" description="PLL3 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODDSEN" description="PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODSPRDW" description="PLL3 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODDIV" description="PLL3 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL3MODSPR" description="PLL3 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL3PDIV2" description="PLL3 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL3PDIV1" description="PLL3 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL3PDIVEN" description="PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL4CFGR1" description="RCC PLL4 configuration register 1" start="+0xB0" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4DIVN" description="PLL4 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL4DIVM" description="PLL4 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL4BYP" description="PLL4 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4SEL" description="PLL4 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL4CFGR2" description="RCC PLL4 configuration register 2" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4DIVNFRAC" description="PLL4 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL4CFGR3" description="RCC PLL4 configuration register 3" start="+0xB8" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4MODSSRST" description="PLL4 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL4 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL4 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4DACEN" description="PLL4 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODSSDIS" description="PLL4 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODDSEN" description="PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODSPRDW" description="PLL4 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODDIV" description="PLL4 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL4MODSPR" description="PLL4 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL4PDIV2" description="PLL4 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL4PDIV1" description="PLL4 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL4PDIVEN" description="PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC1CFGR" description="RCC IC1 configuration register" start="+0xC4" size="4" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1INT" description="Divider IC1 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC1 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC1 = pllx_ck / 3 (default after reset)" start="0x2" />
+        <Enum name="B_0x3" description="IC1 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC1 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC1SEL" description="Divider IC1 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC2CFGR" description="RCC IC2 configuration register" start="+0xC8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2INT" description="Divider IC2 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC2 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC2 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC2 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC2 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC2SEL" description="Divider IC2 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC3CFGR" description="RCC IC3 configuration register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC3INT" description="Divider IC3 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC3 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC3 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC3 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC3SEL" description="Divider IC3 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC4CFGR" description="RCC IC4 configuration register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4INT" description="Divider IC4 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC4 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC4 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC4 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC4SEL" description="Divider IC4 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC5CFGR" description="RCC IC5 configuration register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC5INT" description="Divider IC5 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC5 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC5 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC5 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC5SEL" description="Divider IC5 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC6CFGR" description="RCC IC6 configuration register" start="+0xD8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC6INT" description="Divider IC6 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC6 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC6 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC6 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC6 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC6SEL" description="Divider IC6 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC7CFGR" description="RCC IC7 configuration register" start="+0xDC" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC7INT" description="Divider IC7 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC7 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC7 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC7 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC7SEL" description="Divider IC7 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC8CFGR" description="RCC IC8 configuration register" start="+0xE0" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC8INT" description="Divider IC8 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC8 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC8 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC8 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC8SEL" description="Divider IC8 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC9CFGR" description="RCC IC9 configuration register" start="+0xE4" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC9INT" description="Divider IC9 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC9 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC9 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC9 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC9SEL" description="Divider IC9 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC10CFGR" description="RCC IC10 configuration register" start="+0xE8" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC10INT" description="Divider IC10 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC10 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC10 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC10 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC10SEL" description="Divider IC10 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC11CFGR" description="RCC IC11 configuration register" start="+0xEC" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC11INT" description="Divider IC11 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC11 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC11 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC11 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC11 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC11SEL" description="Divider IC11 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC12CFGR" description="RCC IC12 configuration register" start="+0xF0" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC12INT" description="Divider IC12 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC12 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC12 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC12 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC12SEL" description="Divider IC12 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC13CFGR" description="RCC IC13 configuration register" start="+0xF4" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC13INT" description="Divider IC13 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC13 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC13 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC13 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC13SEL" description="Divider IC13 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC14CFGR" description="RCC IC14 configuration register" start="+0xF8" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC14INT" description="Divider IC14 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC14 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC14 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC14 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC14SEL" description="Divider IC14 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC15CFGR" description="RCC IC15 configuration register" start="+0xFC" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC15INT" description="Divider IC15 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC15 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC15 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC15 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC15SEL" description="Divider IC15 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC16CFGR" description="RCC IC16 configuration register" start="+0x100" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC16INT" description="Divider IC16 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="IC16 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC16 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC16 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC16 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC16SEL" description="Divider IC16 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC17CFGR" description="RCC IC17 configuration register" start="+0x104" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC17INT" description="Divider IC17 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC17 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC17 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC17 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC17SEL" description="Divider IC17 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC18CFGR" description="RCC IC18 configuration register" start="+0x108" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC18INT" description="Divider IC18 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC18 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC18 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC18 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC18SEL" description="Divider IC18 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC19CFGR" description="RCC IC19 configuration register" start="+0x10C" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC19INT" description="Divider IC19 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC19 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC19 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC19 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC19SEL" description="Divider IC19 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC20CFGR" description="RCC IC20 configuration register" start="+0x110" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC20INT" description="Divider IC20 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC20 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC20 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC20 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC20SEL" description="Divider IC20 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CIER" description="RCC clock-source interrupt enable register" start="+0x124" size="4" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYIE" description="LSI ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYIE" description="LSE ready interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYIE" description="MSI ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYIE" description="HSI ready interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYIE" description="HSE ready interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYIE" description="PLL1 ready interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYIE" description="PLL2 ready interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYIE" description="PLL3 ready interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYIE" description="PLL4 ready interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSIE" description="LSE clock security system (CSS) interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE CSS interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE CSS interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSIE" description="HSE clock security system (CSS) interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE CSS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="HSE CSS interrupt enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPIE" description="CPU wakeup from Stop interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Wakeup interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CIFR" description="RCC clock-source interrupt flag register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYF" description="LSI ready interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSI" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYF" description="LSE ready interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSE" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYF" description="MSI ready interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the MSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the MSI" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYF" description="HSI ready interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSI" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYF" description="HSE ready interrupt flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSE" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYF" description="PLL1 ready interrupt flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL1 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL1" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYF" description="PLL2 ready interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL2 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL2" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYF" description="PLL3 ready interrupt flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL3 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL3" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYF" description="PLL4 ready interrupt flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL4 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL4" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSF" description="LSE ready interrupt flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSE" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSF" description="HSE ready interrupt flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSE" start="0x1" />
+      </BitField>
+      <BitField name="WKUPF" description="CPU wakeup from Stop interrupt flag" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no wakeup interrupt caused by the PWR (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="wakeup interrupt caused by the PWR" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CICR" description="RCC clock-source interrupt Clear register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYC" description="LSI ready interrupt clear" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYC" description="LSE ready interrupt clear" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSERDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSERDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYC" description="MSI ready interrupt clear" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYC" description="HSI ready interrupt clear" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYC" description="HSE ready interrupt clear" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSERDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSERDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYC" description="PLL1 ready interrupt clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL1RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYC" description="PLL2 ready interrupt clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL2RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYC" description="PLL3 ready interrupt clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL3RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYC" description="PLL4 ready interrupt clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL4RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSC" description="LSE ready interrupt clear" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSECSSF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSECSSF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSC" description="HSE ready interrupt clear" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSECSSF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSECSSF cleared" start="0x1" />
+      </BitField>
+      <BitField name="WKUPFC" description="CPU Wakeup ready interrupt clear" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="WKUPF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WKUPF cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR1" description="RCC clock configuration for independent peripheral register1" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADF1SEL" description="Source selection for the ADF1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="ADC12SEL" description="Source selection for the ADC12 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="ADCPRE" description="ADC12 Prog clock divider selection (for clock ck_icn_p_adf1)" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_adf1 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_adf1 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_adf1 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_adf1 is divided by 4" start="0x3" />
+      </BitField>
+      <BitField name="DCMIPPSEL" description="Source selection for the DCMIPP kernel clock" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic17_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR2" description="RCC clock configuration for independent peripheral register 2" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETH1PTPSEL" description="Source selection for the ETH1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclke selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic13_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="ETH1PTPDIV" description="ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp)" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_ker_eth1ptp is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_ker_eth1ptp is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_ker_eth1ptp is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_ker_eth1ptp is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_ker_eth1ptp is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="ETH1PWRDOWNACK" description="Set and reset by software." start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Power-down sequence start not yet acknowledged." start="0x0" />
+        <Enum name="B_0x1" description="Power-down sequence start acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="ETH1CLKSEL" description="Source selection for the ETH1 kernel clock" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclke selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic12_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="ETH1SEL" description="Set and reset by software" start="16" size="3" access="Read/Write" />
+      <BitField name="ETH1REFCLKSEL" description="Set and reset by software" start="20" size="1" access="Read/Write" />
+      <BitField name="ETH1GTXCLKSEL" description="Set and reset by software." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MII" start="0x0" />
+        <Enum name="B_0x1" description="RGMII" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR3" description="RCC clock configuration for independent peripheral register3" start="+0x14C" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="FDCANSEL" description="Source selection for the FDCAN kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic19_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="FMCSEL" description="Source selection for the FMC kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="DFTSEL" description="Source selection for the DFT kernel clock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="jtag_tck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pclk3 selected as reference clock" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR4" description="RCC clock configuration for independent peripheral register4" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2C1SEL" description="Source selection for the I2C1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C2SEL" description="Source selection for the I2C2 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C3SEL" description="Source selection for the I2C3 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C4SEL" description="Source selection for the I2C4 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I3C1SEL" description="Source selection for the I3C1 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I3C2SEL" description="Source selection for the I3C2 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LTDCSEL" description="Source selection for the LTDC kernel clock" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic16_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR5" description="RCC lock configuration for independent peripheral register5" start="+0x154" size="4" reset_value="0x0000F0F0" reset_mask="0xFFFFFFFF">
+      <BitField name="MCO1SEL" description="Source selection for the MCO1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_div_ck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="msi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lsi_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="hse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic5_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic10_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="sysa_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="MCO1PRE" description="MCO1 Prog clock divider selection (for clock ck_icn_p_mce3)" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_mce3 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_mce3 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_mce3 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_mce3 is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_icn_p_mce3 is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="MCO2SEL" description="Source selection for the MCO2 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_div_ck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="msi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lsi_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="hse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic15_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic20_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="sysb_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="MCO2PRE" description="MCO2 Prog clock divider selection (for clock ck_icn_p_mce4)" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_mce4 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_mce4 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_mce4 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_mce4 is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_icn_p_mce4 is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="MDF1SEL" description="Source selection for the MDF1 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR6" description="RCC clock configuration for independent peripheral register6" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSPI1SEL" description="Source selection for the XSPI1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI2SEL" description="Source selection for the XSPI2 kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI3SEL" description="Source selection for the XSPI3 kernel clock" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY1SEL" description="Source selection for the OTGPHY1 kernel clock" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hse_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_div2_osc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY1CKREFSEL" description="Set and reset by software" start="16" size="1" access="Read/Write" />
+      <BitField name="OTGPHY2SEL" description="Source selection for the OTGPHY2 kernel clock" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hse_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_div2_osc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY2CKREFSEL" description="Set and reset by software" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RCC_CCIPR7" description="RCC clock configuration for independent peripheral register7" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERSEL" description="Source selection for the PER kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic19_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="ic5_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic10_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic15_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="ic20_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="PSSISEL" description="Source selection for the PSSI kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic20_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="RTCSEL" description="Source selection for the RTC kernel clock" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="lsi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_rtc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="RTCPRE" description="RTC Prog clock divider selection (for clock ck_icn_p_risaf)" start="12" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_risaf is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_risaf is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_risaf is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_risaf is divided by 4" start="0x3" />
+        <Enum name="B_0x3F" description="ck_icn_p_risaf is divided by 64" start="0x3F" />
+      </BitField>
+      <BitField name="SAI1SEL" description="Source selection for the SAI1 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="spdif_symb_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="SAI2SEL" description="Source selection for the SAI2 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="spdif_symb_ck selected as reference clock" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR8" description="RCC clock configuration for independent peripheral register8" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC1SEL" description="Source selection for the SDMMC1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclku selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic4_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic5_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="SDMMC2SEL" description="Source selection for the SDMMC2 kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclku selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic4_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic5_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR9" description="RCC clock configuration for independent peripheral register9" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPDIFRX1SEL" description="Source selection for the SPDIFRX1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI1SEL" description="Source selection for the SPI1 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI2SEL" description="Source selection for the SPI2 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI3SEL" description="Source selection for the SPI3 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI4SEL" description="Source selection for the SPI4 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hse_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI5SEL" description="Source selection for the SPI5 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hse_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI6SEL" description="Source selection for the SPI6 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR12" description="RCC clock configuration for independent peripheral register12" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPTIM1SEL" description="Source selection for the LPTIM1 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM2SEL" description="Source selection for the LPTIM2 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM3SEL" description="Source selection for the LPTIM3 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM4SEL" description="Source selection for the LPTIM4 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM5SEL" description="Source selection for the LPTIM5 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR13" description="RCC clock configuration for independent peripheral register13" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USART1SEL" description="Source selection for the USART1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART2SEL" description="Source selection for the USART2 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART3SEL" description="Source selection for the USART3 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART4SEL" description="Source selection for the UART4 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART5SEL" description="Source selection for the UART5 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART6SEL" description="Source selection for the USART6 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART7SEL" description="Source selection for the UART7 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART8SEL" description="Source selection for the UART8 kernel clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR14" description="RCC clock configuration for independent peripheral register14" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UART9SEL" description="Source selection for the UART9 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART10SEL" description="Source selection for the USART10 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="LPUART1SEL" description="Source selection for the LPUART1 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSRSTR" description="RCC SoC buses reset register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRST" description="ACLKN reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBMRST" description="AHBM reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB1RST" description="AHB1 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB2RST" description="AHB2 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB3RST" description="AHB3 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB4RST" description="AHB4 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB5RST" description="AHB5 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB1RST" description="APB1 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB2RST" description="APB2 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB3RST" description="APB3 reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB4RST" description="APB4 reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB5RST" description="APB5 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NOCRST" description="NOC reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCRSTR" description="RCC miscellaneous configurations reset register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRST" description="DBG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHY1RST" description="XSPIPHY1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHY2RST" description="XSPIPHY2 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1DLLRST" description="SDMMC1DLL reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1DLL is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1DLL is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2DLLRST" description="SDMMC2DLL reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2DLL is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2DLL is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMRSTR" description="RCC memories reset register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RST" description="AXISRAM3 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4RST" description="AXISRAM4reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5RST" description="AXISRAM5 reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6RST" description="AXISRAM6 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1RST" description="AHBSRAM1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2RST" description="AHBSRAM2 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1RST" description="AXISRAM1 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2RST" description="AXISRAM2 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMRST" description="FLEXRAM reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMRST" description="NPUCACHERAM reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMRST" description="VENCRAM reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMRST" description="BOOTROM reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1RSTR" description="RCC AHB1 Reset register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RST" description="GPDMA1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ADC12RST" description="ADC12 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2RSTR" description="RCC AHB2 reset register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRST" description="RAMCFG reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="MDF1RST" description="MDF1 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ADF1RST" description="ADF1 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF1 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3RSTR" description="RCC AHB3 reset register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRST" description="RNG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="HASHRST" description="HASH reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CRYPRST" description="CRYP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAESRST" description="SAES reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PKARST" description="PKA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is under reset" start="0x1" />
+      </BitField>
+      <BitField name="IACRST" description="IAC reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IAC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4RSTR" description="RCC AHB4 reset register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARST" description="GPIOA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBRST" description="GPIOB reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCRST" description="GPIOC reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIODRST" description="GPIOD reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOERST" description="GPIOE reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFRST" description="GPIOF reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGRST" description="GPIOG reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHRST" description="GPIOH reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIONRST" description="GPION reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOORST" description="GPIOO reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPRST" description="GPIOP reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQRST" description="GPIOQ reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PWRRST" description="PWR reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PWR is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CRCRST" description="CRC reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5RSTR" description="RCC AHB5 reset register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RST" description="HPDMA1 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DRST" description="DMA2D reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is under reset" start="0x1" />
+      </BitField>
+      <BitField name="JPEGRST" description="JPEG reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FMCRST" description="FMC reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1RST" description="XSPI1 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PSSIRST" description="PSSI reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2RST" description="SDMMC2 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1RST" description="SDMMC1 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2RST" description="XSPI2 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMRST" description="XSPIM reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3RST" description="XSPI3 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="MCE4RST" description="MCE4 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMURST" description="GFXMMU reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPURST" description="GPU reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SYSCFGOTGHSPHY1RST" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFGOTGHSPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFGOTGHSPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SYSCFGOTGHSPHY2RST" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFGOTGHSPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFGOTGHSPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RST" description="ETH1 reset" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTG1RST" description="OTG1 reset" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1RST" description="OTGPHY1 reset" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2RST" description="OTGPHY2 reset" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTG2RST" description="OTG2 reset" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERST" description="NPUCACHE reset" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPURST" description="NPU reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LRSTR" description="RCC APB1L reset register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RST" description="TIM2 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM3RST" description="TIM3 reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM4RST" description="TIM4 reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM5RST" description="TIM5 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM6RST" description="TIM6 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM7RST" description="TIM7 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM12RST" description="TIM12 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM13RST" description="TIM13 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM14RST" description="TIM14 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1RST" description="LPTIM1 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRST" description="WWDG reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM10RST" description="TIM10 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM11RST" description="TIM11 reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI2RST" description="SPI2 reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI3RST" description="SPI3 reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1RST" description="SPDIFRX1 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART2RST" description="USART2 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART3RST" description="USART3 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART4RST" description="UART4 reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART5RST" description="UART5 reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C1RST" description="I2C1 reset" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C2RST" description="I2C2 reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C3RST" description="I2C3 reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I3C1RST" description="I3C1 reset" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I3C2RST" description="I3C2 reset" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART7RST" description="UART7 reset" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART8RST" description="UART8 reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HRSTR" description="RCC APB1H reset register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRST" description="MDIOS reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FDCANRST" description="FDCAN reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1RST" description="UCPD1 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2RSTR" description="RCC APB2 reset register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RST" description="TIM1 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM8RST" description="TIM8 reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART1RST" description="USART1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART6RST" description="USART6 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART9RST" description="UART9 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART10RST" description="USART10 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI1RST" description="SPI1 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI4RST" description="SPI4 reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM18RST" description="TIM18 reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM15RST" description="TIM15 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM16RST" description="TIM16 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM17RST" description="TIM17 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM9RST" description="TIM9 reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI5RST" description="SPI5 reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAI1RST" description="SAI1 reset" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAI2RST" description="SAI2 reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LRSTR" description="RCC APB4L reset register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRST" description="HDP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1RST" description="LPUART1 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI6RST" description="SPI6 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C4RST" description="I2C4 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2RST" description="LPTIM2 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3RST" description="LPTIM3 reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4RST" description="LPTIM4 reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5RST" description="LPTIM5 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFRST" description="VREFBUF reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is under reset" start="0x1" />
+      </BitField>
+      <BitField name="RTCRST" description="RTC reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETRST" description="R2GRET reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is under reset" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPURST" description="R2GNPU reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SERFRST" description="SERF reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HRSTR" description="RCC APB4H reset register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRST" description="SYSCFG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DTSRST" description="DTS reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is under reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMRST" description="BUSPERFM reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5RSTR" description="RCC APB5 reset register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRST" description="LTDC reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPRST" description="DCMIPP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMRST" description="GFXTIM reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VENCRST" description="VENC reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CSIRST" description="CSI reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_DIVENR" description="RCC IC dividers enable register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1EN" description="IC1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC2EN" description="IC2 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC3EN" description="IC3 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC4EN" description="IC4 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC5EN" description="IC5 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC6EN" description="IC6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC7EN" description="IC7 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC8EN" description="IC8 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC9EN" description="IC9 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC10EN" description="IC10 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC11EN" description="IC11 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC12EN" description="IC12 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC13EN" description="IC13 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC14EN" description="IC14 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC15EN" description="IC15 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC16EN" description="IC16 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC17EN" description="IC17 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC18EN" description="IC18 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC19EN" description="IC19 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC20EN" description="IC20 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSENR" description="RCC SoC buses enable register" start="+0x244" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNEN" description="ACLKN enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is disabled" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCEN" description="ACLKNC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBMEN" description="AHBM enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB1EN" description="AHB1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB2EN" description="AHB2 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB3EN" description="AHB3 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB4EN" description="AHB4 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB5EN" description="AHB5 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB1EN" description="APB1 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB2EN" description="APB2 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB3EN" description="APB3 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB4EN" description="APB4 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB5EN" description="APB5 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCENR" description="RCC miscellaneous configuration enable register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGEN" description="DBG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCO1EN" description="MCO1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCO1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCO1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCO2EN" description="MCO2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCO2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCO2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHYCOMPEN" description="XSPIPHYCOMP enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHYCOMP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHYCOMP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEREN" description="PER enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMENR" description="RCC memory enable register" start="+0x24C" size="4" reset_value="0x000013FF" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3EN" description="AXISRAM3 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4EN" description="AXISRAM4 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5EN" description="AXISRAM5 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6EN" description="AXISRAM6 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1EN" description="AHBSRAM1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2EN" description="AHBSRAM2 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMEN" description="BKPSRAM enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1EN" description="AXISRAM1 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2EN" description="AXISRAM2 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMEN" description="FLEXRAM enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMEN" description="NPUCACHERAM enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMEN" description="VENCRAM enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMEN" description="BOOTROM enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is enabled (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1ENR" description="RCC AHB1 enable register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1EN" description="GPDMA1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADC12EN" description="ADC12 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2ENR" description="RCC AHB2 enable register" start="+0x254" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGEN" description="RAMCFG enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MDF1EN" description="MDF1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADF1EN" description="ADF enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3ENR" description="RCC AHB3 enable register" start="+0x258" size="4" reset_value="0x00004600" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGEN" description="RNG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="HASHEN" description="HASH enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRYPEN" description="CRYP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAESEN" description="SAES enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PKAEN" description="PKA enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RIFSCEN" description="RIFSC enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RIFSC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="IACEN" description="IAC enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="IAC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="RISAFEN" description="RISAF enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RISAF is enabled (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4ENR" description="RCC AHB4 enable register" start="+0x25C" size="4" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAEN" description="GPIOA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBEN" description="GPIOB enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCEN" description="GPIOC enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIODEN" description="GPIOD enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOEEN" description="GPIOE enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFEN" description="GPIOF enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGEN" description="GPIOG enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHEN" description="GPIOH enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIONEN" description="GPION enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOOEN" description="GPIOO enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPEN" description="GPIOP enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQEN" description="GPIOQ enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PWREN" description="PWR enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is disabled" start="0x0" />
+        <Enum name="B_0x1" description="PWR is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="CRCEN" description="CRC enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5ENR" description="RCC AHB5 enable register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1EN" description="HPDMA1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DEN" description="DMA2D enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is enabled" start="0x1" />
+      </BitField>
+      <BitField name="JPEGEN" description="JPEG enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMCEN" description="FMC enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1EN" description="XSPI1 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PSSIEN" description="PSSI enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2EN" description="SDMMC2 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1EN" description="SDMMC1 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2EN" description="XSPI2 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMEN" description="XSPIM enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE1EN" description="MCE1 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE2EN" description="MCE2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE3EN" description="MCE3 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3EN" description="XSPI3 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE4EN" description="MCE4 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMUEN" description="GFXMMU enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPUEN" description="GPU enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1MACEN" description="ETH1MAC enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1MAC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1MAC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1TXEN" description="ETH1TX enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1TX is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1TX is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RXEN" description="ETH1RX enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1RX is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1RX is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1EN" description="ETH1 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTG1EN" description="OTG1 enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1EN" description="OTGPHY1 enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2EN" description="OTGPHY2 enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTG2EN" description="OTG2 enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHEEN" description="NPUCACHE enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is enabled" start="0x1" />
+      </BitField>
+      <BitField name="NPUEN" description="NPU enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LENR" description="RCC APB1L enable register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2EN" description="TIM2 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM3EN" description="TIM3 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM4EN" description="TIM4 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM5EN" description="TIM5 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM6EN" description="TIM6 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM7EN" description="TIM7 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM12EN" description="TIM12 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM13EN" description="TIM13 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM14EN" description="TIM14 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1EN" description="LPTIM1 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WWDGEN" description="WWDG enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM10EN" description="TIM10 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM11EN" description="TIM11 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI2EN" description="SPI2 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI3EN" description="SPI3 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1EN" description="SPDIFRX1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART2EN" description="USART2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART3EN" description="USART3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART4EN" description="UART4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART5EN" description="UART5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C1EN" description="I2C1 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C2EN" description="I2C2 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C3EN" description="I2C3 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I3C1EN" description="I3C1 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I3C2EN" description="I3C2 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART7EN" description="UART7 enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART8EN" description="UART8 enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HENR" description="RCC APB1H enable register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSEN" description="MDIOS enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDCANEN" description="FDCAN enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1EN" description="UCPD1 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2ENR" description="RCC APB2 enable register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1EN" description="TIM1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM8EN" description="TIM8 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART1EN" description="USART1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART6EN" description="USART6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART9EN" description="UART9 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART10EN" description="USART10 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI1EN" description="SPI1 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI4EN" description="SPI4 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM18EN" description="TIM18 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM15EN" description="TIM15 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM16EN" description="TIM16 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM17EN" description="TIM17 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM9EN" description="TIM9 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI5EN" description="SPI5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAI1EN" description="SAI1 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAI2EN" description="SAI2 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB3ENR" description="RCC APB3 enable register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTEN" description="DFT enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LENR" description="RCC APB4L enable register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPEN" description="HDP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1EN" description="LPUART1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI6EN" description="SPI6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C4EN" description="I2C4 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2EN" description="LPTIM2 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3EN" description="LPTIM3 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4EN" description="LPTIM4 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5EN" description="LPTIM5 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFEN" description="VREFBUF enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTCEN" description="RTC enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTCAPBEN" description="RTCAPB enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTCAPB is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTCAPB is enabled" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETEN" description="R2GRET enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is enabled" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPUEN" description="R2GNPU enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SERFEN" description="SERF enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HENR" description="RCC APB4H enable register" start="+0x278" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGEN" description="SYSCFG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BSECEN" description="BSEC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BSEC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="DTSEN" description="DTS enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMEN" description="BUSPERFM enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5ENR" description="RCC APB5 enable register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPEN" description="DCMIPP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMEN" description="GFXTIM enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VENCEN" description="VENC enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSIEN" description="CSI enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_DIVLPENR" description="RCC dividers Sleep enable register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPEN" description="IC1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC2LPEN" description="IC2 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC3LPEN" description="IC3 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC4LPEN" description="IC4 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC5LPEN" description="IC5 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC6LPEN" description="IC6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC7LPEN" description="IC7 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC8LPEN" description="IC8 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC9LPEN" description="IC9 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC10LPEN" description="IC10 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC11LPEN" description="IC11 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC12LPEN" description="IC12 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC13LPEN" description="IC13 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC14LPEN" description="IC14 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC15LPEN" description="IC15 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC16LPEN" description="IC16 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC17LPEN" description="IC17 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC18LPEN" description="IC18 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC19LPEN" description="IC19 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC20LPEN" description="IC20 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSLPENR" description="RCC SoC buses Sleep enable register" start="+0x284" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPEN" description="ACLKN sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCLPEN" description="ACLKNC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBMLPEN" description="AHBM sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB1LPEN" description="AHB1 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB2LPEN" description="AHB2 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB3LPEN" description="AHB3 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB4LPEN" description="AHB4 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB5LPEN" description="AHB5 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB1LPEN" description="APB1 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB2LPEN" description="APB2 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB3LPEN" description="APB3 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB4LPEN" description="APB4 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB5LPEN" description="APB5 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCLPENR" description="RCC miscellaneous configurations Sleep enable register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPEN" description="DBG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHYCOMPLPEN" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHYCOMP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHYCOMP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PERLPEN" description="PER sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMLPENR" description="RCC memory Sleep enable register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPEN" description="AXISRAM3 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4LPEN" description="AXISRAM4 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5LPEN" description="AXISRAM5 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6LPEN" description="AXISRAM6 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1LPEN" description="AHBSRAM1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2LPEN" description="AHBSRAM2 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMLPEN" description="BKPSRAM sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1LPEN" description="AXISRAM1 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2LPEN" description="AXISRAM2 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMLPEN" description="FLEXRAM sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMLPEN" description="NPUCACHERAM sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMLPEN" description="VENCRAM sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMLPEN" description="BOOTROM sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1LPENR" description="RCC AHB1 Sleep enable register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPEN" description="GPDMA1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ADC12LPEN" description="ADC12 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2LPENR" description="RCC AHB2 Sleep enable register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPEN" description="RAMCFG sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MDF1LPEN" description="MDF1 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ADF1LPEN" description="ADF1 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3LPENR" description="RCC AHB3 Sleep enable register" start="+0x298" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPEN" description="RNG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="HASHLPEN" description="HASH sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="CRYPLPEN" description="CRYP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAESLPEN" description="SAES sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PKALPEN" description="PKA sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RIFSCLPEN" description="RIFSC sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RIFSC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IACLPEN" description="IAC sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="IAC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="RISAFLPEN" description="RISAF sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RISAF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4LPENR" description="RCC AHB4 Sleep enable register" start="+0x29C" size="4" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPEN" description="GPIOA sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBLPEN" description="GPIOB sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCLPEN" description="GPIOC sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIODLPEN" description="GPIOD sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOELPEN" description="GPIOE sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFLPEN" description="GPIOF sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGLPEN" description="GPIOG sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHLPEN" description="GPIOH sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIONLPEN" description="GPION sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOOLPEN" description="GPIOO sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPLPEN" description="GPIOP sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQLPEN" description="GPIOQ sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PWRLPEN" description="PWR sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="PWR is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="CRCLPEN" description="CRC sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5LPENR" description="RCC AHB5 Sleep enable register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPEN" description="HPDMA1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DLPEN" description="DMA2D sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="JPEGLPEN" description="JPEG sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FMCLPEN" description="FMC sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1LPEN" description="XSPI1 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PSSILPEN" description="PSSI sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2LPEN" description="SDMMC2 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1LPEN" description="SDMMC1 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2LPEN" description="XSPI2 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMLPEN" description="XSPIM sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE1LPEN" description="MCE1 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE2LPEN" description="MCE2 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE3LPEN" description="MCE3 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3LPEN" description="XSPI3 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE4LPEN" description="MCE4 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMULPEN" description="GFXMMU sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPULPEN" description="GPU sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1MACLPEN" description="ETH1MAC sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1MAC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1MAC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1TXLPEN" description="ETH1TX sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1TX is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1TX is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RXLPEN" description="ETH1RX sleep enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1RX is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1RX is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1LPEN" description="ETH1 sleep enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTG1LPEN" description="OTG1 sleep enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1LPEN" description="OTGPHY1 sleep enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2LPEN" description="OTGPHY2 sleep enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTG2LPEN" description="OTG2 sleep enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHELPEN" description="NPUCACHE sleep enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPULPEN" description="NPU sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LLPENR" description="RCC APB1L Sleep enable register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPEN" description="TIM2 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM3LPEN" description="TIM3 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM4LPEN" description="TIM4 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM5LPEN" description="TIM5 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM6LPEN" description="TIM6 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM7LPEN" description="TIM7 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM12LPEN" description="TIM12 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM13LPEN" description="TIM13 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM14LPEN" description="TIM14 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1LPEN" description="LPTIM1 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="WWDGLPEN" description="WWDG sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM10LPEN" description="TIM10 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM11LPEN" description="TIM11 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI2LPEN" description="SPI2 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI3LPEN" description="SPI3 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1LPEN" description="SPDIFRX1 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART2LPEN" description="USART2 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART3LPEN" description="USART3 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART4LPEN" description="UART4 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART5LPEN" description="UART5 sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C1LPEN" description="I2C1 sleep enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C2LPEN" description="I2C2 sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C3LPEN" description="I2C3 sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I3C1LPEN" description="I3C1 sleep enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I3C2LPEN" description="I3C2 sleep enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART7LPEN" description="UART7 sleep enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART8LPEN" description="UART8 sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HLPENR" description="RCC APB1H Sleep enable register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPEN" description="MDIOS sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FDCANLPEN" description="FDCAN sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1LPEN" description="UCPD1 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2LPENR" description="RCC APB2 Sleep enable register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPEN" description="TIM1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM8LPEN" description="TIM8 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART1LPEN" description="USART1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART6LPEN" description="USART6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART9LPEN" description="UART9 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART10LPEN" description="USART10 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI1LPEN" description="SPI1 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI4LPEN" description="SPI4 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM18LPEN" description="TIM18 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM15LPEN" description="TIM15 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM16LPEN" description="TIM16 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM17LPEN" description="TIM17 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM9LPEN" description="TIM9 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI5LPEN" description="SPI5 sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAI1LPEN" description="SAI1 sleep enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAI2LPEN" description="SAI2 sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB3LPENR" description="RCC APB3 Sleep enable register" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPEN" description="DFT sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LLPENR" description="RCC APB4L Sleep enable register" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPEN" description="HDP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1LPEN" description="LPUART1 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI6LPEN" description="SPI6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C4LPEN" description="I2C4 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2LPEN" description="LPTIM2 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3LPEN" description="LPTIM3 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4LPEN" description="LPTIM4 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5LPEN" description="LPTIM5 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFLPEN" description="VREFBUF sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RTCLPEN" description="RTC sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RTCAPBLPEN" description="RTCAPB sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTCAPB is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTCAPB is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETLPEN" description="R2GRET sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPULPEN" description="R2GNPU sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SERFLPEN" description="SERF sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HLPENR" description="RCC APB4H Sleep enable register" start="+0x2B8" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPEN" description="SYSCFG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BSECLPEN" description="BSEC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BSEC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="DTSLPEN" description="DTS sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMLPEN" description="BUSPERFM sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5LPENR" description="RCC APB5 Sleep enable register" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPEN" description="LTDC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPLPEN" description="DCMIPP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMLPEN" description="GFXTIM sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VENCLPEN" description="VENC sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="CSILPEN" description="CSI sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_RDCR" description="RCC APB5 Sleep enable register" start="+0x44C" size="4" reset_value="0x00060000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRD" description="BOOTROM sleep enable" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="No extra delay added by the BOOTROM" start="0x0" />
+        <Enum name="B_0x1" description="100 us" start="0x1" />
+        <Enum name="B_0x2" description="200 us" start="0x2" />
+        <Enum name="B_0x3" description="500 us" start="0x3" />
+        <Enum name="B_0x4" description="1 ms" start="0x4" />
+        <Enum name="B_0x5" description="2 ms" start="0x5" />
+        <Enum name="B_0x6" description="5 ms (default after reset)" start="0x6" />
+        <Enum name="B_0x7" description="10 ms" start="0x7" />
+        <Enum name="B_0x8" description="20 ms" start="0x8" />
+        <Enum name="B_0x9" description="50 ms" start="0x9" />
+        <Enum name="B_0xA" description="100 ms" start="0xA" />
+        <Enum name="B_0xB" description="200 ms" start="0xB" />
+        <Enum name="B_0xC" description="500 ms" start="0xC" />
+        <Enum name="B_0xD" description="1 s" start="0xD" />
+        <Enum name="B_0xE" description="2 s" start="0xE" />
+        <Enum name="B_0xF" description="5 s" start="0xF" />
+      </BitField>
+      <BitField name="EADLY" description="BOOTROM sleep enable" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="sysrstn low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="The guaranteed sysrstn low pulse duration is about 1 ms (1 x 32 lsi_ck cycles)" start="0x1" />
+        <Enum name="B_0x2" description="The guaranteed sysrstn low pulse duration is about 2 ms (2 x 32 lsi_ck cycles)" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR0" description="RCC oscillator secure configuration register0" start="+0x780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISEC" description="Defines the secure protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="LSESEC" description="Defines the secure protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="MSISEC" description="Defines the secure protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="HSISEC" description="Defines the secure protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="HSESEC" description="Defines the secure protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR0" description="RCC oscillator privilege configuration register0" start="+0x784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPV" description="Defines the privilege protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="LSEPV" description="Defines the privilege protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="MSIPV" description="Defines the privilege protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="HSIPV" description="Defines the privilege protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="HSEPV" description="Defines the privilege protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR0" description="RCC oscillator lock configuration register0" start="+0x788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSILOCK" description="Defines the lock protection of the LSI oscillator configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="LSELOCK" description="Defines the lock protection of the LSE oscillator configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="MSILOCK" description="Defines the lock protection of the MSI oscillator configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="HSILOCK" description="Defines the lock protection of the HSI oscillator configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="HSELOCK" description="Defines the lock protection of the HSE oscillator configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR0" description="RCC oscillator public configuration register0" start="+0x78C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUB" description="Defines the public protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="LSEPUB" description="Defines the public protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="MSIPUB" description="Defines the public protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="HSIPUB" description="Defines the public protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="HSEPUB" description="Defines the public protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR1" description="RCC PLL secure configuration register1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1SEC" description="Defines the secure protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2SEC" description="Defines the secure protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3SEC" description="Defines the secure protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4SEC" description="Defines the secure protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR1" description="RCC PLL privilege configuration register1" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PV" description="Defines the privilege protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2PV" description="Defines the privilege protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3PV" description="Defines the privilege protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4PV" description="Defines the privilege protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR1" description="RCC PLL lock configuration register1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1LOCK" description="Defines the lock protection of the PLL1 PLL configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2LOCK" description="Defines the lock protection of the PLL2 PLL configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3LOCK" description="Defines the lock protection of the PLL3 PLL configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4LOCK" description="Defines the lock protection of the PLL4 PLL configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR1" description="RCC PLL public configuration register1" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUB" description="Defines the public protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2PUB" description="Defines the public protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3PUB" description="Defines the public protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4PUB" description="Defines the public protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR2" description="RCC divider secure configuration register2" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1SEC" description="Defines the secure protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2SEC" description="Defines the secure protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3SEC" description="Defines the secure protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4SEC" description="Defines the secure protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5SEC" description="Defines the secure protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6SEC" description="Defines the secure protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7SEC" description="Defines the secure protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8SEC" description="Defines the secure protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9SEC" description="Defines the secure protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10SEC" description="Defines the secure protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11SEC" description="Defines the secure protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12SEC" description="Defines the secure protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13SEC" description="Defines the secure protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14SEC" description="Defines the secure protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15SEC" description="Defines the secure protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16SEC" description="Defines the secure protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17SEC" description="Defines the secure protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18SEC" description="Defines the secure protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19SEC" description="Defines the secure protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20SEC" description="Defines the secure protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR2" description="RCC divider privilege configuration register2" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PV" description="Defines the privilege protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2PV" description="Defines the privilege protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3PV" description="Defines the privilege protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4PV" description="Defines the privilege protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5PV" description="Defines the privilege protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6PV" description="Defines the privilege protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7PV" description="Defines the privilege protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8PV" description="Defines the privilege protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9PV" description="Defines the privilege protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10PV" description="Defines the privilege protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11PV" description="Defines the privilege protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12PV" description="Defines the privilege protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13PV" description="Defines the privilege protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14PV" description="Defines the privilege protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15PV" description="Defines the privilege protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16PV" description="Defines the privilege protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17PV" description="Defines the privilege protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18PV" description="Defines the privilege protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19PV" description="Defines the privilege protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20PV" description="Defines the privilege protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR2" description="RCC divider lock configuration register2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LOCK" description="Defines the lock protection of the IC1 divider configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2LOCK" description="Defines the lock protection of the IC2 divider configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3LOCK" description="Defines the lock protection of the IC3 divider configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4LOCK" description="Defines the lock protection of the IC4 divider configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5LOCK" description="Defines the lock protection of the IC5 divider configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6LOCK" description="Defines the lock protection of the IC6 divider configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7LOCK" description="Defines the lock protection of the IC7 divider configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8LOCK" description="Defines the lock protection of the IC8 divider configuration bits." start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9LOCK" description="Defines the lock protection of the IC9 divider configuration bits." start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10LOCK" description="Defines the lock protection of the IC10 divider configuration bits." start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11LOCK" description="Defines the lock protection of the IC11 divider configuration bits." start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12LOCK" description="Defines the lock protection of the IC12 divider configuration bits." start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13LOCK" description="Defines the lock protection of the IC13 divider configuration bits." start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14LOCK" description="Defines the lock protection of the IC14 divider configuration bits." start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15LOCK" description="Defines the lock protection of the IC15 divider configuration bits." start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16LOCK" description="Defines the lock protection of the IC16 divider configuration bits." start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17LOCK" description="Defines the lock protection of the IC17 divider configuration bits." start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18LOCK" description="Defines the lock protection of the IC18 divider configuration bits." start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19LOCK" description="Defines the lock protection of the IC19 divider configuration bits." start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20LOCK" description="Defines the lock protection of the IC20 divider configuration bits." start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR2" description="RCC divider public configuration register2" start="+0x7AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUB" description="Defines the public protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2PUB" description="Defines the public protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3PUB" description="Defines the public protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4PUB" description="Defines the public protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5PUB" description="Defines the public protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6PUB" description="Defines the public protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7PUB" description="Defines the public protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8PUB" description="Defines the public protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9PUB" description="Defines the public protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10PUB" description="Defines the public protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11PUB" description="Defines the public protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12PUB" description="Defines the public protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13PUB" description="Defines the public protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14PUB" description="Defines the public protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15PUB" description="Defines the public protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16PUB" description="Defines the public protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17PUB" description="Defines the public protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18PUB" description="Defines the public protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19PUB" description="Defines the public protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20PUB" description="Defines the public protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR3" description="RCC system secure configuration register3" start="+0x7B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODSEC" description="Defines the secure protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSSEC" description="Defines the secure protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSSEC" description="Defines the secure protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PERSEC" description="Defines the secure protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="INTSEC" description="Defines the secure protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTSEC" description="Defines the secure protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTSEC" description="Defines the secure protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR3" description="RCC system privilege configuration register3" start="+0x7B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPV" description="Defines the privilege protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSPV" description="Defines the privilege protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSPV" description="Defines the privilege protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PERPV" description="Defines the privilege protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="INTPV" description="Defines the privilege protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTPV" description="Defines the privilege protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTPV" description="Defines the privilege protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR3" description="RCC system lock configuration register3" start="+0x7B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODLOCK" description="Defines the lock protection of the MOD system configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSLOCK" description="Defines the lock protection of the SYS system configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSLOCK" description="Defines the lock protection of the BUS system configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PERLOCK" description="Defines the lock protection of the PER system configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="INTLOCK" description="Defines the lock protection of the INT system configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTLOCK" description="Defines the lock protection of the RST system configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTLOCK" description="Defines the lock protection of the DFT system configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR3" description="RCC system public configuration register3" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUB" description="Defines the public protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSPUB" description="Defines the public protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSPUB" description="Defines the public protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PERPUB" description="Defines the public protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="INTPUB" description="Defines the public protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTPUB" description="Defines the public protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTPUB" description="Defines the public protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR4" description="RCC bus secure configuration register4" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNSEC" description="Defines the secure protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCSEC" description="Defines the secure protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMSEC" description="Defines the secure protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1SEC" description="Defines the secure protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2SEC" description="Defines the secure protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3SEC" description="Defines the secure protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4SEC" description="Defines the secure protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5SEC" description="Defines the secure protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1SEC" description="Defines the secure protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2SEC" description="Defines the secure protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3SEC" description="Defines the secure protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4SEC" description="Defines the secure protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5SEC" description="Defines the secure protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCSEC" description="Defines the secure protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR4" description="RCC bus privilege configuration register4" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPV" description="Defines the privilege protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCPV" description="Defines the privilege protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMPV" description="Defines the privilege protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1PV" description="Defines the privilege protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2PV" description="Defines the privilege protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3PV" description="Defines the privilege protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4PV" description="Defines the privilege protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5PV" description="Defines the privilege protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1PV" description="Defines the privilege protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2PV" description="Defines the privilege protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3PV" description="Defines the privilege protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4PV" description="Defines the privilege protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5PV" description="Defines the privilege protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCPV" description="Defines the privilege protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR4" description="RCC bus lock configuration register4" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLOCK" description="Defines the lock protection of the ACLKN bus configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCLOCK" description="Defines the lock protection of the ACLKNC bus configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMLOCK" description="Defines the lock protection of the AHBM bus configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1LOCK" description="Defines the lock protection of the AHB1 bus configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2LOCK" description="Defines the lock protection of the AHB2 bus configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3LOCK" description="Defines the lock protection of the AHB3 bus configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4LOCK" description="Defines the lock protection of the AHB4 bus configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5LOCK" description="Defines the lock protection of the AHB5 bus configuration bits." start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1LOCK" description="Defines the lock protection of the APB1 bus configuration bits." start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2LOCK" description="Defines the lock protection of the APB2 bus configuration bits." start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3LOCK" description="Defines the lock protection of the APB3 bus configuration bits." start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4LOCK" description="Defines the lock protection of the APB4 bus configuration bits." start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5LOCK" description="Defines the lock protection of the APB5 bus configuration bits." start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCLOCK" description="Defines the lock protection of the NOC bus configuration bits." start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR4" description="RCC bus public configuration register4" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUB" description="Defines the public protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCPUB" description="Defines the public protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMPUB" description="Defines the public protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1PUB" description="Defines the public protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2PUB" description="Defines the public protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3PUB" description="Defines the public protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4PUB" description="Defines the public protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5PUB" description="Defines the public protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1PUB" description="Defines the public protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2PUB" description="Defines the public protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3PUB" description="Defines the public protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4PUB" description="Defines the public protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5PUB" description="Defines the public protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCPUB" description="Defines the public protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR5" description="RCC bus public configuration register4" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUB" description="Defines the public protection of the AXISRAM3 bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4PUB" description="Defines the public protection of the AXISRAM4 bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5PUB" description="Defines the public protection of the AXISRAM5 bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6PUB" description="Defines the public protection of the AXISRAM6 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1PUB" description="Defines the public protection of the AHBSRAM1 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2PUB" description="Defines the public protection of the AHBSRAM2 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMPUB" description="Defines the public protection of the BKPSRAM bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1PUB" description="Defines the public protection of the AXISRAM1 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2PUB" description="Defines the public protection of the AXISRAM2 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMPUB" description="Defines the public protection of the FLEXRAM bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMPUB" description="Defines the public protection of the NPUCACHERAM bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMPUB" description="Defines the public protection of the VENCRAM bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CSR" description="RCC control set register" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIONS" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEONS" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIONS" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIONS" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEONS" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="WriteOnly" />
+      <BitField name="PLL1ONS" description="PLL1 oscillator enable in Run/Sleep mode." start="8" size="1" access="WriteOnly" />
+      <BitField name="PLL2ONS" description="PLL2 oscillator enable in Run/Sleep mode." start="9" size="1" access="WriteOnly" />
+      <BitField name="PLL3ONS" description="PLL3 oscillator enable in Run/Sleep mode." start="10" size="1" access="WriteOnly" />
+      <BitField name="PLL4ONS" description="PLL4 oscillator enable in Run/Sleep mode." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_STOPCSR" description="RCC Stop configuration register" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSISTOPENS" description="MSISTOPENS" start="0" size="1" access="WriteOnly" />
+      <BitField name="HSISTOPENS" description="HSISTOPENS" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSRSTSR" description="RCC bus reset set register" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRSTS" description="ACLKN reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AHBMRSTS" description="AHBM reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1RSTS" description="AHB1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2RSTS" description="AHB2 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3RSTS" description="AHB3 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4RSTS" description="AHB4 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5RSTS" description="AHB5 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1RSTS" description="APB1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2RSTS" description="APB2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3RSTS" description="APB3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4RSTS" description="APB4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5RSTS" description="APB5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCRSTS" description="NOC reset" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCRSTSR" description="RCC miscellaneous reset register" start="+0xA08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRSTS" description="DBG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY1RSTS" description="XSPIPHY1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY2RSTS" description="XSPIPHY2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1DLLRSTS" description="SDMMC1DLL reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2DLLRSTS" description="SDMMC2DLL reset" start="8" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMRSTSR" description="RCC memory reset register" start="+0xA0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RSTS" description="AXISRAM3 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4RSTS" description="AXISRAM4 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5RSTS" description="AXISRAM5 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6RSTS" description="AXISRAM6 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1RSTS" description="AHBSRAM1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2RSTS" description="AHBSRAM2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1RSTS" description="AXISRAM1 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2RSTS" description="AXISRAM2 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMRSTS" description="FLEXRAM reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMRSTS" description="NPUCACHERAM reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMRSTS" description="VENCRAM reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMRSTS" description="BOOTROM reset" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1RSTSR" description="RCC AHB1 reset register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RSTS" description="GPDMA1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12RSTS" description="ADC12 reset" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2RSTSR" description="RCC AHB2 reset register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRSTS" description="RAMCFG reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1RSTS" description="MDF1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1RSTS" description="ADF1 reset" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3RSTSR" description="RCC AHB3 reset register" start="+0xA18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRSTS" description="RNG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHRSTS" description="HASH reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPRSTS" description="CRYP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESRSTS" description="SAES reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKARSTS" description="PKA reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="IACRSTS" description="IAC reset" start="10" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4RSTSR" description="RCC AHB4 reset register" start="+0xA1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARSTS" description="GPIOA reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBRSTS" description="GPIOB reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCRSTS" description="GPIOC reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODRSTS" description="GPIOD reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOERSTS" description="GPIOE reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFRSTS" description="GPIOF reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGRSTS" description="GPIOG reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHRSTS" description="GPIOH reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONRSTS" description="GPION reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOORSTS" description="GPIOO reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPRSTS" description="GPIOP reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQRSTS" description="GPIOQ reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRRSTS" description="PWR reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCRSTS" description="CRC reset" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5RSTSR" description="RCC AHB5 reset register" start="+0xA20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RSTS" description="HPDMA1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DRSTS" description="DMA2D reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGRSTS" description="JPEG reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCRSTS" description="FMC reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1RSTS" description="XSPI1 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIRSTS" description="PSSI reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2RSTS" description="SDMMC2 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1RSTS" description="SDMMC1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2RSTS" description="XSPI2 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMRSTS" description="XSPIM reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="XSPI3RSTS" description="XSPI3 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4RSTS" description="MCE4 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMURSTS" description="GFXMMU reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPURSTS" description="GPU reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY1RSTS" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY2RSTS" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1RSTS" description="ETH1 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1RSTS" description="OTG1 reset" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1RSTS" description="OTGPHY1 reset" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2RSTS" description="OTGPHY2 reset" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2RSTS" description="OTG2 reset" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERSTS" description="NPUCACHE reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPURSTS" description="NPU reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LRSTSR" description="RCC APB1L reset register" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RSTS" description="TIM2 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3RSTS" description="TIM3 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4RSTS" description="TIM4 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5RSTS" description="TIM5 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6RSTS" description="TIM6 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7RSTS" description="TIM7 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12RSTS" description="TIM12 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13RSTS" description="TIM13 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14RSTS" description="TIM14 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1RSTS" description="LPTIM1 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGRSTS" description="WWDG reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10RSTS" description="TIM10 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11RSTS" description="TIM11 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2RSTS" description="SPI2 reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3RSTS" description="SPI3 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1RSTS" description="SPDIFRX1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2RSTS" description="USART2 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3RSTS" description="USART3 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4RSTS" description="UART4 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5RSTS" description="UART5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1RSTS" description="I2C1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2RSTS" description="I2C2 reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3RSTS" description="I2C3 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1RSTS" description="I3C1 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2RSTS" description="I3C2 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7RSTS" description="UART7 reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8RSTS" description="UART8 reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HRSTSR" description="RCC APB1H reset register" start="+0xA28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRSTS" description="MDIOS reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANRSTS" description="FDCAN reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1RSTS" description="UCPD1 reset" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2RSTSR" description="RCC APB2 reset register" start="+0xA2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RSTS" description="TIM1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8RSTS" description="TIM8 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1RSTS" description="USART1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6RSTS" description="USART6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9RSTS" description="UART9 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10RSTS" description="USART10 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1RSTS" description="SPI1 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4RSTS" description="SPI4 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18RSTS" description="TIM18 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15RSTS" description="TIM15 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16RSTS" description="TIM16 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17RSTS" description="TIM17 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9RSTS" description="TIM9 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5RSTS" description="SPI5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1RSTS" description="SAI1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2RSTS" description="SAI2 reset" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LRSTSR" description="RCC APB4L reset register" start="+0xA34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRSTS" description="HDP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1RSTS" description="LPUART1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6RSTS" description="SPI6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4RSTS" description="I2C4 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2RSTS" description="LPTIM2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3RSTS" description="LPTIM3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4RSTS" description="LPTIM4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5RSTS" description="LPTIM5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFRSTS" description="VREFBUF reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCRSTS" description="RTC reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="R2GRETRSTS" description="R2GRET reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPURSTS" description="R2GNPU reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFRSTS" description="SERF reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HRSTSR" description="RCC APB4H reset register" start="+0xA38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRSTS" description="SYSCFG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DTSRSTS" description="DTS reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMRSTS" description="BUSPERFM reset" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5RSTSR" description="RCC APB5 reset register" start="+0xA3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRSTS" description="LTDC reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPRSTS" description="DCMIPP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMRSTS" description="GFXTIM reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCRSTS" description="VENC reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIRSTS" description="CSI reset" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVENSR" description="RCC Divider enable register" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1ENS" description="IC1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2ENS" description="IC2 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3ENS" description="IC3 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4ENS" description="IC4 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5ENS" description="IC5 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6ENS" description="IC6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7ENS" description="IC7 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8ENS" description="IC8 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9ENS" description="IC9 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10ENS" description="IC10 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11ENS" description="IC11 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12ENS" description="IC12 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13ENS" description="IC13 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14ENS" description="IC14 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15ENS" description="IC15 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16ENS" description="IC16 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17ENS" description="IC17 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18ENS" description="IC18 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19ENS" description="IC19 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20ENS" description="IC20 enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSENSR" description="RCC bus enable register" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNENS" description="ACLKN enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCENS" description="ACLKNC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMENS" description="AHBM enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1ENS" description="AHB1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2ENS" description="AHB2 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3ENS" description="AHB3 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4ENS" description="AHB4 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5ENS" description="AHB5 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1ENS" description="APB1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2ENS" description="APB2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3ENS" description="APB3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4ENS" description="APB4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5ENS" description="APB5 enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCENSR" description="RCC miscellaneous enable register" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGENS" description="DBG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="MCO1ENS" description="MCO1 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="MCO2ENS" description="MCO2 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPENS" description="XSPIPHYCOMP enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERENS" description="PER enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMENSR" description="RCC memory enable register" start="+0xA4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3ENS" description="AXISRAM3 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4ENS" description="AXISRAM4 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5ENS" description="AXISRAM5 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6ENS" description="AXISRAM6 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1ENS" description="AHBSRAM1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2ENS" description="AHBSRAM2 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMENS" description="BKPSRAM enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1ENS" description="AXISRAM1 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2ENS" description="AXISRAM2 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMENS" description="FLEXRAM enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMENS" description="NPUCACHERAM enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMENS" description="VENCRAM enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMENS" description="BOOTROM enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1ENSR" description="RCC AHB1 enable register" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1ENS" description="GPDMA1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12ENS" description="ADC12 enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2ENSR" description="RCC AHB2 enable register" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGENS" description="RAMCFG enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1ENS" description="MDF1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1ENS" description="ADF1 enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3ENSR" description="RCC AHB3 enable register" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGENS" description="RNG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHENS" description="HASH enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPENS" description="CRYP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESENS" description="SAES enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKAENS" description="PKA enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCENS" description="RIFSC enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACENS" description="IAC enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFENS" description="RISAF enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4ENSR" description="RCC AHB4 enable register" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAENS" description="GPIOA enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBENS" description="GPIOB enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCENS" description="GPIOC enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODENS" description="GPIOD enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOEENS" description="GPIOE enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFENS" description="GPIOF enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGENS" description="GPIOG enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHENS" description="GPIOH enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONENS" description="GPION enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOENS" description="GPIOO enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPENS" description="GPIOP enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQENS" description="GPIOQ enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRENS" description="PWR enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCENS" description="CRC enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5ENSR" description="RCC AHB5 enable register" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1ENS" description="HPDMA1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DENS" description="DMA2D enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGENS" description="JPEG enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCENS" description="FMC enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1ENS" description="XSPI1 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIENS" description="PSSI enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2ENS" description="SDMMC2 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1ENS" description="SDMMC1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2ENS" description="XSPI2 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMENS" description="XSPIM enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1ENS" description="MCE1 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2ENS" description="MCE2 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3ENS" description="MCE3 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3ENS" description="XSPI3 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4ENS" description="MCE4 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMUENS" description="GFXMMU enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPUENS" description="GPU enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACENS" description="ETH1MAC enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXENS" description="ETH1TX enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXENS" description="ETH1RX enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1ENS" description="ETH1 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1ENS" description="OTG1 enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1ENS" description="OTGPHY1 enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2ENS" description="OTGPHY2 enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2ENS" description="OTG2 enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHEENS" description="NPUCACHE enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPUENS" description="NPU enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LENSR" description="RCC APB1L enable register" start="+0xA64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2ENS" description="TIM2 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3ENS" description="TIM3 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4ENS" description="TIM4 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5ENS" description="TIM5 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6ENS" description="TIM6 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7ENS" description="TIM7 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12ENS" description="TIM12 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13ENS" description="TIM13 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14ENS" description="TIM14 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1ENS" description="LPTIM1 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGENS" description="WWDG enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10ENS" description="TIM10 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11ENS" description="TIM11 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2ENS" description="SPI2 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3ENS" description="SPI3 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1ENS" description="SPDIFRX1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2ENS" description="USART2 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3ENS" description="USART3 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4ENS" description="UART4 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5ENS" description="UART5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1ENS" description="I2C1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2ENS" description="I2C2 enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3ENS" description="I2C3 enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1ENS" description="I3C1 enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2ENS" description="I3C2 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7ENS" description="UART7 enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8ENS" description="UART8 enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HENSR" description="RCC APB1H enable register" start="+0xA68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSENS" description="MDIOS enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANENS" description="FDCAN enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1ENS" description="UCPD1 enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2ENSR" description="RCC APB2 enable register" start="+0xA6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1ENS" description="TIM1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8ENS" description="TIM8 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1ENS" description="USART1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6ENS" description="USART6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9ENS" description="UART9 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10ENS" description="USART10 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1ENS" description="SPI1 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4ENS" description="SPI4 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18ENS" description="TIM18 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15ENS" description="TIM15 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16ENS" description="TIM16 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17ENS" description="TIM17 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9ENS" description="TIM9 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5ENS" description="SPI5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1ENS" description="SAI1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2ENS" description="SAI2 enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3ENSR" description="RCC APB3 enable register" start="+0xA70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTENS" description="DFT enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LENSR" description="RCC APB4L enable register" start="+0xA74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPENS" description="HDP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1ENS" description="LPUART1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6ENS" description="SPI6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4ENS" description="I2C4 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2ENS" description="LPTIM2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3ENS" description="LPTIM3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4ENS" description="LPTIM4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5ENS" description="LPTIM5 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFENS" description="VREFBUF enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCENS" description="RTC enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBENS" description="RTCAPB enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETENS" description="R2GRET enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPUENS" description="R2GNPU enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFENS" description="SERF enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HENSR" description="RCC APB4H enable register" start="+0xA78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGENS" description="SYSCFG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECENS" description="BSEC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSENS" description="DTS enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMENS" description="BUSPERFM enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5ENSR" description="RCC APB5 enable register" start="+0xA7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCENS" description="LTDC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPENS" description="DCMIPP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMENS" description="GFXTIM enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCENS" description="VENC enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIENS" description="CSI enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVLPENSR" description="RCC divider Sleep enable register" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPENS" description="IC1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2LPENS" description="IC2 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3LPENS" description="IC3 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4LPENS" description="IC4 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5LPENS" description="IC5 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6LPENS" description="IC6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7LPENS" description="IC7 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8LPENS" description="IC8 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9LPENS" description="IC9 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10LPENS" description="IC10 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11LPENS" description="IC11 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12LPENS" description="IC12 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13LPENS" description="IC13 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14LPENS" description="IC14 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15LPENS" description="IC15 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16LPENS" description="IC16 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17LPENS" description="IC17 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18LPENS" description="IC18 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19LPENS" description="IC19 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20LPENS" description="IC20 sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSLPENSR" description="RCC bus Sleep enable register" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPENS" description="ACLKN sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCLPENS" description="ACLKNC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMLPENS" description="AHBM sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1LPENS" description="AHB1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2LPENS" description="AHB2 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3LPENS" description="AHB3 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4LPENS" description="AHB4 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5LPENS" description="AHB5 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1LPENS" description="APB1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2LPENS" description="APB2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3LPENS" description="APB3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4LPENS" description="APB4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5LPENS" description="APB5 sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCLPENSR" description="RCC miscellaneous Sleep enable register" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPENS" description="DBG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPLPENS" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERLPENS" description="PER sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMLPENSR" description="RCC memory sleep enable register" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPENS" description="AXISRAM3 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4LPENS" description="AXISRAM4 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5LPENS" description="AXISRAM5 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6LPENS" description="AXISRAM6 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1LPENS" description="AHBSRAM1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2LPENS" description="AHBSRAM2 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMLPENS" description="BKPSRAM sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1LPENS" description="AXISRAM1 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2LPENS" description="AXISRAM2 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMLPENS" description="FLEXRAM sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMLPENS" description="NPUCACHERAM sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMLPENS" description="VENCRAM sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMLPENS" description="BOOTROM sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1LPENSR" description="RCC AHB1 Sleep enable register" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPENS" description="GPDMA1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12LPENS" description="ADC12 sleep enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2LPENSR" description="RCC AHB2 Sleep enable register" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPENS" description="RAMCFG sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1LPENS" description="MDF1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1LPENS" description="ADF1 sleep enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3LPENSR" description="RCC AHB3 Sleep enable register" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPENS" description="RNG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHLPENS" description="HASH sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPLPENS" description="CRYP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESLPENS" description="SAES sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKALPENS" description="PKA sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCLPENS" description="RIFSC sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACLPENS" description="IAC sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFLPENS" description="RISAF sleep enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4LPENSR" description="RCC AHB4 Sleep enable register" start="+0xA9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPENS" description="GPIOA sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBLPENS" description="GPIOB sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCLPENS" description="GPIOC sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODLPENS" description="GPIOD sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOELPENS" description="GPIOE sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFLPENS" description="GPIOF sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGLPENS" description="GPIOG sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHLPENS" description="GPIOH sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONLPENS" description="GPION sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOLPENS" description="GPIOO sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPLPENS" description="GPIOP sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQLPENS" description="GPIOQ sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRLPENS" description="PWR sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCLPENS" description="CRC sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5LPENSR" description="RCC AHB5 Sleep enable register" start="+0xAA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPENS" description="HPDMA1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DLPENS" description="DMA2D sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGLPENS" description="JPEG sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCLPENS" description="FMC sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1LPENS" description="XSPI1 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSILPENS" description="PSSI sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2LPENS" description="SDMMC2 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1LPENS" description="SDMMC1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2LPENS" description="XSPI2 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMLPENS" description="XSPIM sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1LPENS" description="MCE1 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2LPENS" description="MCE2 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3LPENS" description="MCE3 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3LPENS" description="XSPI3 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4LPENS" description="MCE4 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMULPENS" description="GFXMMU sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPULPENS" description="GPU sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACLPENS" description="ETH1MAC sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXLPENS" description="ETH1TX sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXLPENS" description="ETH1RX sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1LPENS" description="ETH1 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1LPENS" description="OTG1 sleep enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1LPENS" description="OTGPHY1 sleep enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2LPENS" description="OTGPHY2 sleep enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2LPENS" description="OTG2 sleep enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHELPENS" description="NPUCACHE sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPULPENS" description="NPU sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LLPENSR" description="RCC APB1L Sleep enable register" start="+0xAA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPENS" description="TIM2 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3LPENS" description="TIM3 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4LPENS" description="TIM4 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5LPENS" description="TIM5 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6LPENS" description="TIM6 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7LPENS" description="TIM7 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12LPENS" description="TIM12 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13LPENS" description="TIM13 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14LPENS" description="TIM14 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1LPENS" description="LPTIM1 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGLPENS" description="WWDG sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10LPENS" description="TIM10 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11LPENS" description="TIM11 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2LPENS" description="SPI2 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3LPENS" description="SPI3 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1LPENS" description="SPDIFRX1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2LPENS" description="USART2 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3LPENS" description="USART3 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4LPENS" description="UART4 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5LPENS" description="UART5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1LPENS" description="I2C1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2LPENS" description="I2C2 sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3LPENS" description="I2C3 sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1LPENS" description="I3C1 sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2LPENS" description="I3C2 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7LPENS" description="UART7 sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8LPENS" description="UART8 sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HLPENSR" description="RCC APB1H Sleep enable register" start="+0xAA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPENS" description="MDIOS sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANLPENS" description="FDCAN sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1LPENS" description="UCPD1 sleep enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2LPENSR" description="RCC APB2 Sleep enable register" start="+0xAAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPENS" description="TIM1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8LPENS" description="TIM8 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1LPENS" description="USART1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6LPENS" description="USART6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9LPENS" description="UART9 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10LPENS" description="USART10 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1LPENS" description="SPI1 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4LPENS" description="SPI4 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18LPENS" description="TIM18 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15LPENS" description="TIM15 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16LPENS" description="TIM16 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17LPENS" description="TIM17 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9LPENS" description="TIM9 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5LPENS" description="SPI5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1LPENS" description="SAI1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2LPENS" description="SAI2 sleep enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3LPENSR" description="RCC APB3 Sleep enable register" start="+0xAB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPENS" description="DFT sleep enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LLPENSR" description="RCC APB4L Sleep enable register" start="+0xAB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPENS" description="HDP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1LPENS" description="LPUART1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6LPENS" description="SPI6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4LPENS" description="I2C4 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2LPENS" description="LPTIM2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3LPENS" description="LPTIM3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4LPENS" description="LPTIM4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5LPENS" description="LPTIM5 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFLPENS" description="VREFBUF sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCLPENS" description="RTC sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBLPENS" description="RTCAPB sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETLPENS" description="R2GRET sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPULPENS" description="R2GNPU sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFLPENS" description="SERF sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HLPENSR" description="RCC APB4H Sleep enable register" start="+0xAB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPENS" description="SYSCFG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECLPENS" description="BSEC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSLPENS" description="DTS sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMLPENS" description="BUSPERFM sleep enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5LPENSR" description="RCC APB5 Sleep enable register" start="+0xABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPENS" description="LTDC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPLPENS" description="DCMIPP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMLPENS" description="GFXTIM sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCLPENS" description="VENC sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSILPENS" description="CSI sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR0" description="RCC oscillator privilege configuration register0" start="+0xF84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPVS" description="Defines the privilege protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPVS" description="Defines the privilege protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPVS" description="Defines the privilege protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPVS" description="Defines the privilege protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPVS" description="Defines the privilege protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR0" description="RCC oscillator public configuration register0" start="+0xF8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUBS" description="Defines the public protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPUBS" description="Defines the public protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPUBS" description="Defines the public protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPUBS" description="Defines the public protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPUBS" description="Defines the public protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR1" description="RCC PLL privilege configuration register1" start="+0xF94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PVS" description="Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PVS" description="Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PVS" description="Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PVS" description="Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR1" description="RCC PLL public configuration register1" start="+0xF9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUBS" description="Defines the public protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PUBS" description="Defines the public protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PUBS" description="Defines the public protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PUBS" description="Defines the public protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR2" description="RCC divider privilege configuration register2" start="+0xFA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PVS" description="Defines the privilege protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PVS" description="Defines the privilege protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PVS" description="Defines the privilege protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PVS" description="Defines the privilege protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PVS" description="Defines the privilege protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PVS" description="Defines the privilege protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PVS" description="Defines the privilege protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PVS" description="Defines the privilege protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PVS" description="Defines the privilege protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PVS" description="Defines the privilege protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PVS" description="Defines the privilege protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PVS" description="Defines the privilege protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PVS" description="Defines the privilege protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PVS" description="Defines the privilege protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PVS" description="Defines the privilege protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PVS" description="Defines the privilege protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PVS" description="Defines the privilege protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PVS" description="Defines the privilege protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PVS" description="Defines the privilege protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PVS" description="Defines the privilege protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR2" description="RCC divider public configuration register2" start="+0xFAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUBS" description="Defines the public protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PUBS" description="Defines the public protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PUBS" description="Defines the public protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PUBS" description="Defines the public protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PUBS" description="Defines the public protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PUBS" description="Defines the public protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PUBS" description="Defines the public protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PUBS" description="Defines the public protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PUBS" description="Defines the public protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PUBS" description="Defines the public protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PUBS" description="Defines the public protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PUBS" description="Defines the public protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PUBS" description="Defines the public protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PUBS" description="Defines the public protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PUBS" description="Defines the public protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PUBS" description="Defines the public protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PUBS" description="Defines the public protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PUBS" description="Defines the public protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PUBS" description="Defines the public protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PUBS" description="Defines the public protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_SECCFGSR3" description="RCC system secure configuration register3" start="+0xFB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODSECS" description="Defines the secure protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSSECS" description="Defines the secure protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSSECS" description="Defines the secure protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERSECS" description="Defines the secure protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTSECS" description="Defines the secure protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTSECS" description="Defines the secure protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTSECS" description="Defines the secure protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR3" description="RCC system privilege configuration register3" start="+0xFB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPVS" description="Defines the privilege protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPVS" description="Defines the privilege protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPVS" description="Defines the privilege protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPVS" description="Defines the privilege protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPVS" description="Defines the privilege protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPVS" description="Defines the privilege protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPVS" description="Defines the privilege protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_LOCKCFGSR3" description="RCC system lock configuration register3" start="+0xFB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODLOCKS" description="Defines the lock protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSLOCKS" description="Defines the lock protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSLOCKS" description="Defines the lock protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERLOCKS" description="Defines the lock protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTLOCKS" description="Defines the lock protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTLOCKS" description="Defines the lock protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTLOCKS" description="Defines the lock protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR3" description="RCC system public configuration register3" start="+0xFBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUBS" description="Defines the public protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPUBS" description="Defines the public protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPUBS" description="Defines the public protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPUBS" description="Defines the public protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPUBS" description="Defines the public protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPUBS" description="Defines the public protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPUBS" description="Defines the public protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR4" description="RCC privilege configuration register4" start="+0xFC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPVS" description="Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPVS" description="Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPVS" description="Defines the privilege protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PVS" description="Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PVS" description="Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PVS" description="Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PVS" description="Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PVS" description="Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PVS" description="Defines the privilege protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PVS" description="Defines the privilege protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PVS" description="Defines the privilege protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PVS" description="Defines the privilege protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PVS" description="Defines the privilege protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPVS" description="Defines the privilege protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR4" description="RCC public configuration register4" start="+0xFCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUBS" description="Defines the public protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPUBS" description="Defines the public protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPUBS" description="Defines the public protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PUBS" description="Defines the public protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PUBS" description="Defines the public protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PUBS" description="Defines the public protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PUBS" description="Defines the public protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PUBS" description="Defines the public protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PUBS" description="Defines the public protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PUBS" description="Defines the public protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PUBS" description="Defines the public protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PUBS" description="Defines the public protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PUBS" description="Defines the public protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPUBS" description="Defines the public protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR5" description="RCC public configuration register4" start="+0xFD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUBS" description="Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4PUBS" description="Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5PUBS" description="Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6PUBS" description="Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1PUBS" description="Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2PUBS" description="Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMPUBS" description="Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1PUBS" description="Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2PUBS" description="Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMPUBS" description="Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMPUBS" description="Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMPUBS" description="Defines the public protection of the VENCRAM configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_CCR" description="RCC control Clear register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIONC" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEONC" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIONC" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIONC" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEONC" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="WriteOnly" />
+      <BitField name="PLL1ONC" description="PLL1 oscillator enable in Run/Sleep mode." start="8" size="1" access="WriteOnly" />
+      <BitField name="PLL2ONC" description="PLL2 oscillator enable in Run/Sleep mode." start="9" size="1" access="WriteOnly" />
+      <BitField name="PLL3ONC" description="PLL3 oscillator enable in Run/Sleep mode." start="10" size="1" access="WriteOnly" />
+      <BitField name="PLL4ONC" description="PLL4 oscillator enable in Run/Sleep mode." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_STOPCCR" description="RCC StopCCR configuration register" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISTOPENC" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSESTOPENC" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSISTOPENC" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSISTOPENC" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSRSTCR" description="RCC bus reset register" start="+0x1204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRSTC" description="ACLKN reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AHBMRSTC" description="AHBM reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1RSTC" description="AHB1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2RSTC" description="AHB2 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3RSTC" description="AHB3 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4RSTC" description="AHB4 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5RSTC" description="AHB5 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1RSTC" description="APB1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2RSTC" description="APB2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3RSTC" description="APB3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4RSTC" description="APB4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5RSTC" description="APB5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCRSTC" description="NOC reset" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCRSTCR" description="RCC miscellaneous reset register" start="+0x1208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRSTC" description="DBG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY1RSTC" description="XSPIPHY1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY2RSTC" description="XSPIPHY2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1DLLRSTC" description="SDMMC1DLL reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2DLLRSTC" description="SDMMC2DLL reset" start="8" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMRSTCR" description="RCC memory reset register" start="+0x120C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RSTC" description="AXISRAM3 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4RSTC" description="AXISRAM4 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5RSTC" description="AXISRAM5 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6RSTC" description="AXISRAM6 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1RSTC" description="AHBSRAM1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2RSTC" description="AHBSRAM2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1RSTC" description="AXISRAM1 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2RSTC" description="AXISRAM2 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMRSTC" description="FLEXRAM reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMRSTC" description="NPUCACHERAM reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMRSTC" description="VENCRAM reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMRSTC" description="BOOTROM reset" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1RSTCR" description="RCC AHB1 reset register" start="+0x1210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RSTC" description="GPDMA1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12RSTC" description="ADC12 reset" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2RSTCR" description="RCC AHB2 Reset register" start="+0x1214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRSTC" description="RAMCFG reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1RSTC" description="MDF1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1RSTC" description="ADF1 reset" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3RSTCR" description="RCC AHB3 reset register" start="+0x1218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRSTC" description="RNG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHRSTC" description="HASH reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPRSTC" description="CRYP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESRSTC" description="SAES reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKARSTC" description="PKA reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="IACRSTC" description="IAC reset" start="10" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4RSTCR" description="RCC AHB4 reset register" start="+0x121C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARSTC" description="GPIOA reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBRSTC" description="GPIOB reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCRSTC" description="GPIOC reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODRSTC" description="GPIOD reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOERSTC" description="GPIOE reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFRSTC" description="GPIOF reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGRSTC" description="GPIOG reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHRSTC" description="GPIOH reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONRSTC" description="GPION reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOORSTC" description="GPIOO reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPRSTC" description="GPIOP reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQRSTC" description="GPIOQ reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRRSTC" description="PWR reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCRSTC" description="CRC reset" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5RSTCR" description="RCC AHB5 reset register" start="+0x1220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RSTC" description="HPDMA1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DRSTC" description="DMA2D reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGRSTC" description="JPEG reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCRSTC" description="FMC reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1RSTC" description="XSPI1 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIRSTC" description="PSSI reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2RSTC" description="SDMMC2 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1RSTC" description="SDMMC1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2RSTC" description="XSPI2 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMRSTC" description="XSPIM reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="XSPI3RSTC" description="XSPI3 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4RSTC" description="MCE4 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMURSTC" description="GFXMMU reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPURSTC" description="GPU reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY1RSTC" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY2RSTC" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1RSTC" description="ETH1 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1RSTC" description="OTG1 reset" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1RSTC" description="OTGPHY1 reset" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2RSTC" description="OTGPHY2 reset" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2RSTC" description="OTG2 reset" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERSTC" description="NPUCACHE reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPURSTC" description="NPU reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LRSTCR" description="RCC APB1L reset register" start="+0x1224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RSTC" description="TIM2 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3RSTC" description="TIM3 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4RSTC" description="TIM4 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5RSTC" description="TIM5 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6RSTC" description="TIM6 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7RSTC" description="TIM7 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12RSTC" description="TIM12 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13RSTC" description="TIM13 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14RSTC" description="TIM14 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1RSTC" description="LPTIM1 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGRSTC" description="WWDG reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10RSTC" description="TIM10 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11RSTC" description="TIM11 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2RSTC" description="SPI2 reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3RSTC" description="SPI3 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1RSTC" description="SPDIFRX1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2RSTC" description="USART2 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3RSTC" description="USART3 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4RSTC" description="UART4 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5RSTC" description="UART5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1RSTC" description="I2C1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2RSTC" description="I2C2 reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3RSTC" description="I2C3 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1RSTC" description="I3C1 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2RSTC" description="I3C2 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7RSTC" description="UART7 reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8RSTC" description="UART8 reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HRSTCR" description="RCC APB1H reset register" start="+0x1228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRSTC" description="MDIOS reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANRSTC" description="FDCAN reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1RSTC" description="UCPD1 reset" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2RSTCR" description="RCC APB2 reset register" start="+0x122C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RSTC" description="TIM1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8RSTC" description="TIM8 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1RSTC" description="USART1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6RSTC" description="USART6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9RSTC" description="UART9 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10RSTC" description="USART10 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1RSTC" description="SPI1 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4RSTC" description="SPI4 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18RSTC" description="TIM18 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15RSTC" description="TIM15 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16RSTC" description="TIM16 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17RSTC" description="TIM17 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9RSTC" description="TIM9 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5RSTC" description="SPI5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1RSTC" description="SAI1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2RSTC" description="SAI2 reset" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LRSTCR" description="RCC APB4L reset register" start="+0x1234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRSTC" description="HDP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1RSTC" description="LPUART1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6RSTC" description="SPI6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4RSTC" description="I2C4 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2RSTC" description="LPTIM2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3RSTC" description="LPTIM3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4RSTC" description="LPTIM4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5RSTC" description="LPTIM5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFRSTC" description="VREFBUF reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCRSTC" description="RTC reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="R2GRETRSTC" description="R2GRET reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPURSTC" description="R2GNPU reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFRSTC" description="SERF reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HRSTCR" description="RCC APB4H reset register" start="+0x1238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRSTC" description="SYSCFG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DTSRSTC" description="DTS reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMRSTC" description="BUSPERFM reset" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5RSTCR" description="RCC APB5 reset register" start="+0x123C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRSTC" description="LTDC reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPRSTC" description="DCMIPP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMRSTC" description="GFXTIM reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCRSTC" description="VENC reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIRSTC" description="CSI reset" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVENCR" description="RCC divider enable register" start="+0x1240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1ENC" description="IC1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2ENC" description="IC2 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3ENC" description="IC3 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4ENC" description="IC4 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5ENC" description="IC5 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6ENC" description="IC6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7ENC" description="IC7 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8ENC" description="IC8 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9ENC" description="IC9 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10ENC" description="IC10 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11ENC" description="IC11 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12ENC" description="IC12 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13ENC" description="IC13 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14ENC" description="IC14 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15ENC" description="IC15 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16ENC" description="IC16 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17ENC" description="IC17 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18ENC" description="IC18 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19ENC" description="IC19 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20ENC" description="IC20 enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSENCR" description="RCC bus enable register" start="+0x1244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNENC" description="ACLKN enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCENC" description="ACLKNC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMENC" description="AHBM enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1ENC" description="AHB1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2ENC" description="AHB2 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3ENC" description="AHB3 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4ENC" description="AHB4 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5ENC" description="AHB5 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1ENC" description="APB1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2ENC" description="APB2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3ENC" description="APB3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4ENC" description="APB4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5ENC" description="APB5 enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCENCR" description="RCC miscellaneous enable register" start="+0x1248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGENC" description="DBG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="MCO1ENC" description="MCO1 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="MCO2ENC" description="MCO2 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPENC" description="XSPIPHYCOMP enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERENC" description="PER enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMENCR" description="RCC memory enable register" start="+0x124C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3ENC" description="AXISRAM3 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4ENC" description="AXISRAM4 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5ENC" description="AXISRAM5 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6ENC" description="AXISRAM6 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1ENC" description="AHBSRAM1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2ENC" description="AHBSRAM2 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMENC" description="BKPSRAM enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1ENC" description="AXISRAM1 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2ENC" description="AXISRAM2 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMENC" description="FLEXRAM enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMENC" description="NPUCACHERAM enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMENC" description="VENCRAM enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMENC" description="BOOTROM enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1ENCR" description="RCC AHB1 enable register" start="+0x1250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1ENC" description="GPDMA1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12ENC" description="ADC12 enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2ENCR" description="RCC AHB2 enable register" start="+0x1254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGENC" description="RAMCFG enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1ENC" description="MDF1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1ENC" description="ADF1 enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3ENCR" description="RCC AHB3 enable register" start="+0x1258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGENC" description="RNG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHENC" description="HASH enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPENC" description="CRYP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESENC" description="SAES enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKAENC" description="PKA enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCENC" description="RIFSC enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACENC" description="IAC enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFENC" description="RISAF enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4ENCR" description="RCC AHB4 enable register" start="+0x125C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAENC" description="GPIOA enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBENC" description="GPIOB enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCENC" description="GPIOC enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODENC" description="GPIOD enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOEENC" description="GPIOE enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFENC" description="GPIOF enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGENC" description="GPIOG enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHENC" description="GPIOH enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONENC" description="GPION enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOENC" description="GPIOO enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPENC" description="GPIOP enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQENC" description="GPIOQ enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRENC" description="PWR enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCENC" description="CRC enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5ENCR" description="RCC AHB5 enable register" start="+0x1260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1ENC" description="HPDMA1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DENC" description="DMA2D enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGENC" description="JPEG enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCENC" description="FMC enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1ENC" description="XSPI1 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIENC" description="PSSI enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2ENC" description="SDMMC2 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1ENC" description="SDMMC1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2ENC" description="XSPI2 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMENC" description="XSPIM enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1ENC" description="MCE1 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2ENC" description="MCE2 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3ENC" description="MCE3 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3ENC" description="XSPI3 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4ENC" description="MCE4 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMUENC" description="GFXMMU enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPUENC" description="GPU enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACENC" description="ETH1MAC enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXENC" description="ETH1TX enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXENC" description="ETH1RX enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1ENC" description="ETH1 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1ENC" description="OTG1 enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1ENC" description="OTGPHY1 enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2ENC" description="OTGPHY2 enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2ENC" description="OTG2 enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHEENC" description="NPUCACHE enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPUENC" description="NPU enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LENCR" description="RCC APB1L enable register" start="+0x1264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2ENC" description="TIM2 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3ENC" description="TIM3 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4ENC" description="TIM4 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5ENC" description="TIM5 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6ENC" description="TIM6 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7ENC" description="TIM7 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12ENC" description="TIM12 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13ENC" description="TIM13 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14ENC" description="TIM14 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1ENC" description="LPTIM1 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="TIM10ENC" description="TIM10 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11ENC" description="TIM11 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2ENC" description="SPI2 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3ENC" description="SPI3 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1ENC" description="SPDIFRX1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2ENC" description="USART2 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3ENC" description="USART3 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4ENC" description="UART4 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5ENC" description="UART5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1ENC" description="I2C1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2ENC" description="I2C2 enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3ENC" description="I2C3 enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1ENC" description="I3C1 enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2ENC" description="I3C2 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7ENC" description="UART7 enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8ENC" description="UART8 enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HENCR" description="RCC APB1H enable register" start="+0x1268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSENC" description="MDIOS enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANENC" description="FDCAN enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1ENC" description="UCPD1 enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2ENCR" description="RCC APB2 enable register" start="+0x126C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1ENC" description="TIM1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8ENC" description="TIM8 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1ENC" description="USART1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6ENC" description="USART6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9ENC" description="UART9 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10ENC" description="USART10 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1ENC" description="SPI1 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4ENC" description="SPI4 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18ENC" description="TIM18 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15ENC" description="TIM15 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16ENC" description="TIM16 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17ENC" description="TIM17 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9ENC" description="TIM9 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5ENC" description="SPI5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1ENC" description="SAI1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2ENC" description="SAI2 enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3ENCR" description="RCC APB3 enable register" start="+0x1270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTENC" description="DFT enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LENCR" description="RCC APB4L enable register" start="+0x1274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPENC" description="HDP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1ENC" description="LPUART1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6ENC" description="SPI6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4ENC" description="I2C4 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2ENC" description="LPTIM2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3ENC" description="LPTIM3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4ENC" description="LPTIM4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5ENC" description="LPTIM5 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFENC" description="VREFBUF enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCENC" description="RTC enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBENC" description="RTCAPB enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETENC" description="R2GRET enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPUENC" description="R2GNPU enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFENC" description="SERF enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HENCR" description="RCC APB4H enable register" start="+0x1278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGENC" description="SYSCFG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECENC" description="BSEC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSENC" description="DTS enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMENC" description="BUSPERFM enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5ENCR" description="RCC APB5 enable register" start="+0x127C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCENC" description="LTDC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPENC" description="DCMIPP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMENC" description="GFXTIM enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCENC" description="VENC enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIENC" description="CSI enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVLPENCR" description="RCC divider Sleep enable register" start="+0x1280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPENC" description="IC1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2LPENC" description="IC2 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3LPENC" description="IC3 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4LPENC" description="IC4 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5LPENC" description="IC5 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6LPENC" description="IC6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7LPENC" description="IC7 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8LPENC" description="IC8 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9LPENC" description="IC9 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10LPENC" description="IC10 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11LPENC" description="IC11 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12LPENC" description="IC12 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13LPENC" description="IC13 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14LPENC" description="IC14 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15LPENC" description="IC15 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16LPENC" description="IC16 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17LPENC" description="IC17 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18LPENC" description="IC18 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19LPENC" description="IC19 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20LPENC" description="IC20 sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSLPENCR" description="RCC bus Sleep enable register" start="+0x1284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPENC" description="ACLKN sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCLPENC" description="ACLKNC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMLPENC" description="AHBM sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1LPENC" description="AHB1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2LPENC" description="AHB2 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3LPENC" description="AHB3 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4LPENC" description="AHB4 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5LPENC" description="AHB5 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1LPENC" description="APB1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2LPENC" description="APB2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3LPENC" description="APB3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4LPENC" description="APB4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5LPENC" description="APB5 sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCLPENCR" description="RCC miscellaneous Sleep enable register" start="+0x1288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPENC" description="DBG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPLPENC" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERLPENC" description="PER sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMLPENCR" description="RCC memory Sleep enable register" start="+0x128C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPENC" description="AXISRAM3 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4LPENC" description="AXISRAM4 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5LPENC" description="AXISRAM5 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6LPENC" description="AXISRAM6 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1LPENC" description="AHBSRAM1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2LPENC" description="AHBSRAM2 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMLPENC" description="BKPSRAM sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1LPENC" description="AXISRAM1 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2LPENC" description="AXISRAM2 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMLPENC" description="FLEXRAM sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMLPENC" description="NPUCACHERAM sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMLPENC" description="VENCRAM sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMLPENC" description="BOOTROM sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1LPENCR" description="RCC AHB1 Sleep enable register" start="+0x1290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPENC" description="GPDMA1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12LPENC" description="ADC12 sleep enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2LPENCR" description="RCC AHB2 Sleep enable register" start="+0x1294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPENC" description="RAMCFG sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1LPENC" description="MDF1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1LPENC" description="ADF1 sleep enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3LPENCR" description="RCC AHB3 Sleep enable register" start="+0x1298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPENC" description="RNG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHLPENC" description="HASH sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPLPENC" description="CRYP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESLPENC" description="SAES sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKALPENC" description="PKA sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCLPENC" description="RIFSC sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACLPENC" description="IAC sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFLPENC" description="RISAF sleep enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4LPENCR" description="RCC AHB4 Sleep enable register" start="+0x129C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPENC" description="GPIOA sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBLPENC" description="GPIOB sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCLPENC" description="GPIOC sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODLPENC" description="GPIOD sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOELPENC" description="GPIOE sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFLPENC" description="GPIOF sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGLPENC" description="GPIOG sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHLPENC" description="GPIOH sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONLPENC" description="GPION sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOLPENC" description="GPIOO sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPLPENC" description="GPIOP sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQLPENC" description="GPIOQ sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRLPENC" description="PWR sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCLPENC" description="CRC sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5LPENCR" description="RCC AHB5 Sleep enable register" start="+0x12A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPENC" description="HPDMA1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DLPENC" description="DMA2D sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGLPENC" description="JPEG sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCLPENC" description="FMC sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1LPENC" description="XSPI1 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSILPENC" description="PSSI sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2LPENC" description="SDMMC2 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1LPENC" description="SDMMC1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2LPENC" description="XSPI2 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMLPENC" description="XSPIM sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1LPENC" description="MCE1 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2LPENC" description="MCE2 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3LPENC" description="MCE3 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3LPENC" description="XSPI3 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4LPENC" description="MCE4 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMULPENC" description="GFXMMU sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPULPENC" description="GPU sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACLPENC" description="ETH1MAC sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXLPENC" description="ETH1TX sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXLPENC" description="ETH1RX sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1LPENC" description="ETH1 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1LPENC" description="OTG1 sleep enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1LPENC" description="OTGPHY1 sleep enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2LPENC" description="OTGPHY2 sleep enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2LPENC" description="OTG2 sleep enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHELPENC" description="NPUCACHE sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPULPENC" description="NPU sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LLPENCR" description="RCC APB1L Sleep enable register" start="+0x12A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPENC" description="TIM2 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3LPENC" description="TIM3 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4LPENC" description="TIM4 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5LPENC" description="TIM5 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6LPENC" description="TIM6 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7LPENC" description="TIM7 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12LPENC" description="TIM12 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13LPENC" description="TIM13 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14LPENC" description="TIM14 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1LPENC" description="LPTIM1 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGLPENC" description="WWDG sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10LPENC" description="TIM10 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11LPENC" description="TIM11 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2LPENC" description="SPI2 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3LPENC" description="SPI3 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1LPENC" description="SPDIFRX1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2LPENC" description="USART2 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3LPENC" description="USART3 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4LPENC" description="UART4 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5LPENC" description="UART5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1LPENC" description="I2C1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2LPENC" description="I2C2 sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3LPENC" description="I2C3 sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1LPENC" description="I3C1 sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2LPENC" description="I3C2 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7LPENC" description="UART7 sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8LPENC" description="UART8 sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HLPENCR" description="RCC APB1H Sleep enable register" start="+0x12A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPENC" description="MDIOS sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANLPENC" description="FDCAN sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1LPENC" description="UCPD1 sleep enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2LPENCR" description="RCC APB2 Sleep enable register" start="+0x12AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPENC" description="TIM1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8LPENC" description="TIM8 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1LPENC" description="USART1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6LPENC" description="USART6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9LPENC" description="UART9 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10LPENC" description="USART10 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1LPENC" description="SPI1 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4LPENC" description="SPI4 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18LPENC" description="TIM18 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15LPENC" description="TIM15 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16LPENC" description="TIM16 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17LPENC" description="TIM17 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9LPENC" description="TIM9 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5LPENC" description="SPI5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1LPENC" description="SAI1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2LPENC" description="SAI2 sleep enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3LPENCR" description="RCC APB3 Sleep enable register" start="+0x12B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPENC" description="DFT sleep enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LLPENCR" description="RCC APB4L Sleep enable register" start="+0x12B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPENC" description="HDP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1LPENC" description="LPUART1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6LPENC" description="SPI6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4LPENC" description="I2C4 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2LPENC" description="LPTIM2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3LPENC" description="LPTIM3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4LPENC" description="LPTIM4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5LPENC" description="LPTIM5 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFLPENC" description="VREFBUF sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCLPENC" description="RTC sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBLPENC" description="RTCAPB sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETLPENC" description="R2GRET sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPULPENC" description="R2GNPU sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFLPENC" description="SERF sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HLPENCR" description="RCC APB4H Sleep enable register" start="+0x12B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPENC" description="SYSCFG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECLPENC" description="BSEC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSLPENC" description="DTS sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMLPENC" description="BUSPERFM sleep enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5LPENCR" description="RCC APB5 Sleep enable register" start="+0x12BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPENC" description="LTDC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPLPENC" description="DCMIPP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMLPENC" description="GFXTIM sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCLPENC" description="VENC sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSILPENC" description="CSI sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR0" description="RCC oscillator privilege configuration register0" start="+0x1784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPVC" description="Defines the privilege protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPVC" description="Defines the privilege protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPVC" description="Defines the privilege protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPVC" description="Defines the privilege protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPVC" description="Defines the privilege protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR0" description="RCC oscillator public configuration register0" start="+0x178C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUBC" description="Defines the public protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPUBC" description="Defines the public protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPUBC" description="Defines the public protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPUBC" description="Defines the public protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPUBC" description="Defines the public protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR1" description="RCC PLL privilege configuration register1" start="+0x1794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PVC" description="Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PVC" description="Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PVC" description="Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PVC" description="Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR1" description="RCC PLL public configuration register1" start="+0x179C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUBC" description="Defines the public protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PUBC" description="Defines the public protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PUBC" description="Defines the public protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PUBC" description="Defines the public protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR2" description="RCC divider privilege configuration register2" start="+0x17A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PVC" description="Defines the privilege protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PVC" description="Defines the privilege protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PVC" description="Defines the privilege protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PVC" description="Defines the privilege protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PVC" description="Defines the privilege protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PVC" description="Defines the privilege protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PVC" description="Defines the privilege protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PVC" description="Defines the privilege protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PVC" description="Defines the privilege protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PVC" description="Defines the privilege protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PVC" description="Defines the privilege protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PVC" description="Defines the privilege protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PVC" description="Defines the privilege protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PVC" description="Defines the privilege protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PVC" description="Defines the privilege protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PVC" description="Defines the privilege protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PVC" description="Defines the privilege protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PVC" description="Defines the privilege protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PVC" description="Defines the privilege protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PVC" description="Defines the privilege protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR2" description="RCC divider public configuration register2" start="+0x17AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUBC" description="Defines the public protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PUBC" description="Defines the public protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PUBC" description="Defines the public protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PUBC" description="Defines the public protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PUBC" description="Defines the public protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PUBC" description="Defines the public protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PUBC" description="Defines the public protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PUBC" description="Defines the public protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PUBC" description="Defines the public protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PUBC" description="Defines the public protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PUBC" description="Defines the public protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PUBC" description="Defines the public protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PUBC" description="Defines the public protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PUBC" description="Defines the public protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PUBC" description="Defines the public protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PUBC" description="Defines the public protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PUBC" description="Defines the public protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PUBC" description="Defines the public protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PUBC" description="Defines the public protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PUBC" description="Defines the public protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR3" description="RCC system privilege configuration register3" start="+0x17B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPVC" description="Defines the privilege protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPVC" description="Defines the privilege protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPVC" description="Defines the privilege protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPVC" description="Defines the privilege protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPVC" description="Defines the privilege protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPVC" description="Defines the privilege protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPVC" description="Defines the privilege protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR3" description="RCC system public configuration register3" start="+0x17BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUBC" description="Defines the public protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPUBC" description="Defines the public protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPUBC" description="Defines the public protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPUBC" description="Defines the public protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPUBC" description="Defines the public protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPUBC" description="Defines the public protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPUBC" description="Defines the public protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR4" description="RCC privilege configuration register4" start="+0x17C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPVC" description="Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPVC" description="Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPVC" description="Defines the privilege protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PVC" description="Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PVC" description="Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PVC" description="Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PVC" description="Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PVC" description="Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PVC" description="Defines the privilege protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PVC" description="Defines the privilege protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PVC" description="Defines the privilege protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PVC" description="Defines the privilege protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PVC" description="Defines the privilege protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPVC" description="Defines the privilege protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR4" description="RCC public configuration register4" start="+0x17CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUBC" description="Defines the public protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPUBC" description="Defines the public protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPUBC" description="Defines the public protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PUBC" description="Defines the public protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PUBC" description="Defines the public protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PUBC" description="Defines the public protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PUBC" description="Defines the public protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PUBC" description="Defines the public protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PUBC" description="Defines the public protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PUBC" description="Defines the public protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PUBC" description="Defines the public protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PUBC" description="Defines the public protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PUBC" description="Defines the public protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPUBC" description="Defines the public protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR5" description="RCC public configuration register4" start="+0x17D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUBC" description="Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4PUBC" description="Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5PUBC" description="Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6PUBC" description="Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1PUBC" description="Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2PUBC" description="Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMPUBC" description="Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1PUBC" description="Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2PUBC" description="Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMPUBC" description="Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="CACHEAXIRAMPUBC" description="Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMPUBC" description="Defines the public protection of the VENCRAM configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RCC_S" description="Reset and clock control" start="0x56028000">
+    <Register name="RCC_CR" description="RCC control register" start="+0x0" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSION" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="LSEON" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="MSION" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSION" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI is OFF" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ON (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="HSEON" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL1ON" description="PLL1 enable in Run/Sleep mode." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL2ON" description="PLL2 enable in Run/Sleep mode." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL3ON" description="PLL3 enable in Run/Sleep mode." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 is ON" start="0x1" />
+      </BitField>
+      <BitField name="PLL4ON" description="PLL4 enable in Run/Sleep mode." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 is ON" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SR" description="RCC status register" start="+0x4" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDY" description="LSI clock ready flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LSI is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ready" start="0x1" />
+      </BitField>
+      <BitField name="LSERDY" description="LSE clock ready flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LSE is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ready" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDY" description="MSI clock ready flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="MSI is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ready" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDY" description="HSI clock ready flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="HSI is not ready" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ready (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="HSERDY" description="HSE clock ready flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="HSE is not ready (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE is ready" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDY" description="PLL1 clock ready flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL1 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDY" description="PLL2 clock ready flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL2 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDY" description="PLL3 clock ready flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL3 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 locked" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDY" description="PLL4 clock ready flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="PLL4 unlocked (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_STOPCR" description="RCC Stop mode control register" start="+0x8" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISTOPEN" description="LSI oscillator enable in Stop mode." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="LSESTOPEN" description="LSE oscillator enable in Stop mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE is ON" start="0x1" />
+      </BitField>
+      <BitField name="MSISTOPEN" description="MSI oscillator enable in Stop mode." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSISTOPEN" description="HSI oscillator enable in Stop mode." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI is OFF" start="0x0" />
+        <Enum name="B_0x1" description="HSI is ON (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CFGR1" description="RCC configuration register 1" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="STOPWUCK" description="System clock selection after a wake up from system Stop." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI selected as wake up clock from system Stop (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI selected as wake up clock from system Stop" start="0x1" />
+      </BitField>
+      <BitField name="CPUSW" description="CPU clock switch selection" start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic1_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="CPUSWS" description="CPU clock switch status" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic1_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="SYSSW" description="System clock switch selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic2_ck selected as system clock" start="0x3" />
+      </BitField>
+      <BitField name="SYSSWS" description="System clock switch status" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hsi_ck selected as system clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as system clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as system clock" start="0x2" />
+        <Enum name="B_0x3" description="ic2_ck selected as system clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CFGR2" description="RCC configuration register 2" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPRE1" description="CPU domain APB1 prescaler" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk1 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk1 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE2" description="CPU domain APB2 prescaler" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk2 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk2 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE4" description="CPU domain APB4 prescaler" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk4 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk4 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="PPRE5" description="CPU domain APB5 prescaler" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="rcc_pclk5 = sys_bus2_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="rcc_pclk5 = sys_bus2_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="rcc_pclk1 = sys_bus2_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="rcc_pclk1 = sys_bus2_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="rcc_pclk1 = sys_bus2_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="rcc_pclk1 = sys_bus2_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="rcc_pclk1 = sys_bus2_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="rcc_pclk1 = sys_bus2_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="HPRE" description="AHB clock prescaler" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="sys_bus2_ck= sys_bus_ck" start="0x0" />
+        <Enum name="B_0x1" description="sys_bus2_ck = sys_bus_ck / 2 (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="sys_bus2_ck= sys_bus_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="sys_bus2_ck = sys_bus_ck / 8" start="0x3" />
+        <Enum name="B_0x4" description="sys_bus2_ck = sys_bus_ck / 16" start="0x4" />
+        <Enum name="B_0x5" description="sys_bus2_ck = sys_bus_ck / 32" start="0x5" />
+        <Enum name="B_0x6" description="sys_bus2_ck = sys_bus_ck / 64" start="0x6" />
+        <Enum name="B_0x7" description="sys_bus2_ck = sys_bus_ck / 128" start="0x7" />
+      </BitField>
+      <BitField name="TIMPRE" description="Timers clocks prescaler selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="timg_ck = sys_bus_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="timg_ck = sys_bus_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="timg_ck = sys_bus_ck / 4" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CKPROTR" description="RCC clock protection register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSPI3SELS" description="XSPI3 clock selection current status" start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI3 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI3 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI3 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI3 clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI2SELS" description="XSPI2 clock selection current status" start="20" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI2 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI2 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI2 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI2 clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI1SELS" description="XSPI1 clock selection current status" start="24" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as XSPI1 clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as XSPI1 clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as XSPI1 clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as XSPI1 clock" start="0x3" />
+      </BitField>
+      <BitField name="FMCSELS" description="FMC clock selection current status" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="hclk5 selected as FMC clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as FMC clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as FMC clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as FMC clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BDCR" description="RCC backup domain protection register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VSWRST" description="VSW domain software reset." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSW domain is not reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VSW domain is reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_HWRSR" description="RCC reset status register for hardware" start="+0x30" size="4" reset_value="0x00E00000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clear of the reset flags not activated (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="clear the value of the reset flags" start="0x1" />
+      </BitField>
+      <BitField name="LCKRSTF" description="CPU lockup reset flag." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No reset from CPU lockup occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from CPU lockup occurred" start="0x1" />
+      </BitField>
+      <BitField name="BORRSTF" description="BOR flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no BOR occurred" start="0x0" />
+        <Enum name="B_0x1" description="BOR occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset from pin occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from Pin occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PORRSTF" description="POR/PDR flag." start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no POR/PDR reset occurred" start="0x0" />
+        <Enum name="B_0x1" description="POR/PDR reset occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="SFTRSTF" description="Software system reset flag (1)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Software System reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="a Software System reset has been generated by the CPU" start="0x1" />
+      </BitField>
+      <BitField name="IWDGRSTF" description="Independent Watchdog reset flag." start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Independent Watchdog Reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Independent Watchdog Reset occurred" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRSTF" description="Window watchdog reset flag" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Window Watchdog Reset occurred from WWDG (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Window Watchdog Reset occurred from WWDG" start="0x1" />
+      </BitField>
+      <BitField name="LPWRRSTF" description="Illegal Stop or Standby flag." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no illegal reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="illegal Stop or Standby reset occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_RSR" description="RCC reset register" start="+0x34" size="4" reset_value="0x00E00000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clear of the reset flags not activated (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="clear the value of the reset flags" start="0x1" />
+      </BitField>
+      <BitField name="LCKRSTF" description="CPU lockup reset flag." start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No reset from CPU lockup occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from CPU lockup occurred" start="0x1" />
+      </BitField>
+      <BitField name="BORRSTF" description="BOR flag" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no BOR occurred" start="0x0" />
+        <Enum name="B_0x1" description="BOR occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no reset from Pin occurred" start="0x0" />
+        <Enum name="B_0x1" description="Reset from Pin occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="PORRSTF" description="POR/PDR flag." start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no POR/PDR reset occurred" start="0x0" />
+        <Enum name="B_0x1" description="POR/PDR reset occurred (default after power-on reset)" start="0x1" />
+      </BitField>
+      <BitField name="SFTRSTF" description="Software System reset flag (1)" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Software System reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="a Software System reset has been generated by the CPU" start="0x1" />
+      </BitField>
+      <BitField name="IWDGRSTF" description="Independent Watchdog reset flag." start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Independent Watchdog reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Independent Watchdog reset occurred" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRSTF" description="Window Watchdog reset flag" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no Window Watchdog reset occurred from WWDG (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="Window Watchdog reset occurred from WWDG" start="0x1" />
+      </BitField>
+      <BitField name="LPWRRSTF" description="Illegal Stop or Standby flag." start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no illegal reset occurred (default after power-on reset)" start="0x0" />
+        <Enum name="B_0x1" description="illegal Stop or Standby reset occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LSECFGR" description="RCC LSE configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSECSSON" description="LSE clock security system (CSS) enable" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="clock Security System on the LSE oscillator OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System on the LSE oscillator ON" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSRA" description="LSE clock security system (CSS) re-arm function" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 generates a re-arm pulse for the LSECSS function" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSD" description="LSE clock security system (CSS) failure detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No failure detected on the oscillator (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Failure detected on the oscillator" start="0x1" />
+      </BitField>
+      <BitField name="LSEBYP" description="LSE clock bypass" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE oscillator not bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE oscillator bypassed with an external clock" start="0x1" />
+      </BitField>
+      <BitField name="LSEEXT" description="LSE clock type in Bypass mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE in analog mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE in digital mode" start="0x1" />
+      </BitField>
+      <BitField name="LSEGFON" description="LSE clock glitch filter enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE clock glitch filter is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE clock glitch filter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSEDRV" description="LSE oscillator driving capability" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Lowest drive (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Medium low drive" start="0x1" />
+        <Enum name="B_0x2" description="Medium high drive" start="0x2" />
+        <Enum name="B_0x3" description="Highest drive" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MSICFGR" description="RCC MSI configuration register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSIFREQSEL" description="MSI oscillator frequency select" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI oscillator frequency is 4 MHz (default after backup domain reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI oscillator frequency is 16 MHz" start="0x1" />
+      </BitField>
+      <BitField name="MSITRIM" description="MSI clock trimming" start="16" size="5" access="Read/Write" />
+      <BitField name="MSICAL" description="MSI clock calibration" start="23" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSICFGR" description="RCC HSI configuration register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIDIV" description="HSI clock divider" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck = hsi_osc_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="hsi_ck = hsi_osc_ck / 2" start="0x1" />
+      </BitField>
+      <BitField name="HSITRIM" description="HSI clock trimming" start="16" size="7" access="Read/Write">
+        <Enum name="B_0x40" description="bsec_hsi_cal[8:0] - 64" start="0x40" />
+        <Enum name="B_0x41" description="bsec_hsi_cal[8:0] - 63" start="0x41" />
+        <Enum name="B_0x0" description="bsec_hsi_cal[8:0] (default after reset)" start="0x0" />
+        <Enum name="B_0x3E" description="bsec_hsi_cal[8:0] + 62" start="0x3E" />
+        <Enum name="B_0x3F" description="bsec_hsi_cal[8:0] + 63" start="0x3F" />
+      </BitField>
+      <BitField name="HSICAL" description="HSI clock calibration" start="23" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSIMCR" description="RCC HSI monitor control register" start="+0x4C" size="4" reset_value="0x001F07A1" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIREF" description="HSI clock cycle counter reference value." start="0" size="11" access="Read/Write" />
+      <BitField name="HSIDEV" description="HSI clock count deviation value" start="16" size="6" access="Read/Write" />
+      <BitField name="HSIMONEN" description="HSI clock period monitor enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing '0' disables the HSI clock period monitoring, reading '0' means that the HSI clock period monitoring is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Writing '1' enables the HSI clock period monitoring, reading '1' means that the HSI clock period monitoring is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_HSIMSR" description="RCC HSI monitor status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSIVAL" description="HSI clock cycle counter measured value." start="0" size="11" access="ReadOnly" />
+    </Register>
+    <Register name="RCC_HSECFGR" description="RCC HSE configuration register" start="+0x54" size="4" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
+      <BitField name="HSEDIV2BYP" description="HSE div2 oscillator clock in Bypass mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE: hse_div2_osc_ck = hse_osc_ck/2 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE: hse_div2_osc_ck = hse_osc_ck" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSON" description="HSE clock security system (CSS) enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="clock Security System on the HSE oscillator OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System on the HSE oscillator ON" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSRA" description="HSE clock security system (CSS) re-arm function" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing 0 has no effect (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Writing 1 generates a re-arm pulse for the HSECSS function" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSD" description="HSE clock security system (CSS) failure detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No failure detected on the oscillator (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Failure detected on the oscillator" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSBYP" description="HSE clock security system (CSS) bypass enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="clock Security System Bypass of the HSE oscillator is OFF (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock Security System Bypass on the HSE oscillator is ON" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSBPRE" description="HSE clock security system (CSS) bypass divider" start="11" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="HSI clock is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="HSI clock is divided by 2 (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="HSI clock is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="HSI clock is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="HSI clock is divided by 15" start="0xF" />
+      </BitField>
+      <BitField name="HSEBYP" description="HSE clock bypass" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE oscillator not bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE oscillator bypassed with an external clock" start="0x1" />
+      </BitField>
+      <BitField name="HSEEXT" description="HSE clock type in Bypass mode" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE in analog mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE in digital mode" start="0x1" />
+      </BitField>
+      <BitField name="HSEGFON" description="HSE clock glitch filter enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE clock glitch filter is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE clock glitch filter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSEDRV" description="HSE oscillator driving capability" start="18" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Lowest drive (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Medium low drive" start="0x1" />
+        <Enum name="B_0x2" description="Medium high drive" start="0x2" />
+        <Enum name="B_0x3" description="Highest drive" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL1CFGR1" description="RCC PLL1 configuration register 1" start="+0x80" size="4" reset_value="0x08202500" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1DIVN" description="PLL1 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL1DIVM" description="PLL1 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL1BYP" description="PLL1 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1SEL" description="PLL1 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL1CFGR2" description="RCC PLL1 configuration register 2" start="+0x84" size="4" reset_value="0x00800000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1DIVNFRAC" description="PLL1 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL1CFGR3" description="RCC PLL1 configuration register 3" start="+0x88" size="4" reset_value="0x4900000D" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1MODSSRST" description="PLL1 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL1 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL1 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1DACEN" description="PLL1 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODSSDIS" description="PLL1 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODDSEN" description="PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODSPRDW" description="PLL1 Modulation Spread-Spectrum Down" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL1MODDIV" description="PLL1 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL1MODSPR" description="PLL1 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL1PDIV2" description="PLL1 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL1PDIV1" description="PLL1 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL1PDIVEN" description="PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL2CFGR1" description="RCC PLL2 configuration register 1" start="+0x90" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2DIVN" description="PLL2 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL2DIVM" description="PLL2 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL2BYP" description="PLL2 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2SEL" description="PLL2 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL2CFGR2" description="RCC PLL2 configuration register 2" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2DIVNFRAC" description="PLL2 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL2CFGR3" description="RCC PLL2 configuration register 3" start="+0x98" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL2MODSSRST" description="PLL2 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL2 Modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL2 Modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2DACEN" description="PLL2 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODSSDIS" description="PLL2 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODDSEN" description="PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODSPRDW" description="PLL2 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL2MODDIV" description="PLL2 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL2MODSPR" description="PLL2 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL2PDIV2" description="PLL2 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL2PDIV1" description="PLL2 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL2PDIVEN" description="PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL3CFGR1" description="RCC PLL3 configuration register 1" start="+0xA0" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3DIVN" description="PLL3 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL3DIVM" description="PLL3 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL3BYP" description="PLL3 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3SEL" description="PLL3 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL3CFGR2" description="RCC PLL3 configuration register 2" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3DIVNFRAC" description="PLL3 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL3CFGR3" description="RCC PLL3 configuration register 3" start="+0xA8" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL3MODSSRST" description="PLL3 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL3 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL3 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3DACEN" description="PLL3 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODSSDIS" description="PLL3 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODDSEN" description="PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODSPRDW" description="PLL3 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL3MODDIV" description="PLL3 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL3MODSPR" description="PLL3 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL3PDIV2" description="PLL3 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL3PDIV1" description="PLL3 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL3PDIVEN" description="PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL4CFGR1" description="RCC PLL4 configuration register 1" start="+0xB0" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4DIVN" description="PLL4 Integer part for the VCO multiplication factor" start="8" size="12" access="Read/Write" />
+      <BitField name="PLL4DIVM" description="PLL4 reference input clock divide frequency ratio" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable when PLL is enabled" start="0x0" />
+        <Enum name="B_0x1" description="reference clock is divided by 1 (min value)" start="0x1" />
+        <Enum name="B_0x2" description="reference clock is divided by 2" start="0x2" />
+        <Enum name="B_0x3F" description="reference clock is divided by 63" start="0x3F" />
+      </BitField>
+      <BitField name="PLL4BYP" description="PLL4 bypass" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL output is driven by the VCO, via the optional POSTDIV division" start="0x0" />
+        <Enum name="B_0x1" description="PLL output is bypassed and driven by the PLL reference clock (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4SEL" description="PLL4 source selection of the reference clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="I2S_CKIN selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PLL4CFGR2" description="RCC PLL4 configuration register 2" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4DIVNFRAC" description="PLL4 Fractional part of the VCO multiplication factor" start="0" size="24" access="Read/Write" />
+    </Register>
+    <Register name="RCC_PLL4CFGR3" description="RCC PLL4 configuration register 3" start="+0xB8" size="4" reset_value="0x49000005" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL4MODSSRST" description="PLL4 Modulation Spread Spectrum reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The PLL4 modulation Spread Spectrum reset module is released" start="0x0" />
+        <Enum name="B_0x1" description="The PLL4 modulation Spread Spectrum reset module is asserted (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4DACEN" description="PLL4 noise canceling DAC enable in fractional mode." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DAC is not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DAC is active" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODSSDIS" description="PLL4 Modulation Spread-Spectrum Disable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum is active (and Fractional Divide inactive)" start="0x0" />
+        <Enum name="B_0x1" description="Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODDSEN" description="PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Modulation Spread-Spectrum and Fractional Divide are not active (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Modulation Spread-Spectrum and Fractional Divide are active" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODSPRDW" description="PLL4 Modulation Down Spread" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Center-spread modulation selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Down-spread modulation selected" start="0x1" />
+      </BitField>
+      <BitField name="PLL4MODDIV" description="PLL4 Modulation Division frequency adjustment " start="8" size="4" access="Read/Write" />
+      <BitField name="PLL4MODSPR" description="PLL4 Modulation Spread depth adjustment" start="16" size="5" access="Read/Write" />
+      <BitField name="PLL4PDIV2" description="PLL4 VCO frequency divider level 2" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL4PDIV1" description="PLL4 VCO frequency divider level 1" start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Not applicable" start="0x0" />
+        <Enum name="B_0x1" description="VCO output is divided by 1 (minimum value) (default after reset)" start="0x1" />
+        <Enum name="B_0x7" description="VCO output is divided by 7" start="0x7" />
+      </BitField>
+      <BitField name="PLL4PDIVEN" description="PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="POSTDIV1 and POSTDIV2 are powered down" start="0x0" />
+        <Enum name="B_0x1" description="POSTDIV1 and POSTDIV2 dividers are active (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC1CFGR" description="RCC IC1 configuration register" start="+0xC4" size="4" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1INT" description="Divider IC1 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC1 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC1 = pllx_ck / 3 (default after reset)" start="0x2" />
+        <Enum name="B_0x3" description="IC1 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC1 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC1SEL" description="Divider IC1 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC2CFGR" description="RCC IC2 configuration register" start="+0xC8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2INT" description="Divider IC2 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC2 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC2 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC2 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC2 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC2SEL" description="Divider IC2 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC3CFGR" description="RCC IC3 configuration register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC3INT" description="Divider IC3 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC3 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC3 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC3 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC3SEL" description="Divider IC3 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC4CFGR" description="RCC IC4 configuration register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4INT" description="Divider IC4 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC4 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC4 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC4 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC4SEL" description="Divider IC4 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC5CFGR" description="RCC IC5 configuration register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC5INT" description="Divider IC5 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC5 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC5 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC5 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC5SEL" description="Divider IC5 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC6CFGR" description="RCC IC6 configuration register" start="+0xD8" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC6INT" description="Divider IC6 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC6 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC6 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC6 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC6 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC6SEL" description="Divider IC6 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC7CFGR" description="RCC IC7 configuration register" start="+0xDC" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC7INT" description="Divider IC7 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC7 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC7 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC7 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC7SEL" description="Divider IC7 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC8CFGR" description="RCC IC8 configuration register" start="+0xE0" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC8INT" description="Divider IC8 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC8 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC8 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC8 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC8SEL" description="Divider IC8 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC9CFGR" description="RCC IC9 configuration register" start="+0xE4" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC9INT" description="Divider IC9 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC9 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC9 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC9 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC9SEL" description="Divider IC9 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC10CFGR" description="RCC IC10 configuration register" start="+0xE8" size="4" reset_value="0x10000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC10INT" description="Divider IC10 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC10 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC10 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC10 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC10SEL" description="Divider IC10 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected (default after reset)" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC11CFGR" description="RCC IC11 configuration register" start="+0xEC" size="4" reset_value="0x00030000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC11INT" description="Divider IC11 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 = pllx_ck" start="0x0" />
+        <Enum name="B_0x1" description="IC11 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC11 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC11 = pllx_ck / 4 (default after reset)" start="0x3" />
+        <Enum name="B_0xFF" description="IC11 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC11SEL" description="Divider IC11 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC12CFGR" description="RCC IC12 configuration register" start="+0xF0" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC12INT" description="Divider IC12 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC12 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC12 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC12 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC12SEL" description="Divider IC12 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC13CFGR" description="RCC IC13 configuration register" start="+0xF4" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC13INT" description="Divider IC13 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC13 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC13 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC13 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC13SEL" description="Divider IC13 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC14CFGR" description="RCC IC14 configuration register" start="+0xF8" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC14INT" description="Divider IC14 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC14 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC14 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC14 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC14SEL" description="Divider IC14 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC15CFGR" description="RCC IC15 configuration register" start="+0xFC" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC15INT" description="Divider IC15 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC15 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC15 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC15 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC15SEL" description="Divider IC15 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC16CFGR" description="RCC IC16 configuration register" start="+0x100" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC16INT" description="Divider IC16 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x1" description="IC16 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC16 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC16 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC16 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC16SEL" description="Divider IC16 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC17CFGR" description="RCC IC17 configuration register" start="+0x104" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC17INT" description="Divider IC17 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC17 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC17 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC17 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC17SEL" description="Divider IC17 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC18CFGR" description="RCC IC18 configuration register" start="+0x108" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC18INT" description="Divider IC18 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC18 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC18 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC18 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC18SEL" description="Divider IC18 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC19CFGR" description="RCC IC19 configuration register" start="+0x10C" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC19INT" description="Divider IC19 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC19 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC19 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC19 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC19SEL" description="Divider IC19 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_IC20CFGR" description="RCC IC20 configuration register" start="+0x110" size="4" reset_value="0x30000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC20INT" description="Divider IC20 integer division factor" start="16" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 = pllx_ck (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 = pllx_ck / 2" start="0x1" />
+        <Enum name="B_0x2" description="IC20 = pllx_ck / 3" start="0x2" />
+        <Enum name="B_0x3" description="IC20 = pllx_ck / 4" start="0x3" />
+        <Enum name="B_0xFF" description="IC20 = pllx_ck / 256" start="0xFF" />
+      </BitField>
+      <BitField name="IC20SEL" description="Divider IC20 Source Selection" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pll1_ck is selected" start="0x0" />
+        <Enum name="B_0x1" description="pll2_ck is selected" start="0x1" />
+        <Enum name="B_0x2" description="hsi_ck = hsi_osc_ck / 4" start="0x2" />
+        <Enum name="B_0x3" description="hsi_ck = hsi_osc_ck / 8" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CIER" description="RCC clock-source interrupt enable register" start="+0x124" size="4" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYIE" description="LSI ready interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYIE" description="LSE ready interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYIE" description="MSI ready interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYIE" description="HSI ready interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYIE" description="HSE ready interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE ready interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE ready interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYIE" description="PLL1 ready interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYIE" description="PLL2 ready interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYIE" description="PLL3 ready interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYIE" description="PLL4 ready interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 lock interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 lock interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSIE" description="LSE clock security system (CSS) interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE CSS interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE CSS interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSIE" description="HSE clock security system (CSS) interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE CSS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="HSE CSS interrupt enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="WKUPIE" description="CPU wakeup from Stop interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wakeup interrupt disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="Wakeup interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CIFR" description="RCC clock-source interrupt flag register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYF" description="LSI ready interrupt flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSI" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYF" description="LSE ready interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSE" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYF" description="MSI ready interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the MSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the MSI" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYF" description="HSI ready interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSI (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSI" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYF" description="HSE ready interrupt flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSE" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYF" description="PLL1 ready interrupt flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL1 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL1" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYF" description="PLL2 ready interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL2 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL2" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYF" description="PLL3 ready interrupt flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL3 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL3" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYF" description="PLL4 ready interrupt flag" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the PLL4 (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the PLL4" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSF" description="LSE ready interrupt flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the LSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the LSE" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSF" description="HSE ready interrupt flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no clock ready interrupt caused by the HSE (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="clock ready interrupt caused by the HSE" start="0x1" />
+      </BitField>
+      <BitField name="WKUPF" description="CPU wakeup from Stop interrupt flag" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no wakeup interrupt caused by the PWR (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="wakeup interrupt caused by the PWR" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CICR" description="RCC clock-source interrupt Clear register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYC" description="LSI ready interrupt clear" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="LSERDYC" description="LSE ready interrupt clear" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSERDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSERDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="MSIRDYC" description="MSI ready interrupt clear" start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSIRDYC" description="HSI ready interrupt clear" start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSIRDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSIRDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSERDYC" description="HSE ready interrupt clear" start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSERDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSERDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL1RDYC" description="PLL1 ready interrupt clear" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL1RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL2RDYC" description="PLL2 ready interrupt clear" start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL2RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL3RDYC" description="PLL3 ready interrupt clear" start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL3RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="PLL4RDYC" description="PLL4 ready interrupt clear" start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL4RDYF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4RDYF cleared" start="0x1" />
+      </BitField>
+      <BitField name="LSECSSC" description="LSE ready interrupt clear" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSECSSF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSECSSF cleared" start="0x1" />
+      </BitField>
+      <BitField name="HSECSSC" description="HSE ready interrupt clear" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSECSSF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSECSSF cleared" start="0x1" />
+      </BitField>
+      <BitField name="WKUPFC" description="CPU Wakeup ready interrupt clear" start="24" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="WKUPF not modified (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WKUPF cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR1" description="RCC clock configuration for independent peripheral register1" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADF1SEL" description="Source selection for the ADF1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="ADC12SEL" description="Source selection for the ADC12 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="ADCPRE" description="ADC12 Prog clock divider selection (for clock ck_icn_p_adf1)" start="8" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_adf1 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_adf1 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_adf1 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_adf1 is divided by 4" start="0x3" />
+      </BitField>
+      <BitField name="DCMIPPSEL" description="Source selection for the DCMIPP kernel clock" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic17_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR2" description="RCC clock configuration for independent peripheral register 2" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETH1PTPSEL" description="Source selection for the ETH1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclke selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic13_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="ETH1PTPDIV" description="ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp)" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_ker_eth1ptp is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_ker_eth1ptp is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_ker_eth1ptp is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_ker_eth1ptp is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_ker_eth1ptp is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="ETH1PWRDOWNACK" description="Set and reset by software." start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Power-down sequence start not yet acknowledged." start="0x0" />
+        <Enum name="B_0x1" description="Power-down sequence start acknowledged" start="0x1" />
+      </BitField>
+      <BitField name="ETH1CLKSEL" description="Source selection for the ETH1 kernel clock" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclke selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic12_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="ETH1SEL" description="Set and reset by software" start="16" size="3" access="Read/Write" />
+      <BitField name="ETH1REFCLKSEL" description="Set and reset by software" start="20" size="1" access="Read/Write" />
+      <BitField name="ETH1GTXCLKSEL" description="Set and reset by software." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MII" start="0x0" />
+        <Enum name="B_0x1" description="RGMII" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR3" description="RCC clock configuration for independent peripheral register3" start="+0x14C" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="FDCANSEL" description="Source selection for the FDCAN kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic19_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="FMCSEL" description="Source selection for the FMC kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="DFTSEL" description="Source selection for the DFT kernel clock" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="jtag_tck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="pclk3 selected as reference clock" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR4" description="RCC clock configuration for independent peripheral register4" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2C1SEL" description="Source selection for the I2C1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C2SEL" description="Source selection for the I2C2 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C3SEL" description="Source selection for the I2C3 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I2C4SEL" description="Source selection for the I2C4 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I3C1SEL" description="Source selection for the I3C1 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="I3C2SEL" description="Source selection for the I3C2 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic10_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic15_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LTDCSEL" description="Source selection for the LTDC kernel clock" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="pclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic16_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR5" description="RCC lock configuration for independent peripheral register5" start="+0x154" size="4" reset_value="0x0000F0F0" reset_mask="0xFFFFFFFF">
+      <BitField name="MCO1SEL" description="Source selection for the MCO1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_div_ck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="msi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lsi_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="hse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic5_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic10_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="sysa_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="MCO1PRE" description="MCO1 Prog clock divider selection (for clock ck_icn_p_mce3)" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_mce3 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_mce3 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_mce3 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_mce3 is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_icn_p_mce3 is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="MCO2SEL" description="Source selection for the MCO2 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_div_ck selected as reference clock (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="msi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lsi_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="hse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic15_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic20_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="sysb_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="MCO2PRE" description="MCO2 Prog clock divider selection (for clock ck_icn_p_mce4)" start="12" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_mce4 is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_mce4 is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_mce4 is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_mce4 is divided by 4" start="0x3" />
+        <Enum name="B_0xF" description="ck_icn_p_mce4 is divided by 16" start="0xF" />
+      </BitField>
+      <BitField name="MDF1SEL" description="Source selection for the MDF1 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="timg_ck selected as reference clock" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR6" description="RCC clock configuration for independent peripheral register6" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="XSPI1SEL" description="Source selection for the XSPI1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI2SEL" description="Source selection for the XSPI2 kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="XSPI3SEL" description="Source selection for the XSPI3 kernel clock" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic3_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic4_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY1SEL" description="Source selection for the OTGPHY1 kernel clock" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hse_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_div2_osc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY1CKREFSEL" description="Set and reset by software" start="16" size="1" access="Read/Write" />
+      <BitField name="OTGPHY2SEL" description="Source selection for the OTGPHY2 kernel clock" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hse_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_div2_osc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="OTGPHY2CKREFSEL" description="Set and reset by software" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RCC_CCIPR7" description="RCC clock configuration for independent peripheral register7" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERSEL" description="Source selection for the PER kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="hsi_ck selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="msi_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="hse_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic19_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="ic5_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="ic10_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="ic15_ck selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="ic20_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="PSSISEL" description="Source selection for the PSSI kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclk5 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic20_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hsi_div_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="RTCSEL" description="Source selection for the RTC kernel clock" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x1" description="lse_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="lsi_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="hse_rtc_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="RTCPRE" description="RTC Prog clock divider selection (for clock ck_icn_p_risaf)" start="12" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="ck_icn_p_risaf is divided by 1" start="0x0" />
+        <Enum name="B_0x1" description="ck_icn_p_risaf is divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="ck_icn_p_risaf is divided by 3" start="0x2" />
+        <Enum name="B_0x3" description="ck_icn_p_risaf is divided by 4" start="0x3" />
+        <Enum name="B_0x3F" description="ck_icn_p_risaf is divided by 64" start="0x3F" />
+      </BitField>
+      <BitField name="SAI1SEL" description="Source selection for the SAI1 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="spdif_symb_ck selected as reference clock" start="0x7" />
+      </BitField>
+      <BitField name="SAI2SEL" description="Source selection for the SAI2 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+        <Enum name="B_0x7" description="spdif_symb_ck selected as reference clock" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR8" description="RCC clock configuration for independent peripheral register8" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC1SEL" description="Source selection for the SDMMC1 kernel clock" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclku selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic4_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic5_ck selected as reference clock" start="0x3" />
+      </BitField>
+      <BitField name="SDMMC2SEL" description="Source selection for the SDMMC2 kernel clock" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="hclku selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic4_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic5_ck selected as reference clock" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR9" description="RCC clock configuration for independent peripheral register9" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPDIFRX1SEL" description="Source selection for the SPDIFRX1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic7_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic8_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI1SEL" description="Source selection for the SPI1 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI2SEL" description="Source selection for the SPI2 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI3SEL" description="Source selection for the SPI3 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI4SEL" description="Source selection for the SPI4 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hse_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI5SEL" description="Source selection for the SPI5 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hse_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="SPI6SEL" description="Source selection for the SPI6 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic8_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic9_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="msi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="hsi_div_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="I2S_CKIN selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR12" description="RCC clock configuration for independent peripheral register12" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPTIM1SEL" description="Source selection for the LPTIM1 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM2SEL" description="Source selection for the LPTIM2 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM3SEL" description="Source selection for the LPTIM3 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM4SEL" description="Source selection for the LPTIM4 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+      <BitField name="LPTIM5SEL" description="Source selection for the LPTIM5 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic15_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="lse_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lsi_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="timg_ck selected as reference clock" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR13" description="RCC clock configuration for independent peripheral register13" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USART1SEL" description="Source selection for the USART1 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART2SEL" description="Source selection for the USART2 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART3SEL" description="Source selection for the USART3 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART4SEL" description="Source selection for the UART4 kernel clock" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART5SEL" description="Source selection for the UART5 kernel clock" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART6SEL" description="Source selection for the USART6 kernel clock" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART7SEL" description="Source selection for the UART7 kernel clock" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="UART8SEL" description="Source selection for the UART8 kernel clock" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk1 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CCIPR14" description="RCC clock configuration for independent peripheral register14" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UART9SEL" description="Source selection for the UART9 kernel clock" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="USART10SEL" description="Source selection for the USART10 kernel clock" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk2 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+      <BitField name="LPUART1SEL" description="Source selection for the LPUART1 kernel clock" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="pclk4 selected as reference clock" start="0x0" />
+        <Enum name="B_0x1" description="per_ck selected as reference clock" start="0x1" />
+        <Enum name="B_0x2" description="ic9_ck selected as reference clock" start="0x2" />
+        <Enum name="B_0x3" description="ic14_ck selected as reference clock" start="0x3" />
+        <Enum name="B_0x4" description="lse_ck selected as reference clock" start="0x4" />
+        <Enum name="B_0x5" description="msi_ck selected as reference clock" start="0x5" />
+        <Enum name="B_0x6" description="hsi_div_ck selected as reference clock" start="0x6" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSRSTR" description="RCC SoC buses reset register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRST" description="ACLKN reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBMRST" description="AHBM reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB1RST" description="AHB1 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB2RST" description="AHB2 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB3RST" description="AHB3 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB4RST" description="AHB4 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHB5RST" description="AHB5 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB1RST" description="APB1 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB2RST" description="APB2 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB3RST" description="APB3 reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB4RST" description="APB4 reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="APB5RST" description="APB5 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NOCRST" description="NOC reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCRSTR" description="RCC miscellaneous configurations reset register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRST" description="DBG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHY1RST" description="XSPIPHY1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHY2RST" description="XSPIPHY2 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1DLLRST" description="SDMMC1DLL reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1DLL is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1DLL is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2DLLRST" description="SDMMC2DLL reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2DLL is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2DLL is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMRSTR" description="RCC memories reset register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RST" description="AXISRAM3 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4RST" description="AXISRAM4reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5RST" description="AXISRAM5 reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6RST" description="AXISRAM6 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1RST" description="AHBSRAM1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2RST" description="AHBSRAM2 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1RST" description="AXISRAM1 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2RST" description="AXISRAM2 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMRST" description="FLEXRAM reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMRST" description="NPUCACHERAM reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMRST" description="VENCRAM reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMRST" description="BOOTROM reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1RSTR" description="RCC AHB1 Reset register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RST" description="GPDMA1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ADC12RST" description="ADC12 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2RSTR" description="RCC AHB2 reset register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRST" description="RAMCFG reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="MDF1RST" description="MDF1 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ADF1RST" description="ADF1 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF1 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3RSTR" description="RCC AHB3 reset register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRST" description="RNG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="HASHRST" description="HASH reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CRYPRST" description="CRYP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAESRST" description="SAES reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PKARST" description="PKA reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is under reset" start="0x1" />
+      </BitField>
+      <BitField name="IACRST" description="IAC reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IAC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4RSTR" description="RCC AHB4 reset register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARST" description="GPIOA reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBRST" description="GPIOB reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCRST" description="GPIOC reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIODRST" description="GPIOD reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOERST" description="GPIOE reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFRST" description="GPIOF reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGRST" description="GPIOG reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHRST" description="GPIOH reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIONRST" description="GPION reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOORST" description="GPIOO reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPRST" description="GPIOP reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQRST" description="GPIOQ reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PWRRST" description="PWR reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PWR is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CRCRST" description="CRC reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5RSTR" description="RCC AHB5 reset register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RST" description="HPDMA1 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DRST" description="DMA2D reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is under reset" start="0x1" />
+      </BitField>
+      <BitField name="JPEGRST" description="JPEG reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FMCRST" description="FMC reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1RST" description="XSPI1 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="PSSIRST" description="PSSI reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2RST" description="SDMMC2 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1RST" description="SDMMC1 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2RST" description="XSPI2 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMRST" description="XSPIM reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3RST" description="XSPI3 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="MCE4RST" description="MCE4 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMURST" description="GFXMMU reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GPURST" description="GPU reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SYSCFGOTGHSPHY1RST" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFGOTGHSPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFGOTGHSPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SYSCFGOTGHSPHY2RST" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFGOTGHSPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFGOTGHSPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RST" description="ETH1 reset" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTG1RST" description="OTG1 reset" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1RST" description="OTGPHY1 reset" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2RST" description="OTGPHY2 reset" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="OTG2RST" description="OTG2 reset" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERST" description="NPUCACHE reset" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is under reset" start="0x1" />
+      </BitField>
+      <BitField name="NPURST" description="NPU reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LRSTR" description="RCC APB1L reset register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RST" description="TIM2 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM3RST" description="TIM3 reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM4RST" description="TIM4 reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM5RST" description="TIM5 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM6RST" description="TIM6 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM7RST" description="TIM7 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM12RST" description="TIM12 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM13RST" description="TIM13 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM14RST" description="TIM14 reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1RST" description="LPTIM1 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="WWDGRST" description="WWDG reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM10RST" description="TIM10 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM11RST" description="TIM11 reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI2RST" description="SPI2 reset" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI3RST" description="SPI3 reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1RST" description="SPDIFRX1 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART2RST" description="USART2 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART3RST" description="USART3 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART4RST" description="UART4 reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART5RST" description="UART5 reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C1RST" description="I2C1 reset" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C2RST" description="I2C2 reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C3RST" description="I2C3 reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I3C1RST" description="I3C1 reset" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I3C2RST" description="I3C2 reset" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART7RST" description="UART7 reset" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART8RST" description="UART8 reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HRSTR" description="RCC APB1H reset register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRST" description="MDIOS reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is under reset" start="0x1" />
+      </BitField>
+      <BitField name="FDCANRST" description="FDCAN reset" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1RST" description="UCPD1 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2RSTR" description="RCC APB2 reset register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RST" description="TIM1 reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM8RST" description="TIM8 reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART1RST" description="USART1 reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART6RST" description="USART6 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="UART9RST" description="UART9 reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="USART10RST" description="USART10 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI1RST" description="SPI1 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI4RST" description="SPI4 reset" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM18RST" description="TIM18 reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM15RST" description="TIM15 reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM16RST" description="TIM16 reset" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM17RST" description="TIM17 reset" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="TIM9RST" description="TIM9 reset" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI5RST" description="SPI5 reset" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAI1RST" description="SAI1 reset" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SAI2RST" description="SAI2 reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LRSTR" description="RCC APB4L reset register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRST" description="HDP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1RST" description="LPUART1 reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SPI6RST" description="SPI6 reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="I2C4RST" description="I2C4 reset" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2RST" description="LPTIM2 reset" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3RST" description="LPTIM3 reset" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4RST" description="LPTIM4 reset" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5RST" description="LPTIM5 reset" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFRST" description="VREFBUF reset" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is under reset" start="0x1" />
+      </BitField>
+      <BitField name="RTCRST" description="RTC reset" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETRST" description="R2GRET reset" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is under reset" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPURST" description="R2GNPU reset" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is under reset" start="0x1" />
+      </BitField>
+      <BitField name="SERFRST" description="SERF reset" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HRSTR" description="RCC APB4H reset register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRST" description="SYSCFG reset" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DTSRST" description="DTS reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is under reset" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMRST" description="BUSPERFM reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5RSTR" description="RCC APB5 reset register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRST" description="LTDC reset" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPRST" description="DCMIPP reset" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is under reset" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMRST" description="GFXTIM reset" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is under reset" start="0x1" />
+      </BitField>
+      <BitField name="VENCRST" description="VENC reset" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is under reset" start="0x1" />
+      </BitField>
+      <BitField name="CSIRST" description="CSI reset" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is not under reset (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is under reset" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_DIVENR" description="RCC IC dividers enable register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1EN" description="IC1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC2EN" description="IC2 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC3EN" description="IC3 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC4EN" description="IC4 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC5EN" description="IC5 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC6EN" description="IC6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC7EN" description="IC7 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC8EN" description="IC8 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC9EN" description="IC9 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC10EN" description="IC10 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC11EN" description="IC11 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC12EN" description="IC12 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC13EN" description="IC13 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC14EN" description="IC14 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC15EN" description="IC15 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC16EN" description="IC16 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC17EN" description="IC17 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC18EN" description="IC18 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC19EN" description="IC19 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IC20EN" description="IC20 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSENR" description="RCC SoC buses enable register" start="+0x244" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNEN" description="ACLKN enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is disabled" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCEN" description="ACLKNC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBMEN" description="AHBM enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB1EN" description="AHB1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB2EN" description="AHB2 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB3EN" description="AHB3 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB4EN" description="AHB4 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AHB5EN" description="AHB5 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB1EN" description="APB1 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB2EN" description="APB2 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB3EN" description="APB3 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB4EN" description="APB4 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="APB5EN" description="APB5 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCENR" description="RCC miscellaneous configuration enable register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGEN" description="DBG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCO1EN" description="MCO1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCO1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCO1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCO2EN" description="MCO2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCO2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCO2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHYCOMPEN" description="XSPIPHYCOMP enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHYCOMP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHYCOMP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PEREN" description="PER enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMENR" description="RCC memory enable register" start="+0x24C" size="4" reset_value="0x000013FF" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3EN" description="AXISRAM3 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4EN" description="AXISRAM4 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5EN" description="AXISRAM5 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6EN" description="AXISRAM6 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1EN" description="AHBSRAM1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2EN" description="AHBSRAM2 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMEN" description="BKPSRAM enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1EN" description="AXISRAM1 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2EN" description="AXISRAM2 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is disabled" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMEN" description="FLEXRAM enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMEN" description="NPUCACHERAM enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMEN" description="VENCRAM enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMEN" description="BOOTROM enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is enabled (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1ENR" description="RCC AHB1 enable register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1EN" description="GPDMA1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADC12EN" description="ADC12 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2ENR" description="RCC AHB2 enable register" start="+0x254" size="4" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGEN" description="RAMCFG enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="MDF1EN" description="MDF1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ADF1EN" description="ADF enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3ENR" description="RCC AHB3 enable register" start="+0x258" size="4" reset_value="0x00004600" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGEN" description="RNG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="HASHEN" description="HASH enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRYPEN" description="CRYP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAESEN" description="SAES enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PKAEN" description="PKA enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RIFSCEN" description="RIFSC enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RIFSC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="IACEN" description="IAC enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="IAC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="RISAFEN" description="RISAF enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RISAF is enabled (default after reset)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4ENR" description="RCC AHB4 enable register" start="+0x25C" size="4" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAEN" description="GPIOA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBEN" description="GPIOB enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCEN" description="GPIOC enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIODEN" description="GPIOD enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOEEN" description="GPIOE enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFEN" description="GPIOF enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGEN" description="GPIOG enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHEN" description="GPIOH enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIONEN" description="GPION enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOOEN" description="GPIOO enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPEN" description="GPIOP enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQEN" description="GPIOQ enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PWREN" description="PWR enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is disabled" start="0x0" />
+        <Enum name="B_0x1" description="PWR is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="CRCEN" description="CRC enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5ENR" description="RCC AHB5 enable register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1EN" description="HPDMA1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DEN" description="DMA2D enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is enabled" start="0x1" />
+      </BitField>
+      <BitField name="JPEGEN" description="JPEG enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FMCEN" description="FMC enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1EN" description="XSPI1 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="PSSIEN" description="PSSI enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2EN" description="SDMMC2 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1EN" description="SDMMC1 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2EN" description="XSPI2 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMEN" description="XSPIM enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE1EN" description="MCE1 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE2EN" description="MCE2 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE3EN" description="MCE3 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3EN" description="XSPI3 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MCE4EN" description="MCE4 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMUEN" description="GFXMMU enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GPUEN" description="GPU enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1MACEN" description="ETH1MAC enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1MAC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1MAC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1TXEN" description="ETH1TX enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1TX is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1TX is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RXEN" description="ETH1RX enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1RX is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1RX is enabled" start="0x1" />
+      </BitField>
+      <BitField name="ETH1EN" description="ETH1 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTG1EN" description="OTG1 enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1EN" description="OTGPHY1 enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2EN" description="OTGPHY2 enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="OTG2EN" description="OTG2 enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHEEN" description="NPUCACHE enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is enabled" start="0x1" />
+      </BitField>
+      <BitField name="NPUEN" description="NPU enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LENR" description="RCC APB1L enable register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2EN" description="TIM2 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM3EN" description="TIM3 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM4EN" description="TIM4 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM5EN" description="TIM5 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM6EN" description="TIM6 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM7EN" description="TIM7 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM12EN" description="TIM12 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM13EN" description="TIM13 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM14EN" description="TIM14 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1EN" description="LPTIM1 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WWDGEN" description="WWDG enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM10EN" description="TIM10 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM11EN" description="TIM11 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI2EN" description="SPI2 enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI3EN" description="SPI3 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1EN" description="SPDIFRX1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART2EN" description="USART2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART3EN" description="USART3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART4EN" description="UART4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART5EN" description="UART5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C1EN" description="I2C1 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C2EN" description="I2C2 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C3EN" description="I2C3 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I3C1EN" description="I3C1 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I3C2EN" description="I3C2 enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART7EN" description="UART7 enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART8EN" description="UART8 enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HENR" description="RCC APB1H enable register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSEN" description="MDIOS enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FDCANEN" description="FDCAN enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1EN" description="UCPD1 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2ENR" description="RCC APB2 enable register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1EN" description="TIM1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM8EN" description="TIM8 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART1EN" description="USART1 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART6EN" description="USART6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="UART9EN" description="UART9 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="USART10EN" description="USART10 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI1EN" description="SPI1 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI4EN" description="SPI4 enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM18EN" description="TIM18 enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM15EN" description="TIM15 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM16EN" description="TIM16 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM17EN" description="TIM17 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIM9EN" description="TIM9 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI5EN" description="SPI5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAI1EN" description="SAI1 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SAI2EN" description="SAI2 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB3ENR" description="RCC APB3 enable register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTEN" description="DFT enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LENR" description="RCC APB4L enable register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPEN" description="HDP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1EN" description="LPUART1 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SPI6EN" description="SPI6 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="I2C4EN" description="I2C4 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2EN" description="LPTIM2 enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3EN" description="LPTIM3 enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4EN" description="LPTIM4 enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5EN" description="LPTIM5 enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFEN" description="VREFBUF enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTCEN" description="RTC enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="RTCAPBEN" description="RTCAPB enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTCAPB is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTCAPB is enabled" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETEN" description="R2GRET enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is enabled" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPUEN" description="R2GNPU enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SERFEN" description="SERF enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HENR" description="RCC APB4H enable register" start="+0x278" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGEN" description="SYSCFG enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BSECEN" description="BSEC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BSEC is disabled" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is enabled (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="DTSEN" description="DTS enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMEN" description="BUSPERFM enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5ENR" description="RCC APB5 enable register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPEN" description="DCMIPP enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is enabled" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMEN" description="GFXTIM enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is enabled" start="0x1" />
+      </BitField>
+      <BitField name="VENCEN" description="VENC enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CSIEN" description="CSI enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is disabled (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_DIVLPENR" description="RCC dividers Sleep enable register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPEN" description="IC1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC2LPEN" description="IC2 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC3LPEN" description="IC3 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC4LPEN" description="IC4 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC5LPEN" description="IC5 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC6LPEN" description="IC6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC7LPEN" description="IC7 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC8LPEN" description="IC8 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC9LPEN" description="IC9 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC10LPEN" description="IC10 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC11LPEN" description="IC11 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC12LPEN" description="IC12 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC13LPEN" description="IC13 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC14LPEN" description="IC14 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC15LPEN" description="IC15 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC16LPEN" description="IC16 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC17LPEN" description="IC17 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC18LPEN" description="IC18 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC19LPEN" description="IC19 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IC20LPEN" description="IC20 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_BUSLPENR" description="RCC SoC buses Sleep enable register" start="+0x284" size="4" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPEN" description="ACLKN sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCLPEN" description="ACLKNC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="AHBMLPEN" description="AHBM sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB1LPEN" description="AHB1 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB2LPEN" description="AHB2 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB3LPEN" description="AHB3 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB4LPEN" description="AHB4 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHB5LPEN" description="AHB5 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB1LPEN" description="APB1 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB2LPEN" description="APB2 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB3LPEN" description="APB3 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB4LPEN" description="APB4 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="APB5LPEN" description="APB5 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MISCLPENR" description="RCC miscellaneous configurations Sleep enable register" start="+0x288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPEN" description="DBG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DBG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPIPHYCOMPLPEN" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIPHYCOMP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIPHYCOMP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PERLPEN" description="PER sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_MEMLPENR" description="RCC memory Sleep enable register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPEN" description="AXISRAM3 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4LPEN" description="AXISRAM4 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5LPEN" description="AXISRAM5 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6LPEN" description="AXISRAM6 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1LPEN" description="AHBSRAM1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2LPEN" description="AHBSRAM2 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMLPEN" description="BKPSRAM sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1LPEN" description="AXISRAM1 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2LPEN" description="AXISRAM2 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMLPEN" description="FLEXRAM sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMLPEN" description="NPUCACHERAM sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMLPEN" description="VENCRAM sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BOOTROMLPEN" description="BOOTROM sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BOOTROM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BOOTROM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB1LPENR" description="RCC AHB1 Sleep enable register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPEN" description="GPDMA1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPDMA1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPDMA1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ADC12LPEN" description="ADC12 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADC12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB2LPENR" description="RCC AHB2 Sleep enable register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPEN" description="RAMCFG sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RAMCFG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RAMCFG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MDF1LPEN" description="MDF1 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDF1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDF1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ADF1LPEN" description="ADF1 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADF1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ADF1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB3LPENR" description="RCC AHB3 Sleep enable register" start="+0x298" size="4" reset_value="0x00000400" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPEN" description="RNG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RNG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="HASHLPEN" description="HASH sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HASH is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HASH is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="CRYPLPEN" description="CRYP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRYP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAESLPEN" description="SAES sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAES is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAES is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PKALPEN" description="PKA sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PKA is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RIFSCLPEN" description="RIFSC sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RIFSC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="IACLPEN" description="IAC sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IAC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="IAC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="RISAFLPEN" description="RISAF sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RISAF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB4LPENR" description="RCC AHB4 Sleep enable register" start="+0x29C" size="4" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPEN" description="GPIOA sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOA is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOA is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOBLPEN" description="GPIOB sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOB is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOB is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOCLPEN" description="GPIOC sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIODLPEN" description="GPIOD sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOD is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOD is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOELPEN" description="GPIOE sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOE is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOE is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOFLPEN" description="GPIOF sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOGLPEN" description="GPIOG sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOHLPEN" description="GPIOH sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOH is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOH is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIONLPEN" description="GPION sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPION is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPION is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOOLPEN" description="GPIOO sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOO is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOO is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOPLPEN" description="GPIOP sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPIOQLPEN" description="GPIOQ sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPIOQ is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPIOQ is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PWRLPEN" description="PWR sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PWR is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="PWR is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="CRCLPEN" description="CRC sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CRC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_AHB5LPENR" description="RCC AHB5 Sleep enable register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPEN" description="HPDMA1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HPDMA1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HPDMA1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="DMA2DLPEN" description="DMA2D sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA2D is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DMA2D is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="JPEGLPEN" description="JPEG sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JPEG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="JPEG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FMCLPEN" description="FMC sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FMC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FMC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI1LPEN" description="XSPI1 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="PSSILPEN" description="PSSI sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2LPEN" description="SDMMC2 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SDMMC1LPEN" description="SDMMC1 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI2LPEN" description="XSPI2 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPIMLPEN" description="XSPIM sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPIM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPIM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE1LPEN" description="MCE1 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE2LPEN" description="MCE2 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE3LPEN" description="MCE3 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="XSPI3LPEN" description="XSPI3 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="MCE4LPEN" description="MCE4 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MCE4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MCE4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GFXMMULPEN" description="GFXMMU sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXMMU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXMMU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GPULPEN" description="GPU sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1MACLPEN" description="ETH1MAC sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1MAC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1MAC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1TXLPEN" description="ETH1TX sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1TX is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1TX is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1RXLPEN" description="ETH1RX sleep enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1RX is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1RX is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="ETH1LPEN" description="ETH1 sleep enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ETH1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ETH1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTG1LPEN" description="OTG1 sleep enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY1LPEN" description="OTGPHY1 sleep enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTGPHY2LPEN" description="OTGPHY2 sleep enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTGPHY2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTGPHY2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="OTG2LPEN" description="OTG2 sleep enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OTG2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="OTG2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHELPEN" description="NPUCACHE sleep enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHE is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHE is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="NPULPEN" description="NPU sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1LLPENR" description="RCC APB1L Sleep enable register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPEN" description="TIM2 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM3LPEN" description="TIM3 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM4LPEN" description="TIM4 sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM5LPEN" description="TIM5 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM6LPEN" description="TIM6 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM7LPEN" description="TIM7 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM12LPEN" description="TIM12 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM12 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM12 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM13LPEN" description="TIM13 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM13 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM13 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM14LPEN" description="TIM14 sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM14 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM14 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM1LPEN" description="LPTIM1 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="WWDGLPEN" description="WWDG sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WWDG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="WWDG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM10LPEN" description="TIM10 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM11LPEN" description="TIM11 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM11 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM11 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI2LPEN" description="SPI2 sleep enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI3LPEN" description="SPI3 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPDIFRX1LPEN" description="SPDIFRX1 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART2LPEN" description="USART2 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART3LPEN" description="USART3 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART4LPEN" description="UART4 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART5LPEN" description="UART5 sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C1LPEN" description="I2C1 sleep enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C2LPEN" description="I2C2 sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C3LPEN" description="I2C3 sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I3C1LPEN" description="I3C1 sleep enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I3C2LPEN" description="I3C2 sleep enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I3C2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I3C2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART7LPEN" description="UART7 sleep enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART7 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART7 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART8LPEN" description="UART8 sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB1HLPENR" description="RCC APB1H Sleep enable register" start="+0x2A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPEN" description="MDIOS sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MDIOS is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MDIOS is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="FDCANLPEN" description="FDCAN sleep enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FDCAN is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FDCAN is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UCPD1LPEN" description="UCPD1 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UCPD1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UCPD1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB2LPENR" description="RCC APB2 Sleep enable register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPEN" description="TIM1 sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM8LPEN" description="TIM8 sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM8 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM8 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART1LPEN" description="USART1 sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART6LPEN" description="USART6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="UART9LPEN" description="UART9 sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UART9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="UART9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="USART10LPEN" description="USART10 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART10 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="USART10 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI1LPEN" description="SPI1 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI4LPEN" description="SPI4 sleep enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM18LPEN" description="TIM18 sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM18 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM18 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM15LPEN" description="TIM15 sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM15 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM16LPEN" description="TIM16 sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM16 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM16 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM17LPEN" description="TIM17 sleep enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM17 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM17 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="TIM9LPEN" description="TIM9 sleep enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM9 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="TIM9 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI5LPEN" description="SPI5 sleep enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAI1LPEN" description="SAI1 sleep enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SAI2LPEN" description="SAI2 sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SAI2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB3LPENR" description="RCC APB3 Sleep enable register" start="+0x2B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPEN" description="DFT sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4LLPENR" description="RCC APB4L Sleep enable register" start="+0x2B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPEN" description="HDP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HDP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HDP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPUART1LPEN" description="LPUART1 sleep enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPUART1 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPUART1 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SPI6LPEN" description="SPI6 sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI6 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SPI6 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="I2C4LPEN" description="I2C4 sleep enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="I2C4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="I2C4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM2LPEN" description="LPTIM2 sleep enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM2 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM2 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM3LPEN" description="LPTIM3 sleep enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM3 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM3 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM4LPEN" description="LPTIM4 sleep enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM4 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM4 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="LPTIM5LPEN" description="LPTIM5 sleep enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LPTIM5 is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LPTIM5 is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VREFBUFLPEN" description="VREFBUF sleep enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFBUF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VREFBUF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RTCLPEN" description="RTC sleep enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="RTCAPBLPEN" description="RTCAPB sleep enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTCAPB is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RTCAPB is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="R2GRETLPEN" description="R2GRET sleep enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GRET is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GRET is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="R2GNPULPEN" description="R2GNPU sleep enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="R2GNPU is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="R2GNPU is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="SERFLPEN" description="SERF sleep enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SERF is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SERF is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB4HLPENR" description="RCC APB4H Sleep enable register" start="+0x2B8" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPEN" description="SYSCFG sleep enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYSCFG is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYSCFG is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BSECLPEN" description="BSEC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BSEC is disabled in Sleep mode" start="0x0" />
+        <Enum name="B_0x1" description="BSEC is enabled in Sleep mode (default after reset)" start="0x1" />
+      </BitField>
+      <BitField name="DTSLPEN" description="DTS sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTS is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DTS is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="BUSPERFMLPEN" description="BUSPERFM sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSPERFM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUSPERFM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_APB5LPENR" description="RCC APB5 Sleep enable register" start="+0x2BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPEN" description="LTDC sleep enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LTDC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LTDC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="DCMIPPLPEN" description="DCMIPP sleep enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCMIPP is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DCMIPP is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="GFXTIMLPEN" description="GFXTIM sleep enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="GFXTIM is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="GFXTIM is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="VENCLPEN" description="VENC sleep enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENC is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENC is enabled in Sleep mode" start="0x1" />
+      </BitField>
+      <BitField name="CSILPEN" description="CSI sleep enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSI is disabled in Sleep mode (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="CSI is enabled in Sleep mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_RDCR" description="RCC APB5 Sleep enable register" start="+0x44C" size="4" reset_value="0x00060000" reset_mask="0xFFFFFFFF">
+      <BitField name="MRD" description="BOOTROM sleep enable" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="No extra delay added by the BOOTROM" start="0x0" />
+        <Enum name="B_0x1" description="100 us" start="0x1" />
+        <Enum name="B_0x2" description="200 us" start="0x2" />
+        <Enum name="B_0x3" description="500 us" start="0x3" />
+        <Enum name="B_0x4" description="1 ms" start="0x4" />
+        <Enum name="B_0x5" description="2 ms" start="0x5" />
+        <Enum name="B_0x6" description="5 ms (default after reset)" start="0x6" />
+        <Enum name="B_0x7" description="10 ms" start="0x7" />
+        <Enum name="B_0x8" description="20 ms" start="0x8" />
+        <Enum name="B_0x9" description="50 ms" start="0x9" />
+        <Enum name="B_0xA" description="100 ms" start="0xA" />
+        <Enum name="B_0xB" description="200 ms" start="0xB" />
+        <Enum name="B_0xC" description="500 ms" start="0xC" />
+        <Enum name="B_0xD" description="1 s" start="0xD" />
+        <Enum name="B_0xE" description="2 s" start="0xE" />
+        <Enum name="B_0xF" description="5 s" start="0xF" />
+      </BitField>
+      <BitField name="EADLY" description="BOOTROM sleep enable" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="sysrstn low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="The guaranteed sysrstn low pulse duration is about 1 ms (1 x 32 lsi_ck cycles)" start="0x1" />
+        <Enum name="B_0x2" description="The guaranteed sysrstn low pulse duration is about 2 ms (2 x 32 lsi_ck cycles)" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR0" description="RCC oscillator secure configuration register0" start="+0x780" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISEC" description="Defines the secure protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="LSESEC" description="Defines the secure protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="MSISEC" description="Defines the secure protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="HSISEC" description="Defines the secure protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="HSESEC" description="Defines the secure protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR0" description="RCC oscillator privilege configuration register0" start="+0x784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPV" description="Defines the privilege protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="LSEPV" description="Defines the privilege protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="MSIPV" description="Defines the privilege protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="HSIPV" description="Defines the privilege protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="HSEPV" description="Defines the privilege protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR0" description="RCC oscillator lock configuration register0" start="+0x788" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSILOCK" description="Defines the lock protection of the LSI oscillator configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="LSELOCK" description="Defines the lock protection of the LSE oscillator configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="MSILOCK" description="Defines the lock protection of the MSI oscillator configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="HSILOCK" description="Defines the lock protection of the HSI oscillator configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="HSELOCK" description="Defines the lock protection of the HSE oscillator configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR0" description="RCC oscillator public configuration register0" start="+0x78C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUB" description="Defines the public protection of the LSI oscillator configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="LSEPUB" description="Defines the public protection of the LSE oscillator configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LSE configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="LSE configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="MSIPUB" description="Defines the public protection of the MSI oscillator configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="HSIPUB" description="Defines the public protection of the HSI oscillator configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSI configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSI configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="HSEPUB" description="Defines the public protection of the HSE oscillator configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="HSE configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="HSE configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR1" description="RCC PLL secure configuration register1" start="+0x790" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1SEC" description="Defines the secure protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2SEC" description="Defines the secure protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3SEC" description="Defines the secure protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4SEC" description="Defines the secure protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR1" description="RCC PLL privilege configuration register1" start="+0x794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PV" description="Defines the privilege protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2PV" description="Defines the privilege protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3PV" description="Defines the privilege protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4PV" description="Defines the privilege protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR1" description="RCC PLL lock configuration register1" start="+0x798" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1LOCK" description="Defines the lock protection of the PLL1 PLL configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2LOCK" description="Defines the lock protection of the PLL2 PLL configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3LOCK" description="Defines the lock protection of the PLL3 PLL configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4LOCK" description="Defines the lock protection of the PLL4 PLL configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR1" description="RCC PLL public configuration register1" start="+0x79C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUB" description="Defines the public protection of the PLL1 PLL configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL2PUB" description="Defines the public protection of the PLL2 PLL configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL3PUB" description="Defines the public protection of the PLL3 PLL configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PLL4PUB" description="Defines the public protection of the PLL4 PLL configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PLL4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PLL4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR2" description="RCC divider secure configuration register2" start="+0x7A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1SEC" description="Defines the secure protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2SEC" description="Defines the secure protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3SEC" description="Defines the secure protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4SEC" description="Defines the secure protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5SEC" description="Defines the secure protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6SEC" description="Defines the secure protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7SEC" description="Defines the secure protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8SEC" description="Defines the secure protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9SEC" description="Defines the secure protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10SEC" description="Defines the secure protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11SEC" description="Defines the secure protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12SEC" description="Defines the secure protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13SEC" description="Defines the secure protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14SEC" description="Defines the secure protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15SEC" description="Defines the secure protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16SEC" description="Defines the secure protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17SEC" description="Defines the secure protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18SEC" description="Defines the secure protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19SEC" description="Defines the secure protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20SEC" description="Defines the secure protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR2" description="RCC divider privilege configuration register2" start="+0x7A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PV" description="Defines the privilege protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2PV" description="Defines the privilege protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3PV" description="Defines the privilege protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4PV" description="Defines the privilege protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5PV" description="Defines the privilege protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6PV" description="Defines the privilege protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7PV" description="Defines the privilege protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8PV" description="Defines the privilege protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9PV" description="Defines the privilege protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10PV" description="Defines the privilege protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11PV" description="Defines the privilege protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12PV" description="Defines the privilege protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13PV" description="Defines the privilege protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14PV" description="Defines the privilege protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15PV" description="Defines the privilege protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16PV" description="Defines the privilege protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17PV" description="Defines the privilege protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18PV" description="Defines the privilege protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19PV" description="Defines the privilege protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20PV" description="Defines the privilege protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR2" description="RCC divider lock configuration register2" start="+0x7A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LOCK" description="Defines the lock protection of the IC1 divider configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2LOCK" description="Defines the lock protection of the IC2 divider configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3LOCK" description="Defines the lock protection of the IC3 divider configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4LOCK" description="Defines the lock protection of the IC4 divider configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5LOCK" description="Defines the lock protection of the IC5 divider configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6LOCK" description="Defines the lock protection of the IC6 divider configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7LOCK" description="Defines the lock protection of the IC7 divider configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8LOCK" description="Defines the lock protection of the IC8 divider configuration bits." start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9LOCK" description="Defines the lock protection of the IC9 divider configuration bits." start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10LOCK" description="Defines the lock protection of the IC10 divider configuration bits." start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11LOCK" description="Defines the lock protection of the IC11 divider configuration bits." start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12LOCK" description="Defines the lock protection of the IC12 divider configuration bits." start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13LOCK" description="Defines the lock protection of the IC13 divider configuration bits." start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14LOCK" description="Defines the lock protection of the IC14 divider configuration bits." start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15LOCK" description="Defines the lock protection of the IC15 divider configuration bits." start="14" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16LOCK" description="Defines the lock protection of the IC16 divider configuration bits." start="15" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17LOCK" description="Defines the lock protection of the IC17 divider configuration bits." start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18LOCK" description="Defines the lock protection of the IC18 divider configuration bits." start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19LOCK" description="Defines the lock protection of the IC19 divider configuration bits." start="18" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20LOCK" description="Defines the lock protection of the IC20 divider configuration bits." start="19" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR2" description="RCC divider public configuration register2" start="+0x7AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUB" description="Defines the public protection of the IC1 divider configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC2PUB" description="Defines the public protection of the IC2 divider configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC3PUB" description="Defines the public protection of the IC3 divider configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC4PUB" description="Defines the public protection of the IC4 divider configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC5PUB" description="Defines the public protection of the IC5 divider configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC6PUB" description="Defines the public protection of the IC6 divider configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC6 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC6 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC7PUB" description="Defines the public protection of the IC7 divider configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC7 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC7 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC8PUB" description="Defines the public protection of the IC8 divider configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC8 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC8 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC9PUB" description="Defines the public protection of the IC9 divider configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC9 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC9 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC10PUB" description="Defines the public protection of the IC10 divider configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC10 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC10 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC11PUB" description="Defines the public protection of the IC11 divider configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC11 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC11 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC12PUB" description="Defines the public protection of the IC12 divider configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC12 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC12 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC13PUB" description="Defines the public protection of the IC13 divider configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC13 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC13 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC14PUB" description="Defines the public protection of the IC14 divider configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC14 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC14 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC15PUB" description="Defines the public protection of the IC15 divider configuration bits." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC15 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC15 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC16PUB" description="Defines the public protection of the IC16 divider configuration bits." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC16 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC16 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC17PUB" description="Defines the public protection of the IC17 divider configuration bits." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC17 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC17 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC18PUB" description="Defines the public protection of the IC18 divider configuration bits." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC18 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC18 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC19PUB" description="Defines the public protection of the IC19 divider configuration bits." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC19 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC19 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="IC20PUB" description="Defines the public protection of the IC20 divider configuration bits." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IC20 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="IC20 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR3" description="RCC system secure configuration register3" start="+0x7B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODSEC" description="Defines the secure protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSSEC" description="Defines the secure protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSSEC" description="Defines the secure protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="PERSEC" description="Defines the secure protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="INTSEC" description="Defines the secure protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTSEC" description="Defines the secure protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTSEC" description="Defines the secure protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR3" description="RCC system privilege configuration register3" start="+0x7B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPV" description="Defines the privilege protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSPV" description="Defines the privilege protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSPV" description="Defines the privilege protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="PERPV" description="Defines the privilege protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="INTPV" description="Defines the privilege protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTPV" description="Defines the privilege protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTPV" description="Defines the privilege protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR3" description="RCC system lock configuration register3" start="+0x7B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODLOCK" description="Defines the lock protection of the MOD system configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSLOCK" description="Defines the lock protection of the SYS system configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSLOCK" description="Defines the lock protection of the BUS system configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="PERLOCK" description="Defines the lock protection of the PER system configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="INTLOCK" description="Defines the lock protection of the INT system configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTLOCK" description="Defines the lock protection of the RST system configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTLOCK" description="Defines the lock protection of the DFT system configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR3" description="RCC system public configuration register3" start="+0x7BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUB" description="Defines the public protection of the MOD system configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOD configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="MOD configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="SYSPUB" description="Defines the public protection of the SYS system configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SYS configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="SYS configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="BUSPUB" description="Defines the public protection of the BUS system configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUS configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BUS configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="PERPUB" description="Defines the public protection of the PER system configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PER configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="PER configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="INTPUB" description="Defines the public protection of the INT system configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="INT configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="INT configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="RSTPUB" description="Defines the public protection of the RST system configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RST configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="RST configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="DFTPUB" description="Defines the public protection of the DFT system configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFT configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="DFT configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_SECCFGR4" description="RCC bus secure configuration register4" start="+0x7C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNSEC" description="Defines the secure protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCSEC" description="Defines the secure protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMSEC" description="Defines the secure protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1SEC" description="Defines the secure protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2SEC" description="Defines the secure protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3SEC" description="Defines the secure protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4SEC" description="Defines the secure protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5SEC" description="Defines the secure protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1SEC" description="Defines the secure protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2SEC" description="Defines the secure protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3SEC" description="Defines the secure protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4SEC" description="Defines the secure protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5SEC" description="Defines the secure protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCSEC" description="Defines the secure protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-secure software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by secure software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PRIVCFGR4" description="RCC bus privilege configuration register4" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPV" description="Defines the privilege protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCPV" description="Defines the privilege protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMPV" description="Defines the privilege protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1PV" description="Defines the privilege protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2PV" description="Defines the privilege protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3PV" description="Defines the privilege protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4PV" description="Defines the privilege protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5PV" description="Defines the privilege protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1PV" description="Defines the privilege protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2PV" description="Defines the privilege protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3PV" description="Defines the privilege protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4PV" description="Defines the privilege protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5PV" description="Defines the privilege protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCPV" description="Defines the privilege protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-privilege software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by privilege software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_LOCKCFGR4" description="RCC bus lock configuration register4" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLOCK" description="Defines the lock protection of the ACLKN bus configuration bits." start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCLOCK" description="Defines the lock protection of the ACLKNC bus configuration bits." start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMLOCK" description="Defines the lock protection of the AHBM bus configuration bits." start="2" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1LOCK" description="Defines the lock protection of the AHB1 bus configuration bits." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2LOCK" description="Defines the lock protection of the AHB2 bus configuration bits." start="4" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3LOCK" description="Defines the lock protection of the AHB3 bus configuration bits." start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4LOCK" description="Defines the lock protection of the AHB4 bus configuration bits." start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5LOCK" description="Defines the lock protection of the AHB5 bus configuration bits." start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1LOCK" description="Defines the lock protection of the APB1 bus configuration bits." start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2LOCK" description="Defines the lock protection of the APB2 bus configuration bits." start="9" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3LOCK" description="Defines the lock protection of the APB3 bus configuration bits." start="10" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4LOCK" description="Defines the lock protection of the APB4 bus configuration bits." start="11" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5LOCK" description="Defines the lock protection of the APB5 bus configuration bits." start="12" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCLOCK" description="Defines the lock protection of the NOC bus configuration bits." start="13" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-lock software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by lock software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR4" description="RCC bus public configuration register4" start="+0x7CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUB" description="Defines the public protection of the ACLKN bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKN configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKN configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="ACLKNCPUB" description="Defines the public protection of the ACLKNC bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACLKNC configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="ACLKNC configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBMPUB" description="Defines the public protection of the AHBM bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB1PUB" description="Defines the public protection of the AHB1 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB2PUB" description="Defines the public protection of the AHB2 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB3PUB" description="Defines the public protection of the AHB3 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB4PUB" description="Defines the public protection of the AHB4 bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHB5PUB" description="Defines the public protection of the AHB5 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHB5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHB5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB1PUB" description="Defines the public protection of the APB1 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB2PUB" description="Defines the public protection of the APB2 bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB3PUB" description="Defines the public protection of the APB3 bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB4PUB" description="Defines the public protection of the APB4 bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="APB5PUB" description="Defines the public protection of the APB5 bus configuration bits." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="APB5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="APB5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="NOCPUB" description="Defines the public protection of the NOC bus configuration bits." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NOC configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NOC configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_PUBCFGR5" description="RCC bus public configuration register4" start="+0x7D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUB" description="Defines the public protection of the AXISRAM3 bus configuration bits." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM3 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM3 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM4PUB" description="Defines the public protection of the AXISRAM4 bus configuration bits." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM4 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM4 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM5PUB" description="Defines the public protection of the AXISRAM5 bus configuration bits." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM5 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM5 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM6PUB" description="Defines the public protection of the AXISRAM6 bus configuration bits." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM6 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM6 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM1PUB" description="Defines the public protection of the AHBSRAM1 bus configuration bits." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AHBSRAM2PUB" description="Defines the public protection of the AHBSRAM2 bus configuration bits." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AHBSRAM2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AHBSRAM2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="BKPSRAMPUB" description="Defines the public protection of the BKPSRAM bus configuration bits." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BKPSRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="BKPSRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM1PUB" description="Defines the public protection of the AXISRAM1 bus configuration bits." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM1 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM1 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="AXISRAM2PUB" description="Defines the public protection of the AXISRAM2 bus configuration bits." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AXISRAM2 configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="AXISRAM2 configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="FLEXRAMPUB" description="Defines the public protection of the FLEXRAM bus configuration bits." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FLEXRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="FLEXRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="NPUCACHERAMPUB" description="Defines the public protection of the NPUCACHERAM bus configuration bits." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NPUCACHERAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="NPUCACHERAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+      <BitField name="VENCRAMPUB" description="Defines the public protection of the VENCRAM bus configuration bits." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM configuration bits are accessible by non-public software only (default after reset)" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM configuration bits are accessible by public software only" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RCC_CSR" description="RCC control set register" start="+0x800" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIONS" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEONS" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIONS" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIONS" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEONS" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="WriteOnly" />
+      <BitField name="PLL1ONS" description="PLL1 oscillator enable in Run/Sleep mode." start="8" size="1" access="WriteOnly" />
+      <BitField name="PLL2ONS" description="PLL2 oscillator enable in Run/Sleep mode." start="9" size="1" access="WriteOnly" />
+      <BitField name="PLL3ONS" description="PLL3 oscillator enable in Run/Sleep mode." start="10" size="1" access="WriteOnly" />
+      <BitField name="PLL4ONS" description="PLL4 oscillator enable in Run/Sleep mode." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_STOPCSR" description="RCC Stop configuration register" start="+0x808" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSISTOPENS" description="MSISTOPENS" start="0" size="1" access="WriteOnly" />
+      <BitField name="HSISTOPENS" description="HSISTOPENS" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSRSTSR" description="RCC bus reset set register" start="+0xA04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRSTS" description="ACLKN reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AHBMRSTS" description="AHBM reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1RSTS" description="AHB1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2RSTS" description="AHB2 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3RSTS" description="AHB3 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4RSTS" description="AHB4 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5RSTS" description="AHB5 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1RSTS" description="APB1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2RSTS" description="APB2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3RSTS" description="APB3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4RSTS" description="APB4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5RSTS" description="APB5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCRSTS" description="NOC reset" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCRSTSR" description="RCC miscellaneous reset register" start="+0xA08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRSTS" description="DBG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY1RSTS" description="XSPIPHY1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY2RSTS" description="XSPIPHY2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1DLLRSTS" description="SDMMC1DLL reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2DLLRSTS" description="SDMMC2DLL reset" start="8" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMRSTSR" description="RCC memory reset register" start="+0xA0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RSTS" description="AXISRAM3 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4RSTS" description="AXISRAM4 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5RSTS" description="AXISRAM5 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6RSTS" description="AXISRAM6 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1RSTS" description="AHBSRAM1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2RSTS" description="AHBSRAM2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1RSTS" description="AXISRAM1 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2RSTS" description="AXISRAM2 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMRSTS" description="FLEXRAM reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMRSTS" description="NPUCACHERAM reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMRSTS" description="VENCRAM reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMRSTS" description="BOOTROM reset" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1RSTSR" description="RCC AHB1 reset register" start="+0xA10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RSTS" description="GPDMA1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12RSTS" description="ADC12 reset" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2RSTSR" description="RCC AHB2 reset register" start="+0xA14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRSTS" description="RAMCFG reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1RSTS" description="MDF1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1RSTS" description="ADF1 reset" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3RSTSR" description="RCC AHB3 reset register" start="+0xA18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRSTS" description="RNG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHRSTS" description="HASH reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPRSTS" description="CRYP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESRSTS" description="SAES reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKARSTS" description="PKA reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="IACRSTS" description="IAC reset" start="10" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4RSTSR" description="RCC AHB4 reset register" start="+0xA1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARSTS" description="GPIOA reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBRSTS" description="GPIOB reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCRSTS" description="GPIOC reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODRSTS" description="GPIOD reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOERSTS" description="GPIOE reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFRSTS" description="GPIOF reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGRSTS" description="GPIOG reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHRSTS" description="GPIOH reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONRSTS" description="GPION reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOORSTS" description="GPIOO reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPRSTS" description="GPIOP reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQRSTS" description="GPIOQ reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRRSTS" description="PWR reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCRSTS" description="CRC reset" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5RSTSR" description="RCC AHB5 reset register" start="+0xA20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RSTS" description="HPDMA1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DRSTS" description="DMA2D reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGRSTS" description="JPEG reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCRSTS" description="FMC reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1RSTS" description="XSPI1 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIRSTS" description="PSSI reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2RSTS" description="SDMMC2 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1RSTS" description="SDMMC1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2RSTS" description="XSPI2 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMRSTS" description="XSPIM reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="XSPI3RSTS" description="XSPI3 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4RSTS" description="MCE4 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMURSTS" description="GFXMMU reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPURSTS" description="GPU reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY1RSTS" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY2RSTS" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1RSTS" description="ETH1 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1RSTS" description="OTG1 reset" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1RSTS" description="OTGPHY1 reset" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2RSTS" description="OTGPHY2 reset" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2RSTS" description="OTG2 reset" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERSTS" description="NPUCACHE reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPURSTS" description="NPU reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LRSTSR" description="RCC APB1L reset register" start="+0xA24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RSTS" description="TIM2 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3RSTS" description="TIM3 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4RSTS" description="TIM4 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5RSTS" description="TIM5 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6RSTS" description="TIM6 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7RSTS" description="TIM7 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12RSTS" description="TIM12 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13RSTS" description="TIM13 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14RSTS" description="TIM14 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1RSTS" description="LPTIM1 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGRSTS" description="WWDG reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10RSTS" description="TIM10 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11RSTS" description="TIM11 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2RSTS" description="SPI2 reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3RSTS" description="SPI3 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1RSTS" description="SPDIFRX1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2RSTS" description="USART2 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3RSTS" description="USART3 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4RSTS" description="UART4 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5RSTS" description="UART5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1RSTS" description="I2C1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2RSTS" description="I2C2 reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3RSTS" description="I2C3 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1RSTS" description="I3C1 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2RSTS" description="I3C2 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7RSTS" description="UART7 reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8RSTS" description="UART8 reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HRSTSR" description="RCC APB1H reset register" start="+0xA28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRSTS" description="MDIOS reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANRSTS" description="FDCAN reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1RSTS" description="UCPD1 reset" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2RSTSR" description="RCC APB2 reset register" start="+0xA2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RSTS" description="TIM1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8RSTS" description="TIM8 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1RSTS" description="USART1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6RSTS" description="USART6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9RSTS" description="UART9 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10RSTS" description="USART10 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1RSTS" description="SPI1 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4RSTS" description="SPI4 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18RSTS" description="TIM18 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15RSTS" description="TIM15 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16RSTS" description="TIM16 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17RSTS" description="TIM17 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9RSTS" description="TIM9 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5RSTS" description="SPI5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1RSTS" description="SAI1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2RSTS" description="SAI2 reset" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LRSTSR" description="RCC APB4L reset register" start="+0xA34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRSTS" description="HDP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1RSTS" description="LPUART1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6RSTS" description="SPI6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4RSTS" description="I2C4 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2RSTS" description="LPTIM2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3RSTS" description="LPTIM3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4RSTS" description="LPTIM4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5RSTS" description="LPTIM5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFRSTS" description="VREFBUF reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCRSTS" description="RTC reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="R2GRETRSTS" description="R2GRET reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPURSTS" description="R2GNPU reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFRSTS" description="SERF reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HRSTSR" description="RCC APB4H reset register" start="+0xA38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRSTS" description="SYSCFG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DTSRSTS" description="DTS reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMRSTS" description="BUSPERFM reset" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5RSTSR" description="RCC APB5 reset register" start="+0xA3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRSTS" description="LTDC reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPRSTS" description="DCMIPP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMRSTS" description="GFXTIM reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCRSTS" description="VENC reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIRSTS" description="CSI reset" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVENSR" description="RCC Divider enable register" start="+0xA40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1ENS" description="IC1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2ENS" description="IC2 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3ENS" description="IC3 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4ENS" description="IC4 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5ENS" description="IC5 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6ENS" description="IC6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7ENS" description="IC7 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8ENS" description="IC8 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9ENS" description="IC9 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10ENS" description="IC10 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11ENS" description="IC11 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12ENS" description="IC12 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13ENS" description="IC13 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14ENS" description="IC14 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15ENS" description="IC15 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16ENS" description="IC16 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17ENS" description="IC17 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18ENS" description="IC18 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19ENS" description="IC19 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20ENS" description="IC20 enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSENSR" description="RCC bus enable register" start="+0xA44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNENS" description="ACLKN enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCENS" description="ACLKNC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMENS" description="AHBM enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1ENS" description="AHB1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2ENS" description="AHB2 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3ENS" description="AHB3 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4ENS" description="AHB4 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5ENS" description="AHB5 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1ENS" description="APB1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2ENS" description="APB2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3ENS" description="APB3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4ENS" description="APB4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5ENS" description="APB5 enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCENSR" description="RCC miscellaneous enable register" start="+0xA48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGENS" description="DBG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="MCO1ENS" description="MCO1 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="MCO2ENS" description="MCO2 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPENS" description="XSPIPHYCOMP enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERENS" description="PER enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMENSR" description="RCC memory enable register" start="+0xA4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3ENS" description="AXISRAM3 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4ENS" description="AXISRAM4 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5ENS" description="AXISRAM5 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6ENS" description="AXISRAM6 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1ENS" description="AHBSRAM1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2ENS" description="AHBSRAM2 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMENS" description="BKPSRAM enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1ENS" description="AXISRAM1 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2ENS" description="AXISRAM2 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMENS" description="FLEXRAM enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMENS" description="NPUCACHERAM enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMENS" description="VENCRAM enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMENS" description="BOOTROM enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1ENSR" description="RCC AHB1 enable register" start="+0xA50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1ENS" description="GPDMA1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12ENS" description="ADC12 enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2ENSR" description="RCC AHB2 enable register" start="+0xA54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGENS" description="RAMCFG enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1ENS" description="MDF1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1ENS" description="ADF1 enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3ENSR" description="RCC AHB3 enable register" start="+0xA58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGENS" description="RNG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHENS" description="HASH enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPENS" description="CRYP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESENS" description="SAES enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKAENS" description="PKA enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCENS" description="RIFSC enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACENS" description="IAC enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFENS" description="RISAF enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4ENSR" description="RCC AHB4 enable register" start="+0xA5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAENS" description="GPIOA enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBENS" description="GPIOB enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCENS" description="GPIOC enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODENS" description="GPIOD enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOEENS" description="GPIOE enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFENS" description="GPIOF enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGENS" description="GPIOG enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHENS" description="GPIOH enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONENS" description="GPION enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOENS" description="GPIOO enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPENS" description="GPIOP enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQENS" description="GPIOQ enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRENS" description="PWR enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCENS" description="CRC enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5ENSR" description="RCC AHB5 enable register" start="+0xA60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1ENS" description="HPDMA1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DENS" description="DMA2D enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGENS" description="JPEG enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCENS" description="FMC enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1ENS" description="XSPI1 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIENS" description="PSSI enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2ENS" description="SDMMC2 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1ENS" description="SDMMC1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2ENS" description="XSPI2 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMENS" description="XSPIM enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1ENS" description="MCE1 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2ENS" description="MCE2 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3ENS" description="MCE3 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3ENS" description="XSPI3 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4ENS" description="MCE4 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMUENS" description="GFXMMU enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPUENS" description="GPU enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACENS" description="ETH1MAC enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXENS" description="ETH1TX enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXENS" description="ETH1RX enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1ENS" description="ETH1 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1ENS" description="OTG1 enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1ENS" description="OTGPHY1 enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2ENS" description="OTGPHY2 enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2ENS" description="OTG2 enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHEENS" description="NPUCACHE enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPUENS" description="NPU enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LENSR" description="RCC APB1L enable register" start="+0xA64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2ENS" description="TIM2 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3ENS" description="TIM3 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4ENS" description="TIM4 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5ENS" description="TIM5 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6ENS" description="TIM6 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7ENS" description="TIM7 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12ENS" description="TIM12 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13ENS" description="TIM13 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14ENS" description="TIM14 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1ENS" description="LPTIM1 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGENS" description="WWDG enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10ENS" description="TIM10 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11ENS" description="TIM11 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2ENS" description="SPI2 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3ENS" description="SPI3 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1ENS" description="SPDIFRX1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2ENS" description="USART2 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3ENS" description="USART3 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4ENS" description="UART4 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5ENS" description="UART5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1ENS" description="I2C1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2ENS" description="I2C2 enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3ENS" description="I2C3 enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1ENS" description="I3C1 enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2ENS" description="I3C2 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7ENS" description="UART7 enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8ENS" description="UART8 enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HENSR" description="RCC APB1H enable register" start="+0xA68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSENS" description="MDIOS enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANENS" description="FDCAN enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1ENS" description="UCPD1 enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2ENSR" description="RCC APB2 enable register" start="+0xA6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1ENS" description="TIM1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8ENS" description="TIM8 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1ENS" description="USART1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6ENS" description="USART6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9ENS" description="UART9 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10ENS" description="USART10 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1ENS" description="SPI1 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4ENS" description="SPI4 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18ENS" description="TIM18 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15ENS" description="TIM15 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16ENS" description="TIM16 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17ENS" description="TIM17 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9ENS" description="TIM9 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5ENS" description="SPI5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1ENS" description="SAI1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2ENS" description="SAI2 enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3ENSR" description="RCC APB3 enable register" start="+0xA70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTENS" description="DFT enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LENSR" description="RCC APB4L enable register" start="+0xA74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPENS" description="HDP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1ENS" description="LPUART1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6ENS" description="SPI6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4ENS" description="I2C4 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2ENS" description="LPTIM2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3ENS" description="LPTIM3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4ENS" description="LPTIM4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5ENS" description="LPTIM5 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFENS" description="VREFBUF enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCENS" description="RTC enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBENS" description="RTCAPB enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETENS" description="R2GRET enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPUENS" description="R2GNPU enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFENS" description="SERF enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HENSR" description="RCC APB4H enable register" start="+0xA78" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGENS" description="SYSCFG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECENS" description="BSEC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSENS" description="DTS enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMENS" description="BUSPERFM enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5ENSR" description="RCC APB5 enable register" start="+0xA7C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCENS" description="LTDC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPENS" description="DCMIPP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMENS" description="GFXTIM enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCENS" description="VENC enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIENS" description="CSI enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVLPENSR" description="RCC divider Sleep enable register" start="+0xA80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPENS" description="IC1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2LPENS" description="IC2 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3LPENS" description="IC3 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4LPENS" description="IC4 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5LPENS" description="IC5 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6LPENS" description="IC6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7LPENS" description="IC7 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8LPENS" description="IC8 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9LPENS" description="IC9 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10LPENS" description="IC10 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11LPENS" description="IC11 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12LPENS" description="IC12 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13LPENS" description="IC13 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14LPENS" description="IC14 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15LPENS" description="IC15 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16LPENS" description="IC16 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17LPENS" description="IC17 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18LPENS" description="IC18 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19LPENS" description="IC19 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20LPENS" description="IC20 sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSLPENSR" description="RCC bus Sleep enable register" start="+0xA84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPENS" description="ACLKN sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCLPENS" description="ACLKNC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMLPENS" description="AHBM sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1LPENS" description="AHB1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2LPENS" description="AHB2 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3LPENS" description="AHB3 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4LPENS" description="AHB4 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5LPENS" description="AHB5 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1LPENS" description="APB1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2LPENS" description="APB2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3LPENS" description="APB3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4LPENS" description="APB4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5LPENS" description="APB5 sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCLPENSR" description="RCC miscellaneous Sleep enable register" start="+0xA88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPENS" description="DBG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPLPENS" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERLPENS" description="PER sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMLPENSR" description="RCC memory sleep enable register" start="+0xA8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPENS" description="AXISRAM3 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4LPENS" description="AXISRAM4 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5LPENS" description="AXISRAM5 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6LPENS" description="AXISRAM6 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1LPENS" description="AHBSRAM1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2LPENS" description="AHBSRAM2 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMLPENS" description="BKPSRAM sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1LPENS" description="AXISRAM1 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2LPENS" description="AXISRAM2 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMLPENS" description="FLEXRAM sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMLPENS" description="NPUCACHERAM sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMLPENS" description="VENCRAM sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMLPENS" description="BOOTROM sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1LPENSR" description="RCC AHB1 Sleep enable register" start="+0xA90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPENS" description="GPDMA1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12LPENS" description="ADC12 sleep enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2LPENSR" description="RCC AHB2 Sleep enable register" start="+0xA94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPENS" description="RAMCFG sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1LPENS" description="MDF1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1LPENS" description="ADF1 sleep enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3LPENSR" description="RCC AHB3 Sleep enable register" start="+0xA98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPENS" description="RNG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHLPENS" description="HASH sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPLPENS" description="CRYP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESLPENS" description="SAES sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKALPENS" description="PKA sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCLPENS" description="RIFSC sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACLPENS" description="IAC sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFLPENS" description="RISAF sleep enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4LPENSR" description="RCC AHB4 Sleep enable register" start="+0xA9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPENS" description="GPIOA sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBLPENS" description="GPIOB sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCLPENS" description="GPIOC sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODLPENS" description="GPIOD sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOELPENS" description="GPIOE sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFLPENS" description="GPIOF sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGLPENS" description="GPIOG sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHLPENS" description="GPIOH sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONLPENS" description="GPION sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOLPENS" description="GPIOO sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPLPENS" description="GPIOP sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQLPENS" description="GPIOQ sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRLPENS" description="PWR sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCLPENS" description="CRC sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5LPENSR" description="RCC AHB5 Sleep enable register" start="+0xAA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPENS" description="HPDMA1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DLPENS" description="DMA2D sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGLPENS" description="JPEG sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCLPENS" description="FMC sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1LPENS" description="XSPI1 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSILPENS" description="PSSI sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2LPENS" description="SDMMC2 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1LPENS" description="SDMMC1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2LPENS" description="XSPI2 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMLPENS" description="XSPIM sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1LPENS" description="MCE1 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2LPENS" description="MCE2 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3LPENS" description="MCE3 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3LPENS" description="XSPI3 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4LPENS" description="MCE4 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMULPENS" description="GFXMMU sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPULPENS" description="GPU sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACLPENS" description="ETH1MAC sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXLPENS" description="ETH1TX sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXLPENS" description="ETH1RX sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1LPENS" description="ETH1 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1LPENS" description="OTG1 sleep enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1LPENS" description="OTGPHY1 sleep enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2LPENS" description="OTGPHY2 sleep enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2LPENS" description="OTG2 sleep enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHELPENS" description="NPUCACHE sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPULPENS" description="NPU sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LLPENSR" description="RCC APB1L Sleep enable register" start="+0xAA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPENS" description="TIM2 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3LPENS" description="TIM3 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4LPENS" description="TIM4 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5LPENS" description="TIM5 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6LPENS" description="TIM6 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7LPENS" description="TIM7 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12LPENS" description="TIM12 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13LPENS" description="TIM13 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14LPENS" description="TIM14 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1LPENS" description="LPTIM1 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGLPENS" description="WWDG sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10LPENS" description="TIM10 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11LPENS" description="TIM11 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2LPENS" description="SPI2 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3LPENS" description="SPI3 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1LPENS" description="SPDIFRX1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2LPENS" description="USART2 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3LPENS" description="USART3 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4LPENS" description="UART4 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5LPENS" description="UART5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1LPENS" description="I2C1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2LPENS" description="I2C2 sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3LPENS" description="I2C3 sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1LPENS" description="I3C1 sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2LPENS" description="I3C2 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7LPENS" description="UART7 sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8LPENS" description="UART8 sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HLPENSR" description="RCC APB1H Sleep enable register" start="+0xAA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPENS" description="MDIOS sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANLPENS" description="FDCAN sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1LPENS" description="UCPD1 sleep enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2LPENSR" description="RCC APB2 Sleep enable register" start="+0xAAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPENS" description="TIM1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8LPENS" description="TIM8 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1LPENS" description="USART1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6LPENS" description="USART6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9LPENS" description="UART9 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10LPENS" description="USART10 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1LPENS" description="SPI1 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4LPENS" description="SPI4 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18LPENS" description="TIM18 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15LPENS" description="TIM15 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16LPENS" description="TIM16 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17LPENS" description="TIM17 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9LPENS" description="TIM9 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5LPENS" description="SPI5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1LPENS" description="SAI1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2LPENS" description="SAI2 sleep enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3LPENSR" description="RCC APB3 Sleep enable register" start="+0xAB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPENS" description="DFT sleep enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LLPENSR" description="RCC APB4L Sleep enable register" start="+0xAB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPENS" description="HDP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1LPENS" description="LPUART1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6LPENS" description="SPI6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4LPENS" description="I2C4 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2LPENS" description="LPTIM2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3LPENS" description="LPTIM3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4LPENS" description="LPTIM4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5LPENS" description="LPTIM5 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFLPENS" description="VREFBUF sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCLPENS" description="RTC sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBLPENS" description="RTCAPB sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETLPENS" description="R2GRET sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPULPENS" description="R2GNPU sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFLPENS" description="SERF sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HLPENSR" description="RCC APB4H Sleep enable register" start="+0xAB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPENS" description="SYSCFG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECLPENS" description="BSEC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSLPENS" description="DTS sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMLPENS" description="BUSPERFM sleep enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5LPENSR" description="RCC APB5 Sleep enable register" start="+0xABC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPENS" description="LTDC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPLPENS" description="DCMIPP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMLPENS" description="GFXTIM sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCLPENS" description="VENC sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSILPENS" description="CSI sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR0" description="RCC oscillator privilege configuration register0" start="+0xF84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPVS" description="Defines the privilege protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPVS" description="Defines the privilege protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPVS" description="Defines the privilege protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPVS" description="Defines the privilege protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPVS" description="Defines the privilege protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR0" description="RCC oscillator public configuration register0" start="+0xF8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUBS" description="Defines the public protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPUBS" description="Defines the public protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPUBS" description="Defines the public protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPUBS" description="Defines the public protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPUBS" description="Defines the public protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR1" description="RCC PLL privilege configuration register1" start="+0xF94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PVS" description="Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PVS" description="Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PVS" description="Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PVS" description="Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR1" description="RCC PLL public configuration register1" start="+0xF9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUBS" description="Defines the public protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PUBS" description="Defines the public protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PUBS" description="Defines the public protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PUBS" description="Defines the public protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR2" description="RCC divider privilege configuration register2" start="+0xFA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PVS" description="Defines the privilege protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PVS" description="Defines the privilege protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PVS" description="Defines the privilege protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PVS" description="Defines the privilege protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PVS" description="Defines the privilege protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PVS" description="Defines the privilege protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PVS" description="Defines the privilege protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PVS" description="Defines the privilege protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PVS" description="Defines the privilege protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PVS" description="Defines the privilege protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PVS" description="Defines the privilege protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PVS" description="Defines the privilege protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PVS" description="Defines the privilege protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PVS" description="Defines the privilege protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PVS" description="Defines the privilege protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PVS" description="Defines the privilege protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PVS" description="Defines the privilege protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PVS" description="Defines the privilege protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PVS" description="Defines the privilege protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PVS" description="Defines the privilege protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR2" description="RCC divider public configuration register2" start="+0xFAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUBS" description="Defines the public protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PUBS" description="Defines the public protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PUBS" description="Defines the public protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PUBS" description="Defines the public protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PUBS" description="Defines the public protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PUBS" description="Defines the public protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PUBS" description="Defines the public protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PUBS" description="Defines the public protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PUBS" description="Defines the public protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PUBS" description="Defines the public protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PUBS" description="Defines the public protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PUBS" description="Defines the public protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PUBS" description="Defines the public protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PUBS" description="Defines the public protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PUBS" description="Defines the public protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PUBS" description="Defines the public protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PUBS" description="Defines the public protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PUBS" description="Defines the public protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PUBS" description="Defines the public protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PUBS" description="Defines the public protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_SECCFGSR3" description="RCC system secure configuration register3" start="+0xFB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODSECS" description="Defines the secure protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSSECS" description="Defines the secure protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSSECS" description="Defines the secure protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERSECS" description="Defines the secure protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTSECS" description="Defines the secure protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTSECS" description="Defines the secure protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTSECS" description="Defines the secure protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR3" description="RCC system privilege configuration register3" start="+0xFB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPVS" description="Defines the privilege protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPVS" description="Defines the privilege protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPVS" description="Defines the privilege protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPVS" description="Defines the privilege protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPVS" description="Defines the privilege protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPVS" description="Defines the privilege protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPVS" description="Defines the privilege protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_LOCKCFGSR3" description="RCC system lock configuration register3" start="+0xFB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODLOCKS" description="Defines the lock protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSLOCKS" description="Defines the lock protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSLOCKS" description="Defines the lock protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERLOCKS" description="Defines the lock protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTLOCKS" description="Defines the lock protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTLOCKS" description="Defines the lock protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTLOCKS" description="Defines the lock protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR3" description="RCC system public configuration register3" start="+0xFBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUBS" description="Defines the public protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPUBS" description="Defines the public protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPUBS" description="Defines the public protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPUBS" description="Defines the public protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPUBS" description="Defines the public protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPUBS" description="Defines the public protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPUBS" description="Defines the public protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGSR4" description="RCC privilege configuration register4" start="+0xFC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPVS" description="Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPVS" description="Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPVS" description="Defines the privilege protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PVS" description="Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PVS" description="Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PVS" description="Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PVS" description="Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PVS" description="Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PVS" description="Defines the privilege protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PVS" description="Defines the privilege protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PVS" description="Defines the privilege protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PVS" description="Defines the privilege protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PVS" description="Defines the privilege protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPVS" description="Defines the privilege protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR4" description="RCC public configuration register4" start="+0xFCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUBS" description="Defines the public protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPUBS" description="Defines the public protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPUBS" description="Defines the public protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PUBS" description="Defines the public protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PUBS" description="Defines the public protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PUBS" description="Defines the public protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PUBS" description="Defines the public protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PUBS" description="Defines the public protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PUBS" description="Defines the public protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PUBS" description="Defines the public protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PUBS" description="Defines the public protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PUBS" description="Defines the public protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PUBS" description="Defines the public protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPUBS" description="Defines the public protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGSR5" description="RCC public configuration register4" start="+0xFD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUBS" description="Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4PUBS" description="Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5PUBS" description="Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6PUBS" description="Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1PUBS" description="Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2PUBS" description="Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMPUBS" description="Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1PUBS" description="Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2PUBS" description="Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMPUBS" description="Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMPUBS" description="Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMPUBS" description="Defines the public protection of the VENCRAM configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_CCR" description="RCC control Clear register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIONC" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEONC" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIONC" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIONC" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEONC" description="HSE oscillator enable in Run/Sleep mode." start="4" size="1" access="WriteOnly" />
+      <BitField name="PLL1ONC" description="PLL1 oscillator enable in Run/Sleep mode." start="8" size="1" access="WriteOnly" />
+      <BitField name="PLL2ONC" description="PLL2 oscillator enable in Run/Sleep mode." start="9" size="1" access="WriteOnly" />
+      <BitField name="PLL3ONC" description="PLL3 oscillator enable in Run/Sleep mode." start="10" size="1" access="WriteOnly" />
+      <BitField name="PLL4ONC" description="PLL4 oscillator enable in Run/Sleep mode." start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_STOPCCR" description="RCC StopCCR configuration register" start="+0x1008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSISTOPENC" description="LSI oscillator enable in Run/Sleep mode." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSESTOPENC" description="LSE oscillator enable in Run/Sleep mode." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSISTOPENC" description="MSI oscillator enable in Run/Sleep mode." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSISTOPENC" description="HSI oscillator enable in Run/Sleep mode." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSRSTCR" description="RCC bus reset register" start="+0x1204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNRSTC" description="ACLKN reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AHBMRSTC" description="AHBM reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1RSTC" description="AHB1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2RSTC" description="AHB2 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3RSTC" description="AHB3 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4RSTC" description="AHB4 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5RSTC" description="AHB5 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1RSTC" description="APB1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2RSTC" description="APB2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3RSTC" description="APB3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4RSTC" description="APB4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5RSTC" description="APB5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCRSTC" description="NOC reset" start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCRSTCR" description="RCC miscellaneous reset register" start="+0x1208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGRSTC" description="DBG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY1RSTC" description="XSPIPHY1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHY2RSTC" description="XSPIPHY2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1DLLRSTC" description="SDMMC1DLL reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2DLLRSTC" description="SDMMC2DLL reset" start="8" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMRSTCR" description="RCC memory reset register" start="+0x120C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3RSTC" description="AXISRAM3 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4RSTC" description="AXISRAM4 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5RSTC" description="AXISRAM5 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6RSTC" description="AXISRAM6 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1RSTC" description="AHBSRAM1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2RSTC" description="AHBSRAM2 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1RSTC" description="AXISRAM1 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2RSTC" description="AXISRAM2 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMRSTC" description="FLEXRAM reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMRSTC" description="NPUCACHERAM reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMRSTC" description="VENCRAM reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMRSTC" description="BOOTROM reset" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1RSTCR" description="RCC AHB1 reset register" start="+0x1210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1RSTC" description="GPDMA1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12RSTC" description="ADC12 reset" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2RSTCR" description="RCC AHB2 Reset register" start="+0x1214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGRSTC" description="RAMCFG reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1RSTC" description="MDF1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1RSTC" description="ADF1 reset" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3RSTCR" description="RCC AHB3 reset register" start="+0x1218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGRSTC" description="RNG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHRSTC" description="HASH reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPRSTC" description="CRYP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESRSTC" description="SAES reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKARSTC" description="PKA reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="IACRSTC" description="IAC reset" start="10" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4RSTCR" description="RCC AHB4 reset register" start="+0x121C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARSTC" description="GPIOA reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBRSTC" description="GPIOB reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCRSTC" description="GPIOC reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODRSTC" description="GPIOD reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOERSTC" description="GPIOE reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFRSTC" description="GPIOF reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGRSTC" description="GPIOG reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHRSTC" description="GPIOH reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONRSTC" description="GPION reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOORSTC" description="GPIOO reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPRSTC" description="GPIOP reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQRSTC" description="GPIOQ reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRRSTC" description="PWR reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCRSTC" description="CRC reset" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5RSTCR" description="RCC AHB5 reset register" start="+0x1220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1RSTC" description="HPDMA1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DRSTC" description="DMA2D reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGRSTC" description="JPEG reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCRSTC" description="FMC reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1RSTC" description="XSPI1 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIRSTC" description="PSSI reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2RSTC" description="SDMMC2 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1RSTC" description="SDMMC1 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2RSTC" description="XSPI2 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMRSTC" description="XSPIM reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="XSPI3RSTC" description="XSPI3 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4RSTC" description="MCE4 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMURSTC" description="GFXMMU reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPURSTC" description="GPU reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY1RSTC" description="SYSCFGOTGHSPHY1 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SYSCFGOTGHSPHY2RSTC" description="SYSCFGOTGHSPHY2 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1RSTC" description="ETH1 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1RSTC" description="OTG1 reset" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1RSTC" description="OTGPHY1 reset" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2RSTC" description="OTGPHY2 reset" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2RSTC" description="OTG2 reset" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERSTC" description="NPUCACHE reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPURSTC" description="NPU reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LRSTCR" description="RCC APB1L reset register" start="+0x1224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RSTC" description="TIM2 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3RSTC" description="TIM3 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4RSTC" description="TIM4 reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5RSTC" description="TIM5 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6RSTC" description="TIM6 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7RSTC" description="TIM7 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12RSTC" description="TIM12 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13RSTC" description="TIM13 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14RSTC" description="TIM14 reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1RSTC" description="LPTIM1 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGRSTC" description="WWDG reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10RSTC" description="TIM10 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11RSTC" description="TIM11 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2RSTC" description="SPI2 reset" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3RSTC" description="SPI3 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1RSTC" description="SPDIFRX1 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2RSTC" description="USART2 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3RSTC" description="USART3 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4RSTC" description="UART4 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5RSTC" description="UART5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1RSTC" description="I2C1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2RSTC" description="I2C2 reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3RSTC" description="I2C3 reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1RSTC" description="I3C1 reset" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2RSTC" description="I3C2 reset" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7RSTC" description="UART7 reset" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8RSTC" description="UART8 reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HRSTCR" description="RCC APB1H reset register" start="+0x1228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSRSTC" description="MDIOS reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANRSTC" description="FDCAN reset" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1RSTC" description="UCPD1 reset" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2RSTCR" description="RCC APB2 reset register" start="+0x122C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RSTC" description="TIM1 reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8RSTC" description="TIM8 reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1RSTC" description="USART1 reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6RSTC" description="USART6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9RSTC" description="UART9 reset" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10RSTC" description="USART10 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1RSTC" description="SPI1 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4RSTC" description="SPI4 reset" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18RSTC" description="TIM18 reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15RSTC" description="TIM15 reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16RSTC" description="TIM16 reset" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17RSTC" description="TIM17 reset" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9RSTC" description="TIM9 reset" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5RSTC" description="SPI5 reset" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1RSTC" description="SAI1 reset" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2RSTC" description="SAI2 reset" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LRSTCR" description="RCC APB4L reset register" start="+0x1234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPRSTC" description="HDP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1RSTC" description="LPUART1 reset" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6RSTC" description="SPI6 reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4RSTC" description="I2C4 reset" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2RSTC" description="LPTIM2 reset" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3RSTC" description="LPTIM3 reset" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4RSTC" description="LPTIM4 reset" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5RSTC" description="LPTIM5 reset" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFRSTC" description="VREFBUF reset" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCRSTC" description="RTC reset" start="16" size="1" access="WriteOnly" />
+      <BitField name="R2GRETRSTC" description="R2GRET reset" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPURSTC" description="R2GNPU reset" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFRSTC" description="SERF reset" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HRSTCR" description="RCC APB4H reset register" start="+0x1238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRSTC" description="SYSCFG reset" start="0" size="1" access="WriteOnly" />
+      <BitField name="DTSRSTC" description="DTS reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMRSTC" description="BUSPERFM reset" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5RSTCR" description="RCC APB5 reset register" start="+0x123C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRSTC" description="LTDC reset" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPRSTC" description="DCMIPP reset" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMRSTC" description="GFXTIM reset" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCRSTC" description="VENC reset" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIRSTC" description="CSI reset" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVENCR" description="RCC divider enable register" start="+0x1240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1ENC" description="IC1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2ENC" description="IC2 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3ENC" description="IC3 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4ENC" description="IC4 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5ENC" description="IC5 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6ENC" description="IC6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7ENC" description="IC7 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8ENC" description="IC8 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9ENC" description="IC9 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10ENC" description="IC10 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11ENC" description="IC11 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12ENC" description="IC12 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13ENC" description="IC13 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14ENC" description="IC14 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15ENC" description="IC15 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16ENC" description="IC16 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17ENC" description="IC17 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18ENC" description="IC18 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19ENC" description="IC19 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20ENC" description="IC20 enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSENCR" description="RCC bus enable register" start="+0x1244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNENC" description="ACLKN enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCENC" description="ACLKNC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMENC" description="AHBM enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1ENC" description="AHB1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2ENC" description="AHB2 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3ENC" description="AHB3 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4ENC" description="AHB4 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5ENC" description="AHB5 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1ENC" description="APB1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2ENC" description="APB2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3ENC" description="APB3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4ENC" description="APB4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5ENC" description="APB5 enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCENCR" description="RCC miscellaneous enable register" start="+0x1248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGENC" description="DBG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="MCO1ENC" description="MCO1 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="MCO2ENC" description="MCO2 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPENC" description="XSPIPHYCOMP enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERENC" description="PER enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMENCR" description="RCC memory enable register" start="+0x124C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3ENC" description="AXISRAM3 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4ENC" description="AXISRAM4 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5ENC" description="AXISRAM5 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6ENC" description="AXISRAM6 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1ENC" description="AHBSRAM1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2ENC" description="AHBSRAM2 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMENC" description="BKPSRAM enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1ENC" description="AXISRAM1 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2ENC" description="AXISRAM2 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMENC" description="FLEXRAM enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMENC" description="NPUCACHERAM enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMENC" description="VENCRAM enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMENC" description="BOOTROM enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1ENCR" description="RCC AHB1 enable register" start="+0x1250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1ENC" description="GPDMA1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12ENC" description="ADC12 enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2ENCR" description="RCC AHB2 enable register" start="+0x1254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGENC" description="RAMCFG enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1ENC" description="MDF1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1ENC" description="ADF1 enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3ENCR" description="RCC AHB3 enable register" start="+0x1258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGENC" description="RNG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHENC" description="HASH enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPENC" description="CRYP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESENC" description="SAES enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKAENC" description="PKA enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCENC" description="RIFSC enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACENC" description="IAC enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFENC" description="RISAF enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4ENCR" description="RCC AHB4 enable register" start="+0x125C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAENC" description="GPIOA enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBENC" description="GPIOB enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCENC" description="GPIOC enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODENC" description="GPIOD enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOEENC" description="GPIOE enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFENC" description="GPIOF enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGENC" description="GPIOG enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHENC" description="GPIOH enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONENC" description="GPION enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOENC" description="GPIOO enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPENC" description="GPIOP enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQENC" description="GPIOQ enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRENC" description="PWR enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCENC" description="CRC enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5ENCR" description="RCC AHB5 enable register" start="+0x1260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1ENC" description="HPDMA1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DENC" description="DMA2D enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGENC" description="JPEG enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCENC" description="FMC enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1ENC" description="XSPI1 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSIENC" description="PSSI enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2ENC" description="SDMMC2 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1ENC" description="SDMMC1 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2ENC" description="XSPI2 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMENC" description="XSPIM enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1ENC" description="MCE1 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2ENC" description="MCE2 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3ENC" description="MCE3 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3ENC" description="XSPI3 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4ENC" description="MCE4 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMUENC" description="GFXMMU enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPUENC" description="GPU enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACENC" description="ETH1MAC enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXENC" description="ETH1TX enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXENC" description="ETH1RX enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1ENC" description="ETH1 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1ENC" description="OTG1 enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1ENC" description="OTGPHY1 enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2ENC" description="OTGPHY2 enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2ENC" description="OTG2 enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHEENC" description="NPUCACHE enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPUENC" description="NPU enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LENCR" description="RCC APB1L enable register" start="+0x1264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2ENC" description="TIM2 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3ENC" description="TIM3 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4ENC" description="TIM4 enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5ENC" description="TIM5 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6ENC" description="TIM6 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7ENC" description="TIM7 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12ENC" description="TIM12 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13ENC" description="TIM13 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14ENC" description="TIM14 enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1ENC" description="LPTIM1 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="TIM10ENC" description="TIM10 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11ENC" description="TIM11 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2ENC" description="SPI2 enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3ENC" description="SPI3 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1ENC" description="SPDIFRX1 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2ENC" description="USART2 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3ENC" description="USART3 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4ENC" description="UART4 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5ENC" description="UART5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1ENC" description="I2C1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2ENC" description="I2C2 enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3ENC" description="I2C3 enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1ENC" description="I3C1 enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2ENC" description="I3C2 enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7ENC" description="UART7 enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8ENC" description="UART8 enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HENCR" description="RCC APB1H enable register" start="+0x1268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSENC" description="MDIOS enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANENC" description="FDCAN enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1ENC" description="UCPD1 enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2ENCR" description="RCC APB2 enable register" start="+0x126C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1ENC" description="TIM1 enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8ENC" description="TIM8 enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1ENC" description="USART1 enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6ENC" description="USART6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9ENC" description="UART9 enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10ENC" description="USART10 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1ENC" description="SPI1 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4ENC" description="SPI4 enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18ENC" description="TIM18 enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15ENC" description="TIM15 enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16ENC" description="TIM16 enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17ENC" description="TIM17 enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9ENC" description="TIM9 enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5ENC" description="SPI5 enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1ENC" description="SAI1 enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2ENC" description="SAI2 enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3ENCR" description="RCC APB3 enable register" start="+0x1270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTENC" description="DFT enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LENCR" description="RCC APB4L enable register" start="+0x1274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPENC" description="HDP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1ENC" description="LPUART1 enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6ENC" description="SPI6 enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4ENC" description="I2C4 enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2ENC" description="LPTIM2 enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3ENC" description="LPTIM3 enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4ENC" description="LPTIM4 enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5ENC" description="LPTIM5 enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFENC" description="VREFBUF enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCENC" description="RTC enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBENC" description="RTCAPB enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETENC" description="R2GRET enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPUENC" description="R2GNPU enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFENC" description="SERF enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HENCR" description="RCC APB4H enable register" start="+0x1278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGENC" description="SYSCFG enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECENC" description="BSEC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSENC" description="DTS enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMENC" description="BUSPERFM enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5ENCR" description="RCC APB5 enable register" start="+0x127C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCENC" description="LTDC enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPENC" description="DCMIPP enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMENC" description="GFXTIM enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCENC" description="VENC enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSIENC" description="CSI enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_DIVLPENCR" description="RCC divider Sleep enable register" start="+0x1280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1LPENC" description="IC1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2LPENC" description="IC2 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3LPENC" description="IC3 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4LPENC" description="IC4 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5LPENC" description="IC5 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6LPENC" description="IC6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7LPENC" description="IC7 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8LPENC" description="IC8 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9LPENC" description="IC9 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10LPENC" description="IC10 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11LPENC" description="IC11 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12LPENC" description="IC12 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13LPENC" description="IC13 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14LPENC" description="IC14 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15LPENC" description="IC15 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16LPENC" description="IC16 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17LPENC" description="IC17 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18LPENC" description="IC18 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19LPENC" description="IC19 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20LPENC" description="IC20 sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_BUSLPENCR" description="RCC bus Sleep enable register" start="+0x1284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNLPENC" description="ACLKN sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCLPENC" description="ACLKNC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMLPENC" description="AHBM sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1LPENC" description="AHB1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2LPENC" description="AHB2 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3LPENC" description="AHB3 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4LPENC" description="AHB4 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5LPENC" description="AHB5 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1LPENC" description="APB1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2LPENC" description="APB2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3LPENC" description="APB3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4LPENC" description="APB4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5LPENC" description="APB5 sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MISCLPENCR" description="RCC miscellaneous Sleep enable register" start="+0x1288" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGLPENC" description="DBG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="XSPIPHYCOMPLPENC" description="XSPIPHYCOMP sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="PERLPENC" description="PER sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_MEMLPENCR" description="RCC memory Sleep enable register" start="+0x128C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3LPENC" description="AXISRAM3 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4LPENC" description="AXISRAM4 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5LPENC" description="AXISRAM5 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6LPENC" description="AXISRAM6 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1LPENC" description="AHBSRAM1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2LPENC" description="AHBSRAM2 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMLPENC" description="BKPSRAM sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1LPENC" description="AXISRAM1 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2LPENC" description="AXISRAM2 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMLPENC" description="FLEXRAM sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHERAMLPENC" description="NPUCACHERAM sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMLPENC" description="VENCRAM sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="BOOTROMLPENC" description="BOOTROM sleep enable" start="12" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB1LPENCR" description="RCC AHB1 Sleep enable register" start="+0x1290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPDMA1LPENC" description="GPDMA1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="ADC12LPENC" description="ADC12 sleep enable" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB2LPENCR" description="RCC AHB2 Sleep enable register" start="+0x1294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RAMCFGLPENC" description="RAMCFG sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="MDF1LPENC" description="MDF1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="ADF1LPENC" description="ADF1 sleep enable" start="17" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB3LPENCR" description="RCC AHB3 Sleep enable register" start="+0x1298" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGLPENC" description="RNG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="HASHLPENC" description="HASH sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="CRYPLPENC" description="CRYP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="SAESLPENC" description="SAES sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="PKALPENC" description="PKA sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="RIFSCLPENC" description="RIFSC sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="IACLPENC" description="IAC sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="RISAFLPENC" description="RISAF sleep enable" start="14" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB4LPENCR" description="RCC AHB4 Sleep enable register" start="+0x129C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPENC" description="GPIOA sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="GPIOBLPENC" description="GPIOB sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="GPIOCLPENC" description="GPIOC sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GPIODLPENC" description="GPIOD sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="GPIOELPENC" description="GPIOE sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="GPIOFLPENC" description="GPIOF sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="GPIOGLPENC" description="GPIOG sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="GPIOHLPENC" description="GPIOH sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="GPIONLPENC" description="GPION sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="GPIOOLPENC" description="GPIOO sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="GPIOPLPENC" description="GPIOP sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="GPIOQLPENC" description="GPIOQ sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="PWRLPENC" description="PWR sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="CRCLPENC" description="CRC sleep enable" start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_AHB5LPENCR" description="RCC AHB5 Sleep enable register" start="+0x12A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPDMA1LPENC" description="HPDMA1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="DMA2DLPENC" description="DMA2D sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="JPEGLPENC" description="JPEG sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="FMCLPENC" description="FMC sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="XSPI1LPENC" description="XSPI1 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="PSSILPENC" description="PSSI sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="SDMMC2LPENC" description="SDMMC2 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SDMMC1LPENC" description="SDMMC1 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="XSPI2LPENC" description="XSPI2 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="XSPIMLPENC" description="XSPIM sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="MCE1LPENC" description="MCE1 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="MCE2LPENC" description="MCE2 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="MCE3LPENC" description="MCE3 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="XSPI3LPENC" description="XSPI3 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="MCE4LPENC" description="MCE4 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="GFXMMULPENC" description="GFXMMU sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="GPULPENC" description="GPU sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="ETH1MACLPENC" description="ETH1MAC sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="ETH1TXLPENC" description="ETH1TX sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="ETH1RXLPENC" description="ETH1RX sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="ETH1LPENC" description="ETH1 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="OTG1LPENC" description="OTG1 sleep enable" start="26" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY1LPENC" description="OTGPHY1 sleep enable" start="27" size="1" access="WriteOnly" />
+      <BitField name="OTGPHY2LPENC" description="OTGPHY2 sleep enable" start="28" size="1" access="WriteOnly" />
+      <BitField name="OTG2LPENC" description="OTG2 sleep enable" start="29" size="1" access="WriteOnly" />
+      <BitField name="NPUCACHELPENC" description="NPUCACHE sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="NPULPENC" description="NPU sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1LLPENCR" description="RCC APB1L Sleep enable register" start="+0x12A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPENC" description="TIM2 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM3LPENC" description="TIM3 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="TIM4LPENC" description="TIM4 sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="TIM5LPENC" description="TIM5 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="TIM6LPENC" description="TIM6 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="TIM7LPENC" description="TIM7 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="TIM12LPENC" description="TIM12 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="TIM13LPENC" description="TIM13 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIM14LPENC" description="TIM14 sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="LPTIM1LPENC" description="LPTIM1 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="WWDGLPENC" description="WWDG sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="TIM10LPENC" description="TIM10 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="TIM11LPENC" description="TIM11 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="SPI2LPENC" description="SPI2 sleep enable" start="14" size="1" access="WriteOnly" />
+      <BitField name="SPI3LPENC" description="SPI3 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="SPDIFRX1LPENC" description="SPDIFRX1 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="USART2LPENC" description="USART2 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="USART3LPENC" description="USART3 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="UART4LPENC" description="UART4 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="UART5LPENC" description="UART5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="I2C1LPENC" description="I2C1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="I2C2LPENC" description="I2C2 sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="I2C3LPENC" description="I2C3 sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="I3C1LPENC" description="I3C1 sleep enable" start="24" size="1" access="WriteOnly" />
+      <BitField name="I3C2LPENC" description="I3C2 sleep enable" start="25" size="1" access="WriteOnly" />
+      <BitField name="UART7LPENC" description="UART7 sleep enable" start="30" size="1" access="WriteOnly" />
+      <BitField name="UART8LPENC" description="UART8 sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB1HLPENCR" description="RCC APB1H Sleep enable register" start="+0x12A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDIOSLPENC" description="MDIOS sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="FDCANLPENC" description="FDCAN sleep enable" start="8" size="1" access="WriteOnly" />
+      <BitField name="UCPD1LPENC" description="UCPD1 sleep enable" start="18" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB2LPENCR" description="RCC APB2 Sleep enable register" start="+0x12AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPENC" description="TIM1 sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="TIM8LPENC" description="TIM8 sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="USART1LPENC" description="USART1 sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="USART6LPENC" description="USART6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="UART9LPENC" description="UART9 sleep enable" start="6" size="1" access="WriteOnly" />
+      <BitField name="USART10LPENC" description="USART10 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="SPI1LPENC" description="SPI1 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="SPI4LPENC" description="SPI4 sleep enable" start="13" size="1" access="WriteOnly" />
+      <BitField name="TIM18LPENC" description="TIM18 sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="TIM15LPENC" description="TIM15 sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="TIM16LPENC" description="TIM16 sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="TIM17LPENC" description="TIM17 sleep enable" start="18" size="1" access="WriteOnly" />
+      <BitField name="TIM9LPENC" description="TIM9 sleep enable" start="19" size="1" access="WriteOnly" />
+      <BitField name="SPI5LPENC" description="SPI5 sleep enable" start="20" size="1" access="WriteOnly" />
+      <BitField name="SAI1LPENC" description="SAI1 sleep enable" start="21" size="1" access="WriteOnly" />
+      <BitField name="SAI2LPENC" description="SAI2 sleep enable" start="22" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB3LPENCR" description="RCC APB3 Sleep enable register" start="+0x12B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DFTLPENC" description="DFT sleep enable" start="2" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4LLPENCR" description="RCC APB4L Sleep enable register" start="+0x12B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HDPLPENC" description="HDP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="LPUART1LPENC" description="LPUART1 sleep enable" start="3" size="1" access="WriteOnly" />
+      <BitField name="SPI6LPENC" description="SPI6 sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="I2C4LPENC" description="I2C4 sleep enable" start="7" size="1" access="WriteOnly" />
+      <BitField name="LPTIM2LPENC" description="LPTIM2 sleep enable" start="9" size="1" access="WriteOnly" />
+      <BitField name="LPTIM3LPENC" description="LPTIM3 sleep enable" start="10" size="1" access="WriteOnly" />
+      <BitField name="LPTIM4LPENC" description="LPTIM4 sleep enable" start="11" size="1" access="WriteOnly" />
+      <BitField name="LPTIM5LPENC" description="LPTIM5 sleep enable" start="12" size="1" access="WriteOnly" />
+      <BitField name="VREFBUFLPENC" description="VREFBUF sleep enable" start="15" size="1" access="WriteOnly" />
+      <BitField name="RTCLPENC" description="RTC sleep enable" start="16" size="1" access="WriteOnly" />
+      <BitField name="RTCAPBLPENC" description="RTCAPB sleep enable" start="17" size="1" access="WriteOnly" />
+      <BitField name="R2GRETLPENC" description="R2GRET sleep enable" start="22" size="1" access="WriteOnly" />
+      <BitField name="R2GNPULPENC" description="R2GNPU sleep enable" start="23" size="1" access="WriteOnly" />
+      <BitField name="SERFLPENC" description="SERF sleep enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB4HLPENCR" description="RCC APB4H Sleep enable register" start="+0x12B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPENC" description="SYSCFG sleep enable" start="0" size="1" access="WriteOnly" />
+      <BitField name="BSECLPENC" description="BSEC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DTSLPENC" description="DTS sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="BUSPERFMLPENC" description="BUSPERFM sleep enable" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_APB5LPENCR" description="RCC APB5 Sleep enable register" start="+0x12BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPENC" description="LTDC sleep enable" start="1" size="1" access="WriteOnly" />
+      <BitField name="DCMIPPLPENC" description="DCMIPP sleep enable" start="2" size="1" access="WriteOnly" />
+      <BitField name="GFXTIMLPENC" description="GFXTIM sleep enable" start="4" size="1" access="WriteOnly" />
+      <BitField name="VENCLPENC" description="VENC sleep enable" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSILPENC" description="CSI sleep enable" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR0" description="RCC oscillator privilege configuration register0" start="+0x1784" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPVC" description="Defines the privilege protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPVC" description="Defines the privilege protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPVC" description="Defines the privilege protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPVC" description="Defines the privilege protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPVC" description="Defines the privilege protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR0" description="RCC oscillator public configuration register0" start="+0x178C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIPUBC" description="Defines the public protection of the LSI configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="LSEPUBC" description="Defines the public protection of the LSE configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="MSIPUBC" description="Defines the public protection of the MSI configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="HSIPUBC" description="Defines the public protection of the HSI configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="HSEPUBC" description="Defines the public protection of the HSE configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR1" description="RCC PLL privilege configuration register1" start="+0x1794" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PVC" description="Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PVC" description="Defines the privilege protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PVC" description="Defines the privilege protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PVC" description="Defines the privilege protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR1" description="RCC PLL public configuration register1" start="+0x179C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1PUBC" description="Defines the public protection of the PLL1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="PLL2PUBC" description="Defines the public protection of the PLL2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="PLL3PUBC" description="Defines the public protection of the PLL3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PLL4PUBC" description="Defines the public protection of the PLL4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR2" description="RCC divider privilege configuration register2" start="+0x17A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PVC" description="Defines the privilege protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PVC" description="Defines the privilege protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PVC" description="Defines the privilege protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PVC" description="Defines the privilege protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PVC" description="Defines the privilege protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PVC" description="Defines the privilege protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PVC" description="Defines the privilege protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PVC" description="Defines the privilege protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PVC" description="Defines the privilege protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PVC" description="Defines the privilege protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PVC" description="Defines the privilege protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PVC" description="Defines the privilege protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PVC" description="Defines the privilege protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PVC" description="Defines the privilege protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PVC" description="Defines the privilege protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PVC" description="Defines the privilege protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PVC" description="Defines the privilege protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PVC" description="Defines the privilege protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PVC" description="Defines the privilege protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PVC" description="Defines the privilege protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR2" description="RCC divider public configuration register2" start="+0x17AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1PUBC" description="Defines the public protection of the IC1 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="IC2PUBC" description="Defines the public protection of the IC2 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="IC3PUBC" description="Defines the public protection of the IC3 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="IC4PUBC" description="Defines the public protection of the IC4 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="IC5PUBC" description="Defines the public protection of the IC5 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="IC6PUBC" description="Defines the public protection of the IC6 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="IC7PUBC" description="Defines the public protection of the IC7 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="IC8PUBC" description="Defines the public protection of the IC8 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="IC9PUBC" description="Defines the public protection of the IC9 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="IC10PUBC" description="Defines the public protection of the IC10 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="IC11PUBC" description="Defines the public protection of the IC11 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="IC12PUBC" description="Defines the public protection of the IC12 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="IC13PUBC" description="Defines the public protection of the IC13 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="IC14PUBC" description="Defines the public protection of the IC14 configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+      <BitField name="IC15PUBC" description="Defines the public protection of the IC15 configuration bits (enable, ready, divider)." start="14" size="1" access="WriteOnly" />
+      <BitField name="IC16PUBC" description="Defines the public protection of the IC16 configuration bits (enable, ready, divider)." start="15" size="1" access="WriteOnly" />
+      <BitField name="IC17PUBC" description="Defines the public protection of the IC17 configuration bits (enable, ready, divider)." start="16" size="1" access="WriteOnly" />
+      <BitField name="IC18PUBC" description="Defines the public protection of the IC18 configuration bits (enable, ready, divider)." start="17" size="1" access="WriteOnly" />
+      <BitField name="IC19PUBC" description="Defines the public protection of the IC19 configuration bits (enable, ready, divider)." start="18" size="1" access="WriteOnly" />
+      <BitField name="IC20PUBC" description="Defines the public protection of the IC20 configuration bits (enable, ready, divider)." start="19" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR3" description="RCC system privilege configuration register3" start="+0x17B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPVC" description="Defines the privilege protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPVC" description="Defines the privilege protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPVC" description="Defines the privilege protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPVC" description="Defines the privilege protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPVC" description="Defines the privilege protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPVC" description="Defines the privilege protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPVC" description="Defines the privilege protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR3" description="RCC system public configuration register3" start="+0x17BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODPUBC" description="Defines the public protection of the MOD configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="SYSPUBC" description="Defines the public protection of the SYS configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="BUSPUBC" description="Defines the public protection of the BUS configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="PERPUBC" description="Defines the public protection of the PER configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="INTPUBC" description="Defines the public protection of the INT configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="RSTPUBC" description="Defines the public protection of the RST configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="DFTPUBC" description="Defines the public protection of the DFT configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PRIVCFGCR4" description="RCC privilege configuration register4" start="+0x17C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPVC" description="Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPVC" description="Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPVC" description="Defines the privilege protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PVC" description="Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PVC" description="Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PVC" description="Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PVC" description="Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PVC" description="Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PVC" description="Defines the privilege protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PVC" description="Defines the privilege protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PVC" description="Defines the privilege protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PVC" description="Defines the privilege protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PVC" description="Defines the privilege protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPVC" description="Defines the privilege protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR4" description="RCC public configuration register4" start="+0x17CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACLKNPUBC" description="Defines the public protection of the ACLKN configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="ACLKNCPUBC" description="Defines the public protection of the ACLKNC configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AHBMPUBC" description="Defines the public protection of the AHBM configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AHB1PUBC" description="Defines the public protection of the AHB1 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHB2PUBC" description="Defines the public protection of the AHB2 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHB3PUBC" description="Defines the public protection of the AHB3 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="AHB4PUBC" description="Defines the public protection of the AHB4 configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AHB5PUBC" description="Defines the public protection of the AHB5 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="APB1PUBC" description="Defines the public protection of the APB1 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="APB2PUBC" description="Defines the public protection of the APB2 configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="APB3PUBC" description="Defines the public protection of the APB3 configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="APB4PUBC" description="Defines the public protection of the APB4 configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+      <BitField name="APB5PUBC" description="Defines the public protection of the APB5 configuration bits (enable, ready, divider)." start="12" size="1" access="WriteOnly" />
+      <BitField name="NOCPUBC" description="Defines the public protection of the NOC configuration bits (enable, ready, divider)." start="13" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RCC_PUBCFGCR5" description="RCC public configuration register4" start="+0x17D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXISRAM3PUBC" description="Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider)." start="0" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM4PUBC" description="Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider)." start="1" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM5PUBC" description="Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider)." start="2" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM6PUBC" description="Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider)." start="3" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM1PUBC" description="Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider)." start="4" size="1" access="WriteOnly" />
+      <BitField name="AHBSRAM2PUBC" description="Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider)." start="5" size="1" access="WriteOnly" />
+      <BitField name="BKPSRAMPUBC" description="Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider)." start="6" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM1PUBC" description="Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider)." start="7" size="1" access="WriteOnly" />
+      <BitField name="AXISRAM2PUBC" description="Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider)." start="8" size="1" access="WriteOnly" />
+      <BitField name="FLEXRAMPUBC" description="Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider)." start="9" size="1" access="WriteOnly" />
+      <BitField name="CACHEAXIRAMPUBC" description="Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider)." start="10" size="1" access="WriteOnly" />
+      <BitField name="VENCRAMPUBC" description="Defines the public protection of the VENCRAM configuration bits (enable, ready, divider)." start="11" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RIFSC" description="Resource isolation framework security controller" start="0x44024000">
+    <Register name="RIFSC_RISC_CR" description="RIFSC RISC slave configuration register x" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC RISC registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RIFSC RISC registers are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR0" description="RIFSC RISC slave security configuration register 0" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="security configuration for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 0." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 0." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="security configuration for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 1." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 1." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="security configuration for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 2." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 2." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="security configuration for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 3." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 3." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="security configuration for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 4." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 4." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="security configuration for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 5." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 5." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="security configuration for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 6." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 6." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="security configuration for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 7." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 7." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="security configuration for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 8." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 8." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="security configuration for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 9." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 9." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="security configuration for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 10." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 10." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="security configuration for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 11." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 11." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="security configuration for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 12." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 12." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="security configuration for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 13." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 13." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="security configuration for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 14." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 14." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="security configuration for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 15." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 15." start="0x1" />
+      </BitField>
+      <BitField name="SEC16" description="security configuration for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 16." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 16." start="0x1" />
+      </BitField>
+      <BitField name="SEC17" description="security configuration for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 17." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 17." start="0x1" />
+      </BitField>
+      <BitField name="SEC18" description="security configuration for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 18." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 18." start="0x1" />
+      </BitField>
+      <BitField name="SEC19" description="security configuration for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 19." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 19." start="0x1" />
+      </BitField>
+      <BitField name="SEC20" description="security configuration for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 20." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 20." start="0x1" />
+      </BitField>
+      <BitField name="SEC21" description="security configuration for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 21." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 21." start="0x1" />
+      </BitField>
+      <BitField name="SEC22" description="security configuration for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 22." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 22." start="0x1" />
+      </BitField>
+      <BitField name="SEC23" description="security configuration for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 23." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 23." start="0x1" />
+      </BitField>
+      <BitField name="SEC24" description="security configuration for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 24." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 24." start="0x1" />
+      </BitField>
+      <BitField name="SEC25" description="security configuration for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 25." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 25." start="0x1" />
+      </BitField>
+      <BitField name="SEC26" description="security configuration for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 26." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 26." start="0x1" />
+      </BitField>
+      <BitField name="SEC27" description="security configuration for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 27." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 27." start="0x1" />
+      </BitField>
+      <BitField name="SEC28" description="security configuration for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 28." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 28." start="0x1" />
+      </BitField>
+      <BitField name="SEC29" description="security configuration for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 29." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 29." start="0x1" />
+      </BitField>
+      <BitField name="SEC30" description="security configuration for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 30." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 30." start="0x1" />
+      </BitField>
+      <BitField name="SEC31" description="security configuration for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 31." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 31." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR1" description="RIFSC RISC slave security configuration register 1" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC32" description="security configuration for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 32." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 32." start="0x1" />
+      </BitField>
+      <BitField name="SEC33" description="security configuration for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 33." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 33." start="0x1" />
+      </BitField>
+      <BitField name="SEC34" description="security configuration for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 34." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 34." start="0x1" />
+      </BitField>
+      <BitField name="SEC35" description="security configuration for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 35." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 35." start="0x1" />
+      </BitField>
+      <BitField name="SEC36" description="security configuration for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 36." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 36." start="0x1" />
+      </BitField>
+      <BitField name="SEC37" description="security configuration for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 37." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 37." start="0x1" />
+      </BitField>
+      <BitField name="SEC38" description="security configuration for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 38." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 38." start="0x1" />
+      </BitField>
+      <BitField name="SEC39" description="security configuration for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 39." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 39." start="0x1" />
+      </BitField>
+      <BitField name="SEC40" description="security configuration for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 40." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 40." start="0x1" />
+      </BitField>
+      <BitField name="SEC41" description="security configuration for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 41." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 41." start="0x1" />
+      </BitField>
+      <BitField name="SEC42" description="security configuration for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 42." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 42." start="0x1" />
+      </BitField>
+      <BitField name="SEC43" description="security configuration for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 43." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 43." start="0x1" />
+      </BitField>
+      <BitField name="SEC44" description="security configuration for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 44." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 44." start="0x1" />
+      </BitField>
+      <BitField name="SEC45" description="security configuration for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 45." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 45." start="0x1" />
+      </BitField>
+      <BitField name="SEC46" description="security configuration for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 46." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 46." start="0x1" />
+      </BitField>
+      <BitField name="SEC47" description="security configuration for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 47." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 47." start="0x1" />
+      </BitField>
+      <BitField name="SEC48" description="security configuration for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 48." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 48." start="0x1" />
+      </BitField>
+      <BitField name="SEC49" description="security configuration for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 49." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 49." start="0x1" />
+      </BitField>
+      <BitField name="SEC50" description="security configuration for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 50." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 50." start="0x1" />
+      </BitField>
+      <BitField name="SEC51" description="security configuration for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 51." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 51." start="0x1" />
+      </BitField>
+      <BitField name="SEC52" description="security configuration for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 52." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 52." start="0x1" />
+      </BitField>
+      <BitField name="SEC53" description="security configuration for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 53." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 53." start="0x1" />
+      </BitField>
+      <BitField name="SEC54" description="security configuration for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 54." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 54." start="0x1" />
+      </BitField>
+      <BitField name="SEC55" description="security configuration for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 55." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 55." start="0x1" />
+      </BitField>
+      <BitField name="SEC56" description="security configuration for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 56." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 56." start="0x1" />
+      </BitField>
+      <BitField name="SEC57" description="security configuration for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 57." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 57." start="0x1" />
+      </BitField>
+      <BitField name="SEC58" description="security configuration for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 58." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 58." start="0x1" />
+      </BitField>
+      <BitField name="SEC59" description="security configuration for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 59." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 59." start="0x1" />
+      </BitField>
+      <BitField name="SEC60" description="security configuration for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 60." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 60." start="0x1" />
+      </BitField>
+      <BitField name="SEC61" description="security configuration for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 61." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 61." start="0x1" />
+      </BitField>
+      <BitField name="SEC62" description="security configuration for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 62." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 62." start="0x1" />
+      </BitField>
+      <BitField name="SEC63" description="security configuration for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 63." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 63." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR2" description="RIFSC RISC slave security configuration register 2" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC64" description="security configuration for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 64." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 64." start="0x1" />
+      </BitField>
+      <BitField name="SEC65" description="security configuration for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 65." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 65." start="0x1" />
+      </BitField>
+      <BitField name="SEC66" description="security configuration for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 66." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 66." start="0x1" />
+      </BitField>
+      <BitField name="SEC67" description="security configuration for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 67." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 67." start="0x1" />
+      </BitField>
+      <BitField name="SEC68" description="security configuration for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 68." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 68." start="0x1" />
+      </BitField>
+      <BitField name="SEC69" description="security configuration for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 69." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 69." start="0x1" />
+      </BitField>
+      <BitField name="SEC70" description="security configuration for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 70." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 70." start="0x1" />
+      </BitField>
+      <BitField name="SEC71" description="security configuration for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 71." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 71." start="0x1" />
+      </BitField>
+      <BitField name="SEC72" description="security configuration for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 72." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 72." start="0x1" />
+      </BitField>
+      <BitField name="SEC73" description="security configuration for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 73." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 73." start="0x1" />
+      </BitField>
+      <BitField name="SEC74" description="security configuration for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 74." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 74." start="0x1" />
+      </BitField>
+      <BitField name="SEC75" description="security configuration for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 75." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 75." start="0x1" />
+      </BitField>
+      <BitField name="SEC76" description="security configuration for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 76." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 76." start="0x1" />
+      </BitField>
+      <BitField name="SEC77" description="security configuration for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 77." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 77." start="0x1" />
+      </BitField>
+      <BitField name="SEC78" description="security configuration for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 78." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 78." start="0x1" />
+      </BitField>
+      <BitField name="SEC79" description="security configuration for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 79." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 79." start="0x1" />
+      </BitField>
+      <BitField name="SEC80" description="security configuration for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 80." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 80." start="0x1" />
+      </BitField>
+      <BitField name="SEC81" description="security configuration for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 81." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 81." start="0x1" />
+      </BitField>
+      <BitField name="SEC82" description="security configuration for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 82." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 82." start="0x1" />
+      </BitField>
+      <BitField name="SEC83" description="security configuration for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 83." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 83." start="0x1" />
+      </BitField>
+      <BitField name="SEC84" description="security configuration for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 84." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 84." start="0x1" />
+      </BitField>
+      <BitField name="SEC85" description="security configuration for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 85." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 85." start="0x1" />
+      </BitField>
+      <BitField name="SEC86" description="security configuration for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 86." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 86." start="0x1" />
+      </BitField>
+      <BitField name="SEC87" description="security configuration for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 87." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 87." start="0x1" />
+      </BitField>
+      <BitField name="SEC88" description="security configuration for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 88." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 88." start="0x1" />
+      </BitField>
+      <BitField name="SEC89" description="security configuration for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 89." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 89." start="0x1" />
+      </BitField>
+      <BitField name="SEC90" description="security configuration for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 90." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 90." start="0x1" />
+      </BitField>
+      <BitField name="SEC91" description="security configuration for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 91." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 91." start="0x1" />
+      </BitField>
+      <BitField name="SEC92" description="security configuration for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 92." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 92." start="0x1" />
+      </BitField>
+      <BitField name="SEC93" description="security configuration for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 93." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 93." start="0x1" />
+      </BitField>
+      <BitField name="SEC94" description="security configuration for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 94." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 94." start="0x1" />
+      </BitField>
+      <BitField name="SEC95" description="security configuration for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 95." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 95." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR3" description="RIFSC RISC slave security configuration register 3" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC96" description="security configuration for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 96." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 96." start="0x1" />
+      </BitField>
+      <BitField name="SEC97" description="security configuration for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 97." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 97." start="0x1" />
+      </BitField>
+      <BitField name="SEC98" description="security configuration for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 98." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 98." start="0x1" />
+      </BitField>
+      <BitField name="SEC99" description="security configuration for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 99." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 99." start="0x1" />
+      </BitField>
+      <BitField name="SEC100" description="security configuration for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 100." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 100." start="0x1" />
+      </BitField>
+      <BitField name="SEC101" description="security configuration for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 101." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 101." start="0x1" />
+      </BitField>
+      <BitField name="SEC102" description="security configuration for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 102." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 102." start="0x1" />
+      </BitField>
+      <BitField name="SEC103" description="security configuration for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 103." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 103." start="0x1" />
+      </BitField>
+      <BitField name="SEC104" description="security configuration for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 104." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 104." start="0x1" />
+      </BitField>
+      <BitField name="SEC105" description="security configuration for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 105." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 105." start="0x1" />
+      </BitField>
+      <BitField name="SEC106" description="security configuration for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 106." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 106." start="0x1" />
+      </BitField>
+      <BitField name="SEC107" description="security configuration for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 107." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 107." start="0x1" />
+      </BitField>
+      <BitField name="SEC108" description="security configuration for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 108." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 108." start="0x1" />
+      </BitField>
+      <BitField name="SEC109" description="security configuration for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 109." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 109." start="0x1" />
+      </BitField>
+      <BitField name="SEC110" description="security configuration for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 110." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 110." start="0x1" />
+      </BitField>
+      <BitField name="SEC111" description="security configuration for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 111." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 111." start="0x1" />
+      </BitField>
+      <BitField name="SEC112" description="security configuration for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 112." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 112." start="0x1" />
+      </BitField>
+      <BitField name="SEC113" description="security configuration for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 113." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 113." start="0x1" />
+      </BitField>
+      <BitField name="SEC114" description="security configuration for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 114." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 114." start="0x1" />
+      </BitField>
+      <BitField name="SEC115" description="security configuration for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 115." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 115." start="0x1" />
+      </BitField>
+      <BitField name="SEC116" description="security configuration for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 116." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 116." start="0x1" />
+      </BitField>
+      <BitField name="SEC117" description="security configuration for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 117." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 117." start="0x1" />
+      </BitField>
+      <BitField name="SEC118" description="security configuration for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 118." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 118." start="0x1" />
+      </BitField>
+      <BitField name="SEC119" description="security configuration for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 119." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 119." start="0x1" />
+      </BitField>
+      <BitField name="SEC120" description="security configuration for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 120." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 120." start="0x1" />
+      </BitField>
+      <BitField name="SEC121" description="security configuration for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 121." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 121." start="0x1" />
+      </BitField>
+      <BitField name="SEC122" description="security configuration for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 122." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 122." start="0x1" />
+      </BitField>
+      <BitField name="SEC123" description="security configuration for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 123." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 123." start="0x1" />
+      </BitField>
+      <BitField name="SEC124" description="security configuration for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 124." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 124." start="0x1" />
+      </BitField>
+      <BitField name="SEC125" description="security configuration for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 125." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 125." start="0x1" />
+      </BitField>
+      <BitField name="SEC126" description="security configuration for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 126." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 126." start="0x1" />
+      </BitField>
+      <BitField name="SEC127" description="security configuration for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 127." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 127." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR4" description="RIFSC RISC slave security configuration register 4" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC128" description="security configuration for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 128." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 128." start="0x1" />
+      </BitField>
+      <BitField name="SEC129" description="security configuration for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 129." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 129." start="0x1" />
+      </BitField>
+      <BitField name="SEC130" description="security configuration for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 130." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 130." start="0x1" />
+      </BitField>
+      <BitField name="SEC131" description="security configuration for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 131." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 131." start="0x1" />
+      </BitField>
+      <BitField name="SEC132" description="security configuration for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 132." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 132." start="0x1" />
+      </BitField>
+      <BitField name="SEC133" description="security configuration for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 133." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 133." start="0x1" />
+      </BitField>
+      <BitField name="SEC134" description="security configuration for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 134." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 134." start="0x1" />
+      </BitField>
+      <BitField name="SEC135" description="security configuration for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 135." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 135." start="0x1" />
+      </BitField>
+      <BitField name="SEC136" description="security configuration for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 136." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 136." start="0x1" />
+      </BitField>
+      <BitField name="SEC137" description="security configuration for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 137." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 137." start="0x1" />
+      </BitField>
+      <BitField name="SEC138" description="security configuration for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 138." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 138." start="0x1" />
+      </BitField>
+      <BitField name="SEC139" description="security configuration for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 139." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 139." start="0x1" />
+      </BitField>
+      <BitField name="SEC140" description="security configuration for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 140." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 140." start="0x1" />
+      </BitField>
+      <BitField name="SEC141" description="security configuration for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 141." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 141." start="0x1" />
+      </BitField>
+      <BitField name="SEC142" description="security configuration for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 142." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 142." start="0x1" />
+      </BitField>
+      <BitField name="SEC143" description="security configuration for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 143." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 143." start="0x1" />
+      </BitField>
+      <BitField name="SEC144" description="security configuration for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 144." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 144." start="0x1" />
+      </BitField>
+      <BitField name="SEC145" description="security configuration for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 145." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 145." start="0x1" />
+      </BitField>
+      <BitField name="SEC146" description="security configuration for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 146." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 146." start="0x1" />
+      </BitField>
+      <BitField name="SEC147" description="security configuration for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 147." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 147." start="0x1" />
+      </BitField>
+      <BitField name="SEC148" description="security configuration for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 148." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 148." start="0x1" />
+      </BitField>
+      <BitField name="SEC149" description="security configuration for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 149." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 149." start="0x1" />
+      </BitField>
+      <BitField name="SEC150" description="security configuration for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 150." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 150." start="0x1" />
+      </BitField>
+      <BitField name="SEC151" description="security configuration for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 151." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 151." start="0x1" />
+      </BitField>
+      <BitField name="SEC152" description="security configuration for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 152." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 152." start="0x1" />
+      </BitField>
+      <BitField name="SEC153" description="security configuration for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 153." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 153." start="0x1" />
+      </BitField>
+      <BitField name="SEC154" description="security configuration for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 154." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 154." start="0x1" />
+      </BitField>
+      <BitField name="SEC155" description="security configuration for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 155." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 155." start="0x1" />
+      </BitField>
+      <BitField name="SEC156" description="security configuration for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 156." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 156." start="0x1" />
+      </BitField>
+      <BitField name="SEC157" description="security configuration for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 157." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 157." start="0x1" />
+      </BitField>
+      <BitField name="SEC158" description="security configuration for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 158." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 158." start="0x1" />
+      </BitField>
+      <BitField name="SEC159" description="security configuration for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 159." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 159." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR5" description="RIFSC RISC slave security configuration register 5" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC160" description="security configuration for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 160." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 160." start="0x1" />
+      </BitField>
+      <BitField name="SEC161" description="security configuration for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 161." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 161." start="0x1" />
+      </BitField>
+      <BitField name="SEC162" description="security configuration for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 162." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 162." start="0x1" />
+      </BitField>
+      <BitField name="SEC163" description="security configuration for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 163." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 163." start="0x1" />
+      </BitField>
+      <BitField name="SEC164" description="security configuration for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 164." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 164." start="0x1" />
+      </BitField>
+      <BitField name="SEC165" description="security configuration for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 165." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 165." start="0x1" />
+      </BitField>
+      <BitField name="SEC166" description="security configuration for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 166." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 166." start="0x1" />
+      </BitField>
+      <BitField name="SEC167" description="security configuration for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 167." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 167." start="0x1" />
+      </BitField>
+      <BitField name="SEC168" description="security configuration for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 168." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 168." start="0x1" />
+      </BitField>
+      <BitField name="SEC169" description="security configuration for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 169." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 169." start="0x1" />
+      </BitField>
+      <BitField name="SEC170" description="security configuration for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 170." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 170." start="0x1" />
+      </BitField>
+      <BitField name="SEC171" description="security configuration for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 171." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 171." start="0x1" />
+      </BitField>
+      <BitField name="SEC172" description="security configuration for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 172." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 172." start="0x1" />
+      </BitField>
+      <BitField name="SEC173" description="security configuration for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 173." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 173." start="0x1" />
+      </BitField>
+      <BitField name="SEC174" description="security configuration for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 174." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 174." start="0x1" />
+      </BitField>
+      <BitField name="SEC175" description="security configuration for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 175." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 175." start="0x1" />
+      </BitField>
+      <BitField name="SEC176" description="security configuration for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 176." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 176." start="0x1" />
+      </BitField>
+      <BitField name="SEC177" description="security configuration for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 177." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 177." start="0x1" />
+      </BitField>
+      <BitField name="SEC178" description="security configuration for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 178." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 178." start="0x1" />
+      </BitField>
+      <BitField name="SEC179" description="security configuration for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 179." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 179." start="0x1" />
+      </BitField>
+      <BitField name="SEC180" description="security configuration for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 180." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 180." start="0x1" />
+      </BitField>
+      <BitField name="SEC181" description="security configuration for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 181." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 181." start="0x1" />
+      </BitField>
+      <BitField name="SEC182" description="security configuration for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 182." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 182." start="0x1" />
+      </BitField>
+      <BitField name="SEC183" description="security configuration for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 183." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 183." start="0x1" />
+      </BitField>
+      <BitField name="SEC184" description="security configuration for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 184." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 184." start="0x1" />
+      </BitField>
+      <BitField name="SEC185" description="security configuration for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 185." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 185." start="0x1" />
+      </BitField>
+      <BitField name="SEC186" description="security configuration for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 186." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 186." start="0x1" />
+      </BitField>
+      <BitField name="SEC187" description="security configuration for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 187." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 187." start="0x1" />
+      </BitField>
+      <BitField name="SEC188" description="security configuration for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 188." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 188." start="0x1" />
+      </BitField>
+      <BitField name="SEC189" description="security configuration for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 189." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 189." start="0x1" />
+      </BitField>
+      <BitField name="SEC190" description="security configuration for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 190." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 190." start="0x1" />
+      </BitField>
+      <BitField name="SEC191" description="security configuration for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 191." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 191." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR0" description="RIFSC RISFC slave privileged register 0" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged-only access permission for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 0." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 0." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged-only access permission for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 1." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 1." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged-only access permission for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 2." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 2." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged-only access permission for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 3." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 3." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged-only access permission for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 4." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 4." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged-only access permission for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 5." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 5." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged-only access permission for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 6." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 6." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged-only access permission for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 7." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 7." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged-only access permission for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 8." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 8." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged-only access permission for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 9." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 9." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged-only access permission for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 10." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 10." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged-only access permission for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 11." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 11." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged-only access permission for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 12." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 12." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged-only access permission for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 13." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 13." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged-only access permission for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 14." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 14." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged-only access permission for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 15." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 15." start="0x1" />
+      </BitField>
+      <BitField name="PRIV16" description="privileged-only access permission for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 16." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 16." start="0x1" />
+      </BitField>
+      <BitField name="PRIV17" description="privileged-only access permission for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 17." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 17." start="0x1" />
+      </BitField>
+      <BitField name="PRIV18" description="privileged-only access permission for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 18." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 18." start="0x1" />
+      </BitField>
+      <BitField name="PRIV19" description="privileged-only access permission for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 19." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 19." start="0x1" />
+      </BitField>
+      <BitField name="PRIV20" description="privileged-only access permission for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 20." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 20." start="0x1" />
+      </BitField>
+      <BitField name="PRIV21" description="privileged-only access permission for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 21." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 21." start="0x1" />
+      </BitField>
+      <BitField name="PRIV22" description="privileged-only access permission for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 22." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 22." start="0x1" />
+      </BitField>
+      <BitField name="PRIV23" description="privileged-only access permission for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 23." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 23." start="0x1" />
+      </BitField>
+      <BitField name="PRIV24" description="privileged-only access permission for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 24." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 24." start="0x1" />
+      </BitField>
+      <BitField name="PRIV25" description="privileged-only access permission for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 25." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 25." start="0x1" />
+      </BitField>
+      <BitField name="PRIV26" description="privileged-only access permission for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 26." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 26." start="0x1" />
+      </BitField>
+      <BitField name="PRIV27" description="privileged-only access permission for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 27." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 27." start="0x1" />
+      </BitField>
+      <BitField name="PRIV28" description="privileged-only access permission for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 28." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 28." start="0x1" />
+      </BitField>
+      <BitField name="PRIV29" description="privileged-only access permission for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 29." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 29." start="0x1" />
+      </BitField>
+      <BitField name="PRIV30" description="privileged-only access permission for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 30." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 30." start="0x1" />
+      </BitField>
+      <BitField name="PRIV31" description="privileged-only access permission for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 31." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 31." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR1" description="RIFSC RISFC slave privileged register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV32" description="privileged-only access permission for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 32." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 32." start="0x1" />
+      </BitField>
+      <BitField name="PRIV33" description="privileged-only access permission for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 33." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 33." start="0x1" />
+      </BitField>
+      <BitField name="PRIV34" description="privileged-only access permission for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 34." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 34." start="0x1" />
+      </BitField>
+      <BitField name="PRIV35" description="privileged-only access permission for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 35." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 35." start="0x1" />
+      </BitField>
+      <BitField name="PRIV36" description="privileged-only access permission for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 36." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 36." start="0x1" />
+      </BitField>
+      <BitField name="PRIV37" description="privileged-only access permission for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 37." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 37." start="0x1" />
+      </BitField>
+      <BitField name="PRIV38" description="privileged-only access permission for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 38." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 38." start="0x1" />
+      </BitField>
+      <BitField name="PRIV39" description="privileged-only access permission for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 39." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 39." start="0x1" />
+      </BitField>
+      <BitField name="PRIV40" description="privileged-only access permission for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 40." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 40." start="0x1" />
+      </BitField>
+      <BitField name="PRIV41" description="privileged-only access permission for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 41." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 41." start="0x1" />
+      </BitField>
+      <BitField name="PRIV42" description="privileged-only access permission for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 42." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 42." start="0x1" />
+      </BitField>
+      <BitField name="PRIV43" description="privileged-only access permission for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 43." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 43." start="0x1" />
+      </BitField>
+      <BitField name="PRIV44" description="privileged-only access permission for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 44." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 44." start="0x1" />
+      </BitField>
+      <BitField name="PRIV45" description="privileged-only access permission for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 45." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 45." start="0x1" />
+      </BitField>
+      <BitField name="PRIV46" description="privileged-only access permission for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 46." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 46." start="0x1" />
+      </BitField>
+      <BitField name="PRIV47" description="privileged-only access permission for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 47." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 47." start="0x1" />
+      </BitField>
+      <BitField name="PRIV48" description="privileged-only access permission for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 48." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 48." start="0x1" />
+      </BitField>
+      <BitField name="PRIV49" description="privileged-only access permission for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 49." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 49." start="0x1" />
+      </BitField>
+      <BitField name="PRIV50" description="privileged-only access permission for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 50." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 50." start="0x1" />
+      </BitField>
+      <BitField name="PRIV51" description="privileged-only access permission for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 51." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 51." start="0x1" />
+      </BitField>
+      <BitField name="PRIV52" description="privileged-only access permission for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 52." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 52." start="0x1" />
+      </BitField>
+      <BitField name="PRIV53" description="privileged-only access permission for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 53." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 53." start="0x1" />
+      </BitField>
+      <BitField name="PRIV54" description="privileged-only access permission for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 54." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 54." start="0x1" />
+      </BitField>
+      <BitField name="PRIV55" description="privileged-only access permission for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 55." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 55." start="0x1" />
+      </BitField>
+      <BitField name="PRIV56" description="privileged-only access permission for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 56." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 56." start="0x1" />
+      </BitField>
+      <BitField name="PRIV57" description="privileged-only access permission for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 57." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 57." start="0x1" />
+      </BitField>
+      <BitField name="PRIV58" description="privileged-only access permission for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 58." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 58." start="0x1" />
+      </BitField>
+      <BitField name="PRIV59" description="privileged-only access permission for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 59." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 59." start="0x1" />
+      </BitField>
+      <BitField name="PRIV60" description="privileged-only access permission for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 60." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 60." start="0x1" />
+      </BitField>
+      <BitField name="PRIV61" description="privileged-only access permission for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 61." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 61." start="0x1" />
+      </BitField>
+      <BitField name="PRIV62" description="privileged-only access permission for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 62." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 62." start="0x1" />
+      </BitField>
+      <BitField name="PRIV63" description="privileged-only access permission for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 63." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 63." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR2" description="RIFSC RISFC slave privileged register 2" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV64" description="privileged-only access permission for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 64." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 64." start="0x1" />
+      </BitField>
+      <BitField name="PRIV65" description="privileged-only access permission for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 65." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 65." start="0x1" />
+      </BitField>
+      <BitField name="PRIV66" description="privileged-only access permission for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 66." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 66." start="0x1" />
+      </BitField>
+      <BitField name="PRIV67" description="privileged-only access permission for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 67." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 67." start="0x1" />
+      </BitField>
+      <BitField name="PRIV68" description="privileged-only access permission for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 68." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 68." start="0x1" />
+      </BitField>
+      <BitField name="PRIV69" description="privileged-only access permission for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 69." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 69." start="0x1" />
+      </BitField>
+      <BitField name="PRIV70" description="privileged-only access permission for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 70." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 70." start="0x1" />
+      </BitField>
+      <BitField name="PRIV71" description="privileged-only access permission for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 71." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 71." start="0x1" />
+      </BitField>
+      <BitField name="PRIV72" description="privileged-only access permission for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 72." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 72." start="0x1" />
+      </BitField>
+      <BitField name="PRIV73" description="privileged-only access permission for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 73." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 73." start="0x1" />
+      </BitField>
+      <BitField name="PRIV74" description="privileged-only access permission for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 74." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 74." start="0x1" />
+      </BitField>
+      <BitField name="PRIV75" description="privileged-only access permission for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 75." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 75." start="0x1" />
+      </BitField>
+      <BitField name="PRIV76" description="privileged-only access permission for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 76." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 76." start="0x1" />
+      </BitField>
+      <BitField name="PRIV77" description="privileged-only access permission for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 77." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 77." start="0x1" />
+      </BitField>
+      <BitField name="PRIV78" description="privileged-only access permission for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 78." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 78." start="0x1" />
+      </BitField>
+      <BitField name="PRIV79" description="privileged-only access permission for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 79." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 79." start="0x1" />
+      </BitField>
+      <BitField name="PRIV80" description="privileged-only access permission for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 80." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 80." start="0x1" />
+      </BitField>
+      <BitField name="PRIV81" description="privileged-only access permission for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 81." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 81." start="0x1" />
+      </BitField>
+      <BitField name="PRIV82" description="privileged-only access permission for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 82." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 82." start="0x1" />
+      </BitField>
+      <BitField name="PRIV83" description="privileged-only access permission for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 83." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 83." start="0x1" />
+      </BitField>
+      <BitField name="PRIV84" description="privileged-only access permission for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 84." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 84." start="0x1" />
+      </BitField>
+      <BitField name="PRIV85" description="privileged-only access permission for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 85." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 85." start="0x1" />
+      </BitField>
+      <BitField name="PRIV86" description="privileged-only access permission for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 86." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 86." start="0x1" />
+      </BitField>
+      <BitField name="PRIV87" description="privileged-only access permission for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 87." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 87." start="0x1" />
+      </BitField>
+      <BitField name="PRIV88" description="privileged-only access permission for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 88." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 88." start="0x1" />
+      </BitField>
+      <BitField name="PRIV89" description="privileged-only access permission for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 89." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 89." start="0x1" />
+      </BitField>
+      <BitField name="PRIV90" description="privileged-only access permission for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 90." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 90." start="0x1" />
+      </BitField>
+      <BitField name="PRIV91" description="privileged-only access permission for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 91." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 91." start="0x1" />
+      </BitField>
+      <BitField name="PRIV92" description="privileged-only access permission for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 92." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 92." start="0x1" />
+      </BitField>
+      <BitField name="PRIV93" description="privileged-only access permission for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 93." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 93." start="0x1" />
+      </BitField>
+      <BitField name="PRIV94" description="privileged-only access permission for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 94." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 94." start="0x1" />
+      </BitField>
+      <BitField name="PRIV95" description="privileged-only access permission for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 95." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 95." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR3" description="RIFSC RISFC slave privileged register 3" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV96" description="privileged-only access permission for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 96." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 96." start="0x1" />
+      </BitField>
+      <BitField name="PRIV97" description="privileged-only access permission for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 97." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 97." start="0x1" />
+      </BitField>
+      <BitField name="PRIV98" description="privileged-only access permission for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 98." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 98." start="0x1" />
+      </BitField>
+      <BitField name="PRIV99" description="privileged-only access permission for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 99." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 99." start="0x1" />
+      </BitField>
+      <BitField name="PRIV100" description="privileged-only access permission for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 100." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 100." start="0x1" />
+      </BitField>
+      <BitField name="PRIV101" description="privileged-only access permission for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 101." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 101." start="0x1" />
+      </BitField>
+      <BitField name="PRIV102" description="privileged-only access permission for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 102." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 102." start="0x1" />
+      </BitField>
+      <BitField name="PRIV103" description="privileged-only access permission for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 103." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 103." start="0x1" />
+      </BitField>
+      <BitField name="PRIV104" description="privileged-only access permission for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 104." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 104." start="0x1" />
+      </BitField>
+      <BitField name="PRIV105" description="privileged-only access permission for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 105." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 105." start="0x1" />
+      </BitField>
+      <BitField name="PRIV106" description="privileged-only access permission for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 106." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 106." start="0x1" />
+      </BitField>
+      <BitField name="PRIV107" description="privileged-only access permission for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 107." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 107." start="0x1" />
+      </BitField>
+      <BitField name="PRIV108" description="privileged-only access permission for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 108." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 108." start="0x1" />
+      </BitField>
+      <BitField name="PRIV109" description="privileged-only access permission for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 109." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 109." start="0x1" />
+      </BitField>
+      <BitField name="PRIV110" description="privileged-only access permission for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 110." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 110." start="0x1" />
+      </BitField>
+      <BitField name="PRIV111" description="privileged-only access permission for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 111." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 111." start="0x1" />
+      </BitField>
+      <BitField name="PRIV112" description="privileged-only access permission for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 112." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 112." start="0x1" />
+      </BitField>
+      <BitField name="PRIV113" description="privileged-only access permission for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 113." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 113." start="0x1" />
+      </BitField>
+      <BitField name="PRIV114" description="privileged-only access permission for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 114." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 114." start="0x1" />
+      </BitField>
+      <BitField name="PRIV115" description="privileged-only access permission for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 115." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 115." start="0x1" />
+      </BitField>
+      <BitField name="PRIV116" description="privileged-only access permission for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 116." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 116." start="0x1" />
+      </BitField>
+      <BitField name="PRIV117" description="privileged-only access permission for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 117." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 117." start="0x1" />
+      </BitField>
+      <BitField name="PRIV118" description="privileged-only access permission for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 118." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 118." start="0x1" />
+      </BitField>
+      <BitField name="PRIV119" description="privileged-only access permission for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 119." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 119." start="0x1" />
+      </BitField>
+      <BitField name="PRIV120" description="privileged-only access permission for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 120." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 120." start="0x1" />
+      </BitField>
+      <BitField name="PRIV121" description="privileged-only access permission for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 121." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 121." start="0x1" />
+      </BitField>
+      <BitField name="PRIV122" description="privileged-only access permission for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 122." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 122." start="0x1" />
+      </BitField>
+      <BitField name="PRIV123" description="privileged-only access permission for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 123." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 123." start="0x1" />
+      </BitField>
+      <BitField name="PRIV124" description="privileged-only access permission for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 124." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 124." start="0x1" />
+      </BitField>
+      <BitField name="PRIV125" description="privileged-only access permission for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 125." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 125." start="0x1" />
+      </BitField>
+      <BitField name="PRIV126" description="privileged-only access permission for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 126." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 126." start="0x1" />
+      </BitField>
+      <BitField name="PRIV127" description="privileged-only access permission for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 127." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 127." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR4" description="RIFSC RISFC slave privileged register 4" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV128" description="privileged-only access permission for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 128." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 128." start="0x1" />
+      </BitField>
+      <BitField name="PRIV129" description="privileged-only access permission for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 129." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 129." start="0x1" />
+      </BitField>
+      <BitField name="PRIV130" description="privileged-only access permission for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 130." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 130." start="0x1" />
+      </BitField>
+      <BitField name="PRIV131" description="privileged-only access permission for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 131." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 131." start="0x1" />
+      </BitField>
+      <BitField name="PRIV132" description="privileged-only access permission for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 132." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 132." start="0x1" />
+      </BitField>
+      <BitField name="PRIV133" description="privileged-only access permission for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 133." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 133." start="0x1" />
+      </BitField>
+      <BitField name="PRIV134" description="privileged-only access permission for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 134." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 134." start="0x1" />
+      </BitField>
+      <BitField name="PRIV135" description="privileged-only access permission for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 135." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 135." start="0x1" />
+      </BitField>
+      <BitField name="PRIV136" description="privileged-only access permission for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 136." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 136." start="0x1" />
+      </BitField>
+      <BitField name="PRIV137" description="privileged-only access permission for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 137." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 137." start="0x1" />
+      </BitField>
+      <BitField name="PRIV138" description="privileged-only access permission for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 138." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 138." start="0x1" />
+      </BitField>
+      <BitField name="PRIV139" description="privileged-only access permission for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 139." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 139." start="0x1" />
+      </BitField>
+      <BitField name="PRIV140" description="privileged-only access permission for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 140." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 140." start="0x1" />
+      </BitField>
+      <BitField name="PRIV141" description="privileged-only access permission for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 141." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 141." start="0x1" />
+      </BitField>
+      <BitField name="PRIV142" description="privileged-only access permission for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 142." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 142." start="0x1" />
+      </BitField>
+      <BitField name="PRIV143" description="privileged-only access permission for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 143." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 143." start="0x1" />
+      </BitField>
+      <BitField name="PRIV144" description="privileged-only access permission for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 144." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 144." start="0x1" />
+      </BitField>
+      <BitField name="PRIV145" description="privileged-only access permission for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 145." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 145." start="0x1" />
+      </BitField>
+      <BitField name="PRIV146" description="privileged-only access permission for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 146." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 146." start="0x1" />
+      </BitField>
+      <BitField name="PRIV147" description="privileged-only access permission for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 147." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 147." start="0x1" />
+      </BitField>
+      <BitField name="PRIV148" description="privileged-only access permission for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 148." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 148." start="0x1" />
+      </BitField>
+      <BitField name="PRIV149" description="privileged-only access permission for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 149." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 149." start="0x1" />
+      </BitField>
+      <BitField name="PRIV150" description="privileged-only access permission for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 150." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 150." start="0x1" />
+      </BitField>
+      <BitField name="PRIV151" description="privileged-only access permission for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 151." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 151." start="0x1" />
+      </BitField>
+      <BitField name="PRIV152" description="privileged-only access permission for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 152." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 152." start="0x1" />
+      </BitField>
+      <BitField name="PRIV153" description="privileged-only access permission for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 153." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 153." start="0x1" />
+      </BitField>
+      <BitField name="PRIV154" description="privileged-only access permission for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 154." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 154." start="0x1" />
+      </BitField>
+      <BitField name="PRIV155" description="privileged-only access permission for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 155." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 155." start="0x1" />
+      </BitField>
+      <BitField name="PRIV156" description="privileged-only access permission for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 156." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 156." start="0x1" />
+      </BitField>
+      <BitField name="PRIV157" description="privileged-only access permission for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 157." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 157." start="0x1" />
+      </BitField>
+      <BitField name="PRIV158" description="privileged-only access permission for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 158." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 158." start="0x1" />
+      </BitField>
+      <BitField name="PRIV159" description="privileged-only access permission for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 159." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 159." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR5" description="RIFSC RISFC slave privileged register 5" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV160" description="privileged-only access permission for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 160." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 160." start="0x1" />
+      </BitField>
+      <BitField name="PRIV161" description="privileged-only access permission for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 161." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 161." start="0x1" />
+      </BitField>
+      <BitField name="PRIV162" description="privileged-only access permission for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 162." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 162." start="0x1" />
+      </BitField>
+      <BitField name="PRIV163" description="privileged-only access permission for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 163." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 163." start="0x1" />
+      </BitField>
+      <BitField name="PRIV164" description="privileged-only access permission for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 164." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 164." start="0x1" />
+      </BitField>
+      <BitField name="PRIV165" description="privileged-only access permission for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 165." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 165." start="0x1" />
+      </BitField>
+      <BitField name="PRIV166" description="privileged-only access permission for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 166." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 166." start="0x1" />
+      </BitField>
+      <BitField name="PRIV167" description="privileged-only access permission for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 167." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 167." start="0x1" />
+      </BitField>
+      <BitField name="PRIV168" description="privileged-only access permission for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 168." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 168." start="0x1" />
+      </BitField>
+      <BitField name="PRIV169" description="privileged-only access permission for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 169." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 169." start="0x1" />
+      </BitField>
+      <BitField name="PRIV170" description="privileged-only access permission for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 170." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 170." start="0x1" />
+      </BitField>
+      <BitField name="PRIV171" description="privileged-only access permission for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 171." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 171." start="0x1" />
+      </BitField>
+      <BitField name="PRIV172" description="privileged-only access permission for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 172." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 172." start="0x1" />
+      </BitField>
+      <BitField name="PRIV173" description="privileged-only access permission for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 173." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 173." start="0x1" />
+      </BitField>
+      <BitField name="PRIV174" description="privileged-only access permission for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 174." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 174." start="0x1" />
+      </BitField>
+      <BitField name="PRIV175" description="privileged-only access permission for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 175." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 175." start="0x1" />
+      </BitField>
+      <BitField name="PRIV176" description="privileged-only access permission for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 176." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 176." start="0x1" />
+      </BitField>
+      <BitField name="PRIV177" description="privileged-only access permission for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 177." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 177." start="0x1" />
+      </BitField>
+      <BitField name="PRIV178" description="privileged-only access permission for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 178." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 178." start="0x1" />
+      </BitField>
+      <BitField name="PRIV179" description="privileged-only access permission for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 179." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 179." start="0x1" />
+      </BitField>
+      <BitField name="PRIV180" description="privileged-only access permission for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 180." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 180." start="0x1" />
+      </BitField>
+      <BitField name="PRIV181" description="privileged-only access permission for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 181." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 181." start="0x1" />
+      </BitField>
+      <BitField name="PRIV182" description="privileged-only access permission for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 182." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 182." start="0x1" />
+      </BitField>
+      <BitField name="PRIV183" description="privileged-only access permission for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 183." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 183." start="0x1" />
+      </BitField>
+      <BitField name="PRIV184" description="privileged-only access permission for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 184." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 184." start="0x1" />
+      </BitField>
+      <BitField name="PRIV185" description="privileged-only access permission for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 185." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 185." start="0x1" />
+      </BitField>
+      <BitField name="PRIV186" description="privileged-only access permission for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 186." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 186." start="0x1" />
+      </BitField>
+      <BitField name="PRIV187" description="privileged-only access permission for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 187." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 187." start="0x1" />
+      </BitField>
+      <BitField name="PRIV188" description="privileged-only access permission for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 188." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 188." start="0x1" />
+      </BitField>
+      <BitField name="PRIV189" description="privileged-only access permission for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 189." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 189." start="0x1" />
+      </BitField>
+      <BitField name="PRIV190" description="privileged-only access permission for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 190." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 190." start="0x1" />
+      </BitField>
+      <BitField name="PRIV191" description="privileged-only access permission for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 191." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 191." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR0" description="RIFSC RISC slave resource configuration lock register 0" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="resource lock for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC0 in RIFSC_RISC_SECCFGRx and PRIV0 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC0 and PRIV0 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="resource lock for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC1 in RIFSC_RISC_SECCFGRx and PRIV1 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC1 and PRIV1 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="resource lock for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC2 in RIFSC_RISC_SECCFGRx and PRIV2 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC2 and PRIV2 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="resource lock for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC3 in RIFSC_RISC_SECCFGRx and PRIV3 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC3 and PRIV3 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="resource lock for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC4 in RIFSC_RISC_SECCFGRx and PRIV4 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC4 and PRIV4 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="resource lock for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC5 in RIFSC_RISC_SECCFGRx and PRIV5 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC5 and PRIV5 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="resource lock for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC6 in RIFSC_RISC_SECCFGRx and PRIV6 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC6 and PRIV6 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="resource lock for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC7 in RIFSC_RISC_SECCFGRx and PRIV7 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC7 and PRIV7 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="resource lock for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC8 in RIFSC_RISC_SECCFGRx and PRIV8 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC8 and PRIV8 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="resource lock for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC9 in RIFSC_RISC_SECCFGRx and PRIV9 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC9 and PRIV9 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="resource lock for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC10 in RIFSC_RISC_SECCFGRx and PRIV10 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC10 and PRIV10 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="resource lock for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC11 in RIFSC_RISC_SECCFGRx and PRIV11 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC11 and PRIV11 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="resource lock for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC12 in RIFSC_RISC_SECCFGRx and PRIV12 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC12 and PRIV12 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="resource lock for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC13 in RIFSC_RISC_SECCFGRx and PRIV13 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC13 and PRIV13 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="resource lock for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC14 in RIFSC_RISC_SECCFGRx and PRIV14 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC14 and PRIV14 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="resource lock for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC15 in RIFSC_RISC_SECCFGRx and PRIV15 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC15 and PRIV15 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK16" description="resource lock for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC16 in RIFSC_RISC_SECCFGRx and PRIV16 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC16 and PRIV16 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK17" description="resource lock for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC17 in RIFSC_RISC_SECCFGRx and PRIV17 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC17 and PRIV17 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK18" description="resource lock for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC18 in RIFSC_RISC_SECCFGRx and PRIV18 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC18 and PRIV18 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK19" description="resource lock for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC19 in RIFSC_RISC_SECCFGRx and PRIV19 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC19 and PRIV19 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK20" description="resource lock for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC20 in RIFSC_RISC_SECCFGRx and PRIV20 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC20 and PRIV20 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK21" description="resource lock for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC21 in RIFSC_RISC_SECCFGRx and PRIV21 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC21 and PRIV21 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK22" description="resource lock for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC22 in RIFSC_RISC_SECCFGRx and PRIV22 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC22 and PRIV22 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK23" description="resource lock for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC23 in RIFSC_RISC_SECCFGRx and PRIV23 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC23 and PRIV23 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK24" description="resource lock for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC24 in RIFSC_RISC_SECCFGRx and PRIV24 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC24 and PRIV24 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK25" description="resource lock for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC25 in RIFSC_RISC_SECCFGRx and PRIV25 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC25 and PRIV25 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK26" description="resource lock for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC26 in RIFSC_RISC_SECCFGRx and PRIV26 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC26 and PRIV26 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK27" description="resource lock for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC27 in RIFSC_RISC_SECCFGRx and PRIV27 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC27 and PRIV27 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK28" description="resource lock for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC28 in RIFSC_RISC_SECCFGRx and PRIV28 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC28 and PRIV28 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK29" description="resource lock for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC29 in RIFSC_RISC_SECCFGRx and PRIV29 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC29 and PRIV29 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK30" description="resource lock for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC30 in RIFSC_RISC_SECCFGRx and PRIV30 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC30 and PRIV30 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK31" description="resource lock for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC31 in RIFSC_RISC_SECCFGRx and PRIV31 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC31 and PRIV31 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR1" description="RIFSC RISC slave resource configuration lock register 1" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK32" description="resource lock for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC32 in RIFSC_RISC_SECCFGRx and PRIV32 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC32 and PRIV32 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK33" description="resource lock for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC33 in RIFSC_RISC_SECCFGRx and PRIV33 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC33 and PRIV33 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK34" description="resource lock for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC34 in RIFSC_RISC_SECCFGRx and PRIV34 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC34 and PRIV34 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK35" description="resource lock for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC35 in RIFSC_RISC_SECCFGRx and PRIV35 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC35 and PRIV35 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK36" description="resource lock for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC36 in RIFSC_RISC_SECCFGRx and PRIV36 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC36 and PRIV36 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK37" description="resource lock for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC37 in RIFSC_RISC_SECCFGRx and PRIV37 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC37 and PRIV37 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK38" description="resource lock for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC38 in RIFSC_RISC_SECCFGRx and PRIV38 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC38 and PRIV38 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK39" description="resource lock for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC39 in RIFSC_RISC_SECCFGRx and PRIV39 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC39 and PRIV39 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK40" description="resource lock for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC40 in RIFSC_RISC_SECCFGRx and PRIV40 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC40 and PRIV40 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK41" description="resource lock for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC41 in RIFSC_RISC_SECCFGRx and PRIV41 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC41 and PRIV41 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK42" description="resource lock for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC42 in RIFSC_RISC_SECCFGRx and PRIV42 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC42 and PRIV42 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK43" description="resource lock for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC43 in RIFSC_RISC_SECCFGRx and PRIV43 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC43 and PRIV43 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK44" description="resource lock for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC44 in RIFSC_RISC_SECCFGRx and PRIV44 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC44 and PRIV44 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK45" description="resource lock for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC45 in RIFSC_RISC_SECCFGRx and PRIV45 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC45 and PRIV45 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK46" description="resource lock for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC46 in RIFSC_RISC_SECCFGRx and PRIV46 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC46 and PRIV46 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK47" description="resource lock for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC47 in RIFSC_RISC_SECCFGRx and PRIV47 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC47 and PRIV47 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK48" description="resource lock for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC48 in RIFSC_RISC_SECCFGRx and PRIV48 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC48 and PRIV48 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK49" description="resource lock for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC49 in RIFSC_RISC_SECCFGRx and PRIV49 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC49 and PRIV49 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK50" description="resource lock for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC50 in RIFSC_RISC_SECCFGRx and PRIV50 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC50 and PRIV50 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK51" description="resource lock for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC51 in RIFSC_RISC_SECCFGRx and PRIV51 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC51 and PRIV51 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK52" description="resource lock for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC52 in RIFSC_RISC_SECCFGRx and PRIV52 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC52 and PRIV52 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK53" description="resource lock for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC53 in RIFSC_RISC_SECCFGRx and PRIV53 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC53 and PRIV53 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK54" description="resource lock for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC54 in RIFSC_RISC_SECCFGRx and PRIV54 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC54 and PRIV54 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK55" description="resource lock for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC55 in RIFSC_RISC_SECCFGRx and PRIV55 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC55 and PRIV55 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK56" description="resource lock for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC56 in RIFSC_RISC_SECCFGRx and PRIV56 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC56 and PRIV56 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK57" description="resource lock for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC57 in RIFSC_RISC_SECCFGRx and PRIV57 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC57 and PRIV57 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK58" description="resource lock for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC58 in RIFSC_RISC_SECCFGRx and PRIV58 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC58 and PRIV58 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK59" description="resource lock for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC59 in RIFSC_RISC_SECCFGRx and PRIV59 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC59 and PRIV59 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK60" description="resource lock for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC60 in RIFSC_RISC_SECCFGRx and PRIV60 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC60 and PRIV60 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK61" description="resource lock for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC61 in RIFSC_RISC_SECCFGRx and PRIV61 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC61 and PRIV61 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK62" description="resource lock for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC62 in RIFSC_RISC_SECCFGRx and PRIV62 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC62 and PRIV62 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK63" description="resource lock for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC63 in RIFSC_RISC_SECCFGRx and PRIV63 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC63 and PRIV63 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR2" description="RIFSC RISC slave resource configuration lock register 2" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK64" description="resource lock for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC64 in RIFSC_RISC_SECCFGRx and PRIV64 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC64 and PRIV64 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK65" description="resource lock for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC65 in RIFSC_RISC_SECCFGRx and PRIV65 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC65 and PRIV65 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK66" description="resource lock for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC66 in RIFSC_RISC_SECCFGRx and PRIV66 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC66 and PRIV66 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK67" description="resource lock for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC67 in RIFSC_RISC_SECCFGRx and PRIV67 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC67 and PRIV67 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK68" description="resource lock for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC68 in RIFSC_RISC_SECCFGRx and PRIV68 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC68 and PRIV68 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK69" description="resource lock for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC69 in RIFSC_RISC_SECCFGRx and PRIV69 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC69 and PRIV69 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK70" description="resource lock for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC70 in RIFSC_RISC_SECCFGRx and PRIV70 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC70 and PRIV70 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK71" description="resource lock for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC71 in RIFSC_RISC_SECCFGRx and PRIV71 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC71 and PRIV71 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK72" description="resource lock for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC72 in RIFSC_RISC_SECCFGRx and PRIV72 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC72 and PRIV72 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK73" description="resource lock for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC73 in RIFSC_RISC_SECCFGRx and PRIV73 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC73 and PRIV73 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK74" description="resource lock for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC74 in RIFSC_RISC_SECCFGRx and PRIV74 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC74 and PRIV74 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK75" description="resource lock for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC75 in RIFSC_RISC_SECCFGRx and PRIV75 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC75 and PRIV75 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK76" description="resource lock for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC76 in RIFSC_RISC_SECCFGRx and PRIV76 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC76 and PRIV76 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK77" description="resource lock for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC77 in RIFSC_RISC_SECCFGRx and PRIV77 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC77 and PRIV77 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK78" description="resource lock for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC78 in RIFSC_RISC_SECCFGRx and PRIV78 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC78 and PRIV78 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK79" description="resource lock for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC79 in RIFSC_RISC_SECCFGRx and PRIV79 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC79 and PRIV79 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK80" description="resource lock for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC80 in RIFSC_RISC_SECCFGRx and PRIV80 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC80 and PRIV80 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK81" description="resource lock for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC81 in RIFSC_RISC_SECCFGRx and PRIV81 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC81 and PRIV81 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK82" description="resource lock for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC82 in RIFSC_RISC_SECCFGRx and PRIV82 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC82 and PRIV82 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK83" description="resource lock for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC83 in RIFSC_RISC_SECCFGRx and PRIV83 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC83 and PRIV83 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK84" description="resource lock for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC84 in RIFSC_RISC_SECCFGRx and PRIV84 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC84 and PRIV84 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK85" description="resource lock for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC85 in RIFSC_RISC_SECCFGRx and PRIV85 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC85 and PRIV85 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK86" description="resource lock for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC86 in RIFSC_RISC_SECCFGRx and PRIV86 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC86 and PRIV86 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK87" description="resource lock for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC87 in RIFSC_RISC_SECCFGRx and PRIV87 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC87 and PRIV87 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK88" description="resource lock for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC88 in RIFSC_RISC_SECCFGRx and PRIV88 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC88 and PRIV88 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK89" description="resource lock for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC89 in RIFSC_RISC_SECCFGRx and PRIV89 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC89 and PRIV89 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK90" description="resource lock for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC90 in RIFSC_RISC_SECCFGRx and PRIV90 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC90 and PRIV90 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK91" description="resource lock for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC91 in RIFSC_RISC_SECCFGRx and PRIV91 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC91 and PRIV91 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK92" description="resource lock for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC92 in RIFSC_RISC_SECCFGRx and PRIV92 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC92 and PRIV92 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK93" description="resource lock for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC93 in RIFSC_RISC_SECCFGRx and PRIV93 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC93 and PRIV93 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK94" description="resource lock for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC94 in RIFSC_RISC_SECCFGRx and PRIV94 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC94 and PRIV94 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK95" description="resource lock for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC95 in RIFSC_RISC_SECCFGRx and PRIV95 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC95 and PRIV95 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR3" description="RIFSC RISC slave resource configuration lock register 3" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK96" description="resource lock for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC96 in RIFSC_RISC_SECCFGRx and PRIV96 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC96 and PRIV96 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK97" description="resource lock for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC97 in RIFSC_RISC_SECCFGRx and PRIV97 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC97 and PRIV97 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK98" description="resource lock for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC98 in RIFSC_RISC_SECCFGRx and PRIV98 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC98 and PRIV98 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK99" description="resource lock for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC99 in RIFSC_RISC_SECCFGRx and PRIV99 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC99 and PRIV99 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK100" description="resource lock for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC100 in RIFSC_RISC_SECCFGRx and PRIV100 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC100 and PRIV100 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK101" description="resource lock for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC101 in RIFSC_RISC_SECCFGRx and PRIV101 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC101 and PRIV101 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK102" description="resource lock for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC102 in RIFSC_RISC_SECCFGRx and PRIV102 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC102 and PRIV102 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK103" description="resource lock for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC103 in RIFSC_RISC_SECCFGRx and PRIV103 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC103 and PRIV103 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK104" description="resource lock for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC104 in RIFSC_RISC_SECCFGRx and PRIV104 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC104 and PRIV104 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK105" description="resource lock for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC105 in RIFSC_RISC_SECCFGRx and PRIV105 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC105 and PRIV105 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK106" description="resource lock for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC106 in RIFSC_RISC_SECCFGRx and PRIV106 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC106 and PRIV106 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK107" description="resource lock for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC107 in RIFSC_RISC_SECCFGRx and PRIV107 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC107 and PRIV107 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK108" description="resource lock for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC108 in RIFSC_RISC_SECCFGRx and PRIV108 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC108 and PRIV108 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK109" description="resource lock for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC109 in RIFSC_RISC_SECCFGRx and PRIV109 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC109 and PRIV109 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK110" description="resource lock for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC110 in RIFSC_RISC_SECCFGRx and PRIV110 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC110 and PRIV110 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK111" description="resource lock for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC111 in RIFSC_RISC_SECCFGRx and PRIV111 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC111 and PRIV111 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK112" description="resource lock for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC112 in RIFSC_RISC_SECCFGRx and PRIV112 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC112 and PRIV112 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK113" description="resource lock for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC113 in RIFSC_RISC_SECCFGRx and PRIV113 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC113 and PRIV113 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK114" description="resource lock for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC114 in RIFSC_RISC_SECCFGRx and PRIV114 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC114 and PRIV114 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK115" description="resource lock for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC115 in RIFSC_RISC_SECCFGRx and PRIV115 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC115 and PRIV115 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK116" description="resource lock for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC116 in RIFSC_RISC_SECCFGRx and PRIV116 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC116 and PRIV116 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK117" description="resource lock for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC117 in RIFSC_RISC_SECCFGRx and PRIV117 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC117 and PRIV117 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK118" description="resource lock for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC118 in RIFSC_RISC_SECCFGRx and PRIV118 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC118 and PRIV118 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK119" description="resource lock for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC119 in RIFSC_RISC_SECCFGRx and PRIV119 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC119 and PRIV119 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK120" description="resource lock for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC120 in RIFSC_RISC_SECCFGRx and PRIV120 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC120 and PRIV120 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK121" description="resource lock for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC121 in RIFSC_RISC_SECCFGRx and PRIV121 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC121 and PRIV121 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK122" description="resource lock for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC122 in RIFSC_RISC_SECCFGRx and PRIV122 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC122 and PRIV122 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK123" description="resource lock for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC123 in RIFSC_RISC_SECCFGRx and PRIV123 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC123 and PRIV123 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK124" description="resource lock for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC124 in RIFSC_RISC_SECCFGRx and PRIV124 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC124 and PRIV124 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK125" description="resource lock for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC125 in RIFSC_RISC_SECCFGRx and PRIV125 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC125 and PRIV125 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK126" description="resource lock for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC126 in RIFSC_RISC_SECCFGRx and PRIV126 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC126 and PRIV126 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK127" description="resource lock for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC127 in RIFSC_RISC_SECCFGRx and PRIV127 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC127 and PRIV127 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR4" description="RIFSC RISC slave resource configuration lock register 4" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK128" description="resource lock for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC128 in RIFSC_RISC_SECCFGRx and PRIV128 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC128 and PRIV128 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK129" description="resource lock for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC129 in RIFSC_RISC_SECCFGRx and PRIV129 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC129 and PRIV129 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK130" description="resource lock for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC130 in RIFSC_RISC_SECCFGRx and PRIV130 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC130 and PRIV130 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK131" description="resource lock for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC131 in RIFSC_RISC_SECCFGRx and PRIV131 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC131 and PRIV131 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK132" description="resource lock for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC132 in RIFSC_RISC_SECCFGRx and PRIV132 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC132 and PRIV132 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK133" description="resource lock for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC133 in RIFSC_RISC_SECCFGRx and PRIV133 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC133 and PRIV133 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK134" description="resource lock for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC134 in RIFSC_RISC_SECCFGRx and PRIV134 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC134 and PRIV134 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK135" description="resource lock for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC135 in RIFSC_RISC_SECCFGRx and PRIV135 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC135 and PRIV135 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK136" description="resource lock for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC136 in RIFSC_RISC_SECCFGRx and PRIV136 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC136 and PRIV136 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK137" description="resource lock for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC137 in RIFSC_RISC_SECCFGRx and PRIV137 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC137 and PRIV137 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK138" description="resource lock for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC138 in RIFSC_RISC_SECCFGRx and PRIV138 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC138 and PRIV138 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK139" description="resource lock for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC139 in RIFSC_RISC_SECCFGRx and PRIV139 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC139 and PRIV139 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK140" description="resource lock for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC140 in RIFSC_RISC_SECCFGRx and PRIV140 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC140 and PRIV140 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK141" description="resource lock for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC141 in RIFSC_RISC_SECCFGRx and PRIV141 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC141 and PRIV141 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK142" description="resource lock for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC142 in RIFSC_RISC_SECCFGRx and PRIV142 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC142 and PRIV142 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK143" description="resource lock for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC143 in RIFSC_RISC_SECCFGRx and PRIV143 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC143 and PRIV143 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK144" description="resource lock for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC144 in RIFSC_RISC_SECCFGRx and PRIV144 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC144 and PRIV144 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK145" description="resource lock for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC145 in RIFSC_RISC_SECCFGRx and PRIV145 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC145 and PRIV145 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK146" description="resource lock for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC146 in RIFSC_RISC_SECCFGRx and PRIV146 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC146 and PRIV146 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK147" description="resource lock for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC147 in RIFSC_RISC_SECCFGRx and PRIV147 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC147 and PRIV147 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK148" description="resource lock for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC148 in RIFSC_RISC_SECCFGRx and PRIV148 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC148 and PRIV148 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK149" description="resource lock for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC149 in RIFSC_RISC_SECCFGRx and PRIV149 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC149 and PRIV149 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK150" description="resource lock for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC150 in RIFSC_RISC_SECCFGRx and PRIV150 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC150 and PRIV150 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK151" description="resource lock for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC151 in RIFSC_RISC_SECCFGRx and PRIV151 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC151 and PRIV151 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK152" description="resource lock for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC152 in RIFSC_RISC_SECCFGRx and PRIV152 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC152 and PRIV152 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK153" description="resource lock for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC153 in RIFSC_RISC_SECCFGRx and PRIV153 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC153 and PRIV153 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK154" description="resource lock for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC154 in RIFSC_RISC_SECCFGRx and PRIV154 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC154 and PRIV154 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK155" description="resource lock for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC155 in RIFSC_RISC_SECCFGRx and PRIV155 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC155 and PRIV155 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK156" description="resource lock for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC156 in RIFSC_RISC_SECCFGRx and PRIV156 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC156 and PRIV156 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK157" description="resource lock for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC157 in RIFSC_RISC_SECCFGRx and PRIV157 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC157 and PRIV157 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK158" description="resource lock for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC158 in RIFSC_RISC_SECCFGRx and PRIV158 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC158 and PRIV158 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK159" description="resource lock for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC159 in RIFSC_RISC_SECCFGRx and PRIV159 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC159 and PRIV159 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR5" description="RIFSC RISC slave resource configuration lock register 5" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK160" description="resource lock for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC160 in RIFSC_RISC_SECCFGRx and PRIV160 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC160 and PRIV160 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK161" description="resource lock for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC161 in RIFSC_RISC_SECCFGRx and PRIV161 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC161 and PRIV161 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK162" description="resource lock for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC162 in RIFSC_RISC_SECCFGRx and PRIV162 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC162 and PRIV162 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK163" description="resource lock for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC163 in RIFSC_RISC_SECCFGRx and PRIV163 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC163 and PRIV163 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK164" description="resource lock for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC164 in RIFSC_RISC_SECCFGRx and PRIV164 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC164 and PRIV164 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK165" description="resource lock for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC165 in RIFSC_RISC_SECCFGRx and PRIV165 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC165 and PRIV165 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK166" description="resource lock for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC166 in RIFSC_RISC_SECCFGRx and PRIV166 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC166 and PRIV166 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK167" description="resource lock for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC167 in RIFSC_RISC_SECCFGRx and PRIV167 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC167 and PRIV167 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK168" description="resource lock for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC168 in RIFSC_RISC_SECCFGRx and PRIV168 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC168 and PRIV168 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK169" description="resource lock for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC169 in RIFSC_RISC_SECCFGRx and PRIV169 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC169 and PRIV169 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK170" description="resource lock for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC170 in RIFSC_RISC_SECCFGRx and PRIV170 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC170 and PRIV170 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK171" description="resource lock for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC171 in RIFSC_RISC_SECCFGRx and PRIV171 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC171 and PRIV171 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK172" description="resource lock for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC172 in RIFSC_RISC_SECCFGRx and PRIV172 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC172 and PRIV172 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK173" description="resource lock for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC173 in RIFSC_RISC_SECCFGRx and PRIV173 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC173 and PRIV173 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK174" description="resource lock for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC174 in RIFSC_RISC_SECCFGRx and PRIV174 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC174 and PRIV174 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK175" description="resource lock for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC175 in RIFSC_RISC_SECCFGRx and PRIV175 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC175 and PRIV175 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK176" description="resource lock for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC176 in RIFSC_RISC_SECCFGRx and PRIV176 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC176 and PRIV176 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK177" description="resource lock for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC177 in RIFSC_RISC_SECCFGRx and PRIV177 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC177 and PRIV177 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK178" description="resource lock for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC178 in RIFSC_RISC_SECCFGRx and PRIV178 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC178 and PRIV178 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK179" description="resource lock for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC179 in RIFSC_RISC_SECCFGRx and PRIV179 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC179 and PRIV179 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK180" description="resource lock for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC180 in RIFSC_RISC_SECCFGRx and PRIV180 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC180 and PRIV180 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK181" description="resource lock for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC181 in RIFSC_RISC_SECCFGRx and PRIV181 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC181 and PRIV181 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK182" description="resource lock for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC182 in RIFSC_RISC_SECCFGRx and PRIV182 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC182 and PRIV182 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK183" description="resource lock for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC183 in RIFSC_RISC_SECCFGRx and PRIV183 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC183 and PRIV183 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK184" description="resource lock for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC184 in RIFSC_RISC_SECCFGRx and PRIV184 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC184 and PRIV184 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK185" description="resource lock for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC185 in RIFSC_RISC_SECCFGRx and PRIV185 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC185 and PRIV185 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK186" description="resource lock for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC186 in RIFSC_RISC_SECCFGRx and PRIV186 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC186 and PRIV186 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK187" description="resource lock for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC187 in RIFSC_RISC_SECCFGRx and PRIV187 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC187 and PRIV187 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK188" description="resource lock for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC188 in RIFSC_RISC_SECCFGRx and PRIV188 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC188 and PRIV188 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK189" description="resource lock for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC189 in RIFSC_RISC_SECCFGRx and PRIV189 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC189 and PRIV189 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK190" description="resource lock for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC190 in RIFSC_RISC_SECCFGRx and PRIV190 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC190 and PRIV190 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK191" description="resource lock for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC191 in RIFSC_RISC_SECCFGRx and PRIV191 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC191 and PRIV191 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_CR" description="RIFSC RIMC master configuration register" start="+0xC00" size="4" reset_value="0x00000710" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC RIMC registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RIFSC RIMC registers are ignored." start="0x1" />
+      </BitField>
+      <BitField name="DAPCID" description="debug access port compartment ID" start="8" size="3" access="Read/Write" />
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR0" description="RIFSC RIMC master attribute register 0" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR1" description="RIFSC RIMC master attribute register 1" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR2" description="RIFSC RIMC master attribute register 2" start="+0xC18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR3" description="RIFSC RIMC master attribute register 3" start="+0xC1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR4" description="RIFSC RIMC master attribute register 4" start="+0xC20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR5" description="RIFSC RIMC master attribute register 5" start="+0xC24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR6" description="RIFSC RIMC master attribute register 6" start="+0xC28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR7" description="RIFSC RIMC master attribute register 7" start="+0xC2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR8" description="RIFSC RIMC master attribute register 8" start="+0xC30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR9" description="RIFSC RIMC master attribute register 9" start="+0xC34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR10" description="RIFSC RIMC master attribute register 10" start="+0xC38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR11" description="RIFSC RIMC master attribute register 11" start="+0xC3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR0" description="RIFSC peripheral protection status register 0" start="+0xFB0" size="4" reset_value="0xFFFFFF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN0" description="peripheral protection enable 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC0, PRIV0, and RLOCK0 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC0, PRIV0, and RLOCK0 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN1" description="peripheral protection enable 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC1, PRIV1, and RLOCK1 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC1, PRIV1, and RLOCK1 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN2" description="peripheral protection enable 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC2, PRIV2, and RLOCK2 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC2, PRIV2, and RLOCK2 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN3" description="peripheral protection enable 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC3, PRIV3, and RLOCK3 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC3, PRIV3, and RLOCK3 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN4" description="peripheral protection enable 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC4, PRIV4, and RLOCK4 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC4, PRIV4, and RLOCK4 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN5" description="peripheral protection enable 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC5, PRIV5, and RLOCK5 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC5, PRIV5, and RLOCK5 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN6" description="peripheral protection enable 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC6, PRIV6, and RLOCK6 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC6, PRIV6, and RLOCK6 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN7" description="peripheral protection enable 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC7, PRIV7, and RLOCK7 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC7, PRIV7, and RLOCK7 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN8" description="peripheral protection enable 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC8, PRIV8, and RLOCK8 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC8, PRIV8, and RLOCK8 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN9" description="peripheral protection enable 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC9, PRIV9, and RLOCK9 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC9, PRIV9, and RLOCK9 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN10" description="peripheral protection enable 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC10, PRIV10, and RLOCK10 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC10, PRIV10, and RLOCK10 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN11" description="peripheral protection enable 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC11, PRIV11, and RLOCK11 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC11, PRIV11, and RLOCK11 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN12" description="peripheral protection enable 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC12, PRIV12, and RLOCK12 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC12, PRIV12, and RLOCK12 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN13" description="peripheral protection enable 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC13, PRIV13, and RLOCK13 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC13, PRIV13, and RLOCK13 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN14" description="peripheral protection enable 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC14, PRIV14, and RLOCK14 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC14, PRIV14, and RLOCK14 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN15" description="peripheral protection enable 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC15, PRIV15, and RLOCK15 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC15, PRIV15, and RLOCK15 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN16" description="peripheral protection enable 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC16, PRIV16, and RLOCK16 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC16, PRIV16, and RLOCK16 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN17" description="peripheral protection enable 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC17, PRIV17, and RLOCK17 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC17, PRIV17, and RLOCK17 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN18" description="peripheral protection enable 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC18, PRIV18, and RLOCK18 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC18, PRIV18, and RLOCK18 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN19" description="peripheral protection enable 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC19, PRIV19, and RLOCK19 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC19, PRIV19, and RLOCK19 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN20" description="peripheral protection enable 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC20, PRIV20, and RLOCK20 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC20, PRIV20, and RLOCK20 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN21" description="peripheral protection enable 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC21, PRIV21, and RLOCK21 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC21, PRIV21, and RLOCK21 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN22" description="peripheral protection enable 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC22, PRIV22, and RLOCK22 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC22, PRIV22, and RLOCK22 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN23" description="peripheral protection enable 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC23, PRIV23, and RLOCK23 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC23, PRIV23, and RLOCK23 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN24" description="peripheral protection enable 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC24, PRIV24, and RLOCK24 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC24, PRIV24, and RLOCK24 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN25" description="peripheral protection enable 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC25, PRIV25, and RLOCK25 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC25, PRIV25, and RLOCK25 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN26" description="peripheral protection enable 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC26, PRIV26, and RLOCK26 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC26, PRIV26, and RLOCK26 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN27" description="peripheral protection enable 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC27, PRIV27, and RLOCK27 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC27, PRIV27, and RLOCK27 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN28" description="peripheral protection enable 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC28, PRIV28, and RLOCK28 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC28, PRIV28, and RLOCK28 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN29" description="peripheral protection enable 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC29, PRIV29, and RLOCK29 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC29, PRIV29, and RLOCK29 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN30" description="peripheral protection enable 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC30, PRIV30, and RLOCK30 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC30, PRIV30, and RLOCK30 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN31" description="peripheral protection enable 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC31, PRIV31, and RLOCK31 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC31, PRIV31, and RLOCK31 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR1" description="RIFSC peripheral protection status register 1" start="+0xFB4" size="4" reset_value="0x77FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN32" description="peripheral protection enable 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC32, PRIV32, and RLOCK32 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC32, PRIV32, and RLOCK32 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN33" description="peripheral protection enable 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC33, PRIV33, and RLOCK33 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC33, PRIV33, and RLOCK33 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN34" description="peripheral protection enable 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC34, PRIV34, and RLOCK34 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC34, PRIV34, and RLOCK34 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN35" description="peripheral protection enable 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC35, PRIV35, and RLOCK35 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC35, PRIV35, and RLOCK35 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN36" description="peripheral protection enable 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC36, PRIV36, and RLOCK36 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC36, PRIV36, and RLOCK36 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN37" description="peripheral protection enable 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC37, PRIV37, and RLOCK37 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC37, PRIV37, and RLOCK37 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN38" description="peripheral protection enable 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC38, PRIV38, and RLOCK38 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC38, PRIV38, and RLOCK38 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN39" description="peripheral protection enable 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC39, PRIV39, and RLOCK39 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC39, PRIV39, and RLOCK39 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN40" description="peripheral protection enable 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC40, PRIV40, and RLOCK40 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC40, PRIV40, and RLOCK40 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN41" description="peripheral protection enable 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC41, PRIV41, and RLOCK41 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC41, PRIV41, and RLOCK41 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN42" description="peripheral protection enable 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC42, PRIV42, and RLOCK42 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC42, PRIV42, and RLOCK42 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN43" description="peripheral protection enable 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC43, PRIV43, and RLOCK43 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC43, PRIV43, and RLOCK43 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN44" description="peripheral protection enable 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC44, PRIV44, and RLOCK44 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC44, PRIV44, and RLOCK44 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN45" description="peripheral protection enable 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC45, PRIV45, and RLOCK45 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC45, PRIV45, and RLOCK45 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN46" description="peripheral protection enable 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC46, PRIV46, and RLOCK46 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC46, PRIV46, and RLOCK46 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN47" description="peripheral protection enable 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC47, PRIV47, and RLOCK47 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC47, PRIV47, and RLOCK47 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN48" description="peripheral protection enable 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC48, PRIV48, and RLOCK48 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC48, PRIV48, and RLOCK48 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN49" description="peripheral protection enable 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC49, PRIV49, and RLOCK49 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC49, PRIV49, and RLOCK49 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN50" description="peripheral protection enable 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC50, PRIV50, and RLOCK50 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC50, PRIV50, and RLOCK50 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN51" description="peripheral protection enable 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC51, PRIV51, and RLOCK51 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC51, PRIV51, and RLOCK51 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN52" description="peripheral protection enable 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC52, PRIV52, and RLOCK52 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC52, PRIV52, and RLOCK52 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN53" description="peripheral protection enable 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC53, PRIV53, and RLOCK53 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC53, PRIV53, and RLOCK53 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN54" description="peripheral protection enable 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC54, PRIV54, and RLOCK54 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC54, PRIV54, and RLOCK54 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN55" description="peripheral protection enable 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC55, PRIV55, and RLOCK55 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC55, PRIV55, and RLOCK55 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN56" description="peripheral protection enable 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC56, PRIV56, and RLOCK56 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC56, PRIV56, and RLOCK56 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN57" description="peripheral protection enable 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC57, PRIV57, and RLOCK57 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC57, PRIV57, and RLOCK57 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN58" description="peripheral protection enable 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC58, PRIV58, and RLOCK58 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC58, PRIV58, and RLOCK58 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN59" description="peripheral protection enable 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC59, PRIV59, and RLOCK59 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC59, PRIV59, and RLOCK59 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN60" description="peripheral protection enable 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC60, PRIV60, and RLOCK60 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC60, PRIV60, and RLOCK60 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN61" description="peripheral protection enable 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC61, PRIV61, and RLOCK61 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC61, PRIV61, and RLOCK61 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN62" description="peripheral protection enable 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC62, PRIV62, and RLOCK62 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC62, PRIV62, and RLOCK62 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN63" description="peripheral protection enable 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC63, PRIV63, and RLOCK63 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC63, PRIV63, and RLOCK63 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR2" description="RIFSC peripheral protection status register 2" start="+0xFB8" size="4" reset_value="0xF7DFF03B" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN64" description="peripheral protection enable 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC64, PRIV64, and RLOCK64 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC64, PRIV64, and RLOCK64 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN65" description="peripheral protection enable 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC65, PRIV65, and RLOCK65 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC65, PRIV65, and RLOCK65 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN66" description="peripheral protection enable 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC66, PRIV66, and RLOCK66 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC66, PRIV66, and RLOCK66 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN67" description="peripheral protection enable 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC67, PRIV67, and RLOCK67 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC67, PRIV67, and RLOCK67 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN68" description="peripheral protection enable 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC68, PRIV68, and RLOCK68 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC68, PRIV68, and RLOCK68 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN69" description="peripheral protection enable 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC69, PRIV69, and RLOCK69 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC69, PRIV69, and RLOCK69 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN70" description="peripheral protection enable 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC70, PRIV70, and RLOCK70 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC70, PRIV70, and RLOCK70 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN71" description="peripheral protection enable 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC71, PRIV71, and RLOCK71 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC71, PRIV71, and RLOCK71 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN72" description="peripheral protection enable 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC72, PRIV72, and RLOCK72 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC72, PRIV72, and RLOCK72 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN73" description="peripheral protection enable 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC73, PRIV73, and RLOCK73 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC73, PRIV73, and RLOCK73 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN74" description="peripheral protection enable 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC74, PRIV74, and RLOCK74 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC74, PRIV74, and RLOCK74 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN75" description="peripheral protection enable 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC75, PRIV75, and RLOCK75 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC75, PRIV75, and RLOCK75 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN76" description="peripheral protection enable 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC76, PRIV76, and RLOCK76 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC76, PRIV76, and RLOCK76 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN77" description="peripheral protection enable 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC77, PRIV77, and RLOCK77 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC77, PRIV77, and RLOCK77 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN78" description="peripheral protection enable 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC78, PRIV78, and RLOCK78 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC78, PRIV78, and RLOCK78 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN79" description="peripheral protection enable 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC79, PRIV79, and RLOCK79 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC79, PRIV79, and RLOCK79 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN80" description="peripheral protection enable 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC80, PRIV80, and RLOCK80 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC80, PRIV80, and RLOCK80 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN81" description="peripheral protection enable 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC81, PRIV81, and RLOCK81 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC81, PRIV81, and RLOCK81 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN82" description="peripheral protection enable 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC82, PRIV82, and RLOCK82 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC82, PRIV82, and RLOCK82 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN83" description="peripheral protection enable 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC83, PRIV83, and RLOCK83 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC83, PRIV83, and RLOCK83 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN84" description="peripheral protection enable 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC84, PRIV84, and RLOCK84 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC84, PRIV84, and RLOCK84 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN85" description="peripheral protection enable 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC85, PRIV85, and RLOCK85 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC85, PRIV85, and RLOCK85 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN86" description="peripheral protection enable 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC86, PRIV86, and RLOCK86 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC86, PRIV86, and RLOCK86 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN87" description="peripheral protection enable 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC87, PRIV87, and RLOCK87 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC87, PRIV87, and RLOCK87 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN88" description="peripheral protection enable 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC88, PRIV88, and RLOCK88 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC88, PRIV88, and RLOCK88 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN89" description="peripheral protection enable 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC89, PRIV89, and RLOCK89 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC89, PRIV89, and RLOCK89 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN90" description="peripheral protection enable 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC90, PRIV90, and RLOCK90 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC90, PRIV90, and RLOCK90 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN91" description="peripheral protection enable 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC91, PRIV91, and RLOCK91 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC91, PRIV91, and RLOCK91 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN92" description="peripheral protection enable 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC92, PRIV92, and RLOCK92 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC92, PRIV92, and RLOCK92 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN93" description="peripheral protection enable 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC93, PRIV93, and RLOCK93 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC93, PRIV93, and RLOCK93 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN94" description="peripheral protection enable 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC94, PRIV94, and RLOCK94 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC94, PRIV94, and RLOCK94 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN95" description="peripheral protection enable 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC95, PRIV95, and RLOCK95 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC95, PRIV95, and RLOCK95 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR3" description="RIFSC peripheral protection status register 3" start="+0xFBC" size="4" reset_value="0x000005FF" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN96" description="peripheral protection enable 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC96, PRIV96, and RLOCK96 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC96, PRIV96, and RLOCK96 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN97" description="peripheral protection enable 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC97, PRIV97, and RLOCK97 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC97, PRIV97, and RLOCK97 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN98" description="peripheral protection enable 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC98, PRIV98, and RLOCK98 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC98, PRIV98, and RLOCK98 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN99" description="peripheral protection enable 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC99, PRIV99, and RLOCK99 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC99, PRIV99, and RLOCK99 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN100" description="peripheral protection enable 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC100, PRIV100, and RLOCK100 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC100, PRIV100, and RLOCK100 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN101" description="peripheral protection enable 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC101, PRIV101, and RLOCK101 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC101, PRIV101, and RLOCK101 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN102" description="peripheral protection enable 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC102, PRIV102, and RLOCK102 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC102, PRIV102, and RLOCK102 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN103" description="peripheral protection enable 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC103, PRIV103, and RLOCK103 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC103, PRIV103, and RLOCK103 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN104" description="peripheral protection enable 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC104, PRIV104, and RLOCK104 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC104, PRIV104, and RLOCK104 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN105" description="peripheral protection enable 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC105, PRIV105, and RLOCK105 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC105, PRIV105, and RLOCK105 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN106" description="peripheral protection enable 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC106, PRIV106, and RLOCK106 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC106, PRIV106, and RLOCK106 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN107" description="peripheral protection enable 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC107, PRIV107, and RLOCK107 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC107, PRIV107, and RLOCK107 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN108" description="peripheral protection enable 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC108, PRIV108, and RLOCK108 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC108, PRIV108, and RLOCK108 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN109" description="peripheral protection enable 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC109, PRIV109, and RLOCK109 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC109, PRIV109, and RLOCK109 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN110" description="peripheral protection enable 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC110, PRIV110, and RLOCK110 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC110, PRIV110, and RLOCK110 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN111" description="peripheral protection enable 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC111, PRIV111, and RLOCK111 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC111, PRIV111, and RLOCK111 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN112" description="peripheral protection enable 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC112, PRIV112, and RLOCK112 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC112, PRIV112, and RLOCK112 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN113" description="peripheral protection enable 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC113, PRIV113, and RLOCK113 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC113, PRIV113, and RLOCK113 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN114" description="peripheral protection enable 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC114, PRIV114, and RLOCK114 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC114, PRIV114, and RLOCK114 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN115" description="peripheral protection enable 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC115, PRIV115, and RLOCK115 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC115, PRIV115, and RLOCK115 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN116" description="peripheral protection enable 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC116, PRIV116, and RLOCK116 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC116, PRIV116, and RLOCK116 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN117" description="peripheral protection enable 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC117, PRIV117, and RLOCK117 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC117, PRIV117, and RLOCK117 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN118" description="peripheral protection enable 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC118, PRIV118, and RLOCK118 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC118, PRIV118, and RLOCK118 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN119" description="peripheral protection enable 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC119, PRIV119, and RLOCK119 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC119, PRIV119, and RLOCK119 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN120" description="peripheral protection enable 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC120, PRIV120, and RLOCK120 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC120, PRIV120, and RLOCK120 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN121" description="peripheral protection enable 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC121, PRIV121, and RLOCK121 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC121, PRIV121, and RLOCK121 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN122" description="peripheral protection enable 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC122, PRIV122, and RLOCK122 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC122, PRIV122, and RLOCK122 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN123" description="peripheral protection enable 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC123, PRIV123, and RLOCK123 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC123, PRIV123, and RLOCK123 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN124" description="peripheral protection enable 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC124, PRIV124, and RLOCK124 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC124, PRIV124, and RLOCK124 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN125" description="peripheral protection enable 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC125, PRIV125, and RLOCK125 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC125, PRIV125, and RLOCK125 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN126" description="peripheral protection enable 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC126, PRIV126, and RLOCK126 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC126, PRIV126, and RLOCK126 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN127" description="peripheral protection enable 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC127, PRIV127, and RLOCK127 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC127, PRIV127, and RLOCK127 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR4" description="RIFSC peripheral protection status register 4" start="+0xFC0" size="4" reset_value="0x3A0E382E" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN128" description="peripheral protection enable 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC128, PRIV128, and RLOCK128 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC128, PRIV128, and RLOCK128 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN129" description="peripheral protection enable 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC129, PRIV129, and RLOCK129 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC129, PRIV129, and RLOCK129 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN130" description="peripheral protection enable 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC130, PRIV130, and RLOCK130 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC130, PRIV130, and RLOCK130 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN131" description="peripheral protection enable 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC131, PRIV131, and RLOCK131 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC131, PRIV131, and RLOCK131 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN132" description="peripheral protection enable 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC132, PRIV132, and RLOCK132 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC132, PRIV132, and RLOCK132 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN133" description="peripheral protection enable 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC133, PRIV133, and RLOCK133 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC133, PRIV133, and RLOCK133 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN134" description="peripheral protection enable 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC134, PRIV134, and RLOCK134 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC134, PRIV134, and RLOCK134 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN135" description="peripheral protection enable 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC135, PRIV135, and RLOCK135 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC135, PRIV135, and RLOCK135 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN136" description="peripheral protection enable 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC136, PRIV136, and RLOCK136 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC136, PRIV136, and RLOCK136 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN137" description="peripheral protection enable 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC137, PRIV137, and RLOCK137 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC137, PRIV137, and RLOCK137 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN138" description="peripheral protection enable 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC138, PRIV138, and RLOCK138 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC138, PRIV138, and RLOCK138 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN139" description="peripheral protection enable 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC139, PRIV139, and RLOCK139 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC139, PRIV139, and RLOCK139 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN140" description="peripheral protection enable 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC140, PRIV140, and RLOCK140 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC140, PRIV140, and RLOCK140 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN141" description="peripheral protection enable 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC141, PRIV141, and RLOCK141 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC141, PRIV141, and RLOCK141 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN142" description="peripheral protection enable 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC142, PRIV142, and RLOCK142 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC142, PRIV142, and RLOCK142 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN143" description="peripheral protection enable 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC143, PRIV143, and RLOCK143 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC143, PRIV143, and RLOCK143 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN144" description="peripheral protection enable 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC144, PRIV144, and RLOCK144 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC144, PRIV144, and RLOCK144 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN145" description="peripheral protection enable 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC145, PRIV145, and RLOCK145 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC145, PRIV145, and RLOCK145 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN146" description="peripheral protection enable 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC146, PRIV146, and RLOCK146 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC146, PRIV146, and RLOCK146 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN147" description="peripheral protection enable 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC147, PRIV147, and RLOCK147 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC147, PRIV147, and RLOCK147 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN148" description="peripheral protection enable 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC148, PRIV148, and RLOCK148 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC148, PRIV148, and RLOCK148 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN149" description="peripheral protection enable 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC149, PRIV149, and RLOCK149 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC149, PRIV149, and RLOCK149 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN150" description="peripheral protection enable 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC150, PRIV150, and RLOCK150 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC150, PRIV150, and RLOCK150 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN151" description="peripheral protection enable 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC151, PRIV151, and RLOCK151 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC151, PRIV151, and RLOCK151 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN152" description="peripheral protection enable 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC152, PRIV152, and RLOCK152 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC152, PRIV152, and RLOCK152 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN153" description="peripheral protection enable 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC153, PRIV153, and RLOCK153 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC153, PRIV153, and RLOCK153 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN154" description="peripheral protection enable 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC154, PRIV154, and RLOCK154 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC154, PRIV154, and RLOCK154 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN155" description="peripheral protection enable 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC155, PRIV155, and RLOCK155 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC155, PRIV155, and RLOCK155 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN156" description="peripheral protection enable 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC156, PRIV156, and RLOCK156 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC156, PRIV156, and RLOCK156 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN157" description="peripheral protection enable 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC157, PRIV157, and RLOCK157 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC157, PRIV157, and RLOCK157 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN158" description="peripheral protection enable 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC158, PRIV158, and RLOCK158 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC158, PRIV158, and RLOCK158 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN159" description="peripheral protection enable 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC159, PRIV159, and RLOCK159 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC159, PRIV159, and RLOCK159 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR5" description="RIFSC peripheral protection status register 5" start="+0xFC4" size="4" reset_value="0x3DDEEF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN160" description="peripheral protection enable 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC160, PRIV160, and RLOCK160 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC160, PRIV160, and RLOCK160 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN161" description="peripheral protection enable 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC161, PRIV161, and RLOCK161 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC161, PRIV161, and RLOCK161 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN162" description="peripheral protection enable 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC162, PRIV162, and RLOCK162 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC162, PRIV162, and RLOCK162 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN163" description="peripheral protection enable 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC163, PRIV163, and RLOCK163 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC163, PRIV163, and RLOCK163 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN164" description="peripheral protection enable 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC164, PRIV164, and RLOCK164 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC164, PRIV164, and RLOCK164 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN165" description="peripheral protection enable 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC165, PRIV165, and RLOCK165 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC165, PRIV165, and RLOCK165 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN166" description="peripheral protection enable 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC166, PRIV166, and RLOCK166 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC166, PRIV166, and RLOCK166 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN167" description="peripheral protection enable 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC167, PRIV167, and RLOCK167 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC167, PRIV167, and RLOCK167 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN168" description="peripheral protection enable 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC168, PRIV168, and RLOCK168 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC168, PRIV168, and RLOCK168 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN169" description="peripheral protection enable 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC169, PRIV169, and RLOCK169 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC169, PRIV169, and RLOCK169 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN170" description="peripheral protection enable 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC170, PRIV170, and RLOCK170 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC170, PRIV170, and RLOCK170 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN171" description="peripheral protection enable 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC171, PRIV171, and RLOCK171 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC171, PRIV171, and RLOCK171 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN172" description="peripheral protection enable 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC172, PRIV172, and RLOCK172 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC172, PRIV172, and RLOCK172 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN173" description="peripheral protection enable 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC173, PRIV173, and RLOCK173 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC173, PRIV173, and RLOCK173 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN174" description="peripheral protection enable 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC174, PRIV174, and RLOCK174 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC174, PRIV174, and RLOCK174 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN175" description="peripheral protection enable 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC175, PRIV175, and RLOCK175 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC175, PRIV175, and RLOCK175 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN176" description="peripheral protection enable 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC176, PRIV176, and RLOCK176 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC176, PRIV176, and RLOCK176 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN177" description="peripheral protection enable 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC177, PRIV177, and RLOCK177 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC177, PRIV177, and RLOCK177 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN178" description="peripheral protection enable 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC178, PRIV178, and RLOCK178 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC178, PRIV178, and RLOCK178 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN179" description="peripheral protection enable 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC179, PRIV179, and RLOCK179 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC179, PRIV179, and RLOCK179 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN180" description="peripheral protection enable 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC180, PRIV180, and RLOCK180 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC180, PRIV180, and RLOCK180 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN181" description="peripheral protection enable 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC181, PRIV181, and RLOCK181 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC181, PRIV181, and RLOCK181 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN182" description="peripheral protection enable 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC182, PRIV182, and RLOCK182 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC182, PRIV182, and RLOCK182 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN183" description="peripheral protection enable 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC183, PRIV183, and RLOCK183 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC183, PRIV183, and RLOCK183 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN184" description="peripheral protection enable 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC184, PRIV184, and RLOCK184 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC184, PRIV184, and RLOCK184 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN185" description="peripheral protection enable 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC185, PRIV185, and RLOCK185 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC185, PRIV185, and RLOCK185 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN186" description="peripheral protection enable 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC186, PRIV186, and RLOCK186 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC186, PRIV186, and RLOCK186 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN187" description="peripheral protection enable 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC187, PRIV187, and RLOCK187 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC187, PRIV187, and RLOCK187 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN188" description="peripheral protection enable 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC188, PRIV188, and RLOCK188 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC188, PRIV188, and RLOCK188 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN189" description="peripheral protection enable 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC189, PRIV189, and RLOCK189 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC189, PRIV189, and RLOCK189 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN190" description="peripheral protection enable 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC190, PRIV190, and RLOCK190 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC190, PRIV190, and RLOCK190 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN191" description="peripheral protection enable 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC191, PRIV191, and RLOCK191 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC191, PRIV191, and RLOCK191 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RIFSC_S" description="Resource isolation framework security controller" start="0x54024000">
+    <Register name="RIFSC_RISC_CR" description="RIFSC RISC slave configuration register x" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="Global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC RISC registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RIFSC RISC registers are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR0" description="RIFSC RISC slave security configuration register 0" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC0" description="security configuration for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 0." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 0." start="0x1" />
+      </BitField>
+      <BitField name="SEC1" description="security configuration for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 1." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 1." start="0x1" />
+      </BitField>
+      <BitField name="SEC2" description="security configuration for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 2." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 2." start="0x1" />
+      </BitField>
+      <BitField name="SEC3" description="security configuration for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 3." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 3." start="0x1" />
+      </BitField>
+      <BitField name="SEC4" description="security configuration for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 4." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 4." start="0x1" />
+      </BitField>
+      <BitField name="SEC5" description="security configuration for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 5." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 5." start="0x1" />
+      </BitField>
+      <BitField name="SEC6" description="security configuration for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 6." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 6." start="0x1" />
+      </BitField>
+      <BitField name="SEC7" description="security configuration for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 7." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 7." start="0x1" />
+      </BitField>
+      <BitField name="SEC8" description="security configuration for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 8." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 8." start="0x1" />
+      </BitField>
+      <BitField name="SEC9" description="security configuration for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 9." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 9." start="0x1" />
+      </BitField>
+      <BitField name="SEC10" description="security configuration for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 10." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 10." start="0x1" />
+      </BitField>
+      <BitField name="SEC11" description="security configuration for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 11." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 11." start="0x1" />
+      </BitField>
+      <BitField name="SEC12" description="security configuration for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 12." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 12." start="0x1" />
+      </BitField>
+      <BitField name="SEC13" description="security configuration for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 13." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 13." start="0x1" />
+      </BitField>
+      <BitField name="SEC14" description="security configuration for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 14." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 14." start="0x1" />
+      </BitField>
+      <BitField name="SEC15" description="security configuration for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 15." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 15." start="0x1" />
+      </BitField>
+      <BitField name="SEC16" description="security configuration for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 16." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 16." start="0x1" />
+      </BitField>
+      <BitField name="SEC17" description="security configuration for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 17." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 17." start="0x1" />
+      </BitField>
+      <BitField name="SEC18" description="security configuration for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 18." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 18." start="0x1" />
+      </BitField>
+      <BitField name="SEC19" description="security configuration for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 19." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 19." start="0x1" />
+      </BitField>
+      <BitField name="SEC20" description="security configuration for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 20." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 20." start="0x1" />
+      </BitField>
+      <BitField name="SEC21" description="security configuration for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 21." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 21." start="0x1" />
+      </BitField>
+      <BitField name="SEC22" description="security configuration for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 22." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 22." start="0x1" />
+      </BitField>
+      <BitField name="SEC23" description="security configuration for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 23." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 23." start="0x1" />
+      </BitField>
+      <BitField name="SEC24" description="security configuration for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 24." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 24." start="0x1" />
+      </BitField>
+      <BitField name="SEC25" description="security configuration for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 25." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 25." start="0x1" />
+      </BitField>
+      <BitField name="SEC26" description="security configuration for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 26." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 26." start="0x1" />
+      </BitField>
+      <BitField name="SEC27" description="security configuration for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 27." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 27." start="0x1" />
+      </BitField>
+      <BitField name="SEC28" description="security configuration for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 28." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 28." start="0x1" />
+      </BitField>
+      <BitField name="SEC29" description="security configuration for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 29." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 29." start="0x1" />
+      </BitField>
+      <BitField name="SEC30" description="security configuration for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 30." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 30." start="0x1" />
+      </BitField>
+      <BitField name="SEC31" description="security configuration for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 31." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 31." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR1" description="RIFSC RISC slave security configuration register 1" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC32" description="security configuration for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 32." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 32." start="0x1" />
+      </BitField>
+      <BitField name="SEC33" description="security configuration for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 33." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 33." start="0x1" />
+      </BitField>
+      <BitField name="SEC34" description="security configuration for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 34." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 34." start="0x1" />
+      </BitField>
+      <BitField name="SEC35" description="security configuration for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 35." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 35." start="0x1" />
+      </BitField>
+      <BitField name="SEC36" description="security configuration for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 36." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 36." start="0x1" />
+      </BitField>
+      <BitField name="SEC37" description="security configuration for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 37." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 37." start="0x1" />
+      </BitField>
+      <BitField name="SEC38" description="security configuration for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 38." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 38." start="0x1" />
+      </BitField>
+      <BitField name="SEC39" description="security configuration for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 39." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 39." start="0x1" />
+      </BitField>
+      <BitField name="SEC40" description="security configuration for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 40." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 40." start="0x1" />
+      </BitField>
+      <BitField name="SEC41" description="security configuration for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 41." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 41." start="0x1" />
+      </BitField>
+      <BitField name="SEC42" description="security configuration for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 42." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 42." start="0x1" />
+      </BitField>
+      <BitField name="SEC43" description="security configuration for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 43." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 43." start="0x1" />
+      </BitField>
+      <BitField name="SEC44" description="security configuration for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 44." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 44." start="0x1" />
+      </BitField>
+      <BitField name="SEC45" description="security configuration for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 45." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 45." start="0x1" />
+      </BitField>
+      <BitField name="SEC46" description="security configuration for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 46." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 46." start="0x1" />
+      </BitField>
+      <BitField name="SEC47" description="security configuration for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 47." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 47." start="0x1" />
+      </BitField>
+      <BitField name="SEC48" description="security configuration for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 48." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 48." start="0x1" />
+      </BitField>
+      <BitField name="SEC49" description="security configuration for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 49." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 49." start="0x1" />
+      </BitField>
+      <BitField name="SEC50" description="security configuration for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 50." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 50." start="0x1" />
+      </BitField>
+      <BitField name="SEC51" description="security configuration for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 51." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 51." start="0x1" />
+      </BitField>
+      <BitField name="SEC52" description="security configuration for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 52." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 52." start="0x1" />
+      </BitField>
+      <BitField name="SEC53" description="security configuration for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 53." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 53." start="0x1" />
+      </BitField>
+      <BitField name="SEC54" description="security configuration for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 54." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 54." start="0x1" />
+      </BitField>
+      <BitField name="SEC55" description="security configuration for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 55." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 55." start="0x1" />
+      </BitField>
+      <BitField name="SEC56" description="security configuration for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 56." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 56." start="0x1" />
+      </BitField>
+      <BitField name="SEC57" description="security configuration for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 57." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 57." start="0x1" />
+      </BitField>
+      <BitField name="SEC58" description="security configuration for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 58." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 58." start="0x1" />
+      </BitField>
+      <BitField name="SEC59" description="security configuration for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 59." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 59." start="0x1" />
+      </BitField>
+      <BitField name="SEC60" description="security configuration for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 60." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 60." start="0x1" />
+      </BitField>
+      <BitField name="SEC61" description="security configuration for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 61." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 61." start="0x1" />
+      </BitField>
+      <BitField name="SEC62" description="security configuration for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 62." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 62." start="0x1" />
+      </BitField>
+      <BitField name="SEC63" description="security configuration for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 63." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 63." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR2" description="RIFSC RISC slave security configuration register 2" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC64" description="security configuration for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 64." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 64." start="0x1" />
+      </BitField>
+      <BitField name="SEC65" description="security configuration for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 65." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 65." start="0x1" />
+      </BitField>
+      <BitField name="SEC66" description="security configuration for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 66." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 66." start="0x1" />
+      </BitField>
+      <BitField name="SEC67" description="security configuration for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 67." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 67." start="0x1" />
+      </BitField>
+      <BitField name="SEC68" description="security configuration for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 68." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 68." start="0x1" />
+      </BitField>
+      <BitField name="SEC69" description="security configuration for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 69." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 69." start="0x1" />
+      </BitField>
+      <BitField name="SEC70" description="security configuration for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 70." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 70." start="0x1" />
+      </BitField>
+      <BitField name="SEC71" description="security configuration for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 71." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 71." start="0x1" />
+      </BitField>
+      <BitField name="SEC72" description="security configuration for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 72." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 72." start="0x1" />
+      </BitField>
+      <BitField name="SEC73" description="security configuration for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 73." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 73." start="0x1" />
+      </BitField>
+      <BitField name="SEC74" description="security configuration for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 74." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 74." start="0x1" />
+      </BitField>
+      <BitField name="SEC75" description="security configuration for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 75." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 75." start="0x1" />
+      </BitField>
+      <BitField name="SEC76" description="security configuration for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 76." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 76." start="0x1" />
+      </BitField>
+      <BitField name="SEC77" description="security configuration for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 77." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 77." start="0x1" />
+      </BitField>
+      <BitField name="SEC78" description="security configuration for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 78." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 78." start="0x1" />
+      </BitField>
+      <BitField name="SEC79" description="security configuration for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 79." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 79." start="0x1" />
+      </BitField>
+      <BitField name="SEC80" description="security configuration for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 80." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 80." start="0x1" />
+      </BitField>
+      <BitField name="SEC81" description="security configuration for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 81." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 81." start="0x1" />
+      </BitField>
+      <BitField name="SEC82" description="security configuration for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 82." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 82." start="0x1" />
+      </BitField>
+      <BitField name="SEC83" description="security configuration for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 83." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 83." start="0x1" />
+      </BitField>
+      <BitField name="SEC84" description="security configuration for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 84." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 84." start="0x1" />
+      </BitField>
+      <BitField name="SEC85" description="security configuration for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 85." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 85." start="0x1" />
+      </BitField>
+      <BitField name="SEC86" description="security configuration for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 86." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 86." start="0x1" />
+      </BitField>
+      <BitField name="SEC87" description="security configuration for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 87." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 87." start="0x1" />
+      </BitField>
+      <BitField name="SEC88" description="security configuration for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 88." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 88." start="0x1" />
+      </BitField>
+      <BitField name="SEC89" description="security configuration for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 89." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 89." start="0x1" />
+      </BitField>
+      <BitField name="SEC90" description="security configuration for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 90." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 90." start="0x1" />
+      </BitField>
+      <BitField name="SEC91" description="security configuration for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 91." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 91." start="0x1" />
+      </BitField>
+      <BitField name="SEC92" description="security configuration for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 92." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 92." start="0x1" />
+      </BitField>
+      <BitField name="SEC93" description="security configuration for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 93." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 93." start="0x1" />
+      </BitField>
+      <BitField name="SEC94" description="security configuration for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 94." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 94." start="0x1" />
+      </BitField>
+      <BitField name="SEC95" description="security configuration for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 95." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 95." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR3" description="RIFSC RISC slave security configuration register 3" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC96" description="security configuration for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 96." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 96." start="0x1" />
+      </BitField>
+      <BitField name="SEC97" description="security configuration for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 97." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 97." start="0x1" />
+      </BitField>
+      <BitField name="SEC98" description="security configuration for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 98." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 98." start="0x1" />
+      </BitField>
+      <BitField name="SEC99" description="security configuration for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 99." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 99." start="0x1" />
+      </BitField>
+      <BitField name="SEC100" description="security configuration for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 100." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 100." start="0x1" />
+      </BitField>
+      <BitField name="SEC101" description="security configuration for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 101." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 101." start="0x1" />
+      </BitField>
+      <BitField name="SEC102" description="security configuration for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 102." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 102." start="0x1" />
+      </BitField>
+      <BitField name="SEC103" description="security configuration for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 103." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 103." start="0x1" />
+      </BitField>
+      <BitField name="SEC104" description="security configuration for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 104." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 104." start="0x1" />
+      </BitField>
+      <BitField name="SEC105" description="security configuration for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 105." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 105." start="0x1" />
+      </BitField>
+      <BitField name="SEC106" description="security configuration for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 106." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 106." start="0x1" />
+      </BitField>
+      <BitField name="SEC107" description="security configuration for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 107." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 107." start="0x1" />
+      </BitField>
+      <BitField name="SEC108" description="security configuration for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 108." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 108." start="0x1" />
+      </BitField>
+      <BitField name="SEC109" description="security configuration for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 109." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 109." start="0x1" />
+      </BitField>
+      <BitField name="SEC110" description="security configuration for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 110." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 110." start="0x1" />
+      </BitField>
+      <BitField name="SEC111" description="security configuration for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 111." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 111." start="0x1" />
+      </BitField>
+      <BitField name="SEC112" description="security configuration for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 112." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 112." start="0x1" />
+      </BitField>
+      <BitField name="SEC113" description="security configuration for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 113." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 113." start="0x1" />
+      </BitField>
+      <BitField name="SEC114" description="security configuration for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 114." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 114." start="0x1" />
+      </BitField>
+      <BitField name="SEC115" description="security configuration for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 115." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 115." start="0x1" />
+      </BitField>
+      <BitField name="SEC116" description="security configuration for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 116." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 116." start="0x1" />
+      </BitField>
+      <BitField name="SEC117" description="security configuration for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 117." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 117." start="0x1" />
+      </BitField>
+      <BitField name="SEC118" description="security configuration for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 118." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 118." start="0x1" />
+      </BitField>
+      <BitField name="SEC119" description="security configuration for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 119." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 119." start="0x1" />
+      </BitField>
+      <BitField name="SEC120" description="security configuration for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 120." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 120." start="0x1" />
+      </BitField>
+      <BitField name="SEC121" description="security configuration for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 121." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 121." start="0x1" />
+      </BitField>
+      <BitField name="SEC122" description="security configuration for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 122." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 122." start="0x1" />
+      </BitField>
+      <BitField name="SEC123" description="security configuration for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 123." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 123." start="0x1" />
+      </BitField>
+      <BitField name="SEC124" description="security configuration for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 124." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 124." start="0x1" />
+      </BitField>
+      <BitField name="SEC125" description="security configuration for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 125." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 125." start="0x1" />
+      </BitField>
+      <BitField name="SEC126" description="security configuration for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 126." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 126." start="0x1" />
+      </BitField>
+      <BitField name="SEC127" description="security configuration for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 127." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 127." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR4" description="RIFSC RISC slave security configuration register 4" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC128" description="security configuration for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 128." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 128." start="0x1" />
+      </BitField>
+      <BitField name="SEC129" description="security configuration for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 129." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 129." start="0x1" />
+      </BitField>
+      <BitField name="SEC130" description="security configuration for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 130." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 130." start="0x1" />
+      </BitField>
+      <BitField name="SEC131" description="security configuration for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 131." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 131." start="0x1" />
+      </BitField>
+      <BitField name="SEC132" description="security configuration for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 132." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 132." start="0x1" />
+      </BitField>
+      <BitField name="SEC133" description="security configuration for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 133." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 133." start="0x1" />
+      </BitField>
+      <BitField name="SEC134" description="security configuration for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 134." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 134." start="0x1" />
+      </BitField>
+      <BitField name="SEC135" description="security configuration for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 135." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 135." start="0x1" />
+      </BitField>
+      <BitField name="SEC136" description="security configuration for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 136." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 136." start="0x1" />
+      </BitField>
+      <BitField name="SEC137" description="security configuration for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 137." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 137." start="0x1" />
+      </BitField>
+      <BitField name="SEC138" description="security configuration for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 138." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 138." start="0x1" />
+      </BitField>
+      <BitField name="SEC139" description="security configuration for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 139." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 139." start="0x1" />
+      </BitField>
+      <BitField name="SEC140" description="security configuration for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 140." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 140." start="0x1" />
+      </BitField>
+      <BitField name="SEC141" description="security configuration for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 141." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 141." start="0x1" />
+      </BitField>
+      <BitField name="SEC142" description="security configuration for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 142." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 142." start="0x1" />
+      </BitField>
+      <BitField name="SEC143" description="security configuration for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 143." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 143." start="0x1" />
+      </BitField>
+      <BitField name="SEC144" description="security configuration for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 144." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 144." start="0x1" />
+      </BitField>
+      <BitField name="SEC145" description="security configuration for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 145." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 145." start="0x1" />
+      </BitField>
+      <BitField name="SEC146" description="security configuration for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 146." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 146." start="0x1" />
+      </BitField>
+      <BitField name="SEC147" description="security configuration for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 147." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 147." start="0x1" />
+      </BitField>
+      <BitField name="SEC148" description="security configuration for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 148." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 148." start="0x1" />
+      </BitField>
+      <BitField name="SEC149" description="security configuration for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 149." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 149." start="0x1" />
+      </BitField>
+      <BitField name="SEC150" description="security configuration for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 150." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 150." start="0x1" />
+      </BitField>
+      <BitField name="SEC151" description="security configuration for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 151." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 151." start="0x1" />
+      </BitField>
+      <BitField name="SEC152" description="security configuration for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 152." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 152." start="0x1" />
+      </BitField>
+      <BitField name="SEC153" description="security configuration for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 153." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 153." start="0x1" />
+      </BitField>
+      <BitField name="SEC154" description="security configuration for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 154." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 154." start="0x1" />
+      </BitField>
+      <BitField name="SEC155" description="security configuration for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 155." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 155." start="0x1" />
+      </BitField>
+      <BitField name="SEC156" description="security configuration for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 156." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 156." start="0x1" />
+      </BitField>
+      <BitField name="SEC157" description="security configuration for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 157." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 157." start="0x1" />
+      </BitField>
+      <BitField name="SEC158" description="security configuration for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 158." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 158." start="0x1" />
+      </BitField>
+      <BitField name="SEC159" description="security configuration for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 159." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 159." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_SECCFGR5" description="RIFSC RISC slave security configuration register 5" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC160" description="security configuration for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 160." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 160." start="0x1" />
+      </BitField>
+      <BitField name="SEC161" description="security configuration for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 161." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 161." start="0x1" />
+      </BitField>
+      <BitField name="SEC162" description="security configuration for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 162." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 162." start="0x1" />
+      </BitField>
+      <BitField name="SEC163" description="security configuration for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 163." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 163." start="0x1" />
+      </BitField>
+      <BitField name="SEC164" description="security configuration for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 164." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 164." start="0x1" />
+      </BitField>
+      <BitField name="SEC165" description="security configuration for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 165." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 165." start="0x1" />
+      </BitField>
+      <BitField name="SEC166" description="security configuration for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 166." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 166." start="0x1" />
+      </BitField>
+      <BitField name="SEC167" description="security configuration for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 167." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 167." start="0x1" />
+      </BitField>
+      <BitField name="SEC168" description="security configuration for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 168." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 168." start="0x1" />
+      </BitField>
+      <BitField name="SEC169" description="security configuration for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 169." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 169." start="0x1" />
+      </BitField>
+      <BitField name="SEC170" description="security configuration for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 170." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 170." start="0x1" />
+      </BitField>
+      <BitField name="SEC171" description="security configuration for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 171." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 171." start="0x1" />
+      </BitField>
+      <BitField name="SEC172" description="security configuration for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 172." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 172." start="0x1" />
+      </BitField>
+      <BitField name="SEC173" description="security configuration for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 173." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 173." start="0x1" />
+      </BitField>
+      <BitField name="SEC174" description="security configuration for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 174." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 174." start="0x1" />
+      </BitField>
+      <BitField name="SEC175" description="security configuration for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 175." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 175." start="0x1" />
+      </BitField>
+      <BitField name="SEC176" description="security configuration for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 176." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 176." start="0x1" />
+      </BitField>
+      <BitField name="SEC177" description="security configuration for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 177." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 177." start="0x1" />
+      </BitField>
+      <BitField name="SEC178" description="security configuration for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 178." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 178." start="0x1" />
+      </BitField>
+      <BitField name="SEC179" description="security configuration for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 179." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 179." start="0x1" />
+      </BitField>
+      <BitField name="SEC180" description="security configuration for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 180." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 180." start="0x1" />
+      </BitField>
+      <BitField name="SEC181" description="security configuration for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 181." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 181." start="0x1" />
+      </BitField>
+      <BitField name="SEC182" description="security configuration for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 182." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 182." start="0x1" />
+      </BitField>
+      <BitField name="SEC183" description="security configuration for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 183." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 183." start="0x1" />
+      </BitField>
+      <BitField name="SEC184" description="security configuration for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 184." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 184." start="0x1" />
+      </BitField>
+      <BitField name="SEC185" description="security configuration for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 185." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 185." start="0x1" />
+      </BitField>
+      <BitField name="SEC186" description="security configuration for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 186." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 186." start="0x1" />
+      </BitField>
+      <BitField name="SEC187" description="security configuration for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 187." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 187." start="0x1" />
+      </BitField>
+      <BitField name="SEC188" description="security configuration for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 188." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 188." start="0x1" />
+      </BitField>
+      <BitField name="SEC189" description="security configuration for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 189." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 189." start="0x1" />
+      </BitField>
+      <BitField name="SEC190" description="security configuration for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 190." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 190." start="0x1" />
+      </BitField>
+      <BitField name="SEC191" description="security configuration for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Secure and non-secure data access are granted to the peripheral 191." start="0x0" />
+        <Enum name="B_0x1" description="Secure data access only are granted to the peripheral 191." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR0" description="RIFSC RISFC slave privileged register 0" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV0" description="privileged-only access permission for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 0." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 0." start="0x1" />
+      </BitField>
+      <BitField name="PRIV1" description="privileged-only access permission for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 1." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 1." start="0x1" />
+      </BitField>
+      <BitField name="PRIV2" description="privileged-only access permission for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 2." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 2." start="0x1" />
+      </BitField>
+      <BitField name="PRIV3" description="privileged-only access permission for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 3." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 3." start="0x1" />
+      </BitField>
+      <BitField name="PRIV4" description="privileged-only access permission for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 4." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 4." start="0x1" />
+      </BitField>
+      <BitField name="PRIV5" description="privileged-only access permission for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 5." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 5." start="0x1" />
+      </BitField>
+      <BitField name="PRIV6" description="privileged-only access permission for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 6." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 6." start="0x1" />
+      </BitField>
+      <BitField name="PRIV7" description="privileged-only access permission for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 7." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 7." start="0x1" />
+      </BitField>
+      <BitField name="PRIV8" description="privileged-only access permission for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 8." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 8." start="0x1" />
+      </BitField>
+      <BitField name="PRIV9" description="privileged-only access permission for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 9." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 9." start="0x1" />
+      </BitField>
+      <BitField name="PRIV10" description="privileged-only access permission for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 10." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 10." start="0x1" />
+      </BitField>
+      <BitField name="PRIV11" description="privileged-only access permission for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 11." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 11." start="0x1" />
+      </BitField>
+      <BitField name="PRIV12" description="privileged-only access permission for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 12." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 12." start="0x1" />
+      </BitField>
+      <BitField name="PRIV13" description="privileged-only access permission for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 13." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 13." start="0x1" />
+      </BitField>
+      <BitField name="PRIV14" description="privileged-only access permission for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 14." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 14." start="0x1" />
+      </BitField>
+      <BitField name="PRIV15" description="privileged-only access permission for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 15." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 15." start="0x1" />
+      </BitField>
+      <BitField name="PRIV16" description="privileged-only access permission for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 16." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 16." start="0x1" />
+      </BitField>
+      <BitField name="PRIV17" description="privileged-only access permission for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 17." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 17." start="0x1" />
+      </BitField>
+      <BitField name="PRIV18" description="privileged-only access permission for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 18." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 18." start="0x1" />
+      </BitField>
+      <BitField name="PRIV19" description="privileged-only access permission for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 19." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 19." start="0x1" />
+      </BitField>
+      <BitField name="PRIV20" description="privileged-only access permission for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 20." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 20." start="0x1" />
+      </BitField>
+      <BitField name="PRIV21" description="privileged-only access permission for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 21." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 21." start="0x1" />
+      </BitField>
+      <BitField name="PRIV22" description="privileged-only access permission for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 22." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 22." start="0x1" />
+      </BitField>
+      <BitField name="PRIV23" description="privileged-only access permission for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 23." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 23." start="0x1" />
+      </BitField>
+      <BitField name="PRIV24" description="privileged-only access permission for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 24." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 24." start="0x1" />
+      </BitField>
+      <BitField name="PRIV25" description="privileged-only access permission for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 25." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 25." start="0x1" />
+      </BitField>
+      <BitField name="PRIV26" description="privileged-only access permission for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 26." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 26." start="0x1" />
+      </BitField>
+      <BitField name="PRIV27" description="privileged-only access permission for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 27." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 27." start="0x1" />
+      </BitField>
+      <BitField name="PRIV28" description="privileged-only access permission for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 28." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 28." start="0x1" />
+      </BitField>
+      <BitField name="PRIV29" description="privileged-only access permission for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 29." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 29." start="0x1" />
+      </BitField>
+      <BitField name="PRIV30" description="privileged-only access permission for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 30." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 30." start="0x1" />
+      </BitField>
+      <BitField name="PRIV31" description="privileged-only access permission for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 31." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 31." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR1" description="RIFSC RISFC slave privileged register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV32" description="privileged-only access permission for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 32." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 32." start="0x1" />
+      </BitField>
+      <BitField name="PRIV33" description="privileged-only access permission for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 33." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 33." start="0x1" />
+      </BitField>
+      <BitField name="PRIV34" description="privileged-only access permission for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 34." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 34." start="0x1" />
+      </BitField>
+      <BitField name="PRIV35" description="privileged-only access permission for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 35." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 35." start="0x1" />
+      </BitField>
+      <BitField name="PRIV36" description="privileged-only access permission for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 36." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 36." start="0x1" />
+      </BitField>
+      <BitField name="PRIV37" description="privileged-only access permission for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 37." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 37." start="0x1" />
+      </BitField>
+      <BitField name="PRIV38" description="privileged-only access permission for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 38." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 38." start="0x1" />
+      </BitField>
+      <BitField name="PRIV39" description="privileged-only access permission for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 39." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 39." start="0x1" />
+      </BitField>
+      <BitField name="PRIV40" description="privileged-only access permission for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 40." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 40." start="0x1" />
+      </BitField>
+      <BitField name="PRIV41" description="privileged-only access permission for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 41." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 41." start="0x1" />
+      </BitField>
+      <BitField name="PRIV42" description="privileged-only access permission for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 42." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 42." start="0x1" />
+      </BitField>
+      <BitField name="PRIV43" description="privileged-only access permission for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 43." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 43." start="0x1" />
+      </BitField>
+      <BitField name="PRIV44" description="privileged-only access permission for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 44." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 44." start="0x1" />
+      </BitField>
+      <BitField name="PRIV45" description="privileged-only access permission for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 45." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 45." start="0x1" />
+      </BitField>
+      <BitField name="PRIV46" description="privileged-only access permission for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 46." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 46." start="0x1" />
+      </BitField>
+      <BitField name="PRIV47" description="privileged-only access permission for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 47." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 47." start="0x1" />
+      </BitField>
+      <BitField name="PRIV48" description="privileged-only access permission for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 48." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 48." start="0x1" />
+      </BitField>
+      <BitField name="PRIV49" description="privileged-only access permission for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 49." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 49." start="0x1" />
+      </BitField>
+      <BitField name="PRIV50" description="privileged-only access permission for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 50." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 50." start="0x1" />
+      </BitField>
+      <BitField name="PRIV51" description="privileged-only access permission for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 51." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 51." start="0x1" />
+      </BitField>
+      <BitField name="PRIV52" description="privileged-only access permission for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 52." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 52." start="0x1" />
+      </BitField>
+      <BitField name="PRIV53" description="privileged-only access permission for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 53." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 53." start="0x1" />
+      </BitField>
+      <BitField name="PRIV54" description="privileged-only access permission for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 54." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 54." start="0x1" />
+      </BitField>
+      <BitField name="PRIV55" description="privileged-only access permission for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 55." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 55." start="0x1" />
+      </BitField>
+      <BitField name="PRIV56" description="privileged-only access permission for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 56." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 56." start="0x1" />
+      </BitField>
+      <BitField name="PRIV57" description="privileged-only access permission for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 57." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 57." start="0x1" />
+      </BitField>
+      <BitField name="PRIV58" description="privileged-only access permission for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 58." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 58." start="0x1" />
+      </BitField>
+      <BitField name="PRIV59" description="privileged-only access permission for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 59." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 59." start="0x1" />
+      </BitField>
+      <BitField name="PRIV60" description="privileged-only access permission for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 60." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 60." start="0x1" />
+      </BitField>
+      <BitField name="PRIV61" description="privileged-only access permission for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 61." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 61." start="0x1" />
+      </BitField>
+      <BitField name="PRIV62" description="privileged-only access permission for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 62." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 62." start="0x1" />
+      </BitField>
+      <BitField name="PRIV63" description="privileged-only access permission for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 63." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 63." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR2" description="RIFSC RISFC slave privileged register 2" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV64" description="privileged-only access permission for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 64." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 64." start="0x1" />
+      </BitField>
+      <BitField name="PRIV65" description="privileged-only access permission for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 65." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 65." start="0x1" />
+      </BitField>
+      <BitField name="PRIV66" description="privileged-only access permission for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 66." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 66." start="0x1" />
+      </BitField>
+      <BitField name="PRIV67" description="privileged-only access permission for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 67." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 67." start="0x1" />
+      </BitField>
+      <BitField name="PRIV68" description="privileged-only access permission for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 68." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 68." start="0x1" />
+      </BitField>
+      <BitField name="PRIV69" description="privileged-only access permission for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 69." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 69." start="0x1" />
+      </BitField>
+      <BitField name="PRIV70" description="privileged-only access permission for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 70." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 70." start="0x1" />
+      </BitField>
+      <BitField name="PRIV71" description="privileged-only access permission for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 71." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 71." start="0x1" />
+      </BitField>
+      <BitField name="PRIV72" description="privileged-only access permission for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 72." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 72." start="0x1" />
+      </BitField>
+      <BitField name="PRIV73" description="privileged-only access permission for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 73." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 73." start="0x1" />
+      </BitField>
+      <BitField name="PRIV74" description="privileged-only access permission for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 74." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 74." start="0x1" />
+      </BitField>
+      <BitField name="PRIV75" description="privileged-only access permission for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 75." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 75." start="0x1" />
+      </BitField>
+      <BitField name="PRIV76" description="privileged-only access permission for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 76." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 76." start="0x1" />
+      </BitField>
+      <BitField name="PRIV77" description="privileged-only access permission for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 77." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 77." start="0x1" />
+      </BitField>
+      <BitField name="PRIV78" description="privileged-only access permission for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 78." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 78." start="0x1" />
+      </BitField>
+      <BitField name="PRIV79" description="privileged-only access permission for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 79." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 79." start="0x1" />
+      </BitField>
+      <BitField name="PRIV80" description="privileged-only access permission for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 80." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 80." start="0x1" />
+      </BitField>
+      <BitField name="PRIV81" description="privileged-only access permission for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 81." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 81." start="0x1" />
+      </BitField>
+      <BitField name="PRIV82" description="privileged-only access permission for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 82." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 82." start="0x1" />
+      </BitField>
+      <BitField name="PRIV83" description="privileged-only access permission for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 83." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 83." start="0x1" />
+      </BitField>
+      <BitField name="PRIV84" description="privileged-only access permission for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 84." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 84." start="0x1" />
+      </BitField>
+      <BitField name="PRIV85" description="privileged-only access permission for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 85." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 85." start="0x1" />
+      </BitField>
+      <BitField name="PRIV86" description="privileged-only access permission for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 86." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 86." start="0x1" />
+      </BitField>
+      <BitField name="PRIV87" description="privileged-only access permission for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 87." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 87." start="0x1" />
+      </BitField>
+      <BitField name="PRIV88" description="privileged-only access permission for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 88." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 88." start="0x1" />
+      </BitField>
+      <BitField name="PRIV89" description="privileged-only access permission for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 89." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 89." start="0x1" />
+      </BitField>
+      <BitField name="PRIV90" description="privileged-only access permission for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 90." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 90." start="0x1" />
+      </BitField>
+      <BitField name="PRIV91" description="privileged-only access permission for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 91." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 91." start="0x1" />
+      </BitField>
+      <BitField name="PRIV92" description="privileged-only access permission for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 92." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 92." start="0x1" />
+      </BitField>
+      <BitField name="PRIV93" description="privileged-only access permission for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 93." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 93." start="0x1" />
+      </BitField>
+      <BitField name="PRIV94" description="privileged-only access permission for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 94." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 94." start="0x1" />
+      </BitField>
+      <BitField name="PRIV95" description="privileged-only access permission for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 95." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 95." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR3" description="RIFSC RISFC slave privileged register 3" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV96" description="privileged-only access permission for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 96." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 96." start="0x1" />
+      </BitField>
+      <BitField name="PRIV97" description="privileged-only access permission for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 97." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 97." start="0x1" />
+      </BitField>
+      <BitField name="PRIV98" description="privileged-only access permission for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 98." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 98." start="0x1" />
+      </BitField>
+      <BitField name="PRIV99" description="privileged-only access permission for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 99." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 99." start="0x1" />
+      </BitField>
+      <BitField name="PRIV100" description="privileged-only access permission for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 100." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 100." start="0x1" />
+      </BitField>
+      <BitField name="PRIV101" description="privileged-only access permission for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 101." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 101." start="0x1" />
+      </BitField>
+      <BitField name="PRIV102" description="privileged-only access permission for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 102." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 102." start="0x1" />
+      </BitField>
+      <BitField name="PRIV103" description="privileged-only access permission for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 103." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 103." start="0x1" />
+      </BitField>
+      <BitField name="PRIV104" description="privileged-only access permission for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 104." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 104." start="0x1" />
+      </BitField>
+      <BitField name="PRIV105" description="privileged-only access permission for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 105." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 105." start="0x1" />
+      </BitField>
+      <BitField name="PRIV106" description="privileged-only access permission for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 106." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 106." start="0x1" />
+      </BitField>
+      <BitField name="PRIV107" description="privileged-only access permission for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 107." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 107." start="0x1" />
+      </BitField>
+      <BitField name="PRIV108" description="privileged-only access permission for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 108." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 108." start="0x1" />
+      </BitField>
+      <BitField name="PRIV109" description="privileged-only access permission for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 109." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 109." start="0x1" />
+      </BitField>
+      <BitField name="PRIV110" description="privileged-only access permission for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 110." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 110." start="0x1" />
+      </BitField>
+      <BitField name="PRIV111" description="privileged-only access permission for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 111." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 111." start="0x1" />
+      </BitField>
+      <BitField name="PRIV112" description="privileged-only access permission for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 112." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 112." start="0x1" />
+      </BitField>
+      <BitField name="PRIV113" description="privileged-only access permission for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 113." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 113." start="0x1" />
+      </BitField>
+      <BitField name="PRIV114" description="privileged-only access permission for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 114." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 114." start="0x1" />
+      </BitField>
+      <BitField name="PRIV115" description="privileged-only access permission for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 115." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 115." start="0x1" />
+      </BitField>
+      <BitField name="PRIV116" description="privileged-only access permission for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 116." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 116." start="0x1" />
+      </BitField>
+      <BitField name="PRIV117" description="privileged-only access permission for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 117." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 117." start="0x1" />
+      </BitField>
+      <BitField name="PRIV118" description="privileged-only access permission for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 118." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 118." start="0x1" />
+      </BitField>
+      <BitField name="PRIV119" description="privileged-only access permission for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 119." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 119." start="0x1" />
+      </BitField>
+      <BitField name="PRIV120" description="privileged-only access permission for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 120." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 120." start="0x1" />
+      </BitField>
+      <BitField name="PRIV121" description="privileged-only access permission for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 121." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 121." start="0x1" />
+      </BitField>
+      <BitField name="PRIV122" description="privileged-only access permission for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 122." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 122." start="0x1" />
+      </BitField>
+      <BitField name="PRIV123" description="privileged-only access permission for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 123." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 123." start="0x1" />
+      </BitField>
+      <BitField name="PRIV124" description="privileged-only access permission for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 124." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 124." start="0x1" />
+      </BitField>
+      <BitField name="PRIV125" description="privileged-only access permission for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 125." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 125." start="0x1" />
+      </BitField>
+      <BitField name="PRIV126" description="privileged-only access permission for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 126." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 126." start="0x1" />
+      </BitField>
+      <BitField name="PRIV127" description="privileged-only access permission for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 127." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 127." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR4" description="RIFSC RISFC slave privileged register 4" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV128" description="privileged-only access permission for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 128." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 128." start="0x1" />
+      </BitField>
+      <BitField name="PRIV129" description="privileged-only access permission for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 129." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 129." start="0x1" />
+      </BitField>
+      <BitField name="PRIV130" description="privileged-only access permission for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 130." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 130." start="0x1" />
+      </BitField>
+      <BitField name="PRIV131" description="privileged-only access permission for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 131." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 131." start="0x1" />
+      </BitField>
+      <BitField name="PRIV132" description="privileged-only access permission for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 132." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 132." start="0x1" />
+      </BitField>
+      <BitField name="PRIV133" description="privileged-only access permission for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 133." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 133." start="0x1" />
+      </BitField>
+      <BitField name="PRIV134" description="privileged-only access permission for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 134." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 134." start="0x1" />
+      </BitField>
+      <BitField name="PRIV135" description="privileged-only access permission for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 135." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 135." start="0x1" />
+      </BitField>
+      <BitField name="PRIV136" description="privileged-only access permission for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 136." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 136." start="0x1" />
+      </BitField>
+      <BitField name="PRIV137" description="privileged-only access permission for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 137." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 137." start="0x1" />
+      </BitField>
+      <BitField name="PRIV138" description="privileged-only access permission for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 138." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 138." start="0x1" />
+      </BitField>
+      <BitField name="PRIV139" description="privileged-only access permission for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 139." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 139." start="0x1" />
+      </BitField>
+      <BitField name="PRIV140" description="privileged-only access permission for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 140." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 140." start="0x1" />
+      </BitField>
+      <BitField name="PRIV141" description="privileged-only access permission for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 141." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 141." start="0x1" />
+      </BitField>
+      <BitField name="PRIV142" description="privileged-only access permission for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 142." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 142." start="0x1" />
+      </BitField>
+      <BitField name="PRIV143" description="privileged-only access permission for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 143." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 143." start="0x1" />
+      </BitField>
+      <BitField name="PRIV144" description="privileged-only access permission for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 144." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 144." start="0x1" />
+      </BitField>
+      <BitField name="PRIV145" description="privileged-only access permission for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 145." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 145." start="0x1" />
+      </BitField>
+      <BitField name="PRIV146" description="privileged-only access permission for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 146." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 146." start="0x1" />
+      </BitField>
+      <BitField name="PRIV147" description="privileged-only access permission for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 147." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 147." start="0x1" />
+      </BitField>
+      <BitField name="PRIV148" description="privileged-only access permission for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 148." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 148." start="0x1" />
+      </BitField>
+      <BitField name="PRIV149" description="privileged-only access permission for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 149." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 149." start="0x1" />
+      </BitField>
+      <BitField name="PRIV150" description="privileged-only access permission for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 150." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 150." start="0x1" />
+      </BitField>
+      <BitField name="PRIV151" description="privileged-only access permission for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 151." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 151." start="0x1" />
+      </BitField>
+      <BitField name="PRIV152" description="privileged-only access permission for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 152." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 152." start="0x1" />
+      </BitField>
+      <BitField name="PRIV153" description="privileged-only access permission for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 153." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 153." start="0x1" />
+      </BitField>
+      <BitField name="PRIV154" description="privileged-only access permission for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 154." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 154." start="0x1" />
+      </BitField>
+      <BitField name="PRIV155" description="privileged-only access permission for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 155." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 155." start="0x1" />
+      </BitField>
+      <BitField name="PRIV156" description="privileged-only access permission for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 156." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 156." start="0x1" />
+      </BitField>
+      <BitField name="PRIV157" description="privileged-only access permission for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 157." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 157." start="0x1" />
+      </BitField>
+      <BitField name="PRIV158" description="privileged-only access permission for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 158." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 158." start="0x1" />
+      </BitField>
+      <BitField name="PRIV159" description="privileged-only access permission for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 159." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 159." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_PRIVCFGR5" description="RIFSC RISFC slave privileged register 5" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRIV160" description="privileged-only access permission for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 160." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 160." start="0x1" />
+      </BitField>
+      <BitField name="PRIV161" description="privileged-only access permission for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 161." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 161." start="0x1" />
+      </BitField>
+      <BitField name="PRIV162" description="privileged-only access permission for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 162." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 162." start="0x1" />
+      </BitField>
+      <BitField name="PRIV163" description="privileged-only access permission for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 163." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 163." start="0x1" />
+      </BitField>
+      <BitField name="PRIV164" description="privileged-only access permission for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 164." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 164." start="0x1" />
+      </BitField>
+      <BitField name="PRIV165" description="privileged-only access permission for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 165." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 165." start="0x1" />
+      </BitField>
+      <BitField name="PRIV166" description="privileged-only access permission for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 166." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 166." start="0x1" />
+      </BitField>
+      <BitField name="PRIV167" description="privileged-only access permission for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 167." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 167." start="0x1" />
+      </BitField>
+      <BitField name="PRIV168" description="privileged-only access permission for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 168." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 168." start="0x1" />
+      </BitField>
+      <BitField name="PRIV169" description="privileged-only access permission for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 169." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 169." start="0x1" />
+      </BitField>
+      <BitField name="PRIV170" description="privileged-only access permission for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 170." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 170." start="0x1" />
+      </BitField>
+      <BitField name="PRIV171" description="privileged-only access permission for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 171." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 171." start="0x1" />
+      </BitField>
+      <BitField name="PRIV172" description="privileged-only access permission for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 172." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 172." start="0x1" />
+      </BitField>
+      <BitField name="PRIV173" description="privileged-only access permission for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 173." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 173." start="0x1" />
+      </BitField>
+      <BitField name="PRIV174" description="privileged-only access permission for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 174." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 174." start="0x1" />
+      </BitField>
+      <BitField name="PRIV175" description="privileged-only access permission for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 175." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 175." start="0x1" />
+      </BitField>
+      <BitField name="PRIV176" description="privileged-only access permission for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 176." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 176." start="0x1" />
+      </BitField>
+      <BitField name="PRIV177" description="privileged-only access permission for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 177." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 177." start="0x1" />
+      </BitField>
+      <BitField name="PRIV178" description="privileged-only access permission for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 178." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 178." start="0x1" />
+      </BitField>
+      <BitField name="PRIV179" description="privileged-only access permission for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 179." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 179." start="0x1" />
+      </BitField>
+      <BitField name="PRIV180" description="privileged-only access permission for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 180." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 180." start="0x1" />
+      </BitField>
+      <BitField name="PRIV181" description="privileged-only access permission for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 181." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 181." start="0x1" />
+      </BitField>
+      <BitField name="PRIV182" description="privileged-only access permission for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 182." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 182." start="0x1" />
+      </BitField>
+      <BitField name="PRIV183" description="privileged-only access permission for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 183." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 183." start="0x1" />
+      </BitField>
+      <BitField name="PRIV184" description="privileged-only access permission for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 184." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 184." start="0x1" />
+      </BitField>
+      <BitField name="PRIV185" description="privileged-only access permission for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 185." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 185." start="0x1" />
+      </BitField>
+      <BitField name="PRIV186" description="privileged-only access permission for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 186." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 186." start="0x1" />
+      </BitField>
+      <BitField name="PRIV187" description="privileged-only access permission for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 187." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 187." start="0x1" />
+      </BitField>
+      <BitField name="PRIV188" description="privileged-only access permission for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 188." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 188." start="0x1" />
+      </BitField>
+      <BitField name="PRIV189" description="privileged-only access permission for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 189." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 189." start="0x1" />
+      </BitField>
+      <BitField name="PRIV190" description="privileged-only access permission for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 190." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 190." start="0x1" />
+      </BitField>
+      <BitField name="PRIV191" description="privileged-only access permission for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged data access are granted to the peripheral 191." start="0x0" />
+        <Enum name="B_0x1" description="Privileged data access only are granted to the peripheral 191." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR0" description="RIFSC RISC slave resource configuration lock register 0" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK0" description="resource lock for peripheral 0" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC0 in RIFSC_RISC_SECCFGRx and PRIV0 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC0 and PRIV0 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK1" description="resource lock for peripheral 1" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC1 in RIFSC_RISC_SECCFGRx and PRIV1 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC1 and PRIV1 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK2" description="resource lock for peripheral 2" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC2 in RIFSC_RISC_SECCFGRx and PRIV2 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC2 and PRIV2 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK3" description="resource lock for peripheral 3" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC3 in RIFSC_RISC_SECCFGRx and PRIV3 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC3 and PRIV3 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK4" description="resource lock for peripheral 4" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC4 in RIFSC_RISC_SECCFGRx and PRIV4 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC4 and PRIV4 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK5" description="resource lock for peripheral 5" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC5 in RIFSC_RISC_SECCFGRx and PRIV5 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC5 and PRIV5 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK6" description="resource lock for peripheral 6" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC6 in RIFSC_RISC_SECCFGRx and PRIV6 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC6 and PRIV6 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK7" description="resource lock for peripheral 7" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC7 in RIFSC_RISC_SECCFGRx and PRIV7 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC7 and PRIV7 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK8" description="resource lock for peripheral 8" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC8 in RIFSC_RISC_SECCFGRx and PRIV8 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC8 and PRIV8 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK9" description="resource lock for peripheral 9" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC9 in RIFSC_RISC_SECCFGRx and PRIV9 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC9 and PRIV9 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK10" description="resource lock for peripheral 10" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC10 in RIFSC_RISC_SECCFGRx and PRIV10 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC10 and PRIV10 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK11" description="resource lock for peripheral 11" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC11 in RIFSC_RISC_SECCFGRx and PRIV11 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC11 and PRIV11 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK12" description="resource lock for peripheral 12" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC12 in RIFSC_RISC_SECCFGRx and PRIV12 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC12 and PRIV12 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK13" description="resource lock for peripheral 13" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC13 in RIFSC_RISC_SECCFGRx and PRIV13 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC13 and PRIV13 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK14" description="resource lock for peripheral 14" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC14 in RIFSC_RISC_SECCFGRx and PRIV14 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC14 and PRIV14 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK15" description="resource lock for peripheral 15" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC15 in RIFSC_RISC_SECCFGRx and PRIV15 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC15 and PRIV15 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK16" description="resource lock for peripheral 16" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC16 in RIFSC_RISC_SECCFGRx and PRIV16 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC16 and PRIV16 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK17" description="resource lock for peripheral 17" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC17 in RIFSC_RISC_SECCFGRx and PRIV17 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC17 and PRIV17 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK18" description="resource lock for peripheral 18" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC18 in RIFSC_RISC_SECCFGRx and PRIV18 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC18 and PRIV18 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK19" description="resource lock for peripheral 19" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC19 in RIFSC_RISC_SECCFGRx and PRIV19 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC19 and PRIV19 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK20" description="resource lock for peripheral 20" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC20 in RIFSC_RISC_SECCFGRx and PRIV20 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC20 and PRIV20 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK21" description="resource lock for peripheral 21" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC21 in RIFSC_RISC_SECCFGRx and PRIV21 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC21 and PRIV21 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK22" description="resource lock for peripheral 22" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC22 in RIFSC_RISC_SECCFGRx and PRIV22 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC22 and PRIV22 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK23" description="resource lock for peripheral 23" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC23 in RIFSC_RISC_SECCFGRx and PRIV23 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC23 and PRIV23 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK24" description="resource lock for peripheral 24" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC24 in RIFSC_RISC_SECCFGRx and PRIV24 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC24 and PRIV24 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK25" description="resource lock for peripheral 25" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC25 in RIFSC_RISC_SECCFGRx and PRIV25 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC25 and PRIV25 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK26" description="resource lock for peripheral 26" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC26 in RIFSC_RISC_SECCFGRx and PRIV26 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC26 and PRIV26 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK27" description="resource lock for peripheral 27" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC27 in RIFSC_RISC_SECCFGRx and PRIV27 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC27 and PRIV27 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK28" description="resource lock for peripheral 28" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC28 in RIFSC_RISC_SECCFGRx and PRIV28 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC28 and PRIV28 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK29" description="resource lock for peripheral 29" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC29 in RIFSC_RISC_SECCFGRx and PRIV29 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC29 and PRIV29 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK30" description="resource lock for peripheral 30" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC30 in RIFSC_RISC_SECCFGRx and PRIV30 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC30 and PRIV30 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK31" description="resource lock for peripheral 31" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC31 in RIFSC_RISC_SECCFGRx and PRIV31 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC31 and PRIV31 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR1" description="RIFSC RISC slave resource configuration lock register 1" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK32" description="resource lock for peripheral 32" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC32 in RIFSC_RISC_SECCFGRx and PRIV32 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC32 and PRIV32 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK33" description="resource lock for peripheral 33" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC33 in RIFSC_RISC_SECCFGRx and PRIV33 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC33 and PRIV33 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK34" description="resource lock for peripheral 34" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC34 in RIFSC_RISC_SECCFGRx and PRIV34 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC34 and PRIV34 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK35" description="resource lock for peripheral 35" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC35 in RIFSC_RISC_SECCFGRx and PRIV35 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC35 and PRIV35 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK36" description="resource lock for peripheral 36" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC36 in RIFSC_RISC_SECCFGRx and PRIV36 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC36 and PRIV36 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK37" description="resource lock for peripheral 37" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC37 in RIFSC_RISC_SECCFGRx and PRIV37 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC37 and PRIV37 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK38" description="resource lock for peripheral 38" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC38 in RIFSC_RISC_SECCFGRx and PRIV38 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC38 and PRIV38 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK39" description="resource lock for peripheral 39" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC39 in RIFSC_RISC_SECCFGRx and PRIV39 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC39 and PRIV39 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK40" description="resource lock for peripheral 40" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC40 in RIFSC_RISC_SECCFGRx and PRIV40 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC40 and PRIV40 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK41" description="resource lock for peripheral 41" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC41 in RIFSC_RISC_SECCFGRx and PRIV41 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC41 and PRIV41 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK42" description="resource lock for peripheral 42" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC42 in RIFSC_RISC_SECCFGRx and PRIV42 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC42 and PRIV42 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK43" description="resource lock for peripheral 43" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC43 in RIFSC_RISC_SECCFGRx and PRIV43 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC43 and PRIV43 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK44" description="resource lock for peripheral 44" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC44 in RIFSC_RISC_SECCFGRx and PRIV44 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC44 and PRIV44 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK45" description="resource lock for peripheral 45" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC45 in RIFSC_RISC_SECCFGRx and PRIV45 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC45 and PRIV45 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK46" description="resource lock for peripheral 46" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC46 in RIFSC_RISC_SECCFGRx and PRIV46 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC46 and PRIV46 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK47" description="resource lock for peripheral 47" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC47 in RIFSC_RISC_SECCFGRx and PRIV47 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC47 and PRIV47 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK48" description="resource lock for peripheral 48" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC48 in RIFSC_RISC_SECCFGRx and PRIV48 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC48 and PRIV48 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK49" description="resource lock for peripheral 49" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC49 in RIFSC_RISC_SECCFGRx and PRIV49 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC49 and PRIV49 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK50" description="resource lock for peripheral 50" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC50 in RIFSC_RISC_SECCFGRx and PRIV50 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC50 and PRIV50 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK51" description="resource lock for peripheral 51" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC51 in RIFSC_RISC_SECCFGRx and PRIV51 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC51 and PRIV51 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK52" description="resource lock for peripheral 52" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC52 in RIFSC_RISC_SECCFGRx and PRIV52 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC52 and PRIV52 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK53" description="resource lock for peripheral 53" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC53 in RIFSC_RISC_SECCFGRx and PRIV53 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC53 and PRIV53 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK54" description="resource lock for peripheral 54" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC54 in RIFSC_RISC_SECCFGRx and PRIV54 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC54 and PRIV54 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK55" description="resource lock for peripheral 55" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC55 in RIFSC_RISC_SECCFGRx and PRIV55 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC55 and PRIV55 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK56" description="resource lock for peripheral 56" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC56 in RIFSC_RISC_SECCFGRx and PRIV56 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC56 and PRIV56 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK57" description="resource lock for peripheral 57" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC57 in RIFSC_RISC_SECCFGRx and PRIV57 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC57 and PRIV57 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK58" description="resource lock for peripheral 58" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC58 in RIFSC_RISC_SECCFGRx and PRIV58 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC58 and PRIV58 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK59" description="resource lock for peripheral 59" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC59 in RIFSC_RISC_SECCFGRx and PRIV59 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC59 and PRIV59 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK60" description="resource lock for peripheral 60" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC60 in RIFSC_RISC_SECCFGRx and PRIV60 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC60 and PRIV60 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK61" description="resource lock for peripheral 61" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC61 in RIFSC_RISC_SECCFGRx and PRIV61 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC61 and PRIV61 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK62" description="resource lock for peripheral 62" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC62 in RIFSC_RISC_SECCFGRx and PRIV62 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC62 and PRIV62 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK63" description="resource lock for peripheral 63" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC63 in RIFSC_RISC_SECCFGRx and PRIV63 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC63 and PRIV63 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR2" description="RIFSC RISC slave resource configuration lock register 2" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK64" description="resource lock for peripheral 64" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC64 in RIFSC_RISC_SECCFGRx and PRIV64 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC64 and PRIV64 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK65" description="resource lock for peripheral 65" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC65 in RIFSC_RISC_SECCFGRx and PRIV65 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC65 and PRIV65 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK66" description="resource lock for peripheral 66" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC66 in RIFSC_RISC_SECCFGRx and PRIV66 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC66 and PRIV66 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK67" description="resource lock for peripheral 67" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC67 in RIFSC_RISC_SECCFGRx and PRIV67 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC67 and PRIV67 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK68" description="resource lock for peripheral 68" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC68 in RIFSC_RISC_SECCFGRx and PRIV68 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC68 and PRIV68 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK69" description="resource lock for peripheral 69" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC69 in RIFSC_RISC_SECCFGRx and PRIV69 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC69 and PRIV69 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK70" description="resource lock for peripheral 70" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC70 in RIFSC_RISC_SECCFGRx and PRIV70 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC70 and PRIV70 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK71" description="resource lock for peripheral 71" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC71 in RIFSC_RISC_SECCFGRx and PRIV71 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC71 and PRIV71 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK72" description="resource lock for peripheral 72" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC72 in RIFSC_RISC_SECCFGRx and PRIV72 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC72 and PRIV72 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK73" description="resource lock for peripheral 73" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC73 in RIFSC_RISC_SECCFGRx and PRIV73 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC73 and PRIV73 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK74" description="resource lock for peripheral 74" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC74 in RIFSC_RISC_SECCFGRx and PRIV74 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC74 and PRIV74 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK75" description="resource lock for peripheral 75" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC75 in RIFSC_RISC_SECCFGRx and PRIV75 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC75 and PRIV75 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK76" description="resource lock for peripheral 76" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC76 in RIFSC_RISC_SECCFGRx and PRIV76 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC76 and PRIV76 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK77" description="resource lock for peripheral 77" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC77 in RIFSC_RISC_SECCFGRx and PRIV77 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC77 and PRIV77 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK78" description="resource lock for peripheral 78" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC78 in RIFSC_RISC_SECCFGRx and PRIV78 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC78 and PRIV78 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK79" description="resource lock for peripheral 79" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC79 in RIFSC_RISC_SECCFGRx and PRIV79 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC79 and PRIV79 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK80" description="resource lock for peripheral 80" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC80 in RIFSC_RISC_SECCFGRx and PRIV80 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC80 and PRIV80 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK81" description="resource lock for peripheral 81" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC81 in RIFSC_RISC_SECCFGRx and PRIV81 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC81 and PRIV81 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK82" description="resource lock for peripheral 82" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC82 in RIFSC_RISC_SECCFGRx and PRIV82 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC82 and PRIV82 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK83" description="resource lock for peripheral 83" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC83 in RIFSC_RISC_SECCFGRx and PRIV83 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC83 and PRIV83 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK84" description="resource lock for peripheral 84" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC84 in RIFSC_RISC_SECCFGRx and PRIV84 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC84 and PRIV84 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK85" description="resource lock for peripheral 85" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC85 in RIFSC_RISC_SECCFGRx and PRIV85 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC85 and PRIV85 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK86" description="resource lock for peripheral 86" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC86 in RIFSC_RISC_SECCFGRx and PRIV86 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC86 and PRIV86 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK87" description="resource lock for peripheral 87" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC87 in RIFSC_RISC_SECCFGRx and PRIV87 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC87 and PRIV87 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK88" description="resource lock for peripheral 88" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC88 in RIFSC_RISC_SECCFGRx and PRIV88 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC88 and PRIV88 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK89" description="resource lock for peripheral 89" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC89 in RIFSC_RISC_SECCFGRx and PRIV89 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC89 and PRIV89 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK90" description="resource lock for peripheral 90" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC90 in RIFSC_RISC_SECCFGRx and PRIV90 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC90 and PRIV90 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK91" description="resource lock for peripheral 91" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC91 in RIFSC_RISC_SECCFGRx and PRIV91 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC91 and PRIV91 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK92" description="resource lock for peripheral 92" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC92 in RIFSC_RISC_SECCFGRx and PRIV92 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC92 and PRIV92 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK93" description="resource lock for peripheral 93" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC93 in RIFSC_RISC_SECCFGRx and PRIV93 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC93 and PRIV93 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK94" description="resource lock for peripheral 94" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC94 in RIFSC_RISC_SECCFGRx and PRIV94 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC94 and PRIV94 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK95" description="resource lock for peripheral 95" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC95 in RIFSC_RISC_SECCFGRx and PRIV95 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC95 and PRIV95 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR3" description="RIFSC RISC slave resource configuration lock register 3" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK96" description="resource lock for peripheral 96" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC96 in RIFSC_RISC_SECCFGRx and PRIV96 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC96 and PRIV96 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK97" description="resource lock for peripheral 97" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC97 in RIFSC_RISC_SECCFGRx and PRIV97 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC97 and PRIV97 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK98" description="resource lock for peripheral 98" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC98 in RIFSC_RISC_SECCFGRx and PRIV98 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC98 and PRIV98 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK99" description="resource lock for peripheral 99" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC99 in RIFSC_RISC_SECCFGRx and PRIV99 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC99 and PRIV99 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK100" description="resource lock for peripheral 100" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC100 in RIFSC_RISC_SECCFGRx and PRIV100 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC100 and PRIV100 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK101" description="resource lock for peripheral 101" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC101 in RIFSC_RISC_SECCFGRx and PRIV101 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC101 and PRIV101 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK102" description="resource lock for peripheral 102" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC102 in RIFSC_RISC_SECCFGRx and PRIV102 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC102 and PRIV102 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK103" description="resource lock for peripheral 103" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC103 in RIFSC_RISC_SECCFGRx and PRIV103 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC103 and PRIV103 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK104" description="resource lock for peripheral 104" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC104 in RIFSC_RISC_SECCFGRx and PRIV104 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC104 and PRIV104 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK105" description="resource lock for peripheral 105" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC105 in RIFSC_RISC_SECCFGRx and PRIV105 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC105 and PRIV105 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK106" description="resource lock for peripheral 106" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC106 in RIFSC_RISC_SECCFGRx and PRIV106 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC106 and PRIV106 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK107" description="resource lock for peripheral 107" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC107 in RIFSC_RISC_SECCFGRx and PRIV107 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC107 and PRIV107 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK108" description="resource lock for peripheral 108" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC108 in RIFSC_RISC_SECCFGRx and PRIV108 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC108 and PRIV108 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK109" description="resource lock for peripheral 109" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC109 in RIFSC_RISC_SECCFGRx and PRIV109 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC109 and PRIV109 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK110" description="resource lock for peripheral 110" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC110 in RIFSC_RISC_SECCFGRx and PRIV110 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC110 and PRIV110 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK111" description="resource lock for peripheral 111" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC111 in RIFSC_RISC_SECCFGRx and PRIV111 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC111 and PRIV111 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK112" description="resource lock for peripheral 112" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC112 in RIFSC_RISC_SECCFGRx and PRIV112 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC112 and PRIV112 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK113" description="resource lock for peripheral 113" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC113 in RIFSC_RISC_SECCFGRx and PRIV113 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC113 and PRIV113 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK114" description="resource lock for peripheral 114" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC114 in RIFSC_RISC_SECCFGRx and PRIV114 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC114 and PRIV114 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK115" description="resource lock for peripheral 115" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC115 in RIFSC_RISC_SECCFGRx and PRIV115 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC115 and PRIV115 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK116" description="resource lock for peripheral 116" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC116 in RIFSC_RISC_SECCFGRx and PRIV116 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC116 and PRIV116 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK117" description="resource lock for peripheral 117" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC117 in RIFSC_RISC_SECCFGRx and PRIV117 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC117 and PRIV117 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK118" description="resource lock for peripheral 118" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC118 in RIFSC_RISC_SECCFGRx and PRIV118 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC118 and PRIV118 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK119" description="resource lock for peripheral 119" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC119 in RIFSC_RISC_SECCFGRx and PRIV119 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC119 and PRIV119 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK120" description="resource lock for peripheral 120" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC120 in RIFSC_RISC_SECCFGRx and PRIV120 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC120 and PRIV120 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK121" description="resource lock for peripheral 121" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC121 in RIFSC_RISC_SECCFGRx and PRIV121 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC121 and PRIV121 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK122" description="resource lock for peripheral 122" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC122 in RIFSC_RISC_SECCFGRx and PRIV122 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC122 and PRIV122 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK123" description="resource lock for peripheral 123" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC123 in RIFSC_RISC_SECCFGRx and PRIV123 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC123 and PRIV123 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK124" description="resource lock for peripheral 124" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC124 in RIFSC_RISC_SECCFGRx and PRIV124 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC124 and PRIV124 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK125" description="resource lock for peripheral 125" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC125 in RIFSC_RISC_SECCFGRx and PRIV125 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC125 and PRIV125 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK126" description="resource lock for peripheral 126" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC126 in RIFSC_RISC_SECCFGRx and PRIV126 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC126 and PRIV126 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK127" description="resource lock for peripheral 127" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC127 in RIFSC_RISC_SECCFGRx and PRIV127 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC127 and PRIV127 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR4" description="RIFSC RISC slave resource configuration lock register 4" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK128" description="resource lock for peripheral 128" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC128 in RIFSC_RISC_SECCFGRx and PRIV128 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC128 and PRIV128 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK129" description="resource lock for peripheral 129" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC129 in RIFSC_RISC_SECCFGRx and PRIV129 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC129 and PRIV129 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK130" description="resource lock for peripheral 130" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC130 in RIFSC_RISC_SECCFGRx and PRIV130 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC130 and PRIV130 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK131" description="resource lock for peripheral 131" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC131 in RIFSC_RISC_SECCFGRx and PRIV131 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC131 and PRIV131 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK132" description="resource lock for peripheral 132" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC132 in RIFSC_RISC_SECCFGRx and PRIV132 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC132 and PRIV132 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK133" description="resource lock for peripheral 133" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC133 in RIFSC_RISC_SECCFGRx and PRIV133 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC133 and PRIV133 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK134" description="resource lock for peripheral 134" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC134 in RIFSC_RISC_SECCFGRx and PRIV134 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC134 and PRIV134 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK135" description="resource lock for peripheral 135" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC135 in RIFSC_RISC_SECCFGRx and PRIV135 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC135 and PRIV135 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK136" description="resource lock for peripheral 136" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC136 in RIFSC_RISC_SECCFGRx and PRIV136 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC136 and PRIV136 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK137" description="resource lock for peripheral 137" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC137 in RIFSC_RISC_SECCFGRx and PRIV137 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC137 and PRIV137 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK138" description="resource lock for peripheral 138" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC138 in RIFSC_RISC_SECCFGRx and PRIV138 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC138 and PRIV138 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK139" description="resource lock for peripheral 139" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC139 in RIFSC_RISC_SECCFGRx and PRIV139 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC139 and PRIV139 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK140" description="resource lock for peripheral 140" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC140 in RIFSC_RISC_SECCFGRx and PRIV140 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC140 and PRIV140 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK141" description="resource lock for peripheral 141" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC141 in RIFSC_RISC_SECCFGRx and PRIV141 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC141 and PRIV141 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK142" description="resource lock for peripheral 142" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC142 in RIFSC_RISC_SECCFGRx and PRIV142 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC142 and PRIV142 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK143" description="resource lock for peripheral 143" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC143 in RIFSC_RISC_SECCFGRx and PRIV143 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC143 and PRIV143 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK144" description="resource lock for peripheral 144" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC144 in RIFSC_RISC_SECCFGRx and PRIV144 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC144 and PRIV144 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK145" description="resource lock for peripheral 145" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC145 in RIFSC_RISC_SECCFGRx and PRIV145 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC145 and PRIV145 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK146" description="resource lock for peripheral 146" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC146 in RIFSC_RISC_SECCFGRx and PRIV146 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC146 and PRIV146 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK147" description="resource lock for peripheral 147" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC147 in RIFSC_RISC_SECCFGRx and PRIV147 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC147 and PRIV147 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK148" description="resource lock for peripheral 148" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC148 in RIFSC_RISC_SECCFGRx and PRIV148 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC148 and PRIV148 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK149" description="resource lock for peripheral 149" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC149 in RIFSC_RISC_SECCFGRx and PRIV149 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC149 and PRIV149 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK150" description="resource lock for peripheral 150" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC150 in RIFSC_RISC_SECCFGRx and PRIV150 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC150 and PRIV150 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK151" description="resource lock for peripheral 151" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC151 in RIFSC_RISC_SECCFGRx and PRIV151 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC151 and PRIV151 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK152" description="resource lock for peripheral 152" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC152 in RIFSC_RISC_SECCFGRx and PRIV152 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC152 and PRIV152 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK153" description="resource lock for peripheral 153" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC153 in RIFSC_RISC_SECCFGRx and PRIV153 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC153 and PRIV153 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK154" description="resource lock for peripheral 154" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC154 in RIFSC_RISC_SECCFGRx and PRIV154 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC154 and PRIV154 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK155" description="resource lock for peripheral 155" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC155 in RIFSC_RISC_SECCFGRx and PRIV155 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC155 and PRIV155 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK156" description="resource lock for peripheral 156" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC156 in RIFSC_RISC_SECCFGRx and PRIV156 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC156 and PRIV156 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK157" description="resource lock for peripheral 157" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC157 in RIFSC_RISC_SECCFGRx and PRIV157 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC157 and PRIV157 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK158" description="resource lock for peripheral 158" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC158 in RIFSC_RISC_SECCFGRx and PRIV158 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC158 and PRIV158 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK159" description="resource lock for peripheral 159" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC159 in RIFSC_RISC_SECCFGRx and PRIV159 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC159 and PRIV159 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RISC_RCFGLOCKR5" description="RIFSC RISC slave resource configuration lock register 5" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RLOCK160" description="resource lock for peripheral 160" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC160 in RIFSC_RISC_SECCFGRx and PRIV160 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC160 and PRIV160 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK161" description="resource lock for peripheral 161" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC161 in RIFSC_RISC_SECCFGRx and PRIV161 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC161 and PRIV161 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK162" description="resource lock for peripheral 162" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC162 in RIFSC_RISC_SECCFGRx and PRIV162 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC162 and PRIV162 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK163" description="resource lock for peripheral 163" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC163 in RIFSC_RISC_SECCFGRx and PRIV163 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC163 and PRIV163 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK164" description="resource lock for peripheral 164" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC164 in RIFSC_RISC_SECCFGRx and PRIV164 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC164 and PRIV164 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK165" description="resource lock for peripheral 165" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC165 in RIFSC_RISC_SECCFGRx and PRIV165 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC165 and PRIV165 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK166" description="resource lock for peripheral 166" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC166 in RIFSC_RISC_SECCFGRx and PRIV166 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC166 and PRIV166 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK167" description="resource lock for peripheral 167" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC167 in RIFSC_RISC_SECCFGRx and PRIV167 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC167 and PRIV167 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK168" description="resource lock for peripheral 168" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC168 in RIFSC_RISC_SECCFGRx and PRIV168 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC168 and PRIV168 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK169" description="resource lock for peripheral 169" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC169 in RIFSC_RISC_SECCFGRx and PRIV169 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC169 and PRIV169 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK170" description="resource lock for peripheral 170" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC170 in RIFSC_RISC_SECCFGRx and PRIV170 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC170 and PRIV170 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK171" description="resource lock for peripheral 171" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC171 in RIFSC_RISC_SECCFGRx and PRIV171 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC171 and PRIV171 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK172" description="resource lock for peripheral 172" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC172 in RIFSC_RISC_SECCFGRx and PRIV172 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC172 and PRIV172 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK173" description="resource lock for peripheral 173" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC173 in RIFSC_RISC_SECCFGRx and PRIV173 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC173 and PRIV173 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK174" description="resource lock for peripheral 174" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC174 in RIFSC_RISC_SECCFGRx and PRIV174 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC174 and PRIV174 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK175" description="resource lock for peripheral 175" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC175 in RIFSC_RISC_SECCFGRx and PRIV175 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC175 and PRIV175 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK176" description="resource lock for peripheral 176" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC176 in RIFSC_RISC_SECCFGRx and PRIV176 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC176 and PRIV176 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK177" description="resource lock for peripheral 177" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC177 in RIFSC_RISC_SECCFGRx and PRIV177 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC177 and PRIV177 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK178" description="resource lock for peripheral 178" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC178 in RIFSC_RISC_SECCFGRx and PRIV178 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC178 and PRIV178 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK179" description="resource lock for peripheral 179" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC179 in RIFSC_RISC_SECCFGRx and PRIV179 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC179 and PRIV179 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK180" description="resource lock for peripheral 180" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC180 in RIFSC_RISC_SECCFGRx and PRIV180 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC180 and PRIV180 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK181" description="resource lock for peripheral 181" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC181 in RIFSC_RISC_SECCFGRx and PRIV181 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC181 and PRIV181 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK182" description="resource lock for peripheral 182" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC182 in RIFSC_RISC_SECCFGRx and PRIV182 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC182 and PRIV182 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK183" description="resource lock for peripheral 183" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC183 in RIFSC_RISC_SECCFGRx and PRIV183 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC183 and PRIV183 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK184" description="resource lock for peripheral 184" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC184 in RIFSC_RISC_SECCFGRx and PRIV184 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC184 and PRIV184 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK185" description="resource lock for peripheral 185" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC185 in RIFSC_RISC_SECCFGRx and PRIV185 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC185 and PRIV185 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK186" description="resource lock for peripheral 186" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC186 in RIFSC_RISC_SECCFGRx and PRIV186 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC186 and PRIV186 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK187" description="resource lock for peripheral 187" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC187 in RIFSC_RISC_SECCFGRx and PRIV187 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC187 and PRIV187 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK188" description="resource lock for peripheral 188" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC188 in RIFSC_RISC_SECCFGRx and PRIV188 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC188 and PRIV188 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK189" description="resource lock for peripheral 189" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC189 in RIFSC_RISC_SECCFGRx and PRIV189 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC189 and PRIV189 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK190" description="resource lock for peripheral 190" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC190 in RIFSC_RISC_SECCFGRx and PRIV190 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC190 and PRIV190 are ignored." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK191" description="resource lock for peripheral 191" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SEC191 in RIFSC_RISC_SECCFGRx and PRIV191 in RIFSC_RISC_PRIVCFGRx are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to SEC191 and PRIV191 are ignored." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_CR" description="RIFSC RIMC master configuration register" start="+0xC00" size="4" reset_value="0x00000710" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIFSC RIMC registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RIFSC RIMC registers are ignored." start="0x1" />
+      </BitField>
+      <BitField name="DAPCID" description="debug access port compartment ID" start="8" size="3" access="Read/Write" />
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR0" description="RIFSC RIMC master attribute register 0" start="+0xC10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR1" description="RIFSC RIMC master attribute register 1" start="+0xC14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR2" description="RIFSC RIMC master attribute register 2" start="+0xC18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR3" description="RIFSC RIMC master attribute register 3" start="+0xC1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR4" description="RIFSC RIMC master attribute register 4" start="+0xC20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR5" description="RIFSC RIMC master attribute register 5" start="+0xC24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR6" description="RIFSC RIMC master attribute register 6" start="+0xC28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR7" description="RIFSC RIMC master attribute register 7" start="+0xC2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR8" description="RIFSC RIMC master attribute register 8" start="+0xC30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR9" description="RIFSC RIMC master attribute register 9" start="+0xC34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR10" description="RIFSC RIMC master attribute register 10" start="+0xC38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_RIMC_ATTR11" description="RIFSC RIMC master attribute register 11" start="+0xC3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCID" description="master CID" start="4" size="3" access="Read/Write" />
+      <BitField name="MSEC" description="master secure" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is non-secure." start="0x0" />
+        <Enum name="B_0x1" description="This master is secure." start="0x1" />
+      </BitField>
+      <BitField name="MPRIV" description="master privileged" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="This master is unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="This master is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR0" description="RIFSC peripheral protection status register 0" start="+0xFB0" size="4" reset_value="0xFFFFFF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN0" description="peripheral protection enable 0" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC0, PRIV0, and RLOCK0 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC0, PRIV0, and RLOCK0 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN1" description="peripheral protection enable 1" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC1, PRIV1, and RLOCK1 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC1, PRIV1, and RLOCK1 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN2" description="peripheral protection enable 2" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC2, PRIV2, and RLOCK2 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC2, PRIV2, and RLOCK2 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN3" description="peripheral protection enable 3" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC3, PRIV3, and RLOCK3 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC3, PRIV3, and RLOCK3 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN4" description="peripheral protection enable 4" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC4, PRIV4, and RLOCK4 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC4, PRIV4, and RLOCK4 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN5" description="peripheral protection enable 5" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC5, PRIV5, and RLOCK5 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC5, PRIV5, and RLOCK5 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN6" description="peripheral protection enable 6" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC6, PRIV6, and RLOCK6 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC6, PRIV6, and RLOCK6 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN7" description="peripheral protection enable 7" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC7, PRIV7, and RLOCK7 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC7, PRIV7, and RLOCK7 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN8" description="peripheral protection enable 8" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC8, PRIV8, and RLOCK8 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC8, PRIV8, and RLOCK8 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN9" description="peripheral protection enable 9" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC9, PRIV9, and RLOCK9 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC9, PRIV9, and RLOCK9 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN10" description="peripheral protection enable 10" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC10, PRIV10, and RLOCK10 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC10, PRIV10, and RLOCK10 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN11" description="peripheral protection enable 11" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC11, PRIV11, and RLOCK11 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC11, PRIV11, and RLOCK11 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN12" description="peripheral protection enable 12" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC12, PRIV12, and RLOCK12 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC12, PRIV12, and RLOCK12 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN13" description="peripheral protection enable 13" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC13, PRIV13, and RLOCK13 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC13, PRIV13, and RLOCK13 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN14" description="peripheral protection enable 14" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC14, PRIV14, and RLOCK14 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC14, PRIV14, and RLOCK14 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN15" description="peripheral protection enable 15" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC15, PRIV15, and RLOCK15 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC15, PRIV15, and RLOCK15 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN16" description="peripheral protection enable 16" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC16, PRIV16, and RLOCK16 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC16, PRIV16, and RLOCK16 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN17" description="peripheral protection enable 17" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC17, PRIV17, and RLOCK17 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC17, PRIV17, and RLOCK17 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN18" description="peripheral protection enable 18" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC18, PRIV18, and RLOCK18 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC18, PRIV18, and RLOCK18 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN19" description="peripheral protection enable 19" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC19, PRIV19, and RLOCK19 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC19, PRIV19, and RLOCK19 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN20" description="peripheral protection enable 20" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC20, PRIV20, and RLOCK20 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC20, PRIV20, and RLOCK20 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN21" description="peripheral protection enable 21" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC21, PRIV21, and RLOCK21 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC21, PRIV21, and RLOCK21 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN22" description="peripheral protection enable 22" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC22, PRIV22, and RLOCK22 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC22, PRIV22, and RLOCK22 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN23" description="peripheral protection enable 23" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC23, PRIV23, and RLOCK23 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC23, PRIV23, and RLOCK23 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN24" description="peripheral protection enable 24" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC24, PRIV24, and RLOCK24 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC24, PRIV24, and RLOCK24 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN25" description="peripheral protection enable 25" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC25, PRIV25, and RLOCK25 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC25, PRIV25, and RLOCK25 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN26" description="peripheral protection enable 26" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC26, PRIV26, and RLOCK26 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC26, PRIV26, and RLOCK26 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN27" description="peripheral protection enable 27" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC27, PRIV27, and RLOCK27 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC27, PRIV27, and RLOCK27 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN28" description="peripheral protection enable 28" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC28, PRIV28, and RLOCK28 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC28, PRIV28, and RLOCK28 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN29" description="peripheral protection enable 29" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC29, PRIV29, and RLOCK29 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC29, PRIV29, and RLOCK29 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN30" description="peripheral protection enable 30" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC30, PRIV30, and RLOCK30 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC30, PRIV30, and RLOCK30 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN31" description="peripheral protection enable 31" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC31, PRIV31, and RLOCK31 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC31, PRIV31, and RLOCK31 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR1" description="RIFSC peripheral protection status register 1" start="+0xFB4" size="4" reset_value="0x77FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN32" description="peripheral protection enable 32" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC32, PRIV32, and RLOCK32 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC32, PRIV32, and RLOCK32 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN33" description="peripheral protection enable 33" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC33, PRIV33, and RLOCK33 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC33, PRIV33, and RLOCK33 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN34" description="peripheral protection enable 34" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC34, PRIV34, and RLOCK34 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC34, PRIV34, and RLOCK34 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN35" description="peripheral protection enable 35" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC35, PRIV35, and RLOCK35 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC35, PRIV35, and RLOCK35 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN36" description="peripheral protection enable 36" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC36, PRIV36, and RLOCK36 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC36, PRIV36, and RLOCK36 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN37" description="peripheral protection enable 37" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC37, PRIV37, and RLOCK37 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC37, PRIV37, and RLOCK37 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN38" description="peripheral protection enable 38" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC38, PRIV38, and RLOCK38 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC38, PRIV38, and RLOCK38 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN39" description="peripheral protection enable 39" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC39, PRIV39, and RLOCK39 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC39, PRIV39, and RLOCK39 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN40" description="peripheral protection enable 40" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC40, PRIV40, and RLOCK40 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC40, PRIV40, and RLOCK40 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN41" description="peripheral protection enable 41" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC41, PRIV41, and RLOCK41 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC41, PRIV41, and RLOCK41 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN42" description="peripheral protection enable 42" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC42, PRIV42, and RLOCK42 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC42, PRIV42, and RLOCK42 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN43" description="peripheral protection enable 43" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC43, PRIV43, and RLOCK43 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC43, PRIV43, and RLOCK43 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN44" description="peripheral protection enable 44" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC44, PRIV44, and RLOCK44 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC44, PRIV44, and RLOCK44 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN45" description="peripheral protection enable 45" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC45, PRIV45, and RLOCK45 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC45, PRIV45, and RLOCK45 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN46" description="peripheral protection enable 46" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC46, PRIV46, and RLOCK46 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC46, PRIV46, and RLOCK46 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN47" description="peripheral protection enable 47" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC47, PRIV47, and RLOCK47 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC47, PRIV47, and RLOCK47 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN48" description="peripheral protection enable 48" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC48, PRIV48, and RLOCK48 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC48, PRIV48, and RLOCK48 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN49" description="peripheral protection enable 49" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC49, PRIV49, and RLOCK49 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC49, PRIV49, and RLOCK49 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN50" description="peripheral protection enable 50" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC50, PRIV50, and RLOCK50 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC50, PRIV50, and RLOCK50 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN51" description="peripheral protection enable 51" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC51, PRIV51, and RLOCK51 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC51, PRIV51, and RLOCK51 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN52" description="peripheral protection enable 52" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC52, PRIV52, and RLOCK52 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC52, PRIV52, and RLOCK52 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN53" description="peripheral protection enable 53" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC53, PRIV53, and RLOCK53 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC53, PRIV53, and RLOCK53 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN54" description="peripheral protection enable 54" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC54, PRIV54, and RLOCK54 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC54, PRIV54, and RLOCK54 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN55" description="peripheral protection enable 55" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC55, PRIV55, and RLOCK55 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC55, PRIV55, and RLOCK55 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN56" description="peripheral protection enable 56" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC56, PRIV56, and RLOCK56 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC56, PRIV56, and RLOCK56 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN57" description="peripheral protection enable 57" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC57, PRIV57, and RLOCK57 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC57, PRIV57, and RLOCK57 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN58" description="peripheral protection enable 58" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC58, PRIV58, and RLOCK58 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC58, PRIV58, and RLOCK58 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN59" description="peripheral protection enable 59" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC59, PRIV59, and RLOCK59 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC59, PRIV59, and RLOCK59 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN60" description="peripheral protection enable 60" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC60, PRIV60, and RLOCK60 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC60, PRIV60, and RLOCK60 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN61" description="peripheral protection enable 61" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC61, PRIV61, and RLOCK61 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC61, PRIV61, and RLOCK61 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN62" description="peripheral protection enable 62" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC62, PRIV62, and RLOCK62 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC62, PRIV62, and RLOCK62 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN63" description="peripheral protection enable 63" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC63, PRIV63, and RLOCK63 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC63, PRIV63, and RLOCK63 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR2" description="RIFSC peripheral protection status register 2" start="+0xFB8" size="4" reset_value="0xF7DFF03B" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN64" description="peripheral protection enable 64" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC64, PRIV64, and RLOCK64 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC64, PRIV64, and RLOCK64 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN65" description="peripheral protection enable 65" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC65, PRIV65, and RLOCK65 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC65, PRIV65, and RLOCK65 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN66" description="peripheral protection enable 66" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC66, PRIV66, and RLOCK66 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC66, PRIV66, and RLOCK66 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN67" description="peripheral protection enable 67" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC67, PRIV67, and RLOCK67 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC67, PRIV67, and RLOCK67 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN68" description="peripheral protection enable 68" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC68, PRIV68, and RLOCK68 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC68, PRIV68, and RLOCK68 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN69" description="peripheral protection enable 69" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC69, PRIV69, and RLOCK69 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC69, PRIV69, and RLOCK69 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN70" description="peripheral protection enable 70" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC70, PRIV70, and RLOCK70 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC70, PRIV70, and RLOCK70 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN71" description="peripheral protection enable 71" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC71, PRIV71, and RLOCK71 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC71, PRIV71, and RLOCK71 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN72" description="peripheral protection enable 72" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC72, PRIV72, and RLOCK72 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC72, PRIV72, and RLOCK72 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN73" description="peripheral protection enable 73" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC73, PRIV73, and RLOCK73 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC73, PRIV73, and RLOCK73 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN74" description="peripheral protection enable 74" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC74, PRIV74, and RLOCK74 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC74, PRIV74, and RLOCK74 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN75" description="peripheral protection enable 75" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC75, PRIV75, and RLOCK75 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC75, PRIV75, and RLOCK75 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN76" description="peripheral protection enable 76" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC76, PRIV76, and RLOCK76 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC76, PRIV76, and RLOCK76 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN77" description="peripheral protection enable 77" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC77, PRIV77, and RLOCK77 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC77, PRIV77, and RLOCK77 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN78" description="peripheral protection enable 78" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC78, PRIV78, and RLOCK78 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC78, PRIV78, and RLOCK78 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN79" description="peripheral protection enable 79" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC79, PRIV79, and RLOCK79 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC79, PRIV79, and RLOCK79 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN80" description="peripheral protection enable 80" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC80, PRIV80, and RLOCK80 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC80, PRIV80, and RLOCK80 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN81" description="peripheral protection enable 81" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC81, PRIV81, and RLOCK81 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC81, PRIV81, and RLOCK81 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN82" description="peripheral protection enable 82" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC82, PRIV82, and RLOCK82 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC82, PRIV82, and RLOCK82 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN83" description="peripheral protection enable 83" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC83, PRIV83, and RLOCK83 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC83, PRIV83, and RLOCK83 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN84" description="peripheral protection enable 84" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC84, PRIV84, and RLOCK84 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC84, PRIV84, and RLOCK84 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN85" description="peripheral protection enable 85" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC85, PRIV85, and RLOCK85 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC85, PRIV85, and RLOCK85 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN86" description="peripheral protection enable 86" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC86, PRIV86, and RLOCK86 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC86, PRIV86, and RLOCK86 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN87" description="peripheral protection enable 87" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC87, PRIV87, and RLOCK87 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC87, PRIV87, and RLOCK87 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN88" description="peripheral protection enable 88" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC88, PRIV88, and RLOCK88 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC88, PRIV88, and RLOCK88 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN89" description="peripheral protection enable 89" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC89, PRIV89, and RLOCK89 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC89, PRIV89, and RLOCK89 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN90" description="peripheral protection enable 90" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC90, PRIV90, and RLOCK90 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC90, PRIV90, and RLOCK90 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN91" description="peripheral protection enable 91" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC91, PRIV91, and RLOCK91 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC91, PRIV91, and RLOCK91 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN92" description="peripheral protection enable 92" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC92, PRIV92, and RLOCK92 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC92, PRIV92, and RLOCK92 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN93" description="peripheral protection enable 93" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC93, PRIV93, and RLOCK93 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC93, PRIV93, and RLOCK93 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN94" description="peripheral protection enable 94" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC94, PRIV94, and RLOCK94 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC94, PRIV94, and RLOCK94 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN95" description="peripheral protection enable 95" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC95, PRIV95, and RLOCK95 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC95, PRIV95, and RLOCK95 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR3" description="RIFSC peripheral protection status register 3" start="+0xFBC" size="4" reset_value="0x000005FF" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN96" description="peripheral protection enable 96" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC96, PRIV96, and RLOCK96 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC96, PRIV96, and RLOCK96 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN97" description="peripheral protection enable 97" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC97, PRIV97, and RLOCK97 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC97, PRIV97, and RLOCK97 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN98" description="peripheral protection enable 98" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC98, PRIV98, and RLOCK98 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC98, PRIV98, and RLOCK98 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN99" description="peripheral protection enable 99" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC99, PRIV99, and RLOCK99 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC99, PRIV99, and RLOCK99 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN100" description="peripheral protection enable 100" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC100, PRIV100, and RLOCK100 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC100, PRIV100, and RLOCK100 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN101" description="peripheral protection enable 101" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC101, PRIV101, and RLOCK101 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC101, PRIV101, and RLOCK101 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN102" description="peripheral protection enable 102" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC102, PRIV102, and RLOCK102 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC102, PRIV102, and RLOCK102 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN103" description="peripheral protection enable 103" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC103, PRIV103, and RLOCK103 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC103, PRIV103, and RLOCK103 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN104" description="peripheral protection enable 104" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC104, PRIV104, and RLOCK104 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC104, PRIV104, and RLOCK104 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN105" description="peripheral protection enable 105" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC105, PRIV105, and RLOCK105 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC105, PRIV105, and RLOCK105 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN106" description="peripheral protection enable 106" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC106, PRIV106, and RLOCK106 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC106, PRIV106, and RLOCK106 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN107" description="peripheral protection enable 107" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC107, PRIV107, and RLOCK107 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC107, PRIV107, and RLOCK107 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN108" description="peripheral protection enable 108" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC108, PRIV108, and RLOCK108 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC108, PRIV108, and RLOCK108 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN109" description="peripheral protection enable 109" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC109, PRIV109, and RLOCK109 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC109, PRIV109, and RLOCK109 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN110" description="peripheral protection enable 110" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC110, PRIV110, and RLOCK110 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC110, PRIV110, and RLOCK110 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN111" description="peripheral protection enable 111" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC111, PRIV111, and RLOCK111 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC111, PRIV111, and RLOCK111 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN112" description="peripheral protection enable 112" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC112, PRIV112, and RLOCK112 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC112, PRIV112, and RLOCK112 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN113" description="peripheral protection enable 113" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC113, PRIV113, and RLOCK113 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC113, PRIV113, and RLOCK113 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN114" description="peripheral protection enable 114" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC114, PRIV114, and RLOCK114 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC114, PRIV114, and RLOCK114 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN115" description="peripheral protection enable 115" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC115, PRIV115, and RLOCK115 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC115, PRIV115, and RLOCK115 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN116" description="peripheral protection enable 116" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC116, PRIV116, and RLOCK116 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC116, PRIV116, and RLOCK116 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN117" description="peripheral protection enable 117" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC117, PRIV117, and RLOCK117 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC117, PRIV117, and RLOCK117 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN118" description="peripheral protection enable 118" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC118, PRIV118, and RLOCK118 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC118, PRIV118, and RLOCK118 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN119" description="peripheral protection enable 119" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC119, PRIV119, and RLOCK119 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC119, PRIV119, and RLOCK119 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN120" description="peripheral protection enable 120" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC120, PRIV120, and RLOCK120 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC120, PRIV120, and RLOCK120 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN121" description="peripheral protection enable 121" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC121, PRIV121, and RLOCK121 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC121, PRIV121, and RLOCK121 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN122" description="peripheral protection enable 122" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC122, PRIV122, and RLOCK122 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC122, PRIV122, and RLOCK122 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN123" description="peripheral protection enable 123" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC123, PRIV123, and RLOCK123 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC123, PRIV123, and RLOCK123 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN124" description="peripheral protection enable 124" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC124, PRIV124, and RLOCK124 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC124, PRIV124, and RLOCK124 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN125" description="peripheral protection enable 125" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC125, PRIV125, and RLOCK125 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC125, PRIV125, and RLOCK125 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN126" description="peripheral protection enable 126" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC126, PRIV126, and RLOCK126 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC126, PRIV126, and RLOCK126 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN127" description="peripheral protection enable 127" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC127, PRIV127, and RLOCK127 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC127, PRIV127, and RLOCK127 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR4" description="RIFSC peripheral protection status register 4" start="+0xFC0" size="4" reset_value="0x3A0E382E" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN128" description="peripheral protection enable 128" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC128, PRIV128, and RLOCK128 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC128, PRIV128, and RLOCK128 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN129" description="peripheral protection enable 129" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC129, PRIV129, and RLOCK129 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC129, PRIV129, and RLOCK129 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN130" description="peripheral protection enable 130" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC130, PRIV130, and RLOCK130 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC130, PRIV130, and RLOCK130 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN131" description="peripheral protection enable 131" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC131, PRIV131, and RLOCK131 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC131, PRIV131, and RLOCK131 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN132" description="peripheral protection enable 132" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC132, PRIV132, and RLOCK132 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC132, PRIV132, and RLOCK132 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN133" description="peripheral protection enable 133" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC133, PRIV133, and RLOCK133 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC133, PRIV133, and RLOCK133 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN134" description="peripheral protection enable 134" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC134, PRIV134, and RLOCK134 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC134, PRIV134, and RLOCK134 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN135" description="peripheral protection enable 135" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC135, PRIV135, and RLOCK135 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC135, PRIV135, and RLOCK135 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN136" description="peripheral protection enable 136" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC136, PRIV136, and RLOCK136 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC136, PRIV136, and RLOCK136 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN137" description="peripheral protection enable 137" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC137, PRIV137, and RLOCK137 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC137, PRIV137, and RLOCK137 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN138" description="peripheral protection enable 138" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC138, PRIV138, and RLOCK138 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC138, PRIV138, and RLOCK138 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN139" description="peripheral protection enable 139" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC139, PRIV139, and RLOCK139 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC139, PRIV139, and RLOCK139 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN140" description="peripheral protection enable 140" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC140, PRIV140, and RLOCK140 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC140, PRIV140, and RLOCK140 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN141" description="peripheral protection enable 141" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC141, PRIV141, and RLOCK141 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC141, PRIV141, and RLOCK141 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN142" description="peripheral protection enable 142" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC142, PRIV142, and RLOCK142 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC142, PRIV142, and RLOCK142 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN143" description="peripheral protection enable 143" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC143, PRIV143, and RLOCK143 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC143, PRIV143, and RLOCK143 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN144" description="peripheral protection enable 144" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC144, PRIV144, and RLOCK144 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC144, PRIV144, and RLOCK144 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN145" description="peripheral protection enable 145" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC145, PRIV145, and RLOCK145 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC145, PRIV145, and RLOCK145 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN146" description="peripheral protection enable 146" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC146, PRIV146, and RLOCK146 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC146, PRIV146, and RLOCK146 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN147" description="peripheral protection enable 147" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC147, PRIV147, and RLOCK147 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC147, PRIV147, and RLOCK147 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN148" description="peripheral protection enable 148" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC148, PRIV148, and RLOCK148 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC148, PRIV148, and RLOCK148 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN149" description="peripheral protection enable 149" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC149, PRIV149, and RLOCK149 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC149, PRIV149, and RLOCK149 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN150" description="peripheral protection enable 150" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC150, PRIV150, and RLOCK150 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC150, PRIV150, and RLOCK150 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN151" description="peripheral protection enable 151" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC151, PRIV151, and RLOCK151 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC151, PRIV151, and RLOCK151 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN152" description="peripheral protection enable 152" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC152, PRIV152, and RLOCK152 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC152, PRIV152, and RLOCK152 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN153" description="peripheral protection enable 153" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC153, PRIV153, and RLOCK153 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC153, PRIV153, and RLOCK153 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN154" description="peripheral protection enable 154" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC154, PRIV154, and RLOCK154 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC154, PRIV154, and RLOCK154 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN155" description="peripheral protection enable 155" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC155, PRIV155, and RLOCK155 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC155, PRIV155, and RLOCK155 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN156" description="peripheral protection enable 156" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC156, PRIV156, and RLOCK156 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC156, PRIV156, and RLOCK156 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN157" description="peripheral protection enable 157" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC157, PRIV157, and RLOCK157 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC157, PRIV157, and RLOCK157 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN158" description="peripheral protection enable 158" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC158, PRIV158, and RLOCK158 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC158, PRIV158, and RLOCK158 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN159" description="peripheral protection enable 159" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC159, PRIV159, and RLOCK159 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC159, PRIV159, and RLOCK159 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RIFSC_PPSR5" description="RIFSC peripheral protection status register 5" start="+0xFC4" size="4" reset_value="0x3DDEEF7F" reset_mask="0xFFFFFFFF">
+      <BitField name="PPEN160" description="peripheral protection enable 160" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC160, PRIV160, and RLOCK160 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC160, PRIV160, and RLOCK160 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN161" description="peripheral protection enable 161" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC161, PRIV161, and RLOCK161 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC161, PRIV161, and RLOCK161 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN162" description="peripheral protection enable 162" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC162, PRIV162, and RLOCK162 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC162, PRIV162, and RLOCK162 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN163" description="peripheral protection enable 163" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC163, PRIV163, and RLOCK163 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC163, PRIV163, and RLOCK163 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN164" description="peripheral protection enable 164" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC164, PRIV164, and RLOCK164 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC164, PRIV164, and RLOCK164 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN165" description="peripheral protection enable 165" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC165, PRIV165, and RLOCK165 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC165, PRIV165, and RLOCK165 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN166" description="peripheral protection enable 166" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC166, PRIV166, and RLOCK166 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC166, PRIV166, and RLOCK166 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN167" description="peripheral protection enable 167" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC167, PRIV167, and RLOCK167 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC167, PRIV167, and RLOCK167 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN168" description="peripheral protection enable 168" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC168, PRIV168, and RLOCK168 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC168, PRIV168, and RLOCK168 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN169" description="peripheral protection enable 169" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC169, PRIV169, and RLOCK169 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC169, PRIV169, and RLOCK169 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN170" description="peripheral protection enable 170" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC170, PRIV170, and RLOCK170 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC170, PRIV170, and RLOCK170 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN171" description="peripheral protection enable 171" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC171, PRIV171, and RLOCK171 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC171, PRIV171, and RLOCK171 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN172" description="peripheral protection enable 172" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC172, PRIV172, and RLOCK172 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC172, PRIV172, and RLOCK172 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN173" description="peripheral protection enable 173" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC173, PRIV173, and RLOCK173 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC173, PRIV173, and RLOCK173 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN174" description="peripheral protection enable 174" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC174, PRIV174, and RLOCK174 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC174, PRIV174, and RLOCK174 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN175" description="peripheral protection enable 175" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC175, PRIV175, and RLOCK175 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC175, PRIV175, and RLOCK175 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN176" description="peripheral protection enable 176" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC176, PRIV176, and RLOCK176 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC176, PRIV176, and RLOCK176 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN177" description="peripheral protection enable 177" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC177, PRIV177, and RLOCK177 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC177, PRIV177, and RLOCK177 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN178" description="peripheral protection enable 178" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC178, PRIV178, and RLOCK178 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC178, PRIV178, and RLOCK178 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN179" description="peripheral protection enable 179" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC179, PRIV179, and RLOCK179 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC179, PRIV179, and RLOCK179 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN180" description="peripheral protection enable 180" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC180, PRIV180, and RLOCK180 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC180, PRIV180, and RLOCK180 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN181" description="peripheral protection enable 181" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC181, PRIV181, and RLOCK181 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC181, PRIV181, and RLOCK181 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN182" description="peripheral protection enable 182" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC182, PRIV182, and RLOCK182 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC182, PRIV182, and RLOCK182 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN183" description="peripheral protection enable 183" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC183, PRIV183, and RLOCK183 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC183, PRIV183, and RLOCK183 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN184" description="peripheral protection enable 184" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC184, PRIV184, and RLOCK184 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC184, PRIV184, and RLOCK184 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN185" description="peripheral protection enable 185" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC185, PRIV185, and RLOCK185 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC185, PRIV185, and RLOCK185 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN186" description="peripheral protection enable 186" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC186, PRIV186, and RLOCK186 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC186, PRIV186, and RLOCK186 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN187" description="peripheral protection enable 187" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC187, PRIV187, and RLOCK187 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC187, PRIV187, and RLOCK187 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN188" description="peripheral protection enable 188" start="28" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC188, PRIV188, and RLOCK188 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC188, PRIV188, and RLOCK188 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN189" description="peripheral protection enable 189" start="29" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC189, PRIV189, and RLOCK189 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC189, PRIV189, and RLOCK189 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN190" description="peripheral protection enable 190" start="30" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC190, PRIV190, and RLOCK190 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC190, PRIV190, and RLOCK190 register bit present." start="0x1" />
+      </BitField>
+      <BitField name="PPEN191" description="peripheral protection enable 191" start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SEC191, PRIV191, and RLOCK191 register bit not present." start="0x0" />
+        <Enum name="B_0x1" description="SEC191, PRIV191, and RLOCK191 register bit present." start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RISAF" description="Resource isolation slave unit for address space protection" start="0x44026000">
+    <Register name="RISAF_CR" description="RISAF configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RISAF registers are ignored, except RISAF_IACR, RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR (z = A to B)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_IASR" description="RISAF illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAEF" description="configuration access error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="IAEF" description="illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RISAF_IACR" description="RISAF illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAEF" description="configuration access error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="IAEF" description="illegal access error flag" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RISAF_IAESR" description="RISAF illegal access error status register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IACID" description="illegal access compartment ID" start="0" size="3" access="ReadOnly" />
+      <BitField name="IAPRIV" description="illegal access privileged" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was privileged." start="0x1" />
+      </BitField>
+      <BitField name="IASEC" description="illegal access security" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was secure." start="0x1" />
+      </BitField>
+      <BitField name="IANRW" description="illegal access read/write" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was a data read or an instruction fetch." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was a data write." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_IADDR" description="RISAF illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RISAF_REG1_CFGR" description="RISAF region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_STARTR" description="RISAF region 1 start-address register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_ENDR" description="RISAF region 1 end-address register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_CIDCFGR" description="RISAF region 1 CID configuration register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_CFGR" description="RISAF region 2 configuration register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_STARTR" description="RISAF region 2 start-address register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_ENDR" description="RISAF region 2 end-address register" start="+0x88" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_CIDCFGR" description="RISAF region 2 CID configuration register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_CFGR" description="RISAF region 3 configuration register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_STARTR" description="RISAF region 3 start-address register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_ENDR" description="RISAF region 3 end-address register" start="+0xC8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_CIDCFGR" description="RISAF region 3 CID configuration register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_CFGR" description="RISAF region 4 configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_STARTR" description="RISAF region 4 start-address register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_ENDR" description="RISAF region 4 end-address register" start="+0x108" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_CIDCFGR" description="RISAF region 4 CID configuration register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_CFGR" description="RISAF region 5 configuration register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_STARTR" description="RISAF region 5 start-address register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_ENDR" description="RISAF region 5 end-address register" start="+0x148" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_CIDCFGR" description="RISAF region 5 CID configuration register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_CFGR" description="RISAF region 6 configuration register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_STARTR" description="RISAF region 6 start-address register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_ENDR" description="RISAF region 6 end-address register" start="+0x188" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_CIDCFGR" description="RISAF region 6 CID configuration register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_CFGR" description="RISAF region 7 configuration register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_STARTR" description="RISAF region 7 start-address register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_ENDR" description="RISAF region 7 end-address register" start="+0x1C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_CIDCFGR" description="RISAF region 7 CID configuration register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_CFGR" description="RISAF region 8 configuration register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_STARTR" description="RISAF region 8 start-address register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_ENDR" description="RISAF region 8 end-address register" start="+0x208" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_CIDCFGR" description="RISAF region 8 CID configuration register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_CFGR" description="RISAF region 9 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_STARTR" description="RISAF region 9 start-address register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_ENDR" description="RISAF region 9 end-address register" start="+0x248" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_CIDCFGR" description="RISAF region 9 CID configuration register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_CFGR" description="RISAF region 10 configuration register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_STARTR" description="RISAF region 10 start-address register" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_ENDR" description="RISAF region 10 end-address register" start="+0x288" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_CIDCFGR" description="RISAF region 10 CID configuration register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_CFGR" description="RISAF region 11 configuration register" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_STARTR" description="RISAF region 11 start-address register" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_ENDR" description="RISAF region 11 end-address register" start="+0x2C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_CIDCFGR" description="RISAF region 11 CID configuration register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_CFGR" description="RISAF region 12 configuration register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_STARTR" description="RISAF region 12 start-address register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_ENDR" description="RISAF region 12 end-address register" start="+0x308" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_CIDCFGR" description="RISAF region 12 CID configuration register" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_CFGR" description="RISAF region 13 configuration register" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_STARTR" description="RISAF region 13 start-address register" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_ENDR" description="RISAF region 13 end-address register" start="+0x348" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_CIDCFGR" description="RISAF region 13 CID configuration register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_CFGR" description="RISAF region 14 configuration register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_STARTR" description="RISAF region 14 start-address register" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_ENDR" description="RISAF region 14 end-address register" start="+0x388" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_CIDCFGR" description="RISAF region 14 CID configuration register" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_CFGR" description="RISAF region 15 configuration register" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_STARTR" description="RISAF region 15 start-address register" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_ENDR" description="RISAF region 15 end-address register" start="+0x3C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_CIDCFGR" description="RISAF region 15 CID configuration register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_ACFGR" description="RISAF region 1 subregion A configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_ASTARTR" description="RISAF region 1 subregion A start-address register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_AENDR" description="RISAF region 1 subregion A end-address register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_ANESTR" description="RISAF region 1 subregion A nested mode register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_ACFGR" description="RISAF region 2 subregion A configuration register" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_ASTARTR" description="RISAF region 2 subregion A start-address register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_AENDR" description="RISAF region 2 subregion A end-address register" start="+0x98" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_ANESTR" description="RISAF region 2 subregion A nested mode register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_ACFGR" description="RISAF region 3 subregion A configuration register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_ASTARTR" description="RISAF region 3 subregion A start-address register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_AENDR" description="RISAF region 3 subregion A end-address register" start="+0xD8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_ANESTR" description="RISAF region 3 subregion A nested mode register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_ACFGR" description="RISAF region 4 subregion A configuration register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_ASTARTR" description="RISAF region 4 subregion A start-address register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_AENDR" description="RISAF region 4 subregion A end-address register" start="+0x118" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_ANESTR" description="RISAF region 4 subregion A nested mode register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_ACFGR" description="RISAF region 5 subregion A configuration register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_ASTARTR" description="RISAF region 5 subregion A start-address register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_AENDR" description="RISAF region 5 subregion A end-address register" start="+0x158" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_ANESTR" description="RISAF region 5 subregion A nested mode register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_ACFGR" description="RISAF region 6 subregion A configuration register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_ASTARTR" description="RISAF region 6 subregion A start-address register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_AENDR" description="RISAF region 6 subregion A end-address register" start="+0x198" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_ANESTR" description="RISAF region 6 subregion A nested mode register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_ACFGR" description="RISAF region 7 subregion A configuration register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_ASTARTR" description="RISAF region 7 subregion A start-address register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_AENDR" description="RISAF region 7 subregion A end-address register" start="+0x1D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_ANESTR" description="RISAF region 7 subregion A nested mode register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_ACFGR" description="RISAF region 8 subregion A configuration register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_ASTARTR" description="RISAF region 8 subregion A start-address register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_AENDR" description="RISAF region 8 subregion A end-address register" start="+0x218" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_ANESTR" description="RISAF region 8 subregion A nested mode register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_ACFGR" description="RISAF region 9 subregion A configuration register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_ASTARTR" description="RISAF region 9 subregion A start-address register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_AENDR" description="RISAF region 9 subregion A end-address register" start="+0x258" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_ANESTR" description="RISAF region 9 subregion A nested mode register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_ACFGR" description="RISAF region 10 subregion A configuration register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_ASTARTR" description="RISAF region 10 subregion A start-address register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_AENDR" description="RISAF region 10 subregion A end-address register" start="+0x298" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_ANESTR" description="RISAF region 10 subregion A nested mode register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_ACFGR" description="RISAF region 11 subregion A configuration register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_ASTARTR" description="RISAF region 11 subregion A start-address register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_AENDR" description="RISAF region 11 subregion A end-address register" start="+0x2D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_ANESTR" description="RISAF region 11 subregion A nested mode register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_ACFGR" description="RISAF region 12 subregion A configuration register" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_ASTARTR" description="RISAF region 12 subregion A start-address register" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_AENDR" description="RISAF region 12 subregion A end-address register" start="+0x318" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_ANESTR" description="RISAF region 12 subregion A nested mode register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_ACFGR" description="RISAF region 13 subregion A configuration register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_ASTARTR" description="RISAF region 13 subregion A start-address register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_AENDR" description="RISAF region 13 subregion A end-address register" start="+0x358" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_ANESTR" description="RISAF region 13 subregion A nested mode register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_ACFGR" description="RISAF region 14 subregion A configuration register" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_ASTARTR" description="RISAF region 14 subregion A start-address register" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_AENDR" description="RISAF region 14 subregion A end-address register" start="+0x398" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_ANESTR" description="RISAF region 14 subregion A nested mode register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_ACFGR" description="RISAF region 15 subregion A configuration register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_ASTARTR" description="RISAF region 15 subregion A start-address register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_AENDR" description="RISAF region 15 subregion A end-address register" start="+0x3D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_ANESTR" description="RISAF region 15 subregion A nested mode register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_BCFGR" description="RISAF region 1 subregion B configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_BSTARTR" description="RISAF region 1 subregion B start-address register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_BENDR" description="RISAF region 1 subregion B end-address register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_BNESTR" description="RISAF region 1 subregion B nested mode register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_BCFGR" description="RISAF region 2 subregion B configuration register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_BSTARTR" description="RISAF region 2 subregion B start-address register" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_BENDR" description="RISAF region 2 subregion B end-address register" start="+0xA8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_BNESTR" description="RISAF region 2 subregion B nested mode register" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_BCFGR" description="RISAF region 3 subregion B configuration register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_BSTARTR" description="RISAF region 3 subregion B start-address register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_BENDR" description="RISAF region 3 subregion B end-address register" start="+0xE8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_BNESTR" description="RISAF region 3 subregion B nested mode register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_BCFGR" description="RISAF region 4 subregion B configuration register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_BSTARTR" description="RISAF region 4 subregion B start-address register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_BENDR" description="RISAF region 4 subregion B end-address register" start="+0x128" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_BNESTR" description="RISAF region 4 subregion B nested mode register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_BCFGR" description="RISAF region 5 subregion B configuration register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_BSTARTR" description="RISAF region 5 subregion B start-address register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_BENDR" description="RISAF region 5 subregion B end-address register" start="+0x168" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_BNESTR" description="RISAF region 5 subregion B nested mode register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_BCFGR" description="RISAF region 6 subregion B configuration register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_BSTARTR" description="RISAF region 6 subregion B start-address register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_BENDR" description="RISAF region 6 subregion B end-address register" start="+0x1A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_BNESTR" description="RISAF region 6 subregion B nested mode register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_BCFGR" description="RISAF region 7 subregion B configuration register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_BSTARTR" description="RISAF region 7 subregion B start-address register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_BENDR" description="RISAF region 7 subregion B end-address register" start="+0x1E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_BNESTR" description="RISAF region 7 subregion B nested mode register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_BCFGR" description="RISAF region 8 subregion B configuration register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_BSTARTR" description="RISAF region 8 subregion B start-address register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_BENDR" description="RISAF region 8 subregion B end-address register" start="+0x228" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_BNESTR" description="RISAF region 8 subregion B nested mode register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_BCFGR" description="RISAF region 9 subregion B configuration register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_BSTARTR" description="RISAF region 9 subregion B start-address register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_BENDR" description="RISAF region 9 subregion B end-address register" start="+0x268" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_BNESTR" description="RISAF region 9 subregion B nested mode register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_BCFGR" description="RISAF region 10 subregion B configuration register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_BSTARTR" description="RISAF region 10 subregion B start-address register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_BENDR" description="RISAF region 10 subregion B end-address register" start="+0x2A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_BNESTR" description="RISAF region 10 subregion B nested mode register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_BCFGR" description="RISAF region 11 subregion B configuration register" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_BSTARTR" description="RISAF region 11 subregion B start-address register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_BENDR" description="RISAF region 11 subregion B end-address register" start="+0x2E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_BNESTR" description="RISAF region 11 subregion B nested mode register" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_BCFGR" description="RISAF region 12 subregion B configuration register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_BSTARTR" description="RISAF region 12 subregion B start-address register" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_BENDR" description="RISAF region 12 subregion B end-address register" start="+0x328" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_BNESTR" description="RISAF region 12 subregion B nested mode register" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_BCFGR" description="RISAF region 13 subregion B configuration register" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_BSTARTR" description="RISAF region 13 subregion B start-address register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_BENDR" description="RISAF region 13 subregion B end-address register" start="+0x368" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_BNESTR" description="RISAF region 13 subregion B nested mode register" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_BCFGR" description="RISAF region 14 subregion B configuration register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_BSTARTR" description="RISAF region 14 subregion B start-address register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_BENDR" description="RISAF region 14 subregion B end-address register" start="+0x3A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_BNESTR" description="RISAF region 14 subregion B nested mode register" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_BCFGR" description="RISAF region 15 subregion B configuration register" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_BSTARTR" description="RISAF region 15 subregion B start-address register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_BENDR" description="RISAF region 15 subregion B end-address register" start="+0x3E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_BNESTR" description="RISAF region 15 subregion B nested mode register" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RISAF_S" description="Resource isolation slave unit for address space protection" start="0x54026000">
+    <Register name="RISAF_CR" description="RISAF configuration register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GLOCK" description="global lock" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF registers are writable." start="0x0" />
+        <Enum name="B_0x1" description="All writes to RISAF registers are ignored, except RISAF_IACR, RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR (z = A to B)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_IASR" description="RISAF illegal access status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAEF" description="configuration access error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="IAEF" description="illegal access error flag" start="1" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RISAF_IACR" description="RISAF illegal access clear register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAEF" description="configuration access error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="IAEF" description="illegal access error flag" start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RISAF_IAESR" description="RISAF illegal access error status register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IACID" description="illegal access compartment ID" start="0" size="3" access="ReadOnly" />
+      <BitField name="IAPRIV" description="illegal access privileged" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was unprivileged." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was privileged." start="0x1" />
+      </BitField>
+      <BitField name="IASEC" description="illegal access security" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was secure." start="0x1" />
+      </BitField>
+      <BitField name="IANRW" description="illegal access read/write" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Illegal access was a data read or an instruction fetch." start="0x0" />
+        <Enum name="B_0x1" description="Illegal access was a data write." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_IADDR" description="RISAF illegal address register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IADD" description="illegal address" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RISAF_REG1_CFGR" description="RISAF region 1 configuration register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_STARTR" description="RISAF region 1 start-address register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_ENDR" description="RISAF region 1 end-address register" start="+0x48" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_CIDCFGR" description="RISAF region 1 CID configuration register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_CFGR" description="RISAF region 2 configuration register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_STARTR" description="RISAF region 2 start-address register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_ENDR" description="RISAF region 2 end-address register" start="+0x88" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_CIDCFGR" description="RISAF region 2 CID configuration register" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_CFGR" description="RISAF region 3 configuration register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_STARTR" description="RISAF region 3 start-address register" start="+0xC4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_ENDR" description="RISAF region 3 end-address register" start="+0xC8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_CIDCFGR" description="RISAF region 3 CID configuration register" start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_CFGR" description="RISAF region 4 configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_STARTR" description="RISAF region 4 start-address register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_ENDR" description="RISAF region 4 end-address register" start="+0x108" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_CIDCFGR" description="RISAF region 4 CID configuration register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_CFGR" description="RISAF region 5 configuration register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_STARTR" description="RISAF region 5 start-address register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_ENDR" description="RISAF region 5 end-address register" start="+0x148" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_CIDCFGR" description="RISAF region 5 CID configuration register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_CFGR" description="RISAF region 6 configuration register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_STARTR" description="RISAF region 6 start-address register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_ENDR" description="RISAF region 6 end-address register" start="+0x188" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_CIDCFGR" description="RISAF region 6 CID configuration register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_CFGR" description="RISAF region 7 configuration register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_STARTR" description="RISAF region 7 start-address register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_ENDR" description="RISAF region 7 end-address register" start="+0x1C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_CIDCFGR" description="RISAF region 7 CID configuration register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_CFGR" description="RISAF region 8 configuration register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_STARTR" description="RISAF region 8 start-address register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_ENDR" description="RISAF region 8 end-address register" start="+0x208" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_CIDCFGR" description="RISAF region 8 CID configuration register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_CFGR" description="RISAF region 9 configuration register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_STARTR" description="RISAF region 9 start-address register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_ENDR" description="RISAF region 9 end-address register" start="+0x248" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_CIDCFGR" description="RISAF region 9 CID configuration register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_CFGR" description="RISAF region 10 configuration register" start="+0x280" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_STARTR" description="RISAF region 10 start-address register" start="+0x284" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_ENDR" description="RISAF region 10 end-address register" start="+0x288" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_CIDCFGR" description="RISAF region 10 CID configuration register" start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_CFGR" description="RISAF region 11 configuration register" start="+0x2C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_STARTR" description="RISAF region 11 start-address register" start="+0x2C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_ENDR" description="RISAF region 11 end-address register" start="+0x2C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_CIDCFGR" description="RISAF region 11 CID configuration register" start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_CFGR" description="RISAF region 12 configuration register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_STARTR" description="RISAF region 12 start-address register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_ENDR" description="RISAF region 12 end-address register" start="+0x308" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_CIDCFGR" description="RISAF region 12 CID configuration register" start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_CFGR" description="RISAF region 13 configuration register" start="+0x340" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_STARTR" description="RISAF region 13 start-address register" start="+0x344" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_ENDR" description="RISAF region 13 end-address register" start="+0x348" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_CIDCFGR" description="RISAF region 13 CID configuration register" start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_CFGR" description="RISAF region 14 configuration register" start="+0x380" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_STARTR" description="RISAF region 14 start-address register" start="+0x384" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_ENDR" description="RISAF region 14 end-address register" start="+0x388" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_CIDCFGR" description="RISAF region 14 CID configuration register" start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_CFGR" description="RISAF region 15 configuration register" start="+0x3C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="base region enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Base region x is disabled. Access control of primary region 0 (secure, privileged) applies to any access between region x start and end addresses. Associated subregions are also disabled." start="0x0" />
+        <Enum name="B_0x1" description="Base region x is enabled. Access controls defined in region x apply to any access between region x start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="secure region" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access region x. SEC value in RISAF_REGx_zCFGR is internally treated as zeroed by RISAF (only non-secure requests to subregions)." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access region x, and optional subregions can be defined as secure or non-secure." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC0" description="privileged access for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC1" description="privileged access for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC2" description="privileged access for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC3" description="privileged access for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC4" description="privileged access for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC5" description="privileged access for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC6" description="privileged access for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+      <BitField name="PRIVC7" description="privileged access for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y can access to region x in privileged and unprivileged mode." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can access to region x in privileged mode only." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_STARTR" description="RISAF region 15 start-address register" start="+0x3C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDSTART" description="Base region address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_ENDR" description="RISAF region 15 end-address register" start="+0x3C8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="BADDEND" description="Base region address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_CIDCFGR" description="RISAF region 15 CID configuration register" start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDENC0" description="read enable for compartment y" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC1" description="read enable for compartment y" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC2" description="read enable for compartment y" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC3" description="read enable for compartment y" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC4" description="read enable for compartment y" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC5" description="read enable for compartment y" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC6" description="read enable for compartment y" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="RDENC7" description="read enable for compartment y" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot read region x (read as zero)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can read region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC0" description="write enable for compartment y" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC1" description="write enable for compartment y" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC2" description="write enable for compartment y" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC3" description="write enable for compartment y" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC4" description="write enable for compartment y" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC5" description="write enable for compartment y" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC6" description="write enable for compartment y" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+      <BitField name="WRENC7" description="write enable for compartment y" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Application running in compartment y cannot write to region x (write ignored)." start="0x0" />
+        <Enum name="B_0x1" description="Application running in compartment y can write to region x. Additional control defined by SEC and PRIVCy in RISAF_REGx_CFGR, also apply." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_ACFGR" description="RISAF region 1 subregion A configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_ASTARTR" description="RISAF region 1 subregion A start-address register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_AENDR" description="RISAF region 1 subregion A end-address register" start="+0x58" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_ANESTR" description="RISAF region 1 subregion A nested mode register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_ACFGR" description="RISAF region 2 subregion A configuration register" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_ASTARTR" description="RISAF region 2 subregion A start-address register" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_AENDR" description="RISAF region 2 subregion A end-address register" start="+0x98" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_ANESTR" description="RISAF region 2 subregion A nested mode register" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_ACFGR" description="RISAF region 3 subregion A configuration register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_ASTARTR" description="RISAF region 3 subregion A start-address register" start="+0xD4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_AENDR" description="RISAF region 3 subregion A end-address register" start="+0xD8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_ANESTR" description="RISAF region 3 subregion A nested mode register" start="+0xDC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_ACFGR" description="RISAF region 4 subregion A configuration register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_ASTARTR" description="RISAF region 4 subregion A start-address register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_AENDR" description="RISAF region 4 subregion A end-address register" start="+0x118" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_ANESTR" description="RISAF region 4 subregion A nested mode register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_ACFGR" description="RISAF region 5 subregion A configuration register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_ASTARTR" description="RISAF region 5 subregion A start-address register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_AENDR" description="RISAF region 5 subregion A end-address register" start="+0x158" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_ANESTR" description="RISAF region 5 subregion A nested mode register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_ACFGR" description="RISAF region 6 subregion A configuration register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_ASTARTR" description="RISAF region 6 subregion A start-address register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_AENDR" description="RISAF region 6 subregion A end-address register" start="+0x198" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_ANESTR" description="RISAF region 6 subregion A nested mode register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_ACFGR" description="RISAF region 7 subregion A configuration register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_ASTARTR" description="RISAF region 7 subregion A start-address register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_AENDR" description="RISAF region 7 subregion A end-address register" start="+0x1D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_ANESTR" description="RISAF region 7 subregion A nested mode register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_ACFGR" description="RISAF region 8 subregion A configuration register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_ASTARTR" description="RISAF region 8 subregion A start-address register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_AENDR" description="RISAF region 8 subregion A end-address register" start="+0x218" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_ANESTR" description="RISAF region 8 subregion A nested mode register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_ACFGR" description="RISAF region 9 subregion A configuration register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_ASTARTR" description="RISAF region 9 subregion A start-address register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_AENDR" description="RISAF region 9 subregion A end-address register" start="+0x258" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_ANESTR" description="RISAF region 9 subregion A nested mode register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_ACFGR" description="RISAF region 10 subregion A configuration register" start="+0x290" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_ASTARTR" description="RISAF region 10 subregion A start-address register" start="+0x294" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_AENDR" description="RISAF region 10 subregion A end-address register" start="+0x298" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_ANESTR" description="RISAF region 10 subregion A nested mode register" start="+0x29C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_ACFGR" description="RISAF region 11 subregion A configuration register" start="+0x2D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_ASTARTR" description="RISAF region 11 subregion A start-address register" start="+0x2D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_AENDR" description="RISAF region 11 subregion A end-address register" start="+0x2D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_ANESTR" description="RISAF region 11 subregion A nested mode register" start="+0x2DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_ACFGR" description="RISAF region 12 subregion A configuration register" start="+0x310" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_ASTARTR" description="RISAF region 12 subregion A start-address register" start="+0x314" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_AENDR" description="RISAF region 12 subregion A end-address register" start="+0x318" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_ANESTR" description="RISAF region 12 subregion A nested mode register" start="+0x31C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_ACFGR" description="RISAF region 13 subregion A configuration register" start="+0x350" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_ASTARTR" description="RISAF region 13 subregion A start-address register" start="+0x354" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_AENDR" description="RISAF region 13 subregion A end-address register" start="+0x358" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_ANESTR" description="RISAF region 13 subregion A nested mode register" start="+0x35C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_ACFGR" description="RISAF region 14 subregion A configuration register" start="+0x390" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_ASTARTR" description="RISAF region 14 subregion A start-address register" start="+0x394" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_AENDR" description="RISAF region 14 subregion A end-address register" start="+0x398" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_ANESTR" description="RISAF region 14 subregion A nested mode register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_ACFGR" description="RISAF region 15 subregion A configuration register" start="+0x3D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_ASTARTR" description="RISAF region 15 subregion A start-address register" start="+0x3D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_AENDR" description="RISAF region 15 subregion A end-address register" start="+0x3D8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_ANESTR" description="RISAF region 15 subregion A nested mode register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_BCFGR" description="RISAF region 1 subregion B configuration register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG1_BSTARTR" description="RISAF region 1 subregion B start-address register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_BENDR" description="RISAF region 1 subregion B end-address register" start="+0x68" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG1_BNESTR" description="RISAF region 1 subregion B nested mode register" start="+0x6C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_BCFGR" description="RISAF region 2 subregion B configuration register" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG2_BSTARTR" description="RISAF region 2 subregion B start-address register" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_BENDR" description="RISAF region 2 subregion B end-address register" start="+0xA8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG2_BNESTR" description="RISAF region 2 subregion B nested mode register" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_BCFGR" description="RISAF region 3 subregion B configuration register" start="+0xE0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG3_BSTARTR" description="RISAF region 3 subregion B start-address register" start="+0xE4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_BENDR" description="RISAF region 3 subregion B end-address register" start="+0xE8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG3_BNESTR" description="RISAF region 3 subregion B nested mode register" start="+0xEC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_BCFGR" description="RISAF region 4 subregion B configuration register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG4_BSTARTR" description="RISAF region 4 subregion B start-address register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_BENDR" description="RISAF region 4 subregion B end-address register" start="+0x128" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG4_BNESTR" description="RISAF region 4 subregion B nested mode register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_BCFGR" description="RISAF region 5 subregion B configuration register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG5_BSTARTR" description="RISAF region 5 subregion B start-address register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_BENDR" description="RISAF region 5 subregion B end-address register" start="+0x168" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG5_BNESTR" description="RISAF region 5 subregion B nested mode register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_BCFGR" description="RISAF region 6 subregion B configuration register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG6_BSTARTR" description="RISAF region 6 subregion B start-address register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_BENDR" description="RISAF region 6 subregion B end-address register" start="+0x1A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG6_BNESTR" description="RISAF region 6 subregion B nested mode register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_BCFGR" description="RISAF region 7 subregion B configuration register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG7_BSTARTR" description="RISAF region 7 subregion B start-address register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_BENDR" description="RISAF region 7 subregion B end-address register" start="+0x1E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG7_BNESTR" description="RISAF region 7 subregion B nested mode register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_BCFGR" description="RISAF region 8 subregion B configuration register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG8_BSTARTR" description="RISAF region 8 subregion B start-address register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_BENDR" description="RISAF region 8 subregion B end-address register" start="+0x228" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG8_BNESTR" description="RISAF region 8 subregion B nested mode register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_BCFGR" description="RISAF region 9 subregion B configuration register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG9_BSTARTR" description="RISAF region 9 subregion B start-address register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_BENDR" description="RISAF region 9 subregion B end-address register" start="+0x268" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG9_BNESTR" description="RISAF region 9 subregion B nested mode register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_BCFGR" description="RISAF region 10 subregion B configuration register" start="+0x2A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG10_BSTARTR" description="RISAF region 10 subregion B start-address register" start="+0x2A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_BENDR" description="RISAF region 10 subregion B end-address register" start="+0x2A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG10_BNESTR" description="RISAF region 10 subregion B nested mode register" start="+0x2AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_BCFGR" description="RISAF region 11 subregion B configuration register" start="+0x2E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG11_BSTARTR" description="RISAF region 11 subregion B start-address register" start="+0x2E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_BENDR" description="RISAF region 11 subregion B end-address register" start="+0x2E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG11_BNESTR" description="RISAF region 11 subregion B nested mode register" start="+0x2EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_BCFGR" description="RISAF region 12 subregion B configuration register" start="+0x320" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG12_BSTARTR" description="RISAF region 12 subregion B start-address register" start="+0x324" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_BENDR" description="RISAF region 12 subregion B end-address register" start="+0x328" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG12_BNESTR" description="RISAF region 12 subregion B nested mode register" start="+0x32C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_BCFGR" description="RISAF region 13 subregion B configuration register" start="+0x360" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG13_BSTARTR" description="RISAF region 13 subregion B start-address register" start="+0x364" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_BENDR" description="RISAF region 13 subregion B end-address register" start="+0x368" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG13_BNESTR" description="RISAF region 13 subregion B nested mode register" start="+0x36C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_BCFGR" description="RISAF region 14 subregion B configuration register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG14_BSTARTR" description="RISAF region 14 subregion B start-address register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_BENDR" description="RISAF region 14 subregion B end-address register" start="+0x3A8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG14_BNESTR" description="RISAF region 14 subregion B nested mode register" start="+0x3AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_BCFGR" description="RISAF region 15 subregion B configuration register" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SREN" description="subregion enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Subregion z is disabled. Access control of base region x applies to any access between this subregion start and end addresses." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x is enable. Access control defined in subregion z applies to any access between subregion z start and end addresses." start="0x1" />
+      </BitField>
+      <BitField name="RLOCK" description="resource lock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are writable." start="0x0" />
+        <Enum name="B_0x1" description="Writes to RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR are ignored." start="0x1" />
+      </BitField>
+      <BitField name="SRCID" description="subregion CID" start="4" size="3" access="Read/Write" />
+      <BitField name="SEC" description="secure subregion" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only non-secure requests can access subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only secure requests can access subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="privileged subregion" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Privileged and unprivileged accesses are granted in subregion z of region x." start="0x0" />
+        <Enum name="B_0x1" description="Only privileged accesses are granted in subregion z of region x." start="0x1" />
+      </BitField>
+      <BitField name="RDEN" description="read enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any read to subregion z of region x returns zero." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be read." start="0x1" />
+      </BitField>
+      <BitField name="WREN" description="write enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any writes to subregion z of region x are ignored." start="0x0" />
+        <Enum name="B_0x1" description="Subregion z of region x can be written to." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RISAF_REG15_BSTARTR" description="RISAF region 15 subregion B start-address register" start="+0x3E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDSTART" description="subregion address start" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_BENDR" description="RISAF region 15 subregion B end-address register" start="+0x3E8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="SADDEND" description="subregion address end" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RISAF_REG15_BNESTR" description="RISAF region 15 subregion B nested mode register" start="+0x3EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCEN" description="delegated configuration enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RIF configuration for subregion z can be written only by the secure privileged software." start="0x0" />
+        <Enum name="B_0x1" description="RIF configuration for subregion z can be written only " start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RNG" description="True random number generator" start="0x44020000">
+    <Register name="RNG_CR" description="RNG control register" start="+0x000" size="4" reset_value="0x00800D00" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGEN" description="True random number generator enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated." start="0x0" />
+        <Enum name="B_0x1" description="True random number generator is enabled." start="0x1" />
+      </BitField>
+      <BitField name="IE" description="Interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RNG interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or CEIS = 1 in the RNG_SR register." start="0x1" />
+      </BitField>
+      <BitField name="CED" description="Clock error detection " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock error detection enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock error detection is disabled" start="0x1" />
+      </BitField>
+      <BitField name="ARDIS" description="Auto reset disable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When a noise source error occurs RNG performs an automatic reset to clear the SECS bit." start="0x0" />
+        <Enum name="B_0x1" description="When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation." start="0x1" />
+      </BitField>
+      <BitField name="RNG_CONFIG3" description="RNG configuration 3" start="8" size="4" access="Read/Write" />
+      <BitField name="NISTC" description="NIST custom" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware default values for NIST compliant RNG. In this configuration per 128-bit output" start="0x0" />
+        <Enum name="B_0x1" description="Custom values for NIST compliant RNG. See Section 47.6: RNG entropy source validation for proposed configuration." start="0x1" />
+      </BitField>
+      <BitField name="RNG_CONFIG2" description="RNG configuration 2" start="13" size="3" access="Read/Write" />
+      <BitField name="CLKDIV" description="Clock divider factor" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="internal RNG clock after divider is similar to incoming RNG clock." start="0x0" />
+        <Enum name="B_0x1" description="two RNG clock cycles per internal RNG clock." start="0x1" />
+        <Enum name="B_0x2" description="2less thansup&gt;2less than/sup&gt; (= 4) RNG clock cycles per internal RNG clock." start="0x2" />
+        <Enum name="B_0xF" description="2less thansup&gt;15less than/sup&gt; RNG clock cycles per internal clock (for example. an incoming 48 MHz RNG clock becomes a 1.5 kHz internal RNG clock)" start="0xF" />
+      </BitField>
+      <BitField name="RNG_CONFIG1" description="RNG configuration 1" start="20" size="6" access="Read/Write" />
+      <BitField name="CONDRST" description="Conditioning soft reset" start="30" size="1" access="Read/Write" />
+      <BitField name="CONFIGLOCK" description="RNG Config lock" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are allowed." start="0x0" />
+        <Enum name="B_0x1" description="Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RNG_SR" description="RNG status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DRDY" description="Data ready" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The RNG_DR register is not yet valid, no random data is available." start="0x0" />
+        <Enum name="B_0x1" description="The RNG_DR register contains valid random data." start="0x1" />
+      </BitField>
+      <BitField name="CECS" description="Clock error current status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The RNG clock is correct (fless thansub&gt;RNGCLKless than/sub&gt;&gt; fless thansub&gt;HCLKless than/sub&gt;/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered." start="0x0" />
+        <Enum name="B_0x1" description="The RNG clock is too slow (fless thansub&gt;RNGCLKless than/sub&gt;less than fless thansub&gt;HCLKless than/sub&gt;/32)." start="0x1" />
+      </BitField>
+      <BitField name="SECS" description="Seed error current status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered." start="0x0" />
+        <Enum name="B_0x1" description="At least one of the following faulty sequences has been detected:" start="0x1" />
+      </BitField>
+      <BitField name="CEIS" description="Clock error interrupt status" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The RNG clock is correct (fless thansub&gt;RNGCLKless than/sub&gt;&gt; fless thansub&gt;HCLKless than/sub&gt;/32)" start="0x0" />
+        <Enum name="B_0x1" description="The RNG clock before the internal divider is detected too slow (fless thansub&gt;RNGCLKless than/sub&gt;less than fless thansub&gt;HCLKless than/sub&gt;/32)" start="0x1" />
+      </BitField>
+      <BitField name="SEIS" description="Seed error interrupt status" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No faulty sequence detected" start="0x0" />
+        <Enum name="B_0x1" description="At least one faulty sequence is detected. See SECS bit description for details." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RNG_DR" description="RNG data register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNDATA" description="Random data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RNG_NSCR" description="RNG noise source control register" start="+0x00C" size="4" reset_value="0x0003FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_OSC1" description="Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="0" size="3" access="Read/Write" />
+      <BitField name="EN_OSC2" description="Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="3" size="3" access="Read/Write" />
+      <BitField name="EN_OSC3" description="Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="6" size="3" access="Read/Write" />
+      <BitField name="EN_OSC4" description="Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="9" size="3" access="Read/Write" />
+      <BitField name="EN_OSC5" description="Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="12" size="3" access="Read/Write" />
+      <BitField name="EN_OSC6" description="Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="15" size="3" access="Read/Write" />
+    </Register>
+    <Register name="RNG_HTCR" description="RNG health test control register" start="+0x010" size="4" reset_value="0x000072AC" reset_mask="0xFFFFFFFF">
+      <BitField name="HTCFG" description="health test configuration" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RNG_S" description="True random number generator" start="0x54020000">
+    <Register name="RNG_CR" description="RNG control register" start="+0x000" size="4" reset_value="0x00800D00" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGEN" description="True random number generator enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated." start="0x0" />
+        <Enum name="B_0x1" description="True random number generator is enabled." start="0x1" />
+      </BitField>
+      <BitField name="IE" description="Interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RNG interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="RNG interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or CEIS = 1 in the RNG_SR register." start="0x1" />
+      </BitField>
+      <BitField name="CED" description="Clock error detection " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clock error detection enabled" start="0x0" />
+        <Enum name="B_0x1" description="Clock error detection is disabled" start="0x1" />
+      </BitField>
+      <BitField name="ARDIS" description="Auto reset disable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When a noise source error occurs RNG performs an automatic reset to clear the SECS bit." start="0x0" />
+        <Enum name="B_0x1" description="When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation." start="0x1" />
+      </BitField>
+      <BitField name="RNG_CONFIG3" description="RNG configuration 3" start="8" size="4" access="Read/Write" />
+      <BitField name="NISTC" description="NIST custom" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware default values for NIST compliant RNG. In this configuration per 128-bit output" start="0x0" />
+        <Enum name="B_0x1" description="Custom values for NIST compliant RNG. See Section 47.6: RNG entropy source validation for proposed configuration." start="0x1" />
+      </BitField>
+      <BitField name="RNG_CONFIG2" description="RNG configuration 2" start="13" size="3" access="Read/Write" />
+      <BitField name="CLKDIV" description="Clock divider factor" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="internal RNG clock after divider is similar to incoming RNG clock." start="0x0" />
+        <Enum name="B_0x1" description="two RNG clock cycles per internal RNG clock." start="0x1" />
+        <Enum name="B_0x2" description="2less thansup&gt;2less than/sup&gt; (= 4) RNG clock cycles per internal RNG clock." start="0x2" />
+        <Enum name="B_0xF" description="2less thansup&gt;15less than/sup&gt; RNG clock cycles per internal clock (for example. an incoming 48 MHz RNG clock becomes a 1.5 kHz internal RNG clock)" start="0xF" />
+      </BitField>
+      <BitField name="RNG_CONFIG1" description="RNG configuration 1" start="20" size="6" access="Read/Write" />
+      <BitField name="CONDRST" description="Conditioning soft reset" start="30" size="1" access="Read/Write" />
+      <BitField name="CONFIGLOCK" description="RNG Config lock" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are allowed." start="0x0" />
+        <Enum name="B_0x1" description="Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RNG_SR" description="RNG status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DRDY" description="Data ready" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The RNG_DR register is not yet valid, no random data is available." start="0x0" />
+        <Enum name="B_0x1" description="The RNG_DR register contains valid random data." start="0x1" />
+      </BitField>
+      <BitField name="CECS" description="Clock error current status" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="The RNG clock is correct (fless thansub&gt;RNGCLKless than/sub&gt;&gt; fless thansub&gt;HCLKless than/sub&gt;/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered." start="0x0" />
+        <Enum name="B_0x1" description="The RNG clock is too slow (fless thansub&gt;RNGCLKless than/sub&gt;less than fless thansub&gt;HCLKless than/sub&gt;/32)." start="0x1" />
+      </BitField>
+      <BitField name="SECS" description="Seed error current status" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered." start="0x0" />
+        <Enum name="B_0x1" description="At least one of the following faulty sequences has been detected:" start="0x1" />
+      </BitField>
+      <BitField name="CEIS" description="Clock error interrupt status" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The RNG clock is correct (fless thansub&gt;RNGCLKless than/sub&gt;&gt; fless thansub&gt;HCLKless than/sub&gt;/32)" start="0x0" />
+        <Enum name="B_0x1" description="The RNG clock before the internal divider is detected too slow (fless thansub&gt;RNGCLKless than/sub&gt;less than fless thansub&gt;HCLKless than/sub&gt;/32)" start="0x1" />
+      </BitField>
+      <BitField name="SEIS" description="Seed error interrupt status" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No faulty sequence detected" start="0x0" />
+        <Enum name="B_0x1" description="At least one faulty sequence is detected. See SECS bit description for details." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RNG_DR" description="RNG data register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNDATA" description="Random data" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RNG_NSCR" description="RNG noise source control register" start="+0x00C" size="4" reset_value="0x0003FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="EN_OSC1" description="Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="0" size="3" access="Read/Write" />
+      <BitField name="EN_OSC2" description="Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="3" size="3" access="Read/Write" />
+      <BitField name="EN_OSC3" description="Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="6" size="3" access="Read/Write" />
+      <BitField name="EN_OSC4" description="Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="9" size="3" access="Read/Write" />
+      <BitField name="EN_OSC5" description="Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="12" size="3" access="Read/Write" />
+      <BitField name="EN_OSC6" description="Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise." start="15" size="3" access="Read/Write" />
+    </Register>
+    <Register name="RNG_HTCR" description="RNG health test control register" start="+0x010" size="4" reset_value="0x000072AC" reset_mask="0xFFFFFFFF">
+      <BitField name="HTCFG" description="health test configuration" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC" description="Real-time clock" start="0x46004000">
+    <Register name="RTC_TR" description="RTC time register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" access="Read/Write" />
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_DR" description="RTC date register" start="+0x04" size="4" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="Read/Write" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="Read/Write" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="forbidden" start="0x0" />
+        <Enum name="B_0x1" description="Monday" start="0x1" />
+        <Enum name="B_0x7" description="Sunday" start="0x7" />
+      </BitField>
+      <BitField name="YU" description="Year units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="YT" description="Year tens in BCD format" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="RTC_SSR" description="RTC subsecond register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous binary counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_ICSR" description="RTC initialization control and status register" start="+0x0C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="WUTWF" description="Wake-up timer write flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Wake-up timer configuration update not allowed except in initialization mode" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer configuration update allowed" start="0x1" />
+      </BitField>
+      <BitField name="SHPF" description="Shift operation pending" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No shift operation is pending" start="0x0" />
+        <Enum name="B_0x1" description="A shift operation is pending" start="0x1" />
+      </BitField>
+      <BitField name="INITS" description="Initialization status flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Calendar has not been initialized" start="0x0" />
+        <Enum name="B_0x1" description="Calendar has been initialized" start="0x1" />
+      </BitField>
+      <BitField name="RSF" description="Registers synchronization flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calendar shadow registers not yet synchronized" start="0x0" />
+        <Enum name="B_0x1" description="Calendar shadow registers synchronized" start="0x1" />
+      </BitField>
+      <BitField name="INITF" description="Initialization flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Calendar registers update is not allowed" start="0x0" />
+        <Enum name="B_0x1" description="Calendar registers update is allowed" start="0x1" />
+      </BitField>
+      <BitField name="INIT" description="Initialization mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Free running mode" start="0x0" />
+        <Enum name="B_0x1" description="Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start counting from the new value when INIT is reset." start="0x1" />
+      </BitField>
+      <BitField name="BIN" description="Binary mode" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free running BCD calendar mode (Binary mode disabled)." start="0x0" />
+        <Enum name="B_0x1" description="Free running Binary mode (BCD mode disabled)" start="0x1" />
+        <Enum name="B_0x2" description="Free running BCD calendar and Binary modes" start="0x2" />
+        <Enum name="B_0x3" description="Free running BCD calendar and Binary modes" start="0x3" />
+      </BitField>
+      <BitField name="BCDU" description="BCD update (BIN = 10 or 11)" start="10" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1s calendar increment is generated each time SS[7:0] = 0" start="0x0" />
+        <Enum name="B_0x1" description="1s calendar increment is generated each time SS[8:0] = 0" start="0x1" />
+        <Enum name="B_0x2" description="1s calendar increment is generated each time SS[9:0] = 0" start="0x2" />
+        <Enum name="B_0x3" description="1s calendar increment is generated each time SS[10:0] = 0" start="0x3" />
+        <Enum name="B_0x4" description="1s calendar increment is generated each time SS[11:0] = 0" start="0x4" />
+        <Enum name="B_0x5" description="1s calendar increment is generated each time SS[12:0] = 0" start="0x5" />
+        <Enum name="B_0x6" description="1s calendar increment is generated each time SS[13:0] = 0" start="0x6" />
+        <Enum name="B_0x7" description="1s calendar increment is generated each time SS[14:0] = 0" start="0x7" />
+      </BitField>
+      <BitField name="RECALPF" description="Recalibration pending Flag" start="16" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_PRER" description="RTC prescaler register" start="+0x10" size="4" reset_value="0x007F00FF" reset_mask="0xFFFFFFFF">
+      <BitField name="PREDIV_S" description="Synchronous prescaler factor" start="0" size="15" access="Read/Write" />
+      <BitField name="PREDIV_A" description="Asynchronous prescaler factor" start="16" size="7" access="Read/Write" />
+    </Register>
+    <Register name="RTC_WUTR" description="RTC wake-up timer register" start="+0x14" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WUT" description="Wake-up auto-reload value bits" start="0" size="16" access="Read/Write" />
+      <BitField name="WUTOCLR" description="Wake-up auto-reload output clear value" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="RTC_CR" description="RTC control register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCKSEL" description="ck_wut wake-up clock selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="RTC/16 clock is selected" start="0x0" />
+        <Enum name="B_0x1" description="RTC/8 clock is selected" start="0x1" />
+        <Enum name="B_0x2" description="RTC/4 clock is selected" start="0x2" />
+        <Enum name="B_0x3" description="RTC/2 clock is selected" start="0x3" />
+      </BitField>
+      <BitField name="TSEDGE" description="Timestamp event active edge" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC_TS input rising edge generates a timestamp event" start="0x0" />
+        <Enum name="B_0x1" description="RTC_TS input falling edge generates a timestamp event" start="0x1" />
+      </BitField>
+      <BitField name="REFCKON" description="RTC_REFIN reference clock detection enable (50 or 60 Hz)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC_REFIN detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTC_REFIN detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="BYPSHAD" description="Bypass the shadow registers" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles." start="0x0" />
+        <Enum name="B_0x1" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters." start="0x1" />
+      </BitField>
+      <BitField name="FMT" description="Hour format" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="24 hour/day format" start="0x0" />
+        <Enum name="B_0x1" description="AM/PM hour format" start="0x1" />
+      </BitField>
+      <BitField name="SSRUIE" description="SSR underflow interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SSR underflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSR underflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRAE" description="Alarm A enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRBE" description="Alarm B enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm B enabled" start="0x1" />
+      </BitField>
+      <BitField name="WUTE" description="Wake-up timer enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up timer disabled" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSE" description="timestamp enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timestamp disable" start="0x0" />
+        <Enum name="B_0x1" description="timestamp enable" start="0x1" />
+      </BitField>
+      <BitField name="ALRAIE" description="Alarm A interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRBIE" description="Alarm B interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Alarm B interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="WUTIE" description="Wake-up timer interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up timer interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSIE" description="Timestamp interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="ADD1H" description="Add 1 hour (summer time change)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Adds 1 hour to the current time. This can be used for summer time change" start="0x1" />
+      </BitField>
+      <BitField name="SUB1H" description="Subtract 1 hour (winter time change)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Subtracts 1 hour to the current time. This can be used for winter time change." start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Backup" start="18" size="1" access="Read/Write" />
+      <BitField name="COSEL" description="Calibration output selection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration output is 512 Hz" start="0x0" />
+        <Enum name="B_0x1" description="Calibration output is 1 Hz" start="0x1" />
+      </BitField>
+      <BitField name="POL" description="Output polarity" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1)." start="0x0" />
+        <Enum name="B_0x1" description="The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1)." start="0x1" />
+      </BitField>
+      <BitField name="OSEL" description="Output selection" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A output enabled" start="0x1" />
+        <Enum name="B_0x2" description="Alarm B output enabled" start="0x2" />
+        <Enum name="B_0x3" description="Wake-up output enabled" start="0x3" />
+      </BitField>
+      <BitField name="COE" description="Calibration output enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration output enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITSE" description="timestamp on internal event enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="internal event timestamp disabled" start="0x0" />
+        <Enum name="B_0x1" description="internal event timestamp enabled" start="0x1" />
+      </BitField>
+      <BitField name="TAMPTS" description="Activate timestamp on tamper detection event" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection event does not cause a RTC timestamp to be saved" start="0x0" />
+        <Enum name="B_0x1" description="Save RTC timestamp on tamper detection event" start="0x1" />
+      </BitField>
+      <BitField name="TAMPOE" description="Tamper detection output enable on TAMPALRM" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tamper flag is not routed on TAMPALRM" start="0x0" />
+        <Enum name="B_0x1" description="The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL." start="0x1" />
+      </BitField>
+      <BitField name="ALRAFCLR" description="Alarm A flag automatic clear" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event." start="0x0" />
+        <Enum name="B_0x1" description="Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle." start="0x1" />
+      </BitField>
+      <BitField name="ALRBFCLR" description="Alarm B flag automatic clear" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event." start="0x0" />
+        <Enum name="B_0x1" description="Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle." start="0x1" />
+      </BitField>
+      <BitField name="TAMPALRM_PU" description="TAMPALRM pull-up enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up is applied on TAMPALRM output" start="0x0" />
+        <Enum name="B_0x1" description="A pull-up is applied on TAMPALRM output" start="0x1" />
+      </BitField>
+      <BitField name="TAMPALRM_TYPE" description="TAMPALRM output type" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPALRM is push-pull output" start="0x0" />
+        <Enum name="B_0x1" description="TAMPALRM is open-drain output" start="0x1" />
+      </BitField>
+      <BitField name="OUT2EN" description="RTC_OUT2 output enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RTC_PRIVCFGR" description="RTC privilege mode control register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAPRIV" description="Alarm A and SSR underflow privilege protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="ALRBPRIV" description="Alarm B privilege protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Alarm B configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Alarm B configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="WUTPRIV" description="Wake-up timer privilege protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC wake-up timer configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC wake-up timer configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="TSPRIV" description="Timestamp privilege protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Timestamp configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Timestamp configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="CALPRIV" description="Shift register, Delight saving, calibration and reference clock privilege protection" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Shift register, Delight saving, calibration and reference clock can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="Shift register, Delight saving, calibration and reference clock can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="INITPRIV" description="Initialization privilege protection" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Initialization mode, calendar and prescalers registers can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="RTC privilege protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All RTC registers can be written when the APB access is privileged or non-privileged, except the registers protected by other privilege protection bits." start="0x0" />
+        <Enum name="B_0x1" description="All RTC registers can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SECCFGR" description="RTC secure configuration register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRASEC" description="Alarm A and SSR underflow protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="ALRBSEC" description="Alarm B protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC alarm B configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC alarm B configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="WUTSEC" description="Wake-up timer protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC wake-up timer configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC wake-up timer configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="TSSEC" description="Timestamp protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC timestamp configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC timestamp configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="CALSEC" description="Shift register, daylight saving, calibration and reference clock protection" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Shift register, daylight saving, calibration and reference clock can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Shift register, daylight saving, calibration and reference clock can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="INITSEC" description="Initialization protection" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Initialization mode, calendar and prescalers registers can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="RTC global protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All RTC registers can be written when the APB access is secure or non-secure, except the registers protected by other secure protection bits." start="0x0" />
+        <Enum name="B_0x1" description="All RTC registers can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_WPR" description="RTC write protection register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RTC_CALR" description="RTC calibration register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALM" description="Calibration minus" start="0" size="9" access="Read/Write" />
+      <BitField name="LPCAL" description="RTC low-power mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration window is 2less thansup&gt;20less than/sup&gt; RTCCLK, which is a high-consumption mode. This mode must be set only when less than 32s calibration window is required." start="0x0" />
+        <Enum name="B_0x1" description="Calibration window is 2less thansup&gt;20less than/sup&gt; ck_apre, which is the required configuration for ultra-low consumption mode." start="0x1" />
+      </BitField>
+      <BitField name="CALW16" description="Use a 16-second calibration cycle period" start="13" size="1" access="Read/Write" />
+      <BitField name="CALW8" description="Use an 8-second calibration cycle period" start="14" size="1" access="Read/Write" />
+      <BitField name="CALP" description="Increase frequency of RTC by 488.5 ppm" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No RTCCLK pulses are added." start="0x0" />
+        <Enum name="B_0x1" description="One RTCCLK pulse is effectively inserted every 2less thansup&gt;11less than/sup&gt; pulses (frequency increased by 488.5 ppm)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SHIFTR" description="RTC shift control register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUBFS" description="Subtract a fraction of a second" start="0" size="15" access="WriteOnly" />
+      <BitField name="ADD1S" description="Add one second" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Add one second to the clock/calendar" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_TSTR" description="RTC timestamp time register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="ReadOnly" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="ReadOnly" />
+      <BitField name="MNU" description="Minute units in BCD format." start="8" size="4" access="ReadOnly" />
+      <BitField name="MNT" description="Minute tens in BCD format." start="12" size="3" access="ReadOnly" />
+      <BitField name="HU" description="Hour units in BCD format." start="16" size="4" access="ReadOnly" />
+      <BitField name="HT" description="Hour tens in BCD format." start="20" size="2" access="ReadOnly" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_TSDR" description="RTC timestamp date register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="ReadOnly" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="ReadOnly" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="ReadOnly" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="ReadOnly" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_TSSSR" description="RTC timestamp subsecond register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subsecond value/synchronous binary counter values" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_ALRMAR" description="RTC alarm A register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="Read/Write" />
+      <BitField name="MSK1" description="Alarm A seconds mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the seconds match" start="0x0" />
+        <Enum name="B_0x1" description="Seconds don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="MSK2" description="Alarm A minutes mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the minutes match" start="0x0" />
+        <Enum name="B_0x1" description="Minutes don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+      <BitField name="MSK3" description="Alarm A hours mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the hours match" start="0x0" />
+        <Enum name="B_0x1" description="Hours don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" access="Read/Write" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DU[3:0] represents the date units" start="0x0" />
+        <Enum name="B_0x1" description="DU[3:0] represents the week day. DT[1:0] is don't care." start="0x1" />
+      </BitField>
+      <BitField name="MSK4" description="Alarm A date mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the date/day match" start="0x0" />
+        <Enum name="B_0x1" description="Date/day don't care in alarm A comparison" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMASSR" description="RTC alarm A subsecond register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subseconds value" start="0" size="15" access="Read/Write" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match)." start="0x0" />
+        <Enum name="B_0x1" description="SS[31:1] are don't care in Alarm A comparison. Only SS[0] is compared." start="0x1" />
+      </BitField>
+      <BitField name="SSCLR" description="Clear synchronous counter on alarm (Binary mode only)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running." start="0x0" />
+        <Enum name="B_0x1" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMBR" description="RTC alarm B register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" access="Read/Write" />
+      <BitField name="MSK1" description="Alarm B seconds mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the seconds match" start="0x0" />
+        <Enum name="B_0x1" description="Seconds don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="MSK2" description="Alarm B minutes mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the minutes match" start="0x0" />
+        <Enum name="B_0x1" description="Minutes don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+      <BitField name="MSK3" description="Alarm B hours mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the hours match" start="0x0" />
+        <Enum name="B_0x1" description="Hours don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" access="Read/Write" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DU[3:0] represents the date units" start="0x0" />
+        <Enum name="B_0x1" description="DU[3:0] represents the week day. DT[1:0] is don't care." start="0x1" />
+      </BitField>
+      <BitField name="MSK4" description="Alarm B date mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the date and day match" start="0x0" />
+        <Enum name="B_0x1" description="Date and day don't care in alarm B comparison" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMBSSR" description="RTC alarm B subsecond register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subseconds value" start="0" size="15" access="Read/Write" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No comparison on subseconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match)." start="0x0" />
+        <Enum name="B_0x1" description="SS[31:1] are don't care in Alarm B comparison. Only SS[0] is compared." start="0x1" />
+      </BitField>
+      <BitField name="SSCLR" description="Clear synchronous counter on alarm (Binary mode only)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running." start="0x0" />
+        <Enum name="B_0x1" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRBBINR.SS[31:0] value and is automatically reloaded with 0xFFFF FFFF one ck_apre cycle after reaching RTC_ALRBBINR.SS[31:0]." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SR" description="RTC status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAF" description="Alarm A flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBF" description="Alarm B flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTF" description="Wake-up timer flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSF" description="Timestamp flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVF" description="Timestamp overflow flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSF" description="Internal timestamp flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUF" description="SSR underflow flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_MISR" description="RTC non-secure masked interrupt status register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAMF" description="Alarm A masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBMF" description="Alarm B non-secure masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTMF" description="Wake-up timer non-secure masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSMF" description="Timestamp non-secure masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVMF" description="Timestamp overflow non-secure masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSMF" description="Internal timestamp non-secure masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUMF" description="SSR underflow non-secure masked flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_SMISR" description="RTC secure masked interrupt status register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAMF" description="Alarm A interrupt secure masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBMF" description="Alarm B interrupt secure masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTMF" description="Wake-up timer interrupt secure masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSMF" description="Timestamp interrupt secure masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVMF" description="Timestamp overflow interrupt secure masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSMF" description="Internal timestamp interrupt secure masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUMF" description="SSR underflow secure masked flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_SCR" description="RTC status clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALRAF" description="Clear alarm A flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CALRBF" description="Clear alarm B flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CWUTF" description="Clear wake-up timer flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CTSF" description="Clear timestamp flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTSOVF" description="Clear timestamp overflow flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CITSF" description="Clear internal timestamp flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSSRUF" description="Clear SSR underflow flag" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RTC_ALRABINR" description="RTC alarm A binary mode register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous counter alarm value in Binary mode" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RTC_ALRBBINR" description="RTC alarm B binary mode register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous counter alarm value in Binary mode" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC_S" description="Real-time clock" start="0x56004000">
+    <Register name="RTC_TR" description="RTC time register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" access="Read/Write" />
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_DR" description="RTC date register" start="+0x04" size="4" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="Read/Write" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="Read/Write" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="forbidden" start="0x0" />
+        <Enum name="B_0x1" description="Monday" start="0x1" />
+        <Enum name="B_0x7" description="Sunday" start="0x7" />
+      </BitField>
+      <BitField name="YU" description="Year units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="YT" description="Year tens in BCD format" start="20" size="4" access="Read/Write" />
+    </Register>
+    <Register name="RTC_SSR" description="RTC subsecond register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous binary counter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_ICSR" description="RTC initialization control and status register" start="+0x0C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="WUTWF" description="Wake-up timer write flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Wake-up timer configuration update not allowed except in initialization mode" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer configuration update allowed" start="0x1" />
+      </BitField>
+      <BitField name="SHPF" description="Shift operation pending" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No shift operation is pending" start="0x0" />
+        <Enum name="B_0x1" description="A shift operation is pending" start="0x1" />
+      </BitField>
+      <BitField name="INITS" description="Initialization status flag" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Calendar has not been initialized" start="0x0" />
+        <Enum name="B_0x1" description="Calendar has been initialized" start="0x1" />
+      </BitField>
+      <BitField name="RSF" description="Registers synchronization flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calendar shadow registers not yet synchronized" start="0x0" />
+        <Enum name="B_0x1" description="Calendar shadow registers synchronized" start="0x1" />
+      </BitField>
+      <BitField name="INITF" description="Initialization flag" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Calendar registers update is not allowed" start="0x0" />
+        <Enum name="B_0x1" description="Calendar registers update is allowed" start="0x1" />
+      </BitField>
+      <BitField name="INIT" description="Initialization mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Free running mode" start="0x0" />
+        <Enum name="B_0x1" description="Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start counting from the new value when INIT is reset." start="0x1" />
+      </BitField>
+      <BitField name="BIN" description="Binary mode" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free running BCD calendar mode (Binary mode disabled)." start="0x0" />
+        <Enum name="B_0x1" description="Free running Binary mode (BCD mode disabled)" start="0x1" />
+        <Enum name="B_0x2" description="Free running BCD calendar and Binary modes" start="0x2" />
+        <Enum name="B_0x3" description="Free running BCD calendar and Binary modes" start="0x3" />
+      </BitField>
+      <BitField name="BCDU" description="BCD update (BIN = 10 or 11)" start="10" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1s calendar increment is generated each time SS[7:0] = 0" start="0x0" />
+        <Enum name="B_0x1" description="1s calendar increment is generated each time SS[8:0] = 0" start="0x1" />
+        <Enum name="B_0x2" description="1s calendar increment is generated each time SS[9:0] = 0" start="0x2" />
+        <Enum name="B_0x3" description="1s calendar increment is generated each time SS[10:0] = 0" start="0x3" />
+        <Enum name="B_0x4" description="1s calendar increment is generated each time SS[11:0] = 0" start="0x4" />
+        <Enum name="B_0x5" description="1s calendar increment is generated each time SS[12:0] = 0" start="0x5" />
+        <Enum name="B_0x6" description="1s calendar increment is generated each time SS[13:0] = 0" start="0x6" />
+        <Enum name="B_0x7" description="1s calendar increment is generated each time SS[14:0] = 0" start="0x7" />
+      </BitField>
+      <BitField name="RECALPF" description="Recalibration pending Flag" start="16" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_PRER" description="RTC prescaler register" start="+0x10" size="4" reset_value="0x007F00FF" reset_mask="0xFFFFFFFF">
+      <BitField name="PREDIV_S" description="Synchronous prescaler factor" start="0" size="15" access="Read/Write" />
+      <BitField name="PREDIV_A" description="Asynchronous prescaler factor" start="16" size="7" access="Read/Write" />
+    </Register>
+    <Register name="RTC_WUTR" description="RTC wake-up timer register" start="+0x14" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WUT" description="Wake-up auto-reload value bits" start="0" size="16" access="Read/Write" />
+      <BitField name="WUTOCLR" description="Wake-up auto-reload output clear value" start="16" size="16" access="Read/Write" />
+    </Register>
+    <Register name="RTC_CR" description="RTC control register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCKSEL" description="ck_wut wake-up clock selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="RTC/16 clock is selected" start="0x0" />
+        <Enum name="B_0x1" description="RTC/8 clock is selected" start="0x1" />
+        <Enum name="B_0x2" description="RTC/4 clock is selected" start="0x2" />
+        <Enum name="B_0x3" description="RTC/2 clock is selected" start="0x3" />
+      </BitField>
+      <BitField name="TSEDGE" description="Timestamp event active edge" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC_TS input rising edge generates a timestamp event" start="0x0" />
+        <Enum name="B_0x1" description="RTC_TS input falling edge generates a timestamp event" start="0x1" />
+      </BitField>
+      <BitField name="REFCKON" description="RTC_REFIN reference clock detection enable (50 or 60 Hz)" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC_REFIN detection disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTC_REFIN detection enabled" start="0x1" />
+      </BitField>
+      <BitField name="BYPSHAD" description="Bypass the shadow registers" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles." start="0x0" />
+        <Enum name="B_0x1" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters." start="0x1" />
+      </BitField>
+      <BitField name="FMT" description="Hour format" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="24 hour/day format" start="0x0" />
+        <Enum name="B_0x1" description="AM/PM hour format" start="0x1" />
+      </BitField>
+      <BitField name="SSRUIE" description="SSR underflow interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SSR underflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SSR underflow interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRAE" description="Alarm A enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRBE" description="Alarm B enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm B enabled" start="0x1" />
+      </BitField>
+      <BitField name="WUTE" description="Wake-up timer enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up timer disabled" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSE" description="timestamp enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timestamp disable" start="0x0" />
+        <Enum name="B_0x1" description="timestamp enable" start="0x1" />
+      </BitField>
+      <BitField name="ALRAIE" description="Alarm A interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ALRBIE" description="Alarm B interrupt enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Alarm B interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="WUTIE" description="Wake-up timer interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Wake-up timer interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Wake-up timer interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSIE" description="Timestamp interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Timestamp interrupt disable" start="0x0" />
+        <Enum name="B_0x1" description="Timestamp interrupt enable" start="0x1" />
+      </BitField>
+      <BitField name="ADD1H" description="Add 1 hour (summer time change)" start="16" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Adds 1 hour to the current time. This can be used for summer time change" start="0x1" />
+      </BitField>
+      <BitField name="SUB1H" description="Subtract 1 hour (winter time change)" start="17" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Subtracts 1 hour to the current time. This can be used for winter time change." start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Backup" start="18" size="1" access="Read/Write" />
+      <BitField name="COSEL" description="Calibration output selection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration output is 512 Hz" start="0x0" />
+        <Enum name="B_0x1" description="Calibration output is 1 Hz" start="0x1" />
+      </BitField>
+      <BitField name="POL" description="Output polarity" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1)." start="0x0" />
+        <Enum name="B_0x1" description="The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1)." start="0x1" />
+      </BitField>
+      <BitField name="OSEL" description="Output selection" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Alarm A output enabled" start="0x1" />
+        <Enum name="B_0x2" description="Alarm B output enabled" start="0x2" />
+        <Enum name="B_0x3" description="Wake-up output enabled" start="0x3" />
+      </BitField>
+      <BitField name="COE" description="Calibration output enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration output disabled" start="0x0" />
+        <Enum name="B_0x1" description="Calibration output enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITSE" description="timestamp on internal event enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="internal event timestamp disabled" start="0x0" />
+        <Enum name="B_0x1" description="internal event timestamp enabled" start="0x1" />
+      </BitField>
+      <BitField name="TAMPTS" description="Activate timestamp on tamper detection event" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection event does not cause a RTC timestamp to be saved" start="0x0" />
+        <Enum name="B_0x1" description="Save RTC timestamp on tamper detection event" start="0x1" />
+      </BitField>
+      <BitField name="TAMPOE" description="Tamper detection output enable on TAMPALRM" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tamper flag is not routed on TAMPALRM" start="0x0" />
+        <Enum name="B_0x1" description="The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL." start="0x1" />
+      </BitField>
+      <BitField name="ALRAFCLR" description="Alarm A flag automatic clear" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event." start="0x0" />
+        <Enum name="B_0x1" description="Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle." start="0x1" />
+      </BitField>
+      <BitField name="ALRBFCLR" description="Alarm B flag automatic clear" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event." start="0x0" />
+        <Enum name="B_0x1" description="Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle." start="0x1" />
+      </BitField>
+      <BitField name="TAMPALRM_PU" description="TAMPALRM pull-up enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No pull-up is applied on TAMPALRM output" start="0x0" />
+        <Enum name="B_0x1" description="A pull-up is applied on TAMPALRM output" start="0x1" />
+      </BitField>
+      <BitField name="TAMPALRM_TYPE" description="TAMPALRM output type" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPALRM is push-pull output" start="0x0" />
+        <Enum name="B_0x1" description="TAMPALRM is open-drain output" start="0x1" />
+      </BitField>
+      <BitField name="OUT2EN" description="RTC_OUT2 output enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RTC_PRIVCFGR" description="RTC privilege mode control register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAPRIV" description="Alarm A and SSR underflow privilege protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="ALRBPRIV" description="Alarm B privilege protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Alarm B configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Alarm B configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="WUTPRIV" description="Wake-up timer privilege protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC wake-up timer configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC wake-up timer configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="TSPRIV" description="Timestamp privilege protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Timestamp configuration and interrupt clear can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Timestamp configuration and interrupt clear can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="CALPRIV" description="Shift register, Delight saving, calibration and reference clock privilege protection" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Shift register, Delight saving, calibration and reference clock can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="Shift register, Delight saving, calibration and reference clock can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="INITPRIV" description="Initialization privilege protection" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Initialization mode, calendar and prescalers registers can be written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="PRIV" description="RTC privilege protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All RTC registers can be written when the APB access is privileged or non-privileged, except the registers protected by other privilege protection bits." start="0x0" />
+        <Enum name="B_0x1" description="All RTC registers can be written only when the APB access is privileged." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SECCFGR" description="RTC secure configuration register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRASEC" description="Alarm A and SSR underflow protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="ALRBSEC" description="Alarm B protection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC alarm B configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC alarm B configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="WUTSEC" description="Wake-up timer protection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC wake-up timer configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC wake-up timer configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="TSSEC" description="Timestamp protection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC timestamp configuration and interrupt clear can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC timestamp configuration and interrupt clear can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="CALSEC" description="Shift register, daylight saving, calibration and reference clock protection" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Shift register, daylight saving, calibration and reference clock can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Shift register, daylight saving, calibration and reference clock can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="INITSEC" description="Initialization protection" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTC Initialization mode, calendar and prescalers registers can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="SEC" description="RTC global protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All RTC registers can be written when the APB access is secure or non-secure, except the registers protected by other secure protection bits." start="0x0" />
+        <Enum name="B_0x1" description="All RTC registers can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_WPR" description="RTC write protection register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Write protection key" start="0" size="8" access="WriteOnly" />
+    </Register>
+    <Register name="RTC_CALR" description="RTC calibration register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALM" description="Calibration minus" start="0" size="9" access="Read/Write" />
+      <BitField name="LPCAL" description="RTC low-power mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration window is 2less thansup&gt;20less than/sup&gt; RTCCLK, which is a high-consumption mode. This mode must be set only when less than 32s calibration window is required." start="0x0" />
+        <Enum name="B_0x1" description="Calibration window is 2less thansup&gt;20less than/sup&gt; ck_apre, which is the required configuration for ultra-low consumption mode." start="0x1" />
+      </BitField>
+      <BitField name="CALW16" description="Use a 16-second calibration cycle period" start="13" size="1" access="Read/Write" />
+      <BitField name="CALW8" description="Use an 8-second calibration cycle period" start="14" size="1" access="Read/Write" />
+      <BitField name="CALP" description="Increase frequency of RTC by 488.5 ppm" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No RTCCLK pulses are added." start="0x0" />
+        <Enum name="B_0x1" description="One RTCCLK pulse is effectively inserted every 2less thansup&gt;11less than/sup&gt; pulses (frequency increased by 488.5 ppm)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SHIFTR" description="RTC shift control register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUBFS" description="Subtract a fraction of a second" start="0" size="15" access="WriteOnly" />
+      <BitField name="ADD1S" description="Add one second" start="31" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Add one second to the clock/calendar" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_TSTR" description="RTC timestamp time register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="ReadOnly" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="ReadOnly" />
+      <BitField name="MNU" description="Minute units in BCD format." start="8" size="4" access="ReadOnly" />
+      <BitField name="MNT" description="Minute tens in BCD format." start="12" size="3" access="ReadOnly" />
+      <BitField name="HU" description="Hour units in BCD format." start="16" size="4" access="ReadOnly" />
+      <BitField name="HT" description="Hour tens in BCD format." start="20" size="2" access="ReadOnly" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_TSDR" description="RTC timestamp date register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="ReadOnly" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="ReadOnly" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="ReadOnly" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="ReadOnly" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_TSSSR" description="RTC timestamp subsecond register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subsecond value/synchronous binary counter values" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_ALRMAR" description="RTC alarm A register" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="Read/Write" />
+      <BitField name="MSK1" description="Alarm A seconds mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the seconds match" start="0x0" />
+        <Enum name="B_0x1" description="Seconds don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="MSK2" description="Alarm A minutes mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the minutes match" start="0x0" />
+        <Enum name="B_0x1" description="Minutes don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+      <BitField name="MSK3" description="Alarm A hours mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the hours match" start="0x0" />
+        <Enum name="B_0x1" description="Hours don't care in alarm A comparison" start="0x1" />
+      </BitField>
+      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" access="Read/Write" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DU[3:0] represents the date units" start="0x0" />
+        <Enum name="B_0x1" description="DU[3:0] represents the week day. DT[1:0] is don't care." start="0x1" />
+      </BitField>
+      <BitField name="MSK4" description="Alarm A date mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm A set if the date/day match" start="0x0" />
+        <Enum name="B_0x1" description="Date/day don't care in alarm A comparison" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMASSR" description="RTC alarm A subsecond register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subseconds value" start="0" size="15" access="Read/Write" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match)." start="0x0" />
+        <Enum name="B_0x1" description="SS[31:1] are don't care in Alarm A comparison. Only SS[0] is compared." start="0x1" />
+      </BitField>
+      <BitField name="SSCLR" description="Clear synchronous counter on alarm (Binary mode only)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running." start="0x0" />
+        <Enum name="B_0x1" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMBR" description="RTC alarm B register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" access="Read/Write" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" access="Read/Write" />
+      <BitField name="MSK1" description="Alarm B seconds mask" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the seconds match" start="0x0" />
+        <Enum name="B_0x1" description="Seconds don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
+      <BitField name="MSK2" description="Alarm B minutes mask" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the minutes match" start="0x0" />
+        <Enum name="B_0x1" description="Minutes don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
+        <Enum name="B_0x1" description="PM" start="0x1" />
+      </BitField>
+      <BitField name="MSK3" description="Alarm B hours mask" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the hours match" start="0x0" />
+        <Enum name="B_0x1" description="Hours don't care in alarm B comparison" start="0x1" />
+      </BitField>
+      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" access="Read/Write" />
+      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" access="Read/Write" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DU[3:0] represents the date units" start="0x0" />
+        <Enum name="B_0x1" description="DU[3:0] represents the week day. DT[1:0] is don't care." start="0x1" />
+      </BitField>
+      <BitField name="MSK4" description="Alarm B date mask" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Alarm B set if the date and day match" start="0x0" />
+        <Enum name="B_0x1" description="Date and day don't care in alarm B comparison" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_ALRMBSSR" description="RTC alarm B subsecond register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Subseconds value" start="0" size="15" access="Read/Write" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit" start="24" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="No comparison on subseconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match)." start="0x0" />
+        <Enum name="B_0x1" description="SS[31:1] are don't care in Alarm B comparison. Only SS[0] is compared." start="0x1" />
+      </BitField>
+      <BitField name="SSCLR" description="Clear synchronous counter on alarm (Binary mode only)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running." start="0x0" />
+        <Enum name="B_0x1" description="The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRBBINR.SS[31:0] value and is automatically reloaded with 0xFFFF FFFF one ck_apre cycle after reaching RTC_ALRBBINR.SS[31:0]." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="RTC_SR" description="RTC status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAF" description="Alarm A flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBF" description="Alarm B flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTF" description="Wake-up timer flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSF" description="Timestamp flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVF" description="Timestamp overflow flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSF" description="Internal timestamp flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUF" description="SSR underflow flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_MISR" description="RTC non-secure masked interrupt status register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAMF" description="Alarm A masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBMF" description="Alarm B non-secure masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTMF" description="Wake-up timer non-secure masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSMF" description="Timestamp non-secure masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVMF" description="Timestamp overflow non-secure masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSMF" description="Internal timestamp non-secure masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUMF" description="SSR underflow non-secure masked flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_SMISR" description="RTC secure masked interrupt status register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAMF" description="Alarm A interrupt secure masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBMF" description="Alarm B interrupt secure masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTMF" description="Wake-up timer interrupt secure masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TSMF" description="Timestamp interrupt secure masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TSOVMF" description="Timestamp overflow interrupt secure masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="ITSMF" description="Internal timestamp interrupt secure masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="SSRUMF" description="SSR underflow secure masked flag" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="RTC_SCR" description="RTC status clear register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALRAF" description="Clear alarm A flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CALRBF" description="Clear alarm B flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CWUTF" description="Clear wake-up timer flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CTSF" description="Clear timestamp flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTSOVF" description="Clear timestamp overflow flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CITSF" description="Clear internal timestamp flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CSSRUF" description="Clear SSR underflow flag" start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="RTC_ALRABINR" description="RTC alarm A binary mode register" start="+0x70" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous counter alarm value in Binary mode" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="RTC_ALRBBINR" description="RTC alarm B binary mode register" start="+0x74" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Synchronous counter alarm value in Binary mode" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAES" description="Secure AES coprocessor" start="0x44021000">
+    <Register name="SAES_CR" description="SAES control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No swapping (32-bit data)." start="0x0" />
+        <Enum name="B_0x1" description="Half-word swapping (16-bit data)" start="0x1" />
+        <Enum name="B_0x2" description="Byte swapping (8-bit data)" start="0x2" />
+        <Enum name="B_0x3" description="Bit-level swapping" start="0x3" />
+      </BitField>
+      <BitField name="MODE" description="Operating mode" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Encryption" start="0x0" />
+        <Enum name="B_0x1" description="Key derivation (or key preparation), for ECB/CBC decryption only" start="0x1" />
+        <Enum name="B_0x2" description="Decryption" start="0x2" />
+      </BitField>
+      <BitField name="CHMOD" description="CHMOD[1:0]: Chaining mode" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Electronic codebook (ECB)" start="0x0" />
+        <Enum name="B_0x1" description="Cipher-block chaining (CBC)" start="0x1" />
+        <Enum name="B_0x2" description="Counter mode (CTR)" start="0x2" />
+        <Enum name="B_0x3" description="Galois counter mode (GCM) and Galois message authentication code (GMAC)" start="0x3" />
+      </BitField>
+      <BitField name="DMAINEN" description="DMA input enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="DMAOUTEN" description="DMA output enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="GCMPH" description="GCM or CCM phase selection" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Initialization phase" start="0x0" />
+        <Enum name="B_0x1" description="Header phase" start="0x1" />
+        <Enum name="B_0x2" description="Payload phase" start="0x2" />
+        <Enum name="B_0x3" description="Final phase" start="0x3" />
+      </BitField>
+      <BitField name="CHMOD_1" description="CHMOD[2]" start="16" size="1" access="Read/Write" />
+      <BitField name="KEYSIZE" description="Key size selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="128-bit" start="0x0" />
+        <Enum name="B_0x1" description="256-bit" start="0x1" />
+      </BitField>
+      <BitField name="KEYPROT" description="Key protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When KEYVALID is set and KEYSEL[2:0] = 0 application can transfer the ownership of the SAES, with its loaded key, to an application running in another security context (such as non-secure, secure)." start="0x0" />
+        <Enum name="B_0x1" description="When KEYVALID is set, key error flag (KEIF) is set when an access to any registers is detected, this access having a security context (for example, secure, non-secure) that does not match the one of the application that loaded the key." start="0x1" />
+      </BitField>
+      <BitField name="NPBLB" description="Number of padding bytes in last block" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="All bytes are valid (no padding)" start="0x0" />
+        <Enum name="B_0x1" description="Padding for the last LSB byte" start="0x1" />
+        <Enum name="B_0xF" description="Padding for the 15 LSB bytes of last block." start="0xF" />
+      </BitField>
+      <BitField name="KMOD" description="Key mode selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Normal key mode. Key registers are freely usable and no specific use or protection applies to SAES_DINR and SAES_DOUTR registers." start="0x0" />
+        <Enum name="B_0x1" description="Wrapped key mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process." start="0x1" />
+        <Enum name="B_0x2" description="Shared key mode. After a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process." start="0x2" />
+      </BitField>
+      <BitField name="KSHAREID" description="Key share identification" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP peripheral" start="0x0" />
+      </BitField>
+      <BitField name="KEYSEL" description="Key selection" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Software key, loaded in key registers SAES_KEYx" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK)" start="0x1" />
+        <Enum name="B_0x2" description="Boot hardware key (BHK)" start="0x2" />
+        <Enum name="B_0x4" description="XOR of DHUK and BHK" start="0x4" />
+        <Enum name="B_0x7" description="Test mode key (256-bit hardware constant 0xA5A5...A5A5)" start="0x7" />
+      </BitField>
+      <BitField name="IPRST" description="SAES peripheral software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SR" description="SAES status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDERRF" description="Read error flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error" start="0x0" />
+        <Enum name="B_0x1" description="Unexpected read to SAES_DOUTR register occurred during computation or data input phase." start="0x1" />
+      </BitField>
+      <BitField name="WRERRF" description="Write error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error" start="0x0" />
+        <Enum name="B_0x1" description="Unexpected write to SAES_DINR register occurred during computation or data output phase." start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle" start="0x0" />
+        <Enum name="B_0x1" description="Busy" start="0x1" />
+      </BitField>
+      <BitField name="KEYVALID" description="Key valid flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Key not valid" start="0x0" />
+        <Enum name="B_0x1" description="Key valid" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_DINR" description="SAES data input register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="Data input" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_DOUTR" description="SAES data output register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="Data output" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SAES_KEYR0" description="SAES key register 0" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR1" description="SAES key register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR2" description="SAES key register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR3" description="SAES key register 3" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_IVR0" description="SAES initialization vector register 0" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR1" description="SAES initialization vector register 1" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR2" description="SAES initialization vector register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [95:64]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR3" description="SAES initialization vector register 3" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [127:96]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_KEYR4" description="SAES key register 4" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [159:128]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR5" description="SAES key register 5" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [191:160]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR6" description="SAES key register 6" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [223:192]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR7" description="SAES key register 7" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [255:224]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_SUSPR0" description="SAES suspend registers" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR1" description="SAES suspend registers" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR2" description="SAES suspend registers" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR3" description="SAES suspend registers" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR4" description="SAES suspend registers" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR5" description="SAES suspend registers" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR6" description="SAES suspend registers" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR7" description="SAES suspend registers" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IER" description="SAES interrupt enable register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCFIE" description="Computation complete flag interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="RWEIE" description="Read or write error interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="KEIE" description="Key error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="RNGEIE" description="RNG error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_ISR" description="SAES interrupt status register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCF" description="Computation complete flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="RWEIF" description="Read or write error interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No read or write error detected" start="0x0" />
+        <Enum name="B_0x1" description="Read or write error detected" start="0x1" />
+      </BitField>
+      <BitField name="KEIF" description="Key error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No key error detected" start="0x0" />
+        <Enum name="B_0x1" description="Key information failed to load into key registers or the key register use is forbidden" start="0x1" />
+      </BitField>
+      <BitField name="RNGEIF" description="RNG error interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RNG bus is functional" start="0x0" />
+        <Enum name="B_0x1" description="Error detected on RNG bus interface (random seed fetching error)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_ICR" description="SAES interrupt clear register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCF" description="Computation complete flag clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="RWEIF" description="Read or write error interrupt flag clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="KEIF" description="Key error interrupt flag clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="RNGEIF" description="RNG error interrupt flag clear" start="3" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAES_S" description="Secure AES coprocessor" start="0x54021000">
+    <Register name="SAES_CR" description="SAES control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="DATATYPE" description="Data type" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No swapping (32-bit data)." start="0x0" />
+        <Enum name="B_0x1" description="Half-word swapping (16-bit data)" start="0x1" />
+        <Enum name="B_0x2" description="Byte swapping (8-bit data)" start="0x2" />
+        <Enum name="B_0x3" description="Bit-level swapping" start="0x3" />
+      </BitField>
+      <BitField name="MODE" description="Operating mode" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Encryption" start="0x0" />
+        <Enum name="B_0x1" description="Key derivation (or key preparation), for ECB/CBC decryption only" start="0x1" />
+        <Enum name="B_0x2" description="Decryption" start="0x2" />
+      </BitField>
+      <BitField name="CHMOD" description="CHMOD[1:0]: Chaining mode" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Electronic codebook (ECB)" start="0x0" />
+        <Enum name="B_0x1" description="Cipher-block chaining (CBC)" start="0x1" />
+        <Enum name="B_0x2" description="Counter mode (CTR)" start="0x2" />
+        <Enum name="B_0x3" description="Galois counter mode (GCM) and Galois message authentication code (GMAC)" start="0x3" />
+      </BitField>
+      <BitField name="DMAINEN" description="DMA input enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="DMAOUTEN" description="DMA output enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="GCMPH" description="GCM or CCM phase selection" start="13" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Initialization phase" start="0x0" />
+        <Enum name="B_0x1" description="Header phase" start="0x1" />
+        <Enum name="B_0x2" description="Payload phase" start="0x2" />
+        <Enum name="B_0x3" description="Final phase" start="0x3" />
+      </BitField>
+      <BitField name="CHMOD_1" description="CHMOD[2]" start="16" size="1" access="Read/Write" />
+      <BitField name="KEYSIZE" description="Key size selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="128-bit" start="0x0" />
+        <Enum name="B_0x1" description="256-bit" start="0x1" />
+      </BitField>
+      <BitField name="KEYPROT" description="Key protection" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When KEYVALID is set and KEYSEL[2:0] = 0 application can transfer the ownership of the SAES, with its loaded key, to an application running in another security context (such as non-secure, secure)." start="0x0" />
+        <Enum name="B_0x1" description="When KEYVALID is set, key error flag (KEIF) is set when an access to any registers is detected, this access having a security context (for example, secure, non-secure) that does not match the one of the application that loaded the key." start="0x1" />
+      </BitField>
+      <BitField name="NPBLB" description="Number of padding bytes in last block" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="All bytes are valid (no padding)" start="0x0" />
+        <Enum name="B_0x1" description="Padding for the last LSB byte" start="0x1" />
+        <Enum name="B_0xF" description="Padding for the 15 LSB bytes of last block." start="0xF" />
+      </BitField>
+      <BitField name="KMOD" description="Key mode selection" start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Normal key mode. Key registers are freely usable and no specific use or protection applies to SAES_DINR and SAES_DOUTR registers." start="0x0" />
+        <Enum name="B_0x1" description="Wrapped key mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process." start="0x1" />
+        <Enum name="B_0x2" description="Shared key mode. After a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process." start="0x2" />
+      </BitField>
+      <BitField name="KSHAREID" description="Key share identification" start="26" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CRYP peripheral" start="0x0" />
+      </BitField>
+      <BitField name="KEYSEL" description="Key selection" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Software key, loaded in key registers SAES_KEYx" start="0x0" />
+        <Enum name="B_0x1" description="Derived hardware unique key (DHUK)" start="0x1" />
+        <Enum name="B_0x2" description="Boot hardware key (BHK)" start="0x2" />
+        <Enum name="B_0x4" description="XOR of DHUK and BHK" start="0x4" />
+        <Enum name="B_0x7" description="Test mode key (256-bit hardware constant 0xA5A5...A5A5)" start="0x7" />
+      </BitField>
+      <BitField name="IPRST" description="SAES peripheral software reset" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SR" description="SAES status register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDERRF" description="Read error flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error" start="0x0" />
+        <Enum name="B_0x1" description="Unexpected read to SAES_DOUTR register occurred during computation or data input phase." start="0x1" />
+      </BitField>
+      <BitField name="WRERRF" description="Write error flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error" start="0x0" />
+        <Enum name="B_0x1" description="Unexpected write to SAES_DINR register occurred during computation or data output phase." start="0x1" />
+      </BitField>
+      <BitField name="BUSY" description="Busy" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Idle" start="0x0" />
+        <Enum name="B_0x1" description="Busy" start="0x1" />
+      </BitField>
+      <BitField name="KEYVALID" description="Key valid flag" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Key not valid" start="0x0" />
+        <Enum name="B_0x1" description="Key valid" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_DINR" description="SAES data input register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN" description="Data input" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_DOUTR" description="SAES data output register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT" description="Data output" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SAES_KEYR0" description="SAES key register 0" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [31:0]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR1" description="SAES key register 1" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [63:32]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR2" description="SAES key register 2" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [95:64]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR3" description="SAES key register 3" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [127:96]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_IVR0" description="SAES initialization vector register 0" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [31:0]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR1" description="SAES initialization vector register 1" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [63:32]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR2" description="SAES initialization vector register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [95:64]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IVR3" description="SAES initialization vector register 3" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IVI" description="Initialization vector input, bits [127:96]" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_KEYR4" description="SAES key register 4" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [159:128]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR5" description="SAES key register 5" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [191:160]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR6" description="SAES key register 6" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [223:192]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_KEYR7" description="SAES key register 7" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Cryptographic key, bits [255:224]" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SAES_SUSPR0" description="SAES suspend registers" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR1" description="SAES suspend registers" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR2" description="SAES suspend registers" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR3" description="SAES suspend registers" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR4" description="SAES suspend registers" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR5" description="SAES suspend registers" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR6" description="SAES suspend registers" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_SUSPR7" description="SAES suspend registers" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSP" description="Suspend data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAES_IER" description="SAES interrupt enable register" start="+0x300" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCFIE" description="Computation complete flag interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="RWEIE" description="Read or write error interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="KEIE" description="Key error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+      <BitField name="RNGEIE" description="RNG error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled (masked)" start="0x0" />
+        <Enum name="B_0x1" description="Enabled (not masked)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_ISR" description="SAES interrupt status register" start="+0x304" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCF" description="Computation complete flag" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Not completed" start="0x0" />
+        <Enum name="B_0x1" description="Completed" start="0x1" />
+      </BitField>
+      <BitField name="RWEIF" description="Read or write error interrupt flag" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No read or write error detected" start="0x0" />
+        <Enum name="B_0x1" description="Read or write error detected" start="0x1" />
+      </BitField>
+      <BitField name="KEIF" description="Key error interrupt flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No key error detected" start="0x0" />
+        <Enum name="B_0x1" description="Key information failed to load into key registers or the key register use is forbidden" start="0x1" />
+      </BitField>
+      <BitField name="RNGEIF" description="RNG error interrupt flag" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RNG bus is functional" start="0x0" />
+        <Enum name="B_0x1" description="Error detected on RNG bus interface (random seed fetching error)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAES_ICR" description="SAES interrupt clear register" start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCF" description="Computation complete flag clear" start="0" size="1" access="WriteOnly" />
+      <BitField name="RWEIF" description="Read or write error interrupt flag clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="KEIF" description="Key error interrupt flag clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="RNGEIF" description="RNG error interrupt flag clear" start="3" size="1" access="WriteOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI1" description="Serial audio interface" start="0x42005800">
+    <Register name="SAI_GCR" description="SAI global configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCIN" description="Synchronization outputs" start="0" size="2" access="Read/Write" />
+      <BitField name="SYNCOUT" description="Synchronization outputs" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF" start="0x0" />
+        <Enum name="B_0x1" description="Block A used for further synchronization for others SAI" start="0x1" />
+        <Enum name="B_0x2" description="Block B used for further synchronization for others SAI" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR1" description="SAI configuration register 1" start="+0x004" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR2" description="SAI configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AFRCR" description="SAI frame configuration register" start="+0x00C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASLOTR" description="SAI slot register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AIM" description="SAI interrupt mask register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASR" description="SAI status register" start="+0x018" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACLRFR" description="SAI clear flag register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_ADR" description="SAI data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BCR1" description="SAI configuration register 1" start="+0x024" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful config uration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCR2" description="SAI configuration register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BFRCR" description="SAI frame configuration register" start="+0x02C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSLOTR" description="SAI slot register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BIM" description="SAI interrupt mask register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSR" description="SAI status register" start="+0x038" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCLRFR" description="SAI clear flag register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_BDR" description="SAI data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_PDMCR" description="SAI PDM control register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PDM interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="PDM interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Configuration with 2 microphones" start="0x0" />
+        <Enum name="B_0x1" description="Configuration with 4 microphones" start="0x1" />
+        <Enum name="B_0x2" description="Configuration with 6 microphones" start="0x2" />
+        <Enum name="B_0x3" description="Configuration with 8 microphones" start="0x3" />
+      </BitField>
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK1 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK1 clock enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK2 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK2 clock enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_PDMDLY" description="SAI PDM delay register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 of Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI1_S" description="Serial audio interface" start="0x52005800">
+    <Register name="SAI_GCR" description="SAI global configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCIN" description="Synchronization outputs" start="0" size="2" access="Read/Write" />
+      <BitField name="SYNCOUT" description="Synchronization outputs" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF" start="0x0" />
+        <Enum name="B_0x1" description="Block A used for further synchronization for others SAI" start="0x1" />
+        <Enum name="B_0x2" description="Block B used for further synchronization for others SAI" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR1" description="SAI configuration register 1" start="+0x004" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR2" description="SAI configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AFRCR" description="SAI frame configuration register" start="+0x00C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASLOTR" description="SAI slot register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AIM" description="SAI interrupt mask register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASR" description="SAI status register" start="+0x018" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACLRFR" description="SAI clear flag register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_ADR" description="SAI data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BCR1" description="SAI configuration register 1" start="+0x024" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful config uration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCR2" description="SAI configuration register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BFRCR" description="SAI frame configuration register" start="+0x02C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSLOTR" description="SAI slot register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BIM" description="SAI interrupt mask register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSR" description="SAI status register" start="+0x038" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCLRFR" description="SAI clear flag register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_BDR" description="SAI data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_PDMCR" description="SAI PDM control register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PDM interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="PDM interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Configuration with 2 microphones" start="0x0" />
+        <Enum name="B_0x1" description="Configuration with 4 microphones" start="0x1" />
+        <Enum name="B_0x2" description="Configuration with 6 microphones" start="0x2" />
+        <Enum name="B_0x3" description="Configuration with 8 microphones" start="0x3" />
+      </BitField>
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK1 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK1 clock enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK2 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK2 clock enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_PDMDLY" description="SAI PDM delay register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 of Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI2" description="Serial audio interface" start="0x42005C00">
+    <Register name="SAI_GCR" description="SAI global configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCIN" description="Synchronization outputs" start="0" size="2" access="Read/Write" />
+      <BitField name="SYNCOUT" description="Synchronization outputs" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF" start="0x0" />
+        <Enum name="B_0x1" description="Block A used for further synchronization for others SAI" start="0x1" />
+        <Enum name="B_0x2" description="Block B used for further synchronization for others SAI" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR1" description="SAI configuration register 1" start="+0x004" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR2" description="SAI configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AFRCR" description="SAI frame configuration register" start="+0x00C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASLOTR" description="SAI slot register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AIM" description="SAI interrupt mask register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASR" description="SAI status register" start="+0x018" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACLRFR" description="SAI clear flag register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_ADR" description="SAI data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BCR1" description="SAI configuration register 1" start="+0x024" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful config uration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCR2" description="SAI configuration register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BFRCR" description="SAI frame configuration register" start="+0x02C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSLOTR" description="SAI slot register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BIM" description="SAI interrupt mask register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSR" description="SAI status register" start="+0x038" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCLRFR" description="SAI clear flag register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_BDR" description="SAI data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_PDMCR" description="SAI PDM control register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PDM interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="PDM interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Configuration with 2 microphones" start="0x0" />
+        <Enum name="B_0x1" description="Configuration with 4 microphones" start="0x1" />
+        <Enum name="B_0x2" description="Configuration with 6 microphones" start="0x2" />
+        <Enum name="B_0x3" description="Configuration with 8 microphones" start="0x3" />
+      </BitField>
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK1 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK1 clock enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK2 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK2 clock enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_PDMDLY" description="SAI PDM delay register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 of Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI2_S" description="Serial audio interface" start="0x52005C00">
+    <Register name="SAI_GCR" description="SAI global configuration register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCIN" description="Synchronization outputs" start="0" size="2" access="Read/Write" />
+      <BitField name="SYNCOUT" description="Synchronization outputs" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF" start="0x0" />
+        <Enum name="B_0x1" description="Block A used for further synchronization for others SAI" start="0x1" />
+        <Enum name="B_0x2" description="Block B used for further synchronization for others SAI" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR1" description="SAI configuration register 1" start="+0x004" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACR2" description="SAI configuration register 2" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AFRCR" description="SAI frame configuration register" start="+0x00C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASLOTR" description="SAI slot register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_AIM" description="SAI interrupt mask register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ASR" description="SAI status register" start="+0x018" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_ACLRFR" description="SAI clear flag register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_ADR" description="SAI data register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BCR1" description="SAI configuration register 1" start="+0x024" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Master transmitter" start="0x0" />
+        <Enum name="B_0x1" description="Master receiver" start="0x1" />
+        <Enum name="B_0x2" description="Slave transmitter" start="0x2" />
+        <Enum name="B_0x3" description="Slave receiver" start="0x3" />
+      </BitField>
+      <BitField name="PRTCFG" description="Protocol configuration" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Free protocol. Free protocol enables to use the powerful config uration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register." start="0x0" />
+        <Enum name="B_0x1" description="SPDIF protocol" start="0x1" />
+        <Enum name="B_0x2" description="AC'97 protocol" start="0x2" />
+      </BitField>
+      <BitField name="DS" description="Data size" start="5" size="3" access="Read/Write">
+        <Enum name="B_0x2" description="8 bits" start="0x2" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x4" description="16 bits" start="0x4" />
+        <Enum name="B_0x5" description="20 bits" start="0x5" />
+        <Enum name="B_0x6" description="24 bits" start="0x6" />
+        <Enum name="B_0x7" description="32 bits" start="0x7" />
+      </BitField>
+      <BitField name="LSBFIRST" description="Least significant bit first" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data are transferred with MSB first" start="0x0" />
+        <Enum name="B_0x1" description="Data are transferred with LSB first" start="0x1" />
+      </BitField>
+      <BitField name="CKSTR" description="Clock strobing edge" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge." start="0x0" />
+        <Enum name="B_0x1" description="Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge." start="0x1" />
+      </BitField>
+      <BitField name="SYNCEN" description="Synchronization enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="audio subblock in asynchronous mode." start="0x0" />
+        <Enum name="B_0x1" description="audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode" start="0x1" />
+        <Enum name="B_0x2" description="audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode." start="0x2" />
+      </BitField>
+      <BitField name="MONO" description="Mono mode" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stereo mode" start="0x0" />
+        <Enum name="B_0x1" description="Mono mode." start="0x1" />
+      </BitField>
+      <BitField name="OUTDRIV" description="Output drive" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Audio block output driven when SAIEN is set" start="0x0" />
+        <Enum name="B_0x1" description="Audio block output driven immediately after the setting of this bit." start="0x1" />
+      </BitField>
+      <BitField name="SAIEN" description="Audio block enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI audio block disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI audio block enabled." start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="NODIV" description="No divider" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512" start="0x0" />
+        <Enum name="B_0x1" description="the ratio between the Master clock generator and frame synchronization depends on FRL[7:0]" start="0x1" />
+      </BitField>
+      <BitField name="MCKDIV" description="Master clock divider" start="20" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="Divides by 1 the kernel clock input (sai_x_ker_ck)." start="0x0" />
+      </BitField>
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 256" start="0x0" />
+        <Enum name="B_0x1" description="Master clock frequency = Fless thansub&gt;FSless than/sub&gt; x 512" start="0x1" />
+      </BitField>
+      <BitField name="MCKEN" description="Master clock generation enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The master clock is not generated" start="0x0" />
+        <Enum name="B_0x1" description="The master clock is generated independently of SAIEN bit" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCR2" description="SAI configuration register 2" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. " start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
+        <Enum name="B_0x1" description=" FIFO" start="0x1" />
+        <Enum name="B_0x2" description=" FIFO" start="0x2" />
+        <Enum name="B_0x3" description=" FIFO" start="0x3" />
+        <Enum name="B_0x4" description="FIFO full" start="0x4" />
+      </BitField>
+      <BitField name="FFLUSH" description="FIFO flush." start="3" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No FIFO flush." start="0x0" />
+        <Enum name="B_0x1" description="FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled" start="0x1" />
+      </BitField>
+      <BitField name="TRIS" description="Tristate management on data line. " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SD output line is still driven by the SAI when a slot is inactive." start="0x0" />
+        <Enum name="B_0x1" description="SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive." start="0x1" />
+      </BitField>
+      <BitField name="MUTE" description="Mute." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Mute mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="MUTEVAL" description="Mute value." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bit value 0 is sent during the mute mode." start="0x0" />
+        <Enum name="B_0x1" description="Last values are sent during the mute mode." start="0x1" />
+      </BitField>
+      <BitField name="MUTECNT" description="Mute counter." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="1's complement representation." start="0x0" />
+        <Enum name="B_0x1" description="2's complement representation." start="0x1" />
+      </BitField>
+      <BitField name="COMP" description="Companding mode. " start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No companding algorithm" start="0x0" />
+        <Enum name="B_0x2" description=" -Law algorithm" start="0x2" />
+        <Enum name="B_0x3" description="A-Law algorithm" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BFRCR" description="SAI frame configuration register" start="+0x02C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. " start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. " start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition." start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="FS signal is a start frame signal" start="0x0" />
+        <Enum name="B_0x1" description="FS signal is a start of frame signal + channel side identification" start="0x1" />
+      </BitField>
+      <BitField name="FSPOL" description="Frame synchronization polarity. " start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is active low (falling edge)" start="0x0" />
+        <Enum name="B_0x1" description="FS is active high (rising edge)" start="0x1" />
+      </BitField>
+      <BitField name="FSOFF" description="Frame synchronization offset. " start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FS is asserted on the first bit of the slot 0." start="0x0" />
+        <Enum name="B_0x1" description="FS is asserted one bit before the first bit of the slot 0." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSLOTR" description="SAI slot register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset " start="0" size="5" access="Read/Write" />
+      <BitField name="SLOTSZ" description="Slot size" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)." start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+        <Enum name="B_0x2" description="32-bit" start="0x2" />
+      </BitField>
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. " start="8" size="4" access="Read/Write" />
+      <BitField name="SLOTEN" description="Slot enable. " start="16" size="16" access="Read/Write">
+        <Enum name="B_0x0" description="Inactive slot." start="0x0" />
+        <Enum name="B_0x1" description="Active slot." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BIM" description="SAI interrupt mask register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="FREQIE" description="FIFO request interrupt enable." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC'97). " start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interrupt is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BSR" description="SAI status register" start="+0x038" size="4" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun error." start="0x0" />
+        <Enum name="B_0x1" description="Overrun/underrun error detection." start="0x1" />
+      </BitField>
+      <BitField name="MUTEDET" description="Mute detection." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No MUTE detection on the SD input line" start="0x0" />
+        <Enum name="B_0x1" description="MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame" start="0x1" />
+      </BitField>
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. " start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Clock configuration is correct" start="0x0" />
+        <Enum name="B_0x1" description="Clock configuration does not respect the rule concerning the frame length specification defined in Section 59.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)" start="0x1" />
+      </BitField>
+      <BitField name="FREQ" description="FIFO request. " start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No FIFO request." start="0x0" />
+        <Enum name="B_0x1" description="FIFO request to read or to write the SAI_xDR." start="0x1" />
+      </BitField>
+      <BitField name="CNRDY" description="Codec not ready. " start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="External AC'97 Codec is ready" start="0x0" />
+        <Enum name="B_0x1" description="External AC'97 Codec is not ready" start="0x1" />
+      </BitField>
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection." start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is detected earlier than expected." start="0x1" />
+      </BitField>
+      <BitField name="LFSDET" description="Late frame synchronization detection." start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error." start="0x0" />
+        <Enum name="B_0x1" description="Frame synchronization signal is not present at the right time." start="0x1" />
+      </BitField>
+      <BitField name="FLVL" description="FIFO level threshold. " start="16" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="FIFO empty (transmitter and receiver modes)" start="0x0" />
+        <Enum name="B_0x1" description="FIFO less than or equal to 1/4 but not empty (transmitter mode), FIFO less than 1/4 but not empty (receiver mode)" start="0x1" />
+        <Enum name="B_0x2" description="1/4 less than FIFO less than or equal to 1/2 (transmitter mode), 1/4 less than or equal to FIFO less than 1/2 (receiver mode)" start="0x2" />
+        <Enum name="B_0x3" description="1/2 less than FIFO less than or equal to 3/4 (transmitter mode), 1/2 less than or equal to FIFO less than 3/4 (receiver mode)" start="0x3" />
+        <Enum name="B_0x4" description="3/4 less than FIFO but not full (transmitter mode), 3/4 less than or equal to FIFO but not full (receiver mode)" start="0x4" />
+        <Enum name="B_0x5" description="FIFO full (transmitter and receiver modes)" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="SAI_BCLRFR" description="SAI clear flag register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun." start="0" size="1" access="WriteOnly" />
+      <BitField name="CMUTEDET" description="Mute detection flag. " start="1" size="1" access="WriteOnly" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. " start="2" size="1" access="WriteOnly" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. " start="4" size="1" access="WriteOnly" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. " start="5" size="1" access="WriteOnly" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. " start="6" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SAI_BDR" description="SAI data register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data " start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SAI_PDMCR" description="SAI PDM control register" start="+0x0044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PDM interface disabled" start="0x0" />
+        <Enum name="B_0x1" description="PDM interface enabled" start="0x1" />
+      </BitField>
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Configuration with 2 microphones" start="0x0" />
+        <Enum name="B_0x1" description="Configuration with 4 microphones" start="0x1" />
+        <Enum name="B_0x2" description="Configuration with 6 microphones" start="0x2" />
+        <Enum name="B_0x3" description="Configuration with 8 microphones" start="0x3" />
+      </BitField>
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK1 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK1 clock enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SAI_CK2 clock disabled" start="0x0" />
+        <Enum name="B_0x1" description="SAI_CK2 clock enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SAI_PDMDLY" description="SAI PDM delay register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 of Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No delay" start="0x0" />
+        <Enum name="B_0x1" description="Delay of 1 Tless thansub&gt;SAI_CK less than/sub&gt;period" start="0x1" />
+        <Enum name="B_0x2" description="Delay of 2 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x2" />
+        <Enum name="B_0x7" description="Delay of 7 Tless thansub&gt;SAI_CK less than/sub&gt;periods" start="0x7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC1" description="Secure digital input/output MultiMediaCard interface" start="0x48027000">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low." start="0x0" />
+        <Enum name="B_0x2" description="Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low." start="0x2" />
+        <Enum name="B_0x3" description="Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation." start="0x3" />
+      </BitField>
+      <BitField name="VSWITCH" description="Voltage switch sequence start" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch sequence not started and not active." start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch sequence started or active." start="0x1" />
+      </BitField>
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock kept unchanged after successfully received command response." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK clock stopped after successfully received command response." start="0x1" />
+      </BitField>
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage transceiver IOs driven as output when direction signal is low." start="0x0" />
+        <Enum name="B_0x1" description="Voltage transceiver IOs driven as output when direction signal is high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_CLKCR" description="SDMMC clock control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x000" description="SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR)" start="0x000" />
+        <Enum name="B_0x001" description="SDMMC_CK frequency = sdmmc_ker_ck / 2" start="0x001" />
+        <Enum name="B_0x002" description="SDMMC_CK frequency = sdmmc_ker_ck / 4" start="0x002" />
+        <Enum name="B_0x080" description="SDMMC_CK frequency = sdmmc_ker_ck / 256" start="0x080" />
+        <Enum name="B_0x3FF" description="SDMMC_CK frequency = sdmmc_ker_ck / 2046" start="0x3FF" />
+      </BitField>
+      <BitField name="PWRSAV" description="Power saving configuration bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock is always enabled" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK is only enabled when the bus is active" start="0x1" />
+      </BitField>
+      <BitField name="WIDBUS" description="Wide bus mode enable bit" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR)" start="0x0" />
+        <Enum name="B_0x1" description="4-bit wide bus mode: SDMMC_D[3:0] used" start="0x1" />
+        <Enum name="B_0x2" description="8-bit wide bus mode: SDMMC_D[7:0] used" start="0x2" />
+      </BitField>
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and command" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x0" />
+        <Enum name="B_0x1" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x1" />
+      </BitField>
+      <BitField name="HWFC_EN" description="Hardware flow control enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware flow control is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Hardware flow control is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DDR" description="Data rate signaling selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDR Single data rate signaling" start="0x0" />
+        <Enum name="B_0x1" description="DDR double data rate signaling" start="0x1" />
+      </BitField>
+      <BitField name="BUSSPEED" description="Bus speed for selection of SDMMC operating modes" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected" start="0x0" />
+        <Enum name="B_0x1" description="SDR50, DDR50, SDR104, HS200 bus speed mode selected." start="0x1" />
+      </BitField>
+      <BitField name="SELCLKRX" description="Receive clock selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="sdmmc_io_in_ck selected as receive clock" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CKIN feedback clock selected as receive clock" start="0x1" />
+        <Enum name="B_0x2" description="sdmmc_fb_ck tuned feedback clock selected as receive clock." start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ARGR" description="SDMMC argument register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="SDMMC command register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index" start="0" size="6" access="Read/Write" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM" start="6" size="1" access="Read/Write" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" start="7" size="1" access="Read/Write" />
+      <BitField name="WAITRESP" description="Wait for response bits" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No response, expect CMDSENT flag" start="0x0" />
+        <Enum name="B_0x1" description="Short response, expect CMDREND or CCRCFAIL flag" start="0x1" />
+        <Enum name="B_0x2" description="Short response, expect CMDREND flag (No CRC)" start="0x2" />
+        <Enum name="B_0x3" description="Long response, expect CMDREND or CCRCFAIL flag" start="0x3" />
+      </BitField>
+      <BitField name="WAITINT" description="CPSM waits for interrupt request" start="10" size="1" access="Read/Write" />
+      <BitField name="WAITPEND" description="CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" start="11" size="1" access="Read/Write" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) enable bit" start="12" size="1" access="Read/Write" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM" start="13" size="1" access="Read/Write" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal boot mode procedure selected" start="0x0" />
+        <Enum name="B_0x1" description="Alternative boot mode procedure selected." start="0x1" />
+      </BitField>
+      <BitField name="BOOTEN" description="Enable boot mode procedure" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot mode procedure disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boot mode procedure enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="SDMMC response 1 register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="SDMMC response 2 register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="SDMMC response 3 register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="SDMMC response 4 register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="SDMMC data timer register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="SDMMC data length register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="SDMMC data control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not start data transfer without CPSM data transfer command." start="0x0" />
+        <Enum name="B_0x1" description="Start data transfer without CPSM data transfer command." start="0x1" />
+      </BitField>
+      <BitField name="DTDIR" description="Data transfer direction selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="From host to card." start="0x0" />
+        <Enum name="B_0x1" description="From card to host." start="0x1" />
+      </BitField>
+      <BitField name="DTMODE" description="Data transfer mode selection" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Block data transfer ending on block count." start="0x0" />
+        <Enum name="B_0x1" description="SDIO multibyte data transfer." start="0x1" />
+        <Enum name="B_0x2" description="e MMC Stream data transfer. (WIDBUS must select 1-bit wide bus mode)" start="0x2" />
+        <Enum name="B_0x3" description="Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers)." start="0x3" />
+      </BitField>
+      <BitField name="DBLOCKSIZE" description="Data block size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Block length = 2less thansup&gt;0less than/sup&gt; = 1 byte" start="0x0" />
+        <Enum name="B_0x1" description="Block length = 2less thansup&gt;1less than/sup&gt; = 2 bytes" start="0x1" />
+        <Enum name="B_0x2" description="Block length = 2less thansup&gt;2 less than/sup&gt;= 4 bytes" start="0x2" />
+        <Enum name="B_0x3" description="Block length = 2less thansup&gt;3less than/sup&gt; = 8 bytes" start="0x3" />
+        <Enum name="B_0x4" description="Block length = 2less thansup&gt;4less than/sup&gt; = 16 bytes" start="0x4" />
+        <Enum name="B_0x5" description="Block length = 2less thansup&gt;5less than/sup&gt; = 32 bytes" start="0x5" />
+        <Enum name="B_0x6" description="Block length = 2less thansup&gt;6less than/sup&gt; = 64 bytes" start="0x6" />
+        <Enum name="B_0x7" description="Block length = 2less thansup&gt;7less than/sup&gt; = 128 bytes" start="0x7" />
+        <Enum name="B_0x8" description="Block length = 2less thansup&gt;8less than/sup&gt; = 256 bytes" start="0x8" />
+        <Enum name="B_0x9" description="Block length = 2less thansup&gt;9less than/sup&gt; = 512 bytes" start="0x9" />
+        <Enum name="B_0xA" description="Block length = 2less thansup&gt;10less than/sup&gt; = 1024 bytes" start="0xA" />
+        <Enum name="B_0xB" description="Block length = 2less thansup&gt;11less than/sup&gt; = 2048 bytes" start="0xB" />
+        <Enum name="B_0xC" description="Block length = 2less thansup&gt;12less than/sup&gt; = 4096 bytes" start="0xC" />
+        <Enum name="B_0xD" description="Block length = 2less thansup&gt;13less than/sup&gt; = 8192 bytes" start="0xD" />
+        <Enum name="B_0xE" description="Block length = 2less thansup&gt;14less than/sup&gt; = 16384 bytes" start="0xE" />
+      </BitField>
+      <BitField name="RWSTART" description="Read Wait start" start="8" size="1" access="Read/Write" />
+      <BitField name="RWSTOP" description="Read Wait stop" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Read Wait stop." start="0x0" />
+        <Enum name="B_0x1" description="Enable for Read Wait stop when DPSM is in the R_W state." start="0x1" />
+      </BitField>
+      <BitField name="RWMOD" description="Read Wait mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read Wait control using SDMMC_D2" start="0x0" />
+        <Enum name="B_0x1" description="Read Wait control stopping SDMMC_CK" start="0x1" />
+      </BitField>
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions" start="11" size="1" access="Read/Write" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot acknowledgment disabled, not expected to be received" start="0x0" />
+        <Enum name="B_0x1" description="Boot acknowledgment enabled, expected to be received" start="0x1" />
+      </BitField>
+      <BitField name="FIFORST" description="FIFO reset, flushes any remaining data" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO not affected." start="0x0" />
+        <Enum name="B_0x1" description="Flush any remaining data and reset the FIFO pointers. This bit is automatically cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_DCNTR" description="SDMMC data counter register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value" start="0" size="25" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_STAR" description="SDMMC status register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed)" start="0" size="1" access="ReadOnly" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CTIMEOUT" description="Command response timeout" start="2" size="1" access="ReadOnly" />
+      <BitField name="DTIMEOUT" description="Data timeout" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error (masked by hardware when IDMA is enabled)" start="5" size="1" access="ReadOnly" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC)" start="6" size="1" access="ReadOnly" />
+      <BitField name="CMDSENT" description="Command sent (no response required)" start="7" size="1" access="ReadOnly" />
+      <BitField name="DATAEND" description="Data transfer ended correctly" start="8" size="1" access="ReadOnly" />
+      <BitField name="DHOLD" description="Data transfer Hold" start="9" size="1" access="ReadOnly" />
+      <BitField name="DBCKEND" description="Data block sent/received" start="10" size="1" access="ReadOnly" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12" start="11" size="1" access="ReadOnly" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state" start="12" size="1" access="ReadOnly" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full" start="15" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full" start="16" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOF" description="Receive FIFO full" start="17" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty" start="18" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty" start="19" size="1" access="ReadOnly" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card signals not busy on SDMMC_D0." start="0x0" />
+        <Enum name="B_0x1" description="card signals busy on SDMMC_D0." start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card SDMMC_D0 signal does NOT signal change from busy to not busy." start="0x0" />
+        <Enum name="B_0x1" description="card SDMMC_D0 signal changed from busy to NOT busy." start="0x1" />
+      </BitField>
+      <BitField name="SDIOIT" description="SDIO interrupt received" start="22" size="1" access="ReadOnly" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail)" start="23" size="1" access="ReadOnly" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout" start="24" size="1" access="ReadOnly" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion" start="25" size="1" access="ReadOnly" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDMATE" description="IDMA transfer error" start="27" size="1" access="ReadOnly" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete" start="28" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_ICR" description="SDMMC interrupt clear register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXUNDERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="TXUNDERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXOVERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="RXOVERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDREND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDREND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDSENT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDSENT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDC" description="DATAEND flag clear bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DATAEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DATAEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDC" description="DHOLD flag clear bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DHOLD not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DHOLD cleared" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBCKEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DBCKEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DABORTC" description="DABORT flag clear bit" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DABORT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DABORT cleared" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END not cleared" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END cleared" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIOIT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="SDIOIT cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDC" description="VSWEND flag clear bit" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSWEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="VSWEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKSTOP not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CKSTOP cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMATE not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMATE cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMABTC not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMABTC cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_MASKR" description="SDMMC mask register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO underrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO underrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO overrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO overrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command response received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="command Response received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command sent interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command sent interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDIE" description="Data end interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDIE" description="Data hold interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data hold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data hold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data block end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data block end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data transfer abort interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data transfer abort interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO half empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO half empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO half full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO half full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIO Mode interrupt received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDIO Mode interrupt received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment Fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment Fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch critical timing section completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch critical timing section completion interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage Switch clock stopped interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage Switch clock stopped interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA buffer transfer complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA buffer transfer complete interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="SDMMC acknowledgment timer register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOTHRR" description="SDMMC data FIFO threshold register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THR" description="FIFO threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="threshold = 0 byte (no threshold)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="SDMMC DMA control register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABMODE" description="Buffer mode selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single buffer mode." start="0x0" />
+        <Enum name="B_0x1" description="Linked list mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="SDMMC IDMA buffer size register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of bytes per buffer" start="6" size="11" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMABASER" description="SDMMC IDMA buffer base address register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE" description="Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMALAR" description="SDMMC IDMA linked list address register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMALA" description="Word aligned linked list item address offset" start="2" size="14" access="Read/Write" />
+      <BitField name="ABR" description="Acknowledge linked list buffer ready" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated)." start="0x0" />
+        <Enum name="B_0x1" description="Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA." start="0x1" />
+      </BitField>
+      <BitField name="ULS" description="Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMABSIZER is not to be updated from next linked list table." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMABSIZER is to be updated from next linked list table." start="0x1" />
+      </BitField>
+      <BitField name="ULA" description="Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMALAR is not to be updated, last linked list item." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMALAR is to be updated from linked list table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABAR" description="SDMMC IDMA linked list memory base register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABA" description="Word aligned Linked list memory base address" start="2" size="30" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR0" description="SDMMC data FIFO registers 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR1" description="SDMMC data FIFO registers 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR2" description="SDMMC data FIFO registers 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR3" description="SDMMC data FIFO registers 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR4" description="SDMMC data FIFO registers 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR5" description="SDMMC data FIFO registers 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR6" description="SDMMC data FIFO registers 6" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR7" description="SDMMC data FIFO registers 7" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR8" description="SDMMC data FIFO registers 8" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR9" description="SDMMC data FIFO registers 9" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR10" description="SDMMC data FIFO registers 10" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR11" description="SDMMC data FIFO registers 11" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR12" description="SDMMC data FIFO registers 12" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR13" description="SDMMC data FIFO registers 13" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR14" description="SDMMC data FIFO registers 14" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR15" description="SDMMC data FIFO registers 15" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC1_S" description="Secure digital input/output MultiMediaCard interface" start="0x58027000">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low." start="0x0" />
+        <Enum name="B_0x2" description="Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low." start="0x2" />
+        <Enum name="B_0x3" description="Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation." start="0x3" />
+      </BitField>
+      <BitField name="VSWITCH" description="Voltage switch sequence start" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch sequence not started and not active." start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch sequence started or active." start="0x1" />
+      </BitField>
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock kept unchanged after successfully received command response." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK clock stopped after successfully received command response." start="0x1" />
+      </BitField>
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage transceiver IOs driven as output when direction signal is low." start="0x0" />
+        <Enum name="B_0x1" description="Voltage transceiver IOs driven as output when direction signal is high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_CLKCR" description="SDMMC clock control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x000" description="SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR)" start="0x000" />
+        <Enum name="B_0x001" description="SDMMC_CK frequency = sdmmc_ker_ck / 2" start="0x001" />
+        <Enum name="B_0x002" description="SDMMC_CK frequency = sdmmc_ker_ck / 4" start="0x002" />
+        <Enum name="B_0x080" description="SDMMC_CK frequency = sdmmc_ker_ck / 256" start="0x080" />
+        <Enum name="B_0x3FF" description="SDMMC_CK frequency = sdmmc_ker_ck / 2046" start="0x3FF" />
+      </BitField>
+      <BitField name="PWRSAV" description="Power saving configuration bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock is always enabled" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK is only enabled when the bus is active" start="0x1" />
+      </BitField>
+      <BitField name="WIDBUS" description="Wide bus mode enable bit" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR)" start="0x0" />
+        <Enum name="B_0x1" description="4-bit wide bus mode: SDMMC_D[3:0] used" start="0x1" />
+        <Enum name="B_0x2" description="8-bit wide bus mode: SDMMC_D[7:0] used" start="0x2" />
+      </BitField>
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and command" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x0" />
+        <Enum name="B_0x1" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x1" />
+      </BitField>
+      <BitField name="HWFC_EN" description="Hardware flow control enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware flow control is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Hardware flow control is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DDR" description="Data rate signaling selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDR Single data rate signaling" start="0x0" />
+        <Enum name="B_0x1" description="DDR double data rate signaling" start="0x1" />
+      </BitField>
+      <BitField name="BUSSPEED" description="Bus speed for selection of SDMMC operating modes" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected" start="0x0" />
+        <Enum name="B_0x1" description="SDR50, DDR50, SDR104, HS200 bus speed mode selected." start="0x1" />
+      </BitField>
+      <BitField name="SELCLKRX" description="Receive clock selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="sdmmc_io_in_ck selected as receive clock" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CKIN feedback clock selected as receive clock" start="0x1" />
+        <Enum name="B_0x2" description="sdmmc_fb_ck tuned feedback clock selected as receive clock." start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ARGR" description="SDMMC argument register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="SDMMC command register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index" start="0" size="6" access="Read/Write" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM" start="6" size="1" access="Read/Write" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" start="7" size="1" access="Read/Write" />
+      <BitField name="WAITRESP" description="Wait for response bits" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No response, expect CMDSENT flag" start="0x0" />
+        <Enum name="B_0x1" description="Short response, expect CMDREND or CCRCFAIL flag" start="0x1" />
+        <Enum name="B_0x2" description="Short response, expect CMDREND flag (No CRC)" start="0x2" />
+        <Enum name="B_0x3" description="Long response, expect CMDREND or CCRCFAIL flag" start="0x3" />
+      </BitField>
+      <BitField name="WAITINT" description="CPSM waits for interrupt request" start="10" size="1" access="Read/Write" />
+      <BitField name="WAITPEND" description="CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" start="11" size="1" access="Read/Write" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) enable bit" start="12" size="1" access="Read/Write" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM" start="13" size="1" access="Read/Write" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal boot mode procedure selected" start="0x0" />
+        <Enum name="B_0x1" description="Alternative boot mode procedure selected." start="0x1" />
+      </BitField>
+      <BitField name="BOOTEN" description="Enable boot mode procedure" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot mode procedure disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boot mode procedure enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="SDMMC response 1 register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="SDMMC response 2 register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="SDMMC response 3 register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="SDMMC response 4 register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="SDMMC data timer register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="SDMMC data length register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="SDMMC data control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not start data transfer without CPSM data transfer command." start="0x0" />
+        <Enum name="B_0x1" description="Start data transfer without CPSM data transfer command." start="0x1" />
+      </BitField>
+      <BitField name="DTDIR" description="Data transfer direction selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="From host to card." start="0x0" />
+        <Enum name="B_0x1" description="From card to host." start="0x1" />
+      </BitField>
+      <BitField name="DTMODE" description="Data transfer mode selection" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Block data transfer ending on block count." start="0x0" />
+        <Enum name="B_0x1" description="SDIO multibyte data transfer." start="0x1" />
+        <Enum name="B_0x2" description="e MMC Stream data transfer. (WIDBUS must select 1-bit wide bus mode)" start="0x2" />
+        <Enum name="B_0x3" description="Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers)." start="0x3" />
+      </BitField>
+      <BitField name="DBLOCKSIZE" description="Data block size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Block length = 2less thansup&gt;0less than/sup&gt; = 1 byte" start="0x0" />
+        <Enum name="B_0x1" description="Block length = 2less thansup&gt;1less than/sup&gt; = 2 bytes" start="0x1" />
+        <Enum name="B_0x2" description="Block length = 2less thansup&gt;2 less than/sup&gt;= 4 bytes" start="0x2" />
+        <Enum name="B_0x3" description="Block length = 2less thansup&gt;3less than/sup&gt; = 8 bytes" start="0x3" />
+        <Enum name="B_0x4" description="Block length = 2less thansup&gt;4less than/sup&gt; = 16 bytes" start="0x4" />
+        <Enum name="B_0x5" description="Block length = 2less thansup&gt;5less than/sup&gt; = 32 bytes" start="0x5" />
+        <Enum name="B_0x6" description="Block length = 2less thansup&gt;6less than/sup&gt; = 64 bytes" start="0x6" />
+        <Enum name="B_0x7" description="Block length = 2less thansup&gt;7less than/sup&gt; = 128 bytes" start="0x7" />
+        <Enum name="B_0x8" description="Block length = 2less thansup&gt;8less than/sup&gt; = 256 bytes" start="0x8" />
+        <Enum name="B_0x9" description="Block length = 2less thansup&gt;9less than/sup&gt; = 512 bytes" start="0x9" />
+        <Enum name="B_0xA" description="Block length = 2less thansup&gt;10less than/sup&gt; = 1024 bytes" start="0xA" />
+        <Enum name="B_0xB" description="Block length = 2less thansup&gt;11less than/sup&gt; = 2048 bytes" start="0xB" />
+        <Enum name="B_0xC" description="Block length = 2less thansup&gt;12less than/sup&gt; = 4096 bytes" start="0xC" />
+        <Enum name="B_0xD" description="Block length = 2less thansup&gt;13less than/sup&gt; = 8192 bytes" start="0xD" />
+        <Enum name="B_0xE" description="Block length = 2less thansup&gt;14less than/sup&gt; = 16384 bytes" start="0xE" />
+      </BitField>
+      <BitField name="RWSTART" description="Read Wait start" start="8" size="1" access="Read/Write" />
+      <BitField name="RWSTOP" description="Read Wait stop" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Read Wait stop." start="0x0" />
+        <Enum name="B_0x1" description="Enable for Read Wait stop when DPSM is in the R_W state." start="0x1" />
+      </BitField>
+      <BitField name="RWMOD" description="Read Wait mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read Wait control using SDMMC_D2" start="0x0" />
+        <Enum name="B_0x1" description="Read Wait control stopping SDMMC_CK" start="0x1" />
+      </BitField>
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions" start="11" size="1" access="Read/Write" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot acknowledgment disabled, not expected to be received" start="0x0" />
+        <Enum name="B_0x1" description="Boot acknowledgment enabled, expected to be received" start="0x1" />
+      </BitField>
+      <BitField name="FIFORST" description="FIFO reset, flushes any remaining data" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO not affected." start="0x0" />
+        <Enum name="B_0x1" description="Flush any remaining data and reset the FIFO pointers. This bit is automatically cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_DCNTR" description="SDMMC data counter register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value" start="0" size="25" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_STAR" description="SDMMC status register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed)" start="0" size="1" access="ReadOnly" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CTIMEOUT" description="Command response timeout" start="2" size="1" access="ReadOnly" />
+      <BitField name="DTIMEOUT" description="Data timeout" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error (masked by hardware when IDMA is enabled)" start="5" size="1" access="ReadOnly" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC)" start="6" size="1" access="ReadOnly" />
+      <BitField name="CMDSENT" description="Command sent (no response required)" start="7" size="1" access="ReadOnly" />
+      <BitField name="DATAEND" description="Data transfer ended correctly" start="8" size="1" access="ReadOnly" />
+      <BitField name="DHOLD" description="Data transfer Hold" start="9" size="1" access="ReadOnly" />
+      <BitField name="DBCKEND" description="Data block sent/received" start="10" size="1" access="ReadOnly" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12" start="11" size="1" access="ReadOnly" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state" start="12" size="1" access="ReadOnly" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full" start="15" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full" start="16" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOF" description="Receive FIFO full" start="17" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty" start="18" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty" start="19" size="1" access="ReadOnly" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card signals not busy on SDMMC_D0." start="0x0" />
+        <Enum name="B_0x1" description="card signals busy on SDMMC_D0." start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card SDMMC_D0 signal does NOT signal change from busy to not busy." start="0x0" />
+        <Enum name="B_0x1" description="card SDMMC_D0 signal changed from busy to NOT busy." start="0x1" />
+      </BitField>
+      <BitField name="SDIOIT" description="SDIO interrupt received" start="22" size="1" access="ReadOnly" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail)" start="23" size="1" access="ReadOnly" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout" start="24" size="1" access="ReadOnly" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion" start="25" size="1" access="ReadOnly" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDMATE" description="IDMA transfer error" start="27" size="1" access="ReadOnly" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete" start="28" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_ICR" description="SDMMC interrupt clear register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXUNDERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="TXUNDERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXOVERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="RXOVERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDREND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDREND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDSENT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDSENT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDC" description="DATAEND flag clear bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DATAEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DATAEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDC" description="DHOLD flag clear bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DHOLD not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DHOLD cleared" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBCKEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DBCKEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DABORTC" description="DABORT flag clear bit" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DABORT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DABORT cleared" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END not cleared" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END cleared" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIOIT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="SDIOIT cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDC" description="VSWEND flag clear bit" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSWEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="VSWEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKSTOP not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CKSTOP cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMATE not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMATE cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMABTC not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMABTC cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_MASKR" description="SDMMC mask register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO underrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO underrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO overrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO overrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command response received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="command Response received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command sent interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command sent interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDIE" description="Data end interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDIE" description="Data hold interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data hold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data hold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data block end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data block end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data transfer abort interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data transfer abort interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO half empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO half empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO half full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO half full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIO Mode interrupt received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDIO Mode interrupt received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment Fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment Fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch critical timing section completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch critical timing section completion interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage Switch clock stopped interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage Switch clock stopped interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA buffer transfer complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA buffer transfer complete interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="SDMMC acknowledgment timer register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOTHRR" description="SDMMC data FIFO threshold register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THR" description="FIFO threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="threshold = 0 byte (no threshold)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="SDMMC DMA control register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABMODE" description="Buffer mode selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single buffer mode." start="0x0" />
+        <Enum name="B_0x1" description="Linked list mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="SDMMC IDMA buffer size register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of bytes per buffer" start="6" size="11" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMABASER" description="SDMMC IDMA buffer base address register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE" description="Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMALAR" description="SDMMC IDMA linked list address register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMALA" description="Word aligned linked list item address offset" start="2" size="14" access="Read/Write" />
+      <BitField name="ABR" description="Acknowledge linked list buffer ready" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated)." start="0x0" />
+        <Enum name="B_0x1" description="Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA." start="0x1" />
+      </BitField>
+      <BitField name="ULS" description="Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMABSIZER is not to be updated from next linked list table." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMABSIZER is to be updated from next linked list table." start="0x1" />
+      </BitField>
+      <BitField name="ULA" description="Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMALAR is not to be updated, last linked list item." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMALAR is to be updated from linked list table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABAR" description="SDMMC IDMA linked list memory base register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABA" description="Word aligned Linked list memory base address" start="2" size="30" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR0" description="SDMMC data FIFO registers 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR1" description="SDMMC data FIFO registers 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR2" description="SDMMC data FIFO registers 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR3" description="SDMMC data FIFO registers 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR4" description="SDMMC data FIFO registers 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR5" description="SDMMC data FIFO registers 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR6" description="SDMMC data FIFO registers 6" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR7" description="SDMMC data FIFO registers 7" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR8" description="SDMMC data FIFO registers 8" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR9" description="SDMMC data FIFO registers 9" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR10" description="SDMMC data FIFO registers 10" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR11" description="SDMMC data FIFO registers 11" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR12" description="SDMMC data FIFO registers 12" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR13" description="SDMMC data FIFO registers 13" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR14" description="SDMMC data FIFO registers 14" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR15" description="SDMMC data FIFO registers 15" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC2" description="Secure digital input/output MultiMediaCard interface" start="0x48026800">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low." start="0x0" />
+        <Enum name="B_0x2" description="Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low." start="0x2" />
+        <Enum name="B_0x3" description="Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation." start="0x3" />
+      </BitField>
+      <BitField name="VSWITCH" description="Voltage switch sequence start" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch sequence not started and not active." start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch sequence started or active." start="0x1" />
+      </BitField>
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock kept unchanged after successfully received command response." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK clock stopped after successfully received command response." start="0x1" />
+      </BitField>
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage transceiver IOs driven as output when direction signal is low." start="0x0" />
+        <Enum name="B_0x1" description="Voltage transceiver IOs driven as output when direction signal is high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_CLKCR" description="SDMMC clock control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x000" description="SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR)" start="0x000" />
+        <Enum name="B_0x001" description="SDMMC_CK frequency = sdmmc_ker_ck / 2" start="0x001" />
+        <Enum name="B_0x002" description="SDMMC_CK frequency = sdmmc_ker_ck / 4" start="0x002" />
+        <Enum name="B_0x080" description="SDMMC_CK frequency = sdmmc_ker_ck / 256" start="0x080" />
+        <Enum name="B_0x3FF" description="SDMMC_CK frequency = sdmmc_ker_ck / 2046" start="0x3FF" />
+      </BitField>
+      <BitField name="PWRSAV" description="Power saving configuration bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock is always enabled" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK is only enabled when the bus is active" start="0x1" />
+      </BitField>
+      <BitField name="WIDBUS" description="Wide bus mode enable bit" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR)" start="0x0" />
+        <Enum name="B_0x1" description="4-bit wide bus mode: SDMMC_D[3:0] used" start="0x1" />
+        <Enum name="B_0x2" description="8-bit wide bus mode: SDMMC_D[7:0] used" start="0x2" />
+      </BitField>
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and command" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x0" />
+        <Enum name="B_0x1" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x1" />
+      </BitField>
+      <BitField name="HWFC_EN" description="Hardware flow control enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware flow control is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Hardware flow control is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DDR" description="Data rate signaling selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDR Single data rate signaling" start="0x0" />
+        <Enum name="B_0x1" description="DDR double data rate signaling" start="0x1" />
+      </BitField>
+      <BitField name="BUSSPEED" description="Bus speed for selection of SDMMC operating modes" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected" start="0x0" />
+        <Enum name="B_0x1" description="SDR50, DDR50, SDR104, HS200 bus speed mode selected." start="0x1" />
+      </BitField>
+      <BitField name="SELCLKRX" description="Receive clock selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="sdmmc_io_in_ck selected as receive clock" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CKIN feedback clock selected as receive clock" start="0x1" />
+        <Enum name="B_0x2" description="sdmmc_fb_ck tuned feedback clock selected as receive clock." start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ARGR" description="SDMMC argument register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="SDMMC command register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index" start="0" size="6" access="Read/Write" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM" start="6" size="1" access="Read/Write" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" start="7" size="1" access="Read/Write" />
+      <BitField name="WAITRESP" description="Wait for response bits" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No response, expect CMDSENT flag" start="0x0" />
+        <Enum name="B_0x1" description="Short response, expect CMDREND or CCRCFAIL flag" start="0x1" />
+        <Enum name="B_0x2" description="Short response, expect CMDREND flag (No CRC)" start="0x2" />
+        <Enum name="B_0x3" description="Long response, expect CMDREND or CCRCFAIL flag" start="0x3" />
+      </BitField>
+      <BitField name="WAITINT" description="CPSM waits for interrupt request" start="10" size="1" access="Read/Write" />
+      <BitField name="WAITPEND" description="CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" start="11" size="1" access="Read/Write" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) enable bit" start="12" size="1" access="Read/Write" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM" start="13" size="1" access="Read/Write" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal boot mode procedure selected" start="0x0" />
+        <Enum name="B_0x1" description="Alternative boot mode procedure selected." start="0x1" />
+      </BitField>
+      <BitField name="BOOTEN" description="Enable boot mode procedure" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot mode procedure disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boot mode procedure enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="SDMMC response 1 register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="SDMMC response 2 register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="SDMMC response 3 register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="SDMMC response 4 register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="SDMMC data timer register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="SDMMC data length register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="SDMMC data control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not start data transfer without CPSM data transfer command." start="0x0" />
+        <Enum name="B_0x1" description="Start data transfer without CPSM data transfer command." start="0x1" />
+      </BitField>
+      <BitField name="DTDIR" description="Data transfer direction selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="From host to card." start="0x0" />
+        <Enum name="B_0x1" description="From card to host." start="0x1" />
+      </BitField>
+      <BitField name="DTMODE" description="Data transfer mode selection" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Block data transfer ending on block count." start="0x0" />
+        <Enum name="B_0x1" description="SDIO multibyte data transfer." start="0x1" />
+        <Enum name="B_0x2" description="e MMC Stream data transfer. (WIDBUS must select 1-bit wide bus mode)" start="0x2" />
+        <Enum name="B_0x3" description="Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers)." start="0x3" />
+      </BitField>
+      <BitField name="DBLOCKSIZE" description="Data block size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Block length = 2less thansup&gt;0less than/sup&gt; = 1 byte" start="0x0" />
+        <Enum name="B_0x1" description="Block length = 2less thansup&gt;1less than/sup&gt; = 2 bytes" start="0x1" />
+        <Enum name="B_0x2" description="Block length = 2less thansup&gt;2 less than/sup&gt;= 4 bytes" start="0x2" />
+        <Enum name="B_0x3" description="Block length = 2less thansup&gt;3less than/sup&gt; = 8 bytes" start="0x3" />
+        <Enum name="B_0x4" description="Block length = 2less thansup&gt;4less than/sup&gt; = 16 bytes" start="0x4" />
+        <Enum name="B_0x5" description="Block length = 2less thansup&gt;5less than/sup&gt; = 32 bytes" start="0x5" />
+        <Enum name="B_0x6" description="Block length = 2less thansup&gt;6less than/sup&gt; = 64 bytes" start="0x6" />
+        <Enum name="B_0x7" description="Block length = 2less thansup&gt;7less than/sup&gt; = 128 bytes" start="0x7" />
+        <Enum name="B_0x8" description="Block length = 2less thansup&gt;8less than/sup&gt; = 256 bytes" start="0x8" />
+        <Enum name="B_0x9" description="Block length = 2less thansup&gt;9less than/sup&gt; = 512 bytes" start="0x9" />
+        <Enum name="B_0xA" description="Block length = 2less thansup&gt;10less than/sup&gt; = 1024 bytes" start="0xA" />
+        <Enum name="B_0xB" description="Block length = 2less thansup&gt;11less than/sup&gt; = 2048 bytes" start="0xB" />
+        <Enum name="B_0xC" description="Block length = 2less thansup&gt;12less than/sup&gt; = 4096 bytes" start="0xC" />
+        <Enum name="B_0xD" description="Block length = 2less thansup&gt;13less than/sup&gt; = 8192 bytes" start="0xD" />
+        <Enum name="B_0xE" description="Block length = 2less thansup&gt;14less than/sup&gt; = 16384 bytes" start="0xE" />
+      </BitField>
+      <BitField name="RWSTART" description="Read Wait start" start="8" size="1" access="Read/Write" />
+      <BitField name="RWSTOP" description="Read Wait stop" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Read Wait stop." start="0x0" />
+        <Enum name="B_0x1" description="Enable for Read Wait stop when DPSM is in the R_W state." start="0x1" />
+      </BitField>
+      <BitField name="RWMOD" description="Read Wait mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read Wait control using SDMMC_D2" start="0x0" />
+        <Enum name="B_0x1" description="Read Wait control stopping SDMMC_CK" start="0x1" />
+      </BitField>
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions" start="11" size="1" access="Read/Write" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot acknowledgment disabled, not expected to be received" start="0x0" />
+        <Enum name="B_0x1" description="Boot acknowledgment enabled, expected to be received" start="0x1" />
+      </BitField>
+      <BitField name="FIFORST" description="FIFO reset, flushes any remaining data" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO not affected." start="0x0" />
+        <Enum name="B_0x1" description="Flush any remaining data and reset the FIFO pointers. This bit is automatically cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_DCNTR" description="SDMMC data counter register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value" start="0" size="25" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_STAR" description="SDMMC status register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed)" start="0" size="1" access="ReadOnly" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CTIMEOUT" description="Command response timeout" start="2" size="1" access="ReadOnly" />
+      <BitField name="DTIMEOUT" description="Data timeout" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error (masked by hardware when IDMA is enabled)" start="5" size="1" access="ReadOnly" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC)" start="6" size="1" access="ReadOnly" />
+      <BitField name="CMDSENT" description="Command sent (no response required)" start="7" size="1" access="ReadOnly" />
+      <BitField name="DATAEND" description="Data transfer ended correctly" start="8" size="1" access="ReadOnly" />
+      <BitField name="DHOLD" description="Data transfer Hold" start="9" size="1" access="ReadOnly" />
+      <BitField name="DBCKEND" description="Data block sent/received" start="10" size="1" access="ReadOnly" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12" start="11" size="1" access="ReadOnly" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state" start="12" size="1" access="ReadOnly" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full" start="15" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full" start="16" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOF" description="Receive FIFO full" start="17" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty" start="18" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty" start="19" size="1" access="ReadOnly" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card signals not busy on SDMMC_D0." start="0x0" />
+        <Enum name="B_0x1" description="card signals busy on SDMMC_D0." start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card SDMMC_D0 signal does NOT signal change from busy to not busy." start="0x0" />
+        <Enum name="B_0x1" description="card SDMMC_D0 signal changed from busy to NOT busy." start="0x1" />
+      </BitField>
+      <BitField name="SDIOIT" description="SDIO interrupt received" start="22" size="1" access="ReadOnly" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail)" start="23" size="1" access="ReadOnly" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout" start="24" size="1" access="ReadOnly" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion" start="25" size="1" access="ReadOnly" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDMATE" description="IDMA transfer error" start="27" size="1" access="ReadOnly" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete" start="28" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_ICR" description="SDMMC interrupt clear register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXUNDERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="TXUNDERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXOVERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="RXOVERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDREND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDREND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDSENT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDSENT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDC" description="DATAEND flag clear bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DATAEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DATAEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDC" description="DHOLD flag clear bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DHOLD not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DHOLD cleared" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBCKEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DBCKEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DABORTC" description="DABORT flag clear bit" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DABORT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DABORT cleared" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END not cleared" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END cleared" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIOIT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="SDIOIT cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDC" description="VSWEND flag clear bit" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSWEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="VSWEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKSTOP not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CKSTOP cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMATE not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMATE cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMABTC not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMABTC cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_MASKR" description="SDMMC mask register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO underrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO underrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO overrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO overrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command response received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="command Response received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command sent interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command sent interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDIE" description="Data end interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDIE" description="Data hold interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data hold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data hold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data block end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data block end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data transfer abort interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data transfer abort interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO half empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO half empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO half full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO half full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIO Mode interrupt received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDIO Mode interrupt received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment Fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment Fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch critical timing section completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch critical timing section completion interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage Switch clock stopped interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage Switch clock stopped interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA buffer transfer complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA buffer transfer complete interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="SDMMC acknowledgment timer register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOTHRR" description="SDMMC data FIFO threshold register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THR" description="FIFO threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="threshold = 0 byte (no threshold)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="SDMMC DMA control register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABMODE" description="Buffer mode selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single buffer mode." start="0x0" />
+        <Enum name="B_0x1" description="Linked list mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="SDMMC IDMA buffer size register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of bytes per buffer" start="6" size="11" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMABASER" description="SDMMC IDMA buffer base address register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE" description="Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMALAR" description="SDMMC IDMA linked list address register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMALA" description="Word aligned linked list item address offset" start="2" size="14" access="Read/Write" />
+      <BitField name="ABR" description="Acknowledge linked list buffer ready" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated)." start="0x0" />
+        <Enum name="B_0x1" description="Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA." start="0x1" />
+      </BitField>
+      <BitField name="ULS" description="Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMABSIZER is not to be updated from next linked list table." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMABSIZER is to be updated from next linked list table." start="0x1" />
+      </BitField>
+      <BitField name="ULA" description="Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMALAR is not to be updated, last linked list item." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMALAR is to be updated from linked list table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABAR" description="SDMMC IDMA linked list memory base register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABA" description="Word aligned Linked list memory base address" start="2" size="30" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR0" description="SDMMC data FIFO registers 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR1" description="SDMMC data FIFO registers 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR2" description="SDMMC data FIFO registers 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR3" description="SDMMC data FIFO registers 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR4" description="SDMMC data FIFO registers 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR5" description="SDMMC data FIFO registers 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR6" description="SDMMC data FIFO registers 6" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR7" description="SDMMC data FIFO registers 7" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR8" description="SDMMC data FIFO registers 8" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR9" description="SDMMC data FIFO registers 9" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR10" description="SDMMC data FIFO registers 10" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR11" description="SDMMC data FIFO registers 11" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR12" description="SDMMC data FIFO registers 12" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR13" description="SDMMC data FIFO registers 13" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR14" description="SDMMC data FIFO registers 14" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR15" description="SDMMC data FIFO registers 15" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC2_S" description="Secure digital input/output MultiMediaCard interface" start="0x58026800">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low." start="0x0" />
+        <Enum name="B_0x2" description="Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low." start="0x2" />
+        <Enum name="B_0x3" description="Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation." start="0x3" />
+      </BitField>
+      <BitField name="VSWITCH" description="Voltage switch sequence start" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch sequence not started and not active." start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch sequence started or active." start="0x1" />
+      </BitField>
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock kept unchanged after successfully received command response." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK clock stopped after successfully received command response." start="0x1" />
+      </BitField>
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage transceiver IOs driven as output when direction signal is low." start="0x0" />
+        <Enum name="B_0x1" description="Voltage transceiver IOs driven as output when direction signal is high." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_CLKCR" description="SDMMC clock control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x000" description="SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR)" start="0x000" />
+        <Enum name="B_0x001" description="SDMMC_CK frequency = sdmmc_ker_ck / 2" start="0x001" />
+        <Enum name="B_0x002" description="SDMMC_CK frequency = sdmmc_ker_ck / 4" start="0x002" />
+        <Enum name="B_0x080" description="SDMMC_CK frequency = sdmmc_ker_ck / 256" start="0x080" />
+        <Enum name="B_0x3FF" description="SDMMC_CK frequency = sdmmc_ker_ck / 2046" start="0x3FF" />
+      </BitField>
+      <BitField name="PWRSAV" description="Power saving configuration bit" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_CK clock is always enabled" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CK is only enabled when the bus is active" start="0x1" />
+      </BitField>
+      <BitField name="WIDBUS" description="Wide bus mode enable bit" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR)" start="0x0" />
+        <Enum name="B_0x1" description="4-bit wide bus mode: SDMMC_D[3:0] used" start="0x1" />
+        <Enum name="B_0x2" description="8-bit wide bus mode: SDMMC_D[7:0] used" start="0x2" />
+      </BitField>
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and command" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x0" />
+        <Enum name="B_0x1" description="When clock division &gt;1 (CLKDIV &gt; 0) and DDR = 0:" start="0x1" />
+      </BitField>
+      <BitField name="HWFC_EN" description="Hardware flow control enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware flow control is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Hardware flow control is enabled" start="0x1" />
+      </BitField>
+      <BitField name="DDR" description="Data rate signaling selection" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDR Single data rate signaling" start="0x0" />
+        <Enum name="B_0x1" description="DDR double data rate signaling" start="0x1" />
+      </BitField>
+      <BitField name="BUSSPEED" description="Bus speed for selection of SDMMC operating modes" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected" start="0x0" />
+        <Enum name="B_0x1" description="SDR50, DDR50, SDR104, HS200 bus speed mode selected." start="0x1" />
+      </BitField>
+      <BitField name="SELCLKRX" description="Receive clock selection" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="sdmmc_io_in_ck selected as receive clock" start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_CKIN feedback clock selected as receive clock" start="0x1" />
+        <Enum name="B_0x2" description="sdmmc_fb_ck tuned feedback clock selected as receive clock." start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ARGR" description="SDMMC argument register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="SDMMC command register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index" start="0" size="6" access="Read/Write" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM" start="6" size="1" access="Read/Write" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" start="7" size="1" access="Read/Write" />
+      <BitField name="WAITRESP" description="Wait for response bits" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No response, expect CMDSENT flag" start="0x0" />
+        <Enum name="B_0x1" description="Short response, expect CMDREND or CCRCFAIL flag" start="0x1" />
+        <Enum name="B_0x2" description="Short response, expect CMDREND flag (No CRC)" start="0x2" />
+        <Enum name="B_0x3" description="Long response, expect CMDREND or CCRCFAIL flag" start="0x3" />
+      </BitField>
+      <BitField name="WAITINT" description="CPSM waits for interrupt request" start="10" size="1" access="Read/Write" />
+      <BitField name="WAITPEND" description="CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" start="11" size="1" access="Read/Write" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) enable bit" start="12" size="1" access="Read/Write" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM" start="13" size="1" access="Read/Write" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal boot mode procedure selected" start="0x0" />
+        <Enum name="B_0x1" description="Alternative boot mode procedure selected." start="0x1" />
+      </BitField>
+      <BitField name="BOOTEN" description="Enable boot mode procedure" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot mode procedure disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boot mode procedure enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="SDMMC response 1 register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="SDMMC response 2 register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="SDMMC response 3 register" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="SDMMC response 4 register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS" description="Card status according table below" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="SDMMC data timer register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="SDMMC data length register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="SDMMC data control register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not start data transfer without CPSM data transfer command." start="0x0" />
+        <Enum name="B_0x1" description="Start data transfer without CPSM data transfer command." start="0x1" />
+      </BitField>
+      <BitField name="DTDIR" description="Data transfer direction selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="From host to card." start="0x0" />
+        <Enum name="B_0x1" description="From card to host." start="0x1" />
+      </BitField>
+      <BitField name="DTMODE" description="Data transfer mode selection" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Block data transfer ending on block count." start="0x0" />
+        <Enum name="B_0x1" description="SDIO multibyte data transfer." start="0x1" />
+        <Enum name="B_0x2" description="e MMC Stream data transfer. (WIDBUS must select 1-bit wide bus mode)" start="0x2" />
+        <Enum name="B_0x3" description="Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers)." start="0x3" />
+      </BitField>
+      <BitField name="DBLOCKSIZE" description="Data block size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Block length = 2less thansup&gt;0less than/sup&gt; = 1 byte" start="0x0" />
+        <Enum name="B_0x1" description="Block length = 2less thansup&gt;1less than/sup&gt; = 2 bytes" start="0x1" />
+        <Enum name="B_0x2" description="Block length = 2less thansup&gt;2 less than/sup&gt;= 4 bytes" start="0x2" />
+        <Enum name="B_0x3" description="Block length = 2less thansup&gt;3less than/sup&gt; = 8 bytes" start="0x3" />
+        <Enum name="B_0x4" description="Block length = 2less thansup&gt;4less than/sup&gt; = 16 bytes" start="0x4" />
+        <Enum name="B_0x5" description="Block length = 2less thansup&gt;5less than/sup&gt; = 32 bytes" start="0x5" />
+        <Enum name="B_0x6" description="Block length = 2less thansup&gt;6less than/sup&gt; = 64 bytes" start="0x6" />
+        <Enum name="B_0x7" description="Block length = 2less thansup&gt;7less than/sup&gt; = 128 bytes" start="0x7" />
+        <Enum name="B_0x8" description="Block length = 2less thansup&gt;8less than/sup&gt; = 256 bytes" start="0x8" />
+        <Enum name="B_0x9" description="Block length = 2less thansup&gt;9less than/sup&gt; = 512 bytes" start="0x9" />
+        <Enum name="B_0xA" description="Block length = 2less thansup&gt;10less than/sup&gt; = 1024 bytes" start="0xA" />
+        <Enum name="B_0xB" description="Block length = 2less thansup&gt;11less than/sup&gt; = 2048 bytes" start="0xB" />
+        <Enum name="B_0xC" description="Block length = 2less thansup&gt;12less than/sup&gt; = 4096 bytes" start="0xC" />
+        <Enum name="B_0xD" description="Block length = 2less thansup&gt;13less than/sup&gt; = 8192 bytes" start="0xD" />
+        <Enum name="B_0xE" description="Block length = 2less thansup&gt;14less than/sup&gt; = 16384 bytes" start="0xE" />
+      </BitField>
+      <BitField name="RWSTART" description="Read Wait start" start="8" size="1" access="Read/Write" />
+      <BitField name="RWSTOP" description="Read Wait stop" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No Read Wait stop." start="0x0" />
+        <Enum name="B_0x1" description="Enable for Read Wait stop when DPSM is in the R_W state." start="0x1" />
+      </BitField>
+      <BitField name="RWMOD" description="Read Wait mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Read Wait control using SDMMC_D2" start="0x0" />
+        <Enum name="B_0x1" description="Read Wait control stopping SDMMC_CK" start="0x1" />
+      </BitField>
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions" start="11" size="1" access="Read/Write" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boot acknowledgment disabled, not expected to be received" start="0x0" />
+        <Enum name="B_0x1" description="Boot acknowledgment enabled, expected to be received" start="0x1" />
+      </BitField>
+      <BitField name="FIFORST" description="FIFO reset, flushes any remaining data" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO not affected." start="0x0" />
+        <Enum name="B_0x1" description="Flush any remaining data and reset the FIFO pointers. This bit is automatically cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_DCNTR" description="SDMMC data counter register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value" start="0" size="25" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_STAR" description="SDMMC status register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed)" start="0" size="1" access="ReadOnly" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed)" start="1" size="1" access="ReadOnly" />
+      <BitField name="CTIMEOUT" description="Command response timeout" start="2" size="1" access="ReadOnly" />
+      <BitField name="DTIMEOUT" description="Data timeout" start="3" size="1" access="ReadOnly" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" start="4" size="1" access="ReadOnly" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error (masked by hardware when IDMA is enabled)" start="5" size="1" access="ReadOnly" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC)" start="6" size="1" access="ReadOnly" />
+      <BitField name="CMDSENT" description="Command sent (no response required)" start="7" size="1" access="ReadOnly" />
+      <BitField name="DATAEND" description="Data transfer ended correctly" start="8" size="1" access="ReadOnly" />
+      <BitField name="DHOLD" description="Data transfer Hold" start="9" size="1" access="ReadOnly" />
+      <BitField name="DBCKEND" description="Data block sent/received" start="10" size="1" access="ReadOnly" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12" start="11" size="1" access="ReadOnly" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state" start="12" size="1" access="ReadOnly" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state" start="13" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty" start="14" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full" start="15" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full" start="16" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOF" description="Receive FIFO full" start="17" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty" start="18" size="1" access="ReadOnly" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty" start="19" size="1" access="ReadOnly" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card signals not busy on SDMMC_D0." start="0x0" />
+        <Enum name="B_0x1" description="card signals busy on SDMMC_D0." start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected" start="21" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="card SDMMC_D0 signal does NOT signal change from busy to not busy." start="0x0" />
+        <Enum name="B_0x1" description="card SDMMC_D0 signal changed from busy to NOT busy." start="0x1" />
+      </BitField>
+      <BitField name="SDIOIT" description="SDIO interrupt received" start="22" size="1" access="ReadOnly" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail)" start="23" size="1" access="ReadOnly" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout" start="24" size="1" access="ReadOnly" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion" start="25" size="1" access="ReadOnly" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure" start="26" size="1" access="ReadOnly" />
+      <BitField name="IDMATE" description="IDMA transfer error" start="27" size="1" access="ReadOnly" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete" start="28" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="SDMMC_ICR" description="SDMMC interrupt clear register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DCRCFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DCRCFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXUNDERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="TXUNDERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXOVERR not cleared" start="0x0" />
+        <Enum name="B_0x1" description="RXOVERR cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDREND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDREND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CMDSENT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CMDSENT cleared" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDC" description="DATAEND flag clear bit" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DATAEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DATAEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDC" description="DHOLD flag clear bit" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DHOLD not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DHOLD cleared" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DBCKEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DBCKEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="DABORTC" description="DABORT flag clear bit" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DABORT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="DABORT cleared" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END not cleared" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END cleared" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIOIT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="SDIOIT cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKFAIL not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKFAIL cleared" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ACKTIMEOUT not cleared" start="0x0" />
+        <Enum name="B_0x1" description="ACKTIMEOUT cleared" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDC" description="VSWEND flag clear bit" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VSWEND not cleared" start="0x0" />
+        <Enum name="B_0x1" description="VSWEND cleared" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CKSTOP not cleared" start="0x0" />
+        <Enum name="B_0x1" description="CKSTOP cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMATE not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMATE cleared" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMABTC not cleared" start="0x0" />
+        <Enum name="B_0x1" description="IDMABTC cleared" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_MASKR" description="SDMMC mask register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data CRC fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data CRC fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO underrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO underrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO overrun error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO overrun error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command response received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="command Response received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Command sent interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Command sent interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DATAENDIE" description="Data end interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DHOLDIE" description="Data hold interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data hold interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data hold interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data block end interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data block end interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Data transfer abort interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data transfer abort interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO half empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO half empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO half full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO half full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx FIFO full interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx FIFO full interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx FIFO empty interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx FIFO empty interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="BUSYD0END interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="BUSYD0END interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDIO Mode interrupt received interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="SDIO Mode interrupt received interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment Fail interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment Fail interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Acknowledgment timeout interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Acknowledgment timeout interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage switch critical timing section completion interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage switch critical timing section completion interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Voltage Switch clock stopped interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Voltage Switch clock stopped interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA buffer transfer complete interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA buffer transfer complete interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="SDMMC acknowledgment timer register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period" start="0" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOTHRR" description="SDMMC data FIFO threshold register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THR" description="FIFO threshold" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="threshold = 0 byte (no threshold)" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="SDMMC DMA control register" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IDMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IDMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDMABMODE" description="Buffer mode selection" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single buffer mode." start="0x0" />
+        <Enum name="B_0x1" description="Linked list mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="SDMMC IDMA buffer size register" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of bytes per buffer" start="6" size="11" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMABASER" description="SDMMC IDMA buffer base address register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE" description="Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_IDMALAR" description="SDMMC IDMA linked list address register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMALA" description="Word aligned linked list item address offset" start="2" size="14" access="Read/Write" />
+      <BitField name="ABR" description="Acknowledge linked list buffer ready" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated)." start="0x0" />
+        <Enum name="B_0x1" description="Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA." start="0x1" />
+      </BitField>
+      <BitField name="ULS" description="Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMABSIZER is not to be updated from next linked list table." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMABSIZER is to be updated from next linked list table." start="0x1" />
+      </BitField>
+      <BitField name="ULA" description="Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SDMMC_IDMALAR is not to be updated, last linked list item." start="0x0" />
+        <Enum name="B_0x1" description="SDMMC_IDMALAR is to be updated from linked list table." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SDMMC_IDMABAR" description="SDMMC IDMA linked list memory base register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABA" description="Word aligned Linked list memory base address" start="2" size="30" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR0" description="SDMMC data FIFO registers 0" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR1" description="SDMMC data FIFO registers 1" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR2" description="SDMMC data FIFO registers 2" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR3" description="SDMMC data FIFO registers 3" start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR4" description="SDMMC data FIFO registers 4" start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR5" description="SDMMC data FIFO registers 5" start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR6" description="SDMMC data FIFO registers 6" start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR7" description="SDMMC data FIFO registers 7" start="+0x9C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR8" description="SDMMC data FIFO registers 8" start="+0xA0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR9" description="SDMMC data FIFO registers 9" start="+0xA4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR10" description="SDMMC data FIFO registers 10" start="+0xA8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR11" description="SDMMC data FIFO registers 11" start="+0xAC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR12" description="SDMMC data FIFO registers 12" start="+0xB0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR13" description="SDMMC data FIFO registers 13" start="+0xB4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR14" description="SDMMC data FIFO registers 14" start="+0xB8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SDMMC_FIFOR15" description="SDMMC data FIFO registers 15" start="+0xBC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPDIFRX" description="SPDIF receiver interface" start="0x40004000">
+    <Register name="SPDIFRX_CR" description="SPDIFRX control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPDIFRXEN" description="Peripheral block enableless thansup&gt;(1)less than/sup&gt;" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Disable SPDIFRX (STATE_IDLE)." start="0x0" />
+        <Enum name="B_0x1" description="Enable SPDIFRX synchronization only." start="0x1" />
+        <Enum name="B_0x3" description="Enable SPDIF receiver." start="0x3" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Receiver DMA enable for data flowless thansup&gt;(1)less than/sup&gt;" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception." start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception." start="0x0" />
+      </BitField>
+      <BitField name="RXSTEO" description="Stereo modeless thansup&gt;(1)less than/sup&gt;" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The peripheral is in stereo mode." start="0x1" />
+        <Enum name="B_0x0" description="The peripheral is in mono mode." start="0x0" />
+      </BitField>
+      <BitField name="DRFMT" description="RX data formatless thansup&gt;(1)less than/sup&gt;" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Data sample are packed by setting two 16-bit sample into a 32-bit word." start="0x2" />
+        <Enum name="B_0x1" description="Data samples are aligned in the left (MSB)" start="0x1" />
+        <Enum name="B_0x0" description="Data samples are aligned in the right (LSB)." start="0x0" />
+      </BitField>
+      <BitField name="PMSK" description="Mask parity error bitless thansup&gt;(1)less than/sup&gt;" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The parity error bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead." start="0x1" />
+        <Enum name="B_0x0" description="The parity error bit is copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="VMSK" description="Mask of validity bitless thansup&gt;(1)less than/sup&gt;" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The validity bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead." start="0x1" />
+        <Enum name="B_0x0" description="The validity bit is copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="CUMSK" description="Mask of channel status and user bitsless thansup&gt;(1)less than/sup&gt;" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The channel status and user bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead." start="0x1" />
+        <Enum name="B_0x0" description="The channel status and user bits are copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="PTMSK" description="Mask of preamble type bitsless thansup&gt;(1)less than/sup&gt;" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The preamble type bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead." start="0x1" />
+        <Enum name="B_0x0" description="The preamble type bits are copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="CBDMAEN" description="Control buffer DMA enable for control flowless thansup&gt;(1)less than/sup&gt;" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception of channel status and used data information." start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception of channel status and used data information." start="0x0" />
+      </BitField>
+      <BitField name="CHSEL" description="Channel selectionless thansup&gt;(1)less than/sup&gt;" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The control flow takes the channel status from channel B." start="0x1" />
+        <Enum name="B_0x0" description="The control flow takes the channel status from channel A." start="0x0" />
+      </BitField>
+      <BitField name="NBTR" description="Maximum allowed re-tries during synchronization phaseless thansup&gt;(1)less than/sup&gt;" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No re-try is allowed (only one attempt)" start="0x0" />
+        <Enum name="B_0x1" description="3 re-tries allowed" start="0x1" />
+        <Enum name="B_0x2" description="15 re-tries allowed" start="0x2" />
+        <Enum name="B_0x3" description="63 re-tries allowed" start="0x3" />
+      </BitField>
+      <BitField name="WFA" description="Wait for activityless thansup&gt;(1)less than/sup&gt;" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX waits for activity on SPDIFRX_IN line (4 transitions) before performing the synchronization." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not wait for activity on SPDIFRX_IN line before performing the synchronization." start="0x0" />
+      </BitField>
+      <BitField name="INSEL" description="SPDIFRX input selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX_IN0 selected" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX_IN1 selected" start="0x1" />
+        <Enum name="B_0x2" description="SPDIFRX_IN2 selected" start="0x2" />
+        <Enum name="B_0x3" description="SPDIFRX_IN3 selected" start="0x3" />
+      </BitField>
+      <BitField name="CKSEN" description="Symbol clock enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX generates a symbol clock." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not generate a symbol clock." start="0x0" />
+      </BitField>
+      <BitField name="CKSBKPEN" description="Backup symbol clock enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX generates a backup symbol clock if CKSEN = 1." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not generate a backup symbol clock." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_IMR" description="SPDIFRX interrupt mask register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever RXNE=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="CSRNEIE" description="Control buffer ready interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever CSRNE = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="PERRIE" description="Parity error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever PERR=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever OVR=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="SBLKIE" description="Synchronization block detected interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SBD = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="SYNCDIE" description="Synchronization done" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SYNCD = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="IFEIE" description="Serial interface error interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SERR = 1, TERR = 1, or FERR = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_SR" description="SPDIFRX status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNE" description="Read data register not empty" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received." start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="CSRNE" description="Control buffer register not empty " start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No control word available on SPDIFRX_CSR register" start="0x0" />
+        <Enum name="B_0x1" description="A control word is available on SPDIFRX_CSR register." start="0x1" />
+      </BitField>
+      <BitField name="PERR" description="Parity error" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected." start="0x1" />
+      </BitField>
+      <BitField name="SBD" description="Synchronization block detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No B preamble is detected." start="0x0" />
+        <Enum name="B_0x1" description="B preamble is detected." start="0x1" />
+      </BitField>
+      <BitField name="SYNCD" description="Synchronization done" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronization is pending." start="0x0" />
+        <Enum name="B_0x1" description="Synchronization is completed." start="0x1" />
+      </BitField>
+      <BitField name="FERR" description="Framing error" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Manchester violation detected" start="0x0" />
+        <Enum name="B_0x1" description="Manchester violation detected" start="0x1" />
+      </BitField>
+      <BitField name="SERR" description="Synchronization error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error is detected." start="0x0" />
+        <Enum name="B_0x1" description="Synchronization error is detected." start="0x1" />
+      </BitField>
+      <BitField name="TERR" description="Time-out error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No sequence error is detected." start="0x0" />
+        <Enum name="B_0x1" description="Sequence error is detected." start="0x1" />
+      </BitField>
+      <BitField name="WIDTH5" description="duration of 5 symbols counted with spdifrx_ker_ck" start="16" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_IFCR" description="SPDIFRX interrupt flag clear register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERRCF" description="clears the parity error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="clears the overrun error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="SBDCF" description="clears the synchronization block detected flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="SYNCDCF" description="clears the synchronization done flag" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPDIFRX_FMT0_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="data value" start="0" size="24" access="ReadOnly" />
+      <BitField name="PE" description="parity error bit" start="24" size="1" access="ReadOnly" />
+      <BitField name="V" description="validity bit" start="25" size="1" access="ReadOnly" />
+      <BitField name="U" description="user bit" start="26" size="1" access="ReadOnly" />
+      <BitField name="C" description="channel status bit" start="27" size="1" access="ReadOnly" />
+      <BitField name="PT" description="preamble type" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="Preamble B received" start="0x1" />
+        <Enum name="B_0x2" description="Preamble M received" start="0x2" />
+        <Enum name="B_0x3" description="Preamble W received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_FMT1_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="parity error bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="V" description="validity bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="U" description="user bit" start="2" size="1" access="ReadOnly" />
+      <BitField name="C" description="channel Status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="PT" description="preamble type" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="preamble B received" start="0x1" />
+        <Enum name="B_0x2" description="preamble M received" start="0x2" />
+        <Enum name="B_0x3" description="preamble W received" start="0x3" />
+      </BitField>
+      <BitField name="DR" description="data value" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_FMT2_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DRNL1" description="data value" start="0" size="16" access="ReadOnly" />
+      <BitField name="DRNL2" description="data value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_CSR" description="SPDIFRX channel status register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USR" description="user data information" start="0" size="16" access="ReadOnly" />
+      <BitField name="CS" description="channel A status information" start="16" size="8" access="ReadOnly" />
+      <BitField name="SOB" description="start of block" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CS[0] is not the first bit of a new block" start="0x0" />
+        <Enum name="B_0x1" description="CS[0] is the first bit of a new block" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_DIR" description="SPDIFRX debug information register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THI" description="threshold HIGH (THI = 2.5 x UI / Tless thansub&gt;spdifrx_ker_ckless than/sub&gt;)" start="0" size="13" access="ReadOnly" />
+      <BitField name="TLO" description="threshold LOW (TLO = 1.5 x UI / Tless thansub&gt;spdifrx_ker_ckless than/sub&gt;)" start="16" size="13" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPDIFRX_S" description="SPDIF receiver interface" start="0x50004000">
+    <Register name="SPDIFRX_CR" description="SPDIFRX control register" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPDIFRXEN" description="Peripheral block enableless thansup&gt;(1)less than/sup&gt;" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Disable SPDIFRX (STATE_IDLE)." start="0x0" />
+        <Enum name="B_0x1" description="Enable SPDIFRX synchronization only." start="0x1" />
+        <Enum name="B_0x3" description="Enable SPDIF receiver." start="0x3" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Receiver DMA enable for data flowless thansup&gt;(1)less than/sup&gt;" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception." start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception." start="0x0" />
+      </BitField>
+      <BitField name="RXSTEO" description="Stereo modeless thansup&gt;(1)less than/sup&gt;" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The peripheral is in stereo mode." start="0x1" />
+        <Enum name="B_0x0" description="The peripheral is in mono mode." start="0x0" />
+      </BitField>
+      <BitField name="DRFMT" description="RX data formatless thansup&gt;(1)less than/sup&gt;" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x2" description="Data sample are packed by setting two 16-bit sample into a 32-bit word." start="0x2" />
+        <Enum name="B_0x1" description="Data samples are aligned in the left (MSB)" start="0x1" />
+        <Enum name="B_0x0" description="Data samples are aligned in the right (LSB)." start="0x0" />
+      </BitField>
+      <BitField name="PMSK" description="Mask parity error bitless thansup&gt;(1)less than/sup&gt;" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The parity error bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead." start="0x1" />
+        <Enum name="B_0x0" description="The parity error bit is copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="VMSK" description="Mask of validity bitless thansup&gt;(1)less than/sup&gt;" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The validity bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead." start="0x1" />
+        <Enum name="B_0x0" description="The validity bit is copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="CUMSK" description="Mask of channel status and user bitsless thansup&gt;(1)less than/sup&gt;" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The channel status and user bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead." start="0x1" />
+        <Enum name="B_0x0" description="The channel status and user bits are copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="PTMSK" description="Mask of preamble type bitsless thansup&gt;(1)less than/sup&gt;" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The preamble type bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead." start="0x1" />
+        <Enum name="B_0x0" description="The preamble type bits are copied into the SPDIFRX_FMTx_DR." start="0x0" />
+      </BitField>
+      <BitField name="CBDMAEN" description="Control buffer DMA enable for control flowless thansup&gt;(1)less than/sup&gt;" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception of channel status and used data information." start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception of channel status and used data information." start="0x0" />
+      </BitField>
+      <BitField name="CHSEL" description="Channel selectionless thansup&gt;(1)less than/sup&gt;" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The control flow takes the channel status from channel B." start="0x1" />
+        <Enum name="B_0x0" description="The control flow takes the channel status from channel A." start="0x0" />
+      </BitField>
+      <BitField name="NBTR" description="Maximum allowed re-tries during synchronization phaseless thansup&gt;(1)less than/sup&gt;" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="No re-try is allowed (only one attempt)" start="0x0" />
+        <Enum name="B_0x1" description="3 re-tries allowed" start="0x1" />
+        <Enum name="B_0x2" description="15 re-tries allowed" start="0x2" />
+        <Enum name="B_0x3" description="63 re-tries allowed" start="0x3" />
+      </BitField>
+      <BitField name="WFA" description="Wait for activityless thansup&gt;(1)less than/sup&gt;" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX waits for activity on SPDIFRX_IN line (4 transitions) before performing the synchronization." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not wait for activity on SPDIFRX_IN line before performing the synchronization." start="0x0" />
+      </BitField>
+      <BitField name="INSEL" description="SPDIFRX input selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPDIFRX_IN0 selected" start="0x0" />
+        <Enum name="B_0x1" description="SPDIFRX_IN1 selected" start="0x1" />
+        <Enum name="B_0x2" description="SPDIFRX_IN2 selected" start="0x2" />
+        <Enum name="B_0x3" description="SPDIFRX_IN3 selected" start="0x3" />
+      </BitField>
+      <BitField name="CKSEN" description="Symbol clock enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX generates a symbol clock." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not generate a symbol clock." start="0x0" />
+      </BitField>
+      <BitField name="CKSBKPEN" description="Backup symbol clock enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="The SPDIFRX generates a backup symbol clock if CKSEN = 1." start="0x1" />
+        <Enum name="B_0x0" description="The SPDIFRX does not generate a backup symbol clock." start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_IMR" description="SPDIFRX interrupt mask register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever RXNE=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="CSRNEIE" description="Control buffer ready interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever CSRNE = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="PERRIE" description="Parity error interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever PERR=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun error interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever OVR=1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="SBLKIE" description="Synchronization block detected interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SBD = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="SYNCDIE" description="Synchronization done" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SYNCD = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+      <BitField name="IFEIE" description="Serial interface error interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited." start="0x0" />
+        <Enum name="B_0x1" description="A SPDIFRX interface interrupt is generated whenever SERR = 1, TERR = 1, or FERR = 1 in the SPDIFRX_SR register." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_SR" description="SPDIFRX status register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNE" description="Read data register not empty" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received." start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="CSRNE" description="Control buffer register not empty " start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No control word available on SPDIFRX_CSR register" start="0x0" />
+        <Enum name="B_0x1" description="A control word is available on SPDIFRX_CSR register." start="0x1" />
+      </BitField>
+      <BitField name="PERR" description="Parity error" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected." start="0x1" />
+      </BitField>
+      <BitField name="SBD" description="Synchronization block detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No B preamble is detected." start="0x0" />
+        <Enum name="B_0x1" description="B preamble is detected." start="0x1" />
+      </BitField>
+      <BitField name="SYNCD" description="Synchronization done" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Synchronization is pending." start="0x0" />
+        <Enum name="B_0x1" description="Synchronization is completed." start="0x1" />
+      </BitField>
+      <BitField name="FERR" description="Framing error" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Manchester violation detected" start="0x0" />
+        <Enum name="B_0x1" description="Manchester violation detected" start="0x1" />
+      </BitField>
+      <BitField name="SERR" description="Synchronization error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No synchronization error is detected." start="0x0" />
+        <Enum name="B_0x1" description="Synchronization error is detected." start="0x1" />
+      </BitField>
+      <BitField name="TERR" description="Time-out error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No sequence error is detected." start="0x0" />
+        <Enum name="B_0x1" description="Sequence error is detected." start="0x1" />
+      </BitField>
+      <BitField name="WIDTH5" description="duration of 5 symbols counted with spdifrx_ker_ck" start="16" size="15" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_IFCR" description="SPDIFRX interrupt flag clear register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERRCF" description="clears the parity error flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="OVRCF" description="clears the overrun error flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="SBDCF" description="clears the synchronization block detected flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="SYNCDCF" description="clears the synchronization done flag" start="5" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPDIFRX_FMT0_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="data value" start="0" size="24" access="ReadOnly" />
+      <BitField name="PE" description="parity error bit" start="24" size="1" access="ReadOnly" />
+      <BitField name="V" description="validity bit" start="25" size="1" access="ReadOnly" />
+      <BitField name="U" description="user bit" start="26" size="1" access="ReadOnly" />
+      <BitField name="C" description="channel status bit" start="27" size="1" access="ReadOnly" />
+      <BitField name="PT" description="preamble type" start="28" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="Preamble B received" start="0x1" />
+        <Enum name="B_0x2" description="Preamble M received" start="0x2" />
+        <Enum name="B_0x3" description="Preamble W received" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_FMT1_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="parity error bit" start="0" size="1" access="ReadOnly" />
+      <BitField name="V" description="validity bit" start="1" size="1" access="ReadOnly" />
+      <BitField name="U" description="user bit" start="2" size="1" access="ReadOnly" />
+      <BitField name="C" description="channel Status bit" start="3" size="1" access="ReadOnly" />
+      <BitField name="PT" description="preamble type" start="4" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="preamble B received" start="0x1" />
+        <Enum name="B_0x2" description="preamble M received" start="0x2" />
+        <Enum name="B_0x3" description="preamble W received" start="0x3" />
+      </BitField>
+      <BitField name="DR" description="data value" start="8" size="24" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_FMT2_DR" description="SPDIFRX data input register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DRNL1" description="data value" start="0" size="16" access="ReadOnly" />
+      <BitField name="DRNL2" description="data value" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPDIFRX_CSR" description="SPDIFRX channel status register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USR" description="user data information" start="0" size="16" access="ReadOnly" />
+      <BitField name="CS" description="channel A status information" start="16" size="8" access="ReadOnly" />
+      <BitField name="SOB" description="start of block" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CS[0] is not the first bit of a new block" start="0x0" />
+        <Enum name="B_0x1" description="CS[0] is the first bit of a new block" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPDIFRX_DIR" description="SPDIFRX debug information register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THI" description="threshold HIGH (THI = 2.5 x UI / Tless thansub&gt;spdifrx_ker_ckless than/sub&gt;)" start="0" size="13" access="ReadOnly" />
+      <BitField name="TLO" description="threshold LOW (TLO = 1.5 x UI / Tless thansub&gt;spdifrx_ker_ckless than/sub&gt;)" start="16" size="13" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI1" description="Serial peripheral interface" start="0x42003000">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI1_S" description="Serial peripheral interface" start="0x52003000">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI2" description="Serial peripheral interface" start="0x40003800">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI2_S" description="Serial peripheral interface" start="0x50003800">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI3" description="Serial peripheral interface" start="0x40003C00">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI3_S" description="Serial peripheral interface" start="0x50003C00">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI4" description="Serial peripheral interface" start="0x42003400">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI4_S" description="Serial peripheral interface" start="0x52003400">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI5" description="Serial peripheral interface" start="0x42005000">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI5_S" description="Serial peripheral interface" start="0x52005000">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI6" description="Serial peripheral interface" start="0x46001400">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI6_S" description="Serial peripheral interface" start="0x56001400">
+    <Register name="SPI_CR1" description="SPI/I2S control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPE" description="serial peripheral enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Serial peripheral disabled." start="0x0" />
+        <Enum name="B_0x1" description="Serial peripheral enabled" start="0x1" />
+      </BitField>
+      <BitField name="MASRX" description="master automatic suspension in Receive mode " start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost)" start="0x0" />
+        <Enum name="B_0x1" description="SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended." start="0x1" />
+      </BitField>
+      <BitField name="CSTART" description="master transfer start" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="master transfer is at idle" start="0x0" />
+        <Enum name="B_0x1" description="master transfer is ongoing or temporary suspended by automatic suspend" start="0x1" />
+      </BitField>
+      <BitField name="CSUSP" description="master suspend request " start="10" size="1" access="WriteOnly" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI is receiver" start="0x0" />
+        <Enum name="B_0x1" description="SPI is transmitter" start="0x1" />
+      </BitField>
+      <BitField name="SSI" description="internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Full size (33-bit or 17-bit) CRC polynomial is not used" start="0x0" />
+        <Enum name="B_0x1" description="Full size (33-bit or 17-bit) CRC polynomial is used" start="0x1" />
+      </BitField>
+      <BitField name="RCRCINI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="All ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="TCRCINI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="all zero pattern is applied" start="0x0" />
+        <Enum name="B_0x1" description="all ones pattern is applied" start="0x1" />
+      </BitField>
+      <BitField name="IOLOCK" description="locking the AF configuration of associated I/Os" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AF configuration is not locked" start="0x0" />
+        <Enum name="B_0x1" description="AF configuration is locked" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CR2" description="SPI/I2S control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIZE" description="number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="SPI_CFG1" description="SPI/I2S configuration register 1" start="+0x08" size="4" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="DSIZE" description="number of bits in at single SPI data frame" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="not used" start="0x0" />
+        <Enum name="B_0x1" description="not used" start="0x1" />
+        <Enum name="B_0x2" description="not used" start="0x2" />
+        <Enum name="B_0x3" description="4 bits" start="0x3" />
+        <Enum name="B_0x4" description="5 bits" start="0x4" />
+        <Enum name="B_0x5" description="6 bits" start="0x5" />
+        <Enum name="B_0x6" description="7 bits" start="0x6" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+        <Enum name="B_0x1D" description="30 bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31 bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32 bits" start="0x1F" />
+      </BitField>
+      <BitField name="FTHLV" description="FIFO threshold level" start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1-data" start="0x0" />
+        <Enum name="B_0x1" description="2-data" start="0x1" />
+        <Enum name="B_0x2" description="3-data" start="0x2" />
+        <Enum name="B_0x3" description="4-data" start="0x3" />
+        <Enum name="B_0x4" description="5-data" start="0x4" />
+        <Enum name="B_0x5" description="6-data" start="0x5" />
+        <Enum name="B_0x6" description="7-data" start="0x6" />
+        <Enum name="B_0x7" description="8-data" start="0x7" />
+        <Enum name="B_0x8" description="9-data" start="0x8" />
+        <Enum name="B_0x9" description="10-data" start="0x9" />
+        <Enum name="B_0xA" description="11-data" start="0xA" />
+        <Enum name="B_0xB" description="12-data" start="0xB" />
+        <Enum name="B_0xC" description="13-data" start="0xC" />
+        <Enum name="B_0xD" description="14-data" start="0xD" />
+        <Enum name="B_0xE" description="15-data" start="0xE" />
+        <Enum name="B_0xF" description="16-data" start="0xF" />
+      </BitField>
+      <BitField name="UDRCFG" description="behavior of slave transmitter at underrun condition" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="slave sends a constant pattern defined by the user at the SPI_UDRDR register" start="0x0" />
+        <Enum name="B_0x1" description="Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0] = 01), all zeros pattern is repeated." start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Rx-DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Rx-DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tx DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="Tx DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCSIZE" description="length of CRC frame to be transacted and compared" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x3" description="4-bits" start="0x3" />
+        <Enum name="B_0x4" description="5-bits" start="0x4" />
+        <Enum name="B_0x5" description="6-bits" start="0x5" />
+        <Enum name="B_0x6" description="7-bits" start="0x6" />
+        <Enum name="B_0x7" description="8-bits" start="0x7" />
+        <Enum name="B_0x1D" description="30-bits" start="0x1D" />
+        <Enum name="B_0x1E" description="31-bits" start="0x1E" />
+        <Enum name="B_0x1F" description="32-bits" start="0x1F" />
+      </BitField>
+      <BitField name="CRCEN" description="hardware CRC computation enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
+      </BitField>
+      <BitField name="MBR" description="master baud rate prescaler setting" start="28" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI master clock/2" start="0x0" />
+        <Enum name="B_0x1" description="SPI master clock/4" start="0x1" />
+        <Enum name="B_0x2" description="SPI master clock/8" start="0x2" />
+        <Enum name="B_0x3" description="SPI master clock/16" start="0x3" />
+        <Enum name="B_0x4" description="SPI master clock/32" start="0x4" />
+        <Enum name="B_0x5" description="SPI master clock/64" start="0x5" />
+        <Enum name="B_0x6" description="SPI master clock/128" start="0x6" />
+        <Enum name="B_0x7" description="SPI master clock/256" start="0x7" />
+      </BitField>
+      <BitField name="BPASS" description="bypass of the prescaler at master baud rate clock generator" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="bypass is disabled" start="0x0" />
+        <Enum name="B_0x1" description="bypass is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_CFG2" description="SPI/I2S configuration register 2" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no extra delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay added" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay added" start="0xF" />
+      </BitField>
+      <BitField name="MIDI" description="master Inter-Data Idleness" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="no delay" start="0x0" />
+        <Enum name="B_0x1" description="1 clock cycle period delay" start="0x1" />
+        <Enum name="B_0xF" description="15 clock cycle periods delay" start="0xF" />
+      </BitField>
+      <BitField name="RDIOM" description="RDY signal input/output management" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)" start="0x0" />
+        <Enum name="B_0x1" description="RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)" start="0x1" />
+      </BitField>
+      <BitField name="RDIOP" description="RDY signal input/output polarity" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="high level of the signal means the slave is ready for communication" start="0x0" />
+        <Enum name="B_0x1" description="low level of the signal means the slave is ready for communication" start="0x1" />
+      </BitField>
+      <BitField name="IOSWP" description="swap functionality of MISO and MOSI pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no swap" start="0x0" />
+        <Enum name="B_0x1" description="MOSI and MISO are swapped" start="0x1" />
+      </BitField>
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="full-duplex" start="0x0" />
+        <Enum name="B_0x1" description="simplex transmitter" start="0x1" />
+        <Enum name="B_0x2" description="simplex receiver" start="0x2" />
+        <Enum name="B_0x3" description="half-duplex" start="0x3" />
+      </BitField>
+      <BitField name="SP" description="serial protocol" start="19" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Motorola" start="0x0" />
+        <Enum name="B_0x1" description="SPI TI" start="0x1" />
+      </BitField>
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI Slave" start="0x0" />
+        <Enum name="B_0x1" description="SPI Master" start="0x1" />
+      </BitField>
+      <BitField name="LSBFRST" description="data frame format" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MSB transmitted first" start="0x0" />
+        <Enum name="B_0x1" description="LSB transmitted first" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="clock phase" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="the second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="clock polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SCK signal is at 0 when idle" start="0x0" />
+        <Enum name="B_0x1" description="SCK signal is at 1 when idle" start="0x1" />
+      </BitField>
+      <BitField name="SSM" description="software management of SS signal input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS input value is determined by the SS PAD" start="0x0" />
+        <Enum name="B_0x1" description="SS input value is determined by the SSI bit" start="0x1" />
+      </BitField>
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="low level is active for SS signal" start="0x0" />
+        <Enum name="B_0x1" description="high level is active for SS signal" start="0x1" />
+      </BitField>
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS output is disabled and the SPI can work in multi-master configuration" start="0x0" />
+        <Enum name="B_0x1" description="SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting" start="0x1" />
+      </BitField>
+      <BitField name="SSOM" description="SS output management in Master mode" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag" start="0x0" />
+        <Enum name="B_0x1" description="SPI data frames are interleaved with SS non active pulses when MIDI[3:0]&gt;1" start="0x1" />
+      </BitField>
+      <BitField name="AFCNTR" description="alternate function GPIOs control" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The peripheral takes no control of GPIOs while it is disabled" start="0x0" />
+        <Enum name="B_0x1" description="The peripheral keeps always control of all associated GPIOs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_IER" description="SPI/I2S interrupt enable register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPIE" description="RXP interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="RXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DXPIE" description="DXP interrupt enabled" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DXP interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="DXP interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOT/SUSP/TXC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOT/SUSP/TXC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TXTF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TXTF interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UDR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="UDR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OVR interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="OVR interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CRCEIE" description="CRC error interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CRC interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CRC interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIFRE interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIFRE interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="MODFIE" description="mode Fault interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MODF interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="MODF interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SPI_SR" description="SPI/I2S status register" start="+0x14" size="4" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="RXP" description="Rx-packet available" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RxFIFO is empty or an incomplete data packet is received" start="0x0" />
+        <Enum name="B_0x1" description="RxFIFO contains at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="TXP" description="Tx-packet space available" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="not enough free space at TxFIFO to host next data packet" start="0x0" />
+        <Enum name="B_0x1" description="enough free space at TxFIFO to host at least one data packet" start="0x1" />
+      </BitField>
+      <BitField name="DXP" description="duplex packet" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TxFIFO is Full and/or RxFIFO is Empty" start="0x0" />
+        <Enum name="B_0x1" description="both TxFIFO has space for write and RxFIFO contains for read a single packet at least" start="0x1" />
+      </BitField>
+      <BitField name="EOT" description="end of transfer" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="transfer is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="transfer complete" start="0x1" />
+      </BitField>
+      <BitField name="TXTF" description="transmission transfer filled" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="upload of TxFIFO is ongoing or not started" start="0x0" />
+        <Enum name="B_0x1" description="TxFIFO upload is finished" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="underrun" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no underrun" start="0x0" />
+        <Enum name="B_0x1" description="underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="overrun" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no overrun" start="0x0" />
+        <Enum name="B_0x1" description="overrun detected" start="0x1" />
+      </BitField>
+      <BitField name="CRCE" description="CRC error" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no CRC error" start="0x0" />
+        <Enum name="B_0x1" description="CRC error detected" start="0x1" />
+      </BitField>
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no TI Frame Error" start="0x0" />
+        <Enum name="B_0x1" description="TI frame error detected" start="0x1" />
+      </BitField>
+      <BitField name="MODF" description="mode fault" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="no mode fault" start="0x0" />
+        <Enum name="B_0x1" description="mode fault detected." start="0x1" />
+      </BitField>
+      <BitField name="SUSP" description="suspension status " start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="SPI not suspended (Master mode active or other mode)." start="0x0" />
+        <Enum name="B_0x1" description="Master mode is suspended (current frame completed)." start="0x1" />
+      </BitField>
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going." start="0x0" />
+        <Enum name="B_0x1" description="last TxFIFO frame transmission complete" start="0x1" />
+      </BitField>
+      <BitField name="RXPLVL" description="RxFIFO packing level " start="13" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="no next frame is available at RxFIFO" start="0x0" />
+        <Enum name="B_0x1" description="1 frame is available" start="0x1" />
+        <Enum name="B_0x2" description="2 frames are available*" start="0x2" />
+        <Enum name="B_0x3" description="3 frames are available*" start="0x3" />
+      </BitField>
+      <BitField name="RXWNE" description="RxFIFO word not empty " start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="less than four bytes of RxFIFO space is occupied by data" start="0x0" />
+        <Enum name="B_0x1" description="at least four bytes of RxFIFO space is occupied by data" start="0x1" />
+      </BitField>
+      <BitField name="CTSIZE" description="number of data frames remaining in current TSIZE session" start="16" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_IFCR" description="SPI/I2S interrupt/status flags clear register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EOTC" description="end of transfer flag clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXTFC" description="transmission transfer filled flag clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="UDRC" description="underrun flag clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="OVRC" description="overrun flag clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="CRCEC" description="CRC error flag clear" start="7" size="1" access="WriteOnly" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" access="WriteOnly" />
+      <BitField name="MODFC" description="mode fault flag clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="SUSPC" description="Suspend flag clear" start="11" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_TXDR" description="SPI/I2S transmit data register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="transmit data register" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="SPI_RXDR" description="SPI/I2S receive data register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="receive data register" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_CRCPOLY" description="SPI/I2S polynomial register" start="+0x40" size="4" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_TXCRC" description="SPI/I2S transmitter CRC register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_RXCRC" description="SPI/I2S receiver CRC register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SPI_UDRDR" description="SPI/I2S underrun data register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="data at slave underrun condition" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SPI_I2SCFGR" description="SPI/I2S configuration register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
+        <Enum name="B_0x1" description="I2S/PCM mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="slave - transmit" start="0x0" />
+        <Enum name="B_0x1" description="slave - receive" start="0x1" />
+        <Enum name="B_0x2" description="master - transmit" start="0x2" />
+        <Enum name="B_0x3" description="master - receive" start="0x3" />
+        <Enum name="B_0x4" description="slave - Full Duplex" start="0x4" />
+        <Enum name="B_0x5" description="master - Full Duplex" start="0x5" />
+      </BitField>
+      <BitField name="I2SSTD" description="Iless thansup&gt;2less than/sup&gt;S standard selection" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Iless thansup&gt;2less than/sup&gt;S Philips standard." start="0x0" />
+        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
+        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
+        <Enum name="B_0x3" description="PCM standard" start="0x3" />
+      </BitField>
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="short frame synchronization" start="0x0" />
+        <Enum name="B_0x1" description="long frame synchronization" start="0x1" />
+      </BitField>
+      <BitField name="DATLEN" description="data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
+        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
+        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
+        <Enum name="B_0x3" description="Not allowed" start="0x3" />
+      </BitField>
+      <BitField name="CHLEN" description="channel length (number of bits per audio channel)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
+        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
+      </BitField>
+      <BitField name="CKPOL" description="serial audio clock polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK." start="0x0" />
+        <Enum name="B_0x1" description="the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK." start="0x1" />
+      </BitField>
+      <BitField name="FIXCH" description="fixed channel length in slave" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set)" start="0x0" />
+        <Enum name="B_0x1" description="the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN)" start="0x1" />
+      </BitField>
+      <BitField name="WSINV" description="word select inversion" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge." start="0x0" />
+        <Enum name="B_0x1" description="In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge." start="0x1" />
+      </BitField>
+      <BitField name="DATFMT" description="data format" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The data inside the SPI_RXDR or SPI_TXDR are right aligned" start="0x0" />
+        <Enum name="B_0x1" description="The data inside the SPI_RXDR or SPI_TXDR are left aligned." start="0x1" />
+      </BitField>
+      <BitField name="I2SDIV" description="Iless thansup&gt;2less than/sup&gt;S linear prescaler" start="16" size="8" access="Read/Write" />
+      <BitField name="ODD" description="odd factor for the prescaler" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
+        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
+      </BitField>
+      <BitField name="MCKOE" description="master clock output enable" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SYSCFG" description="System configuration controller" start="0x46008000">
+    <Register name="SYSCFG_BOOTCR" description="SYSCFG boot pin control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT0_PD" description="BOOT0 pin pull-down disable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down enabled. The BOOT0 pin can be left open and takes a value of 0 if open." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down disabled. The BOOT0 pin must not be left open." start="0x1" />
+      </BitField>
+      <BitField name="BOOT1_PD" description="BOOT1 pin pull-down disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down enabled. The BOOT1 pin can be left open and takes a value of 0 if open." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down disabled. The BOOT1 pin must not be left open." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CM55CR" description="SYSCFG Cortex-M55 control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPU_IT_EN" description="Enable FPU exception" start="0" size="6" access="Read/Write" />
+      <BitField name="LOCKSVTAIRCR" description="Prevent changes to:" start="16" size="1" access="Read/Write" />
+      <BitField name="LOCKNSVTOR" description="Prevent changes to the non-secure vector table base address." start="17" size="1" access="Read/Write" />
+      <BitField name="LOCKSMPU" description="Prevent changes to programmed secure MPU memory regions." start="18" size="1" access="Read/Write" />
+      <BitField name="LOCKNSMPU" description="Prevent changes to non-secure MPU memory regions already programmed." start="19" size="1" access="Read/Write" />
+      <BitField name="LOCKSAU" description="Prevent changes to secure SAU memory regions already programmed." start="20" size="1" access="Read/Write" />
+      <BitField name="LOCKDCAIC" description="Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR." start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55TCMCR" description="SYSCFG Cortex-M55 TCM control register" start="+0x008" size="4" reset_value="0x00000087" reset_mask="0xFFFFFFFF">
+      <BitField name="CFGITCMSZ" description="Select ITCM memory size" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x7" description="64 KB (default value)" start="0x7" />
+        <Enum name="B_0x8" description="128 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="256 Kbytes" start="0x9" />
+      </BitField>
+      <BitField name="CFGDTCMSZ" description="Select DTCM memory size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x8" description="128 Kbytes (default value)" start="0x8" />
+        <Enum name="B_0x9" description="256 Kbytes" start="0x9" />
+      </BitField>
+      <BitField name="LOCKTCM" description="Disable writes to registers associated with the TCM region" start="16" size="1" access="Read/Write" />
+      <BitField name="LOCKITGU" description="Disable writes to registers associated with the ITCM interface security gating." start="17" size="1" access="Read/Write" />
+      <BitField name="LOCKDTGU" description="Disable writes to registers associated with the DTCM interface security gating." start="18" size="1" access="Read/Write" />
+      <BitField name="ITCMWSDISABLE" description="Disable wait-state applied by default on extended ITCM memory." start="23" size="1" access="Read/Write" />
+      <BitField name="DTCMWSDISABLE" description="Disable wait-state applied by default on extended DTCM memory." start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55RWMCR" description="SYSCFG Cortex-CM55 memory RW margin register" start="+0x00C" size="4" reset_value="0x00001020" reset_mask="0xFFFFFFFF">
+      <BitField name="RME_TCM" description="RW margin enable input for TCM memories" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default RW margin settings" start="0x0" />
+        <Enum name="B_0x1" description="Use external pin RW margin setting" start="0x1" />
+      </BitField>
+      <BitField name="RM_TCM" description="External RW margin inputs for TCM memories" start="1" size="4" access="Read/Write" />
+      <BitField name="BC1_TCM" description="Biasing level adjust input recommended for Vnom" start="5" size="1" access="Read/Write" />
+      <BitField name="BC2_TCM" description="Biasing level adjust input recommended for Vnom + 10%" start="6" size="1" access="Read/Write" />
+      <BitField name="RME_CACHE" description="RW margin enable input for caches memories" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default RW margin settings" start="0x0" />
+        <Enum name="B_0x1" description="Use external pin RW margin setting" start="0x1" />
+      </BitField>
+      <BitField name="RM_CACHE" description="External read/write (RW) margin inputs for caches memories" start="8" size="4" access="Read/Write" />
+      <BitField name="BC1_CACHE" description="Biasing level adjust input recommended for Vnom." start="12" size="1" access="Read/Write" />
+      <BitField name="BC2_CACHE" description="Biasing level adjust input recommended for Vnom + 10%" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_INITSVTORCR" description="SYSCFG Cortex-M55 SVTOR control register" start="+0x010" size="4" reset_value="0x18000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVTOR_ADDR" description="Secure vector table base address" start="7" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_INITNSVTORCR" description="SYSCFG Cortex-M55 NSVTOR control register" start="+0x014" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NSVTOR_ADDR" description="Non-secure vector table base address" start="7" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55RSTCR" description="SYSCFG Cortex-M55 reset type control register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CORE_RESET_TYPE" description="Select reset to apply on core upon SYSRESETREQ" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Warm reset (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Power-on reset" start="0x1" />
+      </BitField>
+      <BitField name="LOCKUP_RST_EN" description="Select action to perform on a lockup state on the core" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lockup state shall be recovered from interrupt (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Lockup requests a warm reset to the RCC." start="0x1" />
+      </BitField>
+      <BitField name="LOCKUP_NMI_EN" description="Select action to perform on a lockup state on the core" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lockup state must be recovered from NVIC interrupt (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Lockup generates a NMI on the core." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CM55PAHBWPR" description="SYSCFG Cortex-M55 P-AHB write posting control register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAHB_ERROR_ACK" description="Error capture in write posting buffer" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error capture" start="0x0" />
+        <Enum name="B_0x1" description="Clean error" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VENCRAMCR" description="SYSCFG VENCRAM control register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VENCRAM_EN" description="VENCRAM allocation VENC if active, or to system (if VENC inactive)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM reserved for the VENC" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM available for the system (VENC inactive)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_POTTAMPRSTCR" description="SYSCFG potential tamper reset register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POTTAMPERSETMASK" description="This bit can be set by software to mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA, SAES, CRYP1/2, and HASH reset in case of potential tamper" start="0x0" />
+        <Enum name="B_0x1" description="PKA, SAES, CRYP1/2, and HASH not reset in case of potential tamper" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_ICNEWRCR" description="SYSCFG AHB-AXI bridge early write response control register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC1_EARLY_WR_RSP_ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2_EARLY_WR_RSP_ENABLE" description="None" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="USB1_EARLY_WR_RSP_ENABLE" description="None" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="USB2_EARLY_WR_RSP_ENABLE" description="None" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_ICNCGCR" description="SYSCFG ICN clock gating control register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ICNCGCR" description="When bit[i] is set to 1, ICN clock gating[i] is OFF." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_ICNBWRCR" description="SYSCFG ICN bandwidth regulator control register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ICNBWRCR" description="Bandwidth regulator control bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_IOCR" description="SYSCFG /O control register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOCR" description="Digital or analog pins" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="High-speed mode disabled, or use ADC ANA pin" start="0x0" />
+        <Enum name="B_0x1" description="High-speed mode enabled, or connect internal ADC ANA signal to GPIO" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO1CCCR" description="SYSCFG VDDIO1 compensation cell control register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO1CCSR" description="SYSCFG VDDIO1 compensation cell status register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO2CCCR" description="SYSCFG VDDIO2 compensation cell control register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO2CCSR" description="SYSCFG VDDIO2 compensation cell status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO3CCCR" description="SYSCFG VDDIO3 compensation cell control register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO3CCSR" description="SYSCFG VDDIO3 compensation cell status register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO4CCCR" description="SYSCFG VDDIO4 compensation cell control register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO4CCSR" description="SYSCFG VDDIO4 compensation cell status register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIOCCCR" description="SYSCFG VDDIO compensation cell control register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIO." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO I/O code from the cell (available in the SYSCFG_VDDIOCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O code from RANSRC[3:0] and RAPSRC[3:0]" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIOCCSR" description="SYSCFG VDDIO compensation cell status register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIO" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIO I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CBR" description="SYSCFG control timer break register" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM55L" description="CM55 lockup lock enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="PVDL_LOCK" description="PVD lock enable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE bits can be programmed by the application." start="0x0" />
+        <Enum name="B_0x1" description="PVD interrupt connected to TIM1/8/15/16/17 break input. PVDE and bits are read only." start="0x1" />
+      </BitField>
+      <BitField name="BKPRAML" description="Backup SRAM double ECC error lock " start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup SRAM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Backup SRAM double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="CM55CACHEL" description="CM55 cache double ECC error lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 cache double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 cache double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="CM55TCML" description="CM55 TCM double ECC error lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 TCM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 TCM double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_SEC_AIDCR" description="SYSCFG DMA CID secure control register" start="+0x070" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="DMACID_SEC" description="Secure OS allocates specific CID to DMA channel through these bits." start="0" size="3" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_FMC_RETIMECR" description="SYSCFG FMC retiming logic control register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFG_RETIME_RX" description="Retiming on Rx path" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No retiming on Rx path" start="0x0" />
+        <Enum name="B_0x1" description="Retiming on Rx path" start="0x1" />
+      </BitField>
+      <BitField name="CFG_RETIME_TX" description="Retiming on Tx path" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No retiming on Tx path" start="0x0" />
+        <Enum name="B_0x1" description="Retiming on Tx path" start="0x1" />
+      </BitField>
+      <BitField name="SDFBCLK_180" description="Delay on feedback clock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No delay on the feedback clock" start="0x0" />
+        <Enum name="B_0x1" description="Half a cycle delay on the feedback clock" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_NPU_ICNCR" description="SYSCFG NPU RAM interleaving control register" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERLEAVING_ACTIVE" description="Control interleaving on NPU RAMs" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interleaving disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interleaving enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_BOOTSR" description="SYSCFG boot pin status register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT0" description="BOOT0 pin value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BOOT0 pin connected to VSS (or left open if BOOT0_PD = 0)" start="0x0" />
+        <Enum name="B_0x1" description="BOOT0 pin connected to VDD" start="0x1" />
+      </BitField>
+      <BitField name="BOOT1" description="BOOT1 pin value" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BOOT1 pin connected to VSS (or left open if BOOT1_PD = 0 in SYSCFG_BOOTCR)" start="0x0" />
+        <Enum name="B_0x1" description="BOOT1 pin connected to VDD" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_AHBWP_ERROR_SR" description="SYSCFG AHB write posting address error register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAHB_ERROR_ADDR" description="Reports address of the first error in P-AHB write-posting buffer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SYSCFG_SMPSHDPCR" description="SYSCFG SMPS observable signals through HDP selection configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPSHDPSEL" description="Others: Reserved" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Standard run mode (no HDP)" start="0x0" />
+        <Enum name="B_0xC" description="Analyze fsm mode analysis" start="0xC" />
+        <Enum name="B_0xD" description="Analyze fsm mos analysis" start="0xD" />
+        <Enum name="B_0xE" description="Analyze fsm rampe analysis" start="0xE" />
+        <Enum name="B_0xF" description="Analyze fsm mode analysis" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_NONSEC_AIDCR" description="SYSCFG DMA CID non-secure control register" start="+0x800" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="DMACID_NONSEC" description="Non-secure OS allocates specific CID to DMA channel through these bits" start="0" size="3" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SYSCFG_S" description="System configuration controller" start="0x56008000">
+    <Register name="SYSCFG_BOOTCR" description="SYSCFG boot pin control register" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT0_PD" description="BOOT0 pin pull-down disable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down enabled. The BOOT0 pin can be left open and takes a value of 0 if open." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down disabled. The BOOT0 pin must not be left open." start="0x1" />
+      </BitField>
+      <BitField name="BOOT1_PD" description="BOOT1 pin pull-down disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Pull-down enabled. The BOOT1 pin can be left open and takes a value of 0 if open." start="0x0" />
+        <Enum name="B_0x1" description="Pull-down disabled. The BOOT1 pin must not be left open." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CM55CR" description="SYSCFG Cortex-M55 control register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FPU_IT_EN" description="Enable FPU exception" start="0" size="6" access="Read/Write" />
+      <BitField name="LOCKSVTAIRCR" description="Prevent changes to:" start="16" size="1" access="Read/Write" />
+      <BitField name="LOCKNSVTOR" description="Prevent changes to the non-secure vector table base address." start="17" size="1" access="Read/Write" />
+      <BitField name="LOCKSMPU" description="Prevent changes to programmed secure MPU memory regions." start="18" size="1" access="Read/Write" />
+      <BitField name="LOCKNSMPU" description="Prevent changes to non-secure MPU memory regions already programmed." start="19" size="1" access="Read/Write" />
+      <BitField name="LOCKSAU" description="Prevent changes to secure SAU memory regions already programmed." start="20" size="1" access="Read/Write" />
+      <BitField name="LOCKDCAIC" description="Disable access to the instruction cache direct cache access registers DCAICLR and DCAICRR." start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55TCMCR" description="SYSCFG Cortex-M55 TCM control register" start="+0x008" size="4" reset_value="0x00000087" reset_mask="0xFFFFFFFF">
+      <BitField name="CFGITCMSZ" description="Select ITCM memory size" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x7" description="64 KB (default value)" start="0x7" />
+        <Enum name="B_0x8" description="128 Kbytes" start="0x8" />
+        <Enum name="B_0x9" description="256 Kbytes" start="0x9" />
+      </BitField>
+      <BitField name="CFGDTCMSZ" description="Select DTCM memory size" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x8" description="128 Kbytes (default value)" start="0x8" />
+        <Enum name="B_0x9" description="256 Kbytes" start="0x9" />
+      </BitField>
+      <BitField name="LOCKTCM" description="Disable writes to registers associated with the TCM region" start="16" size="1" access="Read/Write" />
+      <BitField name="LOCKITGU" description="Disable writes to registers associated with the ITCM interface security gating." start="17" size="1" access="Read/Write" />
+      <BitField name="LOCKDTGU" description="Disable writes to registers associated with the DTCM interface security gating." start="18" size="1" access="Read/Write" />
+      <BitField name="ITCMWSDISABLE" description="Disable wait-state applied by default on extended ITCM memory." start="23" size="1" access="Read/Write" />
+      <BitField name="DTCMWSDISABLE" description="Disable wait-state applied by default on extended DTCM memory." start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55RWMCR" description="SYSCFG Cortex-CM55 memory RW margin register" start="+0x00C" size="4" reset_value="0x00001020" reset_mask="0xFFFFFFFF">
+      <BitField name="RME_TCM" description="RW margin enable input for TCM memories" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default RW margin settings" start="0x0" />
+        <Enum name="B_0x1" description="Use external pin RW margin setting" start="0x1" />
+      </BitField>
+      <BitField name="RM_TCM" description="External RW margin inputs for TCM memories" start="1" size="4" access="Read/Write" />
+      <BitField name="BC1_TCM" description="Biasing level adjust input recommended for Vnom" start="5" size="1" access="Read/Write" />
+      <BitField name="BC2_TCM" description="Biasing level adjust input recommended for Vnom + 10%" start="6" size="1" access="Read/Write" />
+      <BitField name="RME_CACHE" description="RW margin enable input for caches memories" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Default RW margin settings" start="0x0" />
+        <Enum name="B_0x1" description="Use external pin RW margin setting" start="0x1" />
+      </BitField>
+      <BitField name="RM_CACHE" description="External read/write (RW) margin inputs for caches memories" start="8" size="4" access="Read/Write" />
+      <BitField name="BC1_CACHE" description="Biasing level adjust input recommended for Vnom." start="12" size="1" access="Read/Write" />
+      <BitField name="BC2_CACHE" description="Biasing level adjust input recommended for Vnom + 10%" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_INITSVTORCR" description="SYSCFG Cortex-M55 SVTOR control register" start="+0x010" size="4" reset_value="0x18000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SVTOR_ADDR" description="Secure vector table base address" start="7" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_INITNSVTORCR" description="SYSCFG Cortex-M55 NSVTOR control register" start="+0x014" size="4" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NSVTOR_ADDR" description="Non-secure vector table base address" start="7" size="25" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_CM55RSTCR" description="SYSCFG Cortex-M55 reset type control register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CORE_RESET_TYPE" description="Select reset to apply on core upon SYSRESETREQ" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Warm reset (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Power-on reset" start="0x1" />
+      </BitField>
+      <BitField name="LOCKUP_RST_EN" description="Select action to perform on a lockup state on the core" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lockup state shall be recovered from interrupt (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Lockup requests a warm reset to the RCC." start="0x1" />
+      </BitField>
+      <BitField name="LOCKUP_NMI_EN" description="Select action to perform on a lockup state on the core" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Lockup state must be recovered from NVIC interrupt (default value)" start="0x0" />
+        <Enum name="B_0x1" description="Lockup generates a NMI on the core." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CM55PAHBWPR" description="SYSCFG Cortex-M55 P-AHB write posting control register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAHB_ERROR_ACK" description="Error capture in write posting buffer" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Error capture" start="0x0" />
+        <Enum name="B_0x1" description="Clean error" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VENCRAMCR" description="SYSCFG VENCRAM control register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VENCRAM_EN" description="VENCRAM allocation VENC if active, or to system (if VENC inactive)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VENCRAM reserved for the VENC" start="0x0" />
+        <Enum name="B_0x1" description="VENCRAM available for the system (VENC inactive)" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_POTTAMPRSTCR" description="SYSCFG potential tamper reset register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POTTAMPERSETMASK" description="This bit can be set by software to mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PKA, SAES, CRYP1/2, and HASH reset in case of potential tamper" start="0x0" />
+        <Enum name="B_0x1" description="PKA, SAES, CRYP1/2, and HASH not reset in case of potential tamper" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_ICNEWRCR" description="SYSCFG AHB-AXI bridge early write response control register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDMMC1_EARLY_WR_RSP_ENABLE" description="None" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="SDMMC2_EARLY_WR_RSP_ENABLE" description="None" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="USB1_EARLY_WR_RSP_ENABLE" description="None" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+      <BitField name="USB2_EARLY_WR_RSP_ENABLE" description="None" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction." start="0x0" />
+        <Enum name="B_0x1" description="Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_ICNCGCR" description="SYSCFG ICN clock gating control register" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ICNCGCR" description="When bit[i] is set to 1, ICN clock gating[i] is OFF." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_ICNBWRCR" description="SYSCFG ICN bandwidth regulator control register" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ICNBWRCR" description="Bandwidth regulator control bits" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_IOCR" description="SYSCFG /O control register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOCR" description="Digital or analog pins" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="High-speed mode disabled, or use ADC ANA pin" start="0x0" />
+        <Enum name="B_0x1" description="High-speed mode enabled, or connect internal ADC ANA signal to GPIO" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO1CCCR" description="SYSCFG VDDIO1 compensation cell control register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO1CCSR" description="SYSCFG VDDIO1 compensation cell status register" start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO2CCCR" description="SYSCFG VDDIO2 compensation cell control register" start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO2CCSR" description="SYSCFG VDDIO2 compensation cell status register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO3CCCR" description="SYSCFG VDDIO3 compensation cell control register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO3CCSR" description="SYSCFG VDDIO3 compensation cell status register" start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO4CCCR" description="SYSCFG VDDIO4 compensation cell control register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIOx." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIO4CCSR" description="SYSCFG VDDIO4 compensation cell status register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIOx" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIOx I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIOx I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIOCCCR" description="SYSCFG VDDIO compensation cell control register" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RANSRC" description="These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="0" size="4" access="Read/Write" />
+      <BitField name="RAPSRC" description="These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1." start="4" size="4" access="Read/Write" />
+      <BitField name="EN" description="Enables the compensation cell of I/Os supplied by VDDIO." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO I/O compensation cell disabled" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O compensation cell enabled" start="0x1" />
+      </BitField>
+      <BitField name="CS" description="Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VDDIO I/O code from the cell (available in the SYSCFG_VDDIOCCSR)" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O code from RANSRC[3:0] and RAPSRC[3:0]" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_VDDIOCCSR" description="SYSCFG VDDIO compensation cell status register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ANSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors." start="0" size="4" access="ReadOnly" />
+      <BitField name="APSRC" description="This value is provided by the cell, and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors." start="4" size="4" access="ReadOnly" />
+      <BitField name="READY" description="Provides the compensation cell status of I/Os supplied by VDDIO" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="VDDIO I/O compensation cell not ready" start="0x0" />
+        <Enum name="B_0x1" description="VDDIO I/O compensation cell ready" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_CBR" description="SYSCFG control timer break register" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM55L" description="CM55 lockup lock enable " start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="PVDL_LOCK" description="PVD lock enable " start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE bits can be programmed by the application." start="0x0" />
+        <Enum name="B_0x1" description="PVD interrupt connected to TIM1/8/15/16/17 break input. PVDE and bits are read only." start="0x1" />
+      </BitField>
+      <BitField name="BKPRAML" description="Backup SRAM double ECC error lock " start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup SRAM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Backup SRAM double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="CM55CACHEL" description="CM55 cache double ECC error lock" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 cache double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 cache double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+      <BitField name="CM55TCML" description="CM55 TCM double ECC error lock" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Cortex-M55 TCM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs" start="0x0" />
+        <Enum name="B_0x1" description="Cortex-M55 TCM double ECC error signal connected to TIM1/8/15/16/17 break inputs" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_SEC_AIDCR" description="SYSCFG DMA CID secure control register" start="+0x070" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="DMACID_SEC" description="Secure OS allocates specific CID to DMA channel through these bits." start="0" size="3" access="Read/Write" />
+    </Register>
+    <Register name="SYSCFG_FMC_RETIMECR" description="SYSCFG FMC retiming logic control register" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFG_RETIME_RX" description="Retiming on Rx path" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No retiming on Rx path" start="0x0" />
+        <Enum name="B_0x1" description="Retiming on Rx path" start="0x1" />
+      </BitField>
+      <BitField name="CFG_RETIME_TX" description="Retiming on Tx path" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No retiming on Tx path" start="0x0" />
+        <Enum name="B_0x1" description="Retiming on Tx path" start="0x1" />
+      </BitField>
+      <BitField name="SDFBCLK_180" description="Delay on feedback clock" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No delay on the feedback clock" start="0x0" />
+        <Enum name="B_0x1" description="Half a cycle delay on the feedback clock" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_NPU_ICNCR" description="SYSCFG NPU RAM interleaving control register" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERLEAVING_ACTIVE" description="Control interleaving on NPU RAMs" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interleaving disabled" start="0x0" />
+        <Enum name="B_0x1" description="Interleaving enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_BOOTSR" description="SYSCFG boot pin status register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT0" description="BOOT0 pin value" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BOOT0 pin connected to VSS (or left open if BOOT0_PD = 0)" start="0x0" />
+        <Enum name="B_0x1" description="BOOT0 pin connected to VDD" start="0x1" />
+      </BitField>
+      <BitField name="BOOT1" description="BOOT1 pin value" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="BOOT1 pin connected to VSS (or left open if BOOT1_PD = 0 in SYSCFG_BOOTCR)" start="0x0" />
+        <Enum name="B_0x1" description="BOOT1 pin connected to VDD" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_AHBWP_ERROR_SR" description="SYSCFG AHB write posting address error register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PAHB_ERROR_ADDR" description="Reports address of the first error in P-AHB write-posting buffer" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="SYSCFG_SMPSHDPCR" description="SYSCFG SMPS observable signals through HDP selection configuration register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMPSHDPSEL" description="Others: Reserved" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Standard run mode (no HDP)" start="0x0" />
+        <Enum name="B_0xC" description="Analyze fsm mode analysis" start="0xC" />
+        <Enum name="B_0xD" description="Analyze fsm mos analysis" start="0xD" />
+        <Enum name="B_0xE" description="Analyze fsm rampe analysis" start="0xE" />
+        <Enum name="B_0xF" description="Analyze fsm mode analysis" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="SYSCFG_NONSEC_AIDCR" description="SYSCFG DMA CID non-secure control register" start="+0x800" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="DMACID_NONSEC" description="Non-secure OS allocates specific CID to DMA channel through these bits" start="0" size="3" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TAMP" description="Tamper and backup registers" start="0x46004400">
+    <Register name="TAMP_CR1" description="TAMP control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1E" description="Tamper detection on TAMP_IN1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN1 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN1 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2E" description="Tamper detection on TAMP_IN2 enableless thansup&gt;(1)less than/sup&gt;" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN2 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN2 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3E" description="Tamper detection on TAMP_IN3 enableless thansup&gt;(1)less than/sup&gt;" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN3 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN3 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4E" description="Tamper detection on TAMP_IN4 enableless thansup&gt;(1)less than/sup&gt;" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN4 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN4 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5E" description="Tamper detection on TAMP_IN5 enableless thansup&gt;(1)less than/sup&gt;" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN5 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN5 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6E" description="Tamper detection on TAMP_IN6 enableless thansup&gt;(1)less than/sup&gt;" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN6 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN6 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7E" description="Tamper detection on TAMP_IN7 enableless thansup&gt;(1)less than/sup&gt;" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN7 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN7 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP1E" description="Internal tamper 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2E" description="Internal tamper 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3E" description="Internal tamper 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4E" description="Internal tamper 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5E" description="Internal tamper 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6E" description="Internal tamper 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7E" description="Internal tamper 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8E" description="Internal tamper 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9E" description="Internal tamper 9 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11E" description="Internal tamper 11 enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_CR2" description="TAMP control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1POM" description="Tamper 1 potential mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 event detection is in confirmed mode." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 event detection is in potential mode." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2POM" description="Tamper 2 potential mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3POM" description="Tamper 3 potential mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4POM" description="Tamper 4 potential mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5POM" description="Tamper 5 potential mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6POM" description="Tamper 6 potential mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7POM" description="Tamper 7 potential mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP1MSK" description="Tamper 1 mask" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2MSK" description="Tamper 2 mask" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3MSK" description="Tamper 3 mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="BKBLOCK" description="Backup registers and device secretsless thansup&gt;(1)less than/sup&gt; access blocked" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="backup registers and device secretsless thansup&gt;(1)less than/sup&gt; can be accessed if no tamper flag is set" start="0x0" />
+        <Enum name="B_0x1" description="backup registers and device secretsless thansup&gt;(1)less than/sup&gt; cannot be accessed" start="0x1" />
+      </BitField>
+      <BitField name="BKERASE" description="Backup registers and device secretsless thansup&gt;(1)less than/sup&gt; erase" start="23" size="1" access="WriteOnly" />
+      <BitField name="TAMP1TRG" description="Active level for tamper 1 input" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 1 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 1 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2TRG" description="Active level for tamper 2 input" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 2 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 2 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3TRG" description="Active level for tamper 3 input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 3 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 3 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4TRG" description="Active level for tamper 4 input (active mode disabled)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 4 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 4 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5TRG" description="Active level for tamper 5 input (active mode disabled)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 5 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 5 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6TRG" description="Active level for tamper 6 input (active mode disabled)" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 6 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 6 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7TRG" description="Active level for tamper 7 input (active mode disabled)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 7 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 7 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_CR3" description="TAMP control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ITAMP1POM" description="Internal tamper 1 potential mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2POM" description="Internal tamper 2 potential mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3POM" description="Internal tamper 3 potential mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4POM" description="Internal tamper 4 potential mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5POM" description="Internal tamper 5 potential mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6POM" description="Internal tamper 6 potential mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 event detection is in confirmed mode." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 event detection is in potential mode." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7POM" description="Internal tamper 7 potential mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8POM" description="Internal tamper 8 potential mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9POM" description="Internal tamper 9 potential mode" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11POM" description="Internal tamper 11 potential mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_FLTCR" description="TAMP filter control register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMPFREQ" description="Tamper sampling frequency" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)" start="0x0" />
+        <Enum name="B_0x1" description="RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)" start="0x1" />
+        <Enum name="B_0x2" description="RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)" start="0x2" />
+        <Enum name="B_0x3" description="RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)" start="0x3" />
+        <Enum name="B_0x4" description="RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)" start="0x4" />
+        <Enum name="B_0x5" description="RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)" start="0x5" />
+        <Enum name="B_0x6" description="RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)" start="0x6" />
+        <Enum name="B_0x7" description="RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" start="0x7" />
+      </BitField>
+      <BitField name="TAMPFLT" description="TAMP_INx filter count" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)." start="0x0" />
+        <Enum name="B_0x1" description="Tamper event is activated after 2 consecutive samples at the active level." start="0x1" />
+        <Enum name="B_0x2" description="Tamper event is activated after 4 consecutive samples at the active level." start="0x2" />
+        <Enum name="B_0x3" description="Tamper event is activated after 8 consecutive samples at the active level." start="0x3" />
+      </BitField>
+      <BitField name="TAMPPRCH" description="TAMP_INx precharge duration" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 RTCCLK cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 RTCCLK cycles" start="0x1" />
+        <Enum name="B_0x2" description="4 RTCCLK cycles" start="0x2" />
+        <Enum name="B_0x3" description="8 RTCCLK cycles" start="0x3" />
+      </BitField>
+      <BitField name="TAMPPUDIS" description="TAMP_INx pull-up disable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Precharge TAMP_INx pins before sampling (enable internal pull-up)" start="0x0" />
+        <Enum name="B_0x1" description="Disable precharge of TAMP_INx pins." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_ATCR1" description="TAMP active tamper control register 1" start="+0x10" size="4" reset_value="0x00070000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1AM" description="Tamper 1 active mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2AM" description="Tamper 2 active mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3AM" description="Tamper 3 active mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4AM" description="Tamper 4 active mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5AM" description="Tamper 5 active mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6AM" description="Tamper 6 active mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7AM" description="Tamper 7 active mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="ATOSEL1" description="Active tamper shared output 1 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL1 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL1 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL1 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL1 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL2" description="Active tamper shared output 2 selection" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL2 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL2 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL2 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL2 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL3" description="Active tamper shared output 3 selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL3 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL3 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL3 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL3 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL4" description="Active tamper shared output 4 selection" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL4 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL4 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL4 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL4 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATCKSEL" description="Active tamper RTC asynchronous prescaler clock selection" start="16" size="4" access="Read/Write" />
+      <BitField name="ATPER" description="Active tamper output change period" start="24" size="3" access="Read/Write" />
+      <BitField name="ATOSHARE" description="Active tamper output sharing" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Each active tamper input TAMP_INi is compared with its dedicated output TAMP_OUTi" start="0x0" />
+        <Enum name="B_0x1" description="Each active tamper input TAMP_INi is compared with TAMPOUTSELi defined by ATOSELi bits." start="0x1" />
+      </BitField>
+      <BitField name="FLTEN" description="Active tamper filter enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Active tamper filtering disable" start="0x0" />
+        <Enum name="B_0x1" description="Active tamper filtering enable: a tamper event is detected when 2 comparison mismatches occur out of 4 consecutive samples." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_ATSEEDR" description="TAMP active tamper seed register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEED" description="Pseudo-random generator seed value" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="TAMP_ATOR" description="TAMP active tamper output register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRNG" description="Pseudo-random generator value" start="0" size="8" access="ReadOnly" />
+      <BitField name="SEEDF" description="Seed running flag " start="14" size="1" access="ReadOnly" />
+      <BitField name="INITS" description="Active tamper initialization status" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_ATCR2" description="TAMP active tamper control register 2" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATOSEL1" description="Active tamper shared output 1 selection" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL1 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL1 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL1 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL1 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL1 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL1 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL1 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL1 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL2" description="Active tamper shared output 2 selection" start="11" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL2 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL2 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL2 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL2 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL2 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL2 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL2 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL2 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL3" description="Active tamper shared output 3 selection" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL3 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL3 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL3 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL3 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL3 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL3 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL3 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL3 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL4" description="Active tamper shared output 4 selection" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL4 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL4 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL4 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL4 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL4 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL4 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL4 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL4 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL5" description="Active tamper shared output 5 selection" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL5 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL5 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL5 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL5 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL5 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL5 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL5 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL5 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL6" description="Active tamper shared output 6 selection" start="23" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL6 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL6 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL6 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL6 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL6 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL6 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL6 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL6 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL7" description="Active tamper shared output 7 selection" start="26" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL7 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL7 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL7 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL7 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL7 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL7 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL7 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL7 = TAMP_OUT8" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_SECCFGR" description="TAMP secure configuration register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKPRWSEC" description="Backup registers read/write protection offset" start="0" size="8" access="Read/Write" />
+      <BitField name="CNT1SEC" description="Monotonic counter 1 secure protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="BKPWSEC" description="Backup registers write protection offset" start="16" size="8" access="Read/Write" />
+      <BitField name="BHKLOCK" description="Boot hardware key lock" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The Backup registers from TAMP_BKP0R to TAMP_BKP7R can be accessed according to the Protection zone they belong to." start="0x0" />
+        <Enum name="B_0x1" description="The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in read nor in write (they are read as 0 and write ignore)." start="0x1" />
+      </BitField>
+      <BitField name="TAMPSEC" description="Tamper protection (excluding monotonic counters and backup registers)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper configuration and interrupt can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Tamper configuration and interrupt can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_PRIVCFGR" description="TAMP privilege configuration register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT1PRIV" description="Monotonic counter 1 privilege protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="BKPRWPRIV" description="Backup registers zone 1 privilege protection" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup registers zone 1 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Backup registers zone 1 can be read and written only with privileged access" start="0x1" />
+      </BitField>
+      <BitField name="BKPWPRIV" description="Backup registers zone 2 privilege protection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup registers zone 2 can be written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Backup registers zone 2 can be written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="TAMPPRIV" description="Tamper privilege protection (excluding backup registers)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper configuration and interrupt can be written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Tamper configuration and interrupt can be written only with privileged access." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_IER" description="TAMP interrupt enable register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1IE" description="Tamper 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2IE" description="Tamper 2 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3IE" description="Tamper 3 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 interrupt enabled.." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4IE" description="Tamper 4 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5IE" description="Tamper 5 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6IE" description="Tamper 6 interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7IE" description="Tamper 7interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP1IE" description="Internal tamper 1 interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2IE" description="Internal tamper 2 interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3IE" description="Internal tamper 3 interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4IE" description="Internal tamper 4 interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5IE" description="Internal tamper 5 interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6IE" description="Internal tamper 6 interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7IE" description="Internal tamper 7 interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8IE" description="Internal tamper 8 interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9IE" description="Internal tamper 9 interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11IE" description="Internal tamper 11 interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_SR" description="TAMP status register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1F" description="TAMP1 detection flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2F" description="TAMP2 detection flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3F" description="TAMP3 detection flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4F" description="TAMP4 detection flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5F" description="TAMP5 detection flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6F" description="TAMP6 detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7F" description="TAMP7 detection flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1F" description="Internal tamper 1 flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2F" description="Internal tamper 2 flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3F" description="Internal tamper 3 flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4F" description="Internal tamper 4 flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5F" description="Internal tamper 5 flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6F" description="Internal tamper 6 flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7F" description="Internal tamper 7 flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8F" description="Internal tamper 8 flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9F" description="Internal tamper 9 flag " start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11F" description="Internal tamper 11 flag " start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_MISR" description="TAMP non-secure masked interrupt status register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1MF" description="TAMP1 non-secure interrupt masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2MF" description="TAMP2 non-secure interrupt masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3MF" description="TAMP3 non-secure interrupt masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4MF" description="TAMP4 non-secure interrupt masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5MF" description="TAMP5 non-secure interrupt masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6MF" description="TAMP6 non-secure interrupt masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7MF" description="TAMP7 non-secure interrupt masked flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1MF" description="Internal tamper 1 non-secure interrupt masked flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2MF" description="Internal tamper 2 non-secure interrupt masked flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3MF" description="Internal tamper 3 non-secure interrupt masked flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4MF" description="Internal tamper 4 non-secure interrupt masked flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5MF" description="Internal tamper 5 non-secure interrupt masked flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6MF" description="Internal tamper 6 non-secure interrupt masked flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7MF" description="Internal tamper 7 tamper non-secure interrupt masked flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8MF" description="Internal tamper 8 non-secure interrupt masked flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9MF" description="internal tamper 9 non-secure interrupt masked flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11MF" description="internal tamper 11 non-secure interrupt masked flag" start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_SMISR" description="TAMP secure masked interrupt status register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1MF" description="TAMP1 secure interrupt masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2MF" description="TAMP2 secure interrupt masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3MF" description="TAMP3 secure interrupt masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4MF" description="TAMP4 secure interrupt masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5MF" description="TAMP5 secure interrupt masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6MF" description="TAMP6 secure interrupt masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7MF" description="TAMP7 secure interrupt masked flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1MF" description="Internal tamper 1 secure interrupt masked flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2MF" description="Internal tamper 2 secure interrupt masked flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3MF" description="Internal tamper 3 secure interrupt masked flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4MF" description="Internal tamper 4 secure interrupt masked flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5MF" description="Internal tamper 5 secure interrupt masked flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6MF" description="Internal tamper 6 secure interrupt masked flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7MF" description="Internal tamper 7 secure interrupt masked flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8MF" description="Internal tamper 8 secure interrupt masked flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9MF" description="internal tamper 9 secure interrupt masked flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11MF" description="internal tamper 11 secure interrupt masked flag" start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_SCR" description="TAMP status clear register" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTAMP1F" description="Clear TAMP1 detection flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTAMP2F" description="Clear TAMP2 detection flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CTAMP3F" description="Clear TAMP3 detection flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CTAMP4F" description="Clear TAMP4 detection flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTAMP5F" description="Clear TAMP5 detection flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CTAMP6F" description="Clear TAMP6 detection flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CTAMP7F" description="Clear TAMP7 detection flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CITAMP1F" description="Clear ITAMP1 detection flag" start="16" size="1" access="WriteOnly" />
+      <BitField name="CITAMP2F" description="Clear ITAMP2 detection flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="CITAMP3F" description="Clear ITAMP3 detection flag" start="18" size="1" access="WriteOnly" />
+      <BitField name="CITAMP4F" description="Clear ITAMP4 detection flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="CITAMP5F" description="Clear ITAMP5 detection flag" start="20" size="1" access="WriteOnly" />
+      <BitField name="CITAMP6F" description="Clear ITAMP6 detection flag" start="21" size="1" access="WriteOnly" />
+      <BitField name="CITAMP7F" description="Clear ITAMP7 detection flag" start="22" size="1" access="WriteOnly" />
+      <BitField name="CITAMP8F" description="Clear ITAMP8 detection flag" start="23" size="1" access="WriteOnly" />
+      <BitField name="CITAMP9F" description="Clear ITAMP9 detection flag" start="24" size="1" access="WriteOnly" />
+      <BitField name="CITAMP11F" description="Clear ITAMP11 detection flag" start="26" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="TAMP_COUNT1R" description="TAMP monotonic counter 1 register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_OR" description="TAMP option register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VCOREMEN" description="Vless thansub&gt;COREless than/sub&gt; monitoring" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;COREless than/sub&gt; monitoring disable" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;COREless than/sub&gt; monitoring enable" start="0x1" />
+      </BitField>
+      <BitField name="BSEN" description="Boundary scan enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boundary scan is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boundary scan is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_RPCFGR" description="TAMP resources protection configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPCFG0" description="Configurable resource 0 protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Resource 0 is not included in the device secrets protected by TAMP peripheral" start="0x0" />
+        <Enum name="B_0x1" description="Resource 0 is included in the device secrets protected by TAMP peripheral" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_BKP0R" description="TAMP backup 0 register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP1R" description="TAMP backup 1 register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP2R" description="TAMP backup 2 register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP3R" description="TAMP backup 3 register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP4R" description="TAMP backup 4 register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP5R" description="TAMP backup 5 register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP6R" description="TAMP backup 6 register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP7R" description="TAMP backup 7 register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP8R" description="TAMP backup 8 register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP9R" description="TAMP backup 9 register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP10R" description="TAMP backup 10 register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP11R" description="TAMP backup 11 register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP12R" description="TAMP backup 12 register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP13R" description="TAMP backup 13 register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP14R" description="TAMP backup 14 register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP15R" description="TAMP backup 15 register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP16R" description="TAMP backup 16 register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP17R" description="TAMP backup 17 register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP18R" description="TAMP backup 18 register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP19R" description="TAMP backup 19 register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP20R" description="TAMP backup 20 register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP21R" description="TAMP backup 21 register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP22R" description="TAMP backup 22 register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP23R" description="TAMP backup 23 register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP24R" description="TAMP backup 24 register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP25R" description="TAMP backup 25 register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP26R" description="TAMP backup 26 register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP27R" description="TAMP backup 27 register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP28R" description="TAMP backup 28 register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP29R" description="TAMP backup 29 register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP30R" description="TAMP backup 30 register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP31R" description="TAMP backup 31 register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TAMP_S" description="Tamper and backup registers" start="0x56004400">
+    <Register name="TAMP_CR1" description="TAMP control register 1" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1E" description="Tamper detection on TAMP_IN1 enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN1 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN1 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2E" description="Tamper detection on TAMP_IN2 enableless thansup&gt;(1)less than/sup&gt;" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN2 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN2 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3E" description="Tamper detection on TAMP_IN3 enableless thansup&gt;(1)less than/sup&gt;" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN3 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN3 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4E" description="Tamper detection on TAMP_IN4 enableless thansup&gt;(1)less than/sup&gt;" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN4 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN4 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5E" description="Tamper detection on TAMP_IN5 enableless thansup&gt;(1)less than/sup&gt;" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN5 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN5 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6E" description="Tamper detection on TAMP_IN6 enableless thansup&gt;(1)less than/sup&gt;" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN6 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN6 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7E" description="Tamper detection on TAMP_IN7 enableless thansup&gt;(1)less than/sup&gt;" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper detection on TAMP_IN7 is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper detection on TAMP_IN7 is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP1E" description="Internal tamper 1 enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2E" description="Internal tamper 2 enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3E" description="Internal tamper 3 enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4E" description="Internal tamper 4 enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5E" description="Internal tamper 5 enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6E" description="Internal tamper 6 enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7E" description="Internal tamper 7 enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8E" description="Internal tamper 8 enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9E" description="Internal tamper 9 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11E" description="Internal tamper 11 enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_CR2" description="TAMP control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1POM" description="Tamper 1 potential mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 event detection is in confirmed mode." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 event detection is in potential mode." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2POM" description="Tamper 2 potential mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3POM" description="Tamper 3 potential mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4POM" description="Tamper 4 potential mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5POM" description="Tamper 5 potential mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6POM" description="Tamper 6 potential mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7POM" description="Tamper 7 potential mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="TAMP1MSK" description="Tamper 1 mask" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2MSK" description="Tamper 2 mask" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3MSK" description="Tamper 3 mask" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secretsless thansup&gt;(1)less than/sup&gt; are not erased." start="0x1" />
+      </BitField>
+      <BitField name="BKBLOCK" description="Backup registers and device secretsless thansup&gt;(1)less than/sup&gt; access blocked" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="backup registers and device secretsless thansup&gt;(1)less than/sup&gt; can be accessed if no tamper flag is set" start="0x0" />
+        <Enum name="B_0x1" description="backup registers and device secretsless thansup&gt;(1)less than/sup&gt; cannot be accessed" start="0x1" />
+      </BitField>
+      <BitField name="BKERASE" description="Backup registers and device secretsless thansup&gt;(1)less than/sup&gt; erase" start="23" size="1" access="WriteOnly" />
+      <BitField name="TAMP1TRG" description="Active level for tamper 1 input" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 1 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 1 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2TRG" description="Active level for tamper 2 input" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 2 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 2 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3TRG" description="Active level for tamper 3 input" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 3 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 3 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4TRG" description="Active level for tamper 4 input (active mode disabled)" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 4 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 4 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5TRG" description="Active level for tamper 5 input (active mode disabled)" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 5 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 5 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6TRG" description="Active level for tamper 6 input (active mode disabled)" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 6 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 6 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7TRG" description="Active level for tamper 7 input (active mode disabled)" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="If TAMPFLT different to 00 tamper 7 input staying low triggers a tamper detection event." start="0x0" />
+        <Enum name="B_0x1" description="If TAMPFLT different to 00 tamper 7 input staying high triggers a tamper detection event." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_CR3" description="TAMP control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ITAMP1POM" description="Internal tamper 1 potential mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2POM" description="Internal tamper 2 potential mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3POM" description="Internal tamper 3 potential mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4POM" description="Internal tamper 4 potential mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5POM" description="Internal tamper 5 potential mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6POM" description="Internal tamper 6 potential mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 event detection is in confirmed mode." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 event detection is in potential mode." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7POM" description="Internal tamper 7 potential mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8POM" description="Internal tamper 8 potential mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9POM" description="Internal tamper 9 potential mode" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11POM" description="Internal tamper 11 potential mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 event detection is in confirmed modeless thansup&gt;(1)less than/sup&gt;." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 event detection is in potential modeless thansup&gt;(2)less than/sup&gt;." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_FLTCR" description="TAMP filter control register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMPFREQ" description="Tamper sampling frequency" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)" start="0x0" />
+        <Enum name="B_0x1" description="RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)" start="0x1" />
+        <Enum name="B_0x2" description="RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)" start="0x2" />
+        <Enum name="B_0x3" description="RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)" start="0x3" />
+        <Enum name="B_0x4" description="RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)" start="0x4" />
+        <Enum name="B_0x5" description="RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)" start="0x5" />
+        <Enum name="B_0x6" description="RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)" start="0x6" />
+        <Enum name="B_0x7" description="RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" start="0x7" />
+      </BitField>
+      <BitField name="TAMPFLT" description="TAMP_INx filter count" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)." start="0x0" />
+        <Enum name="B_0x1" description="Tamper event is activated after 2 consecutive samples at the active level." start="0x1" />
+        <Enum name="B_0x2" description="Tamper event is activated after 4 consecutive samples at the active level." start="0x2" />
+        <Enum name="B_0x3" description="Tamper event is activated after 8 consecutive samples at the active level." start="0x3" />
+      </BitField>
+      <BitField name="TAMPPRCH" description="TAMP_INx precharge duration" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 RTCCLK cycle" start="0x0" />
+        <Enum name="B_0x1" description="2 RTCCLK cycles" start="0x1" />
+        <Enum name="B_0x2" description="4 RTCCLK cycles" start="0x2" />
+        <Enum name="B_0x3" description="8 RTCCLK cycles" start="0x3" />
+      </BitField>
+      <BitField name="TAMPPUDIS" description="TAMP_INx pull-up disable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Precharge TAMP_INx pins before sampling (enable internal pull-up)" start="0x0" />
+        <Enum name="B_0x1" description="Disable precharge of TAMP_INx pins." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_ATCR1" description="TAMP active tamper control register 1" start="+0x10" size="4" reset_value="0x00070000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1AM" description="Tamper 1 active mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2AM" description="Tamper 2 active mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3AM" description="Tamper 3 active mode" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4AM" description="Tamper 4 active mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5AM" description="Tamper 5 active mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6AM" description="Tamper 6 active mode" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7AM" description="Tamper 7 active mode" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 detection mode is passive." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7 detection mode is active." start="0x1" />
+      </BitField>
+      <BitField name="ATOSEL1" description="Active tamper shared output 1 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL1 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL1 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL1 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL1 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL2" description="Active tamper shared output 2 selection" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL2 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL2 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL2 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL2 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL3" description="Active tamper shared output 3 selection" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL3 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL3 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL3 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL3 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATOSEL4" description="Active tamper shared output 4 selection" start="14" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL4 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL4 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL4 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL4 = TAMP_OUT4" start="0x3" />
+      </BitField>
+      <BitField name="ATCKSEL" description="Active tamper RTC asynchronous prescaler clock selection" start="16" size="4" access="Read/Write" />
+      <BitField name="ATPER" description="Active tamper output change period" start="24" size="3" access="Read/Write" />
+      <BitField name="ATOSHARE" description="Active tamper output sharing" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Each active tamper input TAMP_INi is compared with its dedicated output TAMP_OUTi" start="0x0" />
+        <Enum name="B_0x1" description="Each active tamper input TAMP_INi is compared with TAMPOUTSELi defined by ATOSELi bits." start="0x1" />
+      </BitField>
+      <BitField name="FLTEN" description="Active tamper filter enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Active tamper filtering disable" start="0x0" />
+        <Enum name="B_0x1" description="Active tamper filtering enable: a tamper event is detected when 2 comparison mismatches occur out of 4 consecutive samples." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_ATSEEDR" description="TAMP active tamper seed register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEED" description="Pseudo-random generator seed value" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="TAMP_ATOR" description="TAMP active tamper output register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRNG" description="Pseudo-random generator value" start="0" size="8" access="ReadOnly" />
+      <BitField name="SEEDF" description="Seed running flag " start="14" size="1" access="ReadOnly" />
+      <BitField name="INITS" description="Active tamper initialization status" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_ATCR2" description="TAMP active tamper control register 2" start="+0x1C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATOSEL1" description="Active tamper shared output 1 selection" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL1 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL1 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL1 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL1 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL1 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL1 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL1 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL1 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL2" description="Active tamper shared output 2 selection" start="11" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL2 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL2 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL2 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL2 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL2 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL2 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL2 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL2 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL3" description="Active tamper shared output 3 selection" start="14" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL3 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL3 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL3 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL3 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL3 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL3 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL3 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL3 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL4" description="Active tamper shared output 4 selection" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL4 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL4 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL4 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL4 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL4 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL4 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL4 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL4 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL5" description="Active tamper shared output 5 selection" start="20" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL5 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL5 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL5 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL5 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL5 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL5 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL5 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL5 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL6" description="Active tamper shared output 6 selection" start="23" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL6 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL6 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL6 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL6 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL6 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL6 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL6 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL6 = TAMP_OUT8" start="0x7" />
+      </BitField>
+      <BitField name="ATOSEL7" description="Active tamper shared output 7 selection" start="26" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TAMPOUTSEL7 = TAMP_OUT1" start="0x0" />
+        <Enum name="B_0x1" description="TAMPOUTSEL7 = TAMP_OUT2" start="0x1" />
+        <Enum name="B_0x2" description="TAMPOUTSEL7 = TAMP_OUT3" start="0x2" />
+        <Enum name="B_0x3" description="TAMPOUTSEL7 = TAMP_OUT4" start="0x3" />
+        <Enum name="B_0x4" description="TAMPOUTSEL7 = TAMP_OUT5" start="0x4" />
+        <Enum name="B_0x5" description="TAMPOUTSEL7 = TAMP_OUT6" start="0x5" />
+        <Enum name="B_0x6" description="TAMPOUTSEL7 = TAMP_OUT7" start="0x6" />
+        <Enum name="B_0x7" description="TAMPOUTSEL7 = TAMP_OUT8" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_SECCFGR" description="TAMP secure configuration register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKPRWSEC" description="Backup registers read/write protection offset" start="0" size="8" access="Read/Write" />
+      <BitField name="CNT1SEC" description="Monotonic counter 1 secure protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is secure." start="0x1" />
+      </BitField>
+      <BitField name="BKPWSEC" description="Backup registers write protection offset" start="16" size="8" access="Read/Write" />
+      <BitField name="BHKLOCK" description="Boot hardware key lock" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The Backup registers from TAMP_BKP0R to TAMP_BKP7R can be accessed according to the Protection zone they belong to." start="0x0" />
+        <Enum name="B_0x1" description="The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in read nor in write (they are read as 0 and write ignore)." start="0x1" />
+      </BitField>
+      <BitField name="TAMPSEC" description="Tamper protection (excluding monotonic counters and backup registers)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper configuration and interrupt can be written when the APB access is secure or non-secure." start="0x0" />
+        <Enum name="B_0x1" description="Tamper configuration and interrupt can be written only when the APB access is secure." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_PRIVCFGR" description="TAMP privilege configuration register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT1PRIV" description="Monotonic counter 1 privilege protection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is privileged or non-privileged." start="0x0" />
+        <Enum name="B_0x1" description="Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is privileged." start="0x1" />
+      </BitField>
+      <BitField name="BKPRWPRIV" description="Backup registers zone 1 privilege protection" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup registers zone 1 can be read and written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Backup registers zone 1 can be read and written only with privileged access" start="0x1" />
+      </BitField>
+      <BitField name="BKPWPRIV" description="Backup registers zone 2 privilege protection" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Backup registers zone 2 can be written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Backup registers zone 2 can be written only with privileged access." start="0x1" />
+      </BitField>
+      <BitField name="TAMPPRIV" description="Tamper privilege protection (excluding backup registers)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper configuration and interrupt can be written with privileged or unprivileged access." start="0x0" />
+        <Enum name="B_0x1" description="Tamper configuration and interrupt can be written only with privileged access." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_IER" description="TAMP interrupt enable register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1IE" description="Tamper 1 interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP2IE" description="Tamper 2 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP3IE" description="Tamper 3 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 3 interrupt enabled.." start="0x1" />
+      </BitField>
+      <BitField name="TAMP4IE" description="Tamper 4 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP5IE" description="Tamper 5 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 5 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 5 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP6IE" description="Tamper 6 interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 6 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 6 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TAMP7IE" description="Tamper 7interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Tamper 7 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Tamper 7interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP1IE" description="Internal tamper 1 interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="ITAMP2IE" description="Internal tamper 2 interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP3IE" description="Internal tamper 3 interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP4IE" description="Internal tamper 4 interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP5IE" description="Internal tamper 5 interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 5 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 5 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP6IE" description="Internal tamper 6 interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 6 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 6 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP7IE" description="Internal tamper 7 interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 7 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 7 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP8IE" description="Internal tamper 8 interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 8 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 8 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP9IE" description="Internal tamper 9 interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 9 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 9 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="ITAMP11IE" description="Internal tamper 11 interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal tamper 11 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Internal tamper 11 interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_SR" description="TAMP status register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1F" description="TAMP1 detection flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2F" description="TAMP2 detection flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3F" description="TAMP3 detection flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4F" description="TAMP4 detection flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5F" description="TAMP5 detection flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6F" description="TAMP6 detection flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7F" description="TAMP7 detection flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1F" description="Internal tamper 1 flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2F" description="Internal tamper 2 flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3F" description="Internal tamper 3 flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4F" description="Internal tamper 4 flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5F" description="Internal tamper 5 flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6F" description="Internal tamper 6 flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7F" description="Internal tamper 7 flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8F" description="Internal tamper 8 flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9F" description="Internal tamper 9 flag " start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11F" description="Internal tamper 11 flag " start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_MISR" description="TAMP non-secure masked interrupt status register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1MF" description="TAMP1 non-secure interrupt masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2MF" description="TAMP2 non-secure interrupt masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3MF" description="TAMP3 non-secure interrupt masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4MF" description="TAMP4 non-secure interrupt masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5MF" description="TAMP5 non-secure interrupt masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6MF" description="TAMP6 non-secure interrupt masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7MF" description="TAMP7 non-secure interrupt masked flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1MF" description="Internal tamper 1 non-secure interrupt masked flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2MF" description="Internal tamper 2 non-secure interrupt masked flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3MF" description="Internal tamper 3 non-secure interrupt masked flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4MF" description="Internal tamper 4 non-secure interrupt masked flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5MF" description="Internal tamper 5 non-secure interrupt masked flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6MF" description="Internal tamper 6 non-secure interrupt masked flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7MF" description="Internal tamper 7 tamper non-secure interrupt masked flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8MF" description="Internal tamper 8 non-secure interrupt masked flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9MF" description="internal tamper 9 non-secure interrupt masked flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11MF" description="internal tamper 11 non-secure interrupt masked flag" start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_SMISR" description="TAMP secure masked interrupt status register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1MF" description="TAMP1 secure interrupt masked flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TAMP2MF" description="TAMP2 secure interrupt masked flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="TAMP3MF" description="TAMP3 secure interrupt masked flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="TAMP4MF" description="TAMP4 secure interrupt masked flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TAMP5MF" description="TAMP5 secure interrupt masked flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="TAMP6MF" description="TAMP6 secure interrupt masked flag" start="5" size="1" access="ReadOnly" />
+      <BitField name="TAMP7MF" description="TAMP7 secure interrupt masked flag" start="6" size="1" access="ReadOnly" />
+      <BitField name="ITAMP1MF" description="Internal tamper 1 secure interrupt masked flag" start="16" size="1" access="ReadOnly" />
+      <BitField name="ITAMP2MF" description="Internal tamper 2 secure interrupt masked flag" start="17" size="1" access="ReadOnly" />
+      <BitField name="ITAMP3MF" description="Internal tamper 3 secure interrupt masked flag" start="18" size="1" access="ReadOnly" />
+      <BitField name="ITAMP4MF" description="Internal tamper 4 secure interrupt masked flag" start="19" size="1" access="ReadOnly" />
+      <BitField name="ITAMP5MF" description="Internal tamper 5 secure interrupt masked flag" start="20" size="1" access="ReadOnly" />
+      <BitField name="ITAMP6MF" description="Internal tamper 6 secure interrupt masked flag" start="21" size="1" access="ReadOnly" />
+      <BitField name="ITAMP7MF" description="Internal tamper 7 secure interrupt masked flag" start="22" size="1" access="ReadOnly" />
+      <BitField name="ITAMP8MF" description="Internal tamper 8 secure interrupt masked flag" start="23" size="1" access="ReadOnly" />
+      <BitField name="ITAMP9MF" description="internal tamper 9 secure interrupt masked flag" start="24" size="1" access="ReadOnly" />
+      <BitField name="ITAMP11MF" description="internal tamper 11 secure interrupt masked flag" start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_SCR" description="TAMP status clear register" start="+0x3C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTAMP1F" description="Clear TAMP1 detection flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTAMP2F" description="Clear TAMP2 detection flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CTAMP3F" description="Clear TAMP3 detection flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="CTAMP4F" description="Clear TAMP4 detection flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTAMP5F" description="Clear TAMP5 detection flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="CTAMP6F" description="Clear TAMP6 detection flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="CTAMP7F" description="Clear TAMP7 detection flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="CITAMP1F" description="Clear ITAMP1 detection flag" start="16" size="1" access="WriteOnly" />
+      <BitField name="CITAMP2F" description="Clear ITAMP2 detection flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="CITAMP3F" description="Clear ITAMP3 detection flag" start="18" size="1" access="WriteOnly" />
+      <BitField name="CITAMP4F" description="Clear ITAMP4 detection flag" start="19" size="1" access="WriteOnly" />
+      <BitField name="CITAMP5F" description="Clear ITAMP5 detection flag" start="20" size="1" access="WriteOnly" />
+      <BitField name="CITAMP6F" description="Clear ITAMP6 detection flag" start="21" size="1" access="WriteOnly" />
+      <BitField name="CITAMP7F" description="Clear ITAMP7 detection flag" start="22" size="1" access="WriteOnly" />
+      <BitField name="CITAMP8F" description="Clear ITAMP8 detection flag" start="23" size="1" access="WriteOnly" />
+      <BitField name="CITAMP9F" description="Clear ITAMP9 detection flag" start="24" size="1" access="WriteOnly" />
+      <BitField name="CITAMP11F" description="Clear ITAMP11 detection flag" start="26" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="TAMP_COUNT1R" description="TAMP monotonic counter 1 register" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COUNT" description="This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="TAMP_OR" description="TAMP option register" start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VCOREMEN" description="Vless thansub&gt;COREless than/sub&gt; monitoring" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;COREless than/sub&gt; monitoring disable" start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;COREless than/sub&gt; monitoring enable" start="0x1" />
+      </BitField>
+      <BitField name="BSEN" description="Boundary scan enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Boundary scan is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Boundary scan is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_RPCFGR" description="TAMP resources protection configuration register" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPCFG0" description="Configurable resource 0 protection" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Resource 0 is not included in the device secrets protected by TAMP peripheral" start="0x0" />
+        <Enum name="B_0x1" description="Resource 0 is included in the device secrets protected by TAMP peripheral" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TAMP_BKP0R" description="TAMP backup 0 register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP1R" description="TAMP backup 1 register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP2R" description="TAMP backup 2 register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP3R" description="TAMP backup 3 register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP4R" description="TAMP backup 4 register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP5R" description="TAMP backup 5 register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP6R" description="TAMP backup 6 register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP7R" description="TAMP backup 7 register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP8R" description="TAMP backup 8 register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP9R" description="TAMP backup 9 register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP10R" description="TAMP backup 10 register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP11R" description="TAMP backup 11 register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP12R" description="TAMP backup 12 register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP13R" description="TAMP backup 13 register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP14R" description="TAMP backup 14 register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP15R" description="TAMP backup 15 register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP16R" description="TAMP backup 16 register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP17R" description="TAMP backup 17 register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP18R" description="TAMP backup 18 register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP19R" description="TAMP backup 19 register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP20R" description="TAMP backup 20 register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP21R" description="TAMP backup 21 register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP22R" description="TAMP backup 22 register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP23R" description="TAMP backup 23 register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP24R" description="TAMP backup 24 register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP25R" description="TAMP backup 25 register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP26R" description="TAMP backup 26 register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP27R" description="TAMP backup 27 register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP28R" description="TAMP backup 28 register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP29R" description="TAMP backup 29 register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP30R" description="TAMP backup 30 register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TAMP_BKP31R" description="TAMP backup 31 register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers." start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM1" description="Advanced-control timers" start="0x42000000">
+    <Register name="TIM1_CR1" description="TIM1 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CR2" description="TIM1 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only" start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi" start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[2:0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 (after a dead-time) when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 (after a dead-time) when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write" />
+      <BitField name="OIS2N" description="Output idle state 2 (tim_oc2n output)" start="11" size="1" access="Read/Write" />
+      <BitField name="OIS3" description="Output idle state 3 (tim_oc3n output)" start="12" size="1" access="Read/Write" />
+      <BitField name="OIS3N" description="Output idle state 3 (tim_oc3n output)" start="13" size="1" access="Read/Write" />
+      <BitField name="OIS4" description="Output idle state 4 (tim_oc4 output)" start="14" size="1" access="Read/Write" />
+      <BitField name="OIS4N" description="Output idle state 4 (tim_oc4n output)" start="15" size="1" access="Read/Write" />
+      <BitField name="OIS5" description="Output idle state 5 (tim_oc5 output)" start="16" size="1" access="Read/Write" />
+      <BitField name="OIS6" description="Output idle state 6 (tim_oc6 output)" start="18" size="1" access="Read/Write" />
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on tim_trgo2 is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - the update event is selected as trigger output (tim_trgo2). For instance, a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo2)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo2)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo2)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo2)" start="0x7" />
+        <Enum name="B_0x8" description="Compare - tim_oc5refc signal is used as trigger output (tim_trgo2)" start="0x8" />
+        <Enum name="B_0x9" description="Compare - tim_oc6refc signal is used as trigger output (tim_trgo2)" start="0x9" />
+        <Enum name="B_0xA" description="Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2" start="0xA" />
+        <Enum name="B_0xB" description="Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2" start="0xB" />
+        <Enum name="B_0xC" description="Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xC" />
+        <Enum name="B_0xD" description="Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xD" />
+        <Enum name="B_0xE" description="Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xE" />
+        <Enum name="B_0xF" description="Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xF" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 46.3.32 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_SMCR" description="TIM1 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[2:0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[2:0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External Trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etr_in frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etr_in frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge." start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DIER" description="TIM1 DMA/interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction Change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_SR" description="TIM1 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred." start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="SBIF" description="System break interrupt flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" access="Read/Write" />
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_EGR" description="TIM1 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits update (providing CCPC bit is set)" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CCMR1_Input" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 Selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR1_Output" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0') as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int signal" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input)" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR2_Input" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR2_Output" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc3ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc3ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=0') as long as TIMx_CNT&gt;TIMx_CCR3 else active (tim_oc3ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNT&gt;TIMx_CCR3 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCER" description="TIM1 capture/compare enable register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low." start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NE" description="Capture/compare 2 complementary output enable" start="6" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/compare 3 output enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/compare 3 output polarity" start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NE" description="Capture/compare 3 complementary output enable" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/compare 3 complementary output polarity" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/compare 4 output enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/compare 4 output polarity" start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NE" description="Capture/compare 4 complementary output enable" start="14" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/compare 4 complementary output polarity" start="15" size="1" access="Read/Write" />
+      <BitField name="CC5E" description="Capture/compare 5 output enable" start="16" size="1" access="Read/Write" />
+      <BitField name="CC5P" description="Capture/compare 5 output polarity" start="17" size="1" access="Read/Write" />
+      <BitField name="CC6E" description="Capture/compare 6 output enable" start="20" size="1" access="Read/Write" />
+      <BitField name="CC6P" description="Capture/compare 6 output polarity" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CNT" description="TIM1 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM1_PSC" description="TIM1 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_ARR" description="TIM1 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_RCR" description="TIM1 repetition counter register" start="+0x030" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR1" description="TIM1 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR2" description="TIM1 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR3" description="TIM1 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR4" description="TIM1 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_BDTR" description="TIM1 break and dead-time register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected." start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output." start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In response to a break 2 event. OC and OCN outputs are disabled" start="0x0" />
+        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)." start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk2 acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break2 function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break2 function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk2 is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk2 is active high" start="0x1" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BK2DSRM" description="Break2 disarm" start="27" size="1" access="Read/Write" />
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+      <BitField name="BK2BID" description="Break2 bidirectional" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR5" description="TIM1 capture/compare register 5" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/compare 5 value" start="0" size="20" access="Read/Write" />
+      <BitField name="GC5C1" description="Group channel 5 and channel 1" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of oc5ref on oc1refc" start="0x0" />
+        <Enum name="B_0x1" description="oc1refc is the logical AND of oc1ref and oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C2" description="Group channel 5 and channel 2" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc2refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C3" description="Group channel 5 and channel 3" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc3refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CCR6" description="TIM1 capture/compare register 6" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/compare 6 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR3" description="TIM1 capture/compare mode register 3" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC5M" description="OC5M[2:0]: Output compare 5 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC6M" description="OC6M[2:0]: Output compare 6 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC5M_1" description="OC5M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC6M_1" description="OC6M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_DTR2" description="TIM1 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_ECR" description="TIM1 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled when tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_TISEL" description="TIM1 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_AF1" description="TIM1 alternate function option register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_AF2" description="TIM1 alternate function register 2" start="+0x064" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="TIMx_BKIN2 input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1E" description="tim_brk2_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2E" description="tim_brk2_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3E" description="tim_brk2_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4E" description="tim_brk2_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP5E" description="tim_brk2_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP6E" description="tim_brk2_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP7E" description="tim_brk2_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP8E" description="tim_brk2_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2INP" description="TIMx_BKIN2 input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1P" description="tim_brk2_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2P" description="tim_brk2_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3P" description="tim_brk2_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4P" description="tim_brk2_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DCR" description="TIM1 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2" start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR" start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DMAR" description="TIM1 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM1_S" description="Advanced-control timers" start="0x52000000">
+    <Register name="TIM1_CR1" description="TIM1 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CR2" description="TIM1 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only" start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi" start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[2:0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 (after a dead-time) when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 (after a dead-time) when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write" />
+      <BitField name="OIS2N" description="Output idle state 2 (tim_oc2n output)" start="11" size="1" access="Read/Write" />
+      <BitField name="OIS3" description="Output idle state 3 (tim_oc3n output)" start="12" size="1" access="Read/Write" />
+      <BitField name="OIS3N" description="Output idle state 3 (tim_oc3n output)" start="13" size="1" access="Read/Write" />
+      <BitField name="OIS4" description="Output idle state 4 (tim_oc4 output)" start="14" size="1" access="Read/Write" />
+      <BitField name="OIS4N" description="Output idle state 4 (tim_oc4n output)" start="15" size="1" access="Read/Write" />
+      <BitField name="OIS5" description="Output idle state 5 (tim_oc5 output)" start="16" size="1" access="Read/Write" />
+      <BitField name="OIS6" description="Output idle state 6 (tim_oc6 output)" start="18" size="1" access="Read/Write" />
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on tim_trgo2 is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - the update event is selected as trigger output (tim_trgo2). For instance, a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo2)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo2)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo2)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo2)" start="0x7" />
+        <Enum name="B_0x8" description="Compare - tim_oc5refc signal is used as trigger output (tim_trgo2)" start="0x8" />
+        <Enum name="B_0x9" description="Compare - tim_oc6refc signal is used as trigger output (tim_trgo2)" start="0x9" />
+        <Enum name="B_0xA" description="Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2" start="0xA" />
+        <Enum name="B_0xB" description="Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2" start="0xB" />
+        <Enum name="B_0xC" description="Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xC" />
+        <Enum name="B_0xD" description="Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xD" />
+        <Enum name="B_0xE" description="Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xE" />
+        <Enum name="B_0xF" description="Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xF" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 46.3.32 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_SMCR" description="TIM1 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[2:0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[2:0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External Trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etr_in frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etr_in frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge." start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DIER" description="TIM1 DMA/interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction Change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_SR" description="TIM1 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred." start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="SBIF" description="System break interrupt flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" access="Read/Write" />
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_EGR" description="TIM1 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits update (providing CCPC bit is set)" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CCMR1_Input" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 Selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR1_Output" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0') as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int signal" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input)" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR2_Input" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR2_Output" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc3ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc3ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=0') as long as TIMx_CNT&gt;TIMx_CCR3 else active (tim_oc3ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNT&gt;TIMx_CCR3 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCER" description="TIM1 capture/compare enable register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low." start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NE" description="Capture/compare 2 complementary output enable" start="6" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/compare 3 output enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/compare 3 output polarity" start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NE" description="Capture/compare 3 complementary output enable" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/compare 3 complementary output polarity" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/compare 4 output enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/compare 4 output polarity" start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NE" description="Capture/compare 4 complementary output enable" start="14" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/compare 4 complementary output polarity" start="15" size="1" access="Read/Write" />
+      <BitField name="CC5E" description="Capture/compare 5 output enable" start="16" size="1" access="Read/Write" />
+      <BitField name="CC5P" description="Capture/compare 5 output polarity" start="17" size="1" access="Read/Write" />
+      <BitField name="CC6E" description="Capture/compare 6 output enable" start="20" size="1" access="Read/Write" />
+      <BitField name="CC6P" description="Capture/compare 6 output polarity" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CNT" description="TIM1 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM1_PSC" description="TIM1 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_ARR" description="TIM1 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_RCR" description="TIM1 repetition counter register" start="+0x030" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR1" description="TIM1 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR2" description="TIM1 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR3" description="TIM1 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR4" description="TIM1 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_BDTR" description="TIM1 break and dead-time register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected." start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output." start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In response to a break 2 event. OC and OCN outputs are disabled" start="0x0" />
+        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)." start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk2 acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break2 function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break2 function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk2 is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk2 is active high" start="0x1" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BK2DSRM" description="Break2 disarm" start="27" size="1" access="Read/Write" />
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+      <BitField name="BK2BID" description="Break2 bidirectional" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCR5" description="TIM1 capture/compare register 5" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/compare 5 value" start="0" size="20" access="Read/Write" />
+      <BitField name="GC5C1" description="Group channel 5 and channel 1" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of oc5ref on oc1refc" start="0x0" />
+        <Enum name="B_0x1" description="oc1refc is the logical AND of oc1ref and oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C2" description="Group channel 5 and channel 2" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc2refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C3" description="Group channel 5 and channel 3" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc3refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_CCR6" description="TIM1 capture/compare register 6" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/compare 6 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_CCMR3" description="TIM1 capture/compare mode register 3" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC5M" description="OC5M[2:0]: Output compare 5 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC6M" description="OC6M[2:0]: Output compare 6 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC5M_1" description="OC5M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC6M_1" description="OC6M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_DTR2" description="TIM1 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_ECR" description="TIM1 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled when tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM1_TISEL" description="TIM1 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_AF1" description="TIM1 alternate function option register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_AF2" description="TIM1 alternate function register 2" start="+0x064" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="TIMx_BKIN2 input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1E" description="tim_brk2_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2E" description="tim_brk2_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3E" description="tim_brk2_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4E" description="tim_brk2_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP5E" description="tim_brk2_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP6E" description="tim_brk2_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP7E" description="tim_brk2_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP8E" description="tim_brk2_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2INP" description="TIMx_BKIN2 input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1P" description="tim_brk2_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2P" description="tim_brk2_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3P" description="tim_brk2_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4P" description="tim_brk2_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DCR" description="TIM1 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2" start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR" start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM1_DMAR" description="TIM1 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM2" description="General-purpose timers" start="0x40000000">
+    <Register name="TIM2_CR1" description="TIM2 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_CR2" description="TIM2 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_SMCR" description="TIM2 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DIER" description="TIM2 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_SR" description="TIM2 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_EGR" description="TIM2 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_CCMR1_INPUT" description="TIM2 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR1_OUTPUT" description="TIM2 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR2_INPUT" description="TIM2 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR2_OUTPUT" description="TIM2 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCER" description="TIM2 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CNT" description="TIM2 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_PSC" description="TIM2 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_ARR" description="TIM2 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR1" description="TIM2 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR2" description="TIM2 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR3" description="TIM2 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR4" description="TIM2 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_ECR" description="TIM2 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_TISEL" description="TIM2 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_AF1" description="TIM2 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_AF2" description="TIM2 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DCR" description="TIM2 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DMAR" description="TIM2 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM2_S" description="General-purpose timers" start="0x50000000">
+    <Register name="TIM2_CR1" description="TIM2 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_CR2" description="TIM2 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_SMCR" description="TIM2 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DIER" description="TIM2 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_SR" description="TIM2 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_EGR" description="TIM2 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_CCMR1_INPUT" description="TIM2 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR1_OUTPUT" description="TIM2 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR2_INPUT" description="TIM2 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCMR2_OUTPUT" description="TIM2 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCER" description="TIM2 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CNT" description="TIM2 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_PSC" description="TIM2 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_ARR" description="TIM2 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR1" description="TIM2 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR2" description="TIM2 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR3" description="TIM2 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_CCR4" description="TIM2 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_ECR" description="TIM2 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM2_TISEL" description="TIM2 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_AF1" description="TIM2 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_AF2" description="TIM2 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DCR" description="TIM2 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM2_DMAR" description="TIM2 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM3" description="General purpose timers" start="0x40000400">
+    <Register name="TIM3_CR1" description="TIM3 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_CR2" description="TIM3 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_SMCR" description="TIM3 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DIER" description="TIM3 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_SR" description="TIM3 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_EGR" description="TIM3 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_CCMR1_INPUT" description="TIM3 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR1_OUTPUT" description="TIM3 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR2_INPUT" description="TIM3 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR2_OUTPUT" description="TIM3 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCER" description="TIM3 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CNT" description="TIM3 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_PSC" description="TIM3 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_ARR" description="TIM3 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR1" description="TIM3 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR2" description="TIM3 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR3" description="TIM3 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR4" description="TIM3 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_ECR" description="TIM3 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_TISEL" description="TIM3 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_AF1" description="TIM3 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_AF2" description="TIM3 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DCR" description="TIM3 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DMAR" description="TIM3 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM3_S" description="General purpose timers" start="0x50000400">
+    <Register name="TIM3_CR1" description="TIM3 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_CR2" description="TIM3 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_SMCR" description="TIM3 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DIER" description="TIM3 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_SR" description="TIM3 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_EGR" description="TIM3 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_CCMR1_INPUT" description="TIM3 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR1_OUTPUT" description="TIM3 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR2_INPUT" description="TIM3 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCMR2_OUTPUT" description="TIM3 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCER" description="TIM3 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CNT" description="TIM3 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_PSC" description="TIM3 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_ARR" description="TIM3 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR1" description="TIM3 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR2" description="TIM3 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR3" description="TIM3 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_CCR4" description="TIM3 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_ECR" description="TIM3 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM3_TISEL" description="TIM3 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_AF1" description="TIM3 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_AF2" description="TIM3 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DCR" description="TIM3 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM3_DMAR" description="TIM3 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM4" description="General purpose timers" start="0x40000800">
+    <Register name="TIM4_CR1" description="TIM4 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_CR2" description="TIM4 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_SMCR" description="TIM4 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DIER" description="TIM4 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_SR" description="TIM4 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_EGR" description="TIM4 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_CCMR1_INPUT" description="TIM4 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR1_OUTPUT" description="TIM4 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR2_INPUT" description="TIM4 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR2_OUTPUT" description="TIM4 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCER" description="TIM4 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CNT" description="TIM4 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_PSC" description="TIM4 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_ARR" description="TIM4 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR1" description="TIM4 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR2" description="TIM4 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR3" description="TIM4 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR4" description="TIM4 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_ECR" description="TIM4 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_TISEL" description="TIM4 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_AF1" description="TIM4 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_AF2" description="TIM4 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DCR" description="TIM4 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DMAR" description="TIM4 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM4_S" description="General purpose timers" start="0x50000800">
+    <Register name="TIM4_CR1" description="TIM4 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_CR2" description="TIM4 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_SMCR" description="TIM4 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DIER" description="TIM4 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_SR" description="TIM4 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_EGR" description="TIM4 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_CCMR1_INPUT" description="TIM4 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR1_OUTPUT" description="TIM4 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR2_INPUT" description="TIM4 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCMR2_OUTPUT" description="TIM4 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCER" description="TIM4 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CNT" description="TIM4 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_PSC" description="TIM4 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_ARR" description="TIM4 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR1" description="TIM4 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR2" description="TIM4 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR3" description="TIM4 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_CCR4" description="TIM4 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_ECR" description="TIM4 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM4_TISEL" description="TIM4 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_AF1" description="TIM4 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_AF2" description="TIM4 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DCR" description="TIM4 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM4_DMAR" description="TIM4 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM5" description="General purpose timers" start="0x40000C00">
+    <Register name="TIM5_CR1" description="TIM5 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_CR2" description="TIM5 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_SMCR" description="TIM5 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DIER" description="TIM5 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_SR" description="TIM5 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_EGR" description="TIM5 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_CCMR1_INPUT" description="TIM5 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR1_OUTPUT" description="TIM5 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR2_INPUT" description="TIM5 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR2_OUTPUT" description="TIM5 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCER" description="TIM5 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CNT" description="TIM5 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_PSC" description="TIM5 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_ARR" description="TIM5 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR1" description="TIM5 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR2" description="TIM5 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR3" description="TIM5 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR4" description="TIM5 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_ECR" description="TIM5 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_TISEL" description="TIM5 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_AF1" description="TIM5 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_AF2" description="TIM5 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DCR" description="TIM5 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DMAR" description="TIM5 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM5_S" description="General purpose timers" start="0x50000C00">
+    <Register name="TIM5_CR1" description="TIM5 control register 1" start="+0x000" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering Enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_CR2" description="TIM5 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also Section 53.3.29: Interfacing with Hall sensors on page 2562." start="0x1" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 54.4.25 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_SMCR" description="TIM5 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="OCCS" description="OCREF clear selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr_int is connected to the tim_ocref_clr input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr_int is connected to tim_etrf" start="0x1" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 edge detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered timer input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered timer input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etrp frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etrp frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etrp frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge" start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DIER" description="TIM5 DMA/Interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_SR" description="TIM5 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_EGR" description="TIM5 event generation register" start="+0x014" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_CCMR1_INPUT" description="TIM5 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR1_OUTPUT" description="TIM5 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref=1)." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR2_INPUT" description="TIM5 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCMR2_OUTPUT" description="TIM5 capture/compare mode register 2" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCER" description="TIM5 capture/compare enable register" start="+0x020" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity." start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable." start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity." start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity." start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable." start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity." start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity." start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable." start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/Compare 4 output Polarity." start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity." start="15" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CNT" description="TIM5 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Least significant part of counter value" start="0" size="31" access="Read/Write" />
+      <BitField name="UIFCPY_CNT" description="Value depends on IUFREMAP in TIMx_CR1." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_PSC" description="TIM5 prescaler" start="+0x028" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_ARR" description="TIM5 auto-reload register" start="+0x02C" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR1" description="TIM5 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR2" description="TIM5 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR3" description="TIM5 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare 3 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_CCR4" description="TIM5 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare 4 value" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_ECR" description="TIM5 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled hen tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM5_TISEL" description="TIM5 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH3" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_AF1" description="TIM5 alternate function register 1" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_AF2" description="TIM5 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DCR" description="TIM5 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM5_DMAR" description="TIM5 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM6" description="Basic timers" start="0x40001000">
+    <Register name="TIM6_CR1" description="TIM6 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CR2" description="TIM6 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_DIER" description="TIM6 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_SR" description="TIM6 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_EGR" description="TIM6 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CNT" description="TIM6 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM6_PSC" description="TIM6 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM6_ARR" description="TIM6 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM6_S" description="Basic timers" start="0x50001000">
+    <Register name="TIM6_CR1" description="TIM6 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CR2" description="TIM6 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_DIER" description="TIM6 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_SR" description="TIM6 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_EGR" description="TIM6 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CNT" description="TIM6 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM6_PSC" description="TIM6 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM6_ARR" description="TIM6 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM7" description="Basic timers" start="0x40001400">
+    <Register name="TIM7_CR1" description="TIM7 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM7_CR2" description="TIM7 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM7_DIER" description="TIM7 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM7_SR" description="TIM7 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM7_EGR" description="TIM7 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM7_CNT" description="TIM7 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM7_PSC" description="TIM7 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM7_ARR" description="TIM7 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM7_S" description="Basic timers" start="0x50001400">
+    <Register name="TIM6_CR1" description="TIM6 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CR2" description="TIM6 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_DIER" description="TIM6 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_SR" description="TIM6 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_EGR" description="TIM6 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM6_CNT" description="TIM6 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM6_PSC" description="TIM6 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM6_ARR" description="TIM6 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM8" description="Advanced-control timers" start="0x42000400">
+    <Register name="TIM8_CR1" description="TIM8 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CR2" description="TIM8 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only" start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi" start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[2:0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 (after a dead-time) when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 (after a dead-time) when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write" />
+      <BitField name="OIS2N" description="Output idle state 2 (tim_oc2n output)" start="11" size="1" access="Read/Write" />
+      <BitField name="OIS3" description="Output idle state 3 (tim_oc3n output)" start="12" size="1" access="Read/Write" />
+      <BitField name="OIS3N" description="Output idle state 3 (tim_oc3n output)" start="13" size="1" access="Read/Write" />
+      <BitField name="OIS4" description="Output idle state 4 (tim_oc4 output)" start="14" size="1" access="Read/Write" />
+      <BitField name="OIS4N" description="Output idle state 4 (tim_oc4n output)" start="15" size="1" access="Read/Write" />
+      <BitField name="OIS5" description="Output idle state 5 (tim_oc5 output)" start="16" size="1" access="Read/Write" />
+      <BitField name="OIS6" description="Output idle state 6 (tim_oc6 output)" start="18" size="1" access="Read/Write" />
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on tim_trgo2 is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - the update event is selected as trigger output (tim_trgo2). For instance, a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo2)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo2)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo2)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo2)" start="0x7" />
+        <Enum name="B_0x8" description="Compare - tim_oc5refc signal is used as trigger output (tim_trgo2)" start="0x8" />
+        <Enum name="B_0x9" description="Compare - tim_oc6refc signal is used as trigger output (tim_trgo2)" start="0x9" />
+        <Enum name="B_0xA" description="Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2" start="0xA" />
+        <Enum name="B_0xB" description="Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2" start="0xB" />
+        <Enum name="B_0xC" description="Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xC" />
+        <Enum name="B_0xD" description="Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xD" />
+        <Enum name="B_0xE" description="Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xE" />
+        <Enum name="B_0xF" description="Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xF" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 46.3.32 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_SMCR" description="TIM8 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[2:0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[2:0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External Trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etr_in frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etr_in frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge." start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DIER" description="TIM8 DMA/interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction Change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_SR" description="TIM8 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred." start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="SBIF" description="System break interrupt flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" access="Read/Write" />
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_EGR" description="TIM8 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits update (providing CCPC bit is set)" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CCMR1_Input" description="TIM8 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 Selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR1_Output" description="TIM8 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0') as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int signal" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input)" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR2_Input" description="TIM8 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR2_Output" description="TIM8 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc3ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc3ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=0') as long as TIMx_CNT&gt;TIMx_CCR3 else active (tim_oc3ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNT&gt;TIMx_CCR3 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCER" description="TIM8 capture/compare enable register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low." start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NE" description="Capture/compare 2 complementary output enable" start="6" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/compare 3 output enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/compare 3 output polarity" start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NE" description="Capture/compare 3 complementary output enable" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/compare 3 complementary output polarity" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/compare 4 output enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/compare 4 output polarity" start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NE" description="Capture/compare 4 complementary output enable" start="14" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/compare 4 complementary output polarity" start="15" size="1" access="Read/Write" />
+      <BitField name="CC5E" description="Capture/compare 5 output enable" start="16" size="1" access="Read/Write" />
+      <BitField name="CC5P" description="Capture/compare 5 output polarity" start="17" size="1" access="Read/Write" />
+      <BitField name="CC6E" description="Capture/compare 6 output enable" start="20" size="1" access="Read/Write" />
+      <BitField name="CC6P" description="Capture/compare 6 output polarity" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CNT" description="TIM8 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM8_PSC" description="TIM8 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_ARR" description="TIM8 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_RCR" description="TIM8 repetition counter register" start="+0x030" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR1" description="TIM8 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR2" description="TIM8 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR3" description="TIM8 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR4" description="TIM8 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_BDTR" description="TIM8 break and dead-time register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected." start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output." start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In response to a break 2 event. OC and OCN outputs are disabled" start="0x0" />
+        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)." start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk2 acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break2 function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break2 function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk2 is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk2 is active high" start="0x1" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BK2DSRM" description="Break2 disarm" start="27" size="1" access="Read/Write" />
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+      <BitField name="BK2BID" description="Break2 bidirectional" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR5" description="TIM8 capture/compare register 5" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/compare 5 value" start="0" size="20" access="Read/Write" />
+      <BitField name="GC5C1" description="Group channel 5 and channel 1" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of oc5ref on oc1refc" start="0x0" />
+        <Enum name="B_0x1" description="oc1refc is the logical AND of oc1ref and oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C2" description="Group channel 5 and channel 2" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc2refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C3" description="Group channel 5 and channel 3" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc3refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CCR6" description="TIM8 capture/compare register 6" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/compare 6 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR3" description="TIM8 capture/compare mode register 3" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC5M" description="OC5M[2:0]: Output compare 5 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC6M" description="OC6M[2:0]: Output compare 6 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC5M_1" description="OC5M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC6M_1" description="OC6M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_DTR2" description="TIM8 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_ECR" description="TIM8 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled when tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_TISEL" description="TIM8 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_AF1" description="TIM8 alternate function option register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_AF2" description="TIM8 alternate function register 2" start="+0x064" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="TIMx_BKIN2 input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1E" description="tim_brk2_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2E" description="tim_brk2_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3E" description="tim_brk2_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4E" description="tim_brk2_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP5E" description="tim_brk2_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP6E" description="tim_brk2_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP7E" description="tim_brk2_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP8E" description="tim_brk2_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2INP" description="TIMx_BKIN2 input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1P" description="tim_brk2_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2P" description="tim_brk2_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3P" description="tim_brk2_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4P" description="tim_brk2_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DCR" description="TIM8 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2" start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR" start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DMAR" description="TIM8 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM8_S" description="Advanced-control timers" start="0x52000400">
+    <Register name="TIM8_CR1" description="TIM8 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="DIR" description="Direction" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
+        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
+      </BitField>
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
+        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
+        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
+        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CR2" description="TIM8 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only" start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi" start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="MMS[2:0]: Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo)" start="0x7" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 (after a dead-time) when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 (after a dead-time) when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write" />
+      <BitField name="OIS2N" description="Output idle state 2 (tim_oc2n output)" start="11" size="1" access="Read/Write" />
+      <BitField name="OIS3" description="Output idle state 3 (tim_oc3n output)" start="12" size="1" access="Read/Write" />
+      <BitField name="OIS3N" description="Output idle state 3 (tim_oc3n output)" start="13" size="1" access="Read/Write" />
+      <BitField name="OIS4" description="Output idle state 4 (tim_oc4 output)" start="14" size="1" access="Read/Write" />
+      <BitField name="OIS4N" description="Output idle state 4 (tim_oc4n output)" start="15" size="1" access="Read/Write" />
+      <BitField name="OIS5" description="Output idle state 5 (tim_oc5 output)" start="16" size="1" access="Read/Write" />
+      <BitField name="OIS6" description="Output idle state 6 (tim_oc6 output)" start="18" size="1" access="Read/Write" />
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on tim_trgo2 is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - the update event is selected as trigger output (tim_trgo2). For instance, a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo2)" start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo2)" start="0x5" />
+        <Enum name="B_0x6" description="Compare - tim_oc3refc signal is used as trigger output (tim_trgo2)" start="0x6" />
+        <Enum name="B_0x7" description="Compare - tim_oc4refc signal is used as trigger output (tim_trgo2)" start="0x7" />
+        <Enum name="B_0x8" description="Compare - tim_oc5refc signal is used as trigger output (tim_trgo2)" start="0x8" />
+        <Enum name="B_0x9" description="Compare - tim_oc6refc signal is used as trigger output (tim_trgo2)" start="0x9" />
+        <Enum name="B_0xA" description="Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2" start="0xA" />
+        <Enum name="B_0xB" description="Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2" start="0xB" />
+        <Enum name="B_0xC" description="Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xC" />
+        <Enum name="B_0xD" description="Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xD" />
+        <Enum name="B_0xE" description="Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2" start="0xE" />
+        <Enum name="B_0xF" description="Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2" start="0xF" />
+      </BitField>
+      <BitField name="MMS_1" description="MMS[3]" start="25" size="1" access="Read/Write" />
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 46.3.32 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_SMCR" description="TIM8 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[2:0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x1" description="Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level." start="0x1" />
+        <Enum name="B_0x2" description="Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level." start="0x2" />
+        <Enum name="B_0x3" description="Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input." start="0x3" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[2:0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+        <Enum name="B_0x7" description="External Trigger input (tim_etrf)" start="0x7" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in frequency divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="tim_etr_in frequency divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="tim_etr_in frequency divided by 8" start="0x3" />
+      </BitField>
+      <BitField name="ECE" description="External clock enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
+        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal." start="0x1" />
+      </BitField>
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr_in is non-inverted, active at high level or rising edge." start="0x0" />
+        <Enum name="B_0x1" description="tim_etr_in is inverted, active at low level or falling edge." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMSPS" description="SMS preload source" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The transfer is triggered by the Timer's Update event" start="0x0" />
+        <Enum name="B_0x1" description="The transfer is triggered by the Index event" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DIER" description="TIM8 DMA/interrupt enable register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3IE" description="Capture/compare 3 interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4IE" description="Capture/compare 4 interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC3DE" description="Capture/compare 3 DMA request enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC3 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC4DE" description="Capture/compare 4 DMA request enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC4 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDXIE" description="Index interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="DIRIE" description="Direction change interrupt enable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Direction Change interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Direction Change interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="IERRIE" description="Index error interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index error interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TERRIE" description="Transition error interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transition error interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transition error interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_SR" description="TIM8 status register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="CC3IF" description="Capture/compare 3 interrupt flag" start="3" size="1" access="Read/Write" />
+      <BitField name="CC4IF" description="Capture/compare 4 interrupt flag" start="4" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred." start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3OF" description="Capture/compare 3 overcapture flag" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4OF" description="Capture/compare 4 overcapture flag" start="12" size="1" access="Read/Write" />
+      <BitField name="SBIF" description="System break interrupt flag" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
+      </BitField>
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" access="Read/Write" />
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" access="Read/Write" />
+      <BitField name="IDXF" description="Index interrupt flag" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index event occurred." start="0x0" />
+        <Enum name="B_0x1" description="An index event has occurred" start="0x1" />
+      </BitField>
+      <BitField name="DIRF" description="Direction change interrupt flag" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No direction change" start="0x0" />
+        <Enum name="B_0x1" description="Direction change" start="0x1" />
+      </BitField>
+      <BitField name="IERRF" description="Index error interrupt flag" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No index error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An index error has been detected" start="0x1" />
+      </BitField>
+      <BitField name="TERRF" description="Transition error interrupt flag" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No encoder transition error has been detected." start="0x0" />
+        <Enum name="B_0x1" description="An encoder transition error has been detected" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_EGR" description="TIM8 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" access="WriteOnly" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits update (providing CCPC bit is set)" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CCMR1_Input" description="TIM8 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 Selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR1_Output" description="TIM8 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0') as long as TIMx_CNT&gt;TIMx_CCR1 else active (tim_oc1ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int signal" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input)" start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR2_Input" description="TIM8 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR2_Output" description="TIM8 capture/compare mode register 2 [alternate]" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3" start="0x1" />
+        <Enum name="B_0x2" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4" start="0x2" />
+        <Enum name="B_0x3" description="CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC3M" description="OC3M[2:0]: Output compare 3 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc3ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc3ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=0') as long as TIMx_CNT&gt;TIMx_CCR3 else active (tim_oc3ref='1')." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNT&gt;TIMx_CCR3 else inactive." start="0x7" />
+      </BitField>
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="CC4S" description="Capture/compare 4 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4" start="0x1" />
+        <Enum name="B_0x2" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3" start="0x2" />
+        <Enum name="B_0x3" description="CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC4M" description="OC4M[2:0]: Output compare 4 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC3M_1" description="OC3M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC4M_1" description="OC4M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCER" description="TIM8 capture/compare enable register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low." start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NE" description="Capture/compare 2 complementary output enable" start="6" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+      <BitField name="CC3E" description="Capture/compare 3 output enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CC3P" description="Capture/compare 3 output polarity" start="9" size="1" access="Read/Write" />
+      <BitField name="CC3NE" description="Capture/compare 3 complementary output enable" start="10" size="1" access="Read/Write" />
+      <BitField name="CC3NP" description="Capture/compare 3 complementary output polarity" start="11" size="1" access="Read/Write" />
+      <BitField name="CC4E" description="Capture/compare 4 output enable" start="12" size="1" access="Read/Write" />
+      <BitField name="CC4P" description="Capture/compare 4 output polarity" start="13" size="1" access="Read/Write" />
+      <BitField name="CC4NE" description="Capture/compare 4 complementary output enable" start="14" size="1" access="Read/Write" />
+      <BitField name="CC4NP" description="Capture/compare 4 complementary output polarity" start="15" size="1" access="Read/Write" />
+      <BitField name="CC5E" description="Capture/compare 5 output enable" start="16" size="1" access="Read/Write" />
+      <BitField name="CC5P" description="Capture/compare 5 output polarity" start="17" size="1" access="Read/Write" />
+      <BitField name="CC6E" description="Capture/compare 6 output enable" start="20" size="1" access="Read/Write" />
+      <BitField name="CC6P" description="Capture/compare 6 output polarity" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CNT" description="TIM8 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM8_PSC" description="TIM8 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_ARR" description="TIM8 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_RCR" description="TIM8 repetition counter register" start="+0x030" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR1" description="TIM8 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR2" description="TIM8 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR3" description="TIM8 capture/compare register 3" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR4" description="TIM8 capture/compare register 4" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/compare value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_BDTR" description="TIM8 break and dead-time register" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected." start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output." start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state)." start="0x0" />
+        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="In response to a break 2 event. OC and OCN outputs are disabled" start="0x0" />
+        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)." start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk2 acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break2 function disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break2 function enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk2 is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk2 is active high" start="0x1" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BK2DSRM" description="Break2 disarm" start="27" size="1" access="Read/Write" />
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+      <BitField name="BK2BID" description="Break2 bidirectional" start="29" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCR5" description="TIM8 capture/compare register 5" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/compare 5 value" start="0" size="20" access="Read/Write" />
+      <BitField name="GC5C1" description="Group channel 5 and channel 1" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of oc5ref on oc1refc" start="0x0" />
+        <Enum name="B_0x1" description="oc1refc is the logical AND of oc1ref and oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C2" description="Group channel 5 and channel 2" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc2refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref" start="0x1" />
+      </BitField>
+      <BitField name="GC5C3" description="Group channel 5 and channel 3" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect of tim_oc5ref on tim_oc3refc" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_CCR6" description="TIM8 capture/compare register 6" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/compare 6 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_CCMR3" description="TIM8 capture/compare mode register 3" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" access="Read/Write" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" access="Read/Write" />
+      <BitField name="OC5M" description="OC5M[2:0]: Output compare 5 mode" start="4" size="3" access="Read/Write" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC6M" description="OC6M[2:0]: Output compare 6 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC5M_1" description="OC5M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC6M_1" description="OC6M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_DTR2" description="TIM8 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_ECR" description="TIM8 timer encoder control register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IE" description="Index enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index disabled" start="0x0" />
+        <Enum name="B_0x1" description="Index enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDIR" description="Index direction" start="1" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter whatever the direction" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when up-counting only" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when down-counting only" start="0x2" />
+      </BitField>
+      <BitField name="IBLK" description="Index blanking" start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index always active" start="0x0" />
+        <Enum name="B_0x1" description="Index disabled when tim_ti3 input is active, as per CC3P bitfield" start="0x1" />
+        <Enum name="B_0x2" description="Index disabled when tim_ti4 input is active, as per CC4P bitfield" start="0x2" />
+      </BitField>
+      <BitField name="FIDX" description="First index " start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Index is always active" start="0x0" />
+        <Enum name="B_0x1" description="the first Index only resets the counter" start="0x1" />
+      </BitField>
+      <BitField name="IPOS" description="Index positioning" start="6" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Index resets the counter when AB = 00" start="0x0" />
+        <Enum name="B_0x1" description="Index resets the counter when AB = 01" start="0x1" />
+        <Enum name="B_0x2" description="Index resets the counter when AB = 10" start="0x2" />
+        <Enum name="B_0x3" description="Index resets the counter when AB = 11" start="0x3" />
+      </BitField>
+      <BitField name="PW" description="Pulse width" start="16" size="8" access="Read/Write" />
+      <BitField name="PWPRSC" description="Pulse width prescaler" start="24" size="3" access="Read/Write" />
+    </Register>
+    <Register name="TIM8_TISEL" description="TIM8 timer input selection register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="Selects tim_ti1[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti1_in0: TIMx_CH1" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="Selects tim_ti2[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti2_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI3SEL" description="Selects tim_ti3[15:0] input" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti3_in0: TIMx_CH2" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti3_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti3_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI4SEL" description="Selects tim_ti4[15:0] input" start="24" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ti4_in0: TIMx_CH4" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti4_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti4_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_AF1" description="TIM8 alternate function option register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1)" start="0x1" />
+      </BitField>
+      <BitField name="ETRSEL" description="etr_in source selection" start="14" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="tim_etr0: TIMx_ETR input" start="0x0" />
+        <Enum name="B_0x1" description="tim_etr1" start="0x1" />
+        <Enum name="B_0xF" description="tim_etr15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_AF2" description="TIM8 alternate function register 2" start="+0x064" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="TIMx_BKIN2 input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1E" description="tim_brk2_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2E" description="tim_brk2_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3E" description="tim_brk2_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4E" description="tim_brk2_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP5E" description="tim_brk2_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP6E" description="tim_brk2_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP7E" description="tim_brk2_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP8E" description="tim_brk2_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BK2INP" description="TIMx_BKIN2 input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP1P" description="tim_brk2_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP2P" description="tim_brk2_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP3P" description="tim_brk2_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="BK2CMP4P" description="tim_brk2_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)" start="0x1" />
+      </BitField>
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DCR" description="TIM8 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2" start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR" start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer" start="0x0" />
+        <Enum name="B_0x1" description="2 transfers" start="0x1" />
+        <Enum name="B_0x2" description="3 transfers" start="0x2" />
+        <Enum name="B_0x1A" description="26 transfers" start="0x1A" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x4" description="CC3" start="0x4" />
+        <Enum name="B_0x5" description="CC4" start="0x5" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM8_DMAR" description="TIM8 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM9" description="General-purpose timers" start="0x42004C00">
+    <Register name="TIM9_CR1" description="TIM9 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an update interrupt if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_CR2" description="TIM12 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 49.4.23 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_SMCR" description="TIM9 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful in order to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_DIER" description="TIM9 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_SR" description="TIM9 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_EGR" description="TIM9 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_CCMR1_Input" description="TIM9 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCMR1_Output" description="TIM9 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately" start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event" start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. The tim_oc1ref signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. The tim_oc1ref signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1" start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low" start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high" start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else it is inactive" start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else it is active" start="0x7" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCER" description="TIM9 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity" start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CNT" description="TIM9 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_PSC" description="TIM9 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_ARR" description="TIM9 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCR1" description="TIM9 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCR2" description="TIM9 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_TISEL" description="TIM9 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0x4" description="tim_ti2_in15" start="0x4" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM9_S" description="General-purpose timers" start="0x52004C00">
+    <Register name="TIM9_CR1" description="TIM9 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an update interrupt if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_CR2" description="TIM12 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 49.4.23 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_SMCR" description="TIM9 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful in order to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_DIER" description="TIM9 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_SR" description="TIM9 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_EGR" description="TIM9 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM9_CCMR1_Input" description="TIM9 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCMR1_Output" description="TIM9 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately" start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event" start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. The tim_oc1ref signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. The tim_oc1ref signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1" start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low" start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high" start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else it is inactive" start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else it is active" start="0x7" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCER" description="TIM9 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity" start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CNT" description="TIM9 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_PSC" description="TIM9 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_ARR" description="TIM9 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCR1" description="TIM9 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_CCR2" description="TIM9 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM9_TISEL" description="TIM9 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0x4" description="tim_ti2_in15" start="0x4" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM10" description="General-purpose timers" start="0x40003000">
+    <Register name="TIM10_CR1" description="TIM10 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_DIER" description="TIM10 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_SR" description="TIM10 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_EGR" description="TIM10 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_CCMR1_Input" description="TIM10 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_CCMR1_Output" description="TIM10 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CCER" description="TIM10 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CNT" description="TIM10 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_PSC" description="TIM10 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_ARR" description="TIM10 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CCR1" description="TIM10 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_TISEL" description="TIM10 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM10_S" description="General-purpose timers" start="0x50003000">
+    <Register name="TIM10_CR1" description="TIM10 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_DIER" description="TIM10 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_SR" description="TIM10 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_EGR" description="TIM10 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_CCMR1_Input" description="TIM10 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM10_CCMR1_Output" description="TIM10 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CCER" description="TIM10 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CNT" description="TIM10 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_PSC" description="TIM10 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_ARR" description="TIM10 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_CCR1" description="TIM10 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM10_TISEL" description="TIM10 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM11" description="General-purpose timers" start="0x40003400">
+    <Register name="TIM11_CR1" description="TIM11 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_DIER" description="TIM11 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_SR" description="TIM11 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_EGR" description="TIM11 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_CCMR1_Input" description="TIM11 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_CCMR1_Output" description="TIM11 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CCER" description="TIM11 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CNT" description="TIM11 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_PSC" description="TIM11 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_ARR" description="TIM11 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CCR1" description="TIM11 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_TISEL" description="TIM11 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM11_S" description="General-purpose timers" start="0x50003400">
+    <Register name="TIM11_CR1" description="TIM11 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_DIER" description="TIM11 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_SR" description="TIM11 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_EGR" description="TIM11 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_CCMR1_Input" description="TIM11 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM11_CCMR1_Output" description="TIM11 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CCER" description="TIM11 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CNT" description="TIM11 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_PSC" description="TIM11 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_ARR" description="TIM11 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_CCR1" description="TIM11 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM11_TISEL" description="TIM11 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM12" description="General-purpose timers" start="0x40001800">
+    <Register name="TIM12_CR1" description="TIM12 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an update interrupt if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_CR2" description="TIM12 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 49.4.23 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_SMCR" description="TIM12 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful in order to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_DIER" description="TIM12 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_SR" description="TIM12 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_EGR" description="TIM12 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_CCMR1_Input" description="TIM12 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCMR1_Output" description="TIM12 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately" start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event" start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. The tim_oc1ref signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. The tim_oc1ref signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1" start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low" start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high" start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else it is inactive" start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else it is active" start="0x7" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCER" description="TIM12 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity" start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CNT" description="TIM12 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_PSC" description="TIM12 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_ARR" description="TIM12 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCR1" description="TIM12 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCR2" description="TIM12 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_TISEL" description="TIM12 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0x4" description="tim_ti2_in15" start="0x4" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM12_S" description="General-purpose timers" start="0x50001800">
+    <Register name="TIM12_CR1" description="TIM12 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an update interrupt if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_CR2" description="TIM12 control register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 49.4.23 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_SMCR" description="TIM12 slave mode control register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful in order to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_DIER" description="TIM12 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_SR" description="TIM12 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_EGR" description="TIM12 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM12_CCMR1_Input" description="TIM12 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCMR1_Output" description="TIM12 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately" start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event" start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. The tim_oc1ref signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. The tim_oc1ref signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1" start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low" start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high" start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else it is inactive" start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else it is active" start="0x7" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCER" description="TIM12 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity" start="3" size="1" access="Read/Write" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CNT" description="TIM12 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_PSC" description="TIM12 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_ARR" description="TIM12 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCR1" description="TIM12 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_CCR2" description="TIM12 capture/compare register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM12_TISEL" description="TIM12 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0x4" description="tim_ti2_in15" start="0x4" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM13" description="General-purpose timers" start="0x40001C00">
+    <Register name="TIM13_CR1" description="TIM13 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_DIER" description="TIM13 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_SR" description="TIM13 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_EGR" description="TIM13 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_CCMR1_Input" description="TIM13 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_CCMR1_Output" description="TIM13 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CCER" description="TIM13 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CNT" description="TIM13 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_PSC" description="TIM13 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_ARR" description="TIM13 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CCR1" description="TIM13 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_TISEL" description="TIM13 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM13_S" description="General-purpose timers" start="0x50001C00">
+    <Register name="TIM13_CR1" description="TIM13 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_DIER" description="TIM13 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_SR" description="TIM13 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_EGR" description="TIM13 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_CCMR1_Input" description="TIM13 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM13_CCMR1_Output" description="TIM13 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CCER" description="TIM13 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CNT" description="TIM13 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_PSC" description="TIM13 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_ARR" description="TIM13 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_CCR1" description="TIM13 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM13_TISEL" description="TIM13 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM14" description="General-purpose timers" start="0x40002000">
+    <Register name="TIM14_CR1" description="TIM14 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_DIER" description="TIM14 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_SR" description="TIM14 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_EGR" description="TIM14 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_CCMR1_Input" description="TIM14 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_CCMR1_Output" description="TIM14 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CCER" description="TIM14 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CNT" description="TIM14 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_PSC" description="TIM14 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_ARR" description="TIM14 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CCR1" description="TIM14 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_TISEL" description="TIM14 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM14_S" description="General-purpose timers" start="0x50002000">
+    <Register name="TIM14_CR1" description="TIM14 control register 1" start="+0x000" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt; = tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4 tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_DIER" description="TIM14 Interrupt enable register" start="+0x00C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_SR" description="TIM14 status register" start="+0x010" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_EGR" description="TIM14 event generation register" start="+0x014" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_CCMR1_Input" description="TIM14 capture/compare mode register 1" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM14_CCMR1_Output" description="TIM14 capture/compare mode register 1 [alternate]" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active" start="0x7" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CCER" description="TIM14 capture/compare enable register" start="+0x020" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / tim_oc1 is not active" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / tim_oc1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity." start="3" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CNT" description="TIM14 counter" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_PSC" description="TIM14 prescaler" start="+0x028" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_ARR" description="TIM14 auto-reload register" start="+0x02C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_CCR1" description="TIM14 capture/compare register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM14_TISEL" description="TIM14 timer input selection register" start="+0x05C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM15" description="General purpose timers" start="0x42004000">
+    <Register name="TIM15_CR1" description="TIM15 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt if enabled" start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIM15_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTS less than/sub&gt;= tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIM15_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIM15_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_CR2" description="TIM15 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIM15_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc2=0 when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2=1 when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 57.4.29 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_SMCR" description="TIM15 slave mode control register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DIER" description="TIM15 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_SR" description="TIM15 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIM15_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/Compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_EGR" description="TIM15 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/Compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIM15_SR register. Related interrupt or DMA transfer can occur if enabled" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_CCMR1_INPUT" description="TIM15 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCMR1_OUTPUT" description="TIM15 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIM15_CCR1 disabled. TIM15_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIM15_CCR1 enabled. Read/Write operations access the preload register. TIM15_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIM15_CCR1 and the counter TIM15_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIM15_CNTless thanTIM15_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIM15_CNTless thanTIM15_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input." start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="C2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCER" description="TIM15 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CNT" description="TIM15 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM15_PSC" description="TIM15 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_ARR" description="TIM15 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_RCR" description="TIM15 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCR1" description="TIM15 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCR2" description="TIM15 capture/compare register 2" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_BDTR" description="TIM15 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2 register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be written" start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIM15_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. tim_ocx/tim_ocxn enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk clock failure event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the break input is not be active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIM15_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DTR2" description="TIM15 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_TISEL" description="TIM15 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_AF1" description="TIM15 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_AF2" description="TIM15 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DCR" description="TIM15 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIM15_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIM15_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DMAR" description="TIM15 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM15_S" description="General purpose timers" start="0x52004000">
+    <Register name="TIM15_CR1" description="TIM15 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt if enabled" start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIM15_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTS less than/sub&gt;= tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt; = 2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt; = 4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIM15_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIM15_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_CR2" description="TIM15 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit)." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIM15_SMCR register)." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo)." start="0x3" />
+        <Enum name="B_0x4" description="Compare - tim_oc1refc signal is used as trigger output (tim_trgo)." start="0x4" />
+        <Enum name="B_0x5" description="Compare - tim_oc2refc signal is used as trigger output (tim_trgo)." start="0x5" />
+      </BitField>
+      <BitField name="TI1S" description="tim_ti1 selection" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input" start="0x0" />
+        <Enum name="B_0x1" description="The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination)" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS2" description="Output idle state 2 (tim_oc2 output)" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc2=0 when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc2=1 when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 57.4.29 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_SMCR" description="TIM15 slave mode control register" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="SMS[0]: Slave mode selection" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock." start="0x0" />
+        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers." start="0x4" />
+        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
+        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled." start="0x6" />
+        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter." start="0x7" />
+      </BitField>
+      <BitField name="TS" description="TS[0]: Trigger selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Internal Trigger 0 (tim_itr0)" start="0x0" />
+        <Enum name="B_0x1" description="Internal Trigger 1 (tim_itr1)" start="0x1" />
+        <Enum name="B_0x2" description="Internal Trigger 2 (tim_itr2)" start="0x2" />
+        <Enum name="B_0x3" description="Internal Trigger 3 (tim_itr3)" start="0x3" />
+        <Enum name="B_0x4" description="tim_ti1 Edge Detector (tim_ti1f_ed)" start="0x4" />
+        <Enum name="B_0x5" description="Filtered Timer Input 1 (tim_ti1fp1)" start="0x5" />
+        <Enum name="B_0x6" description="Filtered Timer Input 2 (tim_ti2fp2)" start="0x6" />
+      </BitField>
+      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
+      </BitField>
+      <BitField name="SMS_1" description="SMS[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="TS_1" description="TS[4:3]" start="20" size="2" access="Read/Write" />
+      <BitField name="SMSPE" description="SMS preload enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SMS[3:0] bitfield is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="SMS[3:0] preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DIER" description="TIM15 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_SR" description="TIM15 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" access="Read/Write" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No trigger event occurred" start="0x0" />
+        <Enum name="B_0x1" description="Trigger interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIM15_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+      <BitField name="CC2OF" description="Capture/Compare 2 overcapture flag" start="10" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_EGR" description="TIM15 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+      </BitField>
+      <BitField name="CC2G" description="Capture/Compare 2 generation" start="2" size="1" access="WriteOnly" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="TG" description="Trigger generation" start="6" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="The TIF flag is set in TIM15_SR register. Related interrupt or DMA transfer can occur if enabled" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_CCMR1_INPUT" description="TIM15 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2" start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2" start="0x1" />
+        <Enum name="B_0x2" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1" start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCMR1_OUTPUT" description="TIM15 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1." start="0x1" />
+        <Enum name="B_0x2" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2." start="0x2" />
+        <Enum name="B_0x3" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIM15_CCR1 disabled. TIM15_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIM15_CCR1 enabled. Read/Write operations access the preload register. TIM15_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIM15_CCR1 and the counter TIM15_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIM15_CNT matches the capture/compare register 1 (TIM15_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIM15_CNTless thanTIM15_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIM15_CNTless thanTIM15_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr_int input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input." start="0x1" />
+      </BitField>
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
+        <Enum name="B_0x1" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2." start="0x1" />
+        <Enum name="B_0x2" description="C2 channel is configured as input, tim_ic2 is mapped on tim_ti1." start="0x2" />
+        <Enum name="B_0x3" description="CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIM15_SMCR register)" start="0x3" />
+      </BitField>
+      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
+      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
+      <BitField name="OC2M" description="OC2M[2:0]: Output compare 2 mode" start="12" size="3" access="Read/Write" />
+      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+      <BitField name="OC2M_1" description="OC2M[3]" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCER" description="TIM15 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" access="Read/Write" />
+      <BitField name="CC2P" description="Capture/Compare 2 output polarity" start="5" size="1" access="Read/Write" />
+      <BitField name="CC2NP" description="Capture/Compare 2 complementary output polarity" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CNT" description="TIM15 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM15_PSC" description="TIM15 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_ARR" description="TIM15 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_RCR" description="TIM15 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCR1" description="TIM15 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_CCR2" description="TIM15 capture/compare register 2" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/compare 2 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM15_BDTR" description="TIM15 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2 register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be written" start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIM15_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. tim_ocx/tim_ocxn enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk clock failure event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the break input is not be active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIM15_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DTR2" description="TIM15 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_TISEL" description="TIM15 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+      <BitField name="TI2SEL" description="selects tim_ti2_in[15:0] input" start="8" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CH2 input (tim_ti2_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti2_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti2_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_AF1" description="TIM15 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_AF2" description="TIM15 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DCR" description="TIM15 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIM15_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIM15_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIM15_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+        <Enum name="B_0x3" description="CC2" start="0x3" />
+        <Enum name="B_0x6" description="COM" start="0x6" />
+        <Enum name="B_0x7" description="Trigger" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM15_DMAR" description="TIM15 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM16" description="General purpose timers" start="0x42004400">
+    <Register name="TIM16_CR1" description="TIM16 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="nly counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CR2" description="TIM16 control register 2" start="+0x04" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available)." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DIER" description="TIM16 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_SR" description="TIM16 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_EGR" description="TIM16 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CCMR1_INPUT" description="TIM16 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CCMR1_OUTPUT" description="TIM16 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output Compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input." start="0x1" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_CCER" description="TIM16 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CNT" description="TIM16 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM16_PSC" description="TIM16 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_ARR" description="TIM16 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_RCR" description="TIM16 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_CCR1" description="TIM16 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_BDTR" description="TIM16 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break Disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break Bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DTR2" description="TIM16 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_TISEL" description="TIM16 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_AF1" description="TIM16 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_AF2" description="TIM16 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="tim_ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DCR" description="TIM16 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DMAR" description="TIM16/TIM17 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM16_S" description="General purpose timers" start="0x52004400">
+    <Register name="TIM16_CR1" description="TIM16 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="nly counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CR2" description="TIM16 control register 2" start="+0x04" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available)." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DIER" description="TIM16 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_SR" description="TIM16 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_EGR" description="TIM16 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CCMR1_INPUT" description="TIM16 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CCMR1_OUTPUT" description="TIM16 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output Compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input." start="0x1" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_CCER" description="TIM16 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_CNT" description="TIM16 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM16_PSC" description="TIM16 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_ARR" description="TIM16 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_RCR" description="TIM16 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_CCR1" description="TIM16 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM16_BDTR" description="TIM16 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break Disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break Bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DTR2" description="TIM16 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_TISEL" description="TIM16 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_AF1" description="TIM16 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_AF2" description="TIM16 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="tim_ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DCR" description="TIM16 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="TIM16_DMAR" description="TIM16/TIM17 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM17" description="General purpose timers" start="0x42004800">
+    <Register name="TIM17_CR1" description="TIM17 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="nly counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CR2" description="TIM17 control register 2" start="+0x04" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available)." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DIER" description="TIM17 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_SR" description="TIM17 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_EGR" description="TIM17 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CCMR1_INPUT" description="TIM17 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CCMR1_OUTPUT" description="TIM17 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output Compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input." start="0x1" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_CCER" description="TIM17 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CNT" description="TIM17 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM17_PSC" description="TIM17 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_ARR" description="TIM17 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_RCR" description="TIM17 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_CCR1" description="TIM17 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_BDTR" description="TIM17 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break Disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break Bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DTR2" description="TIM17 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_TISEL" description="TIM17 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_AF1" description="TIM17 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_AF2" description="TIM17 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="tim_ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DCR" description="TIM17 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DMAR" description="TIM16/TIM17 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM17_S" description="General purpose timers" start="0x52004800">
+    <Register name="TIM17_CR1" description="TIM17 control register 1" start="+0x00" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="nly counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
+      </BitField>
+      <BitField name="CKD" description="Clock division" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="tless thansub&gt;DTSless than/sub&gt;=tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="tless thansub&gt;DTSless than/sub&gt;=2*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x1" />
+        <Enum name="B_0x2" description="tless thansub&gt;DTSless than/sub&gt;=4*tless thansub&gt;tim_ker_ckless than/sub&gt;" start="0x2" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CR2" description="TIM17 control register 2" start="+0x04" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
+      </BitField>
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
+        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available)." start="0x1" />
+      </BitField>
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
+        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
+      </BitField>
+      <BitField name="OIS1" description="Output Idle state 1 (tim_oc1 output)" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+      <BitField name="OIS1N" description="Output Idle state 1 (tim_oc1n output)" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n=0 after a dead-time when MOE=0" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n=1 after a dead-time when MOE=0" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DIER" description="TIM17 DMA/interrupt enable register" start="+0x0C" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
+      </BitField>
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
+        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_SR" description="TIM17 status register" start="+0x10" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
+        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
+      </BitField>
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
+        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
+      </BitField>
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
+        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
+      </BitField>
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
+        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_EGR" description="TIM17 event generation register" start="+0x14" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+      <BitField name="CC1G" description="Capture/Compare 1 generation" start="1" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
+      </BitField>
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action" start="0x0" />
+        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
+      </BitField>
+      <BitField name="BG" description="Break generation" start="7" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CCMR1_INPUT" description="TIM17 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
+        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
+        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
+        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
+      </BitField>
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, sampling is done at fless thansub&gt;DTSless than/sub&gt;" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CCMR1_OUTPUT" description="TIM17 capture/compare mode register 1" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
+        <Enum name="B_0x1" description="CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1" start="0x1" />
+      </BitField>
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
+        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, tim_ocx is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
+      </BitField>
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
+        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
+      </BitField>
+      <BitField name="OC1M" description="OC1M[2:0]: Output Compare 1 mode" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state." start="0x0" />
+        <Enum name="B_0x1" description="Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
+        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
+        <Enum name="B_0x3" description="Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
+        <Enum name="B_0x4" description="Force inactive level - tim_oc1ref is forced low." start="0x4" />
+        <Enum name="B_0x5" description="Force active level - tim_oc1ref is forced high." start="0x5" />
+        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive." start="0x6" />
+        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active." start="0x7" />
+      </BitField>
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1ref is not affected by the tim_ocref_clr input." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input." start="0x1" />
+      </BitField>
+      <BitField name="OC1M_1" description="OC1M[3]" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_CCER" description="TIM17 capture/compare enable register" start="+0x20" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
+        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
+      </BitField>
+      <BitField name="CC1P" description="Capture/Compare 1 output polarity" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
+        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
+      </BitField>
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
+        <Enum name="B_0x1" description="On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
+      </BitField>
+      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1n active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1n active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_CNT" description="TIM17 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM17_PSC" description="TIM17 prescaler" start="+0x28" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_ARR" description="TIM17 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_RCR" description="TIM17 repetition counter register" start="+0x30" size="2" reset_value="0x0000" reset_mask="0xFFFF">
+      <BitField name="REP" description="Repetition counter reload value" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_CCR1" description="TIM17 capture/compare register 1" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="TIM17_BDTR" description="TIM17 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
+        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
+        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
+        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
+      </BitField>
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1)" start="0x1" />
+      </BitField>
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
+        <Enum name="B_0x1" description="When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer)." start="0x1" />
+      </BitField>
+      <BitField name="BKE" description="Break enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break inputs (tim_brk and tim_sys_brk event) disabled" start="0x0" />
+      </BitField>
+      <BitField name="BKP" description="Break polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is active low" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is active high" start="0x1" />
+      </BitField>
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
+        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)" start="0x1" />
+      </BitField>
+      <BitField name="MOE" description="Main output enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
+        <Enum name="B_0x1" description="tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)" start="0x1" />
+      </BitField>
+      <BitField name="BKF" description="Break filter" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No filter, tim_brk acts asynchronously" start="0x0" />
+        <Enum name="B_0x1" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=2" start="0x1" />
+        <Enum name="B_0x2" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=4" start="0x2" />
+        <Enum name="B_0x3" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;tim_ker_ckless than/sub&gt;, N=8" start="0x3" />
+        <Enum name="B_0x4" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=6" start="0x4" />
+        <Enum name="B_0x5" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/2, N=8" start="0x5" />
+        <Enum name="B_0x6" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=6" start="0x6" />
+        <Enum name="B_0x7" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/4, N=8" start="0x7" />
+        <Enum name="B_0x8" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=6" start="0x8" />
+        <Enum name="B_0x9" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/8, N=8" start="0x9" />
+        <Enum name="B_0xA" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=5" start="0xA" />
+        <Enum name="B_0xB" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=6" start="0xB" />
+        <Enum name="B_0xC" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/16, N=8" start="0xC" />
+        <Enum name="B_0xD" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=5" start="0xD" />
+        <Enum name="B_0xE" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=6" start="0xE" />
+        <Enum name="B_0xF" description="fless thansub&gt;SAMPLINGless than/sub&gt;=fless thansub&gt;DTSless than/sub&gt;/32, N=8" start="0xF" />
+      </BitField>
+      <BitField name="BKDSRM" description="Break Disarm" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk is armed" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk is disarmed" start="0x1" />
+      </BitField>
+      <BitField name="BKBID" description="Break Bidirectional" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Break input tim_brk in input mode" start="0x0" />
+        <Enum name="B_0x1" description="Break input tim_brk in bidirectional mode" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DTR2" description="TIM17 timer deadtime register 2" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTGF" description="Dead-time falling edge generator setup" start="0" size="8" access="Read/Write" />
+      <BitField name="DTAE" description="Deadtime asymmetric enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits." start="0x1" />
+      </BitField>
+      <BitField name="DTPE" description="Deadtime preload enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Deadtime value is not preloaded" start="0x0" />
+        <Enum name="B_0x1" description="Deadtime value preload is enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_TISEL" description="TIM17 input selection register" start="+0x5C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects tim_ti1_in[15:0] input" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CH1 input (tim_ti1_in0)" start="0x0" />
+        <Enum name="B_0x1" description="tim_ti1_in1" start="0x1" />
+        <Enum name="B_0xF" description="tim_ti1_in15" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_AF1" description="TIM17 alternate function register 1" start="+0x060" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="TIMx_BKIN input enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input disabled" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1E" description="tim_brk_cmp1 enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2E" description="tim_brk_cmp2 enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3E" description="tim_brk_cmp3 enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4E" description="tim_brk_cmp4 enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP5E" description="tim_brk_cmp5 enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp5 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp5 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP6E" description="tim_brk_cmp6 enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp6 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp6 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP7E" description="tim_brk_cmp7 enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp7 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp7 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP8E" description="tim_brk_cmp8 enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp8 input disabled" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp8 input enabled" start="0x1" />
+      </BitField>
+      <BitField name="BKINP" description="TIMx_BKIN input polarity" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_BKIN input is active high" start="0x0" />
+        <Enum name="B_0x1" description="TIMx_BKIN input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP1P" description="tim_brk_cmp1 input polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp1 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp1 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP2P" description="tim_brk_cmp2 input polarity" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp2 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp2 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP3P" description="tim_brk_cmp3 input polarity" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp3 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp3 input is active low" start="0x1" />
+      </BitField>
+      <BitField name="BKCMP4P" description="tim_brk_cmp4 input polarity" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="tim_brk_cmp4 input is active high" start="0x0" />
+        <Enum name="B_0x1" description="tim_brk_cmp4 input is active low" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_AF2" description="TIM17 alternate function register 2" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCRSEL" description="tim_ocref_clr source selection" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="tim_ocref_clr0" start="0x0" />
+        <Enum name="B_0x1" description="tim_ocref_clr1" start="0x1" />
+        <Enum name="B_0x2" description="tim_ocref_clr2" start="0x2" />
+        <Enum name="B_0x3" description="tim_ocref_clr3" start="0x3" />
+        <Enum name="B_0x4" description="tim_ocref_clr4" start="0x4" />
+        <Enum name="B_0x5" description="tim_ocref_clr5" start="0x5" />
+        <Enum name="B_0x6" description="tim_ocref_clr6" start="0x6" />
+        <Enum name="B_0x7" description="tim_ocref_clr7" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DCR" description="TIM17 DMA control register" start="+0x3DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBA" description="DMA base address" start="0" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
+        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
+        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
+      </BitField>
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="1 transfer," start="0x0" />
+        <Enum name="B_0x1" description="2 transfers," start="0x1" />
+        <Enum name="B_0x2" description="3 transfers," start="0x2" />
+        <Enum name="B_0x11" description="18 transfers." start="0x11" />
+      </BitField>
+      <BitField name="DBSS" description="DMA burst source selection" start="16" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="Update" start="0x1" />
+        <Enum name="B_0x2" description="CC1" start="0x2" />
+      </BitField>
+    </Register>
+    <Register name="TIM17_DMAR" description="TIM16/TIM17 DMA address for full transfer" start="+0x3E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM18" description="Basic timers" start="0x42003C00">
+    <Register name="TIM18_CR1" description="TIM18 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_CR2" description="TIM18 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_DIER" description="TIM18 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_SR" description="TIM18 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_EGR" description="TIM18 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_CNT" description="TIM18 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM18_PSC" description="TIM18 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM18_ARR" description="TIM18 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM18_S" description="Basic timers" start="0x52003C00">
+    <Register name="TIM18_CR1" description="TIM18 control register 1" start="+0x00" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
+        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
+      </BitField>
+      <BitField name="UDIS" description="Update disable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
+        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
+      </BitField>
+      <BitField name="URS" description="Update request source" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Any of the following events generates an update interrupt or DMA request if enabled. These events can be:" start="0x0" />
+        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
+      </BitField>
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
+        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the CEN bit)." start="0x1" />
+      </BitField>
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TIMx_ARR register is not buffered." start="0x0" />
+        <Enum name="B_0x1" description="TIMx_ARR register is buffered." start="0x1" />
+      </BitField>
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
+        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
+      </BitField>
+      <BitField name="DITHEN" description="Dithering enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Dithering disabled" start="0x0" />
+        <Enum name="B_0x1" description="Dithering enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_CR2" description="TIM18 control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo)." start="0x0" />
+        <Enum name="B_0x1" description="Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written." start="0x1" />
+        <Enum name="B_0x2" description="Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
+      </BitField>
+      <BitField name="ADSYNC" description="ADC synchronization" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The timer operates independently from the ADC" start="0x0" />
+        <Enum name="B_0x1" description="The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_DIER" description="TIM18 DMA/Interrupt enable register" start="+0x0C" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
+      </BitField>
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
+        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_SR" description="TIM18 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No update occurred." start="0x0" />
+        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_EGR" description="TIM18 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" access="WriteOnly">
+        <Enum name="B_0x0" description="No action." start="0x0" />
+        <Enum name="B_0x1" description="Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="TIM18_CNT" description="TIM18 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TIM18_PSC" description="TIM18 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="TIM18_ARR" description="TIM18 auto-reload register" start="+0x2C" size="4" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UCPD" description="USB Type-C/USB Power Delivery interface" start="0x4000FC00">
+    <Register name="UCPD_CFGR1" description="UCPD configuration register 1" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HBITCLKDIV" description="Division ratio for producing half-bit clock" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 (bypass)" start="0x00" />
+        <Enum name="B_0x1A" description="27" start="0x1A" />
+        <Enum name="B_0x3F" description="64" start="0x3F" />
+      </BitField>
+      <BitField name="IFRGAP" description="Division ratio for producing inter-frame gap timer clock" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="Not supported" start="0x00" />
+        <Enum name="B_0x01" description="2" start="0x01" />
+        <Enum name="B_0x0D" description="14" start="0x0D" />
+        <Enum name="B_0x0E" description="15" start="0x0E" />
+        <Enum name="B_0x0F" description="16" start="0x0F" />
+        <Enum name="B_0x1F" description="32" start="0x1F" />
+      </BitField>
+      <BitField name="TRANSWIN" description="Transition window duration" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="Not supported" start="0x00" />
+        <Enum name="B_0x01" description="2" start="0x01" />
+        <Enum name="B_0x09" description="10 (recommended)" start="0x09" />
+        <Enum name="B_0x1F" description="32" start="0x1F" />
+      </BitField>
+      <BitField name="PSC_USBPDCLK" description="Pre-scaler division ratio for generating ucpd_clk" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 (bypass)" start="0x0" />
+        <Enum name="B_0x1" description="2" start="0x1" />
+        <Enum name="B_0x2" description="4" start="0x2" />
+        <Enum name="B_0x3" description="8" start="0x3" />
+        <Enum name="B_0x4" description="16" start="0x4" />
+      </BitField>
+      <BitField name="RXORDSETEN" description="Receiver ordered set enable" start="20" size="9" access="Read/Write" />
+      <BitField name="TXDMAEN" description="Transmission DMA mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Reception DMA mode enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="UCPDEN" description="UCPD peripheral enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_CFGR2" description="UCPD configuration register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFILTDIS" description="BMC decoder Rx pre-filter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+      <BitField name="RXFILT2N3" description="BMC decoder Rx pre-filter sampling method" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3 samples" start="0x0" />
+        <Enum name="B_0x1" description="2 samples" start="0x1" />
+      </BitField>
+      <BitField name="FORCECLK" description="Force ClkReq clock request" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force clock request" start="0x0" />
+        <Enum name="B_0x1" description="Force clock request" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_CR" description="UCPD control register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMODE" description="Type of Tx packet" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission of Tx packet previously defined in other registers" start="0x0" />
+        <Enum name="B_0x1" description="Cable Reset sequence" start="0x1" />
+        <Enum name="B_0x2" description="BIST test sequence (BIST Carrier Mode 2)" start="0x2" />
+      </BitField>
+      <BitField name="TXSEND" description="Command to send a Tx packet" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Start Tx packet transmission" start="0x1" />
+      </BitField>
+      <BitField name="TXHRST" description="Command to send a Tx Hard Reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Start Tx Hard Reset message" start="0x1" />
+      </BitField>
+      <BitField name="RXMODE" description="Receiver mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal receive mode" start="0x0" />
+        <Enum name="B_0x1" description="BIST receive mode (BIST test data mode)" start="0x1" />
+      </BitField>
+      <BitField name="PHYRXEN" description="USB Power Delivery receiver enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="PHYCCSEL" description="CC1/CC2 line selector for USB Power Delivery signaling" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Use CC1 IO for Power Delivery communication" start="0x0" />
+        <Enum name="B_0x1" description="Use CC2 IO for Power Delivery communication" start="0x1" />
+      </BitField>
+      <BitField name="ANASUBMODE" description="Analog PHY sub-mode" start="7" size="2" access="Read/Write" />
+      <BitField name="ANAMODE" description="Analog PHY operating mode" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Source" start="0x0" />
+        <Enum name="B_0x1" description="Sink" start="0x1" />
+      </BitField>
+      <BitField name="CCENABLE" description="CC line enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Disable both PHYs" start="0x0" />
+        <Enum name="B_0x1" description="Enable CC1 PHY" start="0x1" />
+        <Enum name="B_0x2" description="Enable CC2 PHY" start="0x2" />
+        <Enum name="B_0x3" description="Enable CC1 and CC2 PHY" start="0x3" />
+      </BitField>
+      <BitField name="FRSRXEN" description="FRS event detection enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="FRSTX" description="FRS Tx signaling enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RDCH" description="Rdch condition drive" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Rdch condition drive" start="0x1" />
+      </BitField>
+      <BitField name="CC1TCDIS" description="CC1 Type-C detector disable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+      <BitField name="CC2TCDIS" description="CC2 Type-C detector disable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_IMR" description="UCPD interrupt mask register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXISIE" description="TXIS interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGDISCIE" description="TXMSGDISC interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGSENTIE" description="TXMSGSENT interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGABTIE" description="TXMSGABT interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="HRSTDISCIE" description="HRSTDISC interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="HRSTSENTIE" description="HRSTSENT interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDIE" description="TXUND interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXORDDETIE" description="RXORDDET interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXHRSTDETIE" description="RXHRSTDET interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXOVRIE" description="RXOVR interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXMSGENDIE" description="RXMSGEND interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT1IE" description="TYPECEVT1 interrupt enable" start="14" size="1" access="Read/Write" />
+      <BitField name="TYPECEVT2IE" description="TYPECEVT2 interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="FRSEVTIE" description="FRSEVT interrupt enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_SR" description="UCPD status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXIS" description="Transmit interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="New Tx data write not required" start="0x0" />
+        <Enum name="B_0x1" description="New Tx data write required" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGDISC" description="Message transmission discarded" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx message discarded" start="0x0" />
+        <Enum name="B_0x1" description="Tx message discarded" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGSENT" description="Message transmission completed" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx message completed" start="0x0" />
+        <Enum name="B_0x1" description="Tx message completed" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGABT" description="Transmit message abort" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit message abort" start="0x0" />
+        <Enum name="B_0x1" description="Transmit message abort" start="0x1" />
+      </BitField>
+      <BitField name="HRSTDISC" description="Hard Reset discarded" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hard Reset discarded" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset discarded" start="0x1" />
+      </BitField>
+      <BitField name="HRSTSENT" description="Hard Reset message sent" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hard Reset message sent" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset message sent" start="0x1" />
+      </BitField>
+      <BitField name="TXUND" description="Tx data underrun detection" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx data underrun detected" start="0x0" />
+        <Enum name="B_0x1" description="Tx data underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Receive data register not empty detection" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx data register empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx data register not empty" start="0x1" />
+      </BitField>
+      <BitField name="RXORDDET" description="Rx ordered set (4 K-codes) detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No ordered set detected" start="0x0" />
+        <Enum name="B_0x1" description="A new ordered set detected" start="0x1" />
+      </BitField>
+      <BitField name="RXHRSTDET" description="Rx Hard Reset receipt detection" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Hard Reset not received" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset received" start="0x1" />
+      </BitField>
+      <BitField name="RXOVR" description="Rx data overflow detection" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow" start="0x1" />
+      </BitField>
+      <BitField name="RXMSGEND" description="Rx message received" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new Rx message received" start="0x0" />
+        <Enum name="B_0x1" description="A new Rx message received" start="0x1" />
+      </BitField>
+      <BitField name="RXERR" description="Receive message error" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error detected" start="0x0" />
+        <Enum name="B_0x1" description="Error(s) detected" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT1" description="Type-C voltage level event on CC1 line" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="A new Type-C event" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT2" description="Type-C voltage level event on CC2 line" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="A new Type-C event" start="0x1" />
+      </BitField>
+      <BitField name="TYPEC_VSTATE_CC1" description="The status bitfield indicates the voltage level on the CC1 line in its steady state." start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Lowest" start="0x0" />
+        <Enum name="B_0x1" description="Low" start="0x1" />
+        <Enum name="B_0x2" description="High" start="0x2" />
+        <Enum name="B_0x3" description="Highest" start="0x3" />
+      </BitField>
+      <BitField name="TYPEC_VSTATE_CC2" description="CC2 line voltage level" start="18" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Lowest" start="0x0" />
+        <Enum name="B_0x1" description="Low" start="0x1" />
+        <Enum name="B_0x2" description="High" start="0x2" />
+        <Enum name="B_0x3" description="Highest" start="0x3" />
+      </BitField>
+      <BitField name="FRSEVT" description="FRS detection event" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="New FRS receive event occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_ICR" description="UCPD interrupt clear register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMSGDISCCF" description="Tx message discard flag (TXMSGDISC) clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="TXMSGSENTCF" description="Tx message send flag (TXMSGSENT) clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="TXMSGABTCF" description="Tx message abort flag (TXMSGABT) clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="HRSTDISCCF" description="Hard reset discard flag (HRSTDISC) clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="HRSTSENTCF" description="Hard reset send flag (HRSTSENT) clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="TXUNDCF" description="Tx underflow flag (TXUND) clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="RXORDDETCF" description="Rx ordered set detect flag (RXORDDET) clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="RXHRSTDETCF" description="Rx Hard Reset detect flag (RXHRSTDET) clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="RXOVRCF" description="Rx overflow flag (RXOVR) clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="RXMSGENDCF" description="Rx message received flag (RXMSGEND) clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="TYPECEVT1CF" description="Type-C CC1 event flag (TYPECEVT1) clear" start="14" size="1" access="WriteOnly" />
+      <BitField name="TYPECEVT2CF" description="Type-C CC2 line event flag (TYPECEVT2) clear" start="15" size="1" access="WriteOnly" />
+      <BitField name="FRSEVTCF" description="FRS event flag (FRSEVT) clear" start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="UCPD_TX_ORDSETR" description="UCPD Tx ordered set type register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXORDSET" description="Ordered set to transmit" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_TX_PAYSZR" description="UCPD Tx payload size register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXPAYSZ" description="Payload size yet to transmit" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x2" description="2 bytes - the size of Control message from the protocol layer" start="0x2" />
+        <Enum name="B_0x6" description="6 bytes - the shortest Data message allowed from the protocol layer)" start="0x6" />
+        <Enum name="B_0x1E" description="30 bytes - the longest non-extended Data message allowed from the protocol layer" start="0x1E" />
+        <Enum name="B_0x106" description="262 bytes - the longest possible extended message" start="0x106" />
+        <Enum name="B_0x3FF" description="1024 bytes - the longest possible payload (for future expansion)" start="0x3FF" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_TXDR" description="UCPD Tx data register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="Data byte to transmit" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_RX_ORDSETR" description="UCPD Rx ordered set register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXORDSET" description="Rx ordered set code detected" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="SOP code detected in receiver" start="0x0" />
+        <Enum name="B_0x1" description="SOP' code detected in receiver" start="0x1" />
+        <Enum name="B_0x2" description="SOP'' code detected in receiver" start="0x2" />
+        <Enum name="B_0x3" description="SOP'_Debug detected in receiver" start="0x3" />
+        <Enum name="B_0x4" description="SOP''_Debug detected in receiver" start="0x4" />
+        <Enum name="B_0x5" description="Cable Reset detected in receiver" start="0x5" />
+        <Enum name="B_0x6" description="SOP extension#1 detected in receiver" start="0x6" />
+        <Enum name="B_0x7" description="SOP extension#2 detected in receiver" start="0x7" />
+      </BitField>
+      <BitField name="RXSOP3OF4" description="The bit indicates the number of correct K-codes. For debug purposes only." start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="4 correct K-codes out of 4" start="0x0" />
+        <Enum name="B_0x1" description="3 correct K-codes out of 4" start="0x1" />
+      </BitField>
+      <BitField name="RXSOPKINVALID" description="The bitfield is for debug purposes only." start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No K-code corrupted" start="0x0" />
+        <Enum name="B_0x1" description="First K-code corrupted" start="0x1" />
+        <Enum name="B_0x2" description="Second K-code corrupted" start="0x2" />
+        <Enum name="B_0x3" description="Third K-code corrupted" start="0x3" />
+        <Enum name="B_0x4" description="Fourth K-code corrupted" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_RX_PAYSZR" description="UCPD Rx payload size register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPAYSZ" description="Rx payload size received" start="0" size="10" access="ReadOnly">
+        <Enum name="B_0x2" description="2 bytes - the size of Control message from the protocol layer" start="0x2" />
+        <Enum name="B_0x6" description="6 bytes - the shortest Data message allowed from the protocol layer)" start="0x6" />
+        <Enum name="B_0x1E" description="30 bytes - the longest non-extended Data message allowed from the protocol layer" start="0x1E" />
+        <Enum name="B_0x106" description="262 bytes - the longest possible extended message" start="0x106" />
+        <Enum name="B_0x3FF" description="1024 bytes - the longest possible payload (for future expansion)" start="0x3FF" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_RXDR" description="UCPD receive data register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="Data byte received" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="UCPD_RX_ORDEXTR1" description="UCPD Rx ordered set extension register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXSOPX1" description="Ordered set 1 received" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_RX_ORDEXTR2" description="UCPD Rx ordered set extension register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXSOPX2" description="Ordered set 2 received" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UCPD_S" description="USB Type-C/USB Power Delivery interface" start="0x5000FC00">
+    <Register name="UCPD_CFGR1" description="UCPD configuration register 1" start="+0x000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HBITCLKDIV" description="Division ratio for producing half-bit clock" start="0" size="6" access="Read/Write">
+        <Enum name="B_0x00" description="1 (bypass)" start="0x00" />
+        <Enum name="B_0x1A" description="27" start="0x1A" />
+        <Enum name="B_0x3F" description="64" start="0x3F" />
+      </BitField>
+      <BitField name="IFRGAP" description="Division ratio for producing inter-frame gap timer clock" start="6" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="Not supported" start="0x00" />
+        <Enum name="B_0x01" description="2" start="0x01" />
+        <Enum name="B_0x0D" description="14" start="0x0D" />
+        <Enum name="B_0x0E" description="15" start="0x0E" />
+        <Enum name="B_0x0F" description="16" start="0x0F" />
+        <Enum name="B_0x1F" description="32" start="0x1F" />
+      </BitField>
+      <BitField name="TRANSWIN" description="Transition window duration" start="11" size="5" access="Read/Write">
+        <Enum name="B_0x00" description="Not supported" start="0x00" />
+        <Enum name="B_0x01" description="2" start="0x01" />
+        <Enum name="B_0x09" description="10 (recommended)" start="0x09" />
+        <Enum name="B_0x1F" description="32" start="0x1F" />
+      </BitField>
+      <BitField name="PSC_USBPDCLK" description="Pre-scaler division ratio for generating ucpd_clk" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 (bypass)" start="0x0" />
+        <Enum name="B_0x1" description="2" start="0x1" />
+        <Enum name="B_0x2" description="4" start="0x2" />
+        <Enum name="B_0x3" description="8" start="0x3" />
+        <Enum name="B_0x4" description="16" start="0x4" />
+      </BitField>
+      <BitField name="RXORDSETEN" description="Receiver ordered set enable" start="20" size="9" access="Read/Write" />
+      <BitField name="TXDMAEN" description="Transmission DMA mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXDMAEN" description="Reception DMA mode enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="UCPDEN" description="UCPD peripheral enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_CFGR2" description="UCPD configuration register 2" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFILTDIS" description="BMC decoder Rx pre-filter enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+      <BitField name="RXFILT2N3" description="BMC decoder Rx pre-filter sampling method" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="3 samples" start="0x0" />
+        <Enum name="B_0x1" description="2 samples" start="0x1" />
+      </BitField>
+      <BitField name="FORCECLK" description="Force ClkReq clock request" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Do not force clock request" start="0x0" />
+        <Enum name="B_0x1" description="Force clock request" start="0x1" />
+      </BitField>
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_CR" description="UCPD control register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMODE" description="Type of Tx packet" start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Transmission of Tx packet previously defined in other registers" start="0x0" />
+        <Enum name="B_0x1" description="Cable Reset sequence" start="0x1" />
+        <Enum name="B_0x2" description="BIST test sequence (BIST Carrier Mode 2)" start="0x2" />
+      </BitField>
+      <BitField name="TXSEND" description="Command to send a Tx packet" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Start Tx packet transmission" start="0x1" />
+      </BitField>
+      <BitField name="TXHRST" description="Command to send a Tx Hard Reset" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Start Tx Hard Reset message" start="0x1" />
+      </BitField>
+      <BitField name="RXMODE" description="Receiver mode" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal receive mode" start="0x0" />
+        <Enum name="B_0x1" description="BIST receive mode (BIST test data mode)" start="0x1" />
+      </BitField>
+      <BitField name="PHYRXEN" description="USB Power Delivery receiver enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="PHYCCSEL" description="CC1/CC2 line selector for USB Power Delivery signaling" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Use CC1 IO for Power Delivery communication" start="0x0" />
+        <Enum name="B_0x1" description="Use CC2 IO for Power Delivery communication" start="0x1" />
+      </BitField>
+      <BitField name="ANASUBMODE" description="Analog PHY sub-mode" start="7" size="2" access="Read/Write" />
+      <BitField name="ANAMODE" description="Analog PHY operating mode" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Source" start="0x0" />
+        <Enum name="B_0x1" description="Sink" start="0x1" />
+      </BitField>
+      <BitField name="CCENABLE" description="CC line enable" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Disable both PHYs" start="0x0" />
+        <Enum name="B_0x1" description="Enable CC1 PHY" start="0x1" />
+        <Enum name="B_0x2" description="Enable CC2 PHY" start="0x2" />
+        <Enum name="B_0x3" description="Enable CC1 and CC2 PHY" start="0x3" />
+      </BitField>
+      <BitField name="FRSRXEN" description="FRS event detection enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="FRSTX" description="FRS Tx signaling enable." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RDCH" description="Rdch condition drive" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No effect" start="0x0" />
+        <Enum name="B_0x1" description="Rdch condition drive" start="0x1" />
+      </BitField>
+      <BitField name="CC1TCDIS" description="CC1 Type-C detector disable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+      <BitField name="CC2TCDIS" description="CC2 Type-C detector disable" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Enable" start="0x0" />
+        <Enum name="B_0x1" description="Disable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_IMR" description="UCPD interrupt mask register" start="+0x010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXISIE" description="TXIS interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGDISCIE" description="TXMSGDISC interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGSENTIE" description="TXMSGSENT interrupt enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGABTIE" description="TXMSGABT interrupt enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="HRSTDISCIE" description="HRSTDISC interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="HRSTSENTIE" description="HRSTSENT interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TXUNDIE" description="TXUND interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXORDDETIE" description="RXORDDET interrupt enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXHRSTDETIE" description="RXHRSTDET interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXOVRIE" description="RXOVR interrupt enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="RXMSGENDIE" description="RXMSGEND interrupt enable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT1IE" description="TYPECEVT1 interrupt enable" start="14" size="1" access="Read/Write" />
+      <BitField name="TYPECEVT2IE" description="TYPECEVT2 interrupt enable" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+      <BitField name="FRSEVTIE" description="FRSEVT interrupt enable" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Disable" start="0x0" />
+        <Enum name="B_0x1" description="Enable" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_SR" description="UCPD status register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXIS" description="Transmit interrupt status" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="New Tx data write not required" start="0x0" />
+        <Enum name="B_0x1" description="New Tx data write required" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGDISC" description="Message transmission discarded" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx message discarded" start="0x0" />
+        <Enum name="B_0x1" description="Tx message discarded" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGSENT" description="Message transmission completed" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx message completed" start="0x0" />
+        <Enum name="B_0x1" description="Tx message completed" start="0x1" />
+      </BitField>
+      <BitField name="TXMSGABT" description="Transmit message abort" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No transmit message abort" start="0x0" />
+        <Enum name="B_0x1" description="Transmit message abort" start="0x1" />
+      </BitField>
+      <BitField name="HRSTDISC" description="Hard Reset discarded" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hard Reset discarded" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset discarded" start="0x1" />
+      </BitField>
+      <BitField name="HRSTSENT" description="Hard Reset message sent" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Hard Reset message sent" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset message sent" start="0x1" />
+      </BitField>
+      <BitField name="TXUND" description="Tx data underrun detection" start="6" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Tx data underrun detected" start="0x0" />
+        <Enum name="B_0x1" description="Tx data underrun detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Receive data register not empty detection" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Rx data register empty" start="0x0" />
+        <Enum name="B_0x1" description="Rx data register not empty" start="0x1" />
+      </BitField>
+      <BitField name="RXORDDET" description="Rx ordered set (4 K-codes) detection" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No ordered set detected" start="0x0" />
+        <Enum name="B_0x1" description="A new ordered set detected" start="0x1" />
+      </BitField>
+      <BitField name="RXHRSTDET" description="Rx Hard Reset receipt detection" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Hard Reset not received" start="0x0" />
+        <Enum name="B_0x1" description="Hard Reset received" start="0x1" />
+      </BitField>
+      <BitField name="RXOVR" description="Rx data overflow detection" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overflow" start="0x0" />
+        <Enum name="B_0x1" description="Overflow" start="0x1" />
+      </BitField>
+      <BitField name="RXMSGEND" description="Rx message received" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new Rx message received" start="0x0" />
+        <Enum name="B_0x1" description="A new Rx message received" start="0x1" />
+      </BitField>
+      <BitField name="RXERR" description="Receive message error" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No error detected" start="0x0" />
+        <Enum name="B_0x1" description="Error(s) detected" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT1" description="Type-C voltage level event on CC1 line" start="14" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="A new Type-C event" start="0x1" />
+      </BitField>
+      <BitField name="TYPECEVT2" description="Type-C voltage level event on CC2 line" start="15" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="A new Type-C event" start="0x1" />
+      </BitField>
+      <BitField name="TYPEC_VSTATE_CC1" description="The status bitfield indicates the voltage level on the CC1 line in its steady state." start="16" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Lowest" start="0x0" />
+        <Enum name="B_0x1" description="Low" start="0x1" />
+        <Enum name="B_0x2" description="High" start="0x2" />
+        <Enum name="B_0x3" description="Highest" start="0x3" />
+      </BitField>
+      <BitField name="TYPEC_VSTATE_CC2" description="CC2 line voltage level" start="18" size="2" access="ReadOnly">
+        <Enum name="B_0x0" description="Lowest" start="0x0" />
+        <Enum name="B_0x1" description="Low" start="0x1" />
+        <Enum name="B_0x2" description="High" start="0x2" />
+        <Enum name="B_0x3" description="Highest" start="0x3" />
+      </BitField>
+      <BitField name="FRSEVT" description="FRS detection event" start="20" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new event" start="0x0" />
+        <Enum name="B_0x1" description="New FRS receive event occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_ICR" description="UCPD interrupt clear register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMSGDISCCF" description="Tx message discard flag (TXMSGDISC) clear" start="1" size="1" access="WriteOnly" />
+      <BitField name="TXMSGSENTCF" description="Tx message send flag (TXMSGSENT) clear" start="2" size="1" access="WriteOnly" />
+      <BitField name="TXMSGABTCF" description="Tx message abort flag (TXMSGABT) clear" start="3" size="1" access="WriteOnly" />
+      <BitField name="HRSTDISCCF" description="Hard reset discard flag (HRSTDISC) clear" start="4" size="1" access="WriteOnly" />
+      <BitField name="HRSTSENTCF" description="Hard reset send flag (HRSTSENT) clear" start="5" size="1" access="WriteOnly" />
+      <BitField name="TXUNDCF" description="Tx underflow flag (TXUND) clear" start="6" size="1" access="WriteOnly" />
+      <BitField name="RXORDDETCF" description="Rx ordered set detect flag (RXORDDET) clear" start="9" size="1" access="WriteOnly" />
+      <BitField name="RXHRSTDETCF" description="Rx Hard Reset detect flag (RXHRSTDET) clear" start="10" size="1" access="WriteOnly" />
+      <BitField name="RXOVRCF" description="Rx overflow flag (RXOVR) clear" start="11" size="1" access="WriteOnly" />
+      <BitField name="RXMSGENDCF" description="Rx message received flag (RXMSGEND) clear" start="12" size="1" access="WriteOnly" />
+      <BitField name="TYPECEVT1CF" description="Type-C CC1 event flag (TYPECEVT1) clear" start="14" size="1" access="WriteOnly" />
+      <BitField name="TYPECEVT2CF" description="Type-C CC2 line event flag (TYPECEVT2) clear" start="15" size="1" access="WriteOnly" />
+      <BitField name="FRSEVTCF" description="FRS event flag (FRSEVT) clear" start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="UCPD_TX_ORDSETR" description="UCPD Tx ordered set type register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXORDSET" description="Ordered set to transmit" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_TX_PAYSZR" description="UCPD Tx payload size register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXPAYSZ" description="Payload size yet to transmit" start="0" size="10" access="Read/Write">
+        <Enum name="B_0x2" description="2 bytes - the size of Control message from the protocol layer" start="0x2" />
+        <Enum name="B_0x6" description="6 bytes - the shortest Data message allowed from the protocol layer)" start="0x6" />
+        <Enum name="B_0x1E" description="30 bytes - the longest non-extended Data message allowed from the protocol layer" start="0x1E" />
+        <Enum name="B_0x106" description="262 bytes - the longest possible extended message" start="0x106" />
+        <Enum name="B_0x3FF" description="1024 bytes - the longest possible payload (for future expansion)" start="0x3FF" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_TXDR" description="UCPD Tx data register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="Data byte to transmit" start="0" size="8" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_RX_ORDSETR" description="UCPD Rx ordered set register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXORDSET" description="Rx ordered set code detected" start="0" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="SOP code detected in receiver" start="0x0" />
+        <Enum name="B_0x1" description="SOP' code detected in receiver" start="0x1" />
+        <Enum name="B_0x2" description="SOP'' code detected in receiver" start="0x2" />
+        <Enum name="B_0x3" description="SOP'_Debug detected in receiver" start="0x3" />
+        <Enum name="B_0x4" description="SOP''_Debug detected in receiver" start="0x4" />
+        <Enum name="B_0x5" description="Cable Reset detected in receiver" start="0x5" />
+        <Enum name="B_0x6" description="SOP extension#1 detected in receiver" start="0x6" />
+        <Enum name="B_0x7" description="SOP extension#2 detected in receiver" start="0x7" />
+      </BitField>
+      <BitField name="RXSOP3OF4" description="The bit indicates the number of correct K-codes. For debug purposes only." start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="4 correct K-codes out of 4" start="0x0" />
+        <Enum name="B_0x1" description="3 correct K-codes out of 4" start="0x1" />
+      </BitField>
+      <BitField name="RXSOPKINVALID" description="The bitfield is for debug purposes only." start="4" size="3" access="ReadOnly">
+        <Enum name="B_0x0" description="No K-code corrupted" start="0x0" />
+        <Enum name="B_0x1" description="First K-code corrupted" start="0x1" />
+        <Enum name="B_0x2" description="Second K-code corrupted" start="0x2" />
+        <Enum name="B_0x3" description="Third K-code corrupted" start="0x3" />
+        <Enum name="B_0x4" description="Fourth K-code corrupted" start="0x4" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_RX_PAYSZR" description="UCPD Rx payload size register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXPAYSZ" description="Rx payload size received" start="0" size="10" access="ReadOnly">
+        <Enum name="B_0x2" description="2 bytes - the size of Control message from the protocol layer" start="0x2" />
+        <Enum name="B_0x6" description="6 bytes - the shortest Data message allowed from the protocol layer)" start="0x6" />
+        <Enum name="B_0x1E" description="30 bytes - the longest non-extended Data message allowed from the protocol layer" start="0x1E" />
+        <Enum name="B_0x106" description="262 bytes - the longest possible extended message" start="0x106" />
+        <Enum name="B_0x3FF" description="1024 bytes - the longest possible payload (for future expansion)" start="0x3FF" />
+      </BitField>
+    </Register>
+    <Register name="UCPD_RXDR" description="UCPD receive data register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="Data byte received" start="0" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="UCPD_RX_ORDEXTR1" description="UCPD Rx ordered set extension register 1" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXSOPX1" description="Ordered set 1 received" start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="UCPD_RX_ORDEXTR2" description="UCPD Rx ordered set extension register 2" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXSOPX2" description="Ordered set 2 received" start="0" size="20" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART1" description="Universal synchronous/asynchronous receiver transmitter" start="0x42001000">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART1_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x52001000">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART2" description="Universal synchronous/asynchronous receiver transmitter" start="0x40004400">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART2_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50004400">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART3" description="Universal synchronous/asynchronous receiver transmitter" start="0x40004800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART3_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50004800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART4" description="Universal synchronous/asynchronous receiver transmitter" start="0x40004C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART4_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50004C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART5" description="Universal synchronous/asynchronous receiver transmitter" start="0x40005000">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART5_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50005000">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART6" description="Universal synchronous/asynchronous receiver transmitter" start="0x42001400">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART6_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x52001400">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART7" description="Universal synchronous/asynchronous receiver transmitter" start="0x40007800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART7_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50007800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART8" description="Universal synchronous/asynchronous receiver transmitter" start="0x40007C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART8_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x50007C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART9" description="Universal synchronous/asynchronous receiver transmitter" start="0x42001800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART9_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x52001800">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART10" description="Universal synchronous/asynchronous receiver transmitter" start="0x42001C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART10_S" description="Universal synchronous/asynchronous receiver transmitter" start="0x52001C00">
+    <Register name="USART_CR1_FIFO_ENABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when RXFF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR1_FIFO_DISABLED" description="USART control register 1 [alternate]" start="+0x00" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UE" description="USART enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
+        <Enum name="B_0x1" description="USART enabled" start="0x1" />
+      </BitField>
+      <BitField name="UESM" description="USART enable in low-power mode " start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
+        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode." start="0x1" />
+      </BitField>
+      <BitField name="RE" description="Receiver enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
+      </BitField>
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
+        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
+      </BitField>
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXNEIE" description="Receive data register not empty" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TC=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXEIE" description="Transmit data register empty" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever PE=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="PS" description="Parity selection" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Even parity" start="0x0" />
+        <Enum name="B_0x1" description="Odd parity" start="0x1" />
+      </BitField>
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
+        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
+      </BitField>
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Idle line" start="0x0" />
+        <Enum name="B_0x1" description="Address mark" start="0x1" />
+      </BitField>
+      <BitField name="M0" description="Word length" start="12" size="1" access="Read/Write" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver in Active mode permanently" start="0x0" />
+        <Enum name="B_0x1" description="Receiver can switch between Mute mode and Active mode." start="0x1" />
+      </BitField>
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
+        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
+      </BitField>
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" access="Read/Write" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" access="Read/Write" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="M1" description="Word length" start="28" size="1" access="Read/Write" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
+        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_CR2" description="USART control register 2" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
+        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
+      </BitField>
+      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
+        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
+      </BitField>
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
+        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
+      </BitField>
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
+        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
+      </BitField>
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
+        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
+      </BitField>
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
+        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
+      </BitField>
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
+        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
+      </BitField>
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
+        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
+      </BitField>
+      <BitField name="STOP" description="stop bits" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
+        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
+        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
+        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
+      </BitField>
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
+        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART." start="0x1" />
+      </BitField>
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="RX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (Vless thansub&gt;DDless than/sub&gt; =1/idle, Gnd=0/mark)" start="0x0" />
+        <Enum name="B_0x1" description="TX pin signal values are inverted. ((Vless thansub&gt;DDless than/sub&gt; =0/mark, Gnd=1/idle)." start="0x1" />
+      </BitField>
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)" start="0x0" />
+        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted." start="0x1" />
+      </BitField>
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit." start="0x0" />
+        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit." start="0x1" />
+      </BitField>
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto baud rate detection is disabled." start="0x0" />
+        <Enum name="B_0x1" description="Auto baud rate detection is enabled." start="0x1" />
+      </BitField>
+      <BitField name="ABRMOD" description="Auto baud rate mode" start="21" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate." start="0x0" />
+        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -&gt; Frame = Start10xxxxxx)" start="0x1" />
+        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
+        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
+      </BitField>
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receiver timeout feature disabled." start="0x0" />
+        <Enum name="B_0x1" description="Receiver timeout feature enabled." start="0x1" />
+      </BitField>
+      <BitField name="ADD" description="Address of the USART node " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_CR3" description="USART control register 3" start="+0x08" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
+      </BitField>
+      <BitField name="IREN" description="IrDA mode enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
+        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
+      </BitField>
+      <BitField name="IRLP" description="IrDA low-power" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Normal mode" start="0x0" />
+        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
+      </BitField>
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Half-duplex mode is not selected" start="0x0" />
+        <Enum name="B_0x1" description="Half-duplex mode is selected" start="0x1" />
+      </BitField>
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
+        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
+      </BitField>
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Smartcard mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="Smartcard mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
+      </BitField>
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
+        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
+      </BitField>
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received." start="0x1" />
+      </BitField>
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
+        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted." start="0x1" />
+      </BitField>
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
+        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
+      </BitField>
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data." start="0x0" />
+        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
+      </BitField>
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode)" start="0x0" />
+        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
+      </BitField>
+      <BitField name="DEM" description="Driver enable mode " start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE function is disabled." start="0x0" />
+        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
+      </BitField>
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DE signal is active high." start="0x0" />
+        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
+      </BitField>
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in Transmission mode." start="0x0" />
+      </BitField>
+      <BitField name="WUS0" description="Wakeup from low-power mode interrupt flag selection" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUS1" description="Wakeup from low-power mode interrupt flag selection" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
+      </BitField>
+      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever WUF=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
+      </BitField>
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
+      </BitField>
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
+        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
+      </BitField>
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
+        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
+        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
+        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
+        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="USART_BRR" description="USART baud rate register" start="+0x0C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="USART baud rate" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="USART_GTPR" description="USART guard time and prescaler register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 1" start="0x1" />
+        <Enum name="B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE" description="divides the source clock by 2" start="0x2" />
+        <Enum name="B_0x3_SMARTCARD_MODE" description="divides the source clock by 6" start="0x3" />
+      </BitField>
+      <BitField name="GT" description="Guard time value" start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RTOR" description="USART receiver timeout register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" access="Read/Write" />
+      <BitField name="BLEN" description="Block Length " start="24" size="8" access="Read/Write" />
+    </Register>
+    <Register name="USART_RQR" description="USART request register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" access="WriteOnly" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" access="WriteOnly" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" access="WriteOnly" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" access="WriteOnly" />
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_ISR_FIFO_ENABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun error" start="0x0" />
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXFNE" description="RXFIFO not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXFNF" description="TXFIFO not full" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
+        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
+      </BitField>
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
+        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
+      </BitField>
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
+        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ISR_FIFO_DISABLED" description="USART interrupt and status register [alternate]" start="+0x1C" size="4" reset_value="0x000000C0" reset_mask="0xF00FFFFF">
+      <BitField name="PE" description="Parity error" start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No parity error" start="0x0" />
+        <Enum name="B_0x1" description="Parity error" start="0x1" />
+      </BitField>
+      <BitField name="FE" description="Framing error" start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
+        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
+      </BitField>
+      <BitField name="NE" description="Noise detection flag" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
+        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
+      </BitField>
+      <BitField name="ORE" description="Overrun error" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
+      </BitField>
+      <BitField name="IDLE" description="Idle line detected" start="4" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
+        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
+      </BitField>
+      <BitField name="RXNE" description="Read data register not empty" start="5" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data is not received" start="0x0" />
+        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
+      </BitField>
+      <BitField name="TC" description="Transmission complete" start="6" size="1" access="ReadOnly" />
+      <BitField name="TXE" description="Transmit data register empty" start="7" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Data register full" start="0x0" />
+        <Enum name="B_0x1" description="Data register full" start="0x1" />
+      </BitField>
+      <BitField name="LBDF" description="LIN break detection flag" start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
+        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
+      </BitField>
+      <BitField name="CTSIF" description="CTS interrupt flag" start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No change occurred on the CTS status line" start="0x0" />
+        <Enum name="B_0x1" description="A change occurred on the CTS status line" start="0x1" />
+      </BitField>
+      <BitField name="CTS" description="CTS flag" start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="CTS line set" start="0x0" />
+        <Enum name="B_0x1" description="CTS line reset" start="0x1" />
+      </BitField>
+      <BitField name="RTOF" description="Receiver timeout" start="11" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
+        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
+      </BitField>
+      <BitField name="EOBF" description="End of block flag" start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
+        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
+      </BitField>
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underrun error" start="0x0" />
+        <Enum name="B_0x1" description="underrun error" start="0x1" />
+      </BitField>
+      <BitField name="ABRE" description="Auto baud rate error" start="14" size="1" access="ReadOnly" />
+      <BitField name="ABRF" description="Auto baud rate flag" start="15" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy flag" start="16" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
+        <Enum name="B_0x1" description="Reception on going" start="0x1" />
+      </BitField>
+      <BitField name="CMF" description="Character match flag" start="17" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
+        <Enum name="B_0x1" description="Character match detected" start="0x1" />
+      </BitField>
+      <BitField name="SBKF" description="Send break flag" start="18" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No break character transmitted" start="0x0" />
+        <Enum name="B_0x1" description="Break character transmitted" start="0x1" />
+      </BitField>
+      <BitField name="RWU" description="Receiver wakeup from Mute mode" start="19" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Receiver in Active mode" start="0x0" />
+        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
+      </BitField>
+      <BitField name="WUF" description="Wakeup from low-power mode flag " start="20" size="1" access="ReadOnly" />
+      <BitField name="TEACK" description="Transmit enable acknowledge flag " start="21" size="1" access="ReadOnly" />
+      <BitField name="REACK" description="Receive enable acknowledge flag " start="22" size="1" access="ReadOnly" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
+        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="USART_ICR" description="USART interrupt flag clear register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="NECF" description="Noise detected clear flag" start="2" size="1" access="WriteOnly" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" access="WriteOnly" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" access="WriteOnly" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" access="WriteOnly" />
+      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag" start="7" size="1" access="WriteOnly" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" access="WriteOnly" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" access="WriteOnly" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" access="WriteOnly" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" access="WriteOnly" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" access="WriteOnly" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" access="WriteOnly" />
+      <BitField name="WUCF" description="Wakeup from low-power mode clear flag " start="20" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="USART_RDR" description="USART receive data register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" access="ReadOnly" />
+    </Register>
+    <Register name="USART_TDR" description="USART transmit data register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" access="Read/Write" />
+    </Register>
+    <Register name="USART_PRESC" description="USART prescaler register" start="+0x2C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="VENC" description="Video encoder" start="0x48005000">
+    <Register name="VENC_SWREG0" description="VENC ID register" start="+0x000" size="4" reset_value="0x6E654000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Interrupt register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG1" description="VENC interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Interrupt register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG2" description="VENC bus interface configuration register" start="+0x008" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Bus interface configuration register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG3" description="VENC device configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Device configuration register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG5" description="VENC base address for output stream data register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output stream data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG6" description="VENC base address for output control data register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output control data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG7" description="VENC base address for reference luma register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG8" description="VENC base address for reference chroma register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG9" description="VENC base address for reconstructed luma register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG10" description="VENC base address for reconstructed chroma register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG11" description="VENC base address for input picture luma register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG12" description="VENC base address for input picture cb register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture cb (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG13" description="VENC base address for input picture cr register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture cr (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG14" description="VENC encoder control register 0" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 0 (such as picture information or encoding mode) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG15" description="VENC encoder control register 1" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 1 (such as preprocessing control, crop, rotate, input format) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG16" description="VENC encoder control register 2" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for second reference luma (H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG17" description="VENC encoder control register 3" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for second reference chroma (H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG18" description="VENC encoder control register 4" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 4 (deblock filter mode, H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG19" description="VENC encoder control register 5" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 5 (input format, motion vector etc) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG20" description="VENC encoder control register 6" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of data JPEG (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG21" description="VENC encoder control register 7" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of H264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG22" description="VENC stream header remainder MSB bits register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream header remainder bits MSB (MSB aligned) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG23" description="VENC stream header remainder LSB bits register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream header remainder bits LSB (MSB aligned) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG24" description="VENC stream buffer limit/output stream size register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream buffer limit (64-bit addresses)/output stream size (bits) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG25" description="VENC encoder control register 8" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of MAD control and QP sum output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG26" description="VENC intra-slice bitmap register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra-slice bitmap for probability updates (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG27" description="VENC encoder control register 9" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of H264 QP (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG28" description="VENC encoder control register 10" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H264 checkpoint 1-2 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG29" description="VENC encoder control register 11" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint 3 -4 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG30" description="VENC encoder control register 12" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint 5 -6 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG31" description="VENC encoder control register 13" start="+0x07C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint 7 -8 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG32" description="VENC encoder control register 14" start="+0x080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint 8 -10 / Encoder control register 14 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG33" description="VENC encoder control register 15" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint word error 1-2 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG34" description="VENC encoder control register 16" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint word error 3-4 and the second reference frame control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG35" description="VENC H.264 checkpoint word error 5-6/encoder control register 17" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint word error 5-6 / Encoder control register 17 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG36" description="VENC H.264 checkpoint delta QP 1-8/encoder control register 18" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG37" description="VENC encoder control register 19, stream start offset" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 19 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG38" description="VENC macroblock count output register" start="+0x098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Macroblock count output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG39" description="VENC base address for next pic luminance register" start="+0x09C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for next pic luminance (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG40" description="VENC stabilization mode control register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization mode control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG41" description="VENC stabilization motion sum div8 output register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization motion sum div8 output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG42" description="VENC stabilization GMV output, matrix 1, up-left position output register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization GMV output, matrix 1 (up-left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG43" description="VENC stabilization GMV output, matrix 2, up position output register" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization GMV output, matrix 2 (up position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG44" description="VENC stabilization matrix 3, up-right position output register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 3 (up-right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG45" description="VENC stabilization matrix 4, left position output register" start="+0x0B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 4 (left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG46" description="VENC stabilization matrix 5, GMV position output register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 5 (GMV position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG47" description="VENC stabilization matrix 6, right position output register" start="+0x0BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 6 (right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG48" description="VENC stabilization matrix 7, down-left position output register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 7 (down-left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG49" description="VENC stabilization matrix 8, down position output register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 8 (down position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG50" description="VENC stabilization matrix 9, down-right position output register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 9 (down-right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG51" description="VENC base address for cabac context tables H264 register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for cabac context tables (H264) or probability tables (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG52" description="VENC base address for MV output writing register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for MV output writing (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG53" description="VENC RGB to YUV conversion coefficient A - B register" start="+0x0D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient A - B (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG54" description="VENC RGB to YUV conversion coefficient C - E register" start="+0x0D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient C - E (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG55" description="VENC RGB to YUV conversion coefficient F, RGB mask MSB bit position register" start="+0x0DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient F, RGB mask MSB bit position (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG56" description="VENC intra area register" start="+0x0E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG57" description="VENC CIR intra mb position register" start="+0x0E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="CIR intra mb position (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG58" description="VENC intra slice bitmap for slices 0..31/base address for 1st DCT partition register" start="+0x0E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra slice bitmap for slices 0..31 / Base address for 1st DCT partition (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG59" description="VENC intra slice bitmap for slices 32..63/base address for 2nd DCT partition register" start="+0x0EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra slice bitmap for slices 32..63 / Base address for 2nd DCT partition (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG60" description="VENC 1st ROI area register" start="+0x0F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="1st ROI area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG61" description="VENC 2nd ROI area register" start="+0x0F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="2nd ROI area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG62" description="VENC ROI area delta QP, MV register" start="+0x0F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="ROI area delta QP, MV (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG63" description="VENC synthesis configuration register encoder 0 register" start="+0x0FC" size="4" reset_value="0x1E622780" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Synthesis configuration register encoder 0 (read only) (all format mode)" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="VENC_SWREG64" description="VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 1 / intra 16x16 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG65" description="VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 2 / intra 16x16 mode 2-3 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG66" description="VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 3 / intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG67" description="VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 4 / intra 4x4 mode 2-3 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG68" description="VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 5 / intra 4x4 mode 4-5 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG69" description="VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 6 / intra 4x4 mode 6-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG70" description="VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 7 / intra 4x4 mode 8-9 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG71" description="VENC JPEG luma quantization 8/base address for segmentation map register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 8 / Base address for segmentation map (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG72" description="VENC JPEG luma quantization 9/segment1 parameter register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 9 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG73" description="VENC JPEG luma quantization 10/segment1 parameter register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 10 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG74" description="VENC JPEG luma quantization 11/segment1 parameter register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 11 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG75" description="VENC JPEG luma quantization 12/segment1 parameter register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 12 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG76" description="VENC JPEG luma quantization 13/segment1 parameter register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 13 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG77" description="VENC JPEG luma quantization 14/segment1 parameter register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 14 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG78" description="VENC JPEG luma quantization 15/segment1 parameter register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 15 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG79" description="VENC JPEG luma quantization 16/segment2 parameter register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 16 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG80" description="VENC JPEG chroma quantization 1/segment2 parameter register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 1 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG81" description="VENC JPEG chroma quantization 2/segment2 parameter register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 2 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG82" description="VENC JPEG chroma quantization 3/segment2 parameter register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 3 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG83" description="VENC JPEG chroma quantization 4/segment2 parameter register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 4 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG84" description="VENC JPEG chroma quantization 5/segment2 parameter register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 5 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG85" description="VENC JPEG chroma quantization 6/segment2 parameter register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 6 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG86" description="VENC JPEG chroma quantization 7/segment2 parameter register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 7 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG87" description="VENC JPEG chroma quantization 8/segment2 parameter register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 8 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG88" description="VENC JPEG chroma quantization 9/segment3 parameter register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 9 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG89" description="VENC JPEG chroma quantization 10/segment3 parameter register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 10 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG90" description="VENC JPEG chroma quantization 11/segment3 parameter register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 11 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG91" description="VENC JPEG chroma quantization 12/segment3 parameter register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 12 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG92" description="VENC JPEG chroma quantization 13/segment3 parameter register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 13 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG93" description="VENC JPEG chroma quantization 14/segment3 parameter register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 14 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG94" description="VENC JPEG chroma quantization 15/segment3 parameter register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 15 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG95" description="VENC JPEG chroma quantization 16/segment3 parameter register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 16 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG96" description="VENC DMV 4p/1p penalty values 0-3 register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 0-3 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG97" description="VENC DMV 4p/1p penalty values 4-7 register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 4-7 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG98" description="VENC DMV 4p/1p penalty values register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG99" description="VENC DMV 4p/1p penalty values register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG100" description="VENC DMV 4p/1p penalty values register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG101" description="VENC DMV 4p/1p penalty values register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG102" description="VENC DMV 4p/1p penalty values register" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG103" description="VENC DMV 4p/1p penalty values register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG104" description="VENC DMV 4p/1p penalty values register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG105" description="VENC DMV 4p/1p penalty values register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG106" description="VENC DMV 4p/1p penalty values register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG107" description="VENC DMV 4p/1p penalty values register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG108" description="VENC DMV 4p/1p penalty values register" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG109" description="VENC DMV 4p/1p penalty values register" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG110" description="VENC DMV 4p/1p penalty values register" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG111" description="VENC DMV 4p/1p penalty values register" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG112" description="VENC DMV 4p/1p penalty values register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG113" description="VENC DMV 4p/1p penalty values register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG114" description="VENC DMV 4p/1p penalty values register" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG115" description="VENC DMV 4p/1p penalty values register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG116" description="VENC DMV 4p/1p penalty values register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG117" description="VENC DMV 4p/1p penalty values register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG118" description="VENC DMV 4p/1p penalty values register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG119" description="VENC DMV 4p/1p penalty values register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG120" description="VENC DMV 4p/1p penalty values register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG121" description="VENC DMV 4p/1p penalty values register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG122" description="VENC DMV 4p/1p penalty values register" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG123" description="VENC DMV 4p/1p penalty values register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG124" description="VENC DMV 4p/1p penalty values register" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG125" description="VENC DMV 4p/1p penalty values register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG126" description="VENC DMV 4p/1p penalty values register" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG127" description="VENC DMV 4p/1p penalty values 124-127 register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 124-127 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG128" description="VENC DMV qpel penalty values 0-3 register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 0-3 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG129" description="VENC DMV qpel penalty values 4-7 register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 4-7 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG130" description="VENC DMV qpel penalty values register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG131" description="VENC DMV qpel penalty values register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG132" description="VENC DMV qpel penalty values register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG133" description="VENC DMV qpel penalty values register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG134" description="VENC DMV qpel penalty values register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG135" description="VENC DMV qpel penalty values register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG136" description="VENC DMV qpel penalty values register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG137" description="VENC DMV qpel penalty values register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG138" description="VENC DMV qpel penalty values register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG139" description="VENC DMV qpel penalty values register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG140" description="VENC DMV qpel penalty values register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG141" description="VENC DMV qpel penalty values register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG142" description="VENC DMV qpel penalty values register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG143" description="VENC DMV qpel penalty values register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG144" description="VENC DMV qpel penalty values register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG145" description="VENC DMV qpel penalty values register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG146" description="VENC DMV qpel penalty values register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG147" description="VENC DMV qpel penalty values register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG148" description="VENC DMV qpel penalty values register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG149" description="VENC DMV qpel penalty values register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG150" description="VENC DMV qpel penalty values register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG151" description="VENC DMV qpel penalty values register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG152" description="VENC DMV qpel penalty values register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG153" description="VENC DMV qpel penalty values register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG154" description="VENC DMV qpel penalty values register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG155" description="VENC DMV qpel penalty values register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG156" description="VENC DMV qpel penalty values register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG157" description="VENC DMV qpel penalty values register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG158" description="VENC DMV qpel penalty values register" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG159" description="VENC DMV qpel penalty values 124-127 register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 124-127 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG231" description="VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG232" description="VENC scaling control register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Scaling control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG233" description="VENC scaling control register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Scaling control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG236" description="VENC squared error output calculated for 13x13 pixels per macroblock register" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Squared error output calculated for 13x13 pixels per macroblock (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG237" description="VENC MAD 2 control and output register" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MAD 2 control and output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG238" description="VENC MAD 3 control and output register" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MAD 3 control and output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG256" description="VENC segment 1: intra 16x16 mode 0-2 penalty register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG257" description="VENC segment 1: intra 16x16 mode 3, intra 4x4 0-1 penalty register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 16x16 mode 3 and intra 4x4 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG258" description="VENC segment 1: intra 4x4 mode 2-4 penalty register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG259" description="VENC segment 1: intra 4x4 mode 5-7 penalty register" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG260" description="VENC segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 register" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG261" description="VENC segment 1: bit cost of inter type, intra 16x16 mode favor register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG262" description="VENC segment 1: inter MB mode favor, skip mode penalty, penalty value for 2nd reference frame register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: inter MB mode favor, skip mode penalty, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG263" description="VENC segment 1: penalty value register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG264" description="VENC segment 1: penalty value register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG265" description="VENC segment 1: deadzone rate multiplier for plane 0-1 register" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG266" description="VENC segment 1: deadzone rate multiplier for plane 2-3 register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG267" description="VENC segment 1: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG268" description="VENC segment 2: intra 16x16 mode 0-2 penalty register" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG269" description="VENC segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG270" description="VENC segment 2: intra 4x4 mode 2-4 penalty register" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG271" description="VENC segment 2: intra 4x4 mode 5-7 penalty register" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG272" description="VENC segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG273" description="VENC segment 2: bit cost of inter type, intra 16x16 mode favor register" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG274" description="VENC segment 2: inter MB mode favor, skip mode penalty, penalty value register" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: inter MB mode favor, skip mode penalty, panelty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG275" description="VENC segment 2: penalty value register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG276" description="VENC segment 2: penalty value register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG277" description="VENC segment 2: deadzone rate multiplier for plane 0-1 register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG278" description="VENC segment 2: deadzone rate multiplier for plane 2-3 register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG279" description="VENC segment 2: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG280" description="VENC segment 3: intra 16x16 mode 0-2 penalty register" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG281" description="VENC segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG282" description="VENC segment 3: intra 4x4 mode 2-4 penalty register" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG283" description="VENC segment 3: intra 4x4 mode 5-7 penalty register" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG284" description="VENC segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG285" description="VENC segment 3: bit cost of inter type, intra 16x16 mode favor register" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG286" description="VENC segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame register" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG287" description="VENC segment 3: penalty value register" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG288" description="VENC segment 3: penalty value register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG289" description="VENC segment 3: deadzone rate multiplier for plane 0-1 register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG290" description="VENC segment 3: deadzone rate multiplier for plane 2-3 register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG291" description="VENC segment 3: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG294" description="VENC Mb boost register" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Mb boost (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG295" description="VENC variance control, Pskop conding mode register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Variance control, Pskop conding mode (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG296" description="VENC synthesis configuration register encoder 1 read only register" start="+0x4A0" size="4" reset_value="0x06800000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Synthesis configuration register encoder 1 (read only) (all format mode)" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="VENC_SWREG297" description="VENC MBRC control register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MBRC control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG298" description="VENC segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG299" description="VENC segment 4: skip mode penalty, inter MB mode favor register" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG300" description="VENC segment 4: penalty value register" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG301" description="VENC segment 4: penalty value register" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG302" description="VENC segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG303" description="VENC segment 5: skip mode penalty, inter MB mode favor register" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG304" description="VENC segment 5: penalty value register" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG305" description="VENC segment 5: penalty value register" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG306" description="VENC segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG307" description="VENC segment 6: skip mode penalty, inter MB mode favor register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG308" description="VENC segment 6: penalty value register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG309" description="VENC segment 6: penalty value register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG310" description="VENC segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG311" description="VENC segment 7: skip mode penalty, inter MB mode favor register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG312" description="VENC segment 7: penalty value register" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG313" description="VENC segment 7: penalty value register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG314" description="VENC segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG315" description="VENC segment 8: skip mode penalty, inter MB mode favor register" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG316" description="VENC segment 8: penalty value register" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG317" description="VENC segment 8: penalty value register" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG318" description="VENC segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG319" description="VENC segment 9: skip mode penalty, inter MB mode favor register" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG320" description="VENC segment 9: penalty value register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG321" description="VENC segment 9: penalty value register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG322" description="VENC segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG323" description="VENC segment 10: skip mode penalty, inter MB mode favor register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG324" description="VENC segment 10: penalty value register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG325" description="VENC segment 10: penalty value register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG326" description="VENC segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG327" description="VENC segment 11: skip mode penalty, inter MB mode favor register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG328" description="VENC segment 11: penalty value register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG329" description="VENC segment 11: penalty value register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG330" description="VENC segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG331" description="VENC segment 12: skip mode penalty, inter MB mode favor register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG332" description="VENC segment 12: penalty value register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG333" description="VENC segment 12: penalty value register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG334" description="VENC segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG335" description="VENC segment 13: skip mode penalty, inter MB mode favor register" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG336" description="VENC segment 13: penalty value register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG337" description="VENC segment 13: penalty value register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG338" description="VENC segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG339" description="VENC segment 14: skip mode penalty, inter MB mode favor register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG340" description="VENC segment 14: penalty value register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG341" description="VENC segment 14: penalty value register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG342" description="VENC segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG343" description="VENC segment 15: skip mode penalty, inter MB mode favor register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG344" description="VENC segment 15: penalty value register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG345" description="VENC segment 15: penalty value register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG346" description="VENC segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG347" description="VENC segment 16: skip mode penalty, inter MB mode favor register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG348" description="VENC segment 16: penalty value register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG349" description="VENC segment 16: penalty value register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG350" description="VENC segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG351" description="VENC segment 17: skip mode penalty, inter MB mode favor register" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG352" description="VENC segment 17: penalty value register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG353" description="VENC segment 17: penalty value register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG354" description="VENC segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG355" description="VENC segment 18: skip mode penalty, inter MB mode favor register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG356" description="VENC segment 18: penalty value register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG357" description="VENC segment 18: penalty value register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG358" description="VENC segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG359" description="VENC segment 19: skip mode penalty, inter MB mode favor register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG360" description="VENC segment 19: penalty value register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG361" description="VENC segment 19: penalty value register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG362" description="VENC segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG363" description="VENC segment 20: skip mode penalty, inter MB mode favor register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG364" description="VENC segment 20: penalty value register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG365" description="VENC segment 20: penalty value register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG366" description="VENC segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG367" description="VENC segment 21: skip mode penalty, inter MB mode favor register" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG368" description="VENC segment 21: penalty value register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG369" description="VENC segment 21: penalty value register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG370" description="VENC segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG371" description="VENC segment 22: skip mode penalty, inter MB mode favor register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG372" description="VENC segment 22: penalty value register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG373" description="VENC segment 22: penalty value register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG374" description="VENC segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG375" description="VENC segment 23: skip mode penalty, inter MB mode favor register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG376" description="VENC segment 23: penalty value register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG377" description="VENC segment 23: penalty value register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG378" description="VENC segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG379" description="VENC segment 24: skip mode penalty, inter MB mode favor register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG380" description="VENC segment 24: penalty value register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG381" description="VENC segment 24: penalty value register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG382" description="VENC segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG383" description="VENC segment 25: skip mode penalty, inter MB mode favor register" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG384" description="VENC segment 25: penalty value register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG385" description="VENC segment 25: penalty value register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG386" description="VENC segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG387" description="VENC segment 26: skip mode penalty, inter MB mode favor register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG388" description="VENC segment 26: penalty value register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG389" description="VENC segment 26: penalty value register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG390" description="VENC segment 27: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG391" description="VENC segment 27: skip mode penalty, inter MB mode favor register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG392" description="VENC segment 27: penalty value register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG393" description="VENC segment 27: penalty value register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG394" description="VENC segment 28: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG395" description="VENC segment 28: skip mode penalty, inter MB mode favor register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG396" description="VENC segment 28: penalty value register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG397" description="VENC segment 28: penalty value register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG398" description="VENC segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG399" description="VENC segment 29: skip mode penalty, inter MB mode favor register" start="+0x63C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG400" description="VENC segment 29: penalty value register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG401" description="VENC segment 29: penalty value register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG402" description="VENC segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG403" description="VENC segment 30: skip mode penalty, inter MB mode favor register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG404" description="VENC segment 30: penalty value register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG405" description="VENC segment 30: penalty value register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG406" description="VENC segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG407" description="VENC segment 31: skip mode penalty, inter MB mode favor register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG408" description="VENC segment 31: penalty value register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG409" description="VENC segment 31: penalty value register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG410" description="VENC MBRC control, QP, offset, enable register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MBRC control (QP, offset, enable) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG411" description="VENC gain of MB QP delta. 8.8 format register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="gain of MB QPdelta. 8.8 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG412" description="VENC average of MB complexity register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG413" description="VENC reference compression control register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG414" description="VENC base address for reference luma register" start="+0x678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG415" description="VENC base address for reference chroma register" start="+0x67C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG416" description="VENC base address for reconstructed luma register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG417" description="VENC base address for reconstructed chroma register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG418" description="VENC base address for second reference luma register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG419" description="VENC base address for second reference chroma register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG420" description="VENC limit of chroma RFC buffer register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG421" description="VENC reorder control register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Reorder control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG422" description="VENC AXI read ID register" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG423" description="VENC base address MSB for reference luma compression table register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG424" description="VENC base address MSB for reference chroma compression table register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG425" description="VENC base address MSB for reconstructed luma compression table register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG426" description="VENC base address for reconstructed chroma compression table register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed chroma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG427" description="VENC base address MSB for second reference luma compression table register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address MSB for second reference luma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG428" description="VENC base address MSB for second reference chroma compression table register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address MSB for second reference chroma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG429" description="VENC high 32 bits of base address for output stream data register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output stream data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG430" description="VENC high 32 bits of base address for output control data register" start="+0x6B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output control data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG431" description="VENC high 32 bits of base address for reference luma register" start="+0x6BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG432" description="VENC high 32 bits of base address for reference chroma register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG433" description="VENC high 32 bits of base address for reconstructed luma register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reconstructed luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG434" description="VENC high 32 bits of base address for reconstructed chroma register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reconstructed chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG435" description="VENC high 32 bits of base address for input picture luma register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG436" description="VENC high 32 bits of base address for input picture cb register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture cb (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG437" description="VENC high 32 bits of base address for input picture cr register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture cr (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG438" description="VENC high 32 bits of base address for second reference luma register" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for second reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG439" description="VENC high 32 bits of base address for second reference chroma register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for second reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG440" description="VENC high 32 bits of H264 secondary ref pic base register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of H264 secondary ref pic base (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG441" description="VENC high 32 bits of H264 secondary ref pic base register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of H264 secondary ref pic base (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG442" description="VENC high 32 bits of base address for next pic luminance register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for next pic luminance (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG443" description="VENC high 32 bits of base address for cabac context tables H264 register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for cabac context tables (H264) or probability tables (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG444" description="VENC high 32 bits of base address for MV output writing register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for MV output writing (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG449" description="VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG497" description="VENC low-latency control register" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Low latency control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG498" description="VENC encoder line buffer offset register" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Low latency control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="VENC_S" description="Video encoder" start="0x58005000">
+    <Register name="VENC_SWREG0" description="VENC ID register" start="+0x000" size="4" reset_value="0x6E654000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Interrupt register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG1" description="VENC interrupt register" start="+0x004" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Interrupt register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG2" description="VENC bus interface configuration register" start="+0x008" size="4" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Bus interface configuration register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG3" description="VENC device configuration register" start="+0x00C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Device configuration register (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG5" description="VENC base address for output stream data register" start="+0x014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output stream data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG6" description="VENC base address for output control data register" start="+0x018" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output control data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG7" description="VENC base address for reference luma register" start="+0x01C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG8" description="VENC base address for reference chroma register" start="+0x020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG9" description="VENC base address for reconstructed luma register" start="+0x024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG10" description="VENC base address for reconstructed chroma register" start="+0x028" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG11" description="VENC base address for input picture luma register" start="+0x02C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG12" description="VENC base address for input picture cb register" start="+0x030" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture cb (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG13" description="VENC base address for input picture cr register" start="+0x034" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for input picture cr (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG14" description="VENC encoder control register 0" start="+0x038" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 0 (such as picture information or encoding mode) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG15" description="VENC encoder control register 1" start="+0x03C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 1 (such as preprocessing control, crop, rotate, input format) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG16" description="VENC encoder control register 2" start="+0x040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for second reference luma (H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG17" description="VENC encoder control register 3" start="+0x044" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for second reference chroma (H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG18" description="VENC encoder control register 4" start="+0x048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 4 (deblock filter mode, H264 control) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG19" description="VENC encoder control register 5" start="+0x04C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 5 (input format, motion vector etc) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG20" description="VENC encoder control register 6" start="+0x050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of data JPEG (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG21" description="VENC encoder control register 7" start="+0x054" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of H264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG22" description="VENC stream header remainder MSB bits register" start="+0x058" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream header remainder bits MSB (MSB aligned) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG23" description="VENC stream header remainder LSB bits register" start="+0x05C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream header remainder bits LSB (MSB aligned) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG24" description="VENC stream buffer limit/output stream size register" start="+0x060" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stream buffer limit (64-bit addresses)/output stream size (bits) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG25" description="VENC encoder control register 8" start="+0x064" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of MAD control and QP sum output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG26" description="VENC intra-slice bitmap register" start="+0x068" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra-slice bitmap for probability updates (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG27" description="VENC encoder control register 9" start="+0x06C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Control of H264 QP (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG28" description="VENC encoder control register 10" start="+0x070" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H264 checkpoint 1-2 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG29" description="VENC encoder control register 11" start="+0x074" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint 3 -4 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG30" description="VENC encoder control register 12" start="+0x078" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint 5 -6 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG31" description="VENC encoder control register 13" start="+0x07C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint 7 -8 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG32" description="VENC encoder control register 14" start="+0x080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint 8 -10 / Encoder control register 14 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG33" description="VENC encoder control register 15" start="+0x084" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint word error 1-2 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG34" description="VENC encoder control register 16" start="+0x088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 checkpoint word error 3-4 and the second reference frame control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG35" description="VENC H.264 checkpoint word error 5-6/encoder control register 17" start="+0x08C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint word error 5-6 / Encoder control register 17 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG36" description="VENC H.264 checkpoint delta QP 1-8/encoder control register 18" start="+0x090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG37" description="VENC encoder control register 19, stream start offset" start="+0x094" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Encoder control register 19 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG38" description="VENC macroblock count output register" start="+0x098" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Macroblock count output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG39" description="VENC base address for next pic luminance register" start="+0x09C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for next pic luminance (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG40" description="VENC stabilization mode control register" start="+0x0A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization mode control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG41" description="VENC stabilization motion sum div8 output register" start="+0x0A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization motion sum div8 output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG42" description="VENC stabilization GMV output, matrix 1, up-left position output register" start="+0x0A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization GMV output, matrix 1 (up-left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG43" description="VENC stabilization GMV output, matrix 2, up position output register" start="+0x0AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization GMV output, matrix 2 (up position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG44" description="VENC stabilization matrix 3, up-right position output register" start="+0x0B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 3 (up-right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG45" description="VENC stabilization matrix 4, left position output register" start="+0x0B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 4 (left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG46" description="VENC stabilization matrix 5, GMV position output register" start="+0x0B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 5 (GMV position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG47" description="VENC stabilization matrix 6, right position output register" start="+0x0BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 6 (right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG48" description="VENC stabilization matrix 7, down-left position output register" start="+0x0C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 7 (down-left position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG49" description="VENC stabilization matrix 8, down position output register" start="+0x0C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 8 (down position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG50" description="VENC stabilization matrix 9, down-right position output register" start="+0x0C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Stabilization matrix 9 (down-right position) output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG51" description="VENC base address for cabac context tables H264 register" start="+0x0CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for cabac context tables (H264) or probability tables (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG52" description="VENC base address for MV output writing register" start="+0x0D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for MV output writing (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG53" description="VENC RGB to YUV conversion coefficient A - B register" start="+0x0D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient A - B (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG54" description="VENC RGB to YUV conversion coefficient C - E register" start="+0x0D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient C - E (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG55" description="VENC RGB to YUV conversion coefficient F, RGB mask MSB bit position register" start="+0x0DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="RGB to YUV conversion coefficient F, RGB mask MSB bit position (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG56" description="VENC intra area register" start="+0x0E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG57" description="VENC CIR intra mb position register" start="+0x0E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="CIR intra mb position (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG58" description="VENC intra slice bitmap for slices 0..31/base address for 1st DCT partition register" start="+0x0E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra slice bitmap for slices 0..31 / Base address for 1st DCT partition (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG59" description="VENC intra slice bitmap for slices 32..63/base address for 2nd DCT partition register" start="+0x0EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="intra slice bitmap for slices 32..63 / Base address for 2nd DCT partition (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG60" description="VENC 1st ROI area register" start="+0x0F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="1st ROI area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG61" description="VENC 2nd ROI area register" start="+0x0F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="2nd ROI area (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG62" description="VENC ROI area delta QP, MV register" start="+0x0F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="ROI area delta QP, MV (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG63" description="VENC synthesis configuration register encoder 0 register" start="+0x0FC" size="4" reset_value="0x1E622780" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Synthesis configuration register encoder 0 (read only) (all format mode)" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="VENC_SWREG64" description="VENC JPEG luma quantization 1/intra 16x16 mode 0-1 penalty register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 1 / intra 16x16 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG65" description="VENC JPEG luma quantization 2/intra 16x16 mode 2-3 penalty register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 2 / intra 16x16 mode 2-3 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG66" description="VENC JPEG luma quantization 3/intra 4x4 mode 0-1 penalty register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 3 / intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG67" description="VENC JPEG luma quantization 4/intra 4x4 mode 2-3 penalty register" start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 4 / intra 4x4 mode 2-3 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG68" description="VENC JPEG luma quantization 5/intra 4x4 mode 4-5 penalty register" start="+0x110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 5 / intra 4x4 mode 4-5 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG69" description="VENC JPEG luma quantization 6/intra 4x4 mode 6-7 penalty register" start="+0x114" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 6 / intra 4x4 mode 6-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG70" description="VENC JPEG luma quantization 7/intra 4x4 mode 8-9 penalty register" start="+0x118" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 7 / intra 4x4 mode 8-9 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG71" description="VENC JPEG luma quantization 8/base address for segmentation map register" start="+0x11C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 8 / Base address for segmentation map (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG72" description="VENC JPEG luma quantization 9/segment1 parameter register" start="+0x120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 9 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG73" description="VENC JPEG luma quantization 10/segment1 parameter register" start="+0x124" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 10 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG74" description="VENC JPEG luma quantization 11/segment1 parameter register" start="+0x128" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 11 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG75" description="VENC JPEG luma quantization 12/segment1 parameter register" start="+0x12C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 12 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG76" description="VENC JPEG luma quantization 13/segment1 parameter register" start="+0x130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 13 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG77" description="VENC JPEG luma quantization 14/segment1 parameter register" start="+0x134" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 14 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG78" description="VENC JPEG luma quantization 15/segment1 parameter register" start="+0x138" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 15 / segment1 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG79" description="VENC JPEG luma quantization 16/segment2 parameter register" start="+0x13C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG luma quantization 16 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG80" description="VENC JPEG chroma quantization 1/segment2 parameter register" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 1 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG81" description="VENC JPEG chroma quantization 2/segment2 parameter register" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 2 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG82" description="VENC JPEG chroma quantization 3/segment2 parameter register" start="+0x148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 3 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG83" description="VENC JPEG chroma quantization 4/segment2 parameter register" start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 4 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG84" description="VENC JPEG chroma quantization 5/segment2 parameter register" start="+0x150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 5 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG85" description="VENC JPEG chroma quantization 6/segment2 parameter register" start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 6 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG86" description="VENC JPEG chroma quantization 7/segment2 parameter register" start="+0x158" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 7 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG87" description="VENC JPEG chroma quantization 8/segment2 parameter register" start="+0x15C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 8 / segment2 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG88" description="VENC JPEG chroma quantization 9/segment3 parameter register" start="+0x160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 9 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG89" description="VENC JPEG chroma quantization 10/segment3 parameter register" start="+0x164" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 10 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG90" description="VENC JPEG chroma quantization 11/segment3 parameter register" start="+0x168" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 11 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG91" description="VENC JPEG chroma quantization 12/segment3 parameter register" start="+0x16C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 12 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG92" description="VENC JPEG chroma quantization 13/segment3 parameter register" start="+0x170" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 13 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG93" description="VENC JPEG chroma quantization 14/segment3 parameter register" start="+0x174" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 14 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG94" description="VENC JPEG chroma quantization 15/segment3 parameter register" start="+0x178" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 15 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG95" description="VENC JPEG chroma quantization 16/segment3 parameter register" start="+0x17C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="JPEG chroma quantization 16 / segment3 parameter (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG96" description="VENC DMV 4p/1p penalty values 0-3 register" start="+0x180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 0-3 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG97" description="VENC DMV 4p/1p penalty values 4-7 register" start="+0x184" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 4-7 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG98" description="VENC DMV 4p/1p penalty values register" start="+0x188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG99" description="VENC DMV 4p/1p penalty values register" start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG100" description="VENC DMV 4p/1p penalty values register" start="+0x190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG101" description="VENC DMV 4p/1p penalty values register" start="+0x194" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG102" description="VENC DMV 4p/1p penalty values register" start="+0x198" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG103" description="VENC DMV 4p/1p penalty values register" start="+0x19C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG104" description="VENC DMV 4p/1p penalty values register" start="+0x1A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG105" description="VENC DMV 4p/1p penalty values register" start="+0x1A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG106" description="VENC DMV 4p/1p penalty values register" start="+0x1A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG107" description="VENC DMV 4p/1p penalty values register" start="+0x1AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG108" description="VENC DMV 4p/1p penalty values register" start="+0x1B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG109" description="VENC DMV 4p/1p penalty values register" start="+0x1B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG110" description="VENC DMV 4p/1p penalty values register" start="+0x1B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG111" description="VENC DMV 4p/1p penalty values register" start="+0x1BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG112" description="VENC DMV 4p/1p penalty values register" start="+0x1C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG113" description="VENC DMV 4p/1p penalty values register" start="+0x1C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG114" description="VENC DMV 4p/1p penalty values register" start="+0x1C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG115" description="VENC DMV 4p/1p penalty values register" start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG116" description="VENC DMV 4p/1p penalty values register" start="+0x1D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG117" description="VENC DMV 4p/1p penalty values register" start="+0x1D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG118" description="VENC DMV 4p/1p penalty values register" start="+0x1D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG119" description="VENC DMV 4p/1p penalty values register" start="+0x1DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG120" description="VENC DMV 4p/1p penalty values register" start="+0x1E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG121" description="VENC DMV 4p/1p penalty values register" start="+0x1E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG122" description="VENC DMV 4p/1p penalty values register" start="+0x1E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG123" description="VENC DMV 4p/1p penalty values register" start="+0x1EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG124" description="VENC DMV 4p/1p penalty values register" start="+0x1F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG125" description="VENC DMV 4p/1p penalty values register" start="+0x1F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG126" description="VENC DMV 4p/1p penalty values register" start="+0x1F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG127" description="VENC DMV 4p/1p penalty values 124-127 register" start="+0x1FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV 4p/1p penalty values 124-127 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG128" description="VENC DMV qpel penalty values 0-3 register" start="+0x200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 0-3 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG129" description="VENC DMV qpel penalty values 4-7 register" start="+0x204" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 4-7 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG130" description="VENC DMV qpel penalty values register" start="+0x208" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG131" description="VENC DMV qpel penalty values register" start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG132" description="VENC DMV qpel penalty values register" start="+0x210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG133" description="VENC DMV qpel penalty values register" start="+0x214" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG134" description="VENC DMV qpel penalty values register" start="+0x218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG135" description="VENC DMV qpel penalty values register" start="+0x21C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG136" description="VENC DMV qpel penalty values register" start="+0x220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG137" description="VENC DMV qpel penalty values register" start="+0x224" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG138" description="VENC DMV qpel penalty values register" start="+0x228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG139" description="VENC DMV qpel penalty values register" start="+0x22C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG140" description="VENC DMV qpel penalty values register" start="+0x230" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG141" description="VENC DMV qpel penalty values register" start="+0x234" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG142" description="VENC DMV qpel penalty values register" start="+0x238" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG143" description="VENC DMV qpel penalty values register" start="+0x23C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG144" description="VENC DMV qpel penalty values register" start="+0x240" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG145" description="VENC DMV qpel penalty values register" start="+0x244" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG146" description="VENC DMV qpel penalty values register" start="+0x248" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG147" description="VENC DMV qpel penalty values register" start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG148" description="VENC DMV qpel penalty values register" start="+0x250" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG149" description="VENC DMV qpel penalty values register" start="+0x254" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG150" description="VENC DMV qpel penalty values register" start="+0x258" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG151" description="VENC DMV qpel penalty values register" start="+0x25C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG152" description="VENC DMV qpel penalty values register" start="+0x260" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG153" description="VENC DMV qpel penalty values register" start="+0x264" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG154" description="VENC DMV qpel penalty values register" start="+0x268" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG155" description="VENC DMV qpel penalty values register" start="+0x26C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG156" description="VENC DMV qpel penalty values register" start="+0x270" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG157" description="VENC DMV qpel penalty values register" start="+0x274" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG158" description="VENC DMV qpel penalty values register" start="+0x278" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG159" description="VENC DMV qpel penalty values 124-127 register" start="+0x27C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="DMV qpel penalty values 124-127 (all format mode)" start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="VENC_SWREG231" description="VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register" start="+0x39C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG232" description="VENC scaling control register" start="+0x3A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Scaling control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG233" description="VENC scaling control register" start="+0x3A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Scaling control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG236" description="VENC squared error output calculated for 13x13 pixels per macroblock register" start="+0x3B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Squared error output calculated for 13x13 pixels per macroblock (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG237" description="VENC MAD 2 control and output register" start="+0x3B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MAD 2 control and output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG238" description="VENC MAD 3 control and output register" start="+0x3B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MAD 3 control and output (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG256" description="VENC segment 1: intra 16x16 mode 0-2 penalty register" start="+0x400" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG257" description="VENC segment 1: intra 16x16 mode 3, intra 4x4 0-1 penalty register" start="+0x404" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 16x16 mode 3 and intra 4x4 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG258" description="VENC segment 1: intra 4x4 mode 2-4 penalty register" start="+0x408" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG259" description="VENC segment 1: intra 4x4 mode 5-7 penalty register" start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG260" description="VENC segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 register" start="+0x410" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: intra 4x4 mode 8-9 penalty, previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG261" description="VENC segment 1: bit cost of inter type, intra 16x16 mode favor register" start="+0x414" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG262" description="VENC segment 1: inter MB mode favor, skip mode penalty, penalty value for 2nd reference frame register" start="+0x418" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: inter MB mode favor, skip mode penalty, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG263" description="VENC segment 1: penalty value register" start="+0x41C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG264" description="VENC segment 1: penalty value register" start="+0x420" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG265" description="VENC segment 1: deadzone rate multiplier for plane 0-1 register" start="+0x424" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG266" description="VENC segment 1: deadzone rate multiplier for plane 2-3 register" start="+0x428" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG267" description="VENC segment 1: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x42C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 1: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG268" description="VENC segment 2: intra 16x16 mode 0-2 penalty register" start="+0x430" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG269" description="VENC segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register" start="+0x434" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG270" description="VENC segment 2: intra 4x4 mode 2-4 penalty register" start="+0x438" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG271" description="VENC segment 2: intra 4x4 mode 5-7 penalty register" start="+0x43C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG272" description="VENC segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register" start="+0x440" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG273" description="VENC segment 2: bit cost of inter type, intra 16x16 mode favor register" start="+0x444" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG274" description="VENC segment 2: inter MB mode favor, skip mode penalty, penalty value register" start="+0x448" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: inter MB mode favor, skip mode penalty, panelty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG275" description="VENC segment 2: penalty value register" start="+0x44C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG276" description="VENC segment 2: penalty value register" start="+0x450" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG277" description="VENC segment 2: deadzone rate multiplier for plane 0-1 register" start="+0x454" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG278" description="VENC segment 2: deadzone rate multiplier for plane 2-3 register" start="+0x458" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG279" description="VENC segment 2: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x45C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 2: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG280" description="VENC segment 3: intra 16x16 mode 0-2 penalty register" start="+0x460" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 16x16 mode 0-2 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG281" description="VENC segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty register" start="+0x464" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG282" description="VENC segment 3: intra 4x4 mode 2-4 penalty register" start="+0x468" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 2-4 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG283" description="VENC segment 3: intra 4x4 mode 5-7 penalty register" start="+0x46C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 5-7 penalty (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG284" description="VENC segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 register" start="+0x470" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: intra 4x4 mode 8-9 penalty, intra 4x4 previous mode favor for H.264 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG285" description="VENC segment 3: bit cost of inter type, intra 16x16 mode favor register" start="+0x474" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Bit cost of inter type, intra 16x16 mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG286" description="VENC segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame register" start="+0x478" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: inter MB mode favor in intra/inter selection, inter MB mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG287" description="VENC segment 3: penalty value register" start="+0x47C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG288" description="VENC segment 3: penalty value register" start="+0x480" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG289" description="VENC segment 3: deadzone rate multiplier for plane 0-1 register" start="+0x484" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate multiplier for plane 0-1 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG290" description="VENC segment 3: deadzone rate multiplier for plane 2-3 register" start="+0x488" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate multiplier for plane 2-3 (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG291" description="VENC segment 3: deadzone rate for macroblock skip token 0-1, dmv penalty coefficient register" start="+0x48C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 3: Deadzone rate for macroblock skip token 0-1, dmv penalty coefficient (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG294" description="VENC Mb boost register" start="+0x498" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Mb boost (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG295" description="VENC variance control, Pskop conding mode register" start="+0x49C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Variance control, Pskop conding mode (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG296" description="VENC synthesis configuration register encoder 1 read only register" start="+0x4A0" size="4" reset_value="0x06800000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Synthesis configuration register encoder 1 (read only) (all format mode)" start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="VENC_SWREG297" description="VENC MBRC control register" start="+0x4A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MBRC control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG298" description="VENC segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG299" description="VENC segment 4: skip mode penalty, inter MB mode favor register" start="+0x4AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG300" description="VENC segment 4: penalty value register" start="+0x4B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG301" description="VENC segment 4: penalty value register" start="+0x4B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 4: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG302" description="VENC segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG303" description="VENC segment 5: skip mode penalty, inter MB mode favor register" start="+0x4BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG304" description="VENC segment 5: penalty value register" start="+0x4C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG305" description="VENC segment 5: penalty value register" start="+0x4C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 5: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG306" description="VENC segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG307" description="VENC segment 6: skip mode penalty, inter MB mode favor register" start="+0x4CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG308" description="VENC segment 6: penalty value register" start="+0x4D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG309" description="VENC segment 6: penalty value register" start="+0x4D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 6: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG310" description="VENC segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG311" description="VENC segment 7: skip mode penalty, inter MB mode favor register" start="+0x4DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG312" description="VENC segment 7: penalty value register" start="+0x4E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG313" description="VENC segment 7: penalty value register" start="+0x4E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 7: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG314" description="VENC segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG315" description="VENC segment 8: skip mode penalty, inter MB mode favor register" start="+0x4EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG316" description="VENC segment 8: penalty value register" start="+0x4F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG317" description="VENC segment 8: penalty value register" start="+0x4F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 8: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG318" description="VENC segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x4F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG319" description="VENC segment 9: skip mode penalty, inter MB mode favor register" start="+0x4FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG320" description="VENC segment 9: penalty value register" start="+0x500" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG321" description="VENC segment 9: penalty value register" start="+0x504" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 9: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG322" description="VENC segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x508" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG323" description="VENC segment 10: skip mode penalty, inter MB mode favor register" start="+0x50C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG324" description="VENC segment 10: penalty value register" start="+0x510" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG325" description="VENC segment 10: penalty value register" start="+0x514" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 10: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG326" description="VENC segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x518" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG327" description="VENC segment 11: skip mode penalty, inter MB mode favor register" start="+0x51C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG328" description="VENC segment 11: penalty value register" start="+0x520" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG329" description="VENC segment 11: penalty value register" start="+0x524" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 11: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG330" description="VENC segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x528" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG331" description="VENC segment 12: skip mode penalty, inter MB mode favor register" start="+0x52C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG332" description="VENC segment 12: penalty value register" start="+0x530" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG333" description="VENC segment 12: penalty value register" start="+0x534" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 12: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG334" description="VENC segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x538" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG335" description="VENC segment 13: skip mode penalty, inter MB mode favor register" start="+0x53C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG336" description="VENC segment 13: penalty value register" start="+0x540" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG337" description="VENC segment 13: penalty value register" start="+0x544" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 13: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG338" description="VENC segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x548" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG339" description="VENC segment 14: skip mode penalty, inter MB mode favor register" start="+0x54C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG340" description="VENC segment 14: penalty value register" start="+0x550" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG341" description="VENC segment 14: penalty value register" start="+0x554" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 14: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG342" description="VENC segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x558" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG343" description="VENC segment 15: skip mode penalty, inter MB mode favor register" start="+0x55C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG344" description="VENC segment 15: penalty value register" start="+0x560" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG345" description="VENC segment 15: penalty value register" start="+0x564" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 15: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG346" description="VENC segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x568" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG347" description="VENC segment 16: skip mode penalty, inter MB mode favor register" start="+0x56C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG348" description="VENC segment 16: penalty value register" start="+0x570" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG349" description="VENC segment 16: penalty value register" start="+0x574" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 16: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG350" description="VENC segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x578" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG351" description="VENC segment 17: skip mode penalty, inter MB mode favor register" start="+0x57C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG352" description="VENC segment 17: penalty value register" start="+0x580" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG353" description="VENC segment 17: penalty value register" start="+0x584" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 17: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG354" description="VENC segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x588" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG355" description="VENC segment 18: skip mode penalty, inter MB mode favor register" start="+0x58C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG356" description="VENC segment 18: penalty value register" start="+0x590" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG357" description="VENC segment 18: penalty value register" start="+0x594" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 18: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG358" description="VENC segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x598" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG359" description="VENC segment 19: skip mode penalty, inter MB mode favor register" start="+0x59C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG360" description="VENC segment 19: penalty value register" start="+0x5A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG361" description="VENC segment 19: penalty value register" start="+0x5A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 19: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG362" description="VENC segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG363" description="VENC segment 20: skip mode penalty, inter MB mode favor register" start="+0x5AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG364" description="VENC segment 20: penalty value register" start="+0x5B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG365" description="VENC segment 20: penalty value register" start="+0x5B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 20: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG366" description="VENC segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG367" description="VENC segment 21: skip mode penalty, inter MB mode favor register" start="+0x5BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG368" description="VENC segment 21: penalty value register" start="+0x5C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG369" description="VENC segment 21: penalty value register" start="+0x5C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 21: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG370" description="VENC segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG371" description="VENC segment 22: skip mode penalty, inter MB mode favor register" start="+0x5CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG372" description="VENC segment 22: penalty value register" start="+0x5D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG373" description="VENC segment 22: penalty value register" start="+0x5D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 22: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG374" description="VENC segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG375" description="VENC segment 23: skip mode penalty, inter MB mode favor register" start="+0x5DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG376" description="VENC segment 23: penalty value register" start="+0x5E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG377" description="VENC segment 23: penalty value register" start="+0x5E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 23: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG378" description="VENC segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG379" description="VENC segment 24: skip mode penalty, inter MB mode favor register" start="+0x5EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG380" description="VENC segment 24: penalty value register" start="+0x5F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG381" description="VENC segment 24: penalty value register" start="+0x5F4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 24: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG382" description="VENC segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x5F8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG383" description="VENC segment 25: skip mode penalty, inter MB mode favor register" start="+0x5FC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG384" description="VENC segment 25: penalty value register" start="+0x600" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG385" description="VENC segment 25: penalty value register" start="+0x604" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 25: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG386" description="VENC segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x608" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG387" description="VENC segment 26: skip mode penalty, inter MB mode favor register" start="+0x60C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG388" description="VENC segment 26: penalty value register" start="+0x610" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG389" description="VENC segment 26: penalty value register" start="+0x614" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 26: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG390" description="VENC segment 27: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register" start="+0x618" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG391" description="VENC segment 27: skip mode penalty, inter MB mode favor register" start="+0x61C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG392" description="VENC segment 27: penalty value register" start="+0x620" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG393" description="VENC segment 27: penalty value register" start="+0x624" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 27: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG394" description="VENC segment 28: intra 4x4 previous mode favor, intra 16x16mode favor, penalty value for second reference frame register" start="+0x628" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG395" description="VENC segment 28: skip mode penalty, inter MB mode favor register" start="+0x62C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG396" description="VENC segment 28: penalty value register" start="+0x630" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG397" description="VENC segment 28: penalty value register" start="+0x634" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 28: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG398" description="VENC segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x638" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG399" description="VENC segment 29: skip mode penalty, inter MB mode favor register" start="+0x63C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG400" description="VENC segment 29: penalty value register" start="+0x640" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG401" description="VENC segment 29: penalty value register" start="+0x644" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 29: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG402" description="VENC segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x648" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG403" description="VENC segment 30: skip mode penalty, inter MB mode favor register" start="+0x64C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG404" description="VENC segment 30: penalty value register" start="+0x650" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG405" description="VENC segment 30: penalty value register" start="+0x654" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 30: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG406" description="VENC segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame register" start="+0x658" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: intra 4x4 previous mode favor, intra 16x16 mode favor, penalty value for second reference frame (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG407" description="VENC segment 31: skip mode penalty, inter MB mode favor register" start="+0x65C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: skip mode penalty, inter MB mode favor (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG408" description="VENC segment 31: penalty value register" start="+0x660" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG409" description="VENC segment 31: penalty value register" start="+0x664" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="segment 31: penalty value (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG410" description="VENC MBRC control, QP, offset, enable register" start="+0x668" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="MBRC control (QP, offset, enable) (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG411" description="VENC gain of MB QP delta. 8.8 format register" start="+0x66C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="gain of MB QPdelta. 8.8 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG412" description="VENC average of MB complexity register" start="+0x670" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG413" description="VENC reference compression control register" start="+0x674" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG414" description="VENC base address for reference luma register" start="+0x678" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG415" description="VENC base address for reference chroma register" start="+0x67C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG416" description="VENC base address for reconstructed luma register" start="+0x680" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG417" description="VENC base address for reconstructed chroma register" start="+0x684" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG418" description="VENC base address for second reference luma register" start="+0x688" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG419" description="VENC base address for second reference chroma register" start="+0x68C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG420" description="VENC limit of chroma RFC buffer register" start="+0x690" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="average of MB complexity (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG421" description="VENC reorder control register" start="+0x694" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Reorder control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG422" description="VENC AXI read ID register" start="+0x698" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG423" description="VENC base address MSB for reference luma compression table register" start="+0x69C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG424" description="VENC base address MSB for reference chroma compression table register" start="+0x6A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG425" description="VENC base address MSB for reconstructed luma compression table register" start="+0x6A4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="AXI Read ID (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG426" description="VENC base address for reconstructed chroma compression table register" start="+0x6A8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address for reconstructed chroma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG427" description="VENC base address MSB for second reference luma compression table register" start="+0x6AC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address MSB for second reference luma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG428" description="VENC base address MSB for second reference chroma compression table register" start="+0x6B0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Base address MSB for second reference chroma compression table (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG429" description="VENC high 32 bits of base address for output stream data register" start="+0x6B4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output stream data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG430" description="VENC high 32 bits of base address for output control data register" start="+0x6B8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output control data (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG431" description="VENC high 32 bits of base address for reference luma register" start="+0x6BC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG432" description="VENC high 32 bits of base address for reference chroma register" start="+0x6C0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG433" description="VENC high 32 bits of base address for reconstructed luma register" start="+0x6C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reconstructed luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG434" description="VENC high 32 bits of base address for reconstructed chroma register" start="+0x6C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for reconstructed chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG435" description="VENC high 32 bits of base address for input picture luma register" start="+0x6CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG436" description="VENC high 32 bits of base address for input picture cb register" start="+0x6D0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture cb (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG437" description="VENC high 32 bits of base address for input picture cr register" start="+0x6D4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for input picture cr (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG438" description="VENC high 32 bits of base address for second reference luma register" start="+0x6D8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for second reference luma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG439" description="VENC high 32 bits of base address for second reference chroma register" start="+0x6DC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for second reference chroma (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG440" description="VENC high 32 bits of H264 secondary ref pic base register" start="+0x6E0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of H264 secondary ref pic base (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG441" description="VENC high 32 bits of H264 secondary ref pic base register" start="+0x6E4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of H264 secondary ref pic base (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG442" description="VENC high 32 bits of base address for next pic luminance register" start="+0x6E8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for next pic luminance (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG443" description="VENC high 32 bits of base address for cabac context tables H264 register" start="+0x6EC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for cabac context tables (H264) or probability tables (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG444" description="VENC high 32 bits of base address for MV output writing register" start="+0x6F0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for MV output writing (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG449" description="VENC high 32 bits of base address for output of down-scaled encoder image in YUYV 4:2:2 format register" start="+0x704" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="high 32 bits of Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG497" description="VENC low-latency control register" start="+0x7C4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Low latency control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="VENC_SWREG498" description="VENC encoder line buffer offset register" start="+0x7C8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWREG_FIELD" description="Low latency control (all format mode)" start="0" size="32" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="VREFBUF" description="Voltage reference buffer" start="0x46003C00">
+    <Register name="VREFBUF_CSR" description="VREFBUF control and status register" start="+0x00" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="ENVR" description="Voltage reference buffer mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal voltage reference mode disable (external voltage reference mode)." start="0x0" />
+        <Enum name="B_0x1" description="Internal voltage reference mode (reference buffer enable or hold mode) enable." start="0x1" />
+      </BitField>
+      <BitField name="HIZ" description="High impedance mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;REF+less than/sub&gt; pin is internally connected to the voltage reference buffer output." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;REF+less than/sub&gt; pin is high impedance." start="0x1" />
+      </BitField>
+      <BitField name="VRR" description="Voltage reference buffer ready" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="the voltage reference buffer output is not ready." start="0x0" />
+        <Enum name="B_0x1" description="the voltage reference buffer output reached the requested level." start="0x1" />
+      </BitField>
+      <BitField name="VRS" description="Voltage reference scale" start="4" size="3" access="Read/Write" />
+    </Register>
+    <Register name="VREFBUF_CCR" description="VREFBUF calibration control register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFF00">
+      <BitField name="TRIM" description="Trimming code" start="0" size="6" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="VREFBUF_S" description="Voltage reference buffer" start="0x56003C00">
+    <Register name="VREFBUF_CSR" description="VREFBUF control and status register" start="+0x00" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="ENVR" description="Voltage reference buffer mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Internal voltage reference mode disable (external voltage reference mode)." start="0x0" />
+        <Enum name="B_0x1" description="Internal voltage reference mode (reference buffer enable or hold mode) enable." start="0x1" />
+      </BitField>
+      <BitField name="HIZ" description="High impedance mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Vless thansub&gt;REF+less than/sub&gt; pin is internally connected to the voltage reference buffer output." start="0x0" />
+        <Enum name="B_0x1" description="Vless thansub&gt;REF+less than/sub&gt; pin is high impedance." start="0x1" />
+      </BitField>
+      <BitField name="VRR" description="Voltage reference buffer ready" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="the voltage reference buffer output is not ready." start="0x0" />
+        <Enum name="B_0x1" description="the voltage reference buffer output reached the requested level." start="0x1" />
+      </BitField>
+      <BitField name="VRS" description="Voltage reference scale" start="4" size="3" access="Read/Write" />
+    </Register>
+    <Register name="VREFBUF_CCR" description="VREFBUF calibration control register" start="+0x04" size="4" reset_value="0x00000000" reset_mask="0xFFFFFF00">
+      <BitField name="TRIM" description="Trimming code" start="0" size="6" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDG" description="System window watchdog" start="0x40002C00">
+    <Register name="WWDG_CR" description="WWDG control register" start="+0x000" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="T" description="7-bit counter (MSB to LSB)" start="0" size="7" access="Read/Write" />
+      <BitField name="WDGA" description="Activation bit " start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Watchdog disabled" start="0x0" />
+        <Enum name="B_0x1" description="Watchdog enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="WWDG_CFR" description="WWDG configuration register" start="+0x004" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="W" description="7-bit window value" start="0" size="7" access="Read/Write" />
+      <BitField name="EWI" description="Early wakeup interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="WDGTB" description="Timer base" start="11" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CK counter clock (PCLK div 4096) div 1" start="0x0" />
+        <Enum name="B_0x1" description="CK counter clock (PCLK div 4096) div 2" start="0x1" />
+        <Enum name="B_0x2" description="CK counter clock (PCLK div 4096) div 4" start="0x2" />
+        <Enum name="B_0x3" description="CK counter clock (PCLK div 4096) div 8" start="0x3" />
+        <Enum name="B_0x4" description="CK counter clock (PCLK div 4096) div 16" start="0x4" />
+        <Enum name="B_0x5" description="CK counter clock (PCLK div 4096) div 32" start="0x5" />
+        <Enum name="B_0x6" description="CK counter clock (PCLK div 4096) div 64" start="0x6" />
+        <Enum name="B_0x7" description="CK counter clock (PCLK div 4096) div 128" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="WWDG_SR" description="WWDG status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIF" description="Early wakeup interrupt flag" start="0" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDG_S" description="System window watchdog" start="0x50002C00">
+    <Register name="WWDG_CR" description="WWDG control register" start="+0x000" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="T" description="7-bit counter (MSB to LSB)" start="0" size="7" access="Read/Write" />
+      <BitField name="WDGA" description="Activation bit " start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Watchdog disabled" start="0x0" />
+        <Enum name="B_0x1" description="Watchdog enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="WWDG_CFR" description="WWDG configuration register" start="+0x004" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="W" description="7-bit window value" start="0" size="7" access="Read/Write" />
+      <BitField name="EWI" description="Early wakeup interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="WDGTB" description="Timer base" start="11" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="CK counter clock (PCLK div 4096) div 1" start="0x0" />
+        <Enum name="B_0x1" description="CK counter clock (PCLK div 4096) div 2" start="0x1" />
+        <Enum name="B_0x2" description="CK counter clock (PCLK div 4096) div 4" start="0x2" />
+        <Enum name="B_0x3" description="CK counter clock (PCLK div 4096) div 8" start="0x3" />
+        <Enum name="B_0x4" description="CK counter clock (PCLK div 4096) div 16" start="0x4" />
+        <Enum name="B_0x5" description="CK counter clock (PCLK div 4096) div 32" start="0x5" />
+        <Enum name="B_0x6" description="CK counter clock (PCLK div 4096) div 64" start="0x6" />
+        <Enum name="B_0x7" description="CK counter clock (PCLK div 4096) div 128" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="WWDG_SR" description="WWDG status register" start="+0x008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIF" description="Early wakeup interrupt flag" start="0" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPIM" description="XSPI I/O manager" start="0x4802B400">
+    <Register name="XSPIM_CR" description="XSPIM control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MUXEN" description="Multiplexed mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No multiplexing, hence no arbitration" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 and XSPI2 are multiplexed over the same bus." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="XSPI multiplexing mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="if MUXEN = 0 direct mode, if MUXEN = 1 arbitration mode to output Port 1" start="0x0" />
+        <Enum name="B_0x1" description="if MUXEN = 0 swapped mode, if MUXEN = 1 arbitration mode to output Port 2" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_EN" description="Chip select selector override enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are ignored, the chip select signals from OCTOSPIs or XSPIs are transmitted unconditionally" start="0x0" />
+        <Enum name="B_0x1" description="CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are taken into account" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_O1" description="Chip select selector override setting for XSPI1" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 can only use NCS1 (accesses using NCS2 are ignored)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 can only use NCS2 (accesses using NCS1 are ignored)" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_O2" description="Chip select selector override setting for XSPI2" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 can only use NCS1 (accesses using NCS2 are ignored)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 can only use NCS2 (accesses using NCS1 are ignored)" start="0x1" />
+      </BitField>
+      <BitField name="REQ2ACK_TIME" description="REQ to ACK time" start="16" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPIM_S" description="XSPI I/O manager" start="0x5802B400">
+    <Register name="XSPIM_CR" description="XSPIM control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MUXEN" description="Multiplexed mode enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No multiplexing, hence no arbitration" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 and XSPI2 are multiplexed over the same bus." start="0x1" />
+      </BitField>
+      <BitField name="MODE" description="XSPI multiplexing mode" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="if MUXEN = 0 direct mode, if MUXEN = 1 arbitration mode to output Port 1" start="0x0" />
+        <Enum name="B_0x1" description="if MUXEN = 0 swapped mode, if MUXEN = 1 arbitration mode to output Port 2" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_EN" description="Chip select selector override enable" start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are ignored, the chip select signals from OCTOSPIs or XSPIs are transmitted unconditionally" start="0x0" />
+        <Enum name="B_0x1" description="CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are taken into account" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_O1" description="Chip select selector override setting for XSPI1" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI1 can only use NCS1 (accesses using NCS2 are ignored)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI1 can only use NCS2 (accesses using NCS1 are ignored)" start="0x1" />
+      </BitField>
+      <BitField name="CSSEL_OVR_O2" description="Chip select selector override setting for XSPI2" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI2 can only use NCS1 (accesses using NCS2 are ignored)" start="0x0" />
+        <Enum name="B_0x1" description="XSPI2 can only use NCS2 (accesses using NCS1 are ignored)" start="0x1" />
+      </BitField>
+      <BitField name="REQ2ACK_TIME" description="REQ to ACK time" start="16" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI1" description="Extended-SPI interface" start="0x48025000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI1_S" description="Extended-SPI interface" start="0x58025000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI2" description="Extended-SPI interface" start="0x4802A000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI2_S" description="Extended-SPI interface" start="0x5802A000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI3" description="Extended-SPI interface" start="0x4802D000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="XSPI3_S" description="Extended-SPI interface" start="0x5802D000">
+    <Register name="XSPI_CR" description="XSPI control register" start="+0x0000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="XSPI disabled" start="0x0" />
+        <Enum name="B_0x1" description="XSPI enabled" start="0x1" />
+      </BitField>
+      <BitField name="ABORT" description="Abort request" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no abort requested" start="0x0" />
+        <Enum name="B_0x1" description="abort requested" start="0x1" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled for indirect mode" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled for indirect mode" start="0x1" />
+      </BitField>
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode." start="0x0" />
+        <Enum name="B_0x1" description="timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity." start="0x1" />
+      </BitField>
+      <BitField name="DMM" description="Dual-memory configuration" start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="dual-memory configuration disabled" start="0x0" />
+        <Enum name="B_0x1" description="dual-memory configuration enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTHRES" description="FIFO threshold level" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode." start="0x0" />
+        <Enum name="B_0x1" description="FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode." start="0x1" />
+        <Enum name="B_0x3F" description="FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode." start="0x3F" />
+      </BitField>
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="TOIE" description="Timeout interrupt enable" start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="APMS" description="Automatic status-polling mode stop" start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic status-polling mode is stopped only by abort or by disabling the XSPI." start="0x0" />
+        <Enum name="B_0x1" description="Automatic status-polling mode stops as soon as there is a match." start="0x1" />
+      </BitField>
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register." start="0x0" />
+        <Enum name="B_0x1" description="OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register." start="0x1" />
+      </BitField>
+      <BitField name="CSSEL" description="chip select selection" start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 active" start="0x0" />
+        <Enum name="B_0x1" description="NCS2 active" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF" description="no prefetch data" start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="automatic prefetch enabled" start="0x0" />
+        <Enum name="B_0x1" description="automatic prefetch disabled" start="0x1" />
+      </BitField>
+      <BitField name="NOPREF_AXI" description="no prefetch for signaled AXI transactions" start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="prefetch is enabled for AXI signaled transactions." start="0x0" />
+        <Enum name="B_0x1" description="prefetch is disable for AXI signaled transactions." start="0x1" />
+      </BitField>
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="indirect-write mode" start="0x0" />
+        <Enum name="B_0x1" description="indirect-read mode" start="0x1" />
+        <Enum name="B_0x2" description="automatic status-polling mode" start="0x2" />
+        <Enum name="B_0x3" description="memory-mapped mode" start="0x3" />
+      </BitField>
+      <BitField name="MSEL" description="Flash select" start="30" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="data exchanged over IO[3:0]" start="0x0" />
+        <Enum name="B_0x1" description="data exchanged over IO[7:4]" start="0x1" />
+        <Enum name="B_0x2" description="data exchanged over IO[11:8]" start="0x2" />
+        <Enum name="B_0x3" description="data exchanged over IO[15:12]" start="0x3" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR1" description="XSPI device configuration register 1" start="+0x0008" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="clock mode 0" start="0" size="1" access="ReadOnly" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="CLK is not free running." start="0x0" />
+        <Enum name="B_0x1" description="CLK is free running (always provided)." start="0x1" />
+      </BitField>
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="6" access="Read/Write">
+        <Enum name="B_0x0" description="NCS stays high for at least 1 cycle between external device commands." start="0x0" />
+        <Enum name="B_0x1" description="NCS stays high for at least 2 cycles between external device commands." start="0x1" />
+        <Enum name="B_0x3F" description="NCS stays high for at least 64 cycles between external device commands." start="0x3F" />
+      </BitField>
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" access="Read/Write" />
+      <BitField name="EXTENDMEM" description="extended memory support" start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled)." start="0x0" />
+        <Enum name="B_0x1" description="NCS1 and NCS2 values depend from the address of transfer (hardware controlled)." start="0x1" />
+      </BitField>
+      <BitField name="MTYP" description="Memory type" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x0" />
+        <Enum name="B_0x1" description="Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes." start="0x1" />
+        <Enum name="B_0x2" description="Standard mode" start="0x2" />
+        <Enum name="B_0x3" description="Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping." start="0x3" />
+        <Enum name="B_0x4" description="HyperBus memory mode, the protocol follows the HyperBusless thansup&gt; less than/sup&gt;specification. 8-data-bit DTR mode must be selected." start="0x4" />
+        <Enum name="B_0x5" description="HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR2" description="XSPI device configuration register 2" start="+0x000C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;, kernel clock used directly as XSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the XSPI a kernel clock that has 50% duty-cycle." start="0x0" />
+        <Enum name="B_0x1" description="Fless thansub&gt;CLKless than/sub&gt; = Fless thansub&gt;KERNELless than/sub&gt;/2" start="0x1" />
+      </BitField>
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="wrapped reads are not supported by the memory." start="0x0" />
+        <Enum name="B_0x2" description="external memory supports wrap size of 16 bytes." start="0x2" />
+        <Enum name="B_0x3" description="external memory supports wrap size of 32 bytes." start="0x3" />
+        <Enum name="B_0x4" description="external memory supports wrap size of 64 bytes." start="0x4" />
+        <Enum name="B_0x5" description="external memory supports wrap size of 128 bytes." start="0x5" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR3" description="XSPI device configuration register 3" start="+0x0010" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" access="Read/Write">
+        <Enum name="B_0x0" description="maximum communication disabled" start="0x0" />
+      </BitField>
+      <BitField name="CSBOUND" description="NCS boundary" start="16" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="NCS boundary disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_DCR4" description="XSPI device configuration register 4" start="+0x0014" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="refresh disabled" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_SR" description="XSPI status register" start="+0x0020" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEF" description="Transfer error flag" start="0" size="1" access="ReadOnly" />
+      <BitField name="TCF" description="Transfer complete flag" start="1" size="1" access="ReadOnly" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" access="ReadOnly" />
+      <BitField name="SMF" description="Status match flag" start="3" size="1" access="ReadOnly" />
+      <BitField name="TOF" description="Timeout flag" start="4" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" access="ReadOnly" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_FCR" description="XSPI flag clear register" start="+0x0024" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" access="WriteOnly" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" access="WriteOnly" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" access="WriteOnly" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="XSPI_DLR" description="XSPI data length register" start="+0x0040" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_AR" description="XSPIaddress register" start="+0x0048" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Address" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_DR" description="XSPI data register" start="+0x0050" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PSMKR" description="XSPI polling status mask register" start="+0x0080" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" access="Read/Write">
+        <Enum name="B_0x0" description="bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic." start="0x0" />
+        <Enum name="B_0x1" description="bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_PSMAR" description="XSPI polling status match register" start="+0x0088" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_PIR" description="XSPI polling interval register" start="+0x0090" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CCR" description="XSPI communication configuration register" start="+0x0100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_TCR" description="XSPI timing configuration register" start="+0x0108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no delay hold" start="0x0" />
+        <Enum name="B_0x1" description="1/4 cycle hold" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_IR" description="XSPI instruction register" start="+0x0110" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_ABR" description="XSPI alternate bytes register" start="+0x0120" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_LPTR" description="XSPI low-power timeout register" start="+0x00130" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="None" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPCCR" description="XSPI wrap communication configuration register" start="+0x0140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="alternate bytes on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="DDTR" description="Data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPTCR" description="XSPI wrap timing configuration register" start="+0x0148" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no quarter cycle delay" start="0x0" />
+        <Enum name="B_0x1" description="quarter cycle delay inserted" start="0x1" />
+      </BitField>
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no shift" start="0x0" />
+        <Enum name="B_0x1" description="1/2 cycle shift" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WPIR" description="XSPI wrap instruction register" start="+0x0150" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WPABR" description="XSPI wrap alternate byte register" start="+0x0160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WCCR" description="XSPI write communication configuration register" start="+0x0180" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no instruction" start="0x0" />
+        <Enum name="B_0x1" description="instruction on a single line" start="0x1" />
+        <Enum name="B_0x2" description="instruction on two lines" start="0x2" />
+        <Enum name="B_0x3" description="instruction on four lines" start="0x3" />
+        <Enum name="B_0x4" description="instruction on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for instruction phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for instruction phase" start="0x1" />
+      </BitField>
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit instruction" start="0x0" />
+        <Enum name="B_0x1" description="16-bit instruction" start="0x1" />
+        <Enum name="B_0x2" description="24-bit instruction" start="0x2" />
+        <Enum name="B_0x3" description="32-bit instruction" start="0x3" />
+      </BitField>
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no address" start="0x0" />
+        <Enum name="B_0x1" description="address on a single line" start="0x1" />
+        <Enum name="B_0x2" description="address on two lines" start="0x2" />
+        <Enum name="B_0x3" description="address on four lines" start="0x3" />
+        <Enum name="B_0x4" description="address on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for address phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for address phase" start="0x1" />
+      </BitField>
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit address" start="0x0" />
+        <Enum name="B_0x1" description="16-bit address" start="0x1" />
+        <Enum name="B_0x2" description="24-bit address" start="0x2" />
+        <Enum name="B_0x3" description="32-bit address" start="0x3" />
+      </BitField>
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="alternate bytes on a single line" start="0x1" />
+        <Enum name="B_0x2" description="alternate bytes on two lines" start="0x2" />
+        <Enum name="B_0x3" description="alternate bytes on four lines" start="0x3" />
+        <Enum name="B_0x4" description="alternate bytes on eight lines" start="0x4" />
+      </BitField>
+      <BitField name="ABDTR" description="Alternate bytes double-transfer rate" start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for alternate-bytes phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for alternate-bytes phase" start="0x1" />
+      </BitField>
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="8-bit alternate bytes" start="0x0" />
+        <Enum name="B_0x1" description="16-bit alternate bytes" start="0x1" />
+        <Enum name="B_0x2" description="24-bit alternate bytes" start="0x2" />
+        <Enum name="B_0x3" description="32-bit alternate bytes" start="0x3" />
+      </BitField>
+      <BitField name="DMODE" description="Data mode" start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="no data" start="0x0" />
+        <Enum name="B_0x1" description="data on a single line" start="0x1" />
+        <Enum name="B_0x2" description="data on two lines" start="0x2" />
+        <Enum name="B_0x3" description="data on four lines" start="0x3" />
+        <Enum name="B_0x4" description="data on eight lines" start="0x4" />
+        <Enum name="B_0x5" description="Data on 16 lines" start="0x5" />
+      </BitField>
+      <BitField name="DDTR" description="data double transfer rate" start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DTR mode disabled for data phase" start="0x0" />
+        <Enum name="B_0x1" description="DTR mode enabled for data phase" start="0x1" />
+      </BitField>
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DQS disabled" start="0x0" />
+        <Enum name="B_0x1" description="DQS enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="XSPI_WTCR" description="XSPI write timing configuration register" start="+0x0188" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WIR" description="XSPI write instruction register" start="+0x0190" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="Instruction" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_WABR" description="XSPI write alternate byte register" start="+0x01A0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="None" start="0" size="32" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_HLCR" description="XSPI HyperBus latency configuration register" start="+0x0200" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Variable initial latency" start="0x0" />
+        <Enum name="B_0x1" description="Fixed latency" start="0x1" />
+      </BitField>
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="latency on write accesses" start="0x0" />
+        <Enum name="B_0x1" description="no latency on write accesses" start="0x1" />
+      </BitField>
+      <BitField name="TACC" description="None" start="8" size="8" access="Read/Write" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALFCR" description="XSPI full-cycle calibration configuration" start="+0x0210" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="ReadOnly" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="ReadOnly" />
+      <BitField name="CALMAX" description="Max value" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="XSPI_CALMR" description="XSPI DLL master calibration configuration" start="+0x0218" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSOR" description="XSPI DLL slave output calibration configuration" start="+0x0220" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+    <Register name="XSPI_CALSIR" description="XSPI DLL slave input calibration configuration" start="+0x0228" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FINE" description="None" start="0" size="7" access="Read/Write" />
+      <BitField name="COARSE" description="None" start="16" size="5" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+</Processor>
Index: trunk/firmware/App/SES/STM32N6xx_RAM.icf
===================================================================
--- trunk/firmware/App/SES/STM32N6xx_RAM.icf	(revision 22)
+++ trunk/firmware/App/SES/STM32N6xx_RAM.icf	(revision 22)
@@ -0,0 +1,145 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = FLEX_RAM;
+define region FLASH = FLASH_RAM;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH_RAM                          { section .FLASH_RAM, section .FLASH_RAM.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { section vectors };                                    // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in AXI_RAM5                           { section .AXI_RAM5, section .AXI_RAM5.* };  // This region may be deactivated and not accessible
+place in AXI_RAM6                           { section .AXI_RAM6, section .AXI_RAM6.* };  // This region may be deactivated and not accessible
+place in AXI_RAM7                           { section .AXI_RAM7, section .AXI_RAM7.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.* };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
Index: trunk/firmware/App/SES/blto_App.emProject
===================================================================
--- trunk/firmware/App/SES/blto_App.emProject	(revision 22)
+++ trunk/firmware/App/SES/blto_App.emProject	(revision 22)
@@ -0,0 +1,91 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="blto_App" target="8" version="2">
+  <configuration
+    Name="Debug"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="None" />
+  <configuration Name="Production" />
+  <configuration
+    Name="Release"
+    c_preprocessor_definitions="NDEBUG"
+    gcc_debugging_level="Level 2"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="Level 2 balanced"
+    link_dedupe_code="Yes" />
+  <project Name="blto_App">
+    <configuration
+      LIBRARY_IO_TYPE="RTT"
+      Name="Common"
+      Target="STM32N657X0HxQ"
+      arm_architecture="v8.1M_Mainline"
+      arm_compiler_variant="SEGGER"
+      arm_core_type="Cortex-M55"
+      arm_endian="Little"
+      arm_fp_abi="Hard"
+      arm_fpu_type="FPv5-D16"
+      arm_library_optimization="Fast"
+      arm_linker_heap_size="64"
+      arm_linker_process_stack_size="0"
+      arm_linker_stack_size="8192"
+      arm_linker_variant="SEGGER"
+      arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00040000;RAM;0x30000000;0x00040000;RAM;0x34000000;0x00064000;RAM;0x34200000;0x00070000;RAM;0x34270000;0x00070000;RAM;0x342E0000;0x00070000;RAM;0x34350000;0x00070000;RAM;0x38000000;0x00004000;RAM;0x38004000;0x00004000;RAM;0x3C000000;0x00002000"
+      arm_target_device_name="STM32N657X0"
+      arm_target_interface_type="SWD"
+      arm_v8M_has_cmse="Yes"
+      batch_build_configurations="Debug;Production;Release"
+      build_intermediate_directory="Output/$(Configuration)/Obj"
+      c_preprocessor_definitions="STM32N657xx;__SET_STACK_LIMITS=1;__STM32N657_SUBFAMILY;__STM32N6XX_FAMILY;USE_HAL_DRIVER"
+      c_user_include_directories="./../CubeMX/Appli/Core/Inc;./../CubeMX/Secure_nsclib;./../CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc;./../CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include;./../CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy;./../CubeMX/Drivers/CMSIS/Include"
+      compiler_color_diagnostics="Yes"
+      debug_register_definition_file="$(ProjectDir)/STM32N657_Registers.xml"
+      debug_stack_pointer_start="__stack_end__"
+      debug_start_from_entry_point_symbol="Yes"
+      debug_target_connection="J-Link"
+      gcc_all_warnings="Enable"
+      gcc_c_language_standard="c23"
+      gcc_entry_point="Reset_Handler"
+      gcc_wchar_size="32-Bit"
+      link_linker_script_file="$(ProjectDir)/STM32N6xx_RAM.icf"
+      link_map_file="Full"
+      link_map_file_format="HTML"
+      link_time_optimization="Yes"
+      linker_memory_map_file="$(ProjectDir)/STM32N657X0HxQ_MemoryMap.xml"
+      linker_output_format="bin"
+      linker_printf_fmt_level="long long"
+      linker_printf_fp_enabled="Float"
+      linker_printf_width_precision_supported="Yes"
+      macros="DeviceVectorsFile=$(PackagesDir)/STM32N6xx/Source/stm32n657xx_Vectors.s;DeviceFamily=STM32N6xx;DeviceSubFamily=STM32N657;Target=STM32N657X0HxQ"
+      project_directory=""
+      project_type="Executable"
+      target_reset_script="Reset();" />
+    <folder Name="Script Files">
+      <file file_name="STM32N6xx/Scripts/STM32N6xx_Target.js">
+        <configuration Name="Common" file_type="Reset Script" />
+      </file>
+    </folder>
+    <folder Name="Source Files">
+      <configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
+      <folder
+        Name="Core"
+        exclude="syscalls.c;sysmem.c"
+        filter="*.c;*.h"
+        path="../CubeMX/Appli/Core"
+        recurse="Yes" />
+      <folder
+        Name="HAL"
+        exclude=""
+        filter="*.c;*.h"
+        path="../CubeMX/Drivers/STM32N6xx_HAL_Driver"
+        recurse="Yes" />
+    </folder>
+    <folder Name="System Files">
+      <file file_name="SEGGER_THUMB_Startup.s" />
+      <file file_name="STM32N6xx/Source/stm32n657xx_Vectors.s">
+        <configuration Name="Common" file_type="Assembly" />
+      </file>
+      <file file_name="STM32N6xx/Source/STM32N6xx_Startup.s" />
+    </folder>
+  </project>
+</solution>
Index: trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.htm
===================================================================
--- trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.htm	(revision 21)
+++ 	(revision )
@@ -1,18837 +1,0 @@
-<!DOCTYPE html>
-<html>
-<style>
-body { font-family: "Tahoma", "Open Sans", "Helvetica Neue", Helvetica, Arial, sans-serif; font-size: 0.9rem; line-height: 1.5; min-width: 400px;             padding-left: 20px; padding-left: 80px; padding-right: 5px; }
-html { margin: 0; padding: 0; }
-pre { border: 1px solid #d0d4d9; background: #f6f9fc; padding: 10px 10px; border-radius: 3px; font-size: 0.9rem; font-family: Consolas, Courier, monospace; }
-th { background-color: #f6f9fc; }
-table, th, td { border: 1px solid #d0d4d9; border-collapse: collapse; padding: 4px 4px; }
-h1 { color: #0B5B9A; margin-top: 50px; margin-left: -50pt; margin-bottom: 20px; text-align: left; font-size: 1.5em; border-bottom: 1px solid #0B5B9A; }
-h2 { color: #0B5B9A; margin-top: 30px; margin-left: -50pt;                      text-align: left; font-size: 1.2em; }
-a { color: #0B5B9A; text-decoration: none; }
-a:hover { color: #d3d800; }
-ul { margin: 0; padding: 0; }
-ul li ul { margin: 10px; }
-</style>
-<body>
-<h1>CONTENTS</h1>
-<ul>
-  <li><a href="#LINK INFORMATION">LINK INFORMATION</a>
-<ul>
-  <li><a href="#LINK INFORMATION_Linker version">Linker version</a></li>
-  <li><a href="#LINK INFORMATION_Command line">Command line</a></li>
-</ul>
-  </li>
-  <li><a href="#LINKER SCRIPT">LINKER SCRIPT</a>
-<ul>
-  <li><a href="#LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf&apos;</a></li>
-</ul>
-  </li>
-  <li><a href="#PLACEMENT SUMMARY">PLACEMENT SUMMARY</a>
-<ul>
-  <li><a href="#PLACEMENT SUMMARY_place at 0x34180400">place at 0x34180400</a></li>
-  <li><a href="#PLACEMENT SUMMARY_place at 0x34200000">place at 0x34200000</a></li>
-  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#14&gt; at line 120, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with maximum packing">&quot;&lt;#14&gt; at line 120, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with maximum packing</a></li>
-  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#16&gt; at line 128, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order">&quot;&lt;#16&gt; at line 128, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order</a></li>
-  <li><a href="#PLACEMENT SUMMARY_&quot;&lt;#17&gt; at line 132, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order">&quot;&lt;#17&gt; at line 132, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order</a></li>
-</ul>
-  </li>
-  <li><a href="#MODULE SUMMARY">MODULE SUMMARY</a>
-<ul>
-  <li><a href="#MODULE SUMMARY_Memory use by input file">Memory use by input file</a></li>
-  <li><a href="#MODULE SUMMARY_Memory use by archive member">Memory use by archive member</a></li>
-  <li><a href="#MODULE SUMMARY_Memory use by linker">Memory use by linker</a></li>
-</ul>
-  </li>
-  <li><a href="#MODULE DETAIL">MODULE DETAIL</a>
-<ul>
-  <li><a href="#MODULE DETAIL_Module blto2_FSBL_lto.o">Module blto2_FSBL_lto.o</a></li>
-  <li><a href="#MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</a></li>
-  <li><a href="#MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</a></li>
-  <li><a href="#MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</a></li>
-  <li><a href="#MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</a></li>
-  <li><a href="#MODULE DETAIL_Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)">Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</a></li>
-  <li><a href="#MODULE DETAIL_All modules">All modules</a></li>
-</ul>
-  </li>
-  <li><a href="#SECTION DETAIL">SECTION DETAIL</a>
-<ul>
-  <li><a href="#SECTION DETAIL_Sections by address">Sections by address</a></li>
-</ul>
-  </li>
-  <li><a href="#UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</a>
-<ul>
-  <li><a href="#UNUSED MEMORY SUMMARY_Detail">Detail</a></li>
-</ul>
-  </li>
-  <li><a href="#INITIALIZATION TABLE">INITIALIZATION TABLE</a>
-<ul>
-  <li><a href="#INITIALIZATION TABLE_Constructor list">Constructor list</a></li>
-  <li><a href="#INITIALIZATION TABLE_Initialize by zero">Initialize by zero</a></li>
-  <li><a href="#INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</a></li>
-  <li><a href="#INITIALIZATION TABLE_Summary">Summary</a></li>
-</ul>
-  </li>
-  <li><a href="#LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</a>
-<ul>
-  <li><a href="#LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</a></li>
-  <li><a href="#LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</a></li>
-  <li><a href="#LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</a></li>
-  <li><a href="#LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</a></li>
-  <li><a href="#LINKER-CREATED VENEERS_Summary">Summary</a></li>
-</ul>
-  </li>
-  <li><a href="#SYMBOL LIST">SYMBOL LIST</a>
-<ul>
-  <li><a href="#SYMBOL LIST_Function symbols by name">Function symbols by name</a></li>
-  <li><a href="#SYMBOL LIST_Function symbols by address">Function symbols by address</a></li>
-  <li><a href="#SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</a></li>
-  <li><a href="#SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</a></li>
-  <li><a href="#SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</a></li>
-  <li><a href="#SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</a></li>
-  <li><a href="#SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</a></li>
-  <li><a href="#SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</a></li>
-  <li><a href="#SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</a></li>
-  <li><a href="#SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</a></li>
-</ul>
-  </li>
-  <li><a href="#REGION LIST">REGION LIST</a>
-<ul>
-  <li><a href="#REGION LIST_Regions by name">Regions by name</a></li>
-  <li><a href="#REGION LIST_Analysis">Analysis</a></li>
-</ul>
-  </li>
-  <li><a href="#BLOCK LIST">BLOCK LIST</a>
-<ul>
-  <li><a href="#BLOCK LIST_Blocks by name">Blocks by name</a></li>
-  <li><a href="#BLOCK LIST_Blocks by address">Blocks by address</a></li>
-</ul>
-  </li>
-  <li><a href="#STACK SIZES">STACK SIZES</a>
-<ul>
-  <li><a href="#STACK SIZES_Functions by stack size">Functions by stack size</a></li>
-  <li><a href="#STACK SIZES_Functions without stack size information">Functions without stack size information</a></li>
-</ul>
-  </li>
-  <li><a href="#UNUSED INPUTS">UNUSED INPUTS</a>
-<ul>
-  <li><a href="#UNUSED INPUTS_Unused object files">Unused object files</a></li>
-</ul>
-  </li>
-  <li><a href="#ABSOLUTE LISTING">ABSOLUTE LISTING</a>
-<ul>
-  <li><a href="#ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.main from blto2_FSBL_lto.o, size=1184, align=4">Section .text.main from blto2_FSBL_lto.o, size=1184, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4">Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4">Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4">Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4">Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4">Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4">Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4">Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4">Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4">Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4">Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4">Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4">Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4">Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4">Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4">Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=4, align=4">Section .segger.init.data from [ Linker created ], size=4, align=4</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2</a></li>
-  <li><a href="#ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</a></li>
-</ul>
-  </li>
-  <li><a href="#LINK SUMMARY">LINK SUMMARY</a>
-<ul>
-  <li><a href="#LINK SUMMARY_Memory breakdown">Memory breakdown</a></li>
-  <li><a href="#LINK SUMMARY_Region summary">Region summary</a></li>
-  <li><a href="#LINK SUMMARY_Diagnostic summary">Diagnostic summary</a></li>
-</ul>
-  </li>
-</ul>
-<h1 id="LINK INFORMATION">LINK INFORMATION</h1>
-<h2 id="LINK INFORMATION_Linker version">Linker version</h2>
-
-<pre>
-SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
-Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
-</pre>
-<h2 id="LINK INFORMATION_Command line">Command line</h2>
-
-<pre>
---add-region:ITCM_RAM=0x00010000@0x10000000
---add-region:DTCM_RAM=0x00020000@0x30000000
---add-region:FLEX_RAM=0x00064000@0x34000000
---add-region:AXI_RAM1=0x0009c000@0x34064000
---add-region:AXI_RAM2=0x0007fc00@0x34180400
---add-region:AXI_RAM3=0x00070000@0x34200000
---add-region:AXI_RAM4=0x00070000@0x34270000
---add-region:AXI_RAM5=0x00070000@0x342e0000
---add-region:AXI_RAM6=0x00070000@0x34350000
---add-region:AXI_RAM7=0x00040000@0x343c0000
---add-region:AXI_RAM8=0x00020000@0x34400000
---add-region:AHB_RAM1=0x00004000@0x38000000
---add-region:AHB_RAM2=0x00004000@0x38004000
---add-region:BKP_RAM=0x00002000@0x3c000000
---full-section-headers
---merge-sections
---merge-strings
---map-html
---map-file=Output/Production/Exe/blto2_FSBL.htm
---map-full
---list-all-undefineds
--eReset_Handler
--EL
--mcpu=8.1-M.main
---silent
--TD:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf
---defsym=__STACKSIZE__=8192
---defsym=__STACKSIZE_PROCESS__=0
---defsym=__HEAPSIZE__=256
---defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
---defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
--u_vectors
--o
-D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.elf
-D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Production/Obj/blto2_FSBL_lto.o
-Output/Production/Obj/SEGGER_THUMB_Startup.o
-Output/Production/Obj/stm32n657xx_Vectors.o
-Output/Production/Obj/STM32N6xx_Startup.o
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
-</pre>
-<h1 id="LINKER SCRIPT">LINKER SCRIPT</h1>
-<h2 id="LINKER SCRIPT_Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf&apos;">Linker script &apos;D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf&apos;</h2>
-
-<pre>
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* - Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
--------------------------- END-OF-HEADER -----------------------------
-
-File    : STM32N6xx_RAM.icf
-Purpose : STM32N6xx linker script for application placement in RAM
-          (to be copied to RAM by bootloader or debugger)
-          for use with the SEGGER Linker.
-Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
-          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
-          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
-          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
-          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
-          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
-Literature:
-  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
-  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
-*/
-
-define memory with size = 4G;
-
-//
-// Combined regions per memory type
-//
-define region RAM   = AXI_RAM2;
-
-//
-// Block definitions
-//
-define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
-define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
-define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
-define block tbss                           { section .tbss,      section .tbss.*  };
-define block tdata                          { section .tdata,     section .tdata.* };
-define block tls with fixed order           { block tbss, block tdata };
-define block tdata_load                     { copy of block tdata };
-define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
-define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
-define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
-
-//
-// Explicit initialization settings for sections
-// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
-//
-do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
-do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
-do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
-do not initialize                           { section .vectors_ram };
-initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
-initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
-
-initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
-
-#define USES_ALLOC_FUNC                                   \
-  linked symbol malloc || linked symbol aligned_alloc ||  \
-  linked symbol calloc || linked symbol realloc
-
-initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
-initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
-
-//assert with warning "free() linked into application but there are no calls to an allocation function!" {
-//  linked symbol free => USES_ALLOC_FUNC
-//};
-
-assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
-assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
-assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
-
-//
-// Explicit placement in RAMn
-//
-place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
-place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
-place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
-place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
-place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
-place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
-place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.*  };  // This region may be deactivated and not accessible
-place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
-place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
-place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
-
-//
-// RAM Placement
-//
-place at start of RAM                       { section .vectors };                                   // Vector table section
-place in RAM with minimum size order        { block tdata_load,                                     // Thread-local-storage load image
-                                              block exidx,                                          // ARM exception unwinding block
-                                              block ctors,                                          // Constructors block
-                                              block dtors,                                          // Destructors block
-                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
-                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
-                                            };
-place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
-place in RAM with auto order                { block tls,                                            // Thread-local-storage block
-                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
-                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
-                                            };
-place in RAM                                { block heap };                                         // Heap reserved block
-place at end of RAM                         { block stack };                                        // Stack reserved block at the end
-
-</pre>
-<h1 id="PLACEMENT SUMMARY">PLACEMENT SUMMARY</h1>
-<h2 id="PLACEMENT SUMMARY_place at 0x34180400">place at 0x34180400</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="left">Type</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>_vectors</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34180400</code></td>
-    <td align="right"><code>844</code></td>
-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-</table>
-<h2 id="PLACEMENT SUMMARY_place at 0x34200000">place at 0x34200000</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="left">Type</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>[.bss.block.stack]</code></td>
-    <td align="left"><code>None</code></td>
-    <td align="right"><code>0x341FE000</code></td>
-    <td align="right"><code>8 192</code></td>
-    <td align="right"><code>8</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h2 id="PLACEMENT SUMMARY_&quot;&lt;#14&gt; at line 120, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with maximum packing">&quot;&lt;#14&gt; at line 120, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with maximum packing</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="left">Type</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>main</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418074C</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34180BEC</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34180BFC</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34180D8C</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418134C</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341813E0</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="right"><code>0x34181460</code></td>
-    <td align="right"><code>64</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.rodata..Lswitch.table.RCC_PLL_Config]</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="right"><code>0x341814A0</code></td>
-    <td align="right"><code>12</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>_start</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341814AC</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341814C0</code></td>
-    <td align="right"><code>44</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341814EC</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181554</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181556</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181558</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418155A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418155C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418155E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181560</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181562</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181564</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181566</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181568</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418156A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418156C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418156E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181570</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181572</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181574</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341816A2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341816A4</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181846</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181848</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181EFA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181EFC</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181F82</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34181F84</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182142</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182144</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182146</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182148</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418214A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418214C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418214E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182150</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182152</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182154</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182156</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182158</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418215A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418215C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418215E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182160</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182162</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182164</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182166</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182168</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418216A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418216C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418216E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182170</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182172</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182174</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182176</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182178</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418217A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418217C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418217E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182180</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182182</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182184</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182186</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182188</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418218A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418218C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418218E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182190</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182192</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182194</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182196</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182198</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418219A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418219C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418219E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821A0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821A2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821A4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821A6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821A8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821AA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821AC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821AE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821B0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821B2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821B4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821B6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821B8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821BA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821BC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821BE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821C0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821C2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821C4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821C6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821C8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821CA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821CC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821CE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821D0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821D2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821D4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821D6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821D8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821DA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821DC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821DE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821E0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821E2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821E4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821E6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821E8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821EA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821EC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821EE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821F0</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821F2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821F4</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821F6</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821F8</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821FA</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821FC</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341821FE</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182200</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182202</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182204</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182206</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182208</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418220A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418220C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418220E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182210</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182212</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182214</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182216</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182218</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418221A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418221C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418221E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182220</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182222</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182224</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182226</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182228</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418222A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418222C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418222E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182230</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182232</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182234</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182236</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182238</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418223A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418223C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418223E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182240</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182242</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182244</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182246</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182248</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418224A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418224C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418224E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182250</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182252</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182254</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182256</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182258</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418225A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418225C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418225E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182260</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182262</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182264</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182266</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182268</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418226A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418226C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418226E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182270</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182272</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182274</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182276</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182278</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418227A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418227C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418227E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182280</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182282</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182284</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182286</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182288</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418228A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418228C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418228E</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182290</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182292</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182294</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182296</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x34182298</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418229A</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418229C</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.rodata.block.tdata.copy]</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="right"><code>0x3418229E</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>1</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.init_array]</code></td>
-    <td align="left"><code>----</code></td>
-    <td align="right"><code>0x341822A0</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341822B0</code></td>
-    <td align="right"><code>36</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_table__</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="right"><code>0x341822D4</code></td>
-    <td align="right"><code>36</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_data__</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="right"><code>0x341822F8</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x341822FC</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="right"><code>0x3418230E</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-</table>
-<h2 id="PLACEMENT SUMMARY_&quot;&lt;#16&gt; at line 128, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order">&quot;&lt;#16&gt; at line 128, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="left">Type</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>[.bss.block.heap]</code></td>
-    <td align="left"><code>None</code></td>
-    <td align="right"><code>0x341822A0</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTick</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="right"><code>0x341822A4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="right"><code>0x341822A8</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="left"><code>Init</code></td>
-    <td align="right"><code>0x341822AC</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.bss.block.stack]</code></td>
-    <td align="left"><code>None</code></td>
-    <td align="right"><code>0x341FE000</code></td>
-    <td align="right"><code>8 192</code></td>
-    <td align="right"><code>8</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h2 id="PLACEMENT SUMMARY_&quot;&lt;#17&gt; at line 132, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order">&quot;&lt;#17&gt; at line 132, col 45&quot;: place in [0x34180400 to 0x341FFFFF] with auto order</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="left">Type</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>[.bss.block.heap]</code></td>
-    <td align="left"><code>None</code></td>
-    <td align="right"><code>0x341822A0</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h1 id="MODULE SUMMARY">MODULE SUMMARY</h1>
-<h2 id="MODULE SUMMARY_Memory use by input file">Memory use by input file</h2>
-
-<table>
-  <tr>
-    <th align="left">Object File</th>
-    <th align="right">RX Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-    <td align="right"><code>6 378</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-    <td align="right"><code>1 216</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-    <td align="right"><code>44</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Subtotal (4 objects)</code></td>
-    <td align="right"><code>7 658</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a</code></td>
-    <td align="right"><code>74</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Subtotal (2archives)</code></td>
-    <td align="right"><code>178</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>40</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8 192</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>7 836</code></td>
-    <td align="right"><code>116</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>8 197</code></td>
-  </tr>
-</table>
-<h2 id="MODULE SUMMARY_Memory use by archive member">Memory use by archive member</h2>
-
-<table>
-  <tr>
-    <th align="left">Archive member</th>
-    <th align="right">RX Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-    <td align="right"><code>74</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Subtotal (2 members from 2 archives)</code></td>
-    <td align="right"><code>178</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Objects (4 files)</code></td>
-    <td align="right"><code>7 658</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Linker created (shared data, fills, blocks):</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>40</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8 192</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>7 836</code></td>
-    <td align="right"><code>116</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>8 197</code></td>
-  </tr>
-</table>
-<h2 id="MODULE SUMMARY_Memory use by linker">Memory use by linker</h2>
-
-<table>
-  <tr>
-    <th align="left">Description</th>
-    <th align="right">RX Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>Initialization table</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>40</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Memory for block &apos;stack&apos;</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8 192</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Subtotal (linker created):</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>40</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>8 192</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Objects (4 files)</code></td>
-    <td align="right"><code>7 658</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Archives (2 files)</code></td>
-    <td align="right"><code>178</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>7 836</code></td>
-    <td align="right"><code>116</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>8 197</code></td>
-  </tr>
-</table>
-<h1 id="MODULE DETAIL">MODULE DETAIL</h1>
-<h2 id="MODULE DETAIL_Module blto2_FSBL_lto.o">Module blto2_FSBL_lto.o</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>main</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>64</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>[.rodata..Lswitch.table.RCC_PLL_Config]</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>12</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTick</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>1</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>6 378</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_Module SEGGER_THUMB_Startup.o">Module SEGGER_THUMB_Startup.o</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>_start</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_Module stm32n657xx_Vectors.o">Module stm32n657xx_Vectors.o</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>_vectors</code></td>
-    <td align="right"><code>844</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>1 216</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_Module STM32N6xx_Startup.o">Module STM32N6xx_Startup.o</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="right"><code>44</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>44</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)">Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="right"><code>36</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>74</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)">Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol or [section] name</th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Total:</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-  </tr>
-</table>
-<h2 id="MODULE DETAIL_All modules">All modules</h2>
-
-<table>
-  <tr>
-    <th align="left"></th>
-    <th align="right">Code</th>
-    <th align="right">RO Data</th>
-    <th align="right">RW Data</th>
-    <th align="right">ZI Data</th>
-  </tr>
-  <tr>
-    <td align="left"><code>Grand total:</code></td>
-    <td align="right"><code>7 836</code></td>
-    <td align="right"><code>76</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>5</code></td>
-  </tr>
-</table>
-<h1 id="SECTION DETAIL">SECTION DETAIL</h1>
-<h2 id="SECTION DETAIL_Sections by address">Sections by address</h2>
-
-<table>
-  <tr>
-    <th align="left">Range</th>
-    <th align="left">Symbol or [section] Name</th>
-    <th align="right">Size</th>
-    <th align="right">Al</th>
-    <th align="left">Init</th>
-    <th align="left">Ac</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>34180400-3418074B</code></td>
-    <td align="left"><code>_vectors</code></td>
-    <td align="right"><code>844</code></td>
-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418074C-34180BEB</code></td>
-    <td align="left"><code>main</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34180BEC-34180BFB</code></td>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34180BFC-34180D8B</code></td>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34180D8C-3418134B</code></td>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418134C-341813DF</code></td>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341813E0-3418145F</code></td>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181460-3418149F</code></td>
-    <td align="left"><code>[.rodata..Lswitch.table.HAL_GPIO_DeInit]</code></td>
-    <td align="right"><code>64</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>RO</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341814A0-341814AB</code></td>
-    <td align="left"><code>[.rodata..Lswitch.table.RCC_PLL_Config]</code></td>
-    <td align="right"><code>12</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>RO</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341814AC-341814BF</code></td>
-    <td align="left"><code>_start</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341814C0-341814EB</code></td>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="right"><code>44</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341814EC-34181553</code></td>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181554-34181555</code></td>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181556-34181557</code></td>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181558-34181559</code></td>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418155A-3418155B</code></td>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418155C-3418155D</code></td>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418155E-3418155F</code></td>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181560-34181561</code></td>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181562-34181563</code></td>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181564-34181565</code></td>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181566-34181567</code></td>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181568-34181569</code></td>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418156A-3418156B</code></td>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418156C-3418156D</code></td>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418156E-3418156F</code></td>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181570-34181571</code></td>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181572-34181573</code></td>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181574-341816A1</code></td>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341816A2-341816A3</code></td>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341816A4-34181845</code></td>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181846-34181847</code></td>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181848-34181EF9</code></td>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181EFA-34181EFB</code></td>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181EFC-34181F81</code></td>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181F82-34181F83</code></td>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34181F84-34182141</code></td>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182142-34182143</code></td>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182144-34182145</code></td>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182146-34182147</code></td>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182148-34182149</code></td>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418214A-3418214B</code></td>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418214C-3418214D</code></td>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418214E-3418214F</code></td>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182150-34182151</code></td>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182152-34182153</code></td>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182154-34182155</code></td>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182156-34182157</code></td>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182158-34182159</code></td>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418215A-3418215B</code></td>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418215C-3418215D</code></td>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418215E-3418215F</code></td>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182160-34182161</code></td>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182162-34182163</code></td>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182164-34182165</code></td>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182166-34182167</code></td>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182168-34182169</code></td>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418216A-3418216B</code></td>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418216C-3418216D</code></td>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418216E-3418216F</code></td>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182170-34182171</code></td>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182172-34182173</code></td>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182174-34182175</code></td>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182176-34182177</code></td>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182178-34182179</code></td>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418217A-3418217B</code></td>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418217C-3418217D</code></td>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418217E-3418217F</code></td>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182180-34182181</code></td>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182182-34182183</code></td>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182184-34182185</code></td>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182186-34182187</code></td>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182188-34182189</code></td>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418218A-3418218B</code></td>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418218C-3418218D</code></td>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418218E-3418218F</code></td>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182190-34182191</code></td>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182192-34182193</code></td>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182194-34182195</code></td>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182196-34182197</code></td>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182198-34182199</code></td>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418219A-3418219B</code></td>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418219C-3418219D</code></td>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418219E-3418219F</code></td>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821A0-341821A1</code></td>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821A2-341821A3</code></td>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821A4-341821A5</code></td>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821A6-341821A7</code></td>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821A8-341821A9</code></td>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821AA-341821AB</code></td>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821AC-341821AD</code></td>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821AE-341821AF</code></td>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821B0-341821B1</code></td>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821B2-341821B3</code></td>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821B4-341821B5</code></td>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821B6-341821B7</code></td>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821B8-341821B9</code></td>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821BA-341821BB</code></td>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821BC-341821BD</code></td>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821BE-341821BF</code></td>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821C0-341821C1</code></td>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821C2-341821C3</code></td>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821C4-341821C5</code></td>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821C6-341821C7</code></td>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821C8-341821C9</code></td>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821CA-341821CB</code></td>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821CC-341821CD</code></td>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821CE-341821CF</code></td>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821D0-341821D1</code></td>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821D2-341821D3</code></td>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821D4-341821D5</code></td>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821D6-341821D7</code></td>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821D8-341821D9</code></td>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821DA-341821DB</code></td>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821DC-341821DD</code></td>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821DE-341821DF</code></td>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821E0-341821E1</code></td>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821E2-341821E3</code></td>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821E4-341821E5</code></td>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821E6-341821E7</code></td>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821E8-341821E9</code></td>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821EA-341821EB</code></td>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821EC-341821ED</code></td>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821EE-341821EF</code></td>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821F0-341821F1</code></td>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821F2-341821F3</code></td>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821F4-341821F5</code></td>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821F6-341821F7</code></td>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821F8-341821F9</code></td>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821FA-341821FB</code></td>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821FC-341821FD</code></td>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341821FE-341821FF</code></td>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182200-34182201</code></td>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182202-34182203</code></td>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182204-34182205</code></td>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182206-34182207</code></td>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182208-34182209</code></td>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418220A-3418220B</code></td>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418220C-3418220D</code></td>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418220E-3418220F</code></td>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182210-34182211</code></td>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182212-34182213</code></td>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182214-34182215</code></td>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182216-34182217</code></td>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182218-34182219</code></td>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418221A-3418221B</code></td>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418221C-3418221D</code></td>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418221E-3418221F</code></td>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182220-34182221</code></td>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182222-34182223</code></td>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182224-34182225</code></td>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182226-34182227</code></td>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182228-34182229</code></td>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418222A-3418222B</code></td>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418222C-3418222D</code></td>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418222E-3418222F</code></td>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182230-34182231</code></td>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182232-34182233</code></td>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182234-34182235</code></td>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182236-34182237</code></td>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182238-34182239</code></td>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418223A-3418223B</code></td>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418223C-3418223D</code></td>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418223E-3418223F</code></td>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182240-34182241</code></td>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182242-34182243</code></td>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182244-34182245</code></td>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182246-34182247</code></td>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182248-34182249</code></td>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418224A-3418224B</code></td>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418224C-3418224D</code></td>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418224E-3418224F</code></td>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182250-34182251</code></td>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182252-34182253</code></td>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182254-34182255</code></td>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182256-34182257</code></td>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182258-34182259</code></td>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418225A-3418225B</code></td>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418225C-3418225D</code></td>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418225E-3418225F</code></td>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182260-34182261</code></td>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182262-34182263</code></td>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182264-34182265</code></td>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182266-34182267</code></td>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182268-34182269</code></td>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418226A-3418226B</code></td>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418226C-3418226D</code></td>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418226E-3418226F</code></td>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182270-34182271</code></td>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182272-34182273</code></td>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182274-34182275</code></td>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182276-34182277</code></td>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182278-34182279</code></td>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418227A-3418227B</code></td>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418227C-3418227D</code></td>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418227E-3418227F</code></td>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182280-34182281</code></td>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182282-34182283</code></td>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182284-34182285</code></td>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182286-34182287</code></td>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182288-34182289</code></td>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418228A-3418228B</code></td>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418228C-3418228D</code></td>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418228E-3418228F</code></td>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182290-34182291</code></td>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182292-34182293</code></td>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182294-34182295</code></td>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182296-34182297</code></td>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182298-34182299</code></td>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418229A-3418229B</code></td>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418229C-3418229D</code></td>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418229E-3418229F</code></td>
-    <td align="left" style="color: red;"><code>( UNUSED .=.+2 )</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>-</code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>-</code></td>
-    <td align="left"><code>-</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A0-341822A3</code></td>
-    <td align="left"><code>[.init_array]</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>--</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A4-341822A7</code></td>
-    <td align="left"><code>uwTick</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>ZI</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A8-341822A8</code></td>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>ZI</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A9-341822AB</code></td>
-    <td align="left" style="color: red;"><code>( ALIGN .=.+3 )</code></td>
-    <td align="right"><code>3</code></td>
-    <td align="right"><code>-</code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>-</code></td>
-    <td align="left"><code>-</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822AC-341822AF</code></td>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Init</code></td>
-    <td align="left"><code>RW</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822B0-341822D3</code></td>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="right"><code>36</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822D4-341822F7</code></td>
-    <td align="left"><code>__SEGGER_init_table__</code></td>
-    <td align="right"><code>36</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>RO</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822F8-341822FB</code></td>
-    <td align="left"><code>__SEGGER_init_data__</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>RO</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822FC-3418230D</code></td>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>3418230E-34182321</code></td>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>RX</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182322-341FDFFF</code></td>
-    <td align="left" style="color: red;"><code>( UNUSED .=.+507102 )</code></td>
-    <td align="right"><code>507 102</code></td>
-    <td align="right"><code>-</code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>-</code></td>
-    <td align="left"><code>-</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341FE000-341FFFFF</code></td>
-    <td align="left"><code>[.bss.block.stack]</code></td>
-    <td align="right"><code>8 192</code></td>
-    <td align="right"><code>8</code></td>
-    <td align="left"><code>None</code></td>
-    <td align="left"><code>ZI</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h1 id="UNUSED MEMORY SUMMARY">UNUSED MEMORY SUMMARY</h1>
-<h2 id="UNUSED MEMORY SUMMARY_Detail">Detail</h2>
-
-<table>
-  <tr>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="left">Reason</th>
-  </tr>
-  <tr>
-    <td align="left"><code>3418229E-3418229F</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Unused memory between sections &apos;.init.LTDC_UP_ERR_IRQHandler&apos; and &apos;.init_array&apos;</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A9-341822AB</code></td>
-    <td align="right"><code>3</code></td>
-    <td align="left"><code>Filler between sections &apos;.bss.uwTickPrio&apos; and &apos;.data.SystemCoreClock&apos; as align=4</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left" style="color: red;"><code>NOTE: section &apos;.bss.uwTickPrio&apos; has size 1 that is not a multiple of its alignment 4</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>34182322-341FDFFF</code></td>
-    <td align="right"><code>507 102</code></td>
-    <td align="left"><code>Unused memory between sections &apos;.segger.init.__SEGGER_init_copy&apos; and &apos;.bss.block.stack&apos;</code></td>
-  </tr>
-</table>
-<h1 id="INITIALIZATION TABLE">INITIALIZATION TABLE</h1>
-<h2 id="INITIALIZATION TABLE_Constructor list">Constructor list</h2>
-
-<table>
-  <tr>
-    <th align="left">Table<br/>Address</th>
-    <th align="left">Called<br/>Address</th>
-    <th align="left">Called<br/>Symbol or [section] name</th>
-  </tr>
-  <tr>
-    <td align="left"><code>0x341822A0</code></td>
-    <td align="left"><code>0x34180BFD</code></td>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-  </tr>
-</table>
-<h2 id="INITIALIZATION TABLE_Initialize by zero">Initialize by zero</h2>
-
-<table>
-  <tr>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="left">Symbol or [section] name</th>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A4-341822A7</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>uwTick</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A8-341822A8</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="left"><code>uwTickPrio</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A4-341822A8</code></td>
-    <td align="right"><code>5</code></td>
-    <td align="left"><code>Total (2 sections)</code></td>
-  </tr>
-<h2 id="INITIALIZATION TABLE_Initialize by copy with packing=none">Initialize by copy with packing=none</h2>
-
-<table>
-  <tr>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="left">Symbol or [section] name</th>
-  </tr>
-  <tr>
-    <td align="left"><code>341822AC-341822AF</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>SystemCoreClock</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341822AC-341822AF</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Total (1 sections)</code></td>
-  </tr>
-</pre>
-<h2 id="INITIALIZATION TABLE_Summary">Summary</h2>
-
-<table>
-  <tr>
-    <th align="left">Description</th>
-    <th align="right">Size</th>
-  </tr>
-  <tr>
-    <td align="left">Initialization table</td>
-    <td align="right"><code>36 bytes</code></td>
-  </tr>
-  <tr>
-    <td align="left">Source image</td>
-    <td align="right"><code>4 bytes</code></td>
-  </tr>
-  <tr>
-    <td align="left">Destination image</td>
-    <td align="right"><code>9 bytes</code></td>
-  </tr>
-  <tr>
-    <td align="left">Saving</td>
-    <td align="right"><code>-31 bytes</code></td>
-  </tr>
-</table>
-<h1 id="LINKER-CREATED VENEERS">LINKER-CREATED VENEERS</h1>
-<h2 id="LINKER-CREATED VENEERS_Arm-Arm range extension veneers">Arm-Arm range extension veneers</h2>
-
-<table>
-  <tr>
-    <th align="right">Veneer Size</th>
-    <th align="left">Target</th>
-    <th align="left">Source</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0</code></td>
-    <td align="left"><code>Total</code></td>
-    <td align="left"><code></code></td>
-  </tr>
-</table>
-<h2 id="LINKER-CREATED VENEERS_Thumb-Thumb range extension veneers">Thumb-Thumb range extension veneers</h2>
-
-<table>
-  <tr>
-    <th align="right">Veneer Size</th>
-    <th align="left">Target</th>
-    <th align="left">Source</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0</code></td>
-    <td align="left"><code>Total</code></td>
-    <td align="left"><code></code></td>
-  </tr>
-</table>
-<h2 id="LINKER-CREATED VENEERS_Arm-Thumb mode switch veneers">Arm-Thumb mode switch veneers</h2>
-
-<table>
-  <tr>
-    <th align="right">Veneer Size</th>
-    <th align="left">Target</th>
-    <th align="left">Source</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0</code></td>
-    <td align="left"><code>Total</code></td>
-    <td align="left"><code></code></td>
-  </tr>
-</table>
-<h2 id="LINKER-CREATED VENEERS_Thumb-Arm mode switch veneers">Thumb-Arm mode switch veneers</h2>
-
-<table>
-  <tr>
-    <th align="right">Veneer Size</th>
-    <th align="left">Target</th>
-    <th align="left">Source</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0</code></td>
-    <td align="left"><code>Total</code></td>
-    <td align="left"><code></code></td>
-  </tr>
-</table>
-<h2 id="LINKER-CREATED VENEERS_Summary">Summary</h2>
-
-<table>
-  <tr>
-    <th align="left">Veneer Type</th>
-    <th align="right">Size</th>
-  </tr>
-  <tr>
-    <td align="left">Thumb-Arm mode switch</td>
-    <td align="right">0</td>
-  </tr>
-  <tr>
-    <td align="left">Arm-Thumb mode switch</td>
-    <td align="right">0</td>
-  </tr>
-  <tr>
-    <td align="left">Thumb-Thumb range extension</td>
-    <td align="right">0</td>
-  </tr>
-  <tr>
-    <td align="left">Arm-Arm range extension</td>
-    <td align="right">0</td>
-  </tr>
-  <tr>
-    <td align="left">Total:</td>
-    <td align="right">0</td>
-  </tr>
-</table>
-<h1 id="SYMBOL LIST">SYMBOL LIST</h1>
-<h2 id="SYMBOL LIST_Function symbols by name">Function symbols by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="right"><code>0x3418217D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>0x34182235</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="right"><code>0x3418156F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="right"><code>0x34181561</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="right"><code>0x3418218D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="right"><code>0x34181567</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="right"><code>0x3418216D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="right"><code>0x3418217F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="right"><code>0x34182297</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="right"><code>0x34182299</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="right"><code>0x34182181</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="right"><code>0x34182293</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="right"><code>0x34182193</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="right"><code>0x3418155B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="right"><code>0x3418156D</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="right"><code>0x34182281</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="right"><code>0x3418214B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="right"><code>0x3418215F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="right"><code>0x34182161</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="right"><code>0x34182163</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="right"><code>0x34182165</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="right"><code>0x34182167</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="right"><code>0x34182169</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="right"><code>0x3418214D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="right"><code>0x3418214F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="right"><code>0x34182151</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="right"><code>0x34182153</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="right"><code>0x34182155</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="right"><code>0x34182157</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="right"><code>0x34182159</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="right"><code>0x3418215B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="right"><code>0x3418215D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="right"><code>0x34182283</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="right"><code>0x34182285</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="right"><code>0x34182287</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="right"><code>0x34182289</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="right"><code>0x3418228B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="right"><code>0x3418228D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="right"><code>0x3418228F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="right"><code>0x34182275</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="right"><code>0x34181573</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="right"><code>0x34182199</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="right"><code>0x3418219B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>0x341821C3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>0x341821D7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>0x341821D9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>0x341821DB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>0x341821DD</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>0x341821DF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>0x341821E1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>0x341821C5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>0x341821C7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>0x341821C9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>0x341821CB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>0x341821CD</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>0x341821CF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>0x341821D1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>0x341821D3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>0x341821D5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="right"><code>0x3418219F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="right"><code>0x3418219D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="right"><code>0x341816A5</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="right"><code>0x34180D8D</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="right"><code>0x34181849</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="right"><code>0x34182171</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code>0x341821A3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code>0x341821B7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code>0x341821B9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code>0x341821BB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code>0x341821BD</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code>0x341821BF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code>0x341821C1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code>0x341821A5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code>0x341821A7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code>0x341821A9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code>0x341821AB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code>0x341821AD</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code>0x341821AF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code>0x341821B1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code>0x341821B3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code>0x341821B5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="right"><code>0x34181559</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821E5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821E3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821E9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821E7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821ED</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821EB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821F1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821EF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821F5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821F3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="right"><code>0x341821F9</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="right"><code>0x341821F7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="right"><code>0x34181F83</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="right"><code>0x341821A1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="right"><code>0x34182147</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="right"><code>0x34182195</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="right"><code>0x34181563</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="right"><code>0x3418222B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="right"><code>0x3418222D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="right"><code>0x3418222F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="right"><code>0x34182231</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="right"><code>0x34182233</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="right"><code>0x3418226D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="right"><code>0x34182191</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="right"><code>0x3418218F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="right"><code>0x3418229D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="right"><code>0x3418229B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="right"><code>0x34182175</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="right"><code>0x34182177</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="right"><code>0x34182179</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="right"><code>0x3418217B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code>0x34182237</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="right"><code>0x34182239</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="right"><code>0x3418223B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="right"><code>0x3418223D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="right"><code>0x3418223F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="right"><code>0x34182241</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="right"><code>0x34182291</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="right"><code>0x3418155D</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="right"><code>0x34181555</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="right"><code>0x34182185</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="right"><code>0x34182187</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="right"><code>0x34182189</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="right"><code>0x3418218B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="right"><code>0x34182183</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="right"><code>0x3418216F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="right"><code>0x34181557</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="right"><code>0x34181571</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="right"><code>0x341813E1</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="right"><code>0x3418134D</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="right"><code>0x3418155F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="right"><code>0x34181F85</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="right"><code>0x34181EFD</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="right"><code>0x34182143</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="right"><code>0x34181EFB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="right"><code>0x34182173</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="right"><code>0x34182145</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="right"><code>0x341816A3</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Reset_Handler</code></td>
-    <td align="right"><code>0x341814C1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="right"><code>0x3418216B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="right"><code>0x34182243</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="right"><code>0x34182245</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="right"><code>0x34182247</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="right"><code>0x34182249</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="right"><code>0x34182277</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="right"><code>0x34182279</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="right"><code>0x3418224B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="right"><code>0x3418224D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="right"><code>0x3418224F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="right"><code>0x34182251</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="right"><code>0x34182253</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="right"><code>0x34182255</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="right"><code>0x34182257</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="right"><code>0x34181569</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="right"><code>0x34180BED</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="right"><code>0x34180BFD</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="right"><code>0x34181575</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="right"><code>0x34181847</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="right"><code>0x3418156B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="right"><code>0x34182219</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="right"><code>0x3418221B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="right"><code>0x3418221D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="right"><code>0x3418221F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="right"><code>0x34182221</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="right"><code>0x34182223</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="right"><code>0x34182225</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="right"><code>0x34182227</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="right"><code>0x34182229</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="right"><code>0x341821FB</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="right"><code>0x34182201</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>0x341821FF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="right"><code>0x341821FD</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="right"><code>0x34182203</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="right"><code>0x34182205</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="right"><code>0x34182207</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="right"><code>0x34182209</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="right"><code>0x3418220B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="right"><code>0x3418220D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="right"><code>0x3418220F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="right"><code>0x34182215</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code>0x34182213</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="right"><code>0x34182211</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="right"><code>0x34182217</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="right"><code>0x3418225F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="right"><code>0x34182261</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="right"><code>0x34182265</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="right"><code>0x34182267</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="right"><code>0x34182269</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="right"><code>0x3418227B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="right"><code>0x3418226B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="right"><code>0x34182259</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="right"><code>0x3418225B</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="right"><code>0x3418225D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="right"><code>0x34182263</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>0x3418227D</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code>0x3418227F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="right"><code>0x34181565</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="right"><code>0x34182197</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="right"><code>0x34182295</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="right"><code>0x34182149</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="right"><code>0x3418226F</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="right"><code>0x34182271</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="right"><code>0x34182273</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="right"><code>0x3418230F</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="right"><code>0x341822B1</code></td>
-    <td align="right"><code>26</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_done</code></td>
-    <td align="right"><code>0x341814B7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="right"><code>0x341822FD</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr4</code></td>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr8</code></td>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset</code></td>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset4</code></td>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset8</code></td>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__startup_complete</code></td>
-    <td align="right"><code>0x341814B7</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>_start</code></td>
-    <td align="right"><code>0x341814AD</code></td>
-    <td align="right"><code>14</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>exit</code></td>
-    <td align="right"><code>0x341814BB</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>main</code></td>
-    <td align="right"><code>0x3418074D</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>memset</code></td>
-    <td align="right"><code>0x341814F5</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="right"><code>0x341814C1</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Function symbols by address">Function symbols by address</h2>
-
-<table>
-  <tr>
-    <th align="right">Address</th>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418074D</code></td>
-    <td align="left"><code>main</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34180BED</code></td>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34180BFD</code></td>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34180D8D</code></td>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418134D</code></td>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341813E1</code></td>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814AD</code></td>
-    <td align="left"><code>_start</code></td>
-    <td align="right"><code>14</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814B7</code></td>
-    <td align="left"><code>__startup_complete</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814B7</code></td>
-    <td align="left"><code>__SEGGER_init_done</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814BB</code></td>
-    <td align="left"><code>exit</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814C1</code></td>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814C1</code></td>
-    <td align="left"><code>Reset_Handler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="left"><code>__aeabi_memclr8</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="left"><code>__aeabi_memclr4</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814ED</code></td>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="left"><code>__aeabi_memset8</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="left"><code>__aeabi_memset4</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814EF</code></td>
-    <td align="left"><code>__aeabi_memset</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341814F5</code></td>
-    <td align="left"><code>memset</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181555</code></td>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181557</code></td>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181559</code></td>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418155B</code></td>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418155D</code></td>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418155F</code></td>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181561</code></td>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181563</code></td>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181565</code></td>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181567</code></td>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181569</code></td>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418156B</code></td>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418156D</code></td>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418156F</code></td>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181571</code></td>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181573</code></td>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181575</code></td>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341816A3</code></td>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341816A5</code></td>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181847</code></td>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181849</code></td>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181EFB</code></td>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181EFD</code></td>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181F83</code></td>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34181F85</code></td>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182143</code></td>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182145</code></td>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182147</code></td>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182149</code></td>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418214B</code></td>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418214D</code></td>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418214F</code></td>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182151</code></td>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182153</code></td>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182155</code></td>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182157</code></td>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182159</code></td>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418215B</code></td>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418215D</code></td>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418215F</code></td>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182161</code></td>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182163</code></td>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182165</code></td>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182167</code></td>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182169</code></td>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418216B</code></td>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418216D</code></td>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418216F</code></td>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182171</code></td>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182173</code></td>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182175</code></td>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182177</code></td>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182179</code></td>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418217B</code></td>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418217D</code></td>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418217F</code></td>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182181</code></td>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182183</code></td>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182185</code></td>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182187</code></td>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182189</code></td>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418218B</code></td>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418218D</code></td>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418218F</code></td>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182191</code></td>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182193</code></td>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182195</code></td>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182197</code></td>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182199</code></td>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418219B</code></td>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418219D</code></td>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418219F</code></td>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821A1</code></td>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821A3</code></td>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821A5</code></td>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821A7</code></td>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821A9</code></td>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821AB</code></td>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821AD</code></td>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821AF</code></td>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821B1</code></td>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821B3</code></td>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821B5</code></td>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821B7</code></td>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821B9</code></td>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821BB</code></td>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821BD</code></td>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821BF</code></td>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821C1</code></td>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821C3</code></td>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821C5</code></td>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821C7</code></td>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821C9</code></td>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821CB</code></td>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821CD</code></td>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821CF</code></td>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821D1</code></td>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821D3</code></td>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821D5</code></td>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821D7</code></td>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821D9</code></td>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821DB</code></td>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821DD</code></td>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821DF</code></td>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821E1</code></td>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821E3</code></td>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821E5</code></td>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821E7</code></td>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821E9</code></td>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821EB</code></td>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821ED</code></td>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821EF</code></td>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821F1</code></td>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821F3</code></td>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821F5</code></td>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821F7</code></td>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821F9</code></td>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821FB</code></td>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821FD</code></td>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341821FF</code></td>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182201</code></td>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182203</code></td>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182205</code></td>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182207</code></td>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182209</code></td>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418220B</code></td>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418220D</code></td>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418220F</code></td>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182211</code></td>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182213</code></td>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182215</code></td>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182217</code></td>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182219</code></td>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418221B</code></td>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418221D</code></td>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418221F</code></td>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182221</code></td>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182223</code></td>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182225</code></td>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182227</code></td>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182229</code></td>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418222B</code></td>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418222D</code></td>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418222F</code></td>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182231</code></td>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182233</code></td>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182235</code></td>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182237</code></td>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182239</code></td>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418223B</code></td>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418223D</code></td>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418223F</code></td>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182241</code></td>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182243</code></td>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182245</code></td>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182247</code></td>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182249</code></td>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418224B</code></td>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418224D</code></td>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418224F</code></td>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182251</code></td>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182253</code></td>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182255</code></td>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182257</code></td>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182259</code></td>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418225B</code></td>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418225D</code></td>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418225F</code></td>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182261</code></td>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182263</code></td>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182265</code></td>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182267</code></td>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182269</code></td>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418226B</code></td>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418226D</code></td>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418226F</code></td>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182271</code></td>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182273</code></td>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182275</code></td>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182277</code></td>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182279</code></td>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418227B</code></td>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418227D</code></td>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418227F</code></td>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182281</code></td>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182283</code></td>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182285</code></td>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182287</code></td>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182289</code></td>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418228B</code></td>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418228D</code></td>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418228F</code></td>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182291</code></td>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182293</code></td>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182295</code></td>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182297</code></td>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34182299</code></td>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418229B</code></td>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418229D</code></td>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822B1</code></td>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="right"><code>26</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822FD</code></td>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3418230F</code></td>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Function symbols by descending size">Function symbols by descending size</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_OscConfig</code></td>
-    <td align="right"><code>1 714</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_RCC_ClockConfig</code></td>
-    <td align="right"><code>1 472</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>main</code></td>
-    <td align="right"><code>1 184</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_Config</code></td>
-    <td align="right"><code>446</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HAL_GPIO_Init</code></td>
-    <td align="right"><code>418</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClockUpdate</code></td>
-    <td align="right"><code>400</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemInit</code></td>
-    <td align="right"><code>302</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IC_CheckPLLSources</code></td>
-    <td align="right"><code>148</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_PLL_IsNewConfig</code></td>
-    <td align="right"><code>134</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCCEx_GetPLLSourceFreq</code></td>
-    <td align="right"><code>128</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr</code></td>
-    <td align="right"><code>104</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_ctors</code></td>
-    <td align="right"><code>26</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_copy</code></td>
-    <td align="right"><code>20</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_zero</code></td>
-    <td align="right"><code>18</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SysTick_Handler</code></td>
-    <td align="right"><code>16</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>_start</code></td>
-    <td align="right"><code>14</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BusFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DebugMon_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HardFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MemManage_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NMI_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PendSV_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SVC_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UsageFault_Handler</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>exit</code></td>
-    <td align="right"><code>2</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADC1_2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ADF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BCK_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHEAXI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CACHE_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CRYP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CSI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>CTI_INT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMIPP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DCMI_PSSI_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DMA2D_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DTS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ETH1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>EXTI9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN1_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN2_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN3_IT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FDCAN_CU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FMC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FPU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXMMU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GFXTIM_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>GPU2D_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HASH_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>HPDMA1_Channel9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C1_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C2_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C3_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I2C4_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C1_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_ER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>I3C2_EV_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IAC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ICACHE_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>IWDG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>JPEG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LOCKUP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPTIM5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LPUART1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_LO_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>LTDC_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MCE4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDF1_FLT5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>MDIOS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU0_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>NPU3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PAHB_ERR_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PKA_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>PVD_PVM_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RCC_S_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RIFSC_TAMPER_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RNG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RTC_S_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>Reset_Handler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAES_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_A_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI1_B_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_A_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SAI2_B_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SDMMC2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPDIFRX_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>SPI6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TAMP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TCM_ECC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM11_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM12_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM13_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM14_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM15_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM16_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM17_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM18_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_BRK_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_CC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM1_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_BRK_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_CC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_TRG_CCU_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM8_UP_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>TIM9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART4_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART5_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART7_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART8_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UART9_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>UCPD1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART10_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USART6_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB1_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>USB2_OTG_HS_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>VENC_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WAKEUP_PIN_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>WWDG_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI1_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI2_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>XSPI3_IRQHandler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>2</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_done</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr4</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memclr8</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset4</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__aeabi_memset8</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__startup_complete</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>SEGGER_THUMB_Startup.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>memset</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Wk</code></td>
-    <td align="left"><code>strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>reset_handler</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>STM32N6xx_Startup.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Read-write data symbols by name">Read-write data symbols by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="right"><code>0x341822AC</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Init</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTick</code></td>
-    <td align="right"><code>0x341822A4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="right"><code>0x341822A8</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Read-write data symbols by address">Read-write data symbols by address</h2>
-
-<table>
-  <tr>
-    <th align="right">Address</th>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822A4</code></td>
-    <td align="left"><code>uwTick</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822A8</code></td>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822AC</code></td>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Init</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Read-write data symbols by descending size">Read-write data symbols by descending size</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>SystemCoreClock</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Init</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTick</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>uwTickPrio</code></td>
-    <td align="right"><code>1</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Zero</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>blto2_FSBL_lto.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Read-only data symbols by name">Read-only data symbols by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Address</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_data__</code></td>
-    <td align="right"><code>0x341822F8</code></td>
-    <td align="right"><code>[4]</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__SEGGER_init_table__</code></td>
-    <td align="right"><code>0x341822D4</code></td>
-    <td align="right"><code>[36]</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Read-only data symbols by address">Read-only data symbols by address</h2>
-
-<table>
-  <tr>
-    <th align="right">Address</th>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822D4</code></td>
-    <td align="left"><code>__SEGGER_init_table__</code></td>
-    <td align="right"><code>[36]</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x341822F8</code></td>
-    <td align="left"><code>__SEGGER_init_data__</code></td>
-    <td align="right"><code>[4]</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Cnst</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Untyped symbols by name">Untyped symbols by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Symbol name</th>
-    <th align="right">Value</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
-    <td align="right"><code>0x38004000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_size__</code></td>
-    <td align="right"><code>0x00004000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x00070000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-  <tr>
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-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
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-    <td align="right"><code>0x00020000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
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-    <td align="right"><code>0x34400000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
-    <td align="right"><code>0x34400000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
-    <td align="right"><code>0x3C002000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_size__</code></td>
-    <td align="right"><code>0x00002000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_end__</code></td>
-    <td align="right"><code>0x30020000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_size__</code></td>
-    <td align="right"><code>0x00020000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_start__</code></td>
-    <td align="right"><code>0x30000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_used_end__</code></td>
-    <td align="right"><code>0x30000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__DTCM_RAM_segment_used_start__</code></td>
-    <td align="right"><code>0x30000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_end__</code></td>
-    <td align="right"><code>0x34064000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_size__</code></td>
-    <td align="right"><code>0x00064000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_start__</code></td>
-    <td align="right"><code>0x34000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_used_end__</code></td>
-    <td align="right"><code>0x34000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__FLEX_RAM_segment_used_start__</code></td>
-    <td align="right"><code>0x34000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__HEAPSIZE__</code></td>
-    <td align="right"><code>0x00000100</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_end__</code></td>
-    <td align="right"><code>0x10010000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_size__</code></td>
-    <td align="right"><code>0x00010000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_start__</code></td>
-    <td align="right"><code>0x10000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_used_end__</code></td>
-    <td align="right"><code>0x10000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ITCM_RAM_segment_used_start__</code></td>
-    <td align="right"><code>0x10000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_end__</code></td>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_size__</code></td>
-    <td align="right"><code>0x0007FC00</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_start__</code></td>
-    <td align="right"><code>0x34180400</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_used_end__</code></td>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_used_size__</code></td>
-    <td align="right"><code>0x0007FC00</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__RAM_segment_used_start__</code></td>
-    <td align="right"><code>0x34180400</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__STACKSIZE__</code></td>
-    <td align="right"><code>0x00002000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ctors_end__</code></td>
-    <td align="right"><code>0x341822A4</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__ctors_start__</code></td>
-    <td align="right"><code>0x341822A0</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__stack_end__</code></td>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__stack_start__</code></td>
-    <td align="right"><code>0x341FE000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>__thread_pointer$</code></td>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>_vectors</code></td>
-    <td align="right"><code>0x34180400</code></td>
-    <td align="right"><code>[844]</code></td>
-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>_vectors_end</code></td>
-    <td align="right"><code>0x3418074C</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Lc</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>g_pfnVectors</code></td>
-    <td align="right"><code>0x34180400</code></td>
-    <td align="right"><code>[844]</code></td>
-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>stm32n657xx_Vectors.o</code></td>
-  </tr>
-</table>
-<h2 id="SYMBOL LIST_Untyped symbols by address">Untyped symbols by address</h2>
-
-<table>
-  <tr>
-    <th align="right">Value</th>
-    <th align="left">Symbol name</th>
-    <th align="right">Size</th>
-    <th align="right">Align</th>
-    <th align="left">Type</th>
-    <th align="left">Bd</th>
-    <th align="left">Object File</th>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__thread_pointer$</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__STACKSIZE_PROCESS__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__ITCM_RAM_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__FLEX_RAM_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__DTCM_RAM_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__BKP_RAM_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__AXI_RAM8_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__AXI_RAM7_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__AXI_RAM6_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x00000000</code></td>
-    <td align="left"><code>__AXI_RAM5_segment_used_size__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
-    <td align="right"><code>0x00000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x00000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x00000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x00070000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x0007FC00</code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x0007FC00</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x0009C000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x10000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x10000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x10000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x10010000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x30000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x30000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>0x30000000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34000000</code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34064000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34064000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34100000</code></td>
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-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
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-    <td align="right"><code>1024</code></td>
-    <td align="left"><code>Code</code></td>
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-    <td align="right"><code>0x34180400</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
-    <td align="right"><code>0x34180400</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34180400</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34180400</code></td>
-    <td align="left"><code>__AXI_RAM2_segment_start__</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="right"><code>1024</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x341822A4</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x341FE000</code></td>
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-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__stack_end__</code></td>
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-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__RAM_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
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-    <td align="left"><code>[ Linker created ]</code></td>
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-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__RAM_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__AXI_RAM3_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__AXI_RAM3_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__AXI_RAM3_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__AXI_RAM2_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34200000</code></td>
-    <td align="left"><code>__AXI_RAM2_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34270000</code></td>
-    <td align="left"><code>__AXI_RAM4_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34270000</code></td>
-    <td align="left"><code>__AXI_RAM4_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34270000</code></td>
-    <td align="left"><code>__AXI_RAM4_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34270000</code></td>
-    <td align="left"><code>__AXI_RAM3_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x342E0000</code></td>
-    <td align="left"><code>__AXI_RAM5_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x342E0000</code></td>
-    <td align="left"><code>__AXI_RAM5_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x342E0000</code></td>
-    <td align="left"><code>__AXI_RAM5_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x342E0000</code></td>
-    <td align="left"><code>__AXI_RAM4_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34350000</code></td>
-    <td align="left"><code>__AXI_RAM6_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34350000</code></td>
-    <td align="left"><code>__AXI_RAM6_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34350000</code></td>
-    <td align="left"><code>__AXI_RAM6_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34350000</code></td>
-    <td align="left"><code>__AXI_RAM5_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x343C0000</code></td>
-    <td align="left"><code>__AXI_RAM7_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x343C0000</code></td>
-    <td align="left"><code>__AXI_RAM7_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x343C0000</code></td>
-    <td align="left"><code>__AXI_RAM7_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x343C0000</code></td>
-    <td align="left"><code>__AXI_RAM6_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34400000</code></td>
-    <td align="left"><code>__AXI_RAM8_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34400000</code></td>
-    <td align="left"><code>__AXI_RAM8_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34400000</code></td>
-    <td align="left"><code>__AXI_RAM8_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34400000</code></td>
-    <td align="left"><code>__AXI_RAM7_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x34420000</code></td>
-    <td align="left"><code>__AXI_RAM8_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="left"><code>__AHB_RAM1_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="left"><code>__AHB_RAM1_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38000000</code></td>
-    <td align="left"><code>__AHB_RAM1_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38004000</code></td>
-    <td align="left"><code>__AHB_RAM2_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38004000</code></td>
-    <td align="left"><code>__AHB_RAM2_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38004000</code></td>
-    <td align="left"><code>__AHB_RAM2_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38004000</code></td>
-    <td align="left"><code>__AHB_RAM1_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x38008000</code></td>
-    <td align="left"><code>__AHB_RAM2_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="left"><code>__BKP_RAM_segment_used_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="left"><code>__BKP_RAM_segment_used_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3C000000</code></td>
-    <td align="left"><code>__BKP_RAM_segment_start__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-  <tr>
-    <td align="right"><code>0x3C002000</code></td>
-    <td align="left"><code>__BKP_RAM_segment_end__</code></td>
-    <td align="right"><code></code></td>
-    <td align="right"><code></code></td>
-    <td align="left"><code>----</code></td>
-    <td align="left"><code>Gb</code></td>
-    <td align="left"><code>[ Linker created ]</code></td>
-  </tr>
-</table>
-<h1 id="REGION LIST">REGION LIST</h1>
-<h2 id="REGION LIST_Regions by name">Regions by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Name</th>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-  </tr>
-  <tr>
-    <td align="left"><code>AHB_RAM1</code></td>
-    <td align="left"><code>38000000-38003FFF</code></td>
-    <td align="right"><code>16 384</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AHB_RAM2</code></td>
-    <td align="left"><code>38004000-38007FFF</code></td>
-    <td align="right"><code>16 384</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM1</code></td>
-    <td align="left"><code>34064000-340FFFFF</code></td>
-    <td align="right"><code>638 976</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM2</code></td>
-    <td align="left"><code>34180400-341FFFFF</code></td>
-    <td align="right"><code>523 264</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM3</code></td>
-    <td align="left"><code>34200000-3426FFFF</code></td>
-    <td align="right"><code>458 752</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM4</code></td>
-    <td align="left"><code>34270000-342DFFFF</code></td>
-    <td align="right"><code>458 752</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM5</code></td>
-    <td align="left"><code>342E0000-3434FFFF</code></td>
-    <td align="right"><code>458 752</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM6</code></td>
-    <td align="left"><code>34350000-343BFFFF</code></td>
-    <td align="right"><code>458 752</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM7</code></td>
-    <td align="left"><code>343C0000-343FFFFF</code></td>
-    <td align="right"><code>262 144</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM8</code></td>
-    <td align="left"><code>34400000-3441FFFF</code></td>
-    <td align="right"><code>131 072</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>BKP_RAM</code></td>
-    <td align="left"><code>3C000000-3C001FFF</code></td>
-    <td align="right"><code>8 192</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>DTCM_RAM</code></td>
-    <td align="left"><code>30000000-3001FFFF</code></td>
-    <td align="right"><code>131 072</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>FLEX_RAM</code></td>
-    <td align="left"><code>34000000-34063FFF</code></td>
-    <td align="right"><code>409 600</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>ITCM_RAM</code></td>
-    <td align="left"><code>10000000-1000FFFF</code></td>
-    <td align="right"><code>65 536</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>RAM</code></td>
-    <td align="left"><code>34180400-341FFFFF</code></td>
-    <td align="right"><code>523 264</code></td>
-  </tr>
-</table>
-<h2 id="REGION LIST_Analysis">Analysis</h2>
-
-AXI_RAM2:
-  Identical to region RAM
-
-RAM:
-  Identical to region AXI_RAM2
-<h1 id="BLOCK LIST">BLOCK LIST</h1>
-<h2 id="BLOCK LIST_Blocks by name">Blocks by name</h2>
-
-<table>
-  <tr>
-    <th align="left">Name</th>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="left">Ordering</th>
-  </tr>
-  <tr>
-    <td align="left"><code>ctors</code></td>
-    <td align="left"><code>341822A0-341822A3</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>Auto</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>stack</code></td>
-    <td align="left"><code>341FE000-341FFFFF</code></td>
-    <td align="right"><code>8 192</code></td>
-    <td align="left"><code>Auto</code></td>
-  </tr>
-</table>
-<h2 id="BLOCK LIST_Blocks by address">Blocks by address</h2>
-
-<table>
-  <tr>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="left">Name</th>
-    <th align="left">Ordering</th>
-  </tr>
-  <tr>
-    <td align="left"><code>341822A0-341822A3</code></td>
-    <td align="right"><code>4</code></td>
-    <td align="left"><code>ctors</code></td>
-    <td align="left"><code>Auto</code></td>
-  </tr>
-  <tr>
-    <td align="left"><code>341FE000-341FFFFF</code></td>
-    <td align="right"><code>8 192</code></td>
-    <td align="left"><code>stack</code></td>
-    <td align="left"><code>Auto</code></td>
-  </tr>
-</table>
-<h1 id="STACK SIZES">STACK SIZES</h1>
-<h2 id="STACK SIZES_Functions by stack size">Functions by stack size</h2>
-
-<table>
-  <tr>
-    <th align="left">Function name</th>
-    <th align="right">Stack</th>
-    <th align="left">Object File</th>
-  </tr>
-</table>
-<h2 id="STACK SIZES_Functions without stack size information">Functions without stack size information</h2>
-
-  HAL_RCC_OscConfig
-  HAL_RCC_ClockConfig
-  HAL_GPIO_Init
-  RCC_PLL_IsNewConfig
-  RCC_PLL_Config
-  RCC_IC_CheckPLLSources
-  RCCEx_GetPLLSourceFreq
-  main
-  SystemCoreClockUpdate
-  NMI_Handler
-  HardFault_Handler
-  MemManage_Handler
-  BusFault_Handler
-  UsageFault_Handler
-  SVC_Handler
-  DebugMon_Handler
-  PendSV_Handler
-  SysTick_Handler
-  SystemInit
-  _start
-  __SEGGER_init_done
-  __startup_complete
-  exit
-  PVD_PVM_IRQHandler
-  DTS_IRQHandler
-  RCC_IRQHandler
-  LOCKUP_IRQHandler
-  CACHE_ECC_IRQHandler
-  TCM_ECC_IRQHandler
-  BCK_ECC_IRQHandler
-  FPU_IRQHandler
-  RTC_S_IRQHandler
-  TAMP_IRQHandler
-  RIFSC_TAMPER_IRQHandler
-  IAC_IRQHandler
-  RCC_S_IRQHandler
-  RTC_IRQHandler
-  IWDG_IRQHandler
-  WWDG_IRQHandler
-  EXTI0_IRQHandler
-  EXTI1_IRQHandler
-  EXTI2_IRQHandler
-  EXTI3_IRQHandler
-  EXTI4_IRQHandler
-  EXTI5_IRQHandler
-  EXTI6_IRQHandler
-  EXTI7_IRQHandler
-  EXTI8_IRQHandler
-  EXTI9_IRQHandler
-  EXTI10_IRQHandler
-  EXTI11_IRQHandler
-  EXTI12_IRQHandler
-  EXTI13_IRQHandler
-  EXTI14_IRQHandler
-  EXTI15_IRQHandler
-  SAES_IRQHandler
-  CRYP_IRQHandler
-  PKA_IRQHandler
-  HASH_IRQHandler
-  RNG_IRQHandler
-  MCE1_IRQHandler
-  MCE2_IRQHandler
-  MCE3_IRQHandler
-  MCE4_IRQHandler
-  ADC1_2_IRQHandler
-  CSI_IRQHandler
-  DCMIPP_IRQHandler
-  PAHB_ERR_IRQHandler
-  NPU0_IRQHandler
-  NPU1_IRQHandler
-  NPU2_IRQHandler
-  NPU3_IRQHandler
-  CACHEAXI_IRQHandler
-  LTDC_LO_IRQHandler
-  LTDC_LO_ERR_IRQHandler
-  DMA2D_IRQHandler
-  JPEG_IRQHandler
-  VENC_IRQHandler
-  GFXMMU_IRQHandler
-  GFXTIM_IRQHandler
-  GPU2D_IRQHandler
-  GPU2D_ER_IRQHandler
-  ICACHE_IRQHandler
-  HPDMA1_Channel0_IRQHandler
-  HPDMA1_Channel1_IRQHandler
-  HPDMA1_Channel2_IRQHandler
-  HPDMA1_Channel3_IRQHandler
-  HPDMA1_Channel4_IRQHandler
-  HPDMA1_Channel5_IRQHandler
-  HPDMA1_Channel6_IRQHandler
-  HPDMA1_Channel7_IRQHandler
-  HPDMA1_Channel8_IRQHandler
-  HPDMA1_Channel9_IRQHandler
-  HPDMA1_Channel10_IRQHandler
-  HPDMA1_Channel11_IRQHandler
-  HPDMA1_Channel12_IRQHandler
-  HPDMA1_Channel13_IRQHandler
-  HPDMA1_Channel14_IRQHandler
-  HPDMA1_Channel15_IRQHandler
-  GPDMA1_Channel0_IRQHandler
-  GPDMA1_Channel1_IRQHandler
-  GPDMA1_Channel2_IRQHandler
-  GPDMA1_Channel3_IRQHandler
-  GPDMA1_Channel4_IRQHandler
-  GPDMA1_Channel5_IRQHandler
-  GPDMA1_Channel6_IRQHandler
-  GPDMA1_Channel7_IRQHandler
-  GPDMA1_Channel8_IRQHandler
-  GPDMA1_Channel9_IRQHandler
-  GPDMA1_Channel10_IRQHandler
-  GPDMA1_Channel11_IRQHandler
-  GPDMA1_Channel12_IRQHandler
-  GPDMA1_Channel13_IRQHandler
-  GPDMA1_Channel14_IRQHandler
-  GPDMA1_Channel15_IRQHandler
-  I2C1_EV_IRQHandler
-  I2C1_ER_IRQHandler
-  I2C2_EV_IRQHandler
-  I2C2_ER_IRQHandler
-  I2C3_EV_IRQHandler
-  I2C3_ER_IRQHandler
-  I2C4_EV_IRQHandler
-  I2C4_ER_IRQHandler
-  I3C1_EV_IRQHandler
-  I3C1_ER_IRQHandler
-  I3C2_EV_IRQHandler
-  I3C2_ER_IRQHandler
-  TIM1_BRK_IRQHandler
-  TIM1_UP_IRQHandler
-  TIM1_TRG_CCU_IRQHandler
-  TIM1_CC_IRQHandler
-  TIM2_IRQHandler
-  TIM3_IRQHandler
-  TIM4_IRQHandler
-  TIM5_IRQHandler
-  TIM6_IRQHandler
-  TIM7_IRQHandler
-  TIM8_BRK_IRQHandler
-  TIM8_UP_IRQHandler
-  TIM8_TRG_CCU_IRQHandler
-  TIM8_CC_IRQHandler
-  TIM9_IRQHandler
-  TIM10_IRQHandler
-  TIM11_IRQHandler
-  TIM12_IRQHandler
-  TIM13_IRQHandler
-  TIM14_IRQHandler
-  TIM15_IRQHandler
-  TIM16_IRQHandler
-  TIM17_IRQHandler
-  TIM18_IRQHandler
-  LPTIM1_IRQHandler
-  LPTIM2_IRQHandler
-  LPTIM3_IRQHandler
-  LPTIM4_IRQHandler
-  LPTIM5_IRQHandler
-  ADF1_FLT0_IRQHandler
-  MDF1_FLT0_IRQHandler
-  MDF1_FLT1_IRQHandler
-  MDF1_FLT2_IRQHandler
-  MDF1_FLT3_IRQHandler
-  MDF1_FLT4_IRQHandler
-  MDF1_FLT5_IRQHandler
-  SAI1_A_IRQHandler
-  SAI1_B_IRQHandler
-  SAI2_A_IRQHandler
-  SAI2_B_IRQHandler
-  SPDIFRX_IRQHandler
-  SPI1_IRQHandler
-  SPI2_IRQHandler
-  SPI3_IRQHandler
-  SPI4_IRQHandler
-  SPI5_IRQHandler
-  SPI6_IRQHandler
-  USART1_IRQHandler
-  USART2_IRQHandler
-  USART3_IRQHandler
-  UART4_IRQHandler
-  UART5_IRQHandler
-  USART6_IRQHandler
-  UART7_IRQHandler
-  UART8_IRQHandler
-  UART9_IRQHandler
-  USART10_IRQHandler
-  LPUART1_IRQHandler
-  XSPI1_IRQHandler
-  XSPI2_IRQHandler
-  XSPI3_IRQHandler
-  FMC_IRQHandler
-  SDMMC1_IRQHandler
-  SDMMC2_IRQHandler
-  UCPD1_IRQHandler
-  USB1_OTG_HS_IRQHandler
-  USB2_OTG_HS_IRQHandler
-  ETH1_IRQHandler
-  FDCAN1_IT0_IRQHandler
-  FDCAN1_IT1_IRQHandler
-  FDCAN2_IT0_IRQHandler
-  FDCAN2_IT1_IRQHandler
-  FDCAN3_IT0_IRQHandler
-  FDCAN3_IT1_IRQHandler
-  FDCAN_CU_IRQHandler
-  MDIOS_IRQHandler
-  DCMI_PSSI_IRQHandler
-  WAKEUP_PIN_IRQHandler
-  CTI_INT0_IRQHandler
-  CTI_INT1_IRQHandler
-  LTDC_UP_IRQHandler
-  LTDC_UP_ERR_IRQHandler
-  reset_handler
-  Reset_Handler
-  __SEGGER_init_zero
-  __SEGGER_init_copy
-  __SEGGER_init_ctors
-  __aeabi_memclr
-  __aeabi_memclr8
-  __aeabi_memclr4
-  __aeabi_memset8
-  __aeabi_memset4
-  __aeabi_memset
-  memset
-<h1 id="UNUSED INPUTS">UNUSED INPUTS</h1>
-<h2 id="UNUSED INPUTS_Unused object files">Unused object files</h2>
-
-No unused object files
-<h1 id="ABSOLUTE LISTING">ABSOLUTE LISTING</h1>
-<h2 id="ABSOLUTE LISTING_Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024">Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024</h2>
-
-<pre>
-<br/><span id="_vectors">_vectors:</span>
-<span id="g_pfnVectors">g_pfnVectors:</span>
-<span id="A34180400">  0x34180400:  </span>34200000     DC.W       34200000               ; R_ARM_ABS32
-<span id="A34180404">  0x34180404:  </span>341814C1     DC.W       <a href="#reset_handler">reset_handler</a>
-<span id="A34180408">  0x34180408:  </span>34181555     DC.W       <a href="#NMI_Handler">NMI_Handler</a>
-<span id="A3418040C">  0x3418040C:  </span>34181559     DC.W       <a href="#HardFault_Handler">HardFault_Handler</a>
-<span id="A34180410">  0x34180410:  </span>3418155D     DC.W       <a href="#MemManage_Handler">MemManage_Handler</a>
-<span id="A34180414">  0x34180414:  </span>34181561     DC.W       <a href="#BusFault_Handler">BusFault_Handler</a>
-<span id="A34180418">  0x34180418:  </span>34181565     DC.W       <a href="#UsageFault_Handler">UsageFault_Handler</a>
-<span id="A3418041C">  0x3418041C:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418041D">  0x3418041D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418041E">  0x3418041E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418041F">  0x3418041F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180420">  0x34180420:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180421">  0x34180421:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180422">  0x34180422:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180423">  0x34180423:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180424">  0x34180424:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180425">  0x34180425:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180426">  0x34180426:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180427">  0x34180427:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180428">  0x34180428:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180429">  0x34180429:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418042A">  0x3418042A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418042B">  0x3418042B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418042C">  0x3418042C:  </span>34181569     DC.W       <a href="#SVC_Handler">SVC_Handler</a>
-<span id="A34180430">  0x34180430:  </span>3418156D     DC.W       <a href="#DebugMon_Handler">DebugMon_Handler</a>
-<span id="A34180434">  0x34180434:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180435">  0x34180435:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180436">  0x34180436:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180437">  0x34180437:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180438">  0x34180438:  </span>34181571     DC.W       <a href="#PendSV_Handler">PendSV_Handler</a>
-<span id="A3418043C">  0x3418043C:  </span>34180BED     DC.W       <a href="#SysTick_Handler">SysTick_Handler</a>
-<span id="A34180440">  0x34180440:  </span>34181557     DC.W       <a href="#PVD_PVM_IRQHandler">PVD_PVM_IRQHandler</a>
-<span id="A34180444">  0x34180444:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180445">  0x34180445:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180446">  0x34180446:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180447">  0x34180447:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180448">  0x34180448:  </span>3418155B     DC.W       <a href="#DTS_IRQHandler">DTS_IRQHandler</a>
-<span id="A3418044C">  0x3418044C:  </span>3418155F     DC.W       <a href="#RCC_IRQHandler">RCC_IRQHandler</a>
-<span id="A34180450">  0x34180450:  </span>34181563     DC.W       <a href="#LOCKUP_IRQHandler">LOCKUP_IRQHandler</a>
-<span id="A34180454">  0x34180454:  </span>34181567     DC.W       <a href="#CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler</a>
-<span id="A34180458">  0x34180458:  </span>3418156B     DC.W       <a href="#TCM_ECC_IRQHandler">TCM_ECC_IRQHandler</a>
-<span id="A3418045C">  0x3418045C:  </span>3418156F     DC.W       <a href="#BCK_ECC_IRQHandler">BCK_ECC_IRQHandler</a>
-<span id="A34180460">  0x34180460:  </span>34181573     DC.W       <a href="#FPU_IRQHandler">FPU_IRQHandler</a>
-<span id="A34180464">  0x34180464:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180465">  0x34180465:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180466">  0x34180466:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180467">  0x34180467:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180468">  0x34180468:  </span>341816A3     DC.W       <a href="#RTC_S_IRQHandler">RTC_S_IRQHandler</a>
-<span id="A3418046C">  0x3418046C:  </span>34181847     DC.W       <a href="#TAMP_IRQHandler">TAMP_IRQHandler</a>
-<span id="A34180470">  0x34180470:  </span>34181EFB     DC.W       <a href="#RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler</a>
-<span id="A34180474">  0x34180474:  </span>34181F83     DC.W       <a href="#IAC_IRQHandler">IAC_IRQHandler</a>
-<span id="A34180478">  0x34180478:  </span>34182143     DC.W       <a href="#RCC_S_IRQHandler">RCC_S_IRQHandler</a>
-<span id="A3418047C">  0x3418047C:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418047D">  0x3418047D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418047E">  0x3418047E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418047F">  0x3418047F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180480">  0x34180480:  </span>34182145     DC.W       <a href="#RTC_IRQHandler">RTC_IRQHandler</a>
-<span id="A34180484">  0x34180484:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180485">  0x34180485:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180486">  0x34180486:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180487">  0x34180487:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180488">  0x34180488:  </span>34182147     DC.W       <a href="#IWDG_IRQHandler">IWDG_IRQHandler</a>
-<span id="A3418048C">  0x3418048C:  </span>34182149     DC.W       <a href="#WWDG_IRQHandler">WWDG_IRQHandler</a>
-<span id="A34180490">  0x34180490:  </span>3418214B     DC.W       <a href="#EXTI0_IRQHandler">EXTI0_IRQHandler</a>
-<span id="A34180494">  0x34180494:  </span>3418214D     DC.W       <a href="#EXTI1_IRQHandler">EXTI1_IRQHandler</a>
-<span id="A34180498">  0x34180498:  </span>3418214F     DC.W       <a href="#EXTI2_IRQHandler">EXTI2_IRQHandler</a>
-<span id="A3418049C">  0x3418049C:  </span>34182151     DC.W       <a href="#EXTI3_IRQHandler">EXTI3_IRQHandler</a>
-<span id="A341804A0">  0x341804A0:  </span>34182153     DC.W       <a href="#EXTI4_IRQHandler">EXTI4_IRQHandler</a>
-<span id="A341804A4">  0x341804A4:  </span>34182155     DC.W       <a href="#EXTI5_IRQHandler">EXTI5_IRQHandler</a>
-<span id="A341804A8">  0x341804A8:  </span>34182157     DC.W       <a href="#EXTI6_IRQHandler">EXTI6_IRQHandler</a>
-<span id="A341804AC">  0x341804AC:  </span>34182159     DC.W       <a href="#EXTI7_IRQHandler">EXTI7_IRQHandler</a>
-<span id="A341804B0">  0x341804B0:  </span>3418215B     DC.W       <a href="#EXTI8_IRQHandler">EXTI8_IRQHandler</a>
-<span id="A341804B4">  0x341804B4:  </span>3418215D     DC.W       <a href="#EXTI9_IRQHandler">EXTI9_IRQHandler</a>
-<span id="A341804B8">  0x341804B8:  </span>3418215F     DC.W       <a href="#EXTI10_IRQHandler">EXTI10_IRQHandler</a>
-<span id="A341804BC">  0x341804BC:  </span>34182161     DC.W       <a href="#EXTI11_IRQHandler">EXTI11_IRQHandler</a>
-<span id="A341804C0">  0x341804C0:  </span>34182163     DC.W       <a href="#EXTI12_IRQHandler">EXTI12_IRQHandler</a>
-<span id="A341804C4">  0x341804C4:  </span>34182165     DC.W       <a href="#EXTI13_IRQHandler">EXTI13_IRQHandler</a>
-<span id="A341804C8">  0x341804C8:  </span>34182167     DC.W       <a href="#EXTI14_IRQHandler">EXTI14_IRQHandler</a>
-<span id="A341804CC">  0x341804CC:  </span>34182169     DC.W       <a href="#EXTI15_IRQHandler">EXTI15_IRQHandler</a>
-<span id="A341804D0">  0x341804D0:  </span>3418216B     DC.W       <a href="#SAES_IRQHandler">SAES_IRQHandler</a>
-<span id="A341804D4">  0x341804D4:  </span>3418216D     DC.W       <a href="#CRYP_IRQHandler">CRYP_IRQHandler</a>
-<span id="A341804D8">  0x341804D8:  </span>3418216F     DC.W       <a href="#PKA_IRQHandler">PKA_IRQHandler</a>
-<span id="A341804DC">  0x341804DC:  </span>34182171     DC.W       <a href="#HASH_IRQHandler">HASH_IRQHandler</a>
-<span id="A341804E0">  0x341804E0:  </span>34182173     DC.W       <a href="#RNG_IRQHandler">RNG_IRQHandler</a>
-<span id="A341804E4">  0x341804E4:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341804E5">  0x341804E5:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341804E6">  0x341804E6:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341804E7">  0x341804E7:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341804E8">  0x341804E8:  </span>34182175     DC.W       <a href="#MCE1_IRQHandler">MCE1_IRQHandler</a>
-<span id="A341804EC">  0x341804EC:  </span>34182177     DC.W       <a href="#MCE2_IRQHandler">MCE2_IRQHandler</a>
-<span id="A341804F0">  0x341804F0:  </span>34182179     DC.W       <a href="#MCE3_IRQHandler">MCE3_IRQHandler</a>
-<span id="A341804F4">  0x341804F4:  </span>3418217B     DC.W       <a href="#MCE4_IRQHandler">MCE4_IRQHandler</a>
-<span id="A341804F8">  0x341804F8:  </span>3418217D     DC.W       <a href="#ADC1_2_IRQHandler">ADC1_2_IRQHandler</a>
-<span id="A341804FC">  0x341804FC:  </span>3418217F     DC.W       <a href="#CSI_IRQHandler">CSI_IRQHandler</a>
-<span id="A34180500">  0x34180500:  </span>34182181     DC.W       <a href="#DCMIPP_IRQHandler">DCMIPP_IRQHandler</a>
-<span id="A34180504">  0x34180504:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180505">  0x34180505:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180506">  0x34180506:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180507">  0x34180507:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180508">  0x34180508:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180509">  0x34180509:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050A">  0x3418050A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050B">  0x3418050B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050C">  0x3418050C:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050D">  0x3418050D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050E">  0x3418050E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418050F">  0x3418050F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180510">  0x34180510:  </span>34182183     DC.W       <a href="#PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler</a>
-<span id="A34180514">  0x34180514:  </span>34182185     DC.W       <a href="#NPU0_IRQHandler">NPU0_IRQHandler</a>
-<span id="A34180518">  0x34180518:  </span>34182187     DC.W       <a href="#NPU1_IRQHandler">NPU1_IRQHandler</a>
-<span id="A3418051C">  0x3418051C:  </span>34182189     DC.W       <a href="#NPU2_IRQHandler">NPU2_IRQHandler</a>
-<span id="A34180520">  0x34180520:  </span>3418218B     DC.W       <a href="#NPU3_IRQHandler">NPU3_IRQHandler</a>
-<span id="A34180524">  0x34180524:  </span>3418218D     DC.W       <a href="#CACHEAXI_IRQHandler">CACHEAXI_IRQHandler</a>
-<span id="A34180528">  0x34180528:  </span>3418218F     DC.W       <a href="#LTDC_LO_IRQHandler">LTDC_LO_IRQHandler</a>
-<span id="A3418052C">  0x3418052C:  </span>34182191     DC.W       <a href="#LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler</a>
-<span id="A34180530">  0x34180530:  </span>34182193     DC.W       <a href="#DMA2D_IRQHandler">DMA2D_IRQHandler</a>
-<span id="A34180534">  0x34180534:  </span>34182195     DC.W       <a href="#JPEG_IRQHandler">JPEG_IRQHandler</a>
-<span id="A34180538">  0x34180538:  </span>34182197     DC.W       <a href="#VENC_IRQHandler">VENC_IRQHandler</a>
-<span id="A3418053C">  0x3418053C:  </span>34182199     DC.W       <a href="#GFXMMU_IRQHandler">GFXMMU_IRQHandler</a>
-<span id="A34180540">  0x34180540:  </span>3418219B     DC.W       <a href="#GFXTIM_IRQHandler">GFXTIM_IRQHandler</a>
-<span id="A34180544">  0x34180544:  </span>3418219D     DC.W       <a href="#GPU2D_IRQHandler">GPU2D_IRQHandler</a>
-<span id="A34180548">  0x34180548:  </span>3418219F     DC.W       <a href="#GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler</a>
-<span id="A3418054C">  0x3418054C:  </span>341821A1     DC.W       <a href="#ICACHE_IRQHandler">ICACHE_IRQHandler</a>
-<span id="A34180550">  0x34180550:  </span>341821A3     DC.W       <a href="#HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler</a>
-<span id="A34180554">  0x34180554:  </span>341821A5     DC.W       <a href="#HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler</a>
-<span id="A34180558">  0x34180558:  </span>341821A7     DC.W       <a href="#HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler</a>
-<span id="A3418055C">  0x3418055C:  </span>341821A9     DC.W       <a href="#HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler</a>
-<span id="A34180560">  0x34180560:  </span>341821AB     DC.W       <a href="#HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler</a>
-<span id="A34180564">  0x34180564:  </span>341821AD     DC.W       <a href="#HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler</a>
-<span id="A34180568">  0x34180568:  </span>341821AF     DC.W       <a href="#HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler</a>
-<span id="A3418056C">  0x3418056C:  </span>341821B1     DC.W       <a href="#HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler</a>
-<span id="A34180570">  0x34180570:  </span>341821B3     DC.W       <a href="#HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler</a>
-<span id="A34180574">  0x34180574:  </span>341821B5     DC.W       <a href="#HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler</a>
-<span id="A34180578">  0x34180578:  </span>341821B7     DC.W       <a href="#HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler</a>
-<span id="A3418057C">  0x3418057C:  </span>341821B9     DC.W       <a href="#HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler</a>
-<span id="A34180580">  0x34180580:  </span>341821BB     DC.W       <a href="#HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler</a>
-<span id="A34180584">  0x34180584:  </span>341821BD     DC.W       <a href="#HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler</a>
-<span id="A34180588">  0x34180588:  </span>341821BF     DC.W       <a href="#HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler</a>
-<span id="A3418058C">  0x3418058C:  </span>341821C1     DC.W       <a href="#HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler</a>
-<span id="A34180590">  0x34180590:  </span>341821C3     DC.W       <a href="#GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler</a>
-<span id="A34180594">  0x34180594:  </span>341821C5     DC.W       <a href="#GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler</a>
-<span id="A34180598">  0x34180598:  </span>341821C7     DC.W       <a href="#GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler</a>
-<span id="A3418059C">  0x3418059C:  </span>341821C9     DC.W       <a href="#GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler</a>
-<span id="A341805A0">  0x341805A0:  </span>341821CB     DC.W       <a href="#GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler</a>
-<span id="A341805A4">  0x341805A4:  </span>341821CD     DC.W       <a href="#GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler</a>
-<span id="A341805A8">  0x341805A8:  </span>341821CF     DC.W       <a href="#GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler</a>
-<span id="A341805AC">  0x341805AC:  </span>341821D1     DC.W       <a href="#GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler</a>
-<span id="A341805B0">  0x341805B0:  </span>341821D3     DC.W       <a href="#GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler</a>
-<span id="A341805B4">  0x341805B4:  </span>341821D5     DC.W       <a href="#GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler</a>
-<span id="A341805B8">  0x341805B8:  </span>341821D7     DC.W       <a href="#GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler</a>
-<span id="A341805BC">  0x341805BC:  </span>341821D9     DC.W       <a href="#GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler</a>
-<span id="A341805C0">  0x341805C0:  </span>341821DB     DC.W       <a href="#GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler</a>
-<span id="A341805C4">  0x341805C4:  </span>341821DD     DC.W       <a href="#GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler</a>
-<span id="A341805C8">  0x341805C8:  </span>341821DF     DC.W       <a href="#GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler</a>
-<span id="A341805CC">  0x341805CC:  </span>341821E1     DC.W       <a href="#GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler</a>
-<span id="A341805D0">  0x341805D0:  </span>341821E3     DC.W       <a href="#I2C1_EV_IRQHandler">I2C1_EV_IRQHandler</a>
-<span id="A341805D4">  0x341805D4:  </span>341821E5     DC.W       <a href="#I2C1_ER_IRQHandler">I2C1_ER_IRQHandler</a>
-<span id="A341805D8">  0x341805D8:  </span>341821E7     DC.W       <a href="#I2C2_EV_IRQHandler">I2C2_EV_IRQHandler</a>
-<span id="A341805DC">  0x341805DC:  </span>341821E9     DC.W       <a href="#I2C2_ER_IRQHandler">I2C2_ER_IRQHandler</a>
-<span id="A341805E0">  0x341805E0:  </span>341821EB     DC.W       <a href="#I2C3_EV_IRQHandler">I2C3_EV_IRQHandler</a>
-<span id="A341805E4">  0x341805E4:  </span>341821ED     DC.W       <a href="#I2C3_ER_IRQHandler">I2C3_ER_IRQHandler</a>
-<span id="A341805E8">  0x341805E8:  </span>341821EF     DC.W       <a href="#I2C4_EV_IRQHandler">I2C4_EV_IRQHandler</a>
-<span id="A341805EC">  0x341805EC:  </span>341821F1     DC.W       <a href="#I2C4_ER_IRQHandler">I2C4_ER_IRQHandler</a>
-<span id="A341805F0">  0x341805F0:  </span>341821F3     DC.W       <a href="#I3C1_EV_IRQHandler">I3C1_EV_IRQHandler</a>
-<span id="A341805F4">  0x341805F4:  </span>341821F5     DC.W       <a href="#I3C1_ER_IRQHandler">I3C1_ER_IRQHandler</a>
-<span id="A341805F8">  0x341805F8:  </span>341821F7     DC.W       <a href="#I3C2_EV_IRQHandler">I3C2_EV_IRQHandler</a>
-<span id="A341805FC">  0x341805FC:  </span>341821F9     DC.W       <a href="#I3C2_ER_IRQHandler">I3C2_ER_IRQHandler</a>
-<span id="A34180600">  0x34180600:  </span>341821FB     DC.W       <a href="#TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler</a>
-<span id="A34180604">  0x34180604:  </span>341821FD     DC.W       <a href="#TIM1_UP_IRQHandler">TIM1_UP_IRQHandler</a>
-<span id="A34180608">  0x34180608:  </span>341821FF     DC.W       <a href="#TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler</a>
-<span id="A3418060C">  0x3418060C:  </span>34182201     DC.W       <a href="#TIM1_CC_IRQHandler">TIM1_CC_IRQHandler</a>
-<span id="A34180610">  0x34180610:  </span>34182203     DC.W       <a href="#TIM2_IRQHandler">TIM2_IRQHandler</a>
-<span id="A34180614">  0x34180614:  </span>34182205     DC.W       <a href="#TIM3_IRQHandler">TIM3_IRQHandler</a>
-<span id="A34180618">  0x34180618:  </span>34182207     DC.W       <a href="#TIM4_IRQHandler">TIM4_IRQHandler</a>
-<span id="A3418061C">  0x3418061C:  </span>34182209     DC.W       <a href="#TIM5_IRQHandler">TIM5_IRQHandler</a>
-<span id="A34180620">  0x34180620:  </span>3418220B     DC.W       <a href="#TIM6_IRQHandler">TIM6_IRQHandler</a>
-<span id="A34180624">  0x34180624:  </span>3418220D     DC.W       <a href="#TIM7_IRQHandler">TIM7_IRQHandler</a>
-<span id="A34180628">  0x34180628:  </span>3418220F     DC.W       <a href="#TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler</a>
-<span id="A3418062C">  0x3418062C:  </span>34182211     DC.W       <a href="#TIM8_UP_IRQHandler">TIM8_UP_IRQHandler</a>
-<span id="A34180630">  0x34180630:  </span>34182213     DC.W       <a href="#TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler</a>
-<span id="A34180634">  0x34180634:  </span>34182215     DC.W       <a href="#TIM8_CC_IRQHandler">TIM8_CC_IRQHandler</a>
-<span id="A34180638">  0x34180638:  </span>34182217     DC.W       <a href="#TIM9_IRQHandler">TIM9_IRQHandler</a>
-<span id="A3418063C">  0x3418063C:  </span>34182219     DC.W       <a href="#TIM10_IRQHandler">TIM10_IRQHandler</a>
-<span id="A34180640">  0x34180640:  </span>3418221B     DC.W       <a href="#TIM11_IRQHandler">TIM11_IRQHandler</a>
-<span id="A34180644">  0x34180644:  </span>3418221D     DC.W       <a href="#TIM12_IRQHandler">TIM12_IRQHandler</a>
-<span id="A34180648">  0x34180648:  </span>3418221F     DC.W       <a href="#TIM13_IRQHandler">TIM13_IRQHandler</a>
-<span id="A3418064C">  0x3418064C:  </span>34182221     DC.W       <a href="#TIM14_IRQHandler">TIM14_IRQHandler</a>
-<span id="A34180650">  0x34180650:  </span>34182223     DC.W       <a href="#TIM15_IRQHandler">TIM15_IRQHandler</a>
-<span id="A34180654">  0x34180654:  </span>34182225     DC.W       <a href="#TIM16_IRQHandler">TIM16_IRQHandler</a>
-<span id="A34180658">  0x34180658:  </span>34182227     DC.W       <a href="#TIM17_IRQHandler">TIM17_IRQHandler</a>
-<span id="A3418065C">  0x3418065C:  </span>34182229     DC.W       <a href="#TIM18_IRQHandler">TIM18_IRQHandler</a>
-<span id="A34180660">  0x34180660:  </span>3418222B     DC.W       <a href="#LPTIM1_IRQHandler">LPTIM1_IRQHandler</a>
-<span id="A34180664">  0x34180664:  </span>3418222D     DC.W       <a href="#LPTIM2_IRQHandler">LPTIM2_IRQHandler</a>
-<span id="A34180668">  0x34180668:  </span>3418222F     DC.W       <a href="#LPTIM3_IRQHandler">LPTIM3_IRQHandler</a>
-<span id="A3418066C">  0x3418066C:  </span>34182231     DC.W       <a href="#LPTIM4_IRQHandler">LPTIM4_IRQHandler</a>
-<span id="A34180670">  0x34180670:  </span>34182233     DC.W       <a href="#LPTIM5_IRQHandler">LPTIM5_IRQHandler</a>
-<span id="A34180674">  0x34180674:  </span>34182235     DC.W       <a href="#ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler</a>
-<span id="A34180678">  0x34180678:  </span>34182237     DC.W       <a href="#MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler</a>
-<span id="A3418067C">  0x3418067C:  </span>34182239     DC.W       <a href="#MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler</a>
-<span id="A34180680">  0x34180680:  </span>3418223B     DC.W       <a href="#MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler</a>
-<span id="A34180684">  0x34180684:  </span>3418223D     DC.W       <a href="#MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler</a>
-<span id="A34180688">  0x34180688:  </span>3418223F     DC.W       <a href="#MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler</a>
-<span id="A3418068C">  0x3418068C:  </span>34182241     DC.W       <a href="#MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler</a>
-<span id="A34180690">  0x34180690:  </span>34182243     DC.W       <a href="#SAI1_A_IRQHandler">SAI1_A_IRQHandler</a>
-<span id="A34180694">  0x34180694:  </span>34182245     DC.W       <a href="#SAI1_B_IRQHandler">SAI1_B_IRQHandler</a>
-<span id="A34180698">  0x34180698:  </span>34182247     DC.W       <a href="#SAI2_A_IRQHandler">SAI2_A_IRQHandler</a>
-<span id="A3418069C">  0x3418069C:  </span>34182249     DC.W       <a href="#SAI2_B_IRQHandler">SAI2_B_IRQHandler</a>
-<span id="A341806A0">  0x341806A0:  </span>3418224B     DC.W       <a href="#SPDIFRX_IRQHandler">SPDIFRX_IRQHandler</a>
-<span id="A341806A4">  0x341806A4:  </span>3418224D     DC.W       <a href="#SPI1_IRQHandler">SPI1_IRQHandler</a>
-<span id="A341806A8">  0x341806A8:  </span>3418224F     DC.W       <a href="#SPI2_IRQHandler">SPI2_IRQHandler</a>
-<span id="A341806AC">  0x341806AC:  </span>34182251     DC.W       <a href="#SPI3_IRQHandler">SPI3_IRQHandler</a>
-<span id="A341806B0">  0x341806B0:  </span>34182253     DC.W       <a href="#SPI4_IRQHandler">SPI4_IRQHandler</a>
-<span id="A341806B4">  0x341806B4:  </span>34182255     DC.W       <a href="#SPI5_IRQHandler">SPI5_IRQHandler</a>
-<span id="A341806B8">  0x341806B8:  </span>34182257     DC.W       <a href="#SPI6_IRQHandler">SPI6_IRQHandler</a>
-<span id="A341806BC">  0x341806BC:  </span>34182259     DC.W       <a href="#USART1_IRQHandler">USART1_IRQHandler</a>
-<span id="A341806C0">  0x341806C0:  </span>3418225B     DC.W       <a href="#USART2_IRQHandler">USART2_IRQHandler</a>
-<span id="A341806C4">  0x341806C4:  </span>3418225D     DC.W       <a href="#USART3_IRQHandler">USART3_IRQHandler</a>
-<span id="A341806C8">  0x341806C8:  </span>3418225F     DC.W       <a href="#UART4_IRQHandler">UART4_IRQHandler</a>
-<span id="A341806CC">  0x341806CC:  </span>34182261     DC.W       <a href="#UART5_IRQHandler">UART5_IRQHandler</a>
-<span id="A341806D0">  0x341806D0:  </span>34182263     DC.W       <a href="#USART6_IRQHandler">USART6_IRQHandler</a>
-<span id="A341806D4">  0x341806D4:  </span>34182265     DC.W       <a href="#UART7_IRQHandler">UART7_IRQHandler</a>
-<span id="A341806D8">  0x341806D8:  </span>34182267     DC.W       <a href="#UART8_IRQHandler">UART8_IRQHandler</a>
-<span id="A341806DC">  0x341806DC:  </span>34182269     DC.W       <a href="#UART9_IRQHandler">UART9_IRQHandler</a>
-<span id="A341806E0">  0x341806E0:  </span>3418226B     DC.W       <a href="#USART10_IRQHandler">USART10_IRQHandler</a>
-<span id="A341806E4">  0x341806E4:  </span>3418226D     DC.W       <a href="#LPUART1_IRQHandler">LPUART1_IRQHandler</a>
-<span id="A341806E8">  0x341806E8:  </span>3418226F     DC.W       <a href="#XSPI1_IRQHandler">XSPI1_IRQHandler</a>
-<span id="A341806EC">  0x341806EC:  </span>34182271     DC.W       <a href="#XSPI2_IRQHandler">XSPI2_IRQHandler</a>
-<span id="A341806F0">  0x341806F0:  </span>34182273     DC.W       <a href="#XSPI3_IRQHandler">XSPI3_IRQHandler</a>
-<span id="A341806F4">  0x341806F4:  </span>34182275     DC.W       <a href="#FMC_IRQHandler">FMC_IRQHandler</a>
-<span id="A341806F8">  0x341806F8:  </span>34182277     DC.W       <a href="#SDMMC1_IRQHandler">SDMMC1_IRQHandler</a>
-<span id="A341806FC">  0x341806FC:  </span>34182279     DC.W       <a href="#SDMMC2_IRQHandler">SDMMC2_IRQHandler</a>
-<span id="A34180700">  0x34180700:  </span>3418227B     DC.W       <a href="#UCPD1_IRQHandler">UCPD1_IRQHandler</a>
-<span id="A34180704">  0x34180704:  </span>3418227D     DC.W       <a href="#USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler</a>
-<span id="A34180708">  0x34180708:  </span>3418227F     DC.W       <a href="#USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler</a>
-<span id="A3418070C">  0x3418070C:  </span>34182281     DC.W       <a href="#ETH1_IRQHandler">ETH1_IRQHandler</a>
-<span id="A34180710">  0x34180710:  </span>34182283     DC.W       <a href="#FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler</a>
-<span id="A34180714">  0x34180714:  </span>34182285     DC.W       <a href="#FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler</a>
-<span id="A34180718">  0x34180718:  </span>34182287     DC.W       <a href="#FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler</a>
-<span id="A3418071C">  0x3418071C:  </span>34182289     DC.W       <a href="#FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler</a>
-<span id="A34180720">  0x34180720:  </span>3418228B     DC.W       <a href="#FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler</a>
-<span id="A34180724">  0x34180724:  </span>3418228D     DC.W       <a href="#FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler</a>
-<span id="A34180728">  0x34180728:  </span>3418228F     DC.W       <a href="#FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler</a>
-<span id="A3418072C">  0x3418072C:  </span>34182291     DC.W       <a href="#MDIOS_IRQHandler">MDIOS_IRQHandler</a>
-<span id="A34180730">  0x34180730:  </span>34182293     DC.W       <a href="#DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler</a>
-<span id="A34180734">  0x34180734:  </span>34182295     DC.W       <a href="#WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler</a>
-<span id="A34180738">  0x34180738:  </span>34182297     DC.W       <a href="#CTI_INT0_IRQHandler">CTI_INT0_IRQHandler</a>
-<span id="A3418073C">  0x3418073C:  </span>34182299     DC.W       <a href="#CTI_INT1_IRQHandler">CTI_INT1_IRQHandler</a>
-<span id="A34180740">  0x34180740:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180741">  0x34180741:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180742">  0x34180742:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180743">  0x34180743:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180744">  0x34180744:  </span>3418229B     DC.W       <a href="#LTDC_UP_IRQHandler">LTDC_UP_IRQHandler</a>
-<span id="A34180748">  0x34180748:  </span>3418229D     DC.W       <a href="#LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler</a>
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.main from blto2_FSBL_lto.o, size=1184, align=4">Section .text.main from blto2_FSBL_lto.o, size=1184, align=4</h2>
-
-<pre>
-<br/><span id="main">main:</span>
-<span id="_vectors_end">_vectors_end:</span>
-<span id="A3418074C">  0x3418074C:  </span>B0B6         SUB        SP, SP, #216
-<span id="A3418074E">  0x3418074E:  </span>F64E 5414    MOVW       R4, #0xED14
-<span id="A34180752">  0x34180752:  </span>F2CE 0400    MOVT       R4, #0xE000
-<span id="A34180756">  0x34180756:  </span>6820         LDR        R0, [R4]
-<span id="A34180758">  0x34180758:  </span>0380         LSLS       R0, R0, #14
-<span id="A3418075A">  0x3418075A:  </span>D412         BMI        46L1                      ; 0x34180782
-<span id="A3418075C">  0x3418075C:  </span>F3BF 8F4F    DSB        SY
-<span id="A34180760">  0x34180760:  </span>2000         MOVS       R0, #0
-<span id="A34180762">  0x34180762:  </span>F3BF 8F6F    ISB        SY
-<span id="A34180766">  0x34180766:  </span>F8C4 023C    STR.W      R0, [R4, #0x023C]
-<span id="A3418076A">  0x3418076A:  </span>F3BF 8F4F    DSB        SY
-<span id="A3418076E">  0x3418076E:  </span>F3BF 8F6F    ISB        SY
-<span id="A34180772">  0x34180772:  </span>6820         LDR        R0, [R4]
-<span id="A34180774">  0x34180774:  </span>F440 3000    ORR        R0, R0, #0x020000
-<span id="A34180778">  0x34180778:  </span>6020         STR        R0, [R4]
-<span id="A3418077A">  0x3418077A:  </span>F3BF 8F4F    DSB        SY
-<span id="A3418077E">  0x3418077E:  </span>F3BF 8F6F    ISB        SY
-<br/>.L1:
-<span id="A34180782">  0x34180782:  </span>6820         LDR        R0, [R4]
-<span id="A34180784">  0x34180784:  </span>03C0         LSLS       R0, R0, #15
-<span id="A34180786">  0x34180786:  </span>D426         BMI        46L4                      ; 0x341807D6
-<span id="A34180788">  0x34180788:  </span>2000         MOVS       R0, #0
-<span id="A3418078A">  0x3418078A:  </span>F643 72E0    MOVW       R2, #0x3FE0
-<span id="A3418078E">  0x3418078E:  </span>6720         STR        R0, [R4, #112]
-<span id="A34180790">  0x34180790:  </span>F3BF 8F4F    DSB        SY
-<span id="A34180794">  0x34180794:  </span>6EE1         LDR        R1, [R4, #108]
-<span id="A34180796">  0x34180796:  </span>F3C1 06C9    UBFX       R6, R1, #3, #10
-<span id="A3418079A">  0x3418079A:  </span>F3C1 304E    UBFX       R0, R1, #13, #15
-<span id="A3418079E">  0x3418079E:  </span>F106 0A01    ADD.W      R10, R6, #1
-<span id="A341807A2">  0x341807A2:  </span>BF00         NOP
-<br/>.L2:
-<span id="A341807A4">  0x341807A4:  </span>F04A E001    DLS        LR, R10
-<span id="A341807A8">  0x341807A8:  </span>4631         MOV        R1, R6
-<span id="A341807AA">  0x341807AA:  </span>EA02 1340    AND.W      R3, R2, R0, LSL #5
-<span id="A341807AE">  0x341807AE:  </span>BF00         NOP
-<br/>.L3:
-<span id="A341807B0">  0x341807B0:  </span>EA43 7581    ORR.W      R5, R3, R1, LSL #30
-<span id="A341807B4">  0x341807B4:  </span>3901         SUBS       R1, #1
-<span id="A341807B6">  0x341807B6:  </span>F8C4 524C    STR.W      R5, [R4, #0x024C]
-<span id="A341807BA">  0x341807BA:  </span>F00F C807    LE         LR, .L3                  ; 0x341807B0
-<span id="A341807BE">  0x341807BE:  </span>3801         SUBS       R0, #1
-<span id="A341807C0">  0x341807C0:  </span>D2F0         BCS        46L2                      ; 0x341807A4
-<span id="A341807C2">  0x341807C2:  </span>F3BF 8F4F    DSB        SY
-<span id="A341807C6">  0x341807C6:  </span>6820         LDR        R0, [R4]
-<span id="A341807C8">  0x341807C8:  </span>F440 3080    ORR        R0, R0, #0x010000
-<span id="A341807CC">  0x341807CC:  </span>6020         STR        R0, [R4]
-<span id="A341807CE">  0x341807CE:  </span>F3BF 8F4F    DSB        SY
-<span id="A341807D2">  0x341807D2:  </span>F3BF 8F6F    ISB        SY
-<br/>.L4:
-<span id="A341807D6">  0x341807D6:  </span>F854 0C08    LDR        R0, [R4, #-8]
-<span id="A341807DA">  0x341807DA:  </span>F64F 01FF    MOVW       R1, #0xF8FF
-<span id="A341807DE">  0x341807DE:  </span>F644 0520    MOVW       R5, #0x4820
-<span id="A341807E2">  0x341807E2:  </span>4008         ANDS       R0, R1
-<span id="A341807E4">  0x341807E4:  </span>F240 3100    MOVW       R1, #0x0300
-<span id="A341807E8">  0x341807E8:  </span>F2C0 51FA    MOVT       R1, #0x05FA
-<span id="A341807EC">  0x341807EC:  </span>4308         ORRS       R0, R1
-<span id="A341807EE">  0x341807EE:  </span>F844 0C08    STR        R0, [R4, #-8]
-<span id="A341807F2">  0x341807F2:  </span>F2C5 6502    MOVT       R5, #0x5602
-<span id="A341807F6">  0x341807F6:  </span>F000 FA01    BL         <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>    ; 0x34180BFC
-<span id="A341807FA">  0x341807FA:  </span>F242 20AC    MOVW       R0, #0x22AC              ; 0x341822AC = SystemCoreClock
-<span id="A341807FE">  0x341807FE:  </span>F644 51D3    MOVW       R1, #0x4DD3
-<span id="A34180802">  0x34180802:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822AC = SystemCoreClock
-<span id="A34180806">  0x34180806:  </span>6800         LDR        R0, [R0]
-<span id="A34180808">  0x34180808:  </span>F2C1 0162    MOVT       R1, #0x1062
-<span id="A3418080C">  0x3418080C:  </span>FBA0 0101    UMULL      R0, R1, R0, R1
-<span id="A34180810">  0x34180810:  </span>F04F 30FF    MOV.W      R0, #0xFFFFFFFF
-<span id="A34180814">  0x34180814:  </span>EB00 1191    ADD.W      R1, R0, R1, LSR #6
-<span id="A34180818">  0x34180818:  </span>0E0A         LSRS       R2, R1, #24
-<span id="A3418081A">  0x3418081A:  </span>D124         BNE        46L5                      ; 0x34180866
-<span id="A3418081C">  0x3418081C:  </span>F24E 0210    MOVW       R2, #0xE010
-<span id="A34180820">  0x34180820:  </span>F2CE 0200    MOVT       R2, #0xE000
-<span id="A34180824">  0x34180824:  </span>6051         STR        R1, [R2, #4]
-<span id="A34180826">  0x34180826:  </span>21F0         MOVS       R1, #240
-<span id="A34180828">  0x34180828:  </span>73E1         STRB       R1, [R4, #15]
-<span id="A3418082A">  0x3418082A:  </span>2100         MOVS       R1, #0
-<span id="A3418082C">  0x3418082C:  </span>6091         STR        R1, [R2, #8]
-<span id="A3418082E">  0x3418082E:  </span>2107         MOVS       R1, #7
-<span id="A34180830">  0x34180830:  </span>6011         STR        R1, [R2]
-<span id="A34180832">  0x34180832:  </span>F854 1C08    LDR        R1, [R4, #-8]
-<span id="A34180836">  0x34180836:  </span>F3C1 2102    UBFX       R1, R1, #8, #3
-<span id="A3418083A">  0x3418083A:  </span>F081 0207    EOR        R2, R1, #7
-<span id="A3418083E">  0x3418083E:  </span>2A04         CMP        R2, #4
-<span id="A34180840">  0x34180840:  </span>BF28         IT         CS
-<span id="A34180842">  0x34180842:  </span>2204         MOVCS      R2, #4
-<span id="A34180844">  0x34180844:  </span>4090         LSLS       R0, R2
-<span id="A34180846">  0x34180846:  </span>43C0         MVNS       R0, R0
-<span id="A34180848">  0x34180848:  </span>3903         SUBS       R1, #3
-<span id="A3418084A">  0x3418084A:  </span>BF28         IT         CS
-<span id="A3418084C">  0x3418084C:  </span>4088         LSLCS      R0, R1
-<span id="A3418084E">  0x3418084E:  </span>2101         MOVS       R1, #1
-<span id="A34180850">  0x34180850:  </span>0100         LSLS       R0, R0, #4
-<span id="A34180852">  0x34180852:  </span>73E0         STRB       R0, [R4, #15]
-<span id="A34180854">  0x34180854:  </span>F242 20A8    MOVW       R0, #0x22A8              ; 0x341822A8 = uwTickPrio
-<span id="A34180858">  0x34180858:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A8 = uwTickPrio
-<span id="A3418085C">  0x3418085C:  </span>7001         STRB       R1, [R0]
-<span id="A3418085E">  0x3418085E:  </span>69E8         LDR        R0, [R5, #28]
-<span id="A34180860">  0x34180860:  </span>F440 7000    ORR        R0, R0, #0x0200
-<span id="A34180864">  0x34180864:  </span>61E8         STR        R0, [R5, #28]
-<br/>.L5:
-<span id="A34180866">  0x34180866:  </span>A811         ADD        R0, SP, #68
-<span id="A34180868">  0x34180868:  </span>2194         MOVS       R1, #148
-<span id="A3418086A">  0x3418086A:  </span>F000 FE3F    BL         <a href="#__aeabi_memclr">__aeabi_memclr</a>           ; 0x341814EC
-<span id="A3418086E">  0x3418086E:  </span>4668         MOV        R0, SP
-<span id="A34180870">  0x34180870:  </span>2140         MOVS       R1, #64
-<span id="A34180872">  0x34180872:  </span>F000 FE3B    BL         <a href="#__aeabi_memclr">__aeabi_memclr</a>           ; 0x341814EC
-<span id="A34180876">  0x34180876:  </span>F855 0C20    LDR        R0, [R5, #-32]
-<span id="A3418087A">  0x3418087A:  </span>F242 2AA4    MOVW       R10, #0x22A4             ; 0x341822A4 = uwTick
-<span id="A3418087E">  0x3418087E:  </span>F2C3 4A18    MOVT       R10, #0x3418             ; 0x341822A4 = uwTick
-<span id="A34180882">  0x34180882:  </span>F020 0004    BIC        R0, R0, #4
-<span id="A34180886">  0x34180886:  </span>F845 0C20    STR        R0, [R5, #-32]
-<span id="A3418088A">  0x3418088A:  </span>F8DA 0000    LDR.W      R0, [R10]
-<span id="A3418088E">  0x3418088E:  </span>BF00         NOP
-<br/>.L6:
-<span id="A34180890">  0x34180890:  </span>6829         LDR        R1, [R5]
-<span id="A34180892">  0x34180892:  </span>0389         LSLS       R1, R1, #14
-<span id="A34180894">  0x34180894:  </span>D407         BMI        46L8                      ; 0x341808A6
-<span id="A34180896">  0x34180896:  </span>F8DA 1000    LDR.W      R1, [R10]
-<span id="A3418089A">  0x3418089A:  </span>1A09         SUBS       R1, R1, R0
-<span id="A3418089C">  0x3418089C:  </span>F5B1 7F7A    CMP.W      R1, #0x03E8
-<span id="A341808A0">  0x341808A0:  </span>D9F6         BLS        46L6                      ; 0x34180890
-<span id="A341808A2">  0x341808A2:  </span>B672         CPSID      i
-<br/>.L7:
-<span id="A341808A4">  0x341808A4:  </span>E7FE         B          46L7                      ; 0x341808A4
-<br/>.L8:
-<span id="A341808A6">  0x341808A6:  </span>6828         LDR        R0, [R5]
-<span id="A341808A8">  0x341808A8:  </span>F020 0001    BIC        R0, R0, #1
-<span id="A341808AC">  0x341808AC:  </span>6028         STR        R0, [R5]
-<span id="A341808AE">  0x341808AE:  </span>F8DA 0000    LDR.W      R0, [R10]
-<span id="A341808B2">  0x341808B2:  </span>BF00         NOP
-<br/>.L9:
-<span id="A341808B4">  0x341808B4:  </span>6829         LDR        R1, [R5]
-<span id="A341808B6">  0x341808B6:  </span>0789         LSLS       R1, R1, #30
-<span id="A341808B8">  0x341808B8:  </span>D407         BMI        46L11                     ; 0x341808CA
-<span id="A341808BA">  0x341808BA:  </span>F8DA 1000    LDR.W      R1, [R10]
-<span id="A341808BE">  0x341808BE:  </span>1A09         SUBS       R1, R1, R0
-<span id="A341808C0">  0x341808C0:  </span>F5B1 7F7A    CMP.W      R1, #0x03E8
-<span id="A341808C4">  0x341808C4:  </span>D9F6         BLS        46L9                      ; 0x341808B4
-<span id="A341808C6">  0x341808C6:  </span>B672         CPSID      i
-<br/>.L10:
-<span id="A341808C8">  0x341808C8:  </span>E7FE         B          46L10                     ; 0x341808C8
-<br/>.L11:
-<span id="A341808CA">  0x341808CA:  </span>2002         MOVS       R0, #2
-<span id="A341808CC">  0x341808CC:  </span>9010         STR        R0, [SP, #64]
-<span id="A341808CE">  0x341808CE:  </span>2008         MOVS       R0, #8
-<span id="A341808D0">  0x341808D0:  </span>9013         STR        R0, [SP, #76]
-<span id="A341808D2">  0x341808D2:  </span>2000         MOVS       R0, #0
-<span id="A341808D4">  0x341808D4:  </span>E9CD 0014    STRD       R0, R0, [SP, #80]
-<span id="A341808D8">  0x341808D8:  </span>901A         STR        R0, [SP, #104]
-<span id="A341808DA">  0x341808DA:  </span>9021         STR        R0, [SP, #132]
-<span id="A341808DC">  0x341808DC:  </span>9028         STR        R0, [SP, #160]
-<span id="A341808DE">  0x341808DE:  </span>902F         STR        R0, [SP, #188]
-<span id="A341808E0">  0x341808E0:  </span>A810         ADD        R0, SP, #64
-<span id="A341808E2">  0x341808E2:  </span>F000 FFB1    BL         <a href="#HAL_RCC_OscConfig">HAL_RCC_OscConfig</a>        ; 0x34181848
-<span id="A341808E6">  0x341808E6:  </span>B110         CBZ        R0, .L13                 ; 0x341808EE
-<span id="A341808E8">  0x341808E8:  </span>B672         CPSID      i
-<span id="A341808EA">  0x341808EA:  </span>BF00         NOP
-<br/>.L12:
-<span id="A341808EC">  0x341808EC:  </span>E7FE         B          46L12                     ; 0x341808EC
-<br/>.L13:
-<span id="A341808EE">  0x341808EE:  </span>207F         MOVS       R0, #127
-<span id="A341808F0">  0x341808F0:  </span>F248 265C    MOVW       R6, #0x825C
-<span id="A341808F4">  0x341808F4:  </span>9000         STR        R0, [SP, #0]
-<span id="A341808F6">  0x341808F6:  </span>F64F 50C4    MOVW       R0, #0xFDC4
-<span id="A341808FA">  0x341808FA:  </span>F2C5 6602    MOVT       R6, #0x5602
-<span id="A341808FE">  0x341808FE:  </span>F44F 3140    MOV.W      R1, #0x030000
-<span id="A34180902">  0x34180902:  </span>F6CF 70FF    MOVT       R0, #0xFFFF
-<span id="A34180906">  0x34180906:  </span>5830         LDR        R0, [R6, R0]
-<span id="A34180908">  0x34180908:  </span>EA01 1110    AND.W      R1, R1, R0, LSR #4
-<span id="A3418090C">  0x3418090C:  </span>9101         STR        R1, [SP, #4]
-<span id="A3418090E">  0x3418090E:  </span>F5B1 3F40    CMP.W      R1, #0x030000
-<span id="A34180912">  0x34180912:  </span>F04F 7140    MOV.W      R1, #0x03000000
-<span id="A34180916">  0x34180916:  </span>EA01 1010    AND.W      R0, R1, R0, LSR #4
-<span id="A3418091A">  0x3418091A:  </span>F64F 51C8    MOVW       R1, #0xFDC8
-<span id="A3418091E">  0x3418091E:  </span>9002         STR        R0, [SP, #8]
-<span id="A34180920">  0x34180920:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A34180924">  0x34180924:  </span>5871         LDR        R1, [R6, R1]
-<span id="A34180926">  0x34180926:  </span>F401 02E0    AND        R2, R1, #0x700000
-<span id="A3418092A">  0x3418092A:  </span>9203         STR        R2, [SP, #12]
-<span id="A3418092C">  0x3418092C:  </span>F001 0207    AND        R2, R1, #7
-<span id="A34180930">  0x34180930:  </span>9204         STR        R2, [SP, #16]
-<span id="A34180932">  0x34180932:  </span>F001 0270    AND        R2, R1, #112
-<span id="A34180936">  0x34180936:  </span>9205         STR        R2, [SP, #20]
-<span id="A34180938">  0x34180938:  </span>F401 42E0    AND        R2, R1, #0x7000
-<span id="A3418093C">  0x3418093C:  </span>F401 21E0    AND        R1, R1, #0x070000
-<span id="A34180940">  0x34180940:  </span>E9CD 2106    STRD       R2, R1, [SP, #24]
-<span id="A34180944">  0x34180944:  </span>F64F 6168    MOVW       R1, #0xFE68
-<span id="A34180948">  0x34180948:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A3418094C">  0x3418094C:  </span>5871         LDR        R1, [R6, R1]
-<span id="A3418094E">  0x3418094E:  </span>F001 5240    AND        R2, R1, #0x30000000
-<span id="A34180952">  0x34180952:  </span>9208         STR        R2, [SP, #32]
-<span id="A34180954">  0x34180954:  </span>F04F 0201    MOV.W      R2, #1
-<span id="A34180958">  0x34180958:  </span>FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
-<span id="A3418095C">  0x3418095C:  </span>9109         STR        R1, [SP, #36]
-<span id="A3418095E">  0x3418095E:  </span>F64F 616C    MOVW       R1, #0xFE6C
-<span id="A34180962">  0x34180962:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A34180966">  0x34180966:  </span>5871         LDR        R1, [R6, R1]
-<span id="A34180968">  0x34180968:  </span>F001 5340    AND        R3, R1, #0x30000000
-<span id="A3418096C">  0x3418096C:  </span>FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
-<span id="A34180970">  0x34180970:  </span>E9CD 310A    STRD       R3, R1, [SP, #40]
-<span id="A34180974">  0x34180974:  </span>F64F 617C    MOVW       R1, #0xFE7C
-<span id="A34180978">  0x34180978:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A3418097C">  0x3418097C:  </span>5871         LDR        R1, [R6, R1]
-<span id="A3418097E">  0x3418097E:  </span>F001 5340    AND        R3, R1, #0x30000000
-<span id="A34180982">  0x34180982:  </span>FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
-<span id="A34180986">  0x34180986:  </span>E9CD 310C    STRD       R3, R1, [SP, #48]
-<span id="A3418098A">  0x3418098A:  </span>F64F 6190    MOVW       R1, #0xFE90
-<span id="A3418098E">  0x3418098E:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A34180992">  0x34180992:  </span>5871         LDR        R1, [R6, R1]
-<span id="A34180994">  0x34180994:  </span>FA52 F2A1    UXTAB      R2, R2, R1, ROR #16
-<span id="A34180998">  0x34180998:  </span>F001 5140    AND        R1, R1, #0x30000000
-<span id="A3418099C">  0x3418099C:  </span>E9CD 120E    STRD       R1, R2, [SP, #56]
-<span id="A341809A0">  0x341809A0:  </span>BF18         IT         NE
-<span id="A341809A2">  0x341809A2:  </span>F1B0 7F40    CMPNE.W    R0, #0x03000000
-<span id="A341809A6">  0x341809A6:  </span>D10A         BNE        46L15                     ; 0x341809BE
-<span id="A341809A8">  0x341809A8:  </span>2003         MOVS       R0, #3
-<span id="A341809AA">  0x341809AA:  </span>9000         STR        R0, [SP, #0]
-<span id="A341809AC">  0x341809AC:  </span>2000         MOVS       R0, #0
-<span id="A341809AE">  0x341809AE:  </span>E9CD 0001    STRD       R0, R0, [SP, #4]
-<span id="A341809B2">  0x341809B2:  </span>4668         MOV        R0, SP
-<span id="A341809B4">  0x341809B4:  </span>F000 F9EA    BL         <a href="#HAL_RCC_ClockConfig">HAL_RCC_ClockConfig</a>      ; 0x34180D8C
-<span id="A341809B8">  0x341809B8:  </span>B108         CBZ        R0, .L15                 ; 0x341809BE
-<span id="A341809BA">  0x341809BA:  </span>B672         CPSID      i
-<br/>.L14:
-<span id="A341809BC">  0x341809BC:  </span>E7FE         B          46L14                     ; 0x341809BC
-<br/>.L15:
-<span id="A341809BE">  0x341809BE:  </span>2500         MOVS       R5, #0
-<span id="A341809C0">  0x341809C0:  </span>204B         MOVS       R0, #75
-<span id="A341809C2">  0x341809C2:  </span>E9CD 501D    STRD       R5, R0, [SP, #116]
-<span id="A341809C6">  0x341809C6:  </span>2001         MOVS       R0, #1
-<span id="A341809C8">  0x341809C8:  </span>F04F 0902    MOV.W      R9, #2
-<span id="A341809CC">  0x341809CC:  </span>F04F 0804    MOV.W      R8, #4
-<span id="A341809D0">  0x341809D0:  </span>9510         STR        R5, [SP, #64]
-<span id="A341809D2">  0x341809D2:  </span>E9CD 001F    STRD       R0, R0, [SP, #124]
-<span id="A341809D6">  0x341809D6:  </span>A810         ADD        R0, SP, #64
-<span id="A341809D8">  0x341809D8:  </span>F8CD 8070    STR.W      R8, [SP, #112]
-<span id="A341809DC">  0x341809DC:  </span>E9CD 951A    STRD       R9, R5, [SP, #104]
-<span id="A341809E0">  0x341809E0:  </span>9521         STR        R5, [SP, #132]
-<span id="A341809E2">  0x341809E2:  </span>9528         STR        R5, [SP, #160]
-<span id="A341809E4">  0x341809E4:  </span>952F         STR        R5, [SP, #188]
-<span id="A341809E6">  0x341809E6:  </span>F000 FF2F    BL         <a href="#HAL_RCC_OscConfig">HAL_RCC_OscConfig</a>        ; 0x34181848
-<span id="A341809EA">  0x341809EA:  </span>B110         CBZ        R0, .L17                 ; 0x341809F2
-<span id="A341809EC">  0x341809EC:  </span>B672         CPSID      i
-<span id="A341809EE">  0x341809EE:  </span>BF00         NOP
-<br/>.L16:
-<span id="A341809F0">  0x341809F0:  </span>E7FE         B          46L16                     ; 0x341809F0
-<br/>.L17:
-<span id="A341809F2">  0x341809F2:  </span>207F         MOVS       R0, #127
-<span id="A341809F4">  0x341809F4:  </span>2703         MOVS       R7, #3
-<span id="A341809F6">  0x341809F6:  </span>9000         STR        R0, [SP, #0]
-<span id="A341809F8">  0x341809F8:  </span>F44F 3040    MOV.W      R0, #0x030000
-<span id="A341809FC">  0x341809FC:  </span>9001         STR        R0, [SP, #4]
-<span id="A341809FE">  0x341809FE:  </span>F04F 7040    MOV.W      R0, #0x03000000
-<span id="A34180A02">  0x34180A02:  </span>9002         STR        R0, [SP, #8]
-<span id="A34180A04">  0x34180A04:  </span>F44F 1080    MOV.W      R0, #0x100000
-<span id="A34180A08">  0x34180A08:  </span>E9CD 0503    STRD       R0, R5, [SP, #12]
-<span id="A34180A0C">  0x34180A0C:  </span>4668         MOV        R0, SP
-<span id="A34180A0E">  0x34180A0E:  </span>970F         STR        R7, [SP, #60]
-<span id="A34180A10">  0x34180A10:  </span>E9CD 5505    STRD       R5, R5, [SP, #20]
-<span id="A34180A14">  0x34180A14:  </span>E9CD 5507    STRD       R5, R5, [SP, #28]
-<span id="A34180A18">  0x34180A18:  </span>E9CD 9509    STRD       R9, R5, [SP, #36]
-<span id="A34180A1C">  0x34180A1C:  </span>E9CD 750B    STRD       R7, R5, [SP, #44]
-<span id="A34180A20">  0x34180A20:  </span>E9CD 850D    STRD       R8, R5, [SP, #52]
-<span id="A34180A24">  0x34180A24:  </span>F000 F9B2    BL         <a href="#HAL_RCC_ClockConfig">HAL_RCC_ClockConfig</a>      ; 0x34180D8C
-<span id="A34180A28">  0x34180A28:  </span>B108         CBZ        R0, .L19                 ; 0x34180A2E
-<span id="A34180A2A">  0x34180A2A:  </span>B672         CPSID      i
-<br/>.L18:
-<span id="A34180A2C">  0x34180A2C:  </span>E7FE         B          46L18                     ; 0x34180A2C
-<br/>.L19:
-<span id="A34180A2E">  0x34180A2E:  </span>F04F 0B00    MOV.W      R11, #0
-<span id="A34180A32">  0x34180A32:  </span>F506 6000    ADD.W      R0, R6, #0x0800
-<span id="A34180A36">  0x34180A36:  </span>F44F 3180    MOV.W      R1, #0x010000
-<span id="A34180A3A">  0x34180A3A:  </span>F641 0528    MOVW       R5, #0x1828
-<span id="A34180A3E">  0x34180A3E:  </span>E9CD BB13    STRD       R11, R11, [SP, #76]
-<span id="A34180A42">  0x34180A42:  </span>6001         STR        R1, [R0]
-<span id="A34180A44">  0x34180A44:  </span>6831         LDR        R1, [R6]
-<span id="A34180A46">  0x34180A46:  </span>F2C5 6502    MOVT       R5, #0x5602
-<span id="A34180A4A">  0x34180A4A:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A4C">  0x34180A4C:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A4E">  0x34180A4E:  </span>F8C0 8000    STR.W      R8, [R0]
-<span id="A34180A52">  0x34180A52:  </span>F04F 0801    MOV.W      R8, #1
-<span id="A34180A56">  0x34180A56:  </span>6831         LDR        R1, [R6]
-<span id="A34180A58">  0x34180A58:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A5A">  0x34180A5A:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A5C">  0x34180A5C:  </span>2110         MOVS       R1, #16
-<span id="A34180A5E">  0x34180A5E:  </span>6001         STR        R1, [R0]
-<span id="A34180A60">  0x34180A60:  </span>6831         LDR        R1, [R6]
-<span id="A34180A62">  0x34180A62:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A64">  0x34180A64:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A66">  0x34180A66:  </span>2108         MOVS       R1, #8
-<span id="A34180A68">  0x34180A68:  </span>6001         STR        R1, [R0]
-<span id="A34180A6A">  0x34180A6A:  </span>6831         LDR        R1, [R6]
-<span id="A34180A6C">  0x34180A6C:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A6E">  0x34180A6E:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A70">  0x34180A70:  </span>2180         MOVS       R1, #128
-<span id="A34180A72">  0x34180A72:  </span>6001         STR        R1, [R0]
-<span id="A34180A74">  0x34180A74:  </span>6831         LDR        R1, [R6]
-<span id="A34180A76">  0x34180A76:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A78">  0x34180A78:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A7A">  0x34180A7A:  </span>F8C0 9000    STR.W      R9, [R0]
-<span id="A34180A7E">  0x34180A7E:  </span>6831         LDR        R1, [R6]
-<span id="A34180A80">  0x34180A80:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A82">  0x34180A82:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A84">  0x34180A84:  </span>F44F 4100    MOV.W      R1, #0x8000
-<span id="A34180A88">  0x34180A88:  </span>6001         STR        R1, [R0]
-<span id="A34180A8A">  0x34180A8A:  </span>6831         LDR        R1, [R6]
-<span id="A34180A8C">  0x34180A8C:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A8E">  0x34180A8E:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A90">  0x34180A90:  </span>F44F 4180    MOV.W      R1, #0x4000
-<span id="A34180A94">  0x34180A94:  </span>6001         STR        R1, [R0]
-<span id="A34180A96">  0x34180A96:  </span>6831         LDR        R1, [R6]
-<span id="A34180A98">  0x34180A98:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180A9A">  0x34180A9A:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180A9C">  0x34180A9C:  </span>2140         MOVS       R1, #64
-<span id="A34180A9E">  0x34180A9E:  </span>6001         STR        R1, [R0]
-<span id="A34180AA0">  0x34180AA0:  </span>6831         LDR        R1, [R6]
-<span id="A34180AA2">  0x34180AA2:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180AA4">  0x34180AA4:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180AA6">  0x34180AA6:  </span>2120         MOVS       R1, #32
-<span id="A34180AA8">  0x34180AA8:  </span>6001         STR        R1, [R0]
-<span id="A34180AAA">  0x34180AAA:  </span>6831         LDR        R1, [R6]
-<span id="A34180AAC">  0x34180AAC:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180AAE">  0x34180AAE:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180AB0">  0x34180AB0:  </span>F44F 5100    MOV.W      R1, #0x2000
-<span id="A34180AB4">  0x34180AB4:  </span>6001         STR        R1, [R0]
-<span id="A34180AB6">  0x34180AB6:  </span>6831         LDR        R1, [R6]
-<span id="A34180AB8">  0x34180AB8:  </span>9100         STR        R1, [SP, #0]
-<span id="A34180ABA">  0x34180ABA:  </span>9900         LDR        R1, [SP, #0]
-<span id="A34180ABC">  0x34180ABC:  </span>F8C0 8000    STR.W      R8, [R0]
-<span id="A34180AC0">  0x34180AC0:  </span>A910         ADD        R1, SP, #64
-<span id="A34180AC2">  0x34180AC2:  </span>6830         LDR        R0, [R6]
-<span id="A34180AC4">  0x34180AC4:  </span>9000         STR        R0, [SP, #0]
-<span id="A34180AC6">  0x34180AC6:  </span>9800         LDR        R0, [SP, #0]
-<span id="A34180AC8">  0x34180AC8:  </span>20FF         MOVS       R0, #255
-<span id="A34180ACA">  0x34180ACA:  </span>F8C5 8000    STR.W      R8, [R5]
-<span id="A34180ACE">  0x34180ACE:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180AD2">  0x34180AD2:  </span>A910         ADD        R1, SP, #64
-<span id="A34180AD4">  0x34180AD4:  </span>F244 0000    MOVW       R0, #0x4000
-<span id="A34180AD8">  0x34180AD8:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A34180ADC">  0x34180ADC:  </span>F000 FDE2    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180AE0">  0x34180AE0:  </span>F643 70FF    MOVW       R0, #0x3FFF
-<span id="A34180AE4">  0x34180AE4:  </span>A910         ADD        R1, SP, #64
-<span id="A34180AE6">  0x34180AE6:  </span>F1A5 0928    SUB.W      R9, R5, #40
-<span id="A34180AEA">  0x34180AEA:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180AEE">  0x34180AEE:  </span>F5A9 5080    SUB.W      R0, R9, #0x1000
-<span id="A34180AF2">  0x34180AF2:  </span>A910         ADD        R1, SP, #64
-<span id="A34180AF4">  0x34180AF4:  </span>F000 FDD6    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180AF8">  0x34180AF8:  </span>F64F 76FF    MOVW       R6, #0xFFFF
-<span id="A34180AFC">  0x34180AFC:  </span>A810         ADD        R0, SP, #64
-<span id="A34180AFE">  0x34180AFE:  </span>E880 08C0    STM.W      R0, {R6-R7, R11}
-<span id="A34180B02">  0x34180B02:  </span>F5A9 6000    SUB.W      R0, R9, #0x0800
-<span id="A34180B06">  0x34180B06:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B08">  0x34180B08:  </span>F000 FDCC    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B0C">  0x34180B0C:  </span>A810         ADD        R0, SP, #64
-<span id="A34180B0E">  0x34180B0E:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B10">  0x34180B10:  </span>E880 08C0    STM.W      R0, {R6-R7, R11}
-<span id="A34180B14">  0x34180B14:  </span>F5A9 6040    SUB.W      R0, R9, #0x0C00
-<span id="A34180B18">  0x34180B18:  </span>F000 FDC4    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B1C">  0x34180B1C:  </span>F44F 707F    MOV.W      R0, #0x03FC
-<span id="A34180B20">  0x34180B20:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B22">  0x34180B22:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180B26">  0x34180B26:  </span>F505 7076    ADD.W      R0, R5, #0x03D8
-<span id="A34180B2A">  0x34180B2A:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B2C">  0x34180B2C:  </span>F000 FDBA    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B30">  0x34180B30:  </span>A810         ADD        R0, SP, #64
-<span id="A34180B32">  0x34180B32:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B34">  0x34180B34:  </span>E880 08C0    STM.W      R0, {R6-R7, R11}
-<span id="A34180B38">  0x34180B38:  </span>F5A9 50A0    SUB.W      R0, R9, #0x1400
-<span id="A34180B3C">  0x34180B3C:  </span>F000 FDB2    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B40">  0x34180B40:  </span>A810         ADD        R0, SP, #64
-<span id="A34180B42">  0x34180B42:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B44">  0x34180B44:  </span>E880 08C0    STM.W      R0, {R6-R7, R11}
-<span id="A34180B48">  0x34180B48:  </span>F509 56E0    ADD.W      R6, R9, #0x1C00
-<span id="A34180B4C">  0x34180B4C:  </span>F506 6000    ADD.W      R0, R6, #0x0800
-<span id="A34180B50">  0x34180B50:  </span>F000 FDA8    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B54">  0x34180B54:  </span>203F         MOVS       R0, #63
-<span id="A34180B56">  0x34180B56:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B58">  0x34180B58:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180B5C">  0x34180B5C:  </span>F506 6080    ADD.W      R0, R6, #0x0400
-<span id="A34180B60">  0x34180B60:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B62">  0x34180B62:  </span>F000 FD9F    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B66">  0x34180B66:  </span>F64F 30FE    MOVW       R0, #0xFBFE
-<span id="A34180B6A">  0x34180B6A:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B6C">  0x34180B6C:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180B70">  0x34180B70:  </span>4648         MOV        R0, R9
-<span id="A34180B72">  0x34180B72:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B74">  0x34180B74:  </span>F000 FD96    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B78">  0x34180B78:  </span>F64F 70FF    MOVW       R0, #0xFFFF
-<span id="A34180B7C">  0x34180B7C:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B7E">  0x34180B7E:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180B82">  0x34180B82:  </span>F5A9 6080    SUB.W      R0, R9, #0x0400
-<span id="A34180B86">  0x34180B86:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B88">  0x34180B88:  </span>F000 FD8C    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180B8C">  0x34180B8C:  </span>F649 70FF    MOVW       R0, #0x9FFF
-<span id="A34180B90">  0x34180B90:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B92">  0x34180B92:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180B96">  0x34180B96:  </span>F5A9 50C0    SUB.W      R0, R9, #0x1800
-<span id="A34180B9A">  0x34180B9A:  </span>A910         ADD        R1, SP, #64
-<span id="A34180B9C">  0x34180B9C:  </span>F000 FD82    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180BA0">  0x34180BA0:  </span>F44F 5084    MOV.W      R0, #0x1080
-<span id="A34180BA4">  0x34180BA4:  </span>A910         ADD        R1, SP, #64
-<span id="A34180BA6">  0x34180BA6:  </span>E881 0881    STM.W      R1, {R0, R7, R11}
-<span id="A34180BAA">  0x34180BAA:  </span>4630         MOV        R0, R6
-<span id="A34180BAC">  0x34180BAC:  </span>A910         ADD        R1, SP, #64
-<span id="A34180BAE">  0x34180BAE:  </span>F000 FD79    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180BB2">  0x34180BB2:  </span>4648         MOV        R0, R9
-<span id="A34180BB4">  0x34180BB4:  </span>A910         ADD        R1, SP, #64
-<span id="A34180BB6">  0x34180BB6:  </span>E9CD 8810    STRD       R8, R8, [SP, #64]
-<span id="A34180BBA">  0x34180BBA:  </span>E9CD BB12    STRD       R11, R11, [SP, #72]
-<span id="A34180BBE">  0x34180BBE:  </span>F000 FD71    BL         <a href="#HAL_GPIO_Init">HAL_GPIO_Init</a>            ; 0x341816A4
-<span id="A34180BC2">  0x34180BC2:  </span>BF00         NOP
-<br/>.L20:
-<span id="A34180BC4">  0x34180BC4:  </span>F845 8C10    STR        R8, [R5, #-16]
-<span id="A34180BC8">  0x34180BC8:  </span>F8DA 0000    LDR.W      R0, [R10]
-<br/>.L21:
-<span id="A34180BCC">  0x34180BCC:  </span>F8DA 1000    LDR.W      R1, [R10]
-<span id="A34180BD0">  0x34180BD0:  </span>1A09         SUBS       R1, R1, R0
-<span id="A34180BD2">  0x34180BD2:  </span>29FB         CMP        R1, #251
-<span id="A34180BD4">  0x34180BD4:  </span>D3FA         BCC        46L21                     ; 0x34180BCC
-<span id="A34180BD6">  0x34180BD6:  </span>F8C5 8000    STR.W      R8, [R5]
-<span id="A34180BDA">  0x34180BDA:  </span>F8DA 0000    LDR.W      R0, [R10]
-<span id="A34180BDE">  0x34180BDE:  </span>BF00         NOP
-<br/>.L22:
-<span id="A34180BE0">  0x34180BE0:  </span>F8DA 1000    LDR.W      R1, [R10]
-<span id="A34180BE4">  0x34180BE4:  </span>1A09         SUBS       R1, R1, R0
-<span id="A34180BE6">  0x34180BE6:  </span>29FB         CMP        R1, #251
-<span id="A34180BE8">  0x34180BE8:  </span>D3FA         BCC        46L22                     ; 0x34180BE0
-<span id="A34180BEA">  0x34180BEA:  </span>E7EB         B          46L20                     ; 0x34180BC4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4">Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4</h2>
-
-<pre>
-<br/><span id="SysTick_Handler">SysTick_Handler:</span>
-<span id="A34180BEC">  0x34180BEC:  </span>F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34180BF0">  0x34180BF0:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34180BF4">  0x34180BF4:  </span>6801         LDR        R1, [R0]
-<span id="A34180BF6">  0x34180BF6:  </span>3101         ADDS       R1, #1
-<span id="A34180BF8">  0x34180BF8:  </span>6001         STR        R1, [R0]
-<span id="A34180BFA">  0x34180BFA:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4">Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4</h2>
-
-<pre>
-<br/><span id="SystemCoreClockUpdate">SystemCoreClockUpdate:</span>
-<span id="A34180BFC">  0x34180BFC:  </span>F248 0144    MOVW       R1, #0x8044
-<span id="A34180C00">  0x34180C00:  </span>F646 4000    MOVW       R0, #0x6C00
-<span id="A34180C04">  0x34180C04:  </span>F2C5 6102    MOVT       R1, #0x5602
-<span id="A34180C08">  0x34180C08:  </span>F851 2C24    LDR        R2, [R1, #-36]
-<span id="A34180C0C">  0x34180C0C:  </span>F3C2 5201    UBFX       R2, R2, #20, #2
-<span id="A34180C10">  0x34180C10:  </span>F2C0 20DC    MOVT       R0, #0x02DC
-<span id="A34180C14">  0x34180C14:  </span>E8DF F002    TBB        91PC, R2]
-<span id="A34180C18">  0x34180C18:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A34180C19">  0x34180C19:  </span>0C           DC.B       0x0C                     ; '\x0C'
-<span id="A34180C1A">  0x34180C1A:  </span>AB           DC.B       0xAB                     ; '\xAB'
-<span id="A34180C1B">  0x34180C1B:  </span>19           DC.B       0x19                     ; '\x19'
-<span id="A34180C1C">  0x34180C1C:  </span>6848         LDR        R0, [R1, #4]
-<span id="A34180C1E">  0x34180C1E:  </span>F249 0100    MOVW       R1, #0x9000
-<span id="A34180C22">  0x34180C22:  </span>F2C0 31D0    MOVT       R1, #0x03D0
-<span id="A34180C26">  0x34180C26:  </span>F3C0 10C1    UBFX       R0, R0, #7, #2
-<span id="A34180C2A">  0x34180C2A:  </span>FA21 F000    LSR.W      R0, R1, R0
-<span id="A34180C2E">  0x34180C2E:  </span>E09E         B          46L6                      ; 0x34180D6E
-<span id="A34180C30">  0x34180C30:  </span>6808         LDR        R0, [R1]
-<span id="A34180C32">  0x34180C32:  </span>0580         LSLS       R0, R0, #22
-<span id="A34180C34">  0x34180C34:  </span>F242 4000    MOVW       R0, #0x2400
-<span id="A34180C38">  0x34180C38:  </span>F2C0 00F4    MOVT       R0, #244
-<span id="A34180C3C">  0x34180C3C:  </span>F100 8097    BMI.W      46L6                      ; 0x34180D6E
-<span id="A34180C40">  0x34180C40:  </span>F640 1000    MOVW       R0, #0x0900
-<span id="A34180C44">  0x34180C44:  </span>F2C0 003D    MOVT       R0, #61
-<span id="A34180C48">  0x34180C48:  </span>E091         B          46L6                      ; 0x34180D6E
-<span id="A34180C4A">  0x34180C4A:  </span>F8D1 2080    LDR.W      R2, [R1, #128]
-<span id="A34180C4E">  0x34180C4E:  </span>F3C2 7201    UBFX       R2, R2, #28, #2
-<span id="A34180C52">  0x34180C52:  </span>B530         PUSH       123R4-R5, LR}
-<span id="A34180C54">  0x34180C54:  </span>E8DF F002    TBB        91PC, R2]
-<span id="A34180C58">  0x34180C58:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A34180C59">  0x34180C59:  </span>1A           DC.B       0x1A                     ; '\x1A'
-<span id="A34180C5A">  0x34180C5A:  </span>0A           DC.B       0x0A                     ; '\n'
-<span id="A34180C5B">  0x34180C5B:  </span>12           DC.B       0x12                     ; '\x12'
-<span id="A34180C5C">  0x34180C5C:  </span>6BCD         LDR        R5, [R1, #60]
-<span id="A34180C5E">  0x34180C5E:  </span>012B         LSLS       R3, R5, #4
-<span id="A34180C60">  0x34180C60:  </span>D442         BMI        46L2                      ; 0x34180CE8
-<span id="A34180C62">  0x34180C62:  </span>F101 0C40    ADD.W      R12, R1, #64
-<span id="A34180C66">  0x34180C66:  </span>F101 0E44    ADD.W      LR, R1, #68
-<span id="A34180C6A">  0x34180C6A:  </span>E016         B          46L1                      ; 0x34180C9A
-<span id="A34180C6C">  0x34180C6C:  </span>6DCD         LDR        R5, [R1, #92]
-<span id="A34180C6E">  0x34180C6E:  </span>012B         LSLS       R3, R5, #4
-<span id="A34180C70">  0x34180C70:  </span>D43A         BMI        46L2                      ; 0x34180CE8
-<span id="A34180C72">  0x34180C72:  </span>F101 0C60    ADD.W      R12, R1, #96
-<span id="A34180C76">  0x34180C76:  </span>F101 0E64    ADD.W      LR, R1, #100
-<span id="A34180C7A">  0x34180C7A:  </span>E00E         B          46L1                      ; 0x34180C9A
-<span id="A34180C7C">  0x34180C7C:  </span>6ECD         LDR        R5, [R1, #108]
-<span id="A34180C7E">  0x34180C7E:  </span>012B         LSLS       R3, R5, #4
-<span id="A34180C80">  0x34180C80:  </span>D432         BMI        46L2                      ; 0x34180CE8
-<span id="A34180C82">  0x34180C82:  </span>F101 0C70    ADD.W      R12, R1, #112
-<span id="A34180C86">  0x34180C86:  </span>F101 0E74    ADD.W      LR, R1, #116
-<span id="A34180C8A">  0x34180C8A:  </span>E006         B          46L1                      ; 0x34180C9A
-<span id="A34180C8C">  0x34180C8C:  </span>6CCD         LDR        R5, [R1, #76]
-<span id="A34180C8E">  0x34180C8E:  </span>012B         LSLS       R3, R5, #4
-<span id="A34180C90">  0x34180C90:  </span>D42A         BMI        46L2                      ; 0x34180CE8
-<span id="A34180C92">  0x34180C92:  </span>F101 0C50    ADD.W      R12, R1, #80
-<span id="A34180C96">  0x34180C96:  </span>F101 0E54    ADD.W      LR, R1, #84
-<br/>.L1:
-<span id="A34180C9A">  0x34180C9A:  </span>F8DC 3000    LDR.W      R3, [R12]
-<span id="A34180C9E">  0x34180C9E:  </span>F3C5 240B    UBFX       R4, R5, #8, #12
-<span id="A34180CA2">  0x34180CA2:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A34180CA6">  0x34180CA6:  </span>EE01 3A10    VMOV       S2, R3
-<span id="A34180CAA">  0x34180CAA:  </span>F8DE 2000    LDR.W      R2, [LR]
-<span id="A34180CAE">  0x34180CAE:  </span>EE00 4A10    VMOV       S0, R4
-<span id="A34180CB2">  0x34180CB2:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A34180CB6">  0x34180CB6:  </span>ED9F 2A34    VLDR       S4, =0x33800000          ; [PC, #208] [0x34180D88]
-<span id="A34180CBA">  0x34180CBA:  </span>F3C5 5305    UBFX       R3, R5, #20, #6
-<span id="A34180CBE">  0x34180CBE:  </span>F3C2 64C2    UBFX       R4, R2, #27, #3
-<span id="A34180CC2">  0x34180CC2:  </span>F3C2 6202    UBFX       R2, R2, #24, #3
-<span id="A34180CC6">  0x34180CC6:  </span>EEB8 0A40    VCVT.F32.U32 S0, S0
-<span id="A34180CCA">  0x34180CCA:  </span>EE21 1A02    VMUL.F32   S2, S2, S4
-<span id="A34180CCE">  0x34180CCE:  </span>4362         MULS       R2, R4, R2
-<span id="A34180CD0">  0x34180CD0:  </span>EE31 0A00    VADD.F32   S0, S2, S0
-<span id="A34180CD4">  0x34180CD4:  </span>EE01 3A10    VMOV       S2, R3
-<span id="A34180CD8">  0x34180CD8:  </span>2301         MOVS       R3, #1
-<span id="A34180CDA">  0x34180CDA:  </span>EEB8 2A41    VCVT.F32.U32 S4, S2
-<span id="A34180CDE">  0x34180CDE:  </span>EE01 2A10    VMOV       S2, R2
-<span id="A34180CE2">  0x34180CE2:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A34180CE6">  0x34180CE6:  </span>E006         B          46L3                      ; 0x34180CF6
-<br/>.L2:
-<span id="A34180CE8">  0x34180CE8:  </span>ED9F 0A26    VLDR       S0, =0x00000000          ; [PC, #152] [0x34180D84]
-<span id="A34180CEC">  0x34180CEC:  </span>2300         MOVS       R3, #0
-<span id="A34180CEE">  0x34180CEE:  </span>EEB0 1A40    VMOV.F32   S2, S0
-<span id="A34180CF2">  0x34180CF2:  </span>EEB0 2A40    VMOV.F32   S4, S0
-<br/>.L3:
-<span id="A34180CF6">  0x34180CF6:  </span>F3C5 7202    UBFX       R2, R5, #28, #3
-<span id="A34180CFA">  0x34180CFA:  </span>2A03         CMP        R2, #3
-<span id="A34180CFC">  0x34180CFC:  </span>D83D         BHI        46L7                      ; 0x34180D7A
-<span id="A34180CFE">  0x34180CFE:  </span>E8DF F002    TBB        91PC, R2]
-<span id="A34180D02">  0x34180D02:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A34180D03">  0x34180D03:  </span>0D           DC.B       0x0D                     ; '\r'
-<span id="A34180D04">  0x34180D04:  </span>1E           DC.B       0x1E                     ; '\x1E'
-<span id="A34180D05">  0x34180D05:  </span>1A           DC.B       0x1A                     ; '\x1A'
-<span id="A34180D06">  0x34180D06:  </span>6848         LDR        R0, [R1, #4]
-<span id="A34180D08">  0x34180D08:  </span>F249 0200    MOVW       R2, #0x9000
-<span id="A34180D0C">  0x34180D0C:  </span>F2C0 32D0    MOVT       R2, #0x03D0
-<span id="A34180D10">  0x34180D10:  </span>F3C0 10C1    UBFX       R0, R0, #7, #2
-<span id="A34180D14">  0x34180D14:  </span>FA22 F000    LSR.W      R0, R2, R0
-<span id="A34180D18">  0x34180D18:  </span>B993         CBNZ       R3, .L4                  ; 0x34180D40
-<span id="A34180D1A">  0x34180D1A:  </span>E01F         B          46L5                      ; 0x34180D5C
-<span id="A34180D1C">  0x34180D1C:  </span>6808         LDR        R0, [R1]
-<span id="A34180D1E">  0x34180D1E:  </span>0580         LSLS       R0, R0, #22
-<span id="A34180D20">  0x34180D20:  </span>F242 4000    MOVW       R0, #0x2400
-<span id="A34180D24">  0x34180D24:  </span>F2C0 00F4    MOVT       R0, #244
-<span id="A34180D28">  0x34180D28:  </span>BF5C         ITT        PL
-<span id="A34180D2A">  0x34180D2A:  </span>F640 1000    MOVWPL     R0, #0x0900
-<span id="A34180D2E">  0x34180D2E:  </span>F2C0 003D    MOVTPL     R0, #61
-<span id="A34180D32">  0x34180D32:  </span>B92B         CBNZ       R3, .L4                  ; 0x34180D40
-<span id="A34180D34">  0x34180D34:  </span>E012         B          46L5                      ; 0x34180D5C
-<span id="A34180D36">  0x34180D36:  </span>F248 0000    MOVW       R0, #0x8000
-<span id="A34180D3A">  0x34180D3A:  </span>F2C0 00BB    MOVT       R0, #187
-<span id="A34180D3E">  0x34180D3E:  </span>B16B         CBZ        R3, .L5                  ; 0x34180D5C
-<br/>.L4:
-<span id="A34180D40">  0x34180D40:  </span>EE03 0A10    VMOV       S6, R0
-<span id="A34180D44">  0x34180D44:  </span>EEB8 3A43    VCVT.F32.U32 S6, S6
-<span id="A34180D48">  0x34180D48:  </span>EE20 0A03    VMUL.F32   S0, S0, S6
-<span id="A34180D4C">  0x34180D4C:  </span>EE80 0A02    VDIV.F32   S0, S0, S4
-<span id="A34180D50">  0x34180D50:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
-<span id="A34180D54">  0x34180D54:  </span>EEBC 0AC0    VCVT.U32.F32 S0, S0
-<span id="A34180D58">  0x34180D58:  </span>EE10 0A10    VMOV       R0, S0
-<br/>.L5:
-<span id="A34180D5C">  0x34180D5C:  </span>F8D1 1080    LDR.W      R1, [R1, #128]
-<span id="A34180D60">  0x34180D60:  </span>2201         MOVS       R2, #1
-<span id="A34180D62">  0x34180D62:  </span>FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
-<span id="A34180D66">  0x34180D66:  </span>FBB0 F0F1    UDIV       R0, R0, R1
-<span id="A34180D6A">  0x34180D6A:  </span>E8BD 4030    POP.W      123R4-R5, LR}
-<br/>.L6:
-<span id="A34180D6E">  0x34180D6E:  </span>F242 21AC    MOVW       R1, #0x22AC              ; 0x341822AC = SystemCoreClock
-<span id="A34180D72">  0x34180D72:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822AC = SystemCoreClock
-<span id="A34180D76">  0x34180D76:  </span>6008         STR        R0, [R1]
-<span id="A34180D78">  0x34180D78:  </span>4770         BX         LR
-<br/>.L7:
-<span id="A34180D7A">  0x34180D7A:  </span>2000         MOVS       R0, #0
-<span id="A34180D7C">  0x34180D7C:  </span>2B00         CMP        R3, #0
-<span id="A34180D7E">  0x34180D7E:  </span>D1DF         BNE        46L4                      ; 0x34180D40
-<span id="A34180D80">  0x34180D80:  </span>E7EC         B          46L5                      ; 0x34180D5C
-<span id="A34180D82">  0x34180D82:  </span>BF00         NOP
-<span id="A34180D84">  0x34180D84:  </span>00000000     DC.W       0x00000000
-<span id="A34180D88">  0x34180D88:  </span>33800000     DC.W       0x33800000
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4">Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4</h2>
-
-<pre>
-<br/><span id="HAL_RCC_ClockConfig">HAL_RCC_ClockConfig:</span>
-<span id="A34180D8C">  0x34180D8C:  </span>B570         PUSH       123R4-R6, LR}
-<span id="A34180D8E">  0x34180D8E:  </span>6801         LDR        R1, [R0]
-<span id="A34180D90">  0x34180D90:  </span>F248 0424    MOVW       R4, #0x8024
-<span id="A34180D94">  0x34180D94:  </span>F2C5 6402    MOVT       R4, #0x5602
-<span id="A34180D98">  0x34180D98:  </span>070A         LSLS       R2, R1, #28
-<span id="A34180D9A">  0x34180D9A:  </span>D46A         BMI        46L13                     ; 0x34180E72
-<span id="A34180D9C">  0x34180D9C:  </span>06CA         LSLS       R2, R1, #27
-<span id="A34180D9E">  0x34180D9E:  </span>D475         BMI        46L14                     ; 0x34180E8C
-<br/>.L1:
-<span id="A34180DA0">  0x34180DA0:  </span>068A         LSLS       R2, R1, #26
-<span id="A34180DA2">  0x34180DA2:  </span>F100 8081    BMI.W      46L15                     ; 0x34180EA8
-<br/>.L2:
-<span id="A34180DA6">  0x34180DA6:  </span>064A         LSLS       R2, R1, #25
-<span id="A34180DA8">  0x34180DA8:  </span>F100 808C    BMI.W      46L16                     ; 0x34180EC4
-<br/>.L3:
-<span id="A34180DAC">  0x34180DAC:  </span>074A         LSLS       R2, R1, #29
-<span id="A34180DAE">  0x34180DAE:  </span>F100 8097    BMI.W      46L17                     ; 0x34180EE0
-<br/>.L4:
-<span id="A34180DB2">  0x34180DB2:  </span>07CA         LSLS       R2, R1, #31
-<span id="A34180DB4">  0x34180DB4:  </span>F040 80A2    BNE.W      46L18                     ; 0x34180EFC
-<br/>.L5:
-<span id="A34180DB8">  0x34180DB8:  </span>078A         LSLS       R2, R1, #30
-<span id="A34180DBA">  0x34180DBA:  </span>F100 8216    BMI.W      46L39                     ; 0x341811EA
-<br/>.L6:
-<span id="A34180DBE">  0x34180DBE:  </span>074A         LSLS       R2, R1, #29
-<span id="A34180DC0">  0x34180DC0:  </span>F100 8241    BMI.W      46L43                     ; 0x34181246
-<br/>.L7:
-<span id="A34180DC4">  0x34180DC4:  </span>070A         LSLS       R2, R1, #28
-<span id="A34180DC6">  0x34180DC6:  </span>F100 824C    BMI.W      46L44                     ; 0x34181262
-<br/>.L8:
-<span id="A34180DCA">  0x34180DCA:  </span>06CA         LSLS       R2, R1, #27
-<span id="A34180DCC">  0x34180DCC:  </span>F100 8257    BMI.W      46L45                     ; 0x3418127E
-<br/>.L9:
-<span id="A34180DD0">  0x34180DD0:  </span>068A         LSLS       R2, R1, #26
-<span id="A34180DD2">  0x34180DD2:  </span>F100 8262    BMI.W      46L46                     ; 0x3418129A
-<br/>.L10:
-<span id="A34180DD6">  0x34180DD6:  </span>0649         LSLS       R1, R1, #25
-<span id="A34180DD8">  0x34180DD8:  </span>D50A         BPL        46L12                     ; 0x34180DF0
-<br/>.L11:
-<span id="A34180DDA">  0x34180DDA:  </span>69C0         LDR        R0, [R0, #28]
-<span id="A34180DDC">  0x34180DDC:  </span>6821         LDR        R1, [R4]
-<span id="A34180DDE">  0x34180DDE:  </span>F401 21E0    AND        R1, R1, #0x070000
-<span id="A34180DE2">  0x34180DE2:  </span>4288         CMP        R0, R1
-<span id="A34180DE4">  0x34180DE4:  </span>BF3F         ITTTT      CC
-<span id="A34180DE6">  0x34180DE6:  </span>6821         LDRCC      R1, [R4]
-<span id="A34180DE8">  0x34180DE8:  </span>F421 21E0    BICCC      R1, R1, #0x070000
-<span id="A34180DEC">  0x34180DEC:  </span>4308         ORRCC      R0, R1
-<span id="A34180DEE">  0x34180DEE:  </span>6020         STRCC      R0, [R4]
-<br/>.L12:
-<span id="A34180DF0">  0x34180DF0:  </span>F242 20AC    MOVW       R0, #0x22AC              ; 0x341822AC = SystemCoreClock
-<span id="A34180DF4">  0x34180DF4:  </span>F644 51D3    MOVW       R1, #0x4DD3
-<span id="A34180DF8">  0x34180DF8:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822AC = SystemCoreClock
-<span id="A34180DFC">  0x34180DFC:  </span>6800         LDR        R0, [R0]
-<span id="A34180DFE">  0x34180DFE:  </span>F2C1 0162    MOVT       R1, #0x1062
-<span id="A34180E02">  0x34180E02:  </span>FBA0 0101    UMULL      R0, R1, R0, R1
-<span id="A34180E06">  0x34180E06:  </span>F04F 30FF    MOV.W      R0, #0xFFFFFFFF
-<span id="A34180E0A">  0x34180E0A:  </span>EB00 1091    ADD.W      R0, R0, R1, LSR #6
-<span id="A34180E0E">  0x34180E0E:  </span>0E01         LSRS       R1, R0, #24
-<span id="A34180E10">  0x34180E10:  </span>F040 81DA    BNE.W      46L34                     ; 0x341811C8
-<span id="A34180E14">  0x34180E14:  </span>F242 21A8    MOVW       R1, #0x22A8              ; 0x341822A8 = uwTickPrio
-<span id="A34180E18">  0x34180E18:  </span>F24E 0310    MOVW       R3, #0xE010
-<span id="A34180E1C">  0x34180E1C:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A8 = uwTickPrio
-<span id="A34180E20">  0x34180E20:  </span>780A         LDRB       R2, [R1]
-<span id="A34180E22">  0x34180E22:  </span>F2CE 0300    MOVT       R3, #0xE000
-<span id="A34180E26">  0x34180E26:  </span>6058         STR        R0, [R3, #4]
-<span id="A34180E28">  0x34180E28:  </span>20F0         MOVS       R0, #240
-<span id="A34180E2A">  0x34180E2A:  </span>2A01         CMP        R2, #1
-<span id="A34180E2C">  0x34180E2C:  </span>F603 5213    ADDW       R2, R3, #0x0D13
-<span id="A34180E30">  0x34180E30:  </span>7010         STRB       R0, [R2]
-<span id="A34180E32">  0x34180E32:  </span>F04F 0000    MOV.W      R0, #0
-<span id="A34180E36">  0x34180E36:  </span>6098         STR        R0, [R3, #8]
-<span id="A34180E38">  0x34180E38:  </span>F04F 0007    MOV.W      R0, #7
-<span id="A34180E3C">  0x34180E3C:  </span>6018         STR        R0, [R3]
-<span id="A34180E3E">  0x34180E3E:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34180E42">  0x34180E42:  </span>F040 808A    BNE.W      46L20                     ; 0x34180F5A
-<span id="A34180E46">  0x34180E46:  </span>F852 3C17    LDR        R3, [R2, #-23]
-<span id="A34180E4A">  0x34180E4A:  </span>F04F 35FF    MOV.W      R5, #0xFFFFFFFF
-<span id="A34180E4E">  0x34180E4E:  </span>F3C3 2302    UBFX       R3, R3, #8, #3
-<span id="A34180E52">  0x34180E52:  </span>F083 0607    EOR        R6, R3, #7
-<span id="A34180E56">  0x34180E56:  </span>2E04         CMP        R6, #4
-<span id="A34180E58">  0x34180E58:  </span>BF28         IT         CS
-<span id="A34180E5A">  0x34180E5A:  </span>2604         MOVCS      R6, #4
-<span id="A34180E5C">  0x34180E5C:  </span>FA05 F606    LSL.W      R6, R5, R6
-<span id="A34180E60">  0x34180E60:  </span>43F6         MVNS       R6, R6
-<span id="A34180E62">  0x34180E62:  </span>3B03         SUBS       R3, #3
-<span id="A34180E64">  0x34180E64:  </span>BF28         IT         CS
-<span id="A34180E66">  0x34180E66:  </span>409E         LSLCS      R6, R3
-<span id="A34180E68">  0x34180E68:  </span>0133         LSLS       R3, R6, #4
-<span id="A34180E6A">  0x34180E6A:  </span>7013         STRB       R3, [R2]
-<span id="A34180E6C">  0x34180E6C:  </span>7008         STRB       R0, [R1]
-<span id="A34180E6E">  0x34180E6E:  </span>2000         MOVS       R0, #0
-<span id="A34180E70">  0x34180E70:  </span>BD70         POP        123R4-R6, PC}
-<br/>.L13:
-<span id="A34180E72">  0x34180E72:  </span>6902         LDR        R2, [R0, #16]
-<span id="A34180E74">  0x34180E74:  </span>6823         LDR        R3, [R4]
-<span id="A34180E76">  0x34180E76:  </span>F003 0307    AND        R3, R3, #7
-<span id="A34180E7A">  0x34180E7A:  </span>429A         CMP        R2, R3
-<span id="A34180E7C">  0x34180E7C:  </span>BF81         ITTTT      HI
-<span id="A34180E7E">  0x34180E7E:  </span>6823         LDRHI      R3, [R4]
-<span id="A34180E80">  0x34180E80:  </span>F023 0307    BICHI      R3, R3, #7
-<span id="A34180E84">  0x34180E84:  </span>431A         ORRHI      R2, R3
-<span id="A34180E86">  0x34180E86:  </span>6022         STRHI      R2, [R4]
-<span id="A34180E88">  0x34180E88:  </span>06CA         LSLS       R2, R1, #27
-<span id="A34180E8A">  0x34180E8A:  </span>D589         BPL        46L1                      ; 0x34180DA0
-<br/>.L14:
-<span id="A34180E8C">  0x34180E8C:  </span>6942         LDR        R2, [R0, #20]
-<span id="A34180E8E">  0x34180E8E:  </span>6823         LDR        R3, [R4]
-<span id="A34180E90">  0x34180E90:  </span>F003 0370    AND        R3, R3, #112
-<span id="A34180E94">  0x34180E94:  </span>429A         CMP        R2, R3
-<span id="A34180E96">  0x34180E96:  </span>BF81         ITTTT      HI
-<span id="A34180E98">  0x34180E98:  </span>6823         LDRHI      R3, [R4]
-<span id="A34180E9A">  0x34180E9A:  </span>F023 0370    BICHI      R3, R3, #112
-<span id="A34180E9E">  0x34180E9E:  </span>431A         ORRHI      R2, R3
-<span id="A34180EA0">  0x34180EA0:  </span>6022         STRHI      R2, [R4]
-<span id="A34180EA2">  0x34180EA2:  </span>068A         LSLS       R2, R1, #26
-<span id="A34180EA4">  0x34180EA4:  </span>F57F AF7F    BPL.W      46L2                      ; 0x34180DA6
-<br/>.L15:
-<span id="A34180EA8">  0x34180EA8:  </span>6982         LDR        R2, [R0, #24]
-<span id="A34180EAA">  0x34180EAA:  </span>6823         LDR        R3, [R4]
-<span id="A34180EAC">  0x34180EAC:  </span>F403 43E0    AND        R3, R3, #0x7000
-<span id="A34180EB0">  0x34180EB0:  </span>429A         CMP        R2, R3
-<span id="A34180EB2">  0x34180EB2:  </span>BF81         ITTTT      HI
-<span id="A34180EB4">  0x34180EB4:  </span>6823         LDRHI      R3, [R4]
-<span id="A34180EB6">  0x34180EB6:  </span>F423 43E0    BICHI      R3, R3, #0x7000
-<span id="A34180EBA">  0x34180EBA:  </span>431A         ORRHI      R2, R3
-<span id="A34180EBC">  0x34180EBC:  </span>6022         STRHI      R2, [R4]
-<span id="A34180EBE">  0x34180EBE:  </span>064A         LSLS       R2, R1, #25
-<span id="A34180EC0">  0x34180EC0:  </span>F57F AF74    BPL.W      46L3                      ; 0x34180DAC
-<br/>.L16:
-<span id="A34180EC4">  0x34180EC4:  </span>69C2         LDR        R2, [R0, #28]
-<span id="A34180EC6">  0x34180EC6:  </span>6823         LDR        R3, [R4]
-<span id="A34180EC8">  0x34180EC8:  </span>F403 23E0    AND        R3, R3, #0x070000
-<span id="A34180ECC">  0x34180ECC:  </span>429A         CMP        R2, R3
-<span id="A34180ECE">  0x34180ECE:  </span>BF81         ITTTT      HI
-<span id="A34180ED0">  0x34180ED0:  </span>6823         LDRHI      R3, [R4]
-<span id="A34180ED2">  0x34180ED2:  </span>F423 23E0    BICHI      R3, R3, #0x070000
-<span id="A34180ED6">  0x34180ED6:  </span>431A         ORRHI      R2, R3
-<span id="A34180ED8">  0x34180ED8:  </span>6022         STRHI      R2, [R4]
-<span id="A34180EDA">  0x34180EDA:  </span>074A         LSLS       R2, R1, #29
-<span id="A34180EDC">  0x34180EDC:  </span>F57F AF69    BPL.W      46L4                      ; 0x34180DB2
-<br/>.L17:
-<span id="A34180EE0">  0x34180EE0:  </span>68C2         LDR        R2, [R0, #12]
-<span id="A34180EE2">  0x34180EE2:  </span>6823         LDR        R3, [R4]
-<span id="A34180EE4">  0x34180EE4:  </span>F403 03E0    AND        R3, R3, #0x700000
-<span id="A34180EE8">  0x34180EE8:  </span>429A         CMP        R2, R3
-<span id="A34180EEA">  0x34180EEA:  </span>BF81         ITTTT      HI
-<span id="A34180EEC">  0x34180EEC:  </span>6823         LDRHI      R3, [R4]
-<span id="A34180EEE">  0x34180EEE:  </span>F423 03E0    BICHI      R3, R3, #0x700000
-<span id="A34180EF2">  0x34180EF2:  </span>431A         ORRHI      R2, R3
-<span id="A34180EF4">  0x34180EF4:  </span>6022         STRHI      R2, [R4]
-<span id="A34180EF6">  0x34180EF6:  </span>07CA         LSLS       R2, R1, #31
-<span id="A34180EF8">  0x34180EF8:  </span>F43F AF5E    BEQ.W      46L5                      ; 0x34180DB8
-<br/>.L18:
-<span id="A34180EFC">  0x34180EFC:  </span>6841         LDR        R1, [R0, #4]
-<span id="A34180EFE">  0x34180EFE:  </span>F5B1 3F80    CMP.W      R1, #0x010000
-<span id="A34180F02">  0x34180F02:  </span>D02B         BEQ        46L21                     ; 0x34180F5C
-<span id="A34180F04">  0x34180F04:  </span>F5B1 3F40    CMP.W      R1, #0x030000
-<span id="A34180F08">  0x34180F08:  </span>D00A         BEQ        46L19                     ; 0x34180F20
-<span id="A34180F0A">  0x34180F0A:  </span>F854 2C20    LDR        R2, [R4, #-32]
-<span id="A34180F0E">  0x34180F0E:  </span>F5B1 3F00    CMP.W      R1, #0x020000
-<span id="A34180F12">  0x34180F12:  </span>D12B         BNE        46L22                     ; 0x34180F6C
-<span id="A34180F14">  0x34180F14:  </span>06D1         LSLS       R1, R2, #27
-<span id="A34180F16">  0x34180F16:  </span>F140 8157    BPL.W      46L34                     ; 0x341811C8
-<span id="A34180F1A">  0x34180F1A:  </span>F44F 3100    MOV.W      R1, #0x020000
-<span id="A34180F1E">  0x34180F1E:  </span>E028         B          46L23                     ; 0x34180F72
-<br/>.L19:
-<span id="A34180F20">  0x34180F20:  </span>4605         MOV        R5, R0
-<span id="A34180F22">  0x34180F22:  </span>6A01         LDR        R1, [R0, #32]
-<span id="A34180F24">  0x34180F24:  </span>F8D4 00A0    LDR.W      R0, [R4, #160]
-<span id="A34180F28">  0x34180F28:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A34180F2C">  0x34180F2C:  </span>F000 FA0E    BL         <a href="#RCC_IC_CheckPLLSources">RCC_IC_CheckPLLSources</a>   ; 0x3418134C
-<span id="A34180F30">  0x34180F30:  </span>2800         CMP        R0, #0
-<span id="A34180F32">  0x34180F32:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34180F36">  0x34180F36:  </span>D010         BEQ        46L20                     ; 0x34180F5A
-<span id="A34180F38">  0x34180F38:  </span>E9D5 1308    LDRD       R1, R3, [R5, #32]
-<span id="A34180F3C">  0x34180F3C:  </span>2600         MOVS       R6, #0
-<span id="A34180F3E">  0x34180F3E:  </span>F6CF 76FF    MOVT       R6, #0xFFFF
-<span id="A34180F42">  0x34180F42:  </span>2201         MOVS       R2, #1
-<span id="A34180F44">  0x34180F44:  </span>4628         MOV        R0, R5
-<span id="A34180F46">  0x34180F46:  </span>EB06 4303    ADD.W      R3, R6, R3, LSL #16
-<span id="A34180F4A">  0x34180F4A:  </span>430B         ORRS       R3, R1
-<span id="A34180F4C">  0x34180F4C:  </span>6869         LDR        R1, [R5, #4]
-<span id="A34180F4E">  0x34180F4E:  </span>F8C4 30A0    STR.W      R3, [R4, #160]
-<span id="A34180F52">  0x34180F52:  </span>F604 231C    ADDW       R3, R4, #0x0A1C
-<span id="A34180F56">  0x34180F56:  </span>601A         STR        R2, [R3]
-<span id="A34180F58">  0x34180F58:  </span>E00B         B          46L23                     ; 0x34180F72
-<br/>.L20:
-<span id="A34180F5A">  0x34180F5A:  </span>BD70         POP        123R4-R6, PC}
-<br/>.L21:
-<span id="A34180F5C">  0x34180F5C:  </span>F854 1C20    LDR        R1, [R4, #-32]
-<span id="A34180F60">  0x34180F60:  </span>0749         LSLS       R1, R1, #29
-<span id="A34180F62">  0x34180F62:  </span>F140 8131    BPL.W      46L34                     ; 0x341811C8
-<span id="A34180F66">  0x34180F66:  </span>F44F 3180    MOV.W      R1, #0x010000
-<span id="A34180F6A">  0x34180F6A:  </span>E002         B          46L23                     ; 0x34180F72
-<br/>.L22:
-<span id="A34180F6C">  0x34180F6C:  </span>0712         LSLS       R2, R2, #28
-<span id="A34180F6E">  0x34180F6E:  </span>F140 812B    BPL.W      46L34                     ; 0x341811C8
-<br/>.L23:
-<span id="A34180F72">  0x34180F72:  </span>F854 2C04    LDR        R2, [R4, #-4]
-<span id="A34180F76">  0x34180F76:  </span>F241 3688    MOVW       R6, #0x1388
-<span id="A34180F7A">  0x34180F7A:  </span>F422 3240    BIC        R2, R2, #0x030000
-<span id="A34180F7E">  0x34180F7E:  </span>430A         ORRS       R2, R1
-<span id="A34180F80">  0x34180F80:  </span>F844 2C04    STR        R2, [R4, #-4]
-<span id="A34180F84">  0x34180F84:  </span>F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34180F88">  0x34180F88:  </span>F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34180F8C">  0x34180F8C:  </span>6813         LDR        R3, [R2]
-<span id="A34180F8E">  0x34180F8E:  </span>BF00         NOP
-<br/>.L24:
-<span id="A34180F90">  0x34180F90:  </span>F854 5C04    LDR        R5, [R4, #-4]
-<span id="A34180F94">  0x34180F94:  </span>F405 1540    AND        R5, R5, #0x300000
-<span id="A34180F98">  0x34180F98:  </span>EBB5 1F01    CMP.W      R5, R1, LSL #4
-<span id="A34180F9C">  0x34180F9C:  </span>D005         BEQ        46L25                     ; 0x34180FAA
-<span id="A34180F9E">  0x34180F9E:  </span>6815         LDR        R5, [R2]
-<span id="A34180FA0">  0x34180FA0:  </span>1AED         SUBS       R5, R5, R3
-<span id="A34180FA2">  0x34180FA2:  </span>42B5         CMP        R5, R6
-<span id="A34180FA4">  0x34180FA4:  </span>D9F4         BLS        46L24                     ; 0x34180F90
-<span id="A34180FA6">  0x34180FA6:  </span>2003         MOVS       R0, #3
-<span id="A34180FA8">  0x34180FA8:  </span>BD70         POP        123R4-R6, PC}
-<br/>.L25:
-<span id="A34180FAA">  0x34180FAA:  </span>F854 1C04    LDR        R1, [R4, #-4]
-<span id="A34180FAE">  0x34180FAE:  </span>F3C1 5201    UBFX       R2, R1, #20, #2
-<span id="A34180FB2">  0x34180FB2:  </span>F646 4100    MOVW       R1, #0x6C00
-<span id="A34180FB6">  0x34180FB6:  </span>F2C0 21DC    MOVT       R1, #0x02DC
-<span id="A34180FBA">  0x34180FBA:  </span>E8DF F012    TBH        91PC, R2, LSL #1]
-<span id="A34180FBE">  0x34180FBE:  </span>04           DC.B       0x04                     ; '\x04'
-<span id="A34180FBF">  0x34180FBF:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180FC0">  0x34180FC0:  </span>0E           DC.B       0x0E                     ; '\x0E'
-<span id="A34180FC1">  0x34180FC1:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180FC2">  0x34180FC2:  </span>0D           DC.B       0x0D                     ; '\r'
-<span id="A34180FC3">  0x34180FC3:  </span>01           DC.B       0x01                     ; '\x01'
-<span id="A34180FC4">  0x34180FC4:  </span>1B           DC.B       0x1B                     ; '\x1B'
-<span id="A34180FC5">  0x34180FC5:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34180FC6">  0x34180FC6:  </span>6A61         LDR        R1, [R4, #36]
-<span id="A34180FC8">  0x34180FC8:  </span>F249 0200    MOVW       R2, #0x9000
-<span id="A34180FCC">  0x34180FCC:  </span>F2C0 32D0    MOVT       R2, #0x03D0
-<span id="A34180FD0">  0x34180FD0:  </span>F3C1 11C1    UBFX       R1, R1, #7, #2
-<span id="A34180FD4">  0x34180FD4:  </span>FA22 F101    LSR.W      R1, R2, R1
-<span id="A34180FD8">  0x34180FD8:  </span>E0FE         B          46L38                     ; 0x341811D8
-<span id="A34180FDA">  0x34180FDA:  </span>6A21         LDR        R1, [R4, #32]
-<span id="A34180FDC">  0x34180FDC:  </span>0589         LSLS       R1, R1, #22
-<span id="A34180FDE">  0x34180FDE:  </span>F242 4100    MOVW       R1, #0x2400
-<span id="A34180FE2">  0x34180FE2:  </span>F2C0 01F4    MOVT       R1, #244
-<span id="A34180FE6">  0x34180FE6:  </span>F100 80F7    BMI.W      46L38                     ; 0x341811D8
-<span id="A34180FEA">  0x34180FEA:  </span>F640 1100    MOVW       R1, #0x0900
-<span id="A34180FEE">  0x34180FEE:  </span>F2C0 013D    MOVT       R1, #61
-<span id="A34180FF2">  0x34180FF2:  </span>E0F1         B          46L38                     ; 0x341811D8
-<span id="A34180FF4">  0x34180FF4:  </span>F8D4 10A0    LDR.W      R1, [R4, #160]
-<span id="A34180FF8">  0x34180FF8:  </span>2201         MOVS       R2, #1
-<span id="A34180FFA">  0x34180FFA:  </span>FA52 F5A1    UXTAB      R5, R2, R1, ROR #16
-<span id="A34180FFE">  0x34180FFE:  </span>F8D4 10A0    LDR.W      R1, [R4, #160]
-<span id="A34181002">  0x34181002:  </span>F3C1 7201    UBFX       R2, R1, #28, #2
-<span id="A34181006">  0x34181006:  </span>F854 1C20    LDR        R1, [R4, #-32]
-<span id="A3418100A">  0x3418100A:  </span>E8DF F002    TBB        91PC, R2]
-<span id="A3418100E">  0x3418100E:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A3418100F">  0x3418100F:  </span>1C           DC.B       0x1C                     ; '\x1C'
-<span id="A34181010">  0x34181010:  </span>0A           DC.B       0x0A                     ; '\n'
-<span id="A34181011">  0x34181011:  </span>12           DC.B       0x12                     ; '\x12'
-<span id="A34181012">  0x34181012:  </span>05C9         LSLS       R1, R1, #23
-<span id="A34181014">  0x34181014:  </span>D475         BMI        46L30                     ; 0x34181102
-<span id="A34181016">  0x34181016:  </span>6DE1         LDR        R1, [R4, #92]
-<span id="A34181018">  0x34181018:  </span>0109         LSLS       R1, R1, #4
-<span id="A3418101A">  0x3418101A:  </span>F140 80DA    BPL.W      46L36                     ; 0x341811D2
-<span id="A3418101E">  0x3418101E:  </span>6DE1         LDR        R1, [R4, #92]
-<span id="A34181020">  0x34181020:  </span>E019         B          46L26                     ; 0x34181056
-<span id="A34181022">  0x34181022:  </span>0549         LSLS       R1, R1, #21
-<span id="A34181024">  0x34181024:  </span>D41F         BMI        46L28                     ; 0x34181066
-<span id="A34181026">  0x34181026:  </span>6FE1         LDR        R1, [R4, #124]
-<span id="A34181028">  0x34181028:  </span>0109         LSLS       R1, R1, #4
-<span id="A3418102A">  0x3418102A:  </span>F140 80D2    BPL.W      46L36                     ; 0x341811D2
-<span id="A3418102E">  0x3418102E:  </span>6FE1         LDR        R1, [R4, #124]
-<span id="A34181030">  0x34181030:  </span>E011         B          46L26                     ; 0x34181056
-<span id="A34181032">  0x34181032:  </span>0509         LSLS       R1, R1, #20
-<span id="A34181034">  0x34181034:  </span>D43D         BMI        46L29                     ; 0x341810B2
-<span id="A34181036">  0x34181036:  </span>F8D4 108C    LDR.W      R1, [R4, #140]
-<span id="A3418103A">  0x3418103A:  </span>0109         LSLS       R1, R1, #4
-<span id="A3418103C">  0x3418103C:  </span>F140 80C9    BPL.W      46L36                     ; 0x341811D2
-<span id="A34181040">  0x34181040:  </span>F8D4 108C    LDR.W      R1, [R4, #140]
-<span id="A34181044">  0x34181044:  </span>E007         B          46L26                     ; 0x34181056
-<span id="A34181046">  0x34181046:  </span>0589         LSLS       R1, R1, #22
-<span id="A34181048">  0x34181048:  </span>F100 80C0    BMI.W      46L35                     ; 0x341811CC
-<span id="A3418104C">  0x3418104C:  </span>6EE1         LDR        R1, [R4, #108]
-<span id="A3418104E">  0x3418104E:  </span>0109         LSLS       R1, R1, #4
-<span id="A34181050">  0x34181050:  </span>F140 80BF    BPL.W      46L36                     ; 0x341811D2
-<span id="A34181054">  0x34181054:  </span>6EE1         LDR        R1, [R4, #108]
-<br/>.L26:
-<span id="A34181056">  0x34181056:  </span>4606         MOV        R6, R0
-<span id="A34181058">  0x34181058:  </span>F001 40E0    AND        R0, R1, #0x70000000
-<span id="A3418105C">  0x3418105C:  </span>F000 F9C0    BL         <a href="#RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq</a>   ; 0x341813E0
-<span id="A34181060">  0x34181060:  </span>4601         MOV        R1, R0
-<br/>.L27:
-<span id="A34181062">  0x34181062:  </span>4630         MOV        R0, R6
-<span id="A34181064">  0x34181064:  </span>E0B6         B          46L37                     ; 0x341811D4
-<br/>.L28:
-<span id="A34181066">  0x34181066:  </span>F8D4 1084    LDR.W      R1, [R4, #132]
-<span id="A3418106A">  0x3418106A:  </span>0049         LSLS       R1, R1, #1
-<span id="A3418106C">  0x3418106C:  </span>F140 80B1    BPL.W      46L36                     ; 0x341811D2
-<span id="A34181070">  0x34181070:  </span>4606         MOV        R6, R0
-<span id="A34181072">  0x34181072:  </span>6FE0         LDR        R0, [R4, #124]
-<span id="A34181074">  0x34181074:  </span>F000 40E0    AND        R0, R0, #0x70000000
-<span id="A34181078">  0x34181078:  </span>F000 F9B2    BL         <a href="#RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq</a>   ; 0x341813E0
-<span id="A3418107C">  0x3418107C:  </span>0001         MOVS       R1, R0
-<span id="A3418107E">  0x3418107E:  </span>D0F0         BEQ        46L27                     ; 0x34181062
-<span id="A34181080">  0x34181080:  </span>6FE0         LDR        R0, [R4, #124]
-<span id="A34181082">  0x34181082:  </span>F3C0 5205    UBFX       R2, R0, #20, #6
-<span id="A34181086">  0x34181086:  </span>4630         MOV        R0, R6
-<span id="A34181088">  0x34181088:  </span>2A00         CMP        R2, #0
-<span id="A3418108A">  0x3418108A:  </span>F000 80A2    BEQ.W      46L36                     ; 0x341811D2
-<span id="A3418108E">  0x3418108E:  </span>EE00 1A10    VMOV       S0, R1
-<span id="A34181092">  0x34181092:  </span>6FE1         LDR        R1, [R4, #124]
-<span id="A34181094">  0x34181094:  </span>F8D4 3080    LDR.W      R3, [R4, #128]
-<span id="A34181098">  0x34181098:  </span>F3C1 210B    UBFX       R1, R1, #8, #12
-<span id="A3418109C">  0x3418109C:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A341810A0">  0x341810A0:  </span>EE01 1A10    VMOV       S2, R1
-<span id="A341810A4">  0x341810A4:  </span>F8D4 1084    LDR.W      R1, [R4, #132]
-<span id="A341810A8">  0x341810A8:  </span>EE02 3A10    VMOV       S4, R3
-<span id="A341810AC">  0x341810AC:  </span>F8D4 3084    LDR.W      R3, [R4, #132]
-<span id="A341810B0">  0x341810B0:  </span>E120         B          46L48                     ; 0x341812F4
-<br/>.L29:
-<span id="A341810B2">  0x341810B2:  </span>F8D4 1094    LDR.W      R1, [R4, #148]
-<span id="A341810B6">  0x341810B6:  </span>0049         LSLS       R1, R1, #1
-<span id="A341810B8">  0x341810B8:  </span>F140 808B    BPL.W      46L36                     ; 0x341811D2
-<span id="A341810BC">  0x341810BC:  </span>4606         MOV        R6, R0
-<span id="A341810BE">  0x341810BE:  </span>F8D4 008C    LDR.W      R0, [R4, #140]
-<span id="A341810C2">  0x341810C2:  </span>F000 40E0    AND        R0, R0, #0x70000000
-<span id="A341810C6">  0x341810C6:  </span>F000 F98B    BL         <a href="#RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq</a>   ; 0x341813E0
-<span id="A341810CA">  0x341810CA:  </span>0001         MOVS       R1, R0
-<span id="A341810CC">  0x341810CC:  </span>D0C9         BEQ        46L27                     ; 0x34181062
-<span id="A341810CE">  0x341810CE:  </span>F8D4 008C    LDR.W      R0, [R4, #140]
-<span id="A341810D2">  0x341810D2:  </span>F3C0 5205    UBFX       R2, R0, #20, #6
-<span id="A341810D6">  0x341810D6:  </span>4630         MOV        R0, R6
-<span id="A341810D8">  0x341810D8:  </span>2A00         CMP        R2, #0
-<span id="A341810DA">  0x341810DA:  </span>D07A         BEQ        46L36                     ; 0x341811D2
-<span id="A341810DC">  0x341810DC:  </span>EE00 1A10    VMOV       S0, R1
-<span id="A341810E0">  0x341810E0:  </span>F8D4 108C    LDR.W      R1, [R4, #140]
-<span id="A341810E4">  0x341810E4:  </span>F8D4 3090    LDR.W      R3, [R4, #144]
-<span id="A341810E8">  0x341810E8:  </span>F3C1 210B    UBFX       R1, R1, #8, #12
-<span id="A341810EC">  0x341810EC:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A341810F0">  0x341810F0:  </span>EE01 1A10    VMOV       S2, R1
-<span id="A341810F4">  0x341810F4:  </span>F8D4 1094    LDR.W      R1, [R4, #148]
-<span id="A341810F8">  0x341810F8:  </span>EE02 3A10    VMOV       S4, R3
-<span id="A341810FC">  0x341810FC:  </span>F8D4 3094    LDR.W      R3, [R4, #148]
-<span id="A34181100">  0x34181100:  </span>E0F8         B          46L48                     ; 0x341812F4
-<br/>.L30:
-<span id="A34181102">  0x34181102:  </span>6E61         LDR        R1, [R4, #100]
-<span id="A34181104">  0x34181104:  </span>0049         LSLS       R1, R1, #1
-<span id="A34181106">  0x34181106:  </span>D564         BPL        46L36                     ; 0x341811D2
-<span id="A34181108">  0x34181108:  </span>4606         MOV        R6, R0
-<span id="A3418110A">  0x3418110A:  </span>6DE0         LDR        R0, [R4, #92]
-<span id="A3418110C">  0x3418110C:  </span>F000 40E0    AND        R0, R0, #0x70000000
-<span id="A34181110">  0x34181110:  </span>F000 F966    BL         <a href="#RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq</a>   ; 0x341813E0
-<span id="A34181114">  0x34181114:  </span>0001         MOVS       R1, R0
-<span id="A34181116">  0x34181116:  </span>D0A4         BEQ        46L27                     ; 0x34181062
-<span id="A34181118">  0x34181118:  </span>6DE0         LDR        R0, [R4, #92]
-<span id="A3418111A">  0x3418111A:  </span>F3C0 5205    UBFX       R2, R0, #20, #6
-<span id="A3418111E">  0x3418111E:  </span>4630         MOV        R0, R6
-<span id="A34181120">  0x34181120:  </span>2A00         CMP        R2, #0
-<span id="A34181122">  0x34181122:  </span>D056         BEQ        46L36                     ; 0x341811D2
-<span id="A34181124">  0x34181124:  </span>EE00 1A10    VMOV       S0, R1
-<span id="A34181128">  0x34181128:  </span>6DE1         LDR        R1, [R4, #92]
-<span id="A3418112A">  0x3418112A:  </span>6E23         LDR        R3, [R4, #96]
-<span id="A3418112C">  0x3418112C:  </span>F3C1 210B    UBFX       R1, R1, #8, #12
-<span id="A34181130">  0x34181130:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A34181134">  0x34181134:  </span>EE01 1A10    VMOV       S2, R1
-<span id="A34181138">  0x34181138:  </span>6E61         LDR        R1, [R4, #100]
-<span id="A3418113A">  0x3418113A:  </span>EE02 3A10    VMOV       S4, R3
-<span id="A3418113E">  0x3418113E:  </span>6E63         LDR        R3, [R4, #100]
-<span id="A34181140">  0x34181140:  </span>E0D8         B          46L48                     ; 0x341812F4
-<br/>.L31:
-<span id="A34181142">  0x34181142:  </span>4605         MOV        R5, R0
-<span id="A34181144">  0x34181144:  </span>6A81         LDR        R1, [R0, #40]
-<span id="A34181146">  0x34181146:  </span>F8D4 00A4    LDR.W      R0, [R4, #164]
-<span id="A3418114A">  0x3418114A:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A3418114E">  0x3418114E:  </span>F000 F8FD    BL         <a href="#RCC_IC_CheckPLLSources">RCC_IC_CheckPLLSources</a>   ; 0x3418134C
-<span id="A34181152">  0x34181152:  </span>B3C8         CBZ        R0, .L34                 ; 0x341811C8
-<span id="A34181154">  0x34181154:  </span>F8D4 00B4    LDR.W      R0, [R4, #180]
-<span id="A34181158">  0x34181158:  </span>6B29         LDR        R1, [R5, #48]
-<span id="A3418115A">  0x3418115A:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A3418115E">  0x3418115E:  </span>F000 F8F5    BL         <a href="#RCC_IC_CheckPLLSources">RCC_IC_CheckPLLSources</a>   ; 0x3418134C
-<span id="A34181162">  0x34181162:  </span>B388         CBZ        R0, .L34                 ; 0x341811C8
-<span id="A34181164">  0x34181164:  </span>F8D4 00C8    LDR.W      R0, [R4, #200]
-<span id="A34181168">  0x34181168:  </span>6BA9         LDR        R1, [R5, #56]
-<span id="A3418116A">  0x3418116A:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A3418116E">  0x3418116E:  </span>F000 F8ED    BL         <a href="#RCC_IC_CheckPLLSources">RCC_IC_CheckPLLSources</a>   ; 0x3418134C
-<span id="A34181172">  0x34181172:  </span>B348         CBZ        R0, .L34                 ; 0x341811C8
-<span id="A34181174">  0x34181174:  </span>E9D5 210A    LDRD       R2, R1, [R5, #40]
-<span id="A34181178">  0x34181178:  </span>2300         MOVS       R3, #0
-<span id="A3418117A">  0x3418117A:  </span>F6CF 73FF    MOVT       R3, #0xFFFF
-<span id="A3418117E">  0x3418117E:  </span>4628         MOV        R0, R5
-<span id="A34181180">  0x34181180:  </span>6B2E         LDR        R6, [R5, #48]
-<span id="A34181182">  0x34181182:  </span>EB03 4101    ADD.W      R1, R3, R1, LSL #16
-<span id="A34181186">  0x34181186:  </span>430A         ORRS       R2, R1
-<span id="A34181188">  0x34181188:  </span>68A9         LDR        R1, [R5, #8]
-<span id="A3418118A">  0x3418118A:  </span>F8C4 20A4    STR.W      R2, [R4, #164]
-<span id="A3418118E">  0x3418118E:  </span>6B6A         LDR        R2, [R5, #52]
-<span id="A34181190">  0x34181190:  </span>EB03 4202    ADD.W      R2, R3, R2, LSL #16
-<span id="A34181194">  0x34181194:  </span>4332         ORRS       R2, R6
-<span id="A34181196">  0x34181196:  </span>F8C4 20B4    STR.W      R2, [R4, #180]
-<span id="A3418119A">  0x3418119A:  </span>6BEA         LDR        R2, [R5, #60]
-<span id="A3418119C">  0x3418119C:  </span>EB03 4202    ADD.W      R2, R3, R2, LSL #16
-<span id="A341811A0">  0x341811A0:  </span>6BAB         LDR        R3, [R5, #56]
-<span id="A341811A2">  0x341811A2:  </span>431A         ORRS       R2, R3
-<span id="A341811A4">  0x341811A4:  </span>F240 4322    MOVW       R3, #0x0422
-<span id="A341811A8">  0x341811A8:  </span>F8C4 20C8    STR.W      R2, [R4, #200]
-<span id="A341811AC">  0x341811AC:  </span>F648 2240    MOVW       R2, #0x8A40
-<span id="A341811B0">  0x341811B0:  </span>F2C5 6202    MOVT       R2, #0x5602
-<span id="A341811B4">  0x341811B4:  </span>6013         STR        R3, [R2]
-<span id="A341811B6">  0x341811B6:  </span>E027         B          46L40                     ; 0x34181208
-<br/>.L32:
-<span id="A341811B8">  0x341811B8:  </span>F854 1C20    LDR        R1, [R4, #-32]
-<span id="A341811BC">  0x341811BC:  </span>0709         LSLS       R1, R1, #28
-<span id="A341811BE">  0x341811BE:  </span>D503         BPL        46L34                     ; 0x341811C8
-<span id="A341811C0">  0x341811C0:  </span>2100         MOVS       R1, #0
-<span id="A341811C2">  0x341811C2:  </span>E021         B          46L40                     ; 0x34181208
-<br/>.L33:
-<span id="A341811C4">  0x341811C4:  </span>0752         LSLS       R2, R2, #29
-<span id="A341811C6">  0x341811C6:  </span>D41F         BMI        46L40                     ; 0x34181208
-<br/>.L34:
-<span id="A341811C8">  0x341811C8:  </span>2001         MOVS       R0, #1
-<span id="A341811CA">  0x341811CA:  </span>BD70         POP        123R4-R6, PC}
-<br/>.L35:
-<span id="A341811CC">  0x341811CC:  </span>6F61         LDR        R1, [R4, #116]
-<span id="A341811CE">  0x341811CE:  </span>0049         LSLS       R1, R1, #1
-<span id="A341811D0">  0x341811D0:  </span>D472         BMI        46L47                     ; 0x341812B8
-<br/>.L36:
-<span id="A341811D2">  0x341811D2:  </span>2100         MOVS       R1, #0
-<br/>.L37:
-<span id="A341811D4">  0x341811D4:  </span>FBB1 F1F5    UDIV       R1, R1, R5
-<br/>.L38:
-<span id="A341811D8">  0x341811D8:  </span>F242 22AC    MOVW       R2, #0x22AC              ; 0x341822AC = SystemCoreClock
-<span id="A341811DC">  0x341811DC:  </span>F2C3 4218    MOVT       R2, #0x3418              ; 0x341822AC = SystemCoreClock
-<span id="A341811E0">  0x341811E0:  </span>6011         STR        R1, [R2]
-<span id="A341811E2">  0x341811E2:  </span>6801         LDR        R1, [R0]
-<span id="A341811E4">  0x341811E4:  </span>078A         LSLS       R2, R1, #30
-<span id="A341811E6">  0x341811E6:  </span>F57F ADEA    BPL.W      46L6                      ; 0x34180DBE
-<br/>.L39:
-<span id="A341811EA">  0x341811EA:  </span>6881         LDR        R1, [R0, #8]
-<span id="A341811EC">  0x341811EC:  </span>2900         CMP        R1, #0
-<span id="A341811EE">  0x341811EE:  </span>D0E3         BEQ        46L32                     ; 0x341811B8
-<span id="A341811F0">  0x341811F0:  </span>F1B1 7F40    CMP.W      R1, #0x03000000
-<span id="A341811F4">  0x341811F4:  </span>D0A5         BEQ        46L31                     ; 0x34181142
-<span id="A341811F6">  0x341811F6:  </span>F854 2C20    LDR        R2, [R4, #-32]
-<span id="A341811FA">  0x341811FA:  </span>F1B1 7F00    CMP.W      R1, #0x02000000
-<span id="A341811FE">  0x341811FE:  </span>D1E1         BNE        46L33                     ; 0x341811C4
-<span id="A34181200">  0x34181200:  </span>06D1         LSLS       R1, R2, #27
-<span id="A34181202">  0x34181202:  </span>D5E1         BPL        46L34                     ; 0x341811C8
-<span id="A34181204">  0x34181204:  </span>F04F 7100    MOV.W      R1, #0x02000000
-<br/>.L40:
-<span id="A34181208">  0x34181208:  </span>F854 2C04    LDR        R2, [R4, #-4]
-<span id="A3418120C">  0x3418120C:  </span>F241 3688    MOVW       R6, #0x1388
-<span id="A34181210">  0x34181210:  </span>F022 7240    BIC        R2, R2, #0x03000000
-<span id="A34181214">  0x34181214:  </span>430A         ORRS       R2, R1
-<span id="A34181216">  0x34181216:  </span>F844 2C04    STR        R2, [R4, #-4]
-<span id="A3418121A">  0x3418121A:  </span>F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A3418121E">  0x3418121E:  </span>F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181222">  0x34181222:  </span>6813         LDR        R3, [R2]
-<br/>.L41:
-<span id="A34181224">  0x34181224:  </span>F854 5C04    LDR        R5, [R4, #-4]
-<span id="A34181228">  0x34181228:  </span>F005 5540    AND        R5, R5, #0x30000000
-<span id="A3418122C">  0x3418122C:  </span>EBB5 1F01    CMP.W      R5, R1, LSL #4
-<span id="A34181230">  0x34181230:  </span>D005         BEQ        46L42                     ; 0x3418123E
-<span id="A34181232">  0x34181232:  </span>6815         LDR        R5, [R2]
-<span id="A34181234">  0x34181234:  </span>1AED         SUBS       R5, R5, R3
-<span id="A34181236">  0x34181236:  </span>42B5         CMP        R5, R6
-<span id="A34181238">  0x34181238:  </span>D9F4         BLS        46L41                     ; 0x34181224
-<span id="A3418123A">  0x3418123A:  </span>2003         MOVS       R0, #3
-<span id="A3418123C">  0x3418123C:  </span>BD70         POP        123R4-R6, PC}
-<br/>.L42:
-<span id="A3418123E">  0x3418123E:  </span>6801         LDR        R1, [R0]
-<span id="A34181240">  0x34181240:  </span>074A         LSLS       R2, R1, #29
-<span id="A34181242">  0x34181242:  </span>F57F ADBF    BPL.W      46L7                      ; 0x34180DC4
-<br/>.L43:
-<span id="A34181246">  0x34181246:  </span>68C2         LDR        R2, [R0, #12]
-<span id="A34181248">  0x34181248:  </span>6823         LDR        R3, [R4]
-<span id="A3418124A">  0x3418124A:  </span>F403 03E0    AND        R3, R3, #0x700000
-<span id="A3418124E">  0x3418124E:  </span>429A         CMP        R2, R3
-<span id="A34181250">  0x34181250:  </span>BF3F         ITTTT      CC
-<span id="A34181252">  0x34181252:  </span>6823         LDRCC      R3, [R4]
-<span id="A34181254">  0x34181254:  </span>F423 03E0    BICCC      R3, R3, #0x700000
-<span id="A34181258">  0x34181258:  </span>431A         ORRCC      R2, R3
-<span id="A3418125A">  0x3418125A:  </span>6022         STRCC      R2, [R4]
-<span id="A3418125C">  0x3418125C:  </span>070A         LSLS       R2, R1, #28
-<span id="A3418125E">  0x3418125E:  </span>F57F ADB4    BPL.W      46L8                      ; 0x34180DCA
-<br/>.L44:
-<span id="A34181262">  0x34181262:  </span>6902         LDR        R2, [R0, #16]
-<span id="A34181264">  0x34181264:  </span>6823         LDR        R3, [R4]
-<span id="A34181266">  0x34181266:  </span>F003 0307    AND        R3, R3, #7
-<span id="A3418126A">  0x3418126A:  </span>429A         CMP        R2, R3
-<span id="A3418126C">  0x3418126C:  </span>BF3F         ITTTT      CC
-<span id="A3418126E">  0x3418126E:  </span>6823         LDRCC      R3, [R4]
-<span id="A34181270">  0x34181270:  </span>F023 0307    BICCC      R3, R3, #7
-<span id="A34181274">  0x34181274:  </span>431A         ORRCC      R2, R3
-<span id="A34181276">  0x34181276:  </span>6022         STRCC      R2, [R4]
-<span id="A34181278">  0x34181278:  </span>06CA         LSLS       R2, R1, #27
-<span id="A3418127A">  0x3418127A:  </span>F57F ADA9    BPL.W      46L9                      ; 0x34180DD0
-<br/>.L45:
-<span id="A3418127E">  0x3418127E:  </span>6942         LDR        R2, [R0, #20]
-<span id="A34181280">  0x34181280:  </span>6823         LDR        R3, [R4]
-<span id="A34181282">  0x34181282:  </span>F003 0370    AND        R3, R3, #112
-<span id="A34181286">  0x34181286:  </span>429A         CMP        R2, R3
-<span id="A34181288">  0x34181288:  </span>BF3F         ITTTT      CC
-<span id="A3418128A">  0x3418128A:  </span>6823         LDRCC      R3, [R4]
-<span id="A3418128C">  0x3418128C:  </span>F023 0370    BICCC      R3, R3, #112
-<span id="A34181290">  0x34181290:  </span>431A         ORRCC      R2, R3
-<span id="A34181292">  0x34181292:  </span>6022         STRCC      R2, [R4]
-<span id="A34181294">  0x34181294:  </span>068A         LSLS       R2, R1, #26
-<span id="A34181296">  0x34181296:  </span>F57F AD9E    BPL.W      46L10                     ; 0x34180DD6
-<br/>.L46:
-<span id="A3418129A">  0x3418129A:  </span>6982         LDR        R2, [R0, #24]
-<span id="A3418129C">  0x3418129C:  </span>6823         LDR        R3, [R4]
-<span id="A3418129E">  0x3418129E:  </span>F403 43E0    AND        R3, R3, #0x7000
-<span id="A341812A2">  0x341812A2:  </span>429A         CMP        R2, R3
-<span id="A341812A4">  0x341812A4:  </span>BF3F         ITTTT      CC
-<span id="A341812A6">  0x341812A6:  </span>6823         LDRCC      R3, [R4]
-<span id="A341812A8">  0x341812A8:  </span>F423 43E0    BICCC      R3, R3, #0x7000
-<span id="A341812AC">  0x341812AC:  </span>431A         ORRCC      R2, R3
-<span id="A341812AE">  0x341812AE:  </span>6022         STRCC      R2, [R4]
-<span id="A341812B0">  0x341812B0:  </span>0649         LSLS       R1, R1, #25
-<span id="A341812B2">  0x341812B2:  </span>F53F AD92    BMI.W      46L11                     ; 0x34180DDA
-<span id="A341812B6">  0x341812B6:  </span>E59B         B          46L12                     ; 0x34180DF0
-<br/>.L47:
-<span id="A341812B8">  0x341812B8:  </span>4606         MOV        R6, R0
-<span id="A341812BA">  0x341812BA:  </span>6EE0         LDR        R0, [R4, #108]
-<span id="A341812BC">  0x341812BC:  </span>F000 40E0    AND        R0, R0, #0x70000000
-<span id="A341812C0">  0x341812C0:  </span>F000 F88E    BL         <a href="#RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq</a>   ; 0x341813E0
-<span id="A341812C4">  0x341812C4:  </span>0001         MOVS       R1, R0
-<span id="A341812C6">  0x341812C6:  </span>F43F AECC    BEQ.W      46L27                     ; 0x34181062
-<span id="A341812CA">  0x341812CA:  </span>6EE0         LDR        R0, [R4, #108]
-<span id="A341812CC">  0x341812CC:  </span>F3C0 5205    UBFX       R2, R0, #20, #6
-<span id="A341812D0">  0x341812D0:  </span>4630         MOV        R0, R6
-<span id="A341812D2">  0x341812D2:  </span>2A00         CMP        R2, #0
-<span id="A341812D4">  0x341812D4:  </span>F43F AF7D    BEQ.W      46L36                     ; 0x341811D2
-<span id="A341812D8">  0x341812D8:  </span>EE00 1A10    VMOV       S0, R1
-<span id="A341812DC">  0x341812DC:  </span>6EE1         LDR        R1, [R4, #108]
-<span id="A341812DE">  0x341812DE:  </span>6F23         LDR        R3, [R4, #112]
-<span id="A341812E0">  0x341812E0:  </span>F3C1 210B    UBFX       R1, R1, #8, #12
-<span id="A341812E4">  0x341812E4:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A341812E8">  0x341812E8:  </span>EE01 1A10    VMOV       S2, R1
-<span id="A341812EC">  0x341812EC:  </span>6F61         LDR        R1, [R4, #116]
-<span id="A341812EE">  0x341812EE:  </span>EE02 3A10    VMOV       S4, R3
-<span id="A341812F2">  0x341812F2:  </span>6F63         LDR        R3, [R4, #116]
-<br/>.L48:
-<span id="A341812F4">  0x341812F4:  </span>EEB8 2A42    VCVT.F32.U32 S4, S4
-<span id="A341812F8">  0x341812F8:  </span>ED9F 3A13    VLDR       S6, =0x33800000          ; [PC, #76] [0x34181348]
-<span id="A341812FC">  0x341812FC:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A34181300">  0x34181300:  </span>EE22 2A03    VMUL.F32   S4, S4, S6
-<span id="A34181304">  0x34181304:  </span>EEB8 0A40    VCVT.F32.U32 S0, S0
-<span id="A34181308">  0x34181308:  </span>EE32 1A01    VADD.F32   S2, S4, S2
-<span id="A3418130C">  0x3418130C:  </span>F3C1 61C2    UBFX       R1, R1, #27, #3
-<span id="A34181310">  0x34181310:  </span>EE21 0A00    VMUL.F32   S0, S2, S0
-<span id="A34181314">  0x34181314:  </span>EE01 2A10    VMOV       S2, R2
-<span id="A34181318">  0x34181318:  </span>F3C3 6302    UBFX       R3, R3, #24, #3
-<span id="A3418131C">  0x3418131C:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A34181320">  0x34181320:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
-<span id="A34181324">  0x34181324:  </span>EE01 1A10    VMOV       S2, R1
-<span id="A34181328">  0x34181328:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A3418132C">  0x3418132C:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
-<span id="A34181330">  0x34181330:  </span>EE01 3A10    VMOV       S2, R3
-<span id="A34181334">  0x34181334:  </span>EEB8 1A41    VCVT.F32.U32 S2, S2
-<span id="A34181338">  0x34181338:  </span>EE80 0A01    VDIV.F32   S0, S0, S2
-<span id="A3418133C">  0x3418133C:  </span>EEBC 0AC0    VCVT.U32.F32 S0, S0
-<span id="A34181340">  0x34181340:  </span>EE10 1A10    VMOV       R1, S0
-<span id="A34181344">  0x34181344:  </span>E746         B          46L37                     ; 0x341811D4
-<span id="A34181346">  0x34181346:  </span>BF00         NOP
-<span id="A34181348">  0x34181348:  </span>33800000     DC.W       0x33800000
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4">Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4</h2>
-
-<pre>
-<br/><span id="RCC_IC_CheckPLLSources">RCC_IC_CheckPLLSources:</span>
-<span id="A3418134C">  0x3418134C:  </span>F248 0204    MOVW       R2, #0x8004
-<span id="A34181350">  0x34181350:  </span>EA4F 7030    ROR        R0, R0, #28
-<span id="A34181354">  0x34181354:  </span>F2C5 6202    MOVT       R2, #0x5602
-<span id="A34181358">  0x34181358:  </span>2803         CMP        R0, #3
-<span id="A3418135A">  0x3418135A:  </span>D81F         BHI        46L3                      ; 0x3418139C
-<span id="A3418135C">  0x3418135C:  </span>E8DF F000    TBB        91PC, R0]
-<span id="A34181360">  0x34181360:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A34181361">  0x34181361:  </span>18           DC.B       0x18                     ; '\x18'
-<span id="A34181362">  0x34181362:  </span>08           DC.B       0x08                     ; '\b'
-<span id="A34181363">  0x34181363:  </span>11           DC.B       0x11                     ; '\x11'
-<span id="A34181364">  0x34181364:  </span>4610         MOV        R0, R2
-<span id="A34181366">  0x34181366:  </span>F850 3B7C    LDR        R3, [R0], #124
-<span id="A3418136A">  0x3418136A:  </span>05DB         LSLS       R3, R3, #23
-<span id="A3418136C">  0x3418136C:  </span>D505         BPL        46L1                      ; 0x3418137A
-<span id="A3418136E">  0x3418136E:  </span>E00D         B          46L2                      ; 0x3418138C
-<span id="A34181370">  0x34181370:  </span>4610         MOV        R0, R2
-<span id="A34181372">  0x34181372:  </span>F850 3B9C    LDR        R3, [R0], #156
-<span id="A34181376">  0x34181376:  </span>055B         LSLS       R3, R3, #21
-<span id="A34181378">  0x34181378:  </span>D408         BMI        46L2                      ; 0x3418138C
-<br/>.L1:
-<span id="A3418137A">  0x3418137A:  </span>6800         LDR        R0, [R0]
-<span id="A3418137C">  0x3418137C:  </span>F3C0 60C0    UBFX       R0, R0, #27, #1
-<span id="A34181380">  0x34181380:  </span>E00D         B          46L4                      ; 0x3418139E
-<span id="A34181382">  0x34181382:  </span>4610         MOV        R0, R2
-<span id="A34181384">  0x34181384:  </span>F850 3BAC    LDR        R3, [R0], #172
-<span id="A34181388">  0x34181388:  </span>051B         LSLS       R3, R3, #20
-<span id="A3418138A">  0x3418138A:  </span>D5F6         BPL        46L1                      ; 0x3418137A
-<br/>.L2:
-<span id="A3418138C">  0x3418138C:  </span>2001         MOVS       R0, #1
-<span id="A3418138E">  0x3418138E:  </span>E006         B          46L4                      ; 0x3418139E
-<span id="A34181390">  0x34181390:  </span>4610         MOV        R0, R2
-<span id="A34181392">  0x34181392:  </span>F850 3B8C    LDR        R3, [R0], #140
-<span id="A34181396">  0x34181396:  </span>059B         LSLS       R3, R3, #22
-<span id="A34181398">  0x34181398:  </span>D4F8         BMI        46L2                      ; 0x3418138C
-<span id="A3418139A">  0x3418139A:  </span>E7EE         B          46L1                      ; 0x3418137A
-<br/>.L3:
-<span id="A3418139C">  0x3418139C:  </span>2000         MOVS       R0, #0
-<br/>.L4:
-<span id="A3418139E">  0x3418139E:  </span>EA4F 7131    ROR        R1, R1, #28
-<span id="A341813A2">  0x341813A2:  </span>2903         CMP        R1, #3
-<span id="A341813A4">  0x341813A4:  </span>D81A         BHI        46L7                      ; 0x341813DC
-<span id="A341813A6">  0x341813A6:  </span>E8DF F001    TBB        91PC, R1]
-<span id="A341813AA">  0x341813AA:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A341813AB">  0x341813AB:  </span>14           DC.B       0x14                     ; '\x14'
-<span id="A341813AC">  0x341813AC:  </span>07           DC.B       0x07                     ; '\x07'
-<span id="A341813AD">  0x341813AD:  </span>0F           DC.B       0x0F                     ; '\x0F'
-<span id="A341813AE">  0x341813AE:  </span>F852 1B7C    LDR        R1, [R2], #124
-<span id="A341813B2">  0x341813B2:  </span>05C9         LSLS       R1, R1, #23
-<span id="A341813B4">  0x341813B4:  </span>D504         BPL        46L5                      ; 0x341813C0
-<span id="A341813B6">  0x341813B6:  </span>4770         BX         LR
-<span id="A341813B8">  0x341813B8:  </span>F852 1B9C    LDR        R1, [R2], #156
-<span id="A341813BC">  0x341813BC:  </span>0549         LSLS       R1, R1, #21
-<span id="A341813BE">  0x341813BE:  </span>D402         BMI        46L6                      ; 0x341813C6
-<br/>.L5:
-<span id="A341813C0">  0x341813C0:  </span>6811         LDR        R1, [R2]
-<span id="A341813C2">  0x341813C2:  </span>EA00 60D1    AND.W      R0, R0, R1, LSR #27
-<br/>.L6:
-<span id="A341813C6">  0x341813C6:  </span>4770         BX         LR
-<span id="A341813C8">  0x341813C8:  </span>F852 1BAC    LDR        R1, [R2], #172
-<span id="A341813CC">  0x341813CC:  </span>0509         LSLS       R1, R1, #20
-<span id="A341813CE">  0x341813CE:  </span>D5F7         BPL        46L5                      ; 0x341813C0
-<span id="A341813D0">  0x341813D0:  </span>4770         BX         LR
-<span id="A341813D2">  0x341813D2:  </span>F852 1B8C    LDR        R1, [R2], #140
-<span id="A341813D6">  0x341813D6:  </span>0589         LSLS       R1, R1, #22
-<span id="A341813D8">  0x341813D8:  </span>D5F2         BPL        46L5                      ; 0x341813C0
-<span id="A341813DA">  0x341813DA:  </span>4770         BX         LR
-<br/>.L7:
-<span id="A341813DC">  0x341813DC:  </span>2000         MOVS       R0, #0
-<span id="A341813DE">  0x341813DE:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4">Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4</h2>
-
-<pre>
-<br/><span id="RCCEx_GetPLLSourceFreq">RCCEx_GetPLLSourceFreq:</span>
-<span id="A341813E0">  0x341813E0:  </span>EA4F 7030    ROR        R0, R0, #28
-<span id="A341813E4">  0x341813E4:  </span>2803         CMP        R0, #3
-<span id="A341813E6">  0x341813E6:  </span>D82D         BHI        46L1                      ; 0x34181444
-<span id="A341813E8">  0x341813E8:  </span>E8DF F000    TBB        91PC, R0]
-<span id="A341813EC">  0x341813EC:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A341813ED">  0x341813ED:  </span>25           DC.B       0x25                     ; '%'
-<span id="A341813EE">  0x341813EE:  </span>13           DC.B       0x13                     ; '\x13'
-<span id="A341813EF">  0x341813EF:  </span>20           DC.B       0x20                     ; ' '
-<span id="A341813F0">  0x341813F0:  </span>F248 0004    MOVW       R0, #0x8004
-<span id="A341813F4">  0x341813F4:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A341813F8">  0x341813F8:  </span>6801         LDR        R1, [R0]
-<span id="A341813FA">  0x341813FA:  </span>0709         LSLS       R1, R1, #28
-<span id="A341813FC">  0x341813FC:  </span>D522         BPL        46L1                      ; 0x34181444
-<span id="A341813FE">  0x341813FE:  </span>6C40         LDR        R0, [R0, #68]
-<span id="A34181400">  0x34181400:  </span>F249 0100    MOVW       R1, #0x9000
-<span id="A34181404">  0x34181404:  </span>F2C0 31D0    MOVT       R1, #0x03D0
-<span id="A34181408">  0x34181408:  </span>F3C0 10C1    UBFX       R0, R0, #7, #2
-<span id="A3418140C">  0x3418140C:  </span>FA21 F000    LSR.W      R0, R1, R0
-<span id="A34181410">  0x34181410:  </span>4770         BX         LR
-<span id="A34181412">  0x34181412:  </span>F248 0004    MOVW       R0, #0x8004
-<span id="A34181416">  0x34181416:  </span>F646 4100    MOVW       R1, #0x6C00
-<span id="A3418141A">  0x3418141A:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A3418141E">  0x3418141E:  </span>6800         LDR        R0, [R0]
-<span id="A34181420">  0x34181420:  </span>F2C0 21DC    MOVT       R1, #0x02DC
-<span id="A34181424">  0x34181424:  </span>06C0         LSLS       R0, R0, #27
-<span id="A34181426">  0x34181426:  </span>EA01 70E0    AND.W      R0, R1, R0, ASR #31
-<span id="A3418142A">  0x3418142A:  </span>4770         BX         LR
-<span id="A3418142C">  0x3418142C:  </span>F248 0000    MOVW       R0, #0x8000
-<span id="A34181430">  0x34181430:  </span>F2C0 00BB    MOVT       R0, #187
-<span id="A34181434">  0x34181434:  </span>4770         BX         LR
-<span id="A34181436">  0x34181436:  </span>F248 0004    MOVW       R0, #0x8004
-<span id="A3418143A">  0x3418143A:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A3418143E">  0x3418143E:  </span>6801         LDR        R1, [R0]
-<span id="A34181440">  0x34181440:  </span>0749         LSLS       R1, R1, #29
-<span id="A34181442">  0x34181442:  </span>D401         BMI        46L2                      ; 0x34181448
-<br/>.L1:
-<span id="A34181444">  0x34181444:  </span>2000         MOVS       R0, #0
-<span id="A34181446">  0x34181446:  </span>4770         BX         LR
-<br/>.L2:
-<span id="A34181448">  0x34181448:  </span>6C00         LDR        R0, [R0, #64]
-<span id="A3418144A">  0x3418144A:  </span>0580         LSLS       R0, R0, #22
-<span id="A3418144C">  0x3418144C:  </span>F242 4000    MOVW       R0, #0x2400
-<span id="A34181450">  0x34181450:  </span>F2C0 00F4    MOVT       R0, #244
-<span id="A34181454">  0x34181454:  </span>BF5C         ITT        PL
-<span id="A34181456">  0x34181456:  </span>F640 1000    MOVWPL     R0, #0x0900
-<span id="A3418145A">  0x3418145A:  </span>F2C0 003D    MOVTPL     R0, #61
-<span id="A3418145E">  0x3418145E:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4">Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4</h2>
-
-<pre>
-<span id="A34181460">  0x34181460:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181461">  0x34181461:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181462">  0x34181462:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181463">  0x34181463:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181464">  0x34181464:  </span>01           DC.B       0x01                     ; '\x01'
-<span id="A34181465">  0x34181465:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181466">  0x34181466:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181467">  0x34181467:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181468">  0x34181468:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A34181469">  0x34181469:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418146A">  0x3418146A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418146B">  0x3418146B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418146C">  0x3418146C:  </span>03           DC.B       0x03                     ; '\x03'
-<span id="A3418146D">  0x3418146D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418146E">  0x3418146E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418146F">  0x3418146F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181470">  0x34181470:  </span>04           DC.B       0x04                     ; '\x04'
-<span id="A34181471">  0x34181471:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181472">  0x34181472:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181473">  0x34181473:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181474">  0x34181474:  </span>05           DC.B       0x05                     ; '\x05'
-<span id="A34181475">  0x34181475:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181476">  0x34181476:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181477">  0x34181477:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181478">  0x34181478:  </span>06           DC.B       0x06                     ; '\x06'
-<span id="A34181479">  0x34181479:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418147A">  0x3418147A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418147B">  0x3418147B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418147C">  0x3418147C:  </span>07           DC.B       0x07                     ; '\x07'
-<span id="A3418147D">  0x3418147D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418147E">  0x3418147E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418147F">  0x3418147F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181480">  0x34181480:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181481">  0x34181481:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181482">  0x34181482:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181483">  0x34181483:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181484">  0x34181484:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181485">  0x34181485:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181486">  0x34181486:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181487">  0x34181487:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181488">  0x34181488:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181489">  0x34181489:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148A">  0x3418148A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148B">  0x3418148B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148C">  0x3418148C:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148D">  0x3418148D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148E">  0x3418148E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418148F">  0x3418148F:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181490">  0x34181490:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181491">  0x34181491:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181492">  0x34181492:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181493">  0x34181493:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181494">  0x34181494:  </span>08           DC.B       0x08                     ; '\b'
-<span id="A34181495">  0x34181495:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181496">  0x34181496:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181497">  0x34181497:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A34181498">  0x34181498:  </span>09           DC.B       0x09                     ; '\t'
-<span id="A34181499">  0x34181499:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418149A">  0x3418149A:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418149B">  0x3418149B:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418149C">  0x3418149C:  </span>0A           DC.B       0x0A                     ; '\n'
-<span id="A3418149D">  0x3418149D:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418149E">  0x3418149E:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A3418149F">  0x3418149F:  </span>00           DC.B       0x00                     ; '\0'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4">Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4</h2>
-
-<pre>
-<span id="A341814A0">  0x341814A0:  </span>03           DC.B       0x03                     ; '\x03'
-<span id="A341814A1">  0x341814A1:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A2">  0x341814A2:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A3">  0x341814A3:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A4">  0x341814A4:  </span>02           DC.B       0x02                     ; '\x02'
-<span id="A341814A5">  0x341814A5:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A6">  0x341814A6:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A7">  0x341814A7:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814A8">  0x341814A8:  </span>04           DC.B       0x04                     ; '\x04'
-<span id="A341814A9">  0x341814A9:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814AA">  0x341814AA:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814AB">  0x341814AB:  </span>00           DC.B       0x00                     ; '\0'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4">Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4</h2>
-
-<pre>
-<br/><span id="_start">_start:</span>
-<span id="A341814AC">  0x341814AC:  </span>4C03         LDR        R4, =0x341822D4          ; [PC, #12] [0x341814BC] 
-<br/>.L1:
-<span id="A341814AE">  0x341814AE:  </span>6820         LDR        R0, [R4]
-<span id="A341814B0">  0x341814B0:  </span>3404         ADDS       R4, #4
-<span id="A341814B2">  0x341814B2:  </span>4780         BLX        R0
-<span id="A341814B4">  0x341814B4:  </span>E7FB         B          46L1                      ; 0x341814AE
-<br/><span id="__SEGGER_init_done">__SEGGER_init_done:</span>
-<span id="__startup_complete">__startup_complete:</span>
-<span id="A341814B6">  0x341814B6:  </span>F7FF F949    BL         <a href="#main">main</a>                     ; 0x3418074C
-<br/><span id="exit">exit:</span>
-<span id="A341814BA">  0x341814BA:  </span>E7FE         B          <a href="#exit">exit</a>                     ; 0x341814BA
-<span id="A341814BC">  0x341814BC:  </span>341822D4     DC.W       341822D4               ; R_ARM_ABS32
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4">Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4</h2>
-
-<pre>
-<br/><span id="reset_handler">reset_handler:</span>
-<span id="Reset_Handler">Reset_Handler:</span>
-<span id="A341814C0">  0x341814C0:  </span>4909         LDR        R1, =0x341FE000          ; [PC, #36] [0x341814E8] 
-<span id="A341814C2">  0x341814C2:  </span>F381 880A    MSR        MSPLIM, R1
-<span id="A341814C6">  0x341814C6:  </span>F04F 0100    MOV.W      R1, #0
-<span id="A341814CA">  0x341814CA:  </span>F381 880B    MSR        PSPLIM, R1
-<span id="A341814CE">  0x341814CE:  </span>F000 F851    BL         <a href="#SystemInit">SystemInit</a>               ; 0x34181574
-<span id="A341814D2">  0x341814D2:  </span>F64E 5088    MOVW       R0, #0xED88
-<span id="A341814D6">  0x341814D6:  </span>F2CE 0000    MOVT       R0, #0xE000
-<span id="A341814DA">  0x341814DA:  </span>6801         LDR        R1, [R0]
-<span id="A341814DC">  0x341814DC:  </span>F451 0170    ORRS       R1, R1, #0xF00000
-<span id="A341814E0">  0x341814E0:  </span>6001         STR        R1, [R0]
-<span id="A341814E2">  0x341814E2:  </span>F7FF FFE3    BL         <a href="#_start">_start</a>                   ; 0x341814AC
-<span id="A341814E6">  0x341814E6:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814E7">  0x341814E7:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341814E8">  0x341814E8:  </span>341FE000     DC.W       341FE000               ; R_ARM_ABS32
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4">Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4</h2>
-
-<pre>
-<br/><span id="__aeabi_memclr">__aeabi_memclr:</span>
-<span id="__aeabi_memclr8">__aeabi_memclr8:</span>
-<span id="__aeabi_memclr4">__aeabi_memclr4:</span>
-<span id="A341814EC">  0x341814EC:  </span>2200         MOVS       R2, #0
-<br/><span id="__aeabi_memset8">__aeabi_memset8:</span>
-<span id="__aeabi_memset4">__aeabi_memset4:</span>
-<span id="__aeabi_memset">__aeabi_memset:</span>
-<span id="A341814EE">  0x341814EE:  </span>000B         MOVS       R3, R1
-<span id="A341814F0">  0x341814F0:  </span>0011         MOVS       R1, R2
-<span id="A341814F2">  0x341814F2:  </span>001A         MOVS       R2, R3
-<br/><span id="memset">memset:</span>
-<span id="A341814F4">  0x341814F4:  </span>4684         MOV        R12, R0
-<span id="A341814F6">  0x341814F6:  </span>B35A         CBZ        R2, .L7                  ; 0x34181550
-<br/>.L1:
-<span id="A341814F8">  0x341814F8:  </span>0783         LSLS       R3, R0, #30
-<span id="A341814FA">  0x341814FA:  </span>D004         BEQ        46L2                      ; 0x34181506
-<span id="A341814FC">  0x341814FC:  </span>F800 1B01    STRB       R1, [R0], #1
-<span id="A34181500">  0x34181500:  </span>1E52         SUBS       R2, R2, #1
-<span id="A34181502">  0x34181502:  </span>D1F9         BNE        46L1                      ; 0x341814F8
-<span id="A34181504">  0x34181504:  </span>E024         B          46L7                      ; 0x34181550
-<br/>.L2:
-<span id="A34181506">  0x34181506:  </span>B2C9         UXTB       R1, R1
-<span id="A34181508">  0x34181508:  </span>EA41 2101    ORR.W      R1, R1, R1, LSL #8
-<span id="A3418150C">  0x3418150C:  </span>EA41 4101    ORR.W      R1, R1, R1, LSL #16
-<span id="A34181510">  0x34181510:  </span>2A20         CMP        R2, #32
-<span id="A34181512">  0x34181512:  </span>D311         BCC        46L4                      ; 0x34181538
-<span id="A34181514">  0x34181514:  </span>3A20         SUBS       R2, #32
-<span id="A34181516">  0x34181516:  </span>E92D 03F0    PUSH.W     123R4-R9}
-<span id="A3418151A">  0x3418151A:  </span>460B         MOV        R3, R1
-<span id="A3418151C">  0x3418151C:  </span>460C         MOV        R4, R1
-<span id="A3418151E">  0x3418151E:  </span>460D         MOV        R5, R1
-<span id="A34181520">  0x34181520:  </span>460E         MOV        R6, R1
-<span id="A34181522">  0x34181522:  </span>460F         MOV        R7, R1
-<span id="A34181524">  0x34181524:  </span>4688         MOV        R8, R1
-<span id="A34181526">  0x34181526:  </span>4689         MOV        R9, R1
-<br/>.L3:
-<span id="A34181528">  0x34181528:  </span>E8A0 03FA    STM.W      R0!, {R1, R3-R9}
-<span id="A3418152C">  0x3418152C:  </span>3A20         SUBS       R2, #32
-<span id="A3418152E">  0x3418152E:  </span>D2FB         BCS        46L3                      ; 0x34181528
-<span id="A34181530">  0x34181530:  </span>E8BD 03F0    POP.W      123R4-R9}
-<span id="A34181534">  0x34181534:  </span>3220         ADDS       R2, #32
-<span id="A34181536">  0x34181536:  </span>D00B         BEQ        46L7                      ; 0x34181550
-<br/>.L4:
-<span id="A34181538">  0x34181538:  </span>2A04         CMP        R2, #4
-<span id="A3418153A">  0x3418153A:  </span>D305         BCC        46L6                      ; 0x34181548
-<br/>.L5:
-<span id="A3418153C">  0x3418153C:  </span>F840 1B04    STR        R1, [R0], #4
-<span id="A34181540">  0x34181540:  </span>1F12         SUBS       R2, R2, #4
-<span id="A34181542">  0x34181542:  </span>D005         BEQ        46L7                      ; 0x34181550
-<span id="A34181544">  0x34181544:  </span>2A04         CMP        R2, #4
-<span id="A34181546">  0x34181546:  </span>D2F9         BCS        46L5                      ; 0x3418153C
-<br/>.L6:
-<span id="A34181548">  0x34181548:  </span>F800 1B01    STRB       R1, [R0], #1
-<span id="A3418154C">  0x3418154C:  </span>1E52         SUBS       R2, R2, #1
-<span id="A3418154E">  0x3418154E:  </span>D1FB         BNE        46L6                      ; 0x34181548
-<br/>.L7:
-<span id="A34181550">  0x34181550:  </span>4660         MOV        R0, R12
-<span id="A34181552">  0x34181552:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="NMI_Handler">NMI_Handler:</span>
-<span id="A34181554">  0x34181554:  </span>E7FE         B          <a href="#NMI_Handler">NMI_Handler</a>              ; 0x34181554
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="PVD_PVM_IRQHandler">PVD_PVM_IRQHandler:</span>
-<span id="A34181556">  0x34181556:  </span>E7FE         B          <a href="#PVD_PVM_IRQHandler">PVD_PVM_IRQHandler</a>       ; 0x34181556
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="HardFault_Handler">HardFault_Handler:</span>
-<span id="A34181558">  0x34181558:  </span>E7FE         B          <a href="#HardFault_Handler">HardFault_Handler</a>        ; 0x34181558
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="DTS_IRQHandler">DTS_IRQHandler:</span>
-<span id="A3418155A">  0x3418155A:  </span>E7FE         B          <a href="#DTS_IRQHandler">DTS_IRQHandler</a>           ; 0x3418155A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="MemManage_Handler">MemManage_Handler:</span>
-<span id="A3418155C">  0x3418155C:  </span>E7FE         B          <a href="#MemManage_Handler">MemManage_Handler</a>        ; 0x3418155C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RCC_IRQHandler">RCC_IRQHandler:</span>
-<span id="A3418155E">  0x3418155E:  </span>E7FE         B          <a href="#RCC_IRQHandler">RCC_IRQHandler</a>           ; 0x3418155E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="BusFault_Handler">BusFault_Handler:</span>
-<span id="A34181560">  0x34181560:  </span>E7FE         B          <a href="#BusFault_Handler">BusFault_Handler</a>         ; 0x34181560
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LOCKUP_IRQHandler">LOCKUP_IRQHandler:</span>
-<span id="A34181562">  0x34181562:  </span>E7FE         B          <a href="#LOCKUP_IRQHandler">LOCKUP_IRQHandler</a>        ; 0x34181562
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="UsageFault_Handler">UsageFault_Handler:</span>
-<span id="A34181564">  0x34181564:  </span>E7FE         B          <a href="#UsageFault_Handler">UsageFault_Handler</a>       ; 0x34181564
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler:</span>
-<span id="A34181566">  0x34181566:  </span>E7FE         B          <a href="#CACHE_ECC_IRQHandler">CACHE_ECC_IRQHandler</a>     ; 0x34181566
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="SVC_Handler">SVC_Handler:</span>
-<span id="A34181568">  0x34181568:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TCM_ECC_IRQHandler">TCM_ECC_IRQHandler:</span>
-<span id="A3418156A">  0x3418156A:  </span>E7FE         B          <a href="#TCM_ECC_IRQHandler">TCM_ECC_IRQHandler</a>       ; 0x3418156A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="DebugMon_Handler">DebugMon_Handler:</span>
-<span id="A3418156C">  0x3418156C:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="BCK_ECC_IRQHandler">BCK_ECC_IRQHandler:</span>
-<span id="A3418156E">  0x3418156E:  </span>E7FE         B          <a href="#BCK_ECC_IRQHandler">BCK_ECC_IRQHandler</a>       ; 0x3418156E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4">Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4</h2>
-
-<pre>
-<br/><span id="PendSV_Handler">PendSV_Handler:</span>
-<span id="A34181570">  0x34181570:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FPU_IRQHandler">FPU_IRQHandler:</span>
-<span id="A34181572">  0x34181572:  </span>E7FE         B          <a href="#FPU_IRQHandler">FPU_IRQHandler</a>           ; 0x34181572
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4">Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4</h2>
-
-<pre>
-<br/><span id="SystemInit">SystemInit:</span>
-<span id="A34181574">  0x34181574:  </span>B530         PUSH       123R4-R5, LR}
-<span id="A34181576">  0x34181576:  </span>F240 4100    MOVW       R1, #0x0400              ; 0x34180400 = g_pfnVectors
-<span id="A3418157A">  0x3418157A:  </span>F64E 50D8    MOVW       R0, #0xEDD8
-<span id="A3418157E">  0x3418157E:  </span>F648 2C18    MOVW       R12, #0x8A18
-<span id="A34181582">  0x34181582:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x34180400 = g_pfnVectors
-<span id="A34181586">  0x34181586:  </span>F2CE 0000    MOVT       R0, #0xE000
-<span id="A3418158A">  0x3418158A:  </span>2200         MOVS       R2, #0
-<span id="A3418158C">  0x3418158C:  </span>F2C5 6C02    MOVT       R12, #0x5602
-<span id="A34181590">  0x34181590:  </span>2302         MOVS       R3, #2
-<span id="A34181592">  0x34181592:  </span>F840 1CD0    STR        R1, [R0, #-208]
-<span id="A34181596">  0x34181596:  </span>2101         MOVS       R1, #1
-<span id="A34181598">  0x34181598:  </span>F60C 0E08    ADDW       LR, R12, #0x0808
-<span id="A3418159C">  0x3418159C:  </span>F8CC 1000    STR.W      R1, [R12]
-<span id="A341815A0">  0x341815A0:  </span>F8CC 1800    STR.W      R1, [R12, #0x0800]
-<span id="A341815A4">  0x341815A4:  </span>F8CE 1038    STR.W      R1, [LR, #56]
-<span id="A341815A8">  0x341815A8:  </span>6002         STR        R2, [R0]
-<span id="A341815AA">  0x341815AA:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815AC">  0x341815AC:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815AE">  0x341815AE:  </span>6001         STR        R1, [R0]
-<span id="A341815B0">  0x341815B0:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815B2">  0x341815B2:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815B4">  0x341815B4:  </span>6003         STR        R3, [R0]
-<span id="A341815B6">  0x341815B6:  </span>2303         MOVS       R3, #3
-<span id="A341815B8">  0x341815B8:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815BA">  0x341815BA:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815BC">  0x341815BC:  </span>6003         STR        R3, [R0]
-<span id="A341815BE">  0x341815BE:  </span>2304         MOVS       R3, #4
-<span id="A341815C0">  0x341815C0:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815C2">  0x341815C2:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815C4">  0x341815C4:  </span>6003         STR        R3, [R0]
-<span id="A341815C6">  0x341815C6:  </span>2305         MOVS       R3, #5
-<span id="A341815C8">  0x341815C8:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815CA">  0x341815CA:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815CC">  0x341815CC:  </span>6003         STR        R3, [R0]
-<span id="A341815CE">  0x341815CE:  </span>2306         MOVS       R3, #6
-<span id="A341815D0">  0x341815D0:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815D2">  0x341815D2:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815D4">  0x341815D4:  </span>6003         STR        R3, [R0]
-<span id="A341815D6">  0x341815D6:  </span>2307         MOVS       R3, #7
-<span id="A341815D8">  0x341815D8:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815DA">  0x341815DA:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815DC">  0x341815DC:  </span>6003         STR        R3, [R0]
-<span id="A341815DE">  0x341815DE:  </span>6042         STR        R2, [R0, #4]
-<span id="A341815E0">  0x341815E0:  </span>6082         STR        R2, [R0, #8]
-<span id="A341815E2">  0x341815E2:  </span>F5AC 62F4    SUB.W      R2, R12, #0x07A0
-<span id="A341815E6">  0x341815E6:  </span>F8CC 1060    STR.W      R1, [R12, #96]
-<span id="A341815EA">  0x341815EA:  </span>6813         LDR        R3, [R2]
-<span id="A341815EC">  0x341815EC:  </span>F850 4CD0    LDR        R4, [R0, #-208]
-<span id="A341815F0">  0x341815F0:  </span>F248 0310    MOVW       R3, #0x8010
-<span id="A341815F4">  0x341815F4:  </span>F2C5 6300    MOVT       R3, #0x5600
-<span id="A341815F8">  0x341815F8:  </span>601C         STR        R4, [R3]
-<span id="A341815FA">  0x341815FA:  </span>F644 043C    MOVW       R4, #0x483C
-<span id="A341815FE">  0x341815FE:  </span>F2C5 6402    MOVT       R4, #0x5602
-<span id="A34181602">  0x34181602:  </span>F854 5C08    LDR        R5, [R4, #-8]
-<span id="A34181606">  0x34181606:  </span>F445 7580    ORR        R5, R5, #0x0100
-<span id="A3418160A">  0x3418160A:  </span>F844 5C08    STR        R5, [R4, #-8]
-<span id="A3418160E">  0x3418160E:  </span>F854 5C04    LDR        R5, [R4, #-4]
-<span id="A34181612">  0x34181612:  </span>F445 7580    ORR        R5, R5, #0x0100
-<span id="A34181616">  0x34181616:  </span>F844 5C04    STR        R5, [R4, #-4]
-<span id="A3418161A">  0x3418161A:  </span>6825         LDR        R5, [R4]
-<span id="A3418161C">  0x3418161C:  </span>F445 7540    ORR        R5, R5, #0x0300
-<span id="A34181620">  0x34181620:  </span>6025         STR        R5, [R4]
-<span id="A34181622">  0x34181622:  </span>F240 2587    MOVW       R5, #0x0287
-<span id="A34181626">  0x34181626:  </span>645D         STR        R5, [R3, #68]
-<span id="A34181628">  0x34181628:  </span>64DD         STR        R5, [R3, #76]
-<span id="A3418162A">  0x3418162A:  </span>635D         STR        R5, [R3, #52]
-<span id="A3418162C">  0x3418162C:  </span>63DD         STR        R5, [R3, #60]
-<span id="A3418162E">  0x3418162E:  </span>655D         STR        R5, [R3, #84]
-<span id="A34181630">  0x34181630:  </span>6825         LDR        R5, [R4]
-<span id="A34181632">  0x34181632:  </span>F445 5580    ORR        R5, R5, #0x1000
-<span id="A34181636">  0x34181636:  </span>6025         STR        R5, [R4]
-<span id="A34181638">  0x34181638:  </span>6825         LDR        R5, [R4]
-<span id="A3418163A">  0x3418163A:  </span>F045 0510    ORR        R5, R5, #16
-<span id="A3418163E">  0x3418163E:  </span>6025         STR        R5, [R4]
-<span id="A34181640">  0x34181640:  </span>6824         LDR        R4, [R4]
-<span id="A34181642">  0x34181642:  </span>F852 4C04    LDR        R4, [R2, #-4]
-<span id="A34181646">  0x34181646:  </span>F444 4400    ORR        R4, R4, #0x8000
-<span id="A3418164A">  0x3418164A:  </span>F842 4C04    STR        R4, [R2, #-4]
-<span id="A3418164E">  0x3418164E:  </span>6814         LDR        R4, [R2]
-<span id="A34181650">  0x34181650:  </span>F044 0410    ORR        R4, R4, #16
-<span id="A34181654">  0x34181654:  </span>6014         STR        R4, [R2]
-<span id="A34181656">  0x34181656:  </span>6814         LDR        R4, [R2]
-<span id="A34181658">  0x34181658:  </span>6814         LDR        R4, [R2]
-<span id="A3418165A">  0x3418165A:  </span>F024 0410    BIC        R4, R4, #16
-<span id="A3418165E">  0x3418165E:  </span>6014         STR        R4, [R2]
-<span id="A34181660">  0x34181660:  </span>F44F 5240    MOV.W      R2, #0x3000
-<span id="A34181664">  0x34181664:  </span>F8CC 2008    STR.W      R2, [R12, #8]
-<span id="A34181668">  0x34181668:  </span>F8CE 2000    STR.W      R2, [LR]
-<span id="A3418166C">  0x3418166C:  </span>2240         MOVS       R2, #64
-<span id="A3418166E">  0x3418166E:  </span>F8CC 100C    STR.W      R1, [R12, #12]
-<span id="A34181672">  0x34181672:  </span>F8CE 1004    STR.W      R1, [LR, #4]
-<span id="A34181676">  0x34181676:  </span>F8CE 1044    STR.W      R1, [LR, #68]
-<span id="A3418167A">  0x3418167A:  </span>F8CE 203C    STR.W      R2, [LR, #60]
-<span id="A3418167E">  0x3418167E:  </span>681A         LDR        R2, [R3]
-<span id="A34181680">  0x34181680:  </span>F8CE 1058    STR.W      R1, [LR, #88]
-<span id="A34181684">  0x34181684:  </span>F850 1C50    LDR        R1, [R0, #-80]
-<span id="A34181688">  0x34181688:  </span>F441 0170    ORR        R1, R1, #0xF00000
-<span id="A3418168C">  0x3418168C:  </span>F840 1C50    STR        R1, [R0, #-80]
-<span id="A34181690">  0x34181690:  </span>F64E 5088    MOVW       R0, #0xED88
-<span id="A34181694">  0x34181694:  </span>F2CE 0002    MOVT       R0, #0xE002
-<span id="A34181698">  0x34181698:  </span>6801         LDR        R1, [R0]
-<span id="A3418169A">  0x3418169A:  </span>F441 0170    ORR        R1, R1, #0xF00000
-<span id="A3418169E">  0x3418169E:  </span>6001         STR        R1, [R0]
-<span id="A341816A0">  0x341816A0:  </span>BD30         POP        123R4-R5, PC}
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RTC_S_IRQHandler">RTC_S_IRQHandler:</span>
-<span id="A341816A2">  0x341816A2:  </span>E7FE         B          <a href="#RTC_S_IRQHandler">RTC_S_IRQHandler</a>         ; 0x341816A2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4">Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4</h2>
-
-<pre>
-<br/><span id="HAL_GPIO_Init">HAL_GPIO_Init:</span>
-<span id="A341816A4">  0x341816A4:  </span>E92D 4FF0    PUSH.W     123R4-R11, LR}
-<span id="A341816A8">  0x341816A8:  </span>B083         SUB        SP, SP, #12
-<span id="A341816AA">  0x341816AA:  </span>680C         LDR        R4, [R1]
-<span id="A341816AC">  0x341816AC:  </span>2C00         CMP        R4, #0
-<span id="A341816AE">  0x341816AE:  </span>F000 80C7    BEQ.W      46L6                      ; 0x34181840
-<span id="A341816B2">  0x341816B2:  </span>F245 0E00    MOVW       LR, #0x5000
-<span id="A341816B6">  0x341816B6:  </span>F100 4328    ADD.W      R3, R0, #0xA8000000
-<span id="A341816BA">  0x341816BA:  </span>F2C5 6E02    MOVT       LR, #0x5602
-<span id="A341816BE">  0x341816BE:  </span>F103 73FF    ADD.W      R3, R3, #0x01FE0000
-<span id="A341816C2">  0x341816C2:  </span>EA4F 22B3    ROR        R2, R3, #10
-<span id="A341816C6">  0x341816C6:  </span>F5AE 5380    SUB.W      R3, LR, #0x1000
-<span id="A341816CA">  0x341816CA:  </span>4298         CMP        R0, R3
-<span id="A341816CC">  0x341816CC:  </span>BF14         ITE        NE
-<span id="A341816CE">  0x341816CE:  </span>2310         MOVNE      R3, #16
-<span id="A341816D0">  0x341816D0:  </span>230B         MOVEQ      R3, #11
-<span id="A341816D2">  0x341816D2:  </span>B297         UXTH       R7, R2
-<span id="A341816D4">  0x341816D4:  </span>F24E 06FF    MOVW       R6, #0xE0FF
-<span id="A341816D8">  0x341816D8:  </span>9302         STR        R3, [SP, #8]
-<span id="A341816DA">  0x341816DA:  </span>2500         MOVS       R5, #0
-<span id="A341816DC">  0x341816DC:  </span>2A10         CMP        R2, #16
-<span id="A341816DE">  0x341816DE:  </span>EA5F 932F    CSET       R3, CC
-<span id="A341816E2">  0x341816E2:  </span>FA26 F707    LSR.W      R7, R6, R7
-<span id="A341816E6">  0x341816E6:  </span>9200         STR        R2, [SP, #0]
-<span id="A341816E8">  0x341816E8:  </span>EA03 0207    AND.W      R2, R3, R7
-<span id="A341816EC">  0x341816EC:  </span>9201         STR        R2, [SP, #4]
-<span id="A341816EE">  0x341816EE:  </span>E084         B          46L5                      ; 0x341817FA
-<br/>.L1:
-<span id="A341816F0">  0x341816F0:  </span>F1BB 0F03    CMP.W      R11, #3
-<span id="A341816F4">  0x341816F4:  </span>BF08         IT         EQ
-<span id="A341816F6">  0x341816F6:  </span>F1BC 0F01    CMPEQ.W    R12, #1
-<span id="A341816FA">  0x341816FA:  </span>D024         BEQ        46L3                      ; 0x34181746
-<span id="A341816FC">  0x341816FC:  </span>006B         LSLS       R3, R5, #1
-<span id="A341816FE">  0x341816FE:  </span>2203         MOVS       R2, #3
-<span id="A34181700">  0x34181700:  </span>FA02 F303    LSL.W      R3, R2, R3
-<span id="A34181704">  0x34181704:  </span>43DC         MVNS       R4, R3
-<br/>.L2:
-<span id="A34181706">  0x34181706:  </span>68C3         LDR        R3, [R0, #12]
-<span id="A34181708">  0x34181708:  </span>4023         ANDS       R3, R4
-<span id="A3418170A">  0x3418170A:  </span>006C         LSLS       R4, R5, #1
-<span id="A3418170C">  0x3418170C:  </span>FA0C F604    LSL.W      R6, R12, R4
-<span id="A34181710">  0x34181710:  </span>4333         ORRS       R3, R6
-<span id="A34181712">  0x34181712:  </span>F1BB 0F02    CMP.W      R11, #2
-<span id="A34181716">  0x34181716:  </span>60C3         STR        R3, [R0, #12]
-<span id="A34181718">  0x34181718:  </span>D115         BNE        46L3                      ; 0x34181746
-<span id="A3418171A">  0x3418171A:  </span>F06F 0203    MVN        R2, #3
-<span id="A3418171E">  0x3418171E:  </span>EA02 0655    AND.W      R6, R2, R5, LSR #1
-<span id="A34181722">  0x34181722:  </span>221C         MOVS       R2, #28
-<span id="A34181724">  0x34181724:  </span>690B         LDR        R3, [R1, #16]
-<span id="A34181726">  0x34181726:  </span>EA02 0485    AND.W      R4, R2, R5, LSL #2
-<span id="A3418172A">  0x3418172A:  </span>220F         MOVS       R2, #15
-<span id="A3418172C">  0x3418172C:  </span>40A3         LSLS       R3, R4
-<span id="A3418172E">  0x3418172E:  </span>FA02 F404    LSL.W      R4, R2, R4
-<span id="A34181732">  0x34181732:  </span>F100 0220    ADD.W      R2, R0, #32
-<span id="A34181736">  0x34181736:  </span>5997         LDR        R7, [R2, R6]
-<span id="A34181738">  0x34181738:  </span>43A7         BICS       R7, R4
-<span id="A3418173A">  0x3418173A:  </span>433B         ORRS       R3, R7
-<span id="A3418173C">  0x3418173C:  </span>5193         STR        R3, [R2, R6]
-<span id="A3418173E">  0x3418173E:  </span>F8D1 9004    LDR.W      R9, [R1, #4]
-<span id="A34181742">  0x34181742:  </span>F009 0B03    AND        R11, R9, #3
-<br/>.L3:
-<span id="A34181746">  0x34181746:  </span>006B         LSLS       R3, R5, #1
-<span id="A34181748">  0x34181748:  </span>2203         MOVS       R2, #3
-<span id="A3418174A">  0x3418174A:  </span>6806         LDR        R6, [R0]
-<span id="A3418174C">  0x3418174C:  </span>FA0B F703    LSL.W      R7, R11, R3
-<span id="A34181750">  0x34181750:  </span>FA02 F303    LSL.W      R3, R2, R3
-<span id="A34181754">  0x34181754:  </span>EA26 0303    BIC.W      R3, R6, R3
-<span id="A34181758">  0x34181758:  </span>433B         ORRS       R3, R7
-<span id="A3418175A">  0x3418175A:  </span>F419 3F40    TST        R9, #0x030000
-<span id="A3418175E">  0x3418175E:  </span>6003         STR        R3, [R0]
-<span id="A34181760">  0x34181760:  </span>D046         BEQ        46L4                      ; 0x341817F0
-<span id="A34181762">  0x34181762:  </span>F10E 0460    ADD.W      R4, LR, #96
-<span id="A34181766">  0x34181766:  </span>F025 0303    BIC        R3, R5, #3
-<span id="A3418176A">  0x3418176A:  </span>58E6         LDR        R6, [R4, R3]
-<span id="A3418176C">  0x3418176C:  </span>E9DD 2301    LDRD       R2, R3, [SP, #4]
-<span id="A34181770">  0x34181770:  </span>2A00         CMP        R2, #0
-<span id="A34181772">  0x34181772:  </span>BF1F         ITTTT      NE
-<span id="A34181774">  0x34181774:  </span>9A00         LDRNE      R2, [SP, #0]
-<span id="A34181776">  0x34181776:  </span>F241 4360    MOVWNE     R3, #0x1460              ; 0x34181460 = .rodata..Lswitch.table.HAL_GPIO_DeInit
-<span id="A3418177A">  0x3418177A:  </span>F2C3 4318    MOVTNE     R3, #0x3418              ; 0x34181460 = .rodata..Lswitch.table.HAL_GPIO_DeInit
-<span id="A3418177E">  0x3418177E:  </span>F853 3022    LDRNE.W    R3, [R3, R2, LSL #2]
-<span id="A34181782">  0x34181782:  </span>2218         MOVS       R2, #24
-<span id="A34181784">  0x34181784:  </span>EA02 07C5    AND.W      R7, R2, R5, LSL #3
-<span id="A34181788">  0x34181788:  </span>220F         MOVS       R2, #15
-<span id="A3418178A">  0x3418178A:  </span>40BB         LSLS       R3, R7
-<span id="A3418178C">  0x3418178C:  </span>FA02 F707    LSL.W      R7, R2, R7
-<span id="A34181790">  0x34181790:  </span>EA26 0707    BIC.W      R7, R6, R7
-<span id="A34181794">  0x34181794:  </span>433B         ORRS       R3, R7
-<span id="A34181796">  0x34181796:  </span>08AF         LSRS       R7, R5, #2
-<span id="A34181798">  0x34181798:  </span>F844 3027    STR.W      R3, [R4, R7, LSL #2]
-<span id="A3418179C">  0x3418179C:  </span>F8DE 3080    LDR.W      R3, [LR, #128]
-<span id="A341817A0">  0x341817A0:  </span>684F         LDR        R7, [R1, #4]
-<span id="A341817A2">  0x341817A2:  </span>03FE         LSLS       R6, R7, #15
-<span id="A341817A4">  0x341817A4:  </span>BF4C         ITE        MI
-<span id="A341817A6">  0x341817A6:  </span>EA43 0608    ORRMI.W    R6, R3, R8
-<span id="A341817AA">  0x341817AA:  </span>EA23 0608    BICPL.W    R6, R3, R8
-<span id="A341817AE">  0x341817AE:  </span>F8CE 6080    STR.W      R6, [LR, #128]
-<span id="A341817B2">  0x341817B2:  </span>F8DE 3084    LDR.W      R3, [LR, #132]
-<span id="A341817B6">  0x341817B6:  </span>03BE         LSLS       R6, R7, #14
-<span id="A341817B8">  0x341817B8:  </span>BF4C         ITE        MI
-<span id="A341817BA">  0x341817BA:  </span>EA43 0608    ORRMI.W    R6, R3, R8
-<span id="A341817BE">  0x341817BE:  </span>EA23 0608    BICPL.W    R6, R3, R8
-<span id="A341817C2">  0x341817C2:  </span>F8CE 6084    STR.W      R6, [LR, #132]
-<span id="A341817C6">  0x341817C6:  </span>F8DE 3000    LDR.W      R3, [LR]
-<span id="A341817CA">  0x341817CA:  </span>02FE         LSLS       R6, R7, #11
-<span id="A341817CC">  0x341817CC:  </span>BF4C         ITE        MI
-<span id="A341817CE">  0x341817CE:  </span>EA43 0608    ORRMI.W    R6, R3, R8
-<span id="A341817D2">  0x341817D2:  </span>EA23 0608    BICPL.W    R6, R3, R8
-<span id="A341817D6">  0x341817D6:  </span>F8CE 6000    STR.W      R6, [LR]
-<span id="A341817DA">  0x341817DA:  </span>02BB         LSLS       R3, R7, #10
-<span id="A341817DC">  0x341817DC:  </span>F8DE 3004    LDR.W      R3, [LR, #4]
-<span id="A341817E0">  0x341817E0:  </span>EA43 0708    ORR.W      R7, R3, R8
-<span id="A341817E4">  0x341817E4:  </span>BF58         IT         PL
-<span id="A341817E6">  0x341817E6:  </span>EA23 0708    BICPL.W    R7, R3, R8
-<span id="A341817EA">  0x341817EA:  </span>F8CE 7004    STR.W      R7, [LR, #4]
-<span id="A341817EE">  0x341817EE:  </span>BF00         NOP
-<br/>.L4:
-<span id="A341817F0">  0x341817F0:  </span>680C         LDR        R4, [R1]
-<span id="A341817F2">  0x341817F2:  </span>3501         ADDS       R5, #1
-<span id="A341817F4">  0x341817F4:  </span>FA34 F305    LSRS.W     R3, R4, R5
-<span id="A341817F8">  0x341817F8:  </span>D022         BEQ        46L6                      ; 0x34181840
-<br/>.L5:
-<span id="A341817FA">  0x341817FA:  </span>2201         MOVS       R2, #1
-<span id="A341817FC">  0x341817FC:  </span>FA02 FA05    LSL.W      R10, R2, R5
-<span id="A34181800">  0x34181800:  </span>EA1A 0804    ANDS.W     R8, R10, R4
-<span id="A34181804">  0x34181804:  </span>D0F4         BEQ        46L4                      ; 0x341817F0
-<span id="A34181806">  0x34181806:  </span>E9D1 9C01    LDRD       R9, R12, [R1, #4]
-<span id="A3418180A">  0x3418180A:  </span>F009 0B03    AND        R11, R9, #3
-<span id="A3418180E">  0x3418180E:  </span>F1AB 0301    SUB.W      R3, R11, #1
-<span id="A34181812">  0x34181812:  </span>2B01         CMP        R3, #1
-<span id="A34181814">  0x34181814:  </span>F63F AF6C    BHI.W      46L1                      ; 0x341816F0
-<span id="A34181818">  0x34181818:  </span>68CB         LDR        R3, [R1, #12]
-<span id="A3418181A">  0x3418181A:  </span>2203         MOVS       R2, #3
-<span id="A3418181C">  0x3418181C:  </span>006C         LSLS       R4, R5, #1
-<span id="A3418181E">  0x3418181E:  </span>6886         LDR        R6, [R0, #8]
-<span id="A34181820">  0x34181820:  </span>40A3         LSLS       R3, R4
-<span id="A34181822">  0x34181822:  </span>FA02 F404    LSL.W      R4, R2, R4
-<span id="A34181826">  0x34181826:  </span>43A6         BICS       R6, R4
-<span id="A34181828">  0x34181828:  </span>4333         ORRS       R3, R6
-<span id="A3418182A">  0x3418182A:  </span>6083         STR        R3, [R0, #8]
-<span id="A3418182C">  0x3418182C:  </span>6843         LDR        R3, [R0, #4]
-<span id="A3418182E">  0x3418182E:  </span>F3C9 1600    UBFX       R6, R9, #4, #1
-<span id="A34181832">  0x34181832:  </span>EA23 030A    BIC.W      R3, R3, R10
-<span id="A34181836">  0x34181836:  </span>40AE         LSLS       R6, R5
-<span id="A34181838">  0x34181838:  </span>4333         ORRS       R3, R6
-<span id="A3418183A">  0x3418183A:  </span>43E4         MVNS       R4, R4
-<span id="A3418183C">  0x3418183C:  </span>6043         STR        R3, [R0, #4]
-<span id="A3418183E">  0x3418183E:  </span>E762         B          46L2                      ; 0x34181706
-<br/>.L6:
-<span id="A34181840">  0x34181840:  </span>B003         ADD        SP, SP, #12
-<span id="A34181842">  0x34181842:  </span>E8BD 8FF0    POP.W      123R4-R11, PC}
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TAMP_IRQHandler">TAMP_IRQHandler:</span>
-<span id="A34181846">  0x34181846:  </span>E7FE         B          <a href="#TAMP_IRQHandler">TAMP_IRQHandler</a>          ; 0x34181846
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4">Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4</h2>
-
-<pre>
-<br/><span id="HAL_RCC_OscConfig">HAL_RCC_OscConfig:</span>
-<span id="A34181848">  0x34181848:  </span>E92D 4FF8    PUSH.W     123R3-R11, LR}
-<span id="A3418184C">  0x3418184C:  </span>6801         LDR        R1, [R0]
-<span id="A3418184E">  0x3418184E:  </span>F248 0604    MOVW       R6, #0x8004
-<span id="A34181852">  0x34181852:  </span>4604         MOV        R4, R0
-<span id="A34181854">  0x34181854:  </span>F2C5 6602    MOVT       R6, #0x5602
-<span id="A34181858">  0x34181858:  </span>07C8         LSLS       R0, R1, #31
-<span id="A3418185A">  0x3418185A:  </span>69F0         LDR        R0, [R6, #28]
-<span id="A3418185C">  0x3418185C:  </span>F400 1A40    AND        R10, R0, #0x300000
-<span id="A34181860">  0x34181860:  </span>69F0         LDR        R0, [R6, #28]
-<span id="A34181862">  0x34181862:  </span>F000 5840    AND        R8, R0, #0x30000000
-<span id="A34181866">  0x34181866:  </span>6FF0         LDR        R0, [R6, #124]
-<span id="A34181868">  0x34181868:  </span>F000 49E0    AND        R9, R0, #0x70000000
-<span id="A3418186C">  0x3418186C:  </span>F8D6 008C    LDR.W      R0, [R6, #140]
-<span id="A34181870">  0x34181870:  </span>F000 4BE0    AND        R11, R0, #0x70000000
-<span id="A34181874">  0x34181874:  </span>F8D6 009C    LDR.W      R0, [R6, #156]
-<span id="A34181878">  0x34181878:  </span>F000 4EE0    AND        LR, R0, #0x70000000
-<span id="A3418187C">  0x3418187C:  </span>F8D6 00AC    LDR.W      R0, [R6, #172]
-<span id="A34181880">  0x34181880:  </span>6832         LDR        R2, [R6]
-<span id="A34181882">  0x34181882:  </span>F000 4CE0    AND        R12, R0, #0x70000000
-<span id="A34181886">  0x34181886:  </span>D01D         BEQ        46L4                      ; 0x341818C4
-<span id="A34181888">  0x34181888:  </span>F5BA 1F00    CMP.W      R10, #0x200000
-<span id="A3418188C">  0x3418188C:  </span>BF18         IT         NE
-<span id="A3418188E">  0x3418188E:  </span>F1B8 5F00    CMPNE.W    R8, #0x20000000
-<span id="A34181892">  0x34181892:  </span>F040 82D1    BNE.W      46L65                     ; 0x34181E38
-<br/>.L1:
-<span id="A34181896">  0x34181896:  </span>6860         LDR        R0, [R4, #4]
-<span id="A34181898">  0x34181898:  </span>2800         CMP        R0, #0
-<span id="A3418189A">  0x3418189A:  </span>F000 8246    BEQ.W      46L49                     ; 0x34181D2A
-<span id="A3418189E">  0x3418189E:  </span>F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A341818A2">  0x341818A2:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
-<span id="A341818A6">  0x341818A6:  </span>6807         LDR        R7, [R0]
-<br/>.L2:
-<span id="A341818A8">  0x341818A8:  </span>6833         LDR        R3, [R6]
-<span id="A341818AA">  0x341818AA:  </span>06DB         LSLS       R3, R3, #27
-<span id="A341818AC">  0x341818AC:  </span>6803         LDR        R3, [R0]
-<span id="A341818AE">  0x341818AE:  </span>D405         BMI        46L3                      ; 0x341818BC
-<span id="A341818B0">  0x341818B0:  </span>1BDB         SUBS       R3, R3, R7
-<span id="A341818B2">  0x341818B2:  </span>2B64         CMP        R3, #100
-<span id="A341818B4">  0x341818B4:  </span>D9F8         BLS        46L2                      ; 0x341818A8
-<span id="A341818B6">  0x341818B6:  </span>2003         MOVS       R0, #3
-<span id="A341818B8">  0x341818B8:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L3:
-<span id="A341818BC">  0x341818BC:  </span>6807         LDR        R7, [R0]
-<span id="A341818BE">  0x341818BE:  </span>1AFF         SUBS       R7, R7, R3
-<span id="A341818C0">  0x341818C0:  </span>2F02         CMP        R7, #2
-<span id="A341818C2">  0x341818C2:  </span>D3FB         BCC        46L3                      ; 0x341818BC
-<br/>.L4:
-<span id="A341818C4">  0x341818C4:  </span>0788         LSLS       R0, R1, #30
-<span id="A341818C6">  0x341818C6:  </span>D516         BPL        46L7                      ; 0x341818F6
-<span id="A341818C8">  0x341818C8:  </span>F1BA 0F00    CMP.W      R10, #0
-<span id="A341818CC">  0x341818CC:  </span>BF18         IT         NE
-<span id="A341818CE">  0x341818CE:  </span>F1B8 0F00    CMPNE.W    R8, #0
-<span id="A341818D2">  0x341818D2:  </span>D177         BNE        46L16                     ; 0x341819C4
-<br/>.L5:
-<span id="A341818D4">  0x341818D4:  </span>68E0         LDR        R0, [R4, #12]
-<span id="A341818D6">  0x341818D6:  </span>2800         CMP        R0, #0
-<span id="A341818D8">  0x341818D8:  </span>F000 8227    BEQ.W      46L49                     ; 0x34181D2A
-<br/>.L6:
-<span id="A341818DC">  0x341818DC:  </span>6C70         LDR        R0, [R6, #68]
-<span id="A341818DE">  0x341818DE:  </span>E9D4 3704    LDRD       R3, R7, [R4, #16]
-<span id="A341818E2">  0x341818E2:  </span>F420 70C0    BIC        R0, R0, #0x0180
-<span id="A341818E6">  0x341818E6:  </span>4318         ORRS       R0, R3
-<span id="A341818E8">  0x341818E8:  </span>6470         STR        R0, [R6, #68]
-<span id="A341818EA">  0x341818EA:  </span>6C70         LDR        R0, [R6, #68]
-<span id="A341818EC">  0x341818EC:  </span>F420 00FE    BIC        R0, R0, #0x7F0000
-<span id="A341818F0">  0x341818F0:  </span>EA40 4007    ORR.W      R0, R0, R7, LSL #16
-<span id="A341818F4">  0x341818F4:  </span>6470         STR        R0, [R6, #68]
-<br/>.L7:
-<span id="A341818F6">  0x341818F6:  </span>06C8         LSLS       R0, R1, #27
-<span id="A341818F8">  0x341818F8:  </span>D511         BPL        46L10                     ; 0x3418191E
-<span id="A341818FA">  0x341818FA:  </span>F5BA 1F80    CMP.W      R10, #0x100000
-<span id="A341818FE">  0x341818FE:  </span>BF18         IT         NE
-<span id="A34181900">  0x34181900:  </span>F1B8 5F80    CMPNE.W    R8, #0x10000000
-<span id="A34181904">  0x34181904:  </span>F040 8096    BNE.W      46L22                     ; 0x34181A34
-<br/>.L8:
-<span id="A34181908">  0x34181908:  </span>69E0         LDR        R0, [R4, #28]
-<span id="A3418190A">  0x3418190A:  </span>2800         CMP        R0, #0
-<span id="A3418190C">  0x3418190C:  </span>F000 820D    BEQ.W      46L49                     ; 0x34181D2A
-<span id="A34181910">  0x34181910:  </span>6A63         LDR        R3, [R4, #36]
-<br/>.L9:
-<span id="A34181912">  0x34181912:  </span>6C30         LDR        R0, [R6, #64]
-<span id="A34181914">  0x34181914:  </span>F420 10F8    BIC        R0, R0, #0x1F0000
-<span id="A34181918">  0x34181918:  </span>EA40 4003    ORR.W      R0, R0, R3, LSL #16
-<span id="A3418191C">  0x3418191C:  </span>6430         STR        R0, [R6, #64]
-<br/>.L10:
-<span id="A3418191E">  0x3418191E:  </span>F648 0500    MOVW       R5, #0x8800
-<span id="A34181922">  0x34181922:  </span>0708         LSLS       R0, R1, #28
-<span id="A34181924">  0x34181924:  </span>F2C5 6502    MOVT       R5, #0x5602
-<span id="A34181928">  0x34181928:  </span>D437         BMI        46L14                     ; 0x3418199A
-<br/>.L11:
-<span id="A3418192A">  0x3418192A:  </span>0748         LSLS       R0, R1, #29
-<span id="A3418192C">  0x3418192C:  </span>F100 816F    BMI.W      46L37                     ; 0x34181C0E
-<br/>.L12:
-<span id="A34181930">  0x34181930:  </span>46A1         MOV        R9, R4
-<span id="A34181932">  0x34181932:  </span>F859 0F28    LDR        R0, [R9, #40]!
-<span id="A34181936">  0x34181936:  </span>2800         CMP        R0, #0
-<span id="A34181938">  0x34181938:  </span>F000 80E7    BEQ.W      46L32                     ; 0x34181B0A
-<span id="A3418193C">  0x3418193C:  </span>2000         MOVS       R0, #0
-<span id="A3418193E">  0x3418193E:  </span>4649         MOV        R1, R9
-<span id="A34181940">  0x34181940:  </span>F000 FADC    BL         <a href="#RCC_PLL_IsNewConfig">RCC_PLL_IsNewConfig</a>      ; 0x34181EFC
-<span id="A34181944">  0x34181944:  </span>2800         CMP        R0, #0
-<span id="A34181946">  0x34181946:  </span>6830         LDR        R0, [R6]
-<span id="A34181948">  0x34181948:  </span>F000 80D7    BEQ.W      46L31                     ; 0x34181AFA
-<span id="A3418194C">  0x3418194C:  </span>F8D6 30C0    LDR.W      R3, [R6, #192]
-<span id="A34181950">  0x34181950:  </span>F8D6 00C4    LDR.W      R0, [R6, #196]
-<span id="A34181954">  0x34181954:  </span>F8D6 20D4    LDR.W      R2, [R6, #212]
-<span id="A34181958">  0x34181958:  </span>F8D6 10E8    LDR.W      R1, [R6, #232]
-<span id="A3418195C">  0x3418195C:  </span>F5BA 1F40    CMP.W      R10, #0x300000
-<span id="A34181960">  0x34181960:  </span>BF08         IT         EQ
-<span id="A34181962">  0x34181962:  </span>F013 5340    ANDSEQ     R3, R3, #0x30000000
-<span id="A34181966">  0x34181966:  </span>F000 81E0    BEQ.W      46L49                     ; 0x34181D2A
-<span id="A3418196A">  0x3418196A:  </span>F1B8 5F40    CMP.W      R8, #0x30000000
-<span id="A3418196E">  0x3418196E:  </span>D10C         BNE        46L13                     ; 0x3418198A
-<span id="A34181970">  0x34181970:  </span>F010 5F40    TST        R0, #0x30000000
-<span id="A34181974">  0x34181974:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181978">  0x34181978:  </span>F000 82BD    BEQ.W      46L78                     ; 0x34181EF6
-<span id="A3418197C">  0x3418197C:  </span>F012 5240    ANDS       R2, R2, #0x30000000
-<span id="A34181980">  0x34181980:  </span>BF18         IT         NE
-<span id="A34181982">  0x34181982:  </span>F011 5140    ANDSNE     R1, R1, #0x30000000
-<span id="A34181986">  0x34181986:  </span>F000 82B6    BEQ.W      46L78                     ; 0x34181EF6
-<br/>.L13:
-<span id="A3418198A">  0x3418198A:  </span>2000         MOVS       R0, #0
-<span id="A3418198C">  0x3418198C:  </span>4649         MOV        R1, R9
-<span id="A3418198E">  0x3418198E:  </span>F000 FAF9    BL         <a href="#RCC_PLL_Config">RCC_PLL_Config</a>           ; 0x34181F84
-<span id="A34181992">  0x34181992:  </span>2800         CMP        R0, #0
-<span id="A34181994">  0x34181994:  </span>F040 81C9    BNE.W      46L49                     ; 0x34181D2A
-<span id="A34181998">  0x34181998:  </span>E0B7         B          46L32                     ; 0x34181B0A
-<br/>.L14:
-<span id="A3418199A">  0x3418199A:  </span>69A0         LDR        R0, [R4, #24]
-<span id="A3418199C">  0x3418199C:  </span>2201         MOVS       R2, #1
-<span id="A3418199E">  0x3418199E:  </span>2800         CMP        R0, #0
-<span id="A341819A0">  0x341819A0:  </span>F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A341819A4">  0x341819A4:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
-<span id="A341819A8">  0x341819A8:  </span>F000 8098    BEQ.W      46L29                     ; 0x34181ADC
-<span id="A341819AC">  0x341819AC:  </span>602A         STR        R2, [R5]
-<span id="A341819AE">  0x341819AE:  </span>6802         LDR        R2, [R0]
-<br/>.L15:
-<span id="A341819B0">  0x341819B0:  </span>6833         LDR        R3, [R6]
-<span id="A341819B2">  0x341819B2:  </span>07DB         LSLS       R3, R3, #31
-<span id="A341819B4">  0x341819B4:  </span>D1B9         BNE        46L11                     ; 0x3418192A
-<span id="A341819B6">  0x341819B6:  </span>6803         LDR        R3, [R0]
-<span id="A341819B8">  0x341819B8:  </span>1A9B         SUBS       R3, R3, R2
-<span id="A341819BA">  0x341819BA:  </span>2B01         CMP        R3, #1
-<span id="A341819BC">  0x341819BC:  </span>D9F8         BLS        46L15                     ; 0x341819B0
-<span id="A341819BE">  0x341819BE:  </span>2003         MOVS       R0, #3
-<span id="A341819C0">  0x341819C0:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L16:
-<span id="A341819C4">  0x341819C4:  </span>F1B9 0F00    CMP.W      R9, #0
-<span id="A341819C8">  0x341819C8:  </span>D103         BNE        46L17                     ; 0x341819D2
-<span id="A341819CA">  0x341819CA:  </span>F412 7080    ANDS       R0, R2, #0x0100
-<span id="A341819CE">  0x341819CE:  </span>F47F AF81    BNE.W      46L5                      ; 0x341818D4
-<br/>.L17:
-<span id="A341819D2">  0x341819D2:  </span>F1BB 0F00    CMP.W      R11, #0
-<span id="A341819D6">  0x341819D6:  </span>D103         BNE        46L18                     ; 0x341819E0
-<span id="A341819D8">  0x341819D8:  </span>F412 7000    ANDS       R0, R2, #0x0200
-<span id="A341819DC">  0x341819DC:  </span>F47F AF7A    BNE.W      46L5                      ; 0x341818D4
-<br/>.L18:
-<span id="A341819E0">  0x341819E0:  </span>F1BE 0F00    CMP.W      LR, #0
-<span id="A341819E4">  0x341819E4:  </span>D103         BNE        46L19                     ; 0x341819EE
-<span id="A341819E6">  0x341819E6:  </span>F412 6080    ANDS       R0, R2, #0x0400
-<span id="A341819EA">  0x341819EA:  </span>F47F AF73    BNE.W      46L5                      ; 0x341818D4
-<br/>.L19:
-<span id="A341819EE">  0x341819EE:  </span>F1BC 0F00    CMP.W      R12, #0
-<span id="A341819F2">  0x341819F2:  </span>D103         BNE        46L20                     ; 0x341819FC
-<span id="A341819F4">  0x341819F4:  </span>F412 6000    ANDS       R0, R2, #0x0800
-<span id="A341819F8">  0x341819F8:  </span>F47F AF6C    BNE.W      46L5                      ; 0x341818D4
-<br/>.L20:
-<span id="A341819FC">  0x341819FC:  </span>68E3         LDR        R3, [R4, #12]
-<span id="A341819FE">  0x341819FE:  </span>F648 0000    MOVW       R0, #0x8800
-<span id="A34181A02">  0x34181A02:  </span>F242 25A4    MOVW       R5, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181A06">  0x34181A06:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A34181A0A">  0x34181A0A:  </span>2B00         CMP        R3, #0
-<span id="A34181A0C">  0x34181A0C:  </span>F04F 0308    MOV.W      R3, #8
-<span id="A34181A10">  0x34181A10:  </span>F2C3 4518    MOVT       R5, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181A14">  0x34181A14:  </span>F000 81F1    BEQ.W      46L61                     ; 0x34181DFA
-<span id="A34181A18">  0x34181A18:  </span>6003         STR        R3, [R0]
-<span id="A34181A1A">  0x34181A1A:  </span>682B         LDR        R3, [R5]
-<br/>.L21:
-<span id="A34181A1C">  0x34181A1C:  </span>6830         LDR        R0, [R6]
-<span id="A34181A1E">  0x34181A1E:  </span>0700         LSLS       R0, R0, #28
-<span id="A34181A20">  0x34181A20:  </span>F53F AF5C    BMI.W      46L6                      ; 0x341818DC
-<span id="A34181A24">  0x34181A24:  </span>6828         LDR        R0, [R5]
-<span id="A34181A26">  0x34181A26:  </span>1AC0         SUBS       R0, R0, R3
-<span id="A34181A28">  0x34181A28:  </span>2801         CMP        R0, #1
-<span id="A34181A2A">  0x34181A2A:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181A2E">  0x34181A2E:  </span>D9F5         BLS        46L21                     ; 0x34181A1C
-<span id="A34181A30">  0x34181A30:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L22:
-<span id="A34181A34">  0x34181A34:  </span>F1B9 5F80    CMP.W      R9, #0x10000000
-<span id="A34181A38">  0x34181A38:  </span>D103         BNE        46L23                     ; 0x34181A42
-<span id="A34181A3A">  0x34181A3A:  </span>F412 7080    ANDS       R0, R2, #0x0100
-<span id="A34181A3E">  0x34181A3E:  </span>F47F AF63    BNE.W      46L8                      ; 0x34181908
-<br/>.L23:
-<span id="A34181A42">  0x34181A42:  </span>F1BB 5F80    CMP.W      R11, #0x10000000
-<span id="A34181A46">  0x34181A46:  </span>D103         BNE        46L24                     ; 0x34181A50
-<span id="A34181A48">  0x34181A48:  </span>F412 7000    ANDS       R0, R2, #0x0200
-<span id="A34181A4C">  0x34181A4C:  </span>F47F AF5C    BNE.W      46L8                      ; 0x34181908
-<br/>.L24:
-<span id="A34181A50">  0x34181A50:  </span>F1BE 5F80    CMP.W      LR, #0x10000000
-<span id="A34181A54">  0x34181A54:  </span>D103         BNE        46L25                     ; 0x34181A5E
-<span id="A34181A56">  0x34181A56:  </span>F412 6080    ANDS       R0, R2, #0x0400
-<span id="A34181A5A">  0x34181A5A:  </span>F47F AF55    BNE.W      46L8                      ; 0x34181908
-<br/>.L25:
-<span id="A34181A5E">  0x34181A5E:  </span>F1BC 5F80    CMP.W      R12, #0x10000000
-<span id="A34181A62">  0x34181A62:  </span>D103         BNE        46L26                     ; 0x34181A6C
-<span id="A34181A64">  0x34181A64:  </span>F412 6000    ANDS       R0, R2, #0x0800
-<span id="A34181A68">  0x34181A68:  </span>F47F AF4E    BNE.W      46L8                      ; 0x34181908
-<br/>.L26:
-<span id="A34181A6C">  0x34181A6C:  </span>69E2         LDR        R2, [R4, #28]
-<span id="A34181A6E">  0x34181A6E:  </span>F648 0000    MOVW       R0, #0x8800
-<span id="A34181A72">  0x34181A72:  </span>F2C5 6002    MOVT       R0, #0x5602
-<span id="A34181A76">  0x34181A76:  </span>2A00         CMP        R2, #0
-<span id="A34181A78">  0x34181A78:  </span>F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181A7C">  0x34181A7C:  </span>F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181A80">  0x34181A80:  </span>F000 81CA    BEQ.W      46L63                     ; 0x34181E18
-<span id="A34181A84">  0x34181A84:  </span>E9D4 7308    LDRD       R7, R3, [R4, #32]
-<span id="A34181A88">  0x34181A88:  </span>F8D6 9040    LDR.W      R9, [R6, #64]
-<span id="A34181A8C">  0x34181A8C:  </span>F429 7900    BIC        R9, R9, #0x0200
-<span id="A34181A90">  0x34181A90:  </span>EA47 0709    ORR.W      R7, R7, R9
-<span id="A34181A94">  0x34181A94:  </span>6437         STR        R7, [R6, #64]
-<span id="A34181A96">  0x34181A96:  </span>2704         MOVS       R7, #4
-<span id="A34181A98">  0x34181A98:  </span>6007         STR        R7, [R0]
-<span id="A34181A9A">  0x34181A9A:  </span>F8D2 9000    LDR.W      R9, [R2]
-<br/>.L27:
-<span id="A34181A9E">  0x34181A9E:  </span>6830         LDR        R0, [R6]
-<span id="A34181AA0">  0x34181AA0:  </span>0740         LSLS       R0, R0, #29
-<span id="A34181AA2">  0x34181AA2:  </span>F53F AF36    BMI.W      46L9                      ; 0x34181912
-<span id="A34181AA6">  0x34181AA6:  </span>6810         LDR        R0, [R2]
-<span id="A34181AA8">  0x34181AA8:  </span>EBA0 0009    SUB.W      R0, R0, R9
-<span id="A34181AAC">  0x34181AAC:  </span>2801         CMP        R0, #1
-<span id="A34181AAE">  0x34181AAE:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181AB2">  0x34181AB2:  </span>D9F4         BLS        46L27                     ; 0x34181A9E
-<span id="A34181AB4">  0x34181AB4:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L28:
-<span id="A34181AB8">  0x34181AB8:  </span>F248 0102    MOVW       R1, #0x8002
-<span id="A34181ABC">  0x34181ABC:  </span>4288         CMP        R0, R1
-<span id="A34181ABE">  0x34181ABE:  </span>F000 80D9    BEQ.W      46L41                     ; 0x34181C74
-<span id="A34181AC2">  0x34181AC2:  </span>F501 3180    ADD.W      R1, R1, #0x010000
-<span id="A34181AC6">  0x34181AC6:  </span>4288         CMP        R0, R1
-<span id="A34181AC8">  0x34181AC8:  </span>F040 80AA    BNE.W      46L38                     ; 0x34181C20
-<span id="A34181ACC">  0x34181ACC:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181ACE">  0x34181ACE:  </span>F440 4000    ORR        R0, R0, #0x8000
-<span id="A34181AD2">  0x34181AD2:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181AD4">  0x34181AD4:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181AD6">  0x34181AD6:  </span>F440 3080    ORR        R0, R0, #0x010000
-<span id="A34181ADA">  0x34181ADA:  </span>E0D2         B          46L42                     ; 0x34181C82
-<br/>.L29:
-<span id="A34181ADC">  0x34181ADC:  </span>F8C5 2800    STR.W      R2, [R5, #0x0800]
-<span id="A34181AE0">  0x34181AE0:  </span>6802         LDR        R2, [R0]
-<span id="A34181AE2">  0x34181AE2:  </span>BF00         NOP
-<br/>.L30:
-<span id="A34181AE4">  0x34181AE4:  </span>6833         LDR        R3, [R6]
-<span id="A34181AE6">  0x34181AE6:  </span>07DB         LSLS       R3, R3, #31
-<span id="A34181AE8">  0x34181AE8:  </span>F43F AF1F    BEQ.W      46L11                     ; 0x3418192A
-<span id="A34181AEC">  0x34181AEC:  </span>6803         LDR        R3, [R0]
-<span id="A34181AEE">  0x34181AEE:  </span>1A9B         SUBS       R3, R3, R2
-<span id="A34181AF0">  0x34181AF0:  </span>2B01         CMP        R3, #1
-<span id="A34181AF2">  0x34181AF2:  </span>D9F7         BLS        46L30                     ; 0x34181AE4
-<span id="A34181AF4">  0x34181AF4:  </span>2003         MOVS       R0, #3
-<span id="A34181AF6">  0x34181AF6:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L31:
-<span id="A34181AFA">  0x34181AFA:  </span>F8D9 1000    LDR.W      R1, [R9]
-<span id="A34181AFE">  0x34181AFE:  </span>2902         CMP        R1, #2
-<span id="A34181B00">  0x34181B00:  </span>BF08         IT         EQ
-<span id="A34181B02">  0x34181B02:  </span>F410 7080    ANDSEQ     R0, R0, #0x0100
-<span id="A34181B06">  0x34181B06:  </span>F000 8113    BEQ.W      46L50                     ; 0x34181D30
-<br/>.L32:
-<span id="A34181B0A">  0x34181B0A:  </span>46A1         MOV        R9, R4
-<span id="A34181B0C">  0x34181B0C:  </span>F859 0F44    LDR        R0, [R9, #68]!
-<span id="A34181B10">  0x34181B10:  </span>2800         CMP        R0, #0
-<span id="A34181B12">  0x34181B12:  </span>D03F         BEQ        46L35                     ; 0x34181B94
-<span id="A34181B14">  0x34181B14:  </span>2001         MOVS       R0, #1
-<span id="A34181B16">  0x34181B16:  </span>4649         MOV        R1, R9
-<span id="A34181B18">  0x34181B18:  </span>F000 F9F0    BL         <a href="#RCC_PLL_IsNewConfig">RCC_PLL_IsNewConfig</a>      ; 0x34181EFC
-<span id="A34181B1C">  0x34181B1C:  </span>2800         CMP        R0, #0
-<span id="A34181B1E">  0x34181B1E:  </span>6830         LDR        R0, [R6]
-<span id="A34181B20">  0x34181B20:  </span>D030         BEQ        46L34                     ; 0x34181B84
-<span id="A34181B22">  0x34181B22:  </span>F8D6 30C0    LDR.W      R3, [R6, #192]
-<span id="A34181B26">  0x34181B26:  </span>F8D6 00C4    LDR.W      R0, [R6, #196]
-<span id="A34181B2A">  0x34181B2A:  </span>F8D6 20D4    LDR.W      R2, [R6, #212]
-<span id="A34181B2E">  0x34181B2E:  </span>F8D6 10E8    LDR.W      R1, [R6, #232]
-<span id="A34181B32">  0x34181B32:  </span>F5BA 1F40    CMP.W      R10, #0x300000
-<span id="A34181B36">  0x34181B36:  </span>BF04         ITT        EQ
-<span id="A34181B38">  0x34181B38:  </span>F003 5340    ANDEQ      R3, R3, #0x30000000
-<span id="A34181B3C">  0x34181B3C:  </span>F1B3 5F80    CMPEQ.W    R3, #0x10000000
-<span id="A34181B40">  0x34181B40:  </span>F000 80F3    BEQ.W      46L49                     ; 0x34181D2A
-<span id="A34181B44">  0x34181B44:  </span>F1B8 5F40    CMP.W      R8, #0x30000000
-<span id="A34181B48">  0x34181B48:  </span>D112         BNE        46L33                     ; 0x34181B70
-<span id="A34181B4A">  0x34181B4A:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A34181B4E">  0x34181B4E:  </span>F1B0 5F80    CMP.W      R0, #0x10000000
-<span id="A34181B52">  0x34181B52:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181B56">  0x34181B56:  </span>BF1C         ITT        NE
-<span id="A34181B58">  0x34181B58:  </span>F002 5240    ANDNE      R2, R2, #0x30000000
-<span id="A34181B5C">  0x34181B5C:  </span>F1B2 5F80    CMPNE.W    R2, #0x10000000
-<span id="A34181B60">  0x34181B60:  </span>F000 81C9    BEQ.W      46L78                     ; 0x34181EF6
-<span id="A34181B64">  0x34181B64:  </span>F001 5140    AND        R1, R1, #0x30000000
-<span id="A34181B68">  0x34181B68:  </span>F1B1 5F80    CMP.W      R1, #0x10000000
-<span id="A34181B6C">  0x34181B6C:  </span>F000 81C3    BEQ.W      46L78                     ; 0x34181EF6
-<br/>.L33:
-<span id="A34181B70">  0x34181B70:  </span>2001         MOVS       R0, #1
-<span id="A34181B72">  0x34181B72:  </span>4649         MOV        R1, R9
-<span id="A34181B74">  0x34181B74:  </span>F000 FA06    BL         <a href="#RCC_PLL_Config">RCC_PLL_Config</a>           ; 0x34181F84
-<span id="A34181B78">  0x34181B78:  </span>0001         MOVS       R1, R0
-<span id="A34181B7A">  0x34181B7A:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181B7E">  0x34181B7E:  </span>F040 81BA    BNE.W      46L78                     ; 0x34181EF6
-<span id="A34181B82">  0x34181B82:  </span>E007         B          46L35                     ; 0x34181B94
-<br/>.L34:
-<span id="A34181B84">  0x34181B84:  </span>F8D9 1000    LDR.W      R1, [R9]
-<span id="A34181B88">  0x34181B88:  </span>2902         CMP        R1, #2
-<span id="A34181B8A">  0x34181B8A:  </span>BF08         IT         EQ
-<span id="A34181B8C">  0x34181B8C:  </span>F410 7000    ANDSEQ     R0, R0, #0x0200
-<span id="A34181B90">  0x34181B90:  </span>F000 80EB    BEQ.W      46L54                     ; 0x34181D6A
-<br/>.L35:
-<span id="A34181B94">  0x34181B94:  </span>46A1         MOV        R9, R4
-<span id="A34181B96">  0x34181B96:  </span>F859 0F60    LDR        R0, [R9, #96]!
-<span id="A34181B9A">  0x34181B9A:  </span>2800         CMP        R0, #0
-<span id="A34181B9C">  0x34181B9C:  </span>F000 808E    BEQ.W      46L47                     ; 0x34181CBC
-<span id="A34181BA0">  0x34181BA0:  </span>2002         MOVS       R0, #2
-<span id="A34181BA2">  0x34181BA2:  </span>4649         MOV        R1, R9
-<span id="A34181BA4">  0x34181BA4:  </span>F000 F9AA    BL         <a href="#RCC_PLL_IsNewConfig">RCC_PLL_IsNewConfig</a>      ; 0x34181EFC
-<span id="A34181BA8">  0x34181BA8:  </span>2800         CMP        R0, #0
-<span id="A34181BAA">  0x34181BAA:  </span>6830         LDR        R0, [R6]
-<span id="A34181BAC">  0x34181BAC:  </span>F000 807F    BEQ.W      46L46                     ; 0x34181CAE
-<span id="A34181BB0">  0x34181BB0:  </span>F8D6 30C0    LDR.W      R3, [R6, #192]
-<span id="A34181BB4">  0x34181BB4:  </span>F8D6 00C4    LDR.W      R0, [R6, #196]
-<span id="A34181BB8">  0x34181BB8:  </span>F8D6 20D4    LDR.W      R2, [R6, #212]
-<span id="A34181BBC">  0x34181BBC:  </span>F8D6 10E8    LDR.W      R1, [R6, #232]
-<span id="A34181BC0">  0x34181BC0:  </span>F5BA 1F40    CMP.W      R10, #0x300000
-<span id="A34181BC4">  0x34181BC4:  </span>BF04         ITT        EQ
-<span id="A34181BC6">  0x34181BC6:  </span>F003 5340    ANDEQ      R3, R3, #0x30000000
-<span id="A34181BCA">  0x34181BCA:  </span>F1B3 5F00    CMPEQ.W    R3, #0x20000000
-<span id="A34181BCE">  0x34181BCE:  </span>F000 80AC    BEQ.W      46L49                     ; 0x34181D2A
-<span id="A34181BD2">  0x34181BD2:  </span>F1B8 5F40    CMP.W      R8, #0x30000000
-<span id="A34181BD6">  0x34181BD6:  </span>D112         BNE        46L36                     ; 0x34181BFE
-<span id="A34181BD8">  0x34181BD8:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A34181BDC">  0x34181BDC:  </span>F1B0 5F00    CMP.W      R0, #0x20000000
-<span id="A34181BE0">  0x34181BE0:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181BE4">  0x34181BE4:  </span>BF1C         ITT        NE
-<span id="A34181BE6">  0x34181BE6:  </span>F002 5240    ANDNE      R2, R2, #0x30000000
-<span id="A34181BEA">  0x34181BEA:  </span>F1B2 5F00    CMPNE.W    R2, #0x20000000
-<span id="A34181BEE">  0x34181BEE:  </span>F000 8182    BEQ.W      46L78                     ; 0x34181EF6
-<span id="A34181BF2">  0x34181BF2:  </span>F001 5140    AND        R1, R1, #0x30000000
-<span id="A34181BF6">  0x34181BF6:  </span>F1B1 5F00    CMP.W      R1, #0x20000000
-<span id="A34181BFA">  0x34181BFA:  </span>F000 817C    BEQ.W      46L78                     ; 0x34181EF6
-<br/>.L36:
-<span id="A34181BFE">  0x34181BFE:  </span>2002         MOVS       R0, #2
-<span id="A34181C00">  0x34181C00:  </span>4649         MOV        R1, R9
-<span id="A34181C02">  0x34181C02:  </span>F000 F9BF    BL         <a href="#RCC_PLL_Config">RCC_PLL_Config</a>           ; 0x34181F84
-<span id="A34181C06">  0x34181C06:  </span>2800         CMP        R0, #0
-<span id="A34181C08">  0x34181C08:  </span>F040 808F    BNE.W      46L49                     ; 0x34181D2A
-<span id="A34181C0C">  0x34181C0C:  </span>E056         B          46L47                     ; 0x34181CBC
-<br/>.L37:
-<span id="A34181C0E">  0x34181C0E:  </span>68A0         LDR        R0, [R4, #8]
-<span id="A34181C10">  0x34181C10:  </span>F248 0101    MOVW       R1, #0x8001
-<span id="A34181C14">  0x34181C14:  </span>4288         CMP        R0, R1
-<span id="A34181C16">  0x34181C16:  </span>F73F AF4F    BGT.W      46L28                     ; 0x34181AB8
-<span id="A34181C1A">  0x34181C1A:  </span>B168         CBZ        R0, .L39                 ; 0x34181C38
-<span id="A34181C1C">  0x34181C1C:  </span>2802         CMP        R0, #2
-<span id="A34181C1E">  0x34181C1E:  </span>D032         BEQ        46L43                     ; 0x34181C86
-<br/>.L38:
-<span id="A34181C20">  0x34181C20:  </span>2002         MOVS       R0, #2
-<span id="A34181C22">  0x34181C22:  </span>F8C5 0800    STR.W      R0, [R5, #0x0800]
-<span id="A34181C26">  0x34181C26:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C28">  0x34181C28:  </span>F420 4000    BIC        R0, R0, #0x8000
-<span id="A34181C2C">  0x34181C2C:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C2E">  0x34181C2E:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C30">  0x34181C30:  </span>F420 3080    BIC        R0, R0, #0x010000
-<span id="A34181C34">  0x34181C34:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C36">  0x34181C36:  </span>E027         B          46L44                     ; 0x34181C88
-<br/>.L39:
-<span id="A34181C38">  0x34181C38:  </span>2002         MOVS       R0, #2
-<span id="A34181C3A">  0x34181C3A:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181C3E">  0x34181C3E:  </span>F8C5 0800    STR.W      R0, [R5, #0x0800]
-<span id="A34181C42">  0x34181C42:  </span>F241 3388    MOVW       R3, #0x1388
-<span id="A34181C46">  0x34181C46:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C48">  0x34181C48:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181C4C">  0x34181C4C:  </span>F420 3080    BIC        R0, R0, #0x010000
-<span id="A34181C50">  0x34181C50:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C52">  0x34181C52:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C54">  0x34181C54:  </span>F420 4000    BIC        R0, R0, #0x8000
-<span id="A34181C58">  0x34181C58:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C5A">  0x34181C5A:  </span>680A         LDR        R2, [R1]
-<br/>.L40:
-<span id="A34181C5C">  0x34181C5C:  </span>6830         LDR        R0, [R6]
-<span id="A34181C5E">  0x34181C5E:  </span>0780         LSLS       R0, R0, #30
-<span id="A34181C60">  0x34181C60:  </span>F57F AE66    BPL.W      46L12                     ; 0x34181930
-<span id="A34181C64">  0x34181C64:  </span>6808         LDR        R0, [R1]
-<span id="A34181C66">  0x34181C66:  </span>1A80         SUBS       R0, R0, R2
-<span id="A34181C68">  0x34181C68:  </span>4298         CMP        R0, R3
-<span id="A34181C6A">  0x34181C6A:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181C6E">  0x34181C6E:  </span>D9F5         BLS        46L40                     ; 0x34181C5C
-<span id="A34181C70">  0x34181C70:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L41:
-<span id="A34181C74">  0x34181C74:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C76">  0x34181C76:  </span>F440 4000    ORR        R0, R0, #0x8000
-<span id="A34181C7A">  0x34181C7A:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C7C">  0x34181C7C:  </span>6BF0         LDR        R0, [R6, #60]
-<span id="A34181C7E">  0x34181C7E:  </span>F420 3080    BIC        R0, R0, #0x010000
-<br/>.L42:
-<span id="A34181C82">  0x34181C82:  </span>63F0         STR        R0, [R6, #60]
-<span id="A34181C84">  0x34181C84:  </span>2002         MOVS       R0, #2
-<br/>.L43:
-<span id="A34181C86">  0x34181C86:  </span>6028         STR        R0, [R5]
-<br/>.L44:
-<span id="A34181C88">  0x34181C88:  </span>F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181C8C">  0x34181C8C:  </span>F241 3288    MOVW       R2, #0x1388
-<span id="A34181C90">  0x34181C90:  </span>F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181C94">  0x34181C94:  </span>6801         LDR        R1, [R0]
-<span id="A34181C96">  0x34181C96:  </span>BF00         NOP
-<br/>.L45:
-<span id="A34181C98">  0x34181C98:  </span>6833         LDR        R3, [R6]
-<span id="A34181C9A">  0x34181C9A:  </span>079B         LSLS       R3, R3, #30
-<span id="A34181C9C">  0x34181C9C:  </span>F53F AE48    BMI.W      46L12                     ; 0x34181930
-<span id="A34181CA0">  0x34181CA0:  </span>6803         LDR        R3, [R0]
-<span id="A34181CA2">  0x34181CA2:  </span>1A5B         SUBS       R3, R3, R1
-<span id="A34181CA4">  0x34181CA4:  </span>4293         CMP        R3, R2
-<span id="A34181CA6">  0x34181CA6:  </span>D9F7         BLS        46L45                     ; 0x34181C98
-<span id="A34181CA8">  0x34181CA8:  </span>2003         MOVS       R0, #3
-<span id="A34181CAA">  0x34181CAA:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L46:
-<span id="A34181CAE">  0x34181CAE:  </span>F8D9 1000    LDR.W      R1, [R9]
-<span id="A34181CB2">  0x34181CB2:  </span>2902         CMP        R1, #2
-<span id="A34181CB4">  0x34181CB4:  </span>BF08         IT         EQ
-<span id="A34181CB6">  0x34181CB6:  </span>F410 6080    ANDSEQ     R0, R0, #0x0400
-<span id="A34181CBA">  0x34181CBA:  </span>D06A         BEQ        46L56                     ; 0x34181D92
-<br/>.L47:
-<span id="A34181CBC">  0x34181CBC:  </span>F854 0F7C    LDR        R0, [R4, #124]!
-<span id="A34181CC0">  0x34181CC0:  </span>2800         CMP        R0, #0
-<span id="A34181CC2">  0x34181CC2:  </span>F000 8118    BEQ.W      46L78                     ; 0x34181EF6
-<span id="A34181CC6">  0x34181CC6:  </span>2003         MOVS       R0, #3
-<span id="A34181CC8">  0x34181CC8:  </span>4621         MOV        R1, R4
-<span id="A34181CCA">  0x34181CCA:  </span>F000 F917    BL         <a href="#RCC_PLL_IsNewConfig">RCC_PLL_IsNewConfig</a>      ; 0x34181EFC
-<span id="A34181CCE">  0x34181CCE:  </span>2800         CMP        R0, #0
-<span id="A34181CD0">  0x34181CD0:  </span>6830         LDR        R0, [R6]
-<span id="A34181CD2">  0x34181CD2:  </span>D041         BEQ        46L52                     ; 0x34181D58
-<span id="A34181CD4">  0x34181CD4:  </span>F8D6 30C0    LDR.W      R3, [R6, #192]
-<span id="A34181CD8">  0x34181CD8:  </span>F8D6 00C4    LDR.W      R0, [R6, #196]
-<span id="A34181CDC">  0x34181CDC:  </span>F8D6 20D4    LDR.W      R2, [R6, #212]
-<span id="A34181CE0">  0x34181CE0:  </span>F8D6 10E8    LDR.W      R1, [R6, #232]
-<span id="A34181CE4">  0x34181CE4:  </span>F5BA 1F40    CMP.W      R10, #0x300000
-<span id="A34181CE8">  0x34181CE8:  </span>BF04         ITT        EQ
-<span id="A34181CEA">  0x34181CEA:  </span>F003 5340    ANDEQ      R3, R3, #0x30000000
-<span id="A34181CEE">  0x34181CEE:  </span>F1B3 5F40    CMPEQ.W    R3, #0x30000000
-<span id="A34181CF2">  0x34181CF2:  </span>D01A         BEQ        46L49                     ; 0x34181D2A
-<span id="A34181CF4">  0x34181CF4:  </span>F1B8 5F40    CMP.W      R8, #0x30000000
-<span id="A34181CF8">  0x34181CF8:  </span>D112         BNE        46L48                     ; 0x34181D20
-<span id="A34181CFA">  0x34181CFA:  </span>F000 5040    AND        R0, R0, #0x30000000
-<span id="A34181CFE">  0x34181CFE:  </span>F1B0 5F40    CMP.W      R0, #0x30000000
-<span id="A34181D02">  0x34181D02:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181D06">  0x34181D06:  </span>BF1C         ITT        NE
-<span id="A34181D08">  0x34181D08:  </span>F002 5240    ANDNE      R2, R2, #0x30000000
-<span id="A34181D0C">  0x34181D0C:  </span>F1B2 5F40    CMPNE.W    R2, #0x30000000
-<span id="A34181D10">  0x34181D10:  </span>F000 80F1    BEQ.W      46L78                     ; 0x34181EF6
-<span id="A34181D14">  0x34181D14:  </span>F001 5140    AND        R1, R1, #0x30000000
-<span id="A34181D18">  0x34181D18:  </span>F1B1 5F40    CMP.W      R1, #0x30000000
-<span id="A34181D1C">  0x34181D1C:  </span>F000 80EB    BEQ.W      46L78                     ; 0x34181EF6
-<br/>.L48:
-<span id="A34181D20">  0x34181D20:  </span>2003         MOVS       R0, #3
-<span id="A34181D22">  0x34181D22:  </span>4621         MOV        R1, R4
-<span id="A34181D24">  0x34181D24:  </span>F000 F92E    BL         <a href="#RCC_PLL_Config">RCC_PLL_Config</a>           ; 0x34181F84
-<span id="A34181D28">  0x34181D28:  </span>B1E0         CBZ        R0, .L53                 ; 0x34181D64
-<br/>.L49:
-<span id="A34181D2A">  0x34181D2A:  </span>2001         MOVS       R0, #1
-<span id="A34181D2C">  0x34181D2C:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L50:
-<span id="A34181D30">  0x34181D30:  </span>F44F 7080    MOV.W      R0, #0x0100
-<span id="A34181D34">  0x34181D34:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181D38">  0x34181D38:  </span>6028         STR        R0, [R5]
-<span id="A34181D3A">  0x34181D3A:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181D3E">  0x34181D3E:  </span>680A         LDR        R2, [R1]
-<br/>.L51:
-<span id="A34181D40">  0x34181D40:  </span>6830         LDR        R0, [R6]
-<span id="A34181D42">  0x34181D42:  </span>05C0         LSLS       R0, R0, #23
-<span id="A34181D44">  0x34181D44:  </span>F53F AEE1    BMI.W      46L32                     ; 0x34181B0A
-<span id="A34181D48">  0x34181D48:  </span>6808         LDR        R0, [R1]
-<span id="A34181D4A">  0x34181D4A:  </span>1A80         SUBS       R0, R0, R2
-<span id="A34181D4C">  0x34181D4C:  </span>2801         CMP        R0, #1
-<span id="A34181D4E">  0x34181D4E:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181D52">  0x34181D52:  </span>D9F5         BLS        46L51                     ; 0x34181D40
-<span id="A34181D54">  0x34181D54:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L52:
-<span id="A34181D58">  0x34181D58:  </span>6821         LDR        R1, [R4]
-<span id="A34181D5A">  0x34181D5A:  </span>2902         CMP        R1, #2
-<span id="A34181D5C">  0x34181D5C:  </span>BF08         IT         EQ
-<span id="A34181D5E">  0x34181D5E:  </span>F410 6000    ANDSEQ     R0, R0, #0x0800
-<span id="A34181D62">  0x34181D62:  </span>D037         BEQ        46L59                     ; 0x34181DD4
-<br/>.L53:
-<span id="A34181D64">  0x34181D64:  </span>2000         MOVS       R0, #0
-<span id="A34181D66">  0x34181D66:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L54:
-<span id="A34181D6A">  0x34181D6A:  </span>F44F 7000    MOV.W      R0, #0x0200
-<span id="A34181D6E">  0x34181D6E:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181D72">  0x34181D72:  </span>6028         STR        R0, [R5]
-<span id="A34181D74">  0x34181D74:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181D78">  0x34181D78:  </span>680A         LDR        R2, [R1]
-<br/>.L55:
-<span id="A34181D7A">  0x34181D7A:  </span>6830         LDR        R0, [R6]
-<span id="A34181D7C">  0x34181D7C:  </span>0580         LSLS       R0, R0, #22
-<span id="A34181D7E">  0x34181D7E:  </span>F53F AF09    BMI.W      46L35                     ; 0x34181B94
-<span id="A34181D82">  0x34181D82:  </span>6808         LDR        R0, [R1]
-<span id="A34181D84">  0x34181D84:  </span>1A80         SUBS       R0, R0, R2
-<span id="A34181D86">  0x34181D86:  </span>2801         CMP        R0, #1
-<span id="A34181D88">  0x34181D88:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181D8C">  0x34181D8C:  </span>D9F5         BLS        46L55                     ; 0x34181D7A
-<span id="A34181D8E">  0x34181D8E:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L56:
-<span id="A34181D92">  0x34181D92:  </span>F44F 6080    MOV.W      R0, #0x0400
-<span id="A34181D96">  0x34181D96:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181D9A">  0x34181D9A:  </span>6028         STR        R0, [R5]
-<span id="A34181D9C">  0x34181D9C:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181DA0">  0x34181DA0:  </span>680A         LDR        R2, [R1]
-<br/>.L57:
-<span id="A34181DA2">  0x34181DA2:  </span>6830         LDR        R0, [R6]
-<span id="A34181DA4">  0x34181DA4:  </span>0540         LSLS       R0, R0, #21
-<span id="A34181DA6">  0x34181DA6:  </span>F53F AF89    BMI.W      46L47                     ; 0x34181CBC
-<span id="A34181DAA">  0x34181DAA:  </span>6808         LDR        R0, [R1]
-<span id="A34181DAC">  0x34181DAC:  </span>1A80         SUBS       R0, R0, R2
-<span id="A34181DAE">  0x34181DAE:  </span>2801         CMP        R0, #1
-<span id="A34181DB0">  0x34181DB0:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181DB4">  0x34181DB4:  </span>D9F5         BLS        46L57                     ; 0x34181DA2
-<span id="A34181DB6">  0x34181DB6:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L58:
-<span id="A34181DBA">  0x34181DBA:  </span>F248 0310    MOVW       R3, #0x8010
-<span id="A34181DBE">  0x34181DBE:  </span>4298         CMP        R0, R3
-<span id="A34181DC0">  0x34181DC0:  </span>F000 8082    BEQ.W      46L73                     ; 0x34181EC8
-<span id="A34181DC4">  0x34181DC4:  </span>F503 3380    ADD.W      R3, R3, #0x010000
-<span id="A34181DC8">  0x34181DC8:  </span>4298         CMP        R0, R3
-<span id="A34181DCA">  0x34181DCA:  </span>D15D         BNE        46L70                     ; 0x34181E88
-<span id="A34181DCC">  0x34181DCC:  </span>6D30         LDR        R0, [R6, #80]
-<span id="A34181DCE">  0x34181DCE:  </span>F440 30C0    ORR        R0, R0, #0x018000
-<span id="A34181DD2">  0x34181DD2:  </span>E080         B          46L74                     ; 0x34181ED6
-<br/>.L59:
-<span id="A34181DD4">  0x34181DD4:  </span>F44F 6000    MOV.W      R0, #0x0800
-<span id="A34181DD8">  0x34181DD8:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181DDC">  0x34181DDC:  </span>6028         STR        R0, [R5]
-<span id="A34181DDE">  0x34181DDE:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181DE2">  0x34181DE2:  </span>680A         LDR        R2, [R1]
-<br/>.L60:
-<span id="A34181DE4">  0x34181DE4:  </span>6830         LDR        R0, [R6]
-<span id="A34181DE6">  0x34181DE6:  </span>0500         LSLS       R0, R0, #20
-<span id="A34181DE8">  0x34181DE8:  </span>D4BC         BMI        46L53                     ; 0x34181D64
-<span id="A34181DEA">  0x34181DEA:  </span>6808         LDR        R0, [R1]
-<span id="A34181DEC">  0x34181DEC:  </span>1A80         SUBS       R0, R0, R2
-<span id="A34181DEE">  0x34181DEE:  </span>2801         CMP        R0, #1
-<span id="A34181DF0">  0x34181DF0:  </span>F04F 0001    MOV.W      R0, #1
-<span id="A34181DF4">  0x34181DF4:  </span>D9F6         BLS        46L60                     ; 0x34181DE4
-<span id="A34181DF6">  0x34181DF6:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L61:
-<span id="A34181DFA">  0x34181DFA:  </span>F8C0 3800    STR.W      R3, [R0, #0x0800]
-<span id="A34181DFE">  0x34181DFE:  </span>682B         LDR        R3, [R5]
-<br/>.L62:
-<span id="A34181E00">  0x34181E00:  </span>6830         LDR        R0, [R6]
-<span id="A34181E02">  0x34181E02:  </span>0700         LSLS       R0, R0, #28
-<span id="A34181E04">  0x34181E04:  </span>F57F AD77    BPL.W      46L7                      ; 0x341818F6
-<span id="A34181E08">  0x34181E08:  </span>6828         LDR        R0, [R5]
-<span id="A34181E0A">  0x34181E0A:  </span>1AC0         SUBS       R0, R0, R3
-<span id="A34181E0C">  0x34181E0C:  </span>2801         CMP        R0, #1
-<span id="A34181E0E">  0x34181E0E:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181E12">  0x34181E12:  </span>D9F5         BLS        46L62                     ; 0x34181E00
-<span id="A34181E14">  0x34181E14:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L63:
-<span id="A34181E18">  0x34181E18:  </span>2304         MOVS       R3, #4
-<span id="A34181E1A">  0x34181E1A:  </span>F8C0 3800    STR.W      R3, [R0, #0x0800]
-<span id="A34181E1E">  0x34181E1E:  </span>6813         LDR        R3, [R2]
-<br/>.L64:
-<span id="A34181E20">  0x34181E20:  </span>6830         LDR        R0, [R6]
-<span id="A34181E22">  0x34181E22:  </span>0740         LSLS       R0, R0, #29
-<span id="A34181E24">  0x34181E24:  </span>F57F AD7B    BPL.W      46L10                     ; 0x3418191E
-<span id="A34181E28">  0x34181E28:  </span>6810         LDR        R0, [R2]
-<span id="A34181E2A">  0x34181E2A:  </span>1AC0         SUBS       R0, R0, R3
-<span id="A34181E2C">  0x34181E2C:  </span>2801         CMP        R0, #1
-<span id="A34181E2E">  0x34181E2E:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181E32">  0x34181E32:  </span>D9F5         BLS        46L64                     ; 0x34181E20
-<span id="A34181E34">  0x34181E34:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L65:
-<span id="A34181E38">  0x34181E38:  </span>F1B9 5F00    CMP.W      R9, #0x20000000
-<span id="A34181E3C">  0x34181E3C:  </span>D103         BNE        46L66                     ; 0x34181E46
-<span id="A34181E3E">  0x34181E3E:  </span>F412 7080    ANDS       R0, R2, #0x0100
-<span id="A34181E42">  0x34181E42:  </span>F47F AD28    BNE.W      46L1                      ; 0x34181896
-<br/>.L66:
-<span id="A34181E46">  0x34181E46:  </span>F1BB 5F00    CMP.W      R11, #0x20000000
-<span id="A34181E4A">  0x34181E4A:  </span>D103         BNE        46L67                     ; 0x34181E54
-<span id="A34181E4C">  0x34181E4C:  </span>F412 7000    ANDS       R0, R2, #0x0200
-<span id="A34181E50">  0x34181E50:  </span>F47F AD21    BNE.W      46L1                      ; 0x34181896
-<br/>.L67:
-<span id="A34181E54">  0x34181E54:  </span>F1BE 5F00    CMP.W      LR, #0x20000000
-<span id="A34181E58">  0x34181E58:  </span>D103         BNE        46L68                     ; 0x34181E62
-<span id="A34181E5A">  0x34181E5A:  </span>F412 6080    ANDS       R0, R2, #0x0400
-<span id="A34181E5E">  0x34181E5E:  </span>F47F AD1A    BNE.W      46L1                      ; 0x34181896
-<br/>.L68:
-<span id="A34181E62">  0x34181E62:  </span>F1BC 5F00    CMP.W      R12, #0x20000000
-<span id="A34181E66">  0x34181E66:  </span>D103         BNE        46L69                     ; 0x34181E70
-<span id="A34181E68">  0x34181E68:  </span>F412 6000    ANDS       R0, R2, #0x0800
-<span id="A34181E6C">  0x34181E6C:  </span>F47F AD13    BNE.W      46L1                      ; 0x34181896
-<br/>.L69:
-<span id="A34181E70">  0x34181E70:  </span>6860         LDR        R0, [R4, #4]
-<span id="A34181E72">  0x34181E72:  </span>F248 030F    MOVW       R3, #0x800F
-<span id="A34181E76">  0x34181E76:  </span>F242 25A4    MOVW       R5, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181E7A">  0x34181E7A:  </span>4298         CMP        R0, R3
-<span id="A34181E7C">  0x34181E7C:  </span>F2C3 4518    MOVT       R5, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181E80">  0x34181E80:  </span>DC9B         BGT        46L58                     ; 0x34181DBA
-<span id="A34181E82">  0x34181E82:  </span>B158         CBZ        R0, .L71                 ; 0x34181E9C
-<span id="A34181E84">  0x34181E84:  </span>2810         CMP        R0, #16
-<span id="A34181E86">  0x34181E86:  </span>D027         BEQ        46L75                     ; 0x34181ED8
-<br/>.L70:
-<span id="A34181E88">  0x34181E88:  </span>F206 70FC    ADDW       R0, R6, #0x07FC
-<span id="A34181E8C">  0x34181E8C:  </span>2310         MOVS       R3, #16
-<span id="A34181E8E">  0x34181E8E:  </span>F8C0 3800    STR.W      R3, [R0, #0x0800]
-<span id="A34181E92">  0x34181E92:  </span>6D30         LDR        R0, [R6, #80]
-<span id="A34181E94">  0x34181E94:  </span>F420 30C0    BIC        R0, R0, #0x018000
-<span id="A34181E98">  0x34181E98:  </span>6530         STR        R0, [R6, #80]
-<span id="A34181E9A">  0x34181E9A:  </span>E021         B          46L76                     ; 0x34181EE0
-<br/>.L71:
-<span id="A34181E9C">  0x34181E9C:  </span>F206 70FC    ADDW       R0, R6, #0x07FC
-<span id="A34181EA0">  0x34181EA0:  </span>2310         MOVS       R3, #16
-<span id="A34181EA2">  0x34181EA2:  </span>F8C0 3800    STR.W      R3, [R0, #0x0800]
-<span id="A34181EA6">  0x34181EA6:  </span>6D30         LDR        R0, [R6, #80]
-<span id="A34181EA8">  0x34181EA8:  </span>F420 30C0    BIC        R0, R0, #0x018000
-<span id="A34181EAC">  0x34181EAC:  </span>6530         STR        R0, [R6, #80]
-<span id="A34181EAE">  0x34181EAE:  </span>682B         LDR        R3, [R5]
-<br/>.L72:
-<span id="A34181EB0">  0x34181EB0:  </span>6830         LDR        R0, [R6]
-<span id="A34181EB2">  0x34181EB2:  </span>06C0         LSLS       R0, R0, #27
-<span id="A34181EB4">  0x34181EB4:  </span>F57F AD06    BPL.W      46L4                      ; 0x341818C4
-<span id="A34181EB8">  0x34181EB8:  </span>6828         LDR        R0, [R5]
-<span id="A34181EBA">  0x34181EBA:  </span>1AC0         SUBS       R0, R0, R3
-<span id="A34181EBC">  0x34181EBC:  </span>2864         CMP        R0, #100
-<span id="A34181EBE">  0x34181EBE:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181EC2">  0x34181EC2:  </span>D9F5         BLS        46L72                     ; 0x34181EB0
-<span id="A34181EC4">  0x34181EC4:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-<br/>.L73:
-<span id="A34181EC8">  0x34181EC8:  </span>6D30         LDR        R0, [R6, #80]
-<span id="A34181ECA">  0x34181ECA:  </span>F440 4000    ORR        R0, R0, #0x8000
-<span id="A34181ECE">  0x34181ECE:  </span>6530         STR        R0, [R6, #80]
-<span id="A34181ED0">  0x34181ED0:  </span>6D30         LDR        R0, [R6, #80]
-<span id="A34181ED2">  0x34181ED2:  </span>F420 3080    BIC        R0, R0, #0x010000
-<br/>.L74:
-<span id="A34181ED6">  0x34181ED6:  </span>6530         STR        R0, [R6, #80]
-<br/>.L75:
-<span id="A34181ED8">  0x34181ED8:  </span>F206 70FC    ADDW       R0, R6, #0x07FC
-<span id="A34181EDC">  0x34181EDC:  </span>2310         MOVS       R3, #16
-<span id="A34181EDE">  0x34181EDE:  </span>6003         STR        R3, [R0]
-<br/>.L76:
-<span id="A34181EE0">  0x34181EE0:  </span>682B         LDR        R3, [R5]
-<br/>.L77:
-<span id="A34181EE2">  0x34181EE2:  </span>6830         LDR        R0, [R6]
-<span id="A34181EE4">  0x34181EE4:  </span>06C0         LSLS       R0, R0, #27
-<span id="A34181EE6">  0x34181EE6:  </span>F53F ACED    BMI.W      46L4                      ; 0x341818C4
-<span id="A34181EEA">  0x34181EEA:  </span>6828         LDR        R0, [R5]
-<span id="A34181EEC">  0x34181EEC:  </span>1AC0         SUBS       R0, R0, R3
-<span id="A34181EEE">  0x34181EEE:  </span>2864         CMP        R0, #100
-<span id="A34181EF0">  0x34181EF0:  </span>F04F 0003    MOV.W      R0, #3
-<span id="A34181EF4">  0x34181EF4:  </span>D9F5         BLS        46L77                     ; 0x34181EE2
-<br/>.L78:
-<span id="A34181EF6">  0x34181EF6:  </span>E8BD 8FF8    POP.W      123R3-R11, PC}
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler:</span>
-<span id="A34181EFA">  0x34181EFA:  </span>E7FE         B          <a href="#RIFSC_TAMPER_IRQHandler">RIFSC_TAMPER_IRQHandler</a>  ; 0x34181EFA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4">Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4</h2>
-
-<pre>
-<br/><span id="RCC_PLL_IsNewConfig">RCC_PLL_IsNewConfig:</span>
-<span id="A34181EFC">  0x34181EFC:  </span>B530         PUSH       123R4-R5, LR}
-<span id="A34181EFE">  0x34181EFE:  </span>F248 0E04    MOVW       LR, #0x8004
-<span id="A34181F02">  0x34181F02:  </span>0102         LSLS       R2, R0, #4
-<span id="A34181F04">  0x34181F04:  </span>F2C5 6E02    MOVT       LR, #0x5602
-<span id="A34181F08">  0x34181F08:  </span>F10E 0C7C    ADD.W      R12, LR, #124
-<span id="A34181F0C">  0x34181F0C:  </span>F85C 2002    LDR.W      R2, [R12, R2]
-<span id="A34181F10">  0x34181F10:  </span>E9D1 3401    LDRD       R3, R4, [R1, #4]
-<span id="A34181F14">  0x34181F14:  </span>F022 420C    BIC        R2, R2, #0x8C000000
-<span id="A34181F18">  0x34181F18:  </span>F022 02FF    BIC        R2, R2, #255
-<span id="A34181F1C">  0x34181F1C:  </span>EA43 5304    ORR.W      R3, R3, R4, LSL #20
-<span id="A34181F20">  0x34181F20:  </span>690C         LDR        R4, [R1, #16]
-<span id="A34181F22">  0x34181F22:  </span>EA43 2304    ORR.W      R3, R3, R4, LSL #8
-<span id="A34181F26">  0x34181F26:  </span>429A         CMP        R2, R3
-<span id="A34181F28">  0x34181F28:  </span>D11E         BNE        46L1                      ; 0x34181F68
-<span id="A34181F2A">  0x34181F2A:  </span>0082         LSLS       R2, R0, #2
-<span id="A34181F2C">  0x34181F2C:  </span>EB0E 0382    ADD.W      R3, LR, R2, LSL #2
-<span id="A34181F30">  0x34181F30:  </span>F8D3 3080    LDR.W      R3, [R3, #128]
-<span id="A34181F34">  0x34181F34:  </span>68CC         LDR        R4, [R1, #12]
-<span id="A34181F36">  0x34181F36:  </span>F023 437F    BIC        R3, R3, #0xFF000000
-<span id="A34181F3A">  0x34181F3A:  </span>42A3         CMP        R3, R4
-<span id="A34181F3C">  0x34181F3C:  </span>D114         BNE        46L1                      ; 0x34181F68
-<span id="A34181F3E">  0x34181F3E:  </span>F10E 0384    ADD.W      R3, LR, #132
-<span id="A34181F42">  0x34181F42:  </span>F853 3022    LDR.W      R3, [R3, R2, LSL #2]
-<span id="A34181F46">  0x34181F46:  </span>E9D1 4505    LDRD       R4, R5, [R1, #20]
-<span id="A34181F4A">  0x34181F4A:  </span>F003 537C    AND        R3, R3, #0x3F000000
-<span id="A34181F4E">  0x34181F4E:  </span>062D         LSLS       R5, R5, #24
-<span id="A34181F50">  0x34181F50:  </span>EA45 64C4    ORR.W      R4, R5, R4, LSL #27
-<span id="A34181F54">  0x34181F54:  </span>42A3         CMP        R3, R4
-<span id="A34181F56">  0x34181F56:  </span>D107         BNE        46L1                      ; 0x34181F68
-<span id="A34181F58">  0x34181F58:  </span>F8DE 3000    LDR.W      R3, [LR]
-<span id="A34181F5C">  0x34181F5C:  </span>FA23 F000    LSR.W      R0, R3, R0
-<span id="A34181F60">  0x34181F60:  </span>05C0         LSLS       R0, R0, #23
-<span id="A34181F62">  0x34181F62:  </span>D503         BPL        46L2                      ; 0x34181F6C
-<span id="A34181F64">  0x34181F64:  </span>2002         MOVS       R0, #2
-<span id="A34181F66">  0x34181F66:  </span>E007         B          46L3                      ; 0x34181F78
-<br/>.L1:
-<span id="A34181F68">  0x34181F68:  </span>2001         MOVS       R0, #1
-<span id="A34181F6A">  0x34181F6A:  </span>BD30         POP        123R4-R5, PC}
-<br/>.L2:
-<span id="A34181F6C">  0x34181F6C:  </span>F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
-<span id="A34181F70">  0x34181F70:  </span>0100         LSLS       R0, R0, #4
-<span id="A34181F72">  0x34181F72:  </span>BF4C         ITE        MI
-<span id="A34181F74">  0x34181F74:  </span>2003         MOVMI      R0, #3
-<span id="A34181F76">  0x34181F76:  </span>2001         MOVPL      R0, #1
-<br/>.L3:
-<span id="A34181F78">  0x34181F78:  </span>6809         LDR        R1, [R1]
-<span id="A34181F7A">  0x34181F7A:  </span>4288         CMP        R0, R1
-<span id="A34181F7C">  0x34181F7C:  </span>EA5F 900F    CSET       R0, NE
-<span id="A34181F80">  0x34181F80:  </span>BD30         POP        123R4-R5, PC}
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="IAC_IRQHandler">IAC_IRQHandler:</span>
-<span id="A34181F82">  0x34181F82:  </span>E7FE         B          <a href="#IAC_IRQHandler">IAC_IRQHandler</a>           ; 0x34181F82
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4">Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4</h2>
-
-<pre>
-<br/><span id="RCC_PLL_Config">RCC_PLL_Config:</span>
-<span id="A34181F84">  0x34181F84:  </span>E92D 41F0    PUSH.W     123R4-R8, LR}
-<span id="A34181F88">  0x34181F88:  </span>F248 0304    MOVW       R3, #0x8004
-<span id="A34181F8C">  0x34181F8C:  </span>680C         LDR        R4, [R1]
-<span id="A34181F8E">  0x34181F8E:  </span>F2C5 6302    MOVT       R3, #0x5602
-<span id="A34181F92">  0x34181F92:  </span>0082         LSLS       R2, R0, #2
-<span id="A34181F94">  0x34181F94:  </span>F103 0C7C    ADD.W      R12, R3, #124
-<span id="A34181F98">  0x34181F98:  </span>F103 0E84    ADD.W      LR, R3, #132
-<span id="A34181F9C">  0x34181F9C:  </span>2C01         CMP        R4, #1
-<span id="A34181F9E">  0x34181F9E:  </span>D046         BEQ        46L5                      ; 0x3418202E
-<span id="A34181FA0">  0x34181FA0:  </span>2C03         CMP        R4, #3
-<span id="A34181FA2">  0x34181FA2:  </span>D01B         BEQ        46L2                      ; 0x34181FDC
-<span id="A34181FA4">  0x34181FA4:  </span>2C02         CMP        R4, #2
-<span id="A34181FA6">  0x34181FA6:  </span>F040 80C6    BNE.W      46L12                     ; 0x34182136
-<span id="A34181FAA">  0x34181FAA:  </span>F44F 7480    MOV.W      R4, #0x0100
-<span id="A34181FAE">  0x34181FAE:  </span>F603 78FC    ADDW       R8, R3, #0x0FFC
-<span id="A34181FB2">  0x34181FB2:  </span>FA04 F000    LSL.W      R0, R4, R0
-<span id="A34181FB6">  0x34181FB6:  </span>F242 24A4    MOVW       R4, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34181FBA">  0x34181FBA:  </span>F8C8 0000    STR.W      R0, [R8]
-<span id="A34181FBE">  0x34181FBE:  </span>F103 0680    ADD.W      R6, R3, #128
-<span id="A34181FC2">  0x34181FC2:  </span>F2C3 4418    MOVT       R4, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34181FC6">  0x34181FC6:  </span>6827         LDR        R7, [R4]
-<br/>.L1:
-<span id="A34181FC8">  0x34181FC8:  </span>681D         LDR        R5, [R3]
-<span id="A34181FCA">  0x34181FCA:  </span>4205         TST        R5, R0
-<span id="A34181FCC">  0x34181FCC:  </span>D051         BEQ        46L8                      ; 0x34182072
-<span id="A34181FCE">  0x34181FCE:  </span>6825         LDR        R5, [R4]
-<span id="A34181FD0">  0x34181FD0:  </span>1BED         SUBS       R5, R5, R7
-<span id="A34181FD2">  0x34181FD2:  </span>2D01         CMP        R5, #1
-<span id="A34181FD4">  0x34181FD4:  </span>D9F8         BLS        46L1                      ; 0x34181FC8
-<span id="A34181FD6">  0x34181FD6:  </span>2003         MOVS       R0, #3
-<span id="A34181FD8">  0x34181FD8:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-<br/>.L2:
-<span id="A34181FDC">  0x34181FDC:  </span>6849         LDR        R1, [R1, #4]
-<span id="A34181FDE">  0x34181FDE:  </span>EA4F 7731    ROR        R7, R1, #28
-<span id="A34181FE2">  0x34181FE2:  </span>2F02         CMP        R7, #2
-<span id="A34181FE4">  0x34181FE4:  </span>D80B         BHI        46L3                      ; 0x34181FFE
-<span id="A34181FE6">  0x34181FE6:  </span>F241 46A0    MOVW       R6, #0x14A0              ; 0x341814A0 = .rodata..Lswitch.table.RCC_PLL_Config
-<span id="A34181FEA">  0x34181FEA:  </span>F2C3 4618    MOVT       R6, #0x3418              ; 0x341814A0 = .rodata..Lswitch.table.RCC_PLL_Config
-<span id="A34181FEE">  0x34181FEE:  </span>F856 7027    LDR.W      R7, [R6, R7, LSL #2]
-<span id="A34181FF2">  0x34181FF2:  </span>681E         LDR        R6, [R3]
-<span id="A34181FF4">  0x34181FF4:  </span>FA26 F707    LSR.W      R7, R6, R7
-<span id="A34181FF8">  0x34181FF8:  </span>07FF         LSLS       R7, R7, #31
-<span id="A34181FFA">  0x34181FFA:  </span>F000 809F    BEQ.W      46L13                     ; 0x3418213C
-<br/>.L3:
-<span id="A34181FFE">  0x34181FFE:  </span>F44F 7780    MOV.W      R7, #0x0100
-<span id="A34182002">  0x34182002:  </span>F242 26A4    MOVW       R6, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A34182006">  0x34182006:  </span>FA07 F000    LSL.W      R0, R7, R0
-<span id="A3418200A">  0x3418200A:  </span>F603 77FC    ADDW       R7, R3, #0x0FFC
-<span id="A3418200E">  0x3418200E:  </span>6038         STR        R0, [R7]
-<span id="A34182010">  0x34182010:  </span>F2C3 4618    MOVT       R6, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34182014">  0x34182014:  </span>6837         LDR        R7, [R6]
-<span id="A34182016">  0x34182016:  </span>BF00         NOP
-<br/>.L4:
-<span id="A34182018">  0x34182018:  </span>681D         LDR        R5, [R3]
-<span id="A3418201A">  0x3418201A:  </span>4205         TST        R5, R0
-<span id="A3418201C">  0x3418201C:  </span>F000 8082    BEQ.W      46L10                     ; 0x34182124
-<span id="A34182020">  0x34182020:  </span>6835         LDR        R5, [R6]
-<span id="A34182022">  0x34182022:  </span>1BED         SUBS       R5, R5, R7
-<span id="A34182024">  0x34182024:  </span>2D01         CMP        R5, #1
-<span id="A34182026">  0x34182026:  </span>D9F7         BLS        46L4                      ; 0x34182018
-<span id="A34182028">  0x34182028:  </span>2003         MOVS       R0, #3
-<span id="A3418202A">  0x3418202A:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-<br/>.L5:
-<span id="A3418202E">  0x3418202E:  </span>F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
-<span id="A34182032">  0x34182032:  </span>F021 4180    BIC        R1, R1, #0x40000000
-<span id="A34182036">  0x34182036:  </span>F84E 1022    STR.W      R1, [LR, R2, LSL #2]
-<span id="A3418203A">  0x3418203A:  </span>F44F 7180    MOV.W      R1, #0x0100
-<span id="A3418203E">  0x3418203E:  </span>FA01 F000    LSL.W      R0, R1, R0
-<span id="A34182042">  0x34182042:  </span>F603 71FC    ADDW       R1, R3, #0x0FFC
-<span id="A34182046">  0x34182046:  </span>6008         STR        R0, [R1]
-<span id="A34182048">  0x34182048:  </span>F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
-<span id="A3418204C">  0x3418204C:  </span>F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
-<span id="A34182050">  0x34182050:  </span>680F         LDR        R7, [R1]
-<span id="A34182052">  0x34182052:  </span>BF00         NOP
-<br/>.L6:
-<span id="A34182054">  0x34182054:  </span>681E         LDR        R6, [R3]
-<span id="A34182056">  0x34182056:  </span>4206         TST        R6, R0
-<span id="A34182058">  0x34182058:  </span>D006         BEQ        46L7                      ; 0x34182068
-<span id="A3418205A">  0x3418205A:  </span>680E         LDR        R6, [R1]
-<span id="A3418205C">  0x3418205C:  </span>1BF6         SUBS       R6, R6, R7
-<span id="A3418205E">  0x3418205E:  </span>2E01         CMP        R6, #1
-<span id="A34182060">  0x34182060:  </span>D9F8         BLS        46L6                      ; 0x34182054
-<span id="A34182062">  0x34182062:  </span>2003         MOVS       R0, #3
-<span id="A34182064">  0x34182064:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-<br/>.L7:
-<span id="A34182068">  0x34182068:  </span>F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
-<span id="A3418206C">  0x3418206C:  </span>F020 6000    BIC        R0, R0, #0x08000000
-<span id="A34182070">  0x34182070:  </span>E05F         B          46L11                     ; 0x34182132
-<br/>.L8:
-<span id="A34182072">  0x34182072:  </span>F85E 5022    LDR.W      R5, [LR, R2, LSL #2]
-<span id="A34182076">  0x34182076:  </span>27FF         MOVS       R7, #255
-<span id="A34182078">  0x34182078:  </span>F6C8 4700    MOVT       R7, #0x8C00
-<span id="A3418207C">  0x3418207C:  </span>F045 0504    ORR        R5, R5, #4
-<span id="A34182080">  0x34182080:  </span>F84E 5022    STR.W      R5, [LR, R2, LSL #2]
-<span id="A34182084">  0x34182084:  </span>F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
-<span id="A34182088">  0x34182088:  </span>F025 6500    BIC        R5, R5, #0x08000000
-<span id="A3418208C">  0x3418208C:  </span>F84C 5022    STR.W      R5, [R12, R2, LSL #2]
-<span id="A34182090">  0x34182090:  </span>F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
-<span id="A34182094">  0x34182094:  </span>403D         ANDS       R5, R7
-<span id="A34182096">  0x34182096:  </span>684F         LDR        R7, [R1, #4]
-<span id="A34182098">  0x34182098:  </span>433D         ORRS       R5, R7
-<span id="A3418209A">  0x3418209A:  </span>688F         LDR        R7, [R1, #8]
-<span id="A3418209C">  0x3418209C:  </span>EA45 5507    ORR.W      R5, R5, R7, LSL #20
-<span id="A341820A0">  0x341820A0:  </span>690F         LDR        R7, [R1, #16]
-<span id="A341820A2">  0x341820A2:  </span>EA45 2507    ORR.W      R5, R5, R7, LSL #8
-<span id="A341820A6">  0x341820A6:  </span>F84C 5022    STR.W      R5, [R12, R2, LSL #2]
-<span id="A341820AA">  0x341820AA:  </span>F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
-<span id="A341820AE">  0x341820AE:  </span>694D         LDR        R5, [R1, #20]
-<span id="A341820B0">  0x341820B0:  </span>F027 577C    BIC        R7, R7, #0x3F000000
-<span id="A341820B4">  0x341820B4:  </span>EA47 67C5    ORR.W      R7, R7, R5, LSL #27
-<span id="A341820B8">  0x341820B8:  </span>698D         LDR        R5, [R1, #24]
-<span id="A341820BA">  0x341820BA:  </span>EA47 6705    ORR.W      R7, R7, R5, LSL #24
-<span id="A341820BE">  0x341820BE:  </span>F84E 7022    STR.W      R7, [LR, R2, LSL #2]
-<span id="A341820C2">  0x341820C2:  </span>F856 7022    LDR.W      R7, [R6, R2, LSL #2]
-<span id="A341820C6">  0x341820C6:  </span>68CD         LDR        R5, [R1, #12]
-<span id="A341820C8">  0x341820C8:  </span>F007 477F    AND        R7, R7, #0xFF000000
-<span id="A341820CC">  0x341820CC:  </span>432F         ORRS       R7, R5
-<span id="A341820CE">  0x341820CE:  </span>F846 7022    STR.W      R7, [R6, R2, LSL #2]
-<span id="A341820D2">  0x341820D2:  </span>F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
-<span id="A341820D6">  0x341820D6:  </span>F027 0708    BIC        R7, R7, #8
-<span id="A341820DA">  0x341820DA:  </span>F84E 7022    STR.W      R7, [LR, R2, LSL #2]
-<span id="A341820DE">  0x341820DE:  </span>68C9         LDR        R1, [R1, #12]
-<span id="A341820E0">  0x341820E0:  </span>2900         CMP        R1, #0
-<span id="A341820E2">  0x341820E2:  </span>BF1E         ITTT       NE
-<span id="A341820E4">  0x341820E4:  </span>F85E 1022    LDRNE.W    R1, [LR, R2, LSL #2]
-<span id="A341820E8">  0x341820E8:  </span>F041 010A    ORRNE      R1, R1, #10
-<span id="A341820EC">  0x341820EC:  </span>F84E 1022    STRNE.W    R1, [LR, R2, LSL #2]
-<span id="A341820F0">  0x341820F0:  </span>F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
-<span id="A341820F4">  0x341820F4:  </span>F041 4180    ORR        R1, R1, #0x40000000
-<span id="A341820F8">  0x341820F8:  </span>F041 0101    ORR        R1, R1, #1
-<span id="A341820FC">  0x341820FC:  </span>F84E 1022    STR.W      R1, [LR, R2, LSL #2]
-<span id="A34182100">  0x34182100:  </span>F64F 0100    MOVW       R1, #0xF800
-<span id="A34182104">  0x34182104:  </span>F6CF 71FF    MOVT       R1, #0xFFFF
-<span id="A34182108">  0x34182108:  </span>F848 0001    STR.W      R0, [R8, R1]
-<span id="A3418210C">  0x3418210C:  </span>6821         LDR        R1, [R4]
-<span id="A3418210E">  0x3418210E:  </span>BF00         NOP
-<br/>.L9:
-<span id="A34182110">  0x34182110:  </span>681A         LDR        R2, [R3]
-<span id="A34182112">  0x34182112:  </span>4202         TST        R2, R0
-<span id="A34182114">  0x34182114:  </span>D10F         BNE        46L12                     ; 0x34182136
-<span id="A34182116">  0x34182116:  </span>6822         LDR        R2, [R4]
-<span id="A34182118">  0x34182118:  </span>1A52         SUBS       R2, R2, R1
-<span id="A3418211A">  0x3418211A:  </span>2A01         CMP        R2, #1
-<span id="A3418211C">  0x3418211C:  </span>D9F8         BLS        46L9                      ; 0x34182110
-<span id="A3418211E">  0x3418211E:  </span>2003         MOVS       R0, #3
-<span id="A34182120">  0x34182120:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-<br/>.L10:
-<span id="A34182124">  0x34182124:  </span>F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
-<span id="A34182128">  0x34182128:  </span>F020 40F0    BIC        R0, R0, #0x78000000
-<span id="A3418212C">  0x3418212C:  </span>4308         ORRS       R0, R1
-<span id="A3418212E">  0x3418212E:  </span>F040 6000    ORR        R0, R0, #0x08000000
-<br/>.L11:
-<span id="A34182132">  0x34182132:  </span>F84C 0022    STR.W      R0, [R12, R2, LSL #2]
-<br/>.L12:
-<span id="A34182136">  0x34182136:  </span>2000         MOVS       R0, #0
-<span id="A34182138">  0x34182138:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-<br/>.L13:
-<span id="A3418213C">  0x3418213C:  </span>2001         MOVS       R0, #1
-<span id="A3418213E">  0x3418213E:  </span>E8BD 81F0    POP.W      123R4-R8, PC}
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RCC_S_IRQHandler">RCC_S_IRQHandler:</span>
-<span id="A34182142">  0x34182142:  </span>E7FE         B          <a href="#RCC_S_IRQHandler">RCC_S_IRQHandler</a>         ; 0x34182142
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RTC_IRQHandler">RTC_IRQHandler:</span>
-<span id="A34182144">  0x34182144:  </span>E7FE         B          <a href="#RTC_IRQHandler">RTC_IRQHandler</a>           ; 0x34182144
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="IWDG_IRQHandler">IWDG_IRQHandler:</span>
-<span id="A34182146">  0x34182146:  </span>E7FE         B          <a href="#IWDG_IRQHandler">IWDG_IRQHandler</a>          ; 0x34182146
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="WWDG_IRQHandler">WWDG_IRQHandler:</span>
-<span id="A34182148">  0x34182148:  </span>E7FE         B          <a href="#WWDG_IRQHandler">WWDG_IRQHandler</a>          ; 0x34182148
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI0_IRQHandler">EXTI0_IRQHandler:</span>
-<span id="A3418214A">  0x3418214A:  </span>E7FE         B          <a href="#EXTI0_IRQHandler">EXTI0_IRQHandler</a>         ; 0x3418214A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI1_IRQHandler">EXTI1_IRQHandler:</span>
-<span id="A3418214C">  0x3418214C:  </span>E7FE         B          <a href="#EXTI1_IRQHandler">EXTI1_IRQHandler</a>         ; 0x3418214C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI2_IRQHandler">EXTI2_IRQHandler:</span>
-<span id="A3418214E">  0x3418214E:  </span>E7FE         B          <a href="#EXTI2_IRQHandler">EXTI2_IRQHandler</a>         ; 0x3418214E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI3_IRQHandler">EXTI3_IRQHandler:</span>
-<span id="A34182150">  0x34182150:  </span>E7FE         B          <a href="#EXTI3_IRQHandler">EXTI3_IRQHandler</a>         ; 0x34182150
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI4_IRQHandler">EXTI4_IRQHandler:</span>
-<span id="A34182152">  0x34182152:  </span>E7FE         B          <a href="#EXTI4_IRQHandler">EXTI4_IRQHandler</a>         ; 0x34182152
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI5_IRQHandler">EXTI5_IRQHandler:</span>
-<span id="A34182154">  0x34182154:  </span>E7FE         B          <a href="#EXTI5_IRQHandler">EXTI5_IRQHandler</a>         ; 0x34182154
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI6_IRQHandler">EXTI6_IRQHandler:</span>
-<span id="A34182156">  0x34182156:  </span>E7FE         B          <a href="#EXTI6_IRQHandler">EXTI6_IRQHandler</a>         ; 0x34182156
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI7_IRQHandler">EXTI7_IRQHandler:</span>
-<span id="A34182158">  0x34182158:  </span>E7FE         B          <a href="#EXTI7_IRQHandler">EXTI7_IRQHandler</a>         ; 0x34182158
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI8_IRQHandler">EXTI8_IRQHandler:</span>
-<span id="A3418215A">  0x3418215A:  </span>E7FE         B          <a href="#EXTI8_IRQHandler">EXTI8_IRQHandler</a>         ; 0x3418215A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI9_IRQHandler">EXTI9_IRQHandler:</span>
-<span id="A3418215C">  0x3418215C:  </span>E7FE         B          <a href="#EXTI9_IRQHandler">EXTI9_IRQHandler</a>         ; 0x3418215C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI10_IRQHandler">EXTI10_IRQHandler:</span>
-<span id="A3418215E">  0x3418215E:  </span>E7FE         B          <a href="#EXTI10_IRQHandler">EXTI10_IRQHandler</a>        ; 0x3418215E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI11_IRQHandler">EXTI11_IRQHandler:</span>
-<span id="A34182160">  0x34182160:  </span>E7FE         B          <a href="#EXTI11_IRQHandler">EXTI11_IRQHandler</a>        ; 0x34182160
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI12_IRQHandler">EXTI12_IRQHandler:</span>
-<span id="A34182162">  0x34182162:  </span>E7FE         B          <a href="#EXTI12_IRQHandler">EXTI12_IRQHandler</a>        ; 0x34182162
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI13_IRQHandler">EXTI13_IRQHandler:</span>
-<span id="A34182164">  0x34182164:  </span>E7FE         B          <a href="#EXTI13_IRQHandler">EXTI13_IRQHandler</a>        ; 0x34182164
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI14_IRQHandler">EXTI14_IRQHandler:</span>
-<span id="A34182166">  0x34182166:  </span>E7FE         B          <a href="#EXTI14_IRQHandler">EXTI14_IRQHandler</a>        ; 0x34182166
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="EXTI15_IRQHandler">EXTI15_IRQHandler:</span>
-<span id="A34182168">  0x34182168:  </span>E7FE         B          <a href="#EXTI15_IRQHandler">EXTI15_IRQHandler</a>        ; 0x34182168
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SAES_IRQHandler">SAES_IRQHandler:</span>
-<span id="A3418216A">  0x3418216A:  </span>E7FE         B          <a href="#SAES_IRQHandler">SAES_IRQHandler</a>          ; 0x3418216A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CRYP_IRQHandler">CRYP_IRQHandler:</span>
-<span id="A3418216C">  0x3418216C:  </span>E7FE         B          <a href="#CRYP_IRQHandler">CRYP_IRQHandler</a>          ; 0x3418216C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="PKA_IRQHandler">PKA_IRQHandler:</span>
-<span id="A3418216E">  0x3418216E:  </span>E7FE         B          <a href="#PKA_IRQHandler">PKA_IRQHandler</a>           ; 0x3418216E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HASH_IRQHandler">HASH_IRQHandler:</span>
-<span id="A34182170">  0x34182170:  </span>E7FE         B          <a href="#HASH_IRQHandler">HASH_IRQHandler</a>          ; 0x34182170
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="RNG_IRQHandler">RNG_IRQHandler:</span>
-<span id="A34182172">  0x34182172:  </span>E7FE         B          <a href="#RNG_IRQHandler">RNG_IRQHandler</a>           ; 0x34182172
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MCE1_IRQHandler">MCE1_IRQHandler:</span>
-<span id="A34182174">  0x34182174:  </span>E7FE         B          <a href="#MCE1_IRQHandler">MCE1_IRQHandler</a>          ; 0x34182174
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MCE2_IRQHandler">MCE2_IRQHandler:</span>
-<span id="A34182176">  0x34182176:  </span>E7FE         B          <a href="#MCE2_IRQHandler">MCE2_IRQHandler</a>          ; 0x34182176
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MCE3_IRQHandler">MCE3_IRQHandler:</span>
-<span id="A34182178">  0x34182178:  </span>E7FE         B          <a href="#MCE3_IRQHandler">MCE3_IRQHandler</a>          ; 0x34182178
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MCE4_IRQHandler">MCE4_IRQHandler:</span>
-<span id="A3418217A">  0x3418217A:  </span>E7FE         B          <a href="#MCE4_IRQHandler">MCE4_IRQHandler</a>          ; 0x3418217A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="ADC1_2_IRQHandler">ADC1_2_IRQHandler:</span>
-<span id="A3418217C">  0x3418217C:  </span>E7FE         B          <a href="#ADC1_2_IRQHandler">ADC1_2_IRQHandler</a>        ; 0x3418217C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CSI_IRQHandler">CSI_IRQHandler:</span>
-<span id="A3418217E">  0x3418217E:  </span>E7FE         B          <a href="#CSI_IRQHandler">CSI_IRQHandler</a>           ; 0x3418217E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="DCMIPP_IRQHandler">DCMIPP_IRQHandler:</span>
-<span id="A34182180">  0x34182180:  </span>E7FE         B          <a href="#DCMIPP_IRQHandler">DCMIPP_IRQHandler</a>        ; 0x34182180
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler:</span>
-<span id="A34182182">  0x34182182:  </span>E7FE         B          <a href="#PAHB_ERR_IRQHandler">PAHB_ERR_IRQHandler</a>      ; 0x34182182
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="NPU0_IRQHandler">NPU0_IRQHandler:</span>
-<span id="A34182184">  0x34182184:  </span>E7FE         B          <a href="#NPU0_IRQHandler">NPU0_IRQHandler</a>          ; 0x34182184
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="NPU1_IRQHandler">NPU1_IRQHandler:</span>
-<span id="A34182186">  0x34182186:  </span>E7FE         B          <a href="#NPU1_IRQHandler">NPU1_IRQHandler</a>          ; 0x34182186
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="NPU2_IRQHandler">NPU2_IRQHandler:</span>
-<span id="A34182188">  0x34182188:  </span>E7FE         B          <a href="#NPU2_IRQHandler">NPU2_IRQHandler</a>          ; 0x34182188
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="NPU3_IRQHandler">NPU3_IRQHandler:</span>
-<span id="A3418218A">  0x3418218A:  </span>E7FE         B          <a href="#NPU3_IRQHandler">NPU3_IRQHandler</a>          ; 0x3418218A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CACHEAXI_IRQHandler">CACHEAXI_IRQHandler:</span>
-<span id="A3418218C">  0x3418218C:  </span>E7FE         B          <a href="#CACHEAXI_IRQHandler">CACHEAXI_IRQHandler</a>      ; 0x3418218C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LTDC_LO_IRQHandler">LTDC_LO_IRQHandler:</span>
-<span id="A3418218E">  0x3418218E:  </span>E7FE         B          <a href="#LTDC_LO_IRQHandler">LTDC_LO_IRQHandler</a>       ; 0x3418218E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler:</span>
-<span id="A34182190">  0x34182190:  </span>E7FE         B          <a href="#LTDC_LO_ERR_IRQHandler">LTDC_LO_ERR_IRQHandler</a>   ; 0x34182190
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="DMA2D_IRQHandler">DMA2D_IRQHandler:</span>
-<span id="A34182192">  0x34182192:  </span>E7FE         B          <a href="#DMA2D_IRQHandler">DMA2D_IRQHandler</a>         ; 0x34182192
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="JPEG_IRQHandler">JPEG_IRQHandler:</span>
-<span id="A34182194">  0x34182194:  </span>E7FE         B          <a href="#JPEG_IRQHandler">JPEG_IRQHandler</a>          ; 0x34182194
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="VENC_IRQHandler">VENC_IRQHandler:</span>
-<span id="A34182196">  0x34182196:  </span>E7FE         B          <a href="#VENC_IRQHandler">VENC_IRQHandler</a>          ; 0x34182196
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GFXMMU_IRQHandler">GFXMMU_IRQHandler:</span>
-<span id="A34182198">  0x34182198:  </span>E7FE         B          <a href="#GFXMMU_IRQHandler">GFXMMU_IRQHandler</a>        ; 0x34182198
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GFXTIM_IRQHandler">GFXTIM_IRQHandler:</span>
-<span id="A3418219A">  0x3418219A:  </span>E7FE         B          <a href="#GFXTIM_IRQHandler">GFXTIM_IRQHandler</a>        ; 0x3418219A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPU2D_IRQHandler">GPU2D_IRQHandler:</span>
-<span id="A3418219C">  0x3418219C:  </span>E7FE         B          <a href="#GPU2D_IRQHandler">GPU2D_IRQHandler</a>         ; 0x3418219C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler:</span>
-<span id="A3418219E">  0x3418219E:  </span>E7FE         B          <a href="#GPU2D_ER_IRQHandler">GPU2D_ER_IRQHandler</a>      ; 0x3418219E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="ICACHE_IRQHandler">ICACHE_IRQHandler:</span>
-<span id="A341821A0">  0x341821A0:  </span>E7FE         B          <a href="#ICACHE_IRQHandler">ICACHE_IRQHandler</a>        ; 0x341821A0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler:</span>
-<span id="A341821A2">  0x341821A2:  </span>E7FE         B          <a href="#HPDMA1_Channel0_IRQHandler">HPDMA1_Channel0_IRQHandler</a> ; 0x341821A2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler:</span>
-<span id="A341821A4">  0x341821A4:  </span>E7FE         B          <a href="#HPDMA1_Channel1_IRQHandler">HPDMA1_Channel1_IRQHandler</a> ; 0x341821A4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler:</span>
-<span id="A341821A6">  0x341821A6:  </span>E7FE         B          <a href="#HPDMA1_Channel2_IRQHandler">HPDMA1_Channel2_IRQHandler</a> ; 0x341821A6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler:</span>
-<span id="A341821A8">  0x341821A8:  </span>E7FE         B          <a href="#HPDMA1_Channel3_IRQHandler">HPDMA1_Channel3_IRQHandler</a> ; 0x341821A8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler:</span>
-<span id="A341821AA">  0x341821AA:  </span>E7FE         B          <a href="#HPDMA1_Channel4_IRQHandler">HPDMA1_Channel4_IRQHandler</a> ; 0x341821AA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler:</span>
-<span id="A341821AC">  0x341821AC:  </span>E7FE         B          <a href="#HPDMA1_Channel5_IRQHandler">HPDMA1_Channel5_IRQHandler</a> ; 0x341821AC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler:</span>
-<span id="A341821AE">  0x341821AE:  </span>E7FE         B          <a href="#HPDMA1_Channel6_IRQHandler">HPDMA1_Channel6_IRQHandler</a> ; 0x341821AE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler:</span>
-<span id="A341821B0">  0x341821B0:  </span>E7FE         B          <a href="#HPDMA1_Channel7_IRQHandler">HPDMA1_Channel7_IRQHandler</a> ; 0x341821B0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler:</span>
-<span id="A341821B2">  0x341821B2:  </span>E7FE         B          <a href="#HPDMA1_Channel8_IRQHandler">HPDMA1_Channel8_IRQHandler</a> ; 0x341821B2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler:</span>
-<span id="A341821B4">  0x341821B4:  </span>E7FE         B          <a href="#HPDMA1_Channel9_IRQHandler">HPDMA1_Channel9_IRQHandler</a> ; 0x341821B4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler:</span>
-<span id="A341821B6">  0x341821B6:  </span>E7FE         B          <a href="#HPDMA1_Channel10_IRQHandler">HPDMA1_Channel10_IRQHandler</a> ; 0x341821B6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler:</span>
-<span id="A341821B8">  0x341821B8:  </span>E7FE         B          <a href="#HPDMA1_Channel11_IRQHandler">HPDMA1_Channel11_IRQHandler</a> ; 0x341821B8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler:</span>
-<span id="A341821BA">  0x341821BA:  </span>E7FE         B          <a href="#HPDMA1_Channel12_IRQHandler">HPDMA1_Channel12_IRQHandler</a> ; 0x341821BA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler:</span>
-<span id="A341821BC">  0x341821BC:  </span>E7FE         B          <a href="#HPDMA1_Channel13_IRQHandler">HPDMA1_Channel13_IRQHandler</a> ; 0x341821BC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler:</span>
-<span id="A341821BE">  0x341821BE:  </span>E7FE         B          <a href="#HPDMA1_Channel14_IRQHandler">HPDMA1_Channel14_IRQHandler</a> ; 0x341821BE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler:</span>
-<span id="A341821C0">  0x341821C0:  </span>E7FE         B          <a href="#HPDMA1_Channel15_IRQHandler">HPDMA1_Channel15_IRQHandler</a> ; 0x341821C0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler:</span>
-<span id="A341821C2">  0x341821C2:  </span>E7FE         B          <a href="#GPDMA1_Channel0_IRQHandler">GPDMA1_Channel0_IRQHandler</a> ; 0x341821C2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler:</span>
-<span id="A341821C4">  0x341821C4:  </span>E7FE         B          <a href="#GPDMA1_Channel1_IRQHandler">GPDMA1_Channel1_IRQHandler</a> ; 0x341821C4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler:</span>
-<span id="A341821C6">  0x341821C6:  </span>E7FE         B          <a href="#GPDMA1_Channel2_IRQHandler">GPDMA1_Channel2_IRQHandler</a> ; 0x341821C6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler:</span>
-<span id="A341821C8">  0x341821C8:  </span>E7FE         B          <a href="#GPDMA1_Channel3_IRQHandler">GPDMA1_Channel3_IRQHandler</a> ; 0x341821C8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler:</span>
-<span id="A341821CA">  0x341821CA:  </span>E7FE         B          <a href="#GPDMA1_Channel4_IRQHandler">GPDMA1_Channel4_IRQHandler</a> ; 0x341821CA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler:</span>
-<span id="A341821CC">  0x341821CC:  </span>E7FE         B          <a href="#GPDMA1_Channel5_IRQHandler">GPDMA1_Channel5_IRQHandler</a> ; 0x341821CC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler:</span>
-<span id="A341821CE">  0x341821CE:  </span>E7FE         B          <a href="#GPDMA1_Channel6_IRQHandler">GPDMA1_Channel6_IRQHandler</a> ; 0x341821CE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler:</span>
-<span id="A341821D0">  0x341821D0:  </span>E7FE         B          <a href="#GPDMA1_Channel7_IRQHandler">GPDMA1_Channel7_IRQHandler</a> ; 0x341821D0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler:</span>
-<span id="A341821D2">  0x341821D2:  </span>E7FE         B          <a href="#GPDMA1_Channel8_IRQHandler">GPDMA1_Channel8_IRQHandler</a> ; 0x341821D2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler:</span>
-<span id="A341821D4">  0x341821D4:  </span>E7FE         B          <a href="#GPDMA1_Channel9_IRQHandler">GPDMA1_Channel9_IRQHandler</a> ; 0x341821D4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler:</span>
-<span id="A341821D6">  0x341821D6:  </span>E7FE         B          <a href="#GPDMA1_Channel10_IRQHandler">GPDMA1_Channel10_IRQHandler</a> ; 0x341821D6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler:</span>
-<span id="A341821D8">  0x341821D8:  </span>E7FE         B          <a href="#GPDMA1_Channel11_IRQHandler">GPDMA1_Channel11_IRQHandler</a> ; 0x341821D8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler:</span>
-<span id="A341821DA">  0x341821DA:  </span>E7FE         B          <a href="#GPDMA1_Channel12_IRQHandler">GPDMA1_Channel12_IRQHandler</a> ; 0x341821DA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler:</span>
-<span id="A341821DC">  0x341821DC:  </span>E7FE         B          <a href="#GPDMA1_Channel13_IRQHandler">GPDMA1_Channel13_IRQHandler</a> ; 0x341821DC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler:</span>
-<span id="A341821DE">  0x341821DE:  </span>E7FE         B          <a href="#GPDMA1_Channel14_IRQHandler">GPDMA1_Channel14_IRQHandler</a> ; 0x341821DE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler:</span>
-<span id="A341821E0">  0x341821E0:  </span>E7FE         B          <a href="#GPDMA1_Channel15_IRQHandler">GPDMA1_Channel15_IRQHandler</a> ; 0x341821E0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C1_EV_IRQHandler">I2C1_EV_IRQHandler:</span>
-<span id="A341821E2">  0x341821E2:  </span>E7FE         B          <a href="#I2C1_EV_IRQHandler">I2C1_EV_IRQHandler</a>       ; 0x341821E2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C1_ER_IRQHandler">I2C1_ER_IRQHandler:</span>
-<span id="A341821E4">  0x341821E4:  </span>E7FE         B          <a href="#I2C1_ER_IRQHandler">I2C1_ER_IRQHandler</a>       ; 0x341821E4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C2_EV_IRQHandler">I2C2_EV_IRQHandler:</span>
-<span id="A341821E6">  0x341821E6:  </span>E7FE         B          <a href="#I2C2_EV_IRQHandler">I2C2_EV_IRQHandler</a>       ; 0x341821E6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C2_ER_IRQHandler">I2C2_ER_IRQHandler:</span>
-<span id="A341821E8">  0x341821E8:  </span>E7FE         B          <a href="#I2C2_ER_IRQHandler">I2C2_ER_IRQHandler</a>       ; 0x341821E8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C3_EV_IRQHandler">I2C3_EV_IRQHandler:</span>
-<span id="A341821EA">  0x341821EA:  </span>E7FE         B          <a href="#I2C3_EV_IRQHandler">I2C3_EV_IRQHandler</a>       ; 0x341821EA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C3_ER_IRQHandler">I2C3_ER_IRQHandler:</span>
-<span id="A341821EC">  0x341821EC:  </span>E7FE         B          <a href="#I2C3_ER_IRQHandler">I2C3_ER_IRQHandler</a>       ; 0x341821EC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C4_EV_IRQHandler">I2C4_EV_IRQHandler:</span>
-<span id="A341821EE">  0x341821EE:  </span>E7FE         B          <a href="#I2C4_EV_IRQHandler">I2C4_EV_IRQHandler</a>       ; 0x341821EE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I2C4_ER_IRQHandler">I2C4_ER_IRQHandler:</span>
-<span id="A341821F0">  0x341821F0:  </span>E7FE         B          <a href="#I2C4_ER_IRQHandler">I2C4_ER_IRQHandler</a>       ; 0x341821F0
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I3C1_EV_IRQHandler">I3C1_EV_IRQHandler:</span>
-<span id="A341821F2">  0x341821F2:  </span>E7FE         B          <a href="#I3C1_EV_IRQHandler">I3C1_EV_IRQHandler</a>       ; 0x341821F2
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I3C1_ER_IRQHandler">I3C1_ER_IRQHandler:</span>
-<span id="A341821F4">  0x341821F4:  </span>E7FE         B          <a href="#I3C1_ER_IRQHandler">I3C1_ER_IRQHandler</a>       ; 0x341821F4
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I3C2_EV_IRQHandler">I3C2_EV_IRQHandler:</span>
-<span id="A341821F6">  0x341821F6:  </span>E7FE         B          <a href="#I3C2_EV_IRQHandler">I3C2_EV_IRQHandler</a>       ; 0x341821F6
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="I3C2_ER_IRQHandler">I3C2_ER_IRQHandler:</span>
-<span id="A341821F8">  0x341821F8:  </span>E7FE         B          <a href="#I3C2_ER_IRQHandler">I3C2_ER_IRQHandler</a>       ; 0x341821F8
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler:</span>
-<span id="A341821FA">  0x341821FA:  </span>E7FE         B          <a href="#TIM1_BRK_IRQHandler">TIM1_BRK_IRQHandler</a>      ; 0x341821FA
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM1_UP_IRQHandler">TIM1_UP_IRQHandler:</span>
-<span id="A341821FC">  0x341821FC:  </span>E7FE         B          <a href="#TIM1_UP_IRQHandler">TIM1_UP_IRQHandler</a>       ; 0x341821FC
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler:</span>
-<span id="A341821FE">  0x341821FE:  </span>E7FE         B          <a href="#TIM1_TRG_CCU_IRQHandler">TIM1_TRG_CCU_IRQHandler</a>  ; 0x341821FE
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM1_CC_IRQHandler">TIM1_CC_IRQHandler:</span>
-<span id="A34182200">  0x34182200:  </span>E7FE         B          <a href="#TIM1_CC_IRQHandler">TIM1_CC_IRQHandler</a>       ; 0x34182200
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM2_IRQHandler">TIM2_IRQHandler:</span>
-<span id="A34182202">  0x34182202:  </span>E7FE         B          <a href="#TIM2_IRQHandler">TIM2_IRQHandler</a>          ; 0x34182202
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM3_IRQHandler">TIM3_IRQHandler:</span>
-<span id="A34182204">  0x34182204:  </span>E7FE         B          <a href="#TIM3_IRQHandler">TIM3_IRQHandler</a>          ; 0x34182204
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM4_IRQHandler">TIM4_IRQHandler:</span>
-<span id="A34182206">  0x34182206:  </span>E7FE         B          <a href="#TIM4_IRQHandler">TIM4_IRQHandler</a>          ; 0x34182206
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM5_IRQHandler">TIM5_IRQHandler:</span>
-<span id="A34182208">  0x34182208:  </span>E7FE         B          <a href="#TIM5_IRQHandler">TIM5_IRQHandler</a>          ; 0x34182208
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM6_IRQHandler">TIM6_IRQHandler:</span>
-<span id="A3418220A">  0x3418220A:  </span>E7FE         B          <a href="#TIM6_IRQHandler">TIM6_IRQHandler</a>          ; 0x3418220A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM7_IRQHandler">TIM7_IRQHandler:</span>
-<span id="A3418220C">  0x3418220C:  </span>E7FE         B          <a href="#TIM7_IRQHandler">TIM7_IRQHandler</a>          ; 0x3418220C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler:</span>
-<span id="A3418220E">  0x3418220E:  </span>E7FE         B          <a href="#TIM8_BRK_IRQHandler">TIM8_BRK_IRQHandler</a>      ; 0x3418220E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM8_UP_IRQHandler">TIM8_UP_IRQHandler:</span>
-<span id="A34182210">  0x34182210:  </span>E7FE         B          <a href="#TIM8_UP_IRQHandler">TIM8_UP_IRQHandler</a>       ; 0x34182210
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler:</span>
-<span id="A34182212">  0x34182212:  </span>E7FE         B          <a href="#TIM8_TRG_CCU_IRQHandler">TIM8_TRG_CCU_IRQHandler</a>  ; 0x34182212
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM8_CC_IRQHandler">TIM8_CC_IRQHandler:</span>
-<span id="A34182214">  0x34182214:  </span>E7FE         B          <a href="#TIM8_CC_IRQHandler">TIM8_CC_IRQHandler</a>       ; 0x34182214
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM9_IRQHandler">TIM9_IRQHandler:</span>
-<span id="A34182216">  0x34182216:  </span>E7FE         B          <a href="#TIM9_IRQHandler">TIM9_IRQHandler</a>          ; 0x34182216
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM10_IRQHandler">TIM10_IRQHandler:</span>
-<span id="A34182218">  0x34182218:  </span>E7FE         B          <a href="#TIM10_IRQHandler">TIM10_IRQHandler</a>         ; 0x34182218
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM11_IRQHandler">TIM11_IRQHandler:</span>
-<span id="A3418221A">  0x3418221A:  </span>E7FE         B          <a href="#TIM11_IRQHandler">TIM11_IRQHandler</a>         ; 0x3418221A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM12_IRQHandler">TIM12_IRQHandler:</span>
-<span id="A3418221C">  0x3418221C:  </span>E7FE         B          <a href="#TIM12_IRQHandler">TIM12_IRQHandler</a>         ; 0x3418221C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM13_IRQHandler">TIM13_IRQHandler:</span>
-<span id="A3418221E">  0x3418221E:  </span>E7FE         B          <a href="#TIM13_IRQHandler">TIM13_IRQHandler</a>         ; 0x3418221E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM14_IRQHandler">TIM14_IRQHandler:</span>
-<span id="A34182220">  0x34182220:  </span>E7FE         B          <a href="#TIM14_IRQHandler">TIM14_IRQHandler</a>         ; 0x34182220
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM15_IRQHandler">TIM15_IRQHandler:</span>
-<span id="A34182222">  0x34182222:  </span>E7FE         B          <a href="#TIM15_IRQHandler">TIM15_IRQHandler</a>         ; 0x34182222
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM16_IRQHandler">TIM16_IRQHandler:</span>
-<span id="A34182224">  0x34182224:  </span>E7FE         B          <a href="#TIM16_IRQHandler">TIM16_IRQHandler</a>         ; 0x34182224
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM17_IRQHandler">TIM17_IRQHandler:</span>
-<span id="A34182226">  0x34182226:  </span>E7FE         B          <a href="#TIM17_IRQHandler">TIM17_IRQHandler</a>         ; 0x34182226
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="TIM18_IRQHandler">TIM18_IRQHandler:</span>
-<span id="A34182228">  0x34182228:  </span>E7FE         B          <a href="#TIM18_IRQHandler">TIM18_IRQHandler</a>         ; 0x34182228
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPTIM1_IRQHandler">LPTIM1_IRQHandler:</span>
-<span id="A3418222A">  0x3418222A:  </span>E7FE         B          <a href="#LPTIM1_IRQHandler">LPTIM1_IRQHandler</a>        ; 0x3418222A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPTIM2_IRQHandler">LPTIM2_IRQHandler:</span>
-<span id="A3418222C">  0x3418222C:  </span>E7FE         B          <a href="#LPTIM2_IRQHandler">LPTIM2_IRQHandler</a>        ; 0x3418222C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPTIM3_IRQHandler">LPTIM3_IRQHandler:</span>
-<span id="A3418222E">  0x3418222E:  </span>E7FE         B          <a href="#LPTIM3_IRQHandler">LPTIM3_IRQHandler</a>        ; 0x3418222E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPTIM4_IRQHandler">LPTIM4_IRQHandler:</span>
-<span id="A34182230">  0x34182230:  </span>E7FE         B          <a href="#LPTIM4_IRQHandler">LPTIM4_IRQHandler</a>        ; 0x34182230
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPTIM5_IRQHandler">LPTIM5_IRQHandler:</span>
-<span id="A34182232">  0x34182232:  </span>E7FE         B          <a href="#LPTIM5_IRQHandler">LPTIM5_IRQHandler</a>        ; 0x34182232
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler:</span>
-<span id="A34182234">  0x34182234:  </span>E7FE         B          <a href="#ADF1_FLT0_IRQHandler">ADF1_FLT0_IRQHandler</a>     ; 0x34182234
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler:</span>
-<span id="A34182236">  0x34182236:  </span>E7FE         B          <a href="#MDF1_FLT0_IRQHandler">MDF1_FLT0_IRQHandler</a>     ; 0x34182236
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler:</span>
-<span id="A34182238">  0x34182238:  </span>E7FE         B          <a href="#MDF1_FLT1_IRQHandler">MDF1_FLT1_IRQHandler</a>     ; 0x34182238
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler:</span>
-<span id="A3418223A">  0x3418223A:  </span>E7FE         B          <a href="#MDF1_FLT2_IRQHandler">MDF1_FLT2_IRQHandler</a>     ; 0x3418223A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler:</span>
-<span id="A3418223C">  0x3418223C:  </span>E7FE         B          <a href="#MDF1_FLT3_IRQHandler">MDF1_FLT3_IRQHandler</a>     ; 0x3418223C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler:</span>
-<span id="A3418223E">  0x3418223E:  </span>E7FE         B          <a href="#MDF1_FLT4_IRQHandler">MDF1_FLT4_IRQHandler</a>     ; 0x3418223E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler:</span>
-<span id="A34182240">  0x34182240:  </span>E7FE         B          <a href="#MDF1_FLT5_IRQHandler">MDF1_FLT5_IRQHandler</a>     ; 0x34182240
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SAI1_A_IRQHandler">SAI1_A_IRQHandler:</span>
-<span id="A34182242">  0x34182242:  </span>E7FE         B          <a href="#SAI1_A_IRQHandler">SAI1_A_IRQHandler</a>        ; 0x34182242
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SAI1_B_IRQHandler">SAI1_B_IRQHandler:</span>
-<span id="A34182244">  0x34182244:  </span>E7FE         B          <a href="#SAI1_B_IRQHandler">SAI1_B_IRQHandler</a>        ; 0x34182244
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SAI2_A_IRQHandler">SAI2_A_IRQHandler:</span>
-<span id="A34182246">  0x34182246:  </span>E7FE         B          <a href="#SAI2_A_IRQHandler">SAI2_A_IRQHandler</a>        ; 0x34182246
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SAI2_B_IRQHandler">SAI2_B_IRQHandler:</span>
-<span id="A34182248">  0x34182248:  </span>E7FE         B          <a href="#SAI2_B_IRQHandler">SAI2_B_IRQHandler</a>        ; 0x34182248
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPDIFRX_IRQHandler">SPDIFRX_IRQHandler:</span>
-<span id="A3418224A">  0x3418224A:  </span>E7FE         B          <a href="#SPDIFRX_IRQHandler">SPDIFRX_IRQHandler</a>       ; 0x3418224A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI1_IRQHandler">SPI1_IRQHandler:</span>
-<span id="A3418224C">  0x3418224C:  </span>E7FE         B          <a href="#SPI1_IRQHandler">SPI1_IRQHandler</a>          ; 0x3418224C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI2_IRQHandler">SPI2_IRQHandler:</span>
-<span id="A3418224E">  0x3418224E:  </span>E7FE         B          <a href="#SPI2_IRQHandler">SPI2_IRQHandler</a>          ; 0x3418224E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI3_IRQHandler">SPI3_IRQHandler:</span>
-<span id="A34182250">  0x34182250:  </span>E7FE         B          <a href="#SPI3_IRQHandler">SPI3_IRQHandler</a>          ; 0x34182250
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI4_IRQHandler">SPI4_IRQHandler:</span>
-<span id="A34182252">  0x34182252:  </span>E7FE         B          <a href="#SPI4_IRQHandler">SPI4_IRQHandler</a>          ; 0x34182252
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI5_IRQHandler">SPI5_IRQHandler:</span>
-<span id="A34182254">  0x34182254:  </span>E7FE         B          <a href="#SPI5_IRQHandler">SPI5_IRQHandler</a>          ; 0x34182254
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SPI6_IRQHandler">SPI6_IRQHandler:</span>
-<span id="A34182256">  0x34182256:  </span>E7FE         B          <a href="#SPI6_IRQHandler">SPI6_IRQHandler</a>          ; 0x34182256
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USART1_IRQHandler">USART1_IRQHandler:</span>
-<span id="A34182258">  0x34182258:  </span>E7FE         B          <a href="#USART1_IRQHandler">USART1_IRQHandler</a>        ; 0x34182258
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USART2_IRQHandler">USART2_IRQHandler:</span>
-<span id="A3418225A">  0x3418225A:  </span>E7FE         B          <a href="#USART2_IRQHandler">USART2_IRQHandler</a>        ; 0x3418225A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USART3_IRQHandler">USART3_IRQHandler:</span>
-<span id="A3418225C">  0x3418225C:  </span>E7FE         B          <a href="#USART3_IRQHandler">USART3_IRQHandler</a>        ; 0x3418225C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UART4_IRQHandler">UART4_IRQHandler:</span>
-<span id="A3418225E">  0x3418225E:  </span>E7FE         B          <a href="#UART4_IRQHandler">UART4_IRQHandler</a>         ; 0x3418225E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UART5_IRQHandler">UART5_IRQHandler:</span>
-<span id="A34182260">  0x34182260:  </span>E7FE         B          <a href="#UART5_IRQHandler">UART5_IRQHandler</a>         ; 0x34182260
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USART6_IRQHandler">USART6_IRQHandler:</span>
-<span id="A34182262">  0x34182262:  </span>E7FE         B          <a href="#USART6_IRQHandler">USART6_IRQHandler</a>        ; 0x34182262
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UART7_IRQHandler">UART7_IRQHandler:</span>
-<span id="A34182264">  0x34182264:  </span>E7FE         B          <a href="#UART7_IRQHandler">UART7_IRQHandler</a>         ; 0x34182264
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UART8_IRQHandler">UART8_IRQHandler:</span>
-<span id="A34182266">  0x34182266:  </span>E7FE         B          <a href="#UART8_IRQHandler">UART8_IRQHandler</a>         ; 0x34182266
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UART9_IRQHandler">UART9_IRQHandler:</span>
-<span id="A34182268">  0x34182268:  </span>E7FE         B          <a href="#UART9_IRQHandler">UART9_IRQHandler</a>         ; 0x34182268
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USART10_IRQHandler">USART10_IRQHandler:</span>
-<span id="A3418226A">  0x3418226A:  </span>E7FE         B          <a href="#USART10_IRQHandler">USART10_IRQHandler</a>       ; 0x3418226A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LPUART1_IRQHandler">LPUART1_IRQHandler:</span>
-<span id="A3418226C">  0x3418226C:  </span>E7FE         B          <a href="#LPUART1_IRQHandler">LPUART1_IRQHandler</a>       ; 0x3418226C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="XSPI1_IRQHandler">XSPI1_IRQHandler:</span>
-<span id="A3418226E">  0x3418226E:  </span>E7FE         B          <a href="#XSPI1_IRQHandler">XSPI1_IRQHandler</a>         ; 0x3418226E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="XSPI2_IRQHandler">XSPI2_IRQHandler:</span>
-<span id="A34182270">  0x34182270:  </span>E7FE         B          <a href="#XSPI2_IRQHandler">XSPI2_IRQHandler</a>         ; 0x34182270
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="XSPI3_IRQHandler">XSPI3_IRQHandler:</span>
-<span id="A34182272">  0x34182272:  </span>E7FE         B          <a href="#XSPI3_IRQHandler">XSPI3_IRQHandler</a>         ; 0x34182272
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FMC_IRQHandler">FMC_IRQHandler:</span>
-<span id="A34182274">  0x34182274:  </span>E7FE         B          <a href="#FMC_IRQHandler">FMC_IRQHandler</a>           ; 0x34182274
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SDMMC1_IRQHandler">SDMMC1_IRQHandler:</span>
-<span id="A34182276">  0x34182276:  </span>E7FE         B          <a href="#SDMMC1_IRQHandler">SDMMC1_IRQHandler</a>        ; 0x34182276
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="SDMMC2_IRQHandler">SDMMC2_IRQHandler:</span>
-<span id="A34182278">  0x34182278:  </span>E7FE         B          <a href="#SDMMC2_IRQHandler">SDMMC2_IRQHandler</a>        ; 0x34182278
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="UCPD1_IRQHandler">UCPD1_IRQHandler:</span>
-<span id="A3418227A">  0x3418227A:  </span>E7FE         B          <a href="#UCPD1_IRQHandler">UCPD1_IRQHandler</a>         ; 0x3418227A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler:</span>
-<span id="A3418227C">  0x3418227C:  </span>E7FE         B          <a href="#USB1_OTG_HS_IRQHandler">USB1_OTG_HS_IRQHandler</a>   ; 0x3418227C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler:</span>
-<span id="A3418227E">  0x3418227E:  </span>E7FE         B          <a href="#USB2_OTG_HS_IRQHandler">USB2_OTG_HS_IRQHandler</a>   ; 0x3418227E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="ETH1_IRQHandler">ETH1_IRQHandler:</span>
-<span id="A34182280">  0x34182280:  </span>E7FE         B          <a href="#ETH1_IRQHandler">ETH1_IRQHandler</a>          ; 0x34182280
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler:</span>
-<span id="A34182282">  0x34182282:  </span>E7FE         B          <a href="#FDCAN1_IT0_IRQHandler">FDCAN1_IT0_IRQHandler</a>    ; 0x34182282
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler:</span>
-<span id="A34182284">  0x34182284:  </span>E7FE         B          <a href="#FDCAN1_IT1_IRQHandler">FDCAN1_IT1_IRQHandler</a>    ; 0x34182284
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler:</span>
-<span id="A34182286">  0x34182286:  </span>E7FE         B          <a href="#FDCAN2_IT0_IRQHandler">FDCAN2_IT0_IRQHandler</a>    ; 0x34182286
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler:</span>
-<span id="A34182288">  0x34182288:  </span>E7FE         B          <a href="#FDCAN2_IT1_IRQHandler">FDCAN2_IT1_IRQHandler</a>    ; 0x34182288
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler:</span>
-<span id="A3418228A">  0x3418228A:  </span>E7FE         B          <a href="#FDCAN3_IT0_IRQHandler">FDCAN3_IT0_IRQHandler</a>    ; 0x3418228A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler:</span>
-<span id="A3418228C">  0x3418228C:  </span>E7FE         B          <a href="#FDCAN3_IT1_IRQHandler">FDCAN3_IT1_IRQHandler</a>    ; 0x3418228C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler:</span>
-<span id="A3418228E">  0x3418228E:  </span>E7FE         B          <a href="#FDCAN_CU_IRQHandler">FDCAN_CU_IRQHandler</a>      ; 0x3418228E
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="MDIOS_IRQHandler">MDIOS_IRQHandler:</span>
-<span id="A34182290">  0x34182290:  </span>E7FE         B          <a href="#MDIOS_IRQHandler">MDIOS_IRQHandler</a>         ; 0x34182290
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler:</span>
-<span id="A34182292">  0x34182292:  </span>E7FE         B          <a href="#DCMI_PSSI_IRQHandler">DCMI_PSSI_IRQHandler</a>     ; 0x34182292
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler:</span>
-<span id="A34182294">  0x34182294:  </span>E7FE         B          <a href="#WAKEUP_PIN_IRQHandler">WAKEUP_PIN_IRQHandler</a>    ; 0x34182294
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CTI_INT0_IRQHandler">CTI_INT0_IRQHandler:</span>
-<span id="A34182296">  0x34182296:  </span>E7FE         B          <a href="#CTI_INT0_IRQHandler">CTI_INT0_IRQHandler</a>      ; 0x34182296
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="CTI_INT1_IRQHandler">CTI_INT1_IRQHandler:</span>
-<span id="A34182298">  0x34182298:  </span>E7FE         B          <a href="#CTI_INT1_IRQHandler">CTI_INT1_IRQHandler</a>      ; 0x34182298
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LTDC_UP_IRQHandler">LTDC_UP_IRQHandler:</span>
-<span id="A3418229A">  0x3418229A:  </span>E7FE         B          <a href="#LTDC_UP_IRQHandler">LTDC_UP_IRQHandler</a>       ; 0x3418229A
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2">Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2</h2>
-
-<pre>
-<br/><span id="LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler:</span>
-<span id="A3418229C">  0x3418229C:  </span>E7FE         B          <a href="#LTDC_UP_ERR_IRQHandler">LTDC_UP_ERR_IRQHandler</a>   ; 0x3418229C
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .init_array from STM32N6xx_Startup.o, size=4, align=4">Section .init_array from STM32N6xx_Startup.o, size=4, align=4</h2>
-
-<pre>
-<span id="A341822A0">  0x341822A0:  </span>34180BFD     DC.W       <a href="#SystemCoreClockUpdate">SystemCoreClockUpdate</a>
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4">Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4</h2>
-
-<pre>
-<br/><span id="uwTick">uwTick:</span>
-<span id="A341822A4">  0x341822A4:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822A5">  0x341822A5:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822A6">  0x341822A6:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822A7">  0x341822A7:  </span>00           DC.B       0x00                     ; '\0'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4">Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4</h2>
-
-<pre>
-<br/><span id="uwTickPrio">uwTickPrio:</span>
-<span id="A341822A8">  0x341822A8:  </span>03           DC.B       0x03                     ; '\x03'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4">Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4</h2>
-
-<pre>
-<br/><span id="SystemCoreClock">SystemCoreClock:</span>
-<span id="A341822AC">  0x341822AC:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822AD">  0x341822AD:  </span>90           DC.B       0x90                     ; '\x90'
-<span id="A341822AE">  0x341822AE:  </span>D0           DC.B       0xD0                     ; '\xD0'
-<span id="A341822AF">  0x341822AF:  </span>03           DC.B       0x03                     ; '\x03'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4">Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4</h2>
-
-<pre>
-<br/><span id="__SEGGER_init_ctors">__SEGGER_init_ctors:</span>
-<span id="A341822B0">  0x341822B0:  </span>B500         PUSH       123LR}
-<span id="A341822B2">  0x341822B2:  </span>4806         LDR        R0, =0x341822A0          ; [PC, #24] [0x341822CC] 
-<span id="A341822B4">  0x341822B4:  </span>4906         LDR        R1, =uwTick              ; [PC, #24] [0x341822D0] =0x341822A4 
-<br/>.L1:
-<span id="A341822B6">  0x341822B6:  </span>4288         CMP        R0, R1
-<span id="A341822B8">  0x341822B8:  </span>D005         BEQ        46L2                      ; 0x341822C6
-<span id="A341822BA">  0x341822BA:  </span>6802         LDR        R2, [R0]
-<span id="A341822BC">  0x341822BC:  </span>3004         ADDS       R0, #4
-<span id="A341822BE">  0x341822BE:  </span>B403         PUSH       123R0-R1}
-<span id="A341822C0">  0x341822C0:  </span>4790         BLX        R2
-<span id="A341822C2">  0x341822C2:  </span>BC03         POP        123R0-R1}
-<span id="A341822C4">  0x341822C4:  </span>E7F7         B          46L1                      ; 0x341822B6
-<br/>.L2:
-<span id="A341822C6">  0x341822C6:  </span>BC08         POP        123R3}
-<span id="A341822C8">  0x341822C8:  </span>4718         BX         R3
-<span id="A341822CA">  0x341822CA:  </span>0000         NOP
-<span id="A341822CC">  0x341822CC:  </span>341822A0     DC.W       341822A0               ; R_ARM_ABS32
-<span id="A341822D0">  0x341822D0:  </span>341822A4     DC.W       <a href="#uwTick">uwTick</a>
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .segger.init.table from [ Linker created ], size=36, align=4">Section .segger.init.table from [ Linker created ], size=36, align=4</h2>
-
-<pre>
-<span id="A341822D4">  0x341822D4:  </span>341822FD     DC.W       <a href="#__SEGGER_init_zero">__SEGGER_init_zero</a>
-<span id="A341822D8">  0x341822D8:  </span>A4           DC.B       0xA4                     ; '\xA4'
-<span id="A341822D9">  0x341822D9:  </span>22           DC.B       0x22                     ; '\"'
-<span id="A341822DA">  0x341822DA:  </span>18           DC.B       0x18                     ; '\x18'
-<span id="A341822DB">  0x341822DB:  </span>34           DC.B       0x34                     ; '4'
-<span id="A341822DC">  0x341822DC:  </span>05           DC.B       0x05                     ; '\x05'
-<span id="A341822DD">  0x341822DD:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822DE">  0x341822DE:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822DF">  0x341822DF:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822E0">  0x341822E0:  </span>3418230F     DC.W       <a href="#__SEGGER_init_copy">__SEGGER_init_copy</a>
-<span id="A341822E4">  0x341822E4:  </span>AC           DC.B       0xAC                     ; '\xAC'
-<span id="A341822E5">  0x341822E5:  </span>22           DC.B       0x22                     ; '\"'
-<span id="A341822E6">  0x341822E6:  </span>18           DC.B       0x18                     ; '\x18'
-<span id="A341822E7">  0x341822E7:  </span>34           DC.B       0x34                     ; '4'
-<span id="A341822E8">  0x341822E8:  </span>341822F8     DC.W       341822F8               ; R_ARM_ABS32
-<span id="A341822EC">  0x341822EC:  </span>04           DC.B       0x04                     ; '\x04'
-<span id="A341822ED">  0x341822ED:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822EE">  0x341822EE:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822EF">  0x341822EF:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822F0">  0x341822F0:  </span>341822B1     DC.W       <a href="#__SEGGER_init_ctors">__SEGGER_init_ctors</a>
-<span id="A341822F4">  0x341822F4:  </span>341814B7     DC.W       <a href="#__SEGGER_init_done">__SEGGER_init_done</a>
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .segger.init.data from [ Linker created ], size=4, align=4">Section .segger.init.data from [ Linker created ], size=4, align=4</h2>
-
-<pre>
-<span id="A341822F8">  0x341822F8:  </span>00           DC.B       0x00                     ; '\0'
-<span id="A341822F9">  0x341822F9:  </span>90           DC.B       0x90                     ; '\x90'
-<span id="A341822FA">  0x341822FA:  </span>D0           DC.B       0xD0                     ; '\xD0'
-<span id="A341822FB">  0x341822FB:  </span>03           DC.B       0x03                     ; '\x03'
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2">Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2</h2>
-
-<pre>
-<br/><span id="__SEGGER_init_zero">__SEGGER_init_zero:</span>
-<span id="A341822FC">  0x341822FC:  </span>6820         LDR        R0, [R4]
-<span id="A341822FE">  0x341822FE:  </span>6861         LDR        R1, [R4, #4]
-<span id="A34182300">  0x34182300:  </span>3408         ADDS       R4, #8
-<span id="A34182302">  0x34182302:  </span>2200         MOVS       R2, #0
-<span id="A34182304">  0x34182304:  </span>E000         B          46L2                      ; 0x34182308
-<br/>.L1:
-<span id="A34182306">  0x34182306:  </span>5442         STRB       R2, [R0, R1]
-<br/>.L2:
-<span id="A34182308">  0x34182308:  </span>1E49         SUBS       R1, R1, #1
-<span id="A3418230A">  0x3418230A:  </span>D5FC         BPL        46L1                      ; 0x34182306
-<span id="A3418230C">  0x3418230C:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2">Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2</h2>
-
-<pre>
-<br/><span id="__SEGGER_init_copy">__SEGGER_init_copy:</span>
-<span id="A3418230E">  0x3418230E:  </span>6820         LDR        R0, [R4]
-<span id="A34182310">  0x34182310:  </span>6861         LDR        R1, [R4, #4]
-<span id="A34182312">  0x34182312:  </span>68A2         LDR        R2, [R4, #8]
-<span id="A34182314">  0x34182314:  </span>340C         ADDS       R4, #12
-<span id="A34182316">  0x34182316:  </span>E001         B          46L2                      ; 0x3418231C
-<br/>.L1:
-<span id="A34182318">  0x34182318:  </span>5C8B         LDRB       R3, [R1, R2]
-<span id="A3418231A">  0x3418231A:  </span>5483         STRB       R3, [R0, R2]
-<br/>.L2:
-<span id="A3418231C">  0x3418231C:  </span>1E52         SUBS       R2, R2, #1
-<span id="A3418231E">  0x3418231E:  </span>D5FB         BPL        46L1                      ; 0x34182318
-<span id="A34182320">  0x34182320:  </span>4770         BX         LR
-</pre>
-<h2 id="ABSOLUTE LISTING_Section .bss.block.stack from [ Linker created ], size=8192, align=8">Section .bss.block.stack from [ Linker created ], size=8192, align=8</h2>
-
-<pre>
-(341FE000-341FFFFF excluded)
-</pre>
-<h1 id="LINK SUMMARY">LINK SUMMARY</h1>
-<h2 id="LINK SUMMARY_Memory breakdown">Memory breakdown</h2>
-
-<pre>
-  7 836 bytes read-only  code    + 
-    116 bytes read-only  data    =   7 952 bytes read-only (total)
-  8 201 bytes read-write data
-</pre>
-<h2 id="LINK SUMMARY_Region summary">Region summary</h2>
-
-<table>
-  <tr>
-    <th align="left">Name</th>
-    <th align="left">Range</th>
-    <th align="right">Size</th>
-    <th align="right">Used</th>
-    <th align="right">Unused</th>
-    <th align="right">Alignment Loss</th>
-  </tr>
-  <tr>
-    <td align="left"><code>AXI_RAM2</code></td>
-    <td align="left"><code>34180400-341FFFFF</code></td>
-    <td align="right"><code>523 264</code></td>
-    <td align="right"><code>16 157   3.09</code></td>
-    <td align="right"><code>507 104  96.91</code></td>
-    <td align="right"><code>3   0.00</code></td>
-  </tr>
-</table>
-<h2 id="LINK SUMMARY_Diagnostic summary">Diagnostic summary</h2>
-
-<pre>
-Link complete: 0 errors.
-</pre>
-</body></html>
Index: trunk/firmware/FSBL/SES/blto2_FSBL.emProject
===================================================================
--- trunk/firmware/FSBL/SES/blto2_FSBL.emProject	(revision 21)
+++ trunk/firmware/FSBL/SES/blto2_FSBL.emProject	(revision 22)
@@ -81,10 +81,4 @@
       gcc_optimization_level="Level 2 for speed"
       post_build_command="&quot;C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_SigningTool_CLI.exe&quot; -s -bin &quot;$(ProjectDir)/$(OutDir)/$(ProjectName).bin&quot; -nk -of 0x80000000 -t fsbl -o &quot;$(ProjectDir)/$(OutDir)/$(ProjectName)_Trusted.bin&quot; -hv 2.3 -dump &quot;$(ProjectDir)/$(OutDir)/$(ProjectName)_Trusted.bin&quot; -align" />
-    <folder
-      Name="CMSIS"
-      exclude=""
-      filter="*.c;*.h"
-      path="../CubeMX/Drivers/CMSIS"
-      recurse="Yes" />
     <folder Name="Script Files">
       <file file_name="STM32N6xx/Scripts/STM32N6xx_Target.js">
